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([191.17.222.139]) by smtp.gmail.com with ESMTPSA id l39-20020a05687106a700b0014fb4bdc746sm11354475oao.8.2023.01.02.03.52.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 03:52:46 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng Subject: [PATCH v5 00/11] riscv: OpenSBI boot test and cleanups Date: Mon, 2 Jan 2023 08:52:30 -0300 Message-Id: <20230102115241.25733-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::30; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Jan 2023 11:52:50 -0000 Hi, This new version is still rebased on top of [1]: "[PATCH v2 00/12] hw/riscv: Improve Spike HTIF emulation fidelity" from Bin Meng. The change from v4 is on patch 9 where we added an extra flag in riscv_load_kernel() to allow for boards that don't load initrd (e.g. opentitan and sifive_e) to opt out from loading it altogether. * Patch without reviews: 9 Changes from v4: - patch 9: - added a 'load_init' flag in riscv_load_kernel() to control whether the function should execute riscv_load_initrd() or not v4 link: https://lists.gnu.org/archive/html/qemu-devel/2022-12/msg04652.html Changes from v3: - patch 1: - fixed more instances of 'opensbi' and 'Opensbi' to 'OpenSBI' - changed tests order - patch 4 (new): - added a g_assert(filename) guard in riscv_load_initrd() and riscv_load_kernel() v3 link: https://mail.gnu.org/archive/html/qemu-devel/2022-12/msg04491.html Changes from v2: - patch 1: - reduced code repetition with a boot_opensbi() helper - renamed 'opensbi' to 'OpenSBI' in the file header - patch 9: - renamed riscv_load_kernel() to riscv_load_kernel_and_initrd() v2 link: https://mail.gnu.org/archive/html/qemu-devel/2022-12/msg04466.html Changes from v1: - patches were rebased with [1] - patches 13-15: removed * will be re-sent in a follow-up series - patches 4-5: removed since they're picked by Bin in [1] - patch 1: - added a 'skip' riscv32 spike test v1 link: https://mail.gnu.org/archive/html/qemu-devel/2022-12/msg03860.html Based-on: <20221227064812.1903326-1-bmeng@tinylab.org> Cc: Alistair Francis Cc: Bin Meng [1] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334352 Daniel Henrique Barboza (11): tests/avocado: add RISC-V OpenSBI boot test hw/riscv/spike: use 'fdt' from MachineState hw/riscv/sifive_u: use 'fdt' from MachineState hw/riscv/boot.c: exit early if filename is NULL in load functions hw/riscv/spike.c: load initrd right after riscv_load_kernel() hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() hw/riscv/boot.c: use MachineState in riscv_load_initrd() hw/riscv/boot.c: use MachineState in riscv_load_kernel() hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() hw/riscv/boot.c: make riscv_load_initrd() static hw/riscv/boot.c | 91 +++++++++++++++++++++++----------- hw/riscv/microchip_pfsoc.c | 20 +------- hw/riscv/opentitan.c | 3 +- hw/riscv/sifive_e.c | 4 +- hw/riscv/sifive_u.c | 32 +++--------- hw/riscv/spike.c | 37 ++++---------- hw/riscv/virt.c | 21 +------- include/hw/riscv/boot.h | 5 +- include/hw/riscv/sifive_u.h | 3 -- include/hw/riscv/spike.h | 2 - tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++ 11 files changed, 150 insertions(+), 133 deletions(-) create mode 100644 tests/avocado/riscv_opensbi.py -- 2.39.0 From MAILER-DAEMON Mon Jan 02 06:52:53 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pCJN7-0007AL-Ea for mharc-qemu-riscv@gnu.org; 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([191.17.222.139]) by smtp.gmail.com with ESMTPSA id l39-20020a05687106a700b0014fb4bdc746sm11354475oao.8.2023.01.02.03.52.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 03:52:49 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Cleber Rosa , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v5 01/11] tests/avocado: add RISC-V OpenSBI boot test Date: Mon, 2 Jan 2023 08:52:31 -0300 Message-Id: <20230102115241.25733-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230102115241.25733-1-dbarboza@ventanamicro.com> References: <20230102115241.25733-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::2c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Jan 2023 11:52:52 -0000 This test is used to do a quick sanity check to ensure that we're able to run the existing QEMU FW image. 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | RISCV32_BIOS_BIN firmware with minimal options. The riscv32 'spike' machine isn't bootable at this moment, requiring an OpenSBI fix [1] and QEMU side changes [2]. We could just leave at that or add a 'skip' test to remind us about it. To work as a reminder that we have a riscv32 'spike' test that should be enabled as soon as OpenSBI QEMU rom receives the fix, we're adding a 'skip' test: (06/18) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv32_spike: SKIP: requires OpenSBI fix to work [1] https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.1860569-1-bmeng@tinylab.org/ [2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159 Cc: Cleber Rosa Cc: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Daniel Henrique Barboza --- tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 tests/avocado/riscv_opensbi.py diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py new file mode 100644 index 0000000000..e02f0d404a --- /dev/null +++ b/tests/avocado/riscv_opensbi.py @@ -0,0 +1,65 @@ +# OpenSBI boot test for RISC-V machines +# +# Copyright (c) 2022, Ventana Micro +# +# This work is licensed under the terms of the GNU GPL, version 2 or +# later. See the COPYING file in the top-level directory. + +from avocado_qemu import QemuSystemTest +from avocado import skip +from avocado_qemu import wait_for_console_pattern + +class RiscvOpenSBI(QemuSystemTest): + """ + :avocado: tags=accel:tcg + """ + timeout = 5 + + def boot_opensbi(self): + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG') + + @skip("requires OpenSBI fix to work") + def test_riscv32_spike(self): + """ + :avocado: tags=arch:riscv32 + :avocado: tags=machine:spike + """ + self.boot_opensbi() + + def test_riscv64_spike(self): + """ + :avocado: tags=arch:riscv64 + :avocado: tags=machine:spike + """ + self.boot_opensbi() + + def test_riscv32_sifive_u(self): + """ + :avocado: tags=arch:riscv32 + :avocado: tags=machine:sifive_u + """ + self.boot_opensbi() + + def test_riscv64_sifive_u(self): + """ + :avocado: tags=arch:riscv64 + :avocado: tags=machine:sifive_u + """ + self.boot_opensbi() + + def test_riscv32_virt(self): + """ + :avocado: tags=arch:riscv32 + :avocado: tags=machine:virt + """ + self.boot_opensbi() + + def test_riscv64_virt(self): + """ + :avocado: tags=arch:riscv64 + :avocado: tags=machine:virt + """ + self.boot_opensbi() -- 2.39.0 From MAILER-DAEMON Mon Jan 02 06:52:56 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pCJNA-0007Dj-2J for mharc-qemu-riscv@gnu.org; Mon, 02 Jan 2023 06:52:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pCJN8-0007Av-Hu for qemu-riscv@nongnu.org; Mon, 02 Jan 2023 06:52:54 -0500 Received: from mail-oa1-x2c.google.com ([2001:4860:4864:20::2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pCJN7-0002uA-1W for qemu-riscv@nongnu.org; Mon, 02 Jan 2023 06:52:54 -0500 Received: by mail-oa1-x2c.google.com with SMTP id 586e51a60fabf-12c8312131fso33457460fac.4 for ; Mon, 02 Jan 2023 03:52:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8tYhCgeu+CUPdU0tlNGR+x3OI3mYmG0ZDZI1kUqM/1s=; b=UdT6ilTSt972XE81gYaspt6L9Aw4du3Wot7oNrmNBiPh2CRo+Lb49xTG/jKAYT0i+o aONB4VNBwRd8NtSPswjQ0tCcbNZ1x4R+nJIBH0j5ZerV5LaSL9nr5QM4FGvCDo6+XcWj /gBWGL2lYuiLR3t3RMVuUTHxcdnIRucJUedPaW54XOsi/kEu12rQ0/SA3upz4D+sMjKF b2+txD923m+ryFDauxHm2Dfc4ZBxq3gh1HoBflCl/RdSk8veSB0roiIH4F+vd9rqs453 408w1fziScmJclRi7QxXAEDxsq9RG0WvVMs+9IXp9iTVlbGr2p8BY1Wo17dYGB9RYETl 5wwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8tYhCgeu+CUPdU0tlNGR+x3OI3mYmG0ZDZI1kUqM/1s=; b=N61caA5MxqYU/0S1Ek2/zkHxb58YcbUZFZW6fl1uFox1q5vXHoyopqs67105azorQw mAbMKqgKS4vefW82GlRbPKps1l3lftHyHe8E0Si5DrN7AI31OdcLic0STxKr0/7kSVga Um25gqZK7Sce9s942MHeW4WaR2wqGfNKkfMtLFJ2pDKPWk0m9UDMMKwjfgcyvwPPfu8W mE/tqe6tHctzHTYRXqVHzoFcwFZlABUgRwkieAUCp7XrmLRFBMrAm3sYSc4IyivfrTZn uhgWxYN2xnxx6pvDa5PYkJUuwMPRiVxnoqJO3jcQbERe4uht9HC3+6zYIdrVrgH24xPj WwNg== X-Gm-Message-State: AFqh2kqj/4/9NqUDFQndTwkJaqabxG7PzI8syh1IDaQ2n+JUUx8eZAYz VzueAYainNeiCZbASP6i8WEgIA== X-Google-Smtp-Source: AMrXdXu7jwkKbzqaZ4NJ7RMjItpnBS69O3IKBMEGkTuNUe5iggof9qujNOzW9MxAgasW5UT5rbhH7Q== X-Received: by 2002:a05:6870:b6a7:b0:144:7395:2140 with SMTP id cy39-20020a056870b6a700b0014473952140mr22269021oab.35.1672660372462; Mon, 02 Jan 2023 03:52:52 -0800 (PST) Received: from grind.. ([191.17.222.139]) by smtp.gmail.com with ESMTPSA id l39-20020a05687106a700b0014fb4bdc746sm11354475oao.8.2023.01.02.03.52.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 03:52:52 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v5 02/11] hw/riscv/spike: use 'fdt' from MachineState Date: Mon, 2 Jan 2023 08:52:32 -0300 Message-Id: <20230102115241.25733-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230102115241.25733-1-dbarboza@ventanamicro.com> References: <20230102115241.25733-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::2c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Jan 2023 11:52:54 -0000 The MachineState object provides a 'fdt' pointer that is already being used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP command. Remove the 'fdt' pointer from SpikeState and use MachineState::fdt instead. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/spike.c | 12 +++++------- include/hw/riscv/spike.h | 2 -- 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 1679c325d5..25c5420ee6 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -53,6 +53,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, bool is_32_bit, bool htif_custom_base) { void *fdt; + int fdt_size; uint64_t addr, size; unsigned long clint_addr; int cpu, socket; @@ -65,7 +66,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, "sifive,clint0", "riscv,clint0" }; - fdt = s->fdt = create_device_tree(&s->fdt_size); + fdt = mc->fdt = create_device_tree(&fdt_size); if (!fdt) { error_report("create_device_tree() failed"); exit(1); @@ -327,18 +328,15 @@ static void spike_board_init(MachineState *machine) hwaddr end = riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, &start); - qemu_fdt_setprop_cell(s->fdt, "/chosen", + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", end); } /* Compute the fdt load address in dram */ fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, - machine->ram_size, s->fdt); - - /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ - machine->fdt = s->fdt; + machine->ram_size, machine->fdt); /* load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index 73d69234de..d13a147942 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -37,8 +37,6 @@ struct SpikeState { /*< public >*/ RISCVHartArrayState soc[SPIKE_SOCKETS_MAX]; - void *fdt; - int fdt_size; }; enum { -- 2.39.0 From MAILER-DAEMON Mon Jan 02 06:53:00 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pCJNE-0007F3-EO for mharc-qemu-riscv@gnu.org; Mon, 02 Jan 2023 06:53:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pCJNC-0007ES-4m for qemu-riscv@nongnu.org; Mon, 02 Jan 2023 06:52:58 -0500 Received: from mail-oa1-x34.google.com ([2001:4860:4864:20::34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pCJNA-0002us-H5 for qemu-riscv@nongnu.org; Mon, 02 Jan 2023 06:52:57 -0500 Received: by mail-oa1-x34.google.com with SMTP id 586e51a60fabf-14ffd3c5b15so21907706fac.3 for ; Mon, 02 Jan 2023 03:52:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IU6x7WVTw6l9F2GnZ9QyTDYaXQmzpFAwXIcNmwcVoDs=; b=KcGxxWGt0kgajXe04hoEALoyXpUhf1zbWurOwPWAu561KUEuA3I5BoUGoLT9pxR5K2 SLo4wSYqyAOMU16zB0gSnE6lze0o2QZW48nhSjj9BPn2TcNnJlzftWnZfYDzN2kb5Ca2 dp4Y9CNnmezs7DcmDnNBZEWIos4nD6lCwFDVoeP9iYp1EaaoqA4h3Zgikw/0nQz2J7Ad JlgBMemK0azbsVqw0U/5jAZhGdVo9PQEqAOV74ZOxn91xnuoSdstPw9xZoOHSDo4lndS 0PHXFGktLxm6oHP89w493tKSPfjYbMOKa81ai7xfKXXxftpHFfnx3sDfYQQdwesWY2pr Si2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IU6x7WVTw6l9F2GnZ9QyTDYaXQmzpFAwXIcNmwcVoDs=; b=2ATeii6kJDaVrCNJTGJmYdKE3a3fRgmuFBZzS0msbRbV3OKxxhywcPnfezUrEouSHl GBeJZEymy2ohTshpHKu0+DAr2I+ZY5el7/VK8jQWD3bhCaUMfb/4sdm3wbAWw4IO+gjP Yb9gfxCSu5ai6Alqb9ARnKLfw3x9N3pPcVcMUvDVOok2K1bOWZWlGK9sgvEHDxAvoFk9 bmAvkH81N5fSEzWEhxpq66PqN3VI+efi9aZJ/Qd01kSNFN7+Vk4Y77icLCEU1zdZ5M4X Ky4V5YUUXVejhj98F0zVdK7YehVnsOxwSM3u9w8MT1Xvt8uvZvLLacX8PZJysYEAcjvq B1vA== X-Gm-Message-State: AFqh2kpToLh/mmBveezk1oZuTkIL7gZr9pvS5DqR8inzYJyrhmDcxvNi 7a3NF4trG7alY2ffWi9Znw00mw== X-Google-Smtp-Source: AMrXdXvJPOxxMD2bh6SWO6mwoBQnqxpRYNL9EVZ1Vkh5hqDQSn5f5T1ekXrdJ+EYvrT6p/PqBP3w5Q== X-Received: by 2002:a05:6870:7e02:b0:14f:eee9:d20a with SMTP id wx2-20020a0568707e0200b0014feee9d20amr11072926oab.11.1672660375265; Mon, 02 Jan 2023 03:52:55 -0800 (PST) Received: from grind.. ([191.17.222.139]) by smtp.gmail.com with ESMTPSA id l39-20020a05687106a700b0014fb4bdc746sm11354475oao.8.2023.01.02.03.52.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 03:52:54 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v5 03/11] hw/riscv/sifive_u: use 'fdt' from MachineState Date: Mon, 2 Jan 2023 08:52:33 -0300 Message-Id: <20230102115241.25733-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230102115241.25733-1-dbarboza@ventanamicro.com> References: <20230102115241.25733-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::34; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Jan 2023 11:52:58 -0000 The MachineState object provides a 'fdt' pointer that is already being used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP command. Remove the 'fdt' pointer from SiFiveUState and use MachineState::fdt instead. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/sifive_u.c | 15 ++++++--------- include/hw/riscv/sifive_u.h | 3 --- 2 files changed, 6 insertions(+), 12 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index a58ddb36ac..ddceb750ea 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -98,7 +98,7 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, { MachineState *ms = MACHINE(qdev_get_machine()); void *fdt; - int cpu; + int cpu, fdt_size; uint32_t *cells; char *nodename; uint32_t plic_phandle, prci_phandle, gpio_phandle, phandle = 1; @@ -112,14 +112,14 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, }; if (ms->dtb) { - fdt = s->fdt = load_device_tree(ms->dtb, &s->fdt_size); + fdt = ms->fdt = load_device_tree(ms->dtb, &fdt_size); if (!fdt) { error_report("load_device_tree() failed"); exit(1); } goto update_bootargs; } else { - fdt = s->fdt = create_device_tree(&s->fdt_size); + fdt = ms->fdt = create_device_tree(&fdt_size); if (!fdt) { error_report("create_device_tree() failed"); exit(1); @@ -612,9 +612,9 @@ static void sifive_u_machine_init(MachineState *machine) hwaddr end = riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, &start); - qemu_fdt_setprop_cell(s->fdt, "/chosen", + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", end); } } else { @@ -627,14 +627,11 @@ static void sifive_u_machine_init(MachineState *machine) /* Compute the fdt load address in dram */ fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, - machine->ram_size, s->fdt); + machine->ram_size, machine->fdt); if (!riscv_is_32bit(&s->soc.u_cpus)) { start_addr_hi32 = (uint64_t)start_addr >> 32; } - /* Set machine->fdt for 'dumpdtb' QMP/HMP command */ - machine->fdt = s->fdt; - /* reset vector */ uint32_t reset_vec[12] = { s->msel, /* MSEL pin state */ diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index e680d61ece..4a8828a30e 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -67,9 +67,6 @@ typedef struct SiFiveUState { /*< public >*/ SiFiveUSoCState soc; - void *fdt; - int fdt_size; - bool start_in_flash; uint32_t msel; uint32_t serial; -- 2.39.0 From MAILER-DAEMON Mon Jan 02 06:53:01 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pCJNF-0007Fo-Oa for mharc-qemu-riscv@gnu.org; Mon, 02 Jan 2023 06:53:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pCJNE-0007F7-Hy for qemu-riscv@nongnu.org; Mon, 02 Jan 2023 06:53:00 -0500 Received: from mail-oa1-x31.google.com ([2001:4860:4864:20::31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pCJND-0002vS-21 for qemu-riscv@nongnu.org; Mon, 02 Jan 2023 06:53:00 -0500 Received: by mail-oa1-x31.google.com with SMTP id 586e51a60fabf-14455716674so33429885fac.7 for ; Mon, 02 Jan 2023 03:52:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=P3cARjG1/wwT2hePMTnt8/W2vA3rPNVOtanqBwKMrFs=; b=pmfbqOZC6/jh2dRtZBXFkSR18HYOOBZAjCGIvUJSf/dGllvN8IAnchSYgZ2jtIq88W g6vQ0i38y02NAbl8KjZG2KD1u1hWxUtfG182aHkWnSLCLk7gx4rG3x8yi9XpoR9ZJG0r d17gablDCW9n0l+VETE1sGAJD15FixW1OvYnE5W7oMcPnmuZ+VOFJEoJoGMlgIwZR8g9 NnwYNTc6PaWGPbElRkl1isq8mcVKe4gYUysBLgtrYmfgBCsBCAiYkaXLDqDIPCvguCVa OAG8QZAKsE4KU9ZV3HEV+YBpxxMgyBNPQS+S66TM9mFGw7HWThS1VUSYIjJ8Xq1g+LIm dZNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=P3cARjG1/wwT2hePMTnt8/W2vA3rPNVOtanqBwKMrFs=; b=K4+ual9z7xgT/yKOGgd7eStDhdG6yiUMK9hRnf10t6eV03OOdC1IwxpqYucij9Snoj OIMLLU5otRQzsojvj+2QJIXpbqQllT4CCXut6Uyl78GDhpmhE6S6/0cyNmJZnyiAtw4N mmqNc8fkTOJ14DRY3mCRE/3Mq8LhQ+pIs67dUqvcaUgXpojABP6qiJC/YQ7+FLatEm3K 7A7p7SN+hvNPE+2zqTDYST7/0wBttvMCk9geHpALMdpXhzZp2b+1qC8cu14jRX9cGhxg D2jD8H8zW+cpeRlu8UE4ZjvTzh5QFHzkUztJovhFvEuDChUeJ7rzpy753JfPXl0E3YHT LnBw== X-Gm-Message-State: AFqh2kqhPcC3vjWZNrsvPN2AgPGmHgcR7unnehOb0m4wvLensTgPncSx qE6ZpyZrlBL8RksiGJo4VEX8fQ== X-Google-Smtp-Source: AMrXdXvzyxsNdC8fIt03RXPijjHzHCjxQACNpy8BM7CSCL9Rd6UcCzV14qqoZZ8Bcnw4hjyIjxI/3Q== X-Received: by 2002:a05:6870:578f:b0:14f:b93f:941a with SMTP id i15-20020a056870578f00b0014fb93f941amr12576540oap.50.1672660378072; Mon, 02 Jan 2023 03:52:58 -0800 (PST) Received: from grind.. ([191.17.222.139]) by smtp.gmail.com with ESMTPSA id l39-20020a05687106a700b0014fb4bdc746sm11354475oao.8.2023.01.02.03.52.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 03:52:57 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 04/11] hw/riscv/boot.c: exit early if filename is NULL in load functions Date: Mon, 2 Jan 2023 08:52:34 -0300 Message-Id: <20230102115241.25733-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230102115241.25733-1-dbarboza@ventanamicro.com> References: <20230102115241.25733-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Jan 2023 11:53:00 -0000 riscv_load_firmware(), riscv_load_initrd() and riscv_load_kernel() works under the assumption that a 'filename' parameter is always not NULL. This is currently the case since all callers of these functions are checking for NULL before calling them. Add an g_assert() to make sure that a NULL value in these cases are to be considered a bug. Suggested-by: Alex Bennée Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 98b80af51b..31aa3385a0 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -153,6 +153,8 @@ target_ulong riscv_load_firmware(const char *firmware_filename, uint64_t firmware_entry, firmware_end; ssize_t firmware_size; + g_assert(firmware_filename != NULL); + if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, &firmware_entry, NULL, &firmware_end, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { @@ -177,6 +179,8 @@ target_ulong riscv_load_kernel(const char *kernel_filename, { uint64_t kernel_load_base, kernel_entry; + g_assert(kernel_filename != NULL); + /* * NB: Use low address not ELF entry point to ensure that the fw_dynamic * behaviour when loading an ELF matches the fw_payload, fw_jump and BBL @@ -209,6 +213,8 @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, { ssize_t size; + g_assert(filename != NULL); + /* * We want to put the initrd far enough into RAM that when the * kernel is uncompressed it will not clobber the initrd. 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([191.17.222.139]) by smtp.gmail.com with ESMTPSA id l39-20020a05687106a700b0014fb4bdc746sm11354475oao.8.2023.01.02.03.52.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 03:53:00 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v5 05/11] hw/riscv/spike.c: load initrd right after riscv_load_kernel() Date: Mon, 2 Jan 2023 08:52:35 -0300 Message-Id: <20230102115241.25733-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230102115241.25733-1-dbarboza@ventanamicro.com> References: <20230102115241.25733-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Jan 2023 11:53:03 -0000 This will make the code more in line with what the other boards are doing. We'll also avoid an extra check to machine->kernel_filename since we already checked that before executing riscv_load_kernel(). Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/spike.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 25c5420ee6..004dfb2d5b 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -302,6 +302,10 @@ static void spike_board_init(MachineState *machine) g_free(firmware_name); } + /* Create device tree */ + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, + riscv_is_32bit(&s->soc[0]), htif_custom_base); + /* Load kernel */ if (machine->kernel_filename) { kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], @@ -310,6 +314,17 @@ static void spike_board_init(MachineState *machine) kernel_entry = riscv_load_kernel(machine->kernel_filename, kernel_start_addr, htif_symbol_callback); + + if (machine->initrd_filename) { + hwaddr start; + hwaddr end = riscv_load_initrd(machine->initrd_filename, + machine->ram_size, kernel_entry, + &start); + qemu_fdt_setprop_cell(machine->fdt, "/chosen", + "linux,initrd-start", start); + qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", + end); + } } else { /* * If dynamic firmware is used, it doesn't know where is the next mode @@ -318,22 +333,6 @@ static void spike_board_init(MachineState *machine) kernel_entry = 0; } - /* Create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc[0]), htif_custom_base); - - /* Load initrd */ - if (machine->kernel_filename && machine->initrd_filename) { - hwaddr start; - hwaddr end = riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", - end); - } - /* Compute the fdt load address in dram */ fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, machine->ram_size, machine->fdt); -- 2.39.0 From MAILER-DAEMON Mon Jan 02 06:53:07 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pCJNL-0007Hs-2S for mharc-qemu-riscv@gnu.org; Mon, 02 Jan 2023 06:53:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pCJNK-0007Ha-2B for qemu-riscv@nongnu.org; Mon, 02 Jan 2023 06:53:06 -0500 Received: from mail-oa1-x31.google.com ([2001:4860:4864:20::31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pCJNI-0002uY-8m for qemu-riscv@nongnu.org; Mon, 02 Jan 2023 06:53:05 -0500 Received: by mail-oa1-x31.google.com with SMTP id 586e51a60fabf-150b06cb1aeso3859811fac.11 for ; Mon, 02 Jan 2023 03:53:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=h/tVtZ9GkUVaaiXEE01175qcEKY/cJoHRK1XXhkLTCg=; b=UU6cpk+6zjtvxoPF2OmZ74ykyO67lQpcRqivb3m1eCuXJ/8Z6zBN4QKUQNF+wG2+wk 48/IxIA/0aE3CR9i9/vToSXjOxmXi42bKxcwLylp2HeUktP1DhA6p3TFD1NOzSpPx4R8 5WgNZM811jy2A1gxuM6bu3ljP5GiXVCbs5LchK95fIpK1aqUPOdr5yij2XqfGFEzv70q 0KWAGTY/T8HvOMPCB/waDJWu34OwE3AmKQEbk6Ttp1/p24vZakGA6lrf3Sjfn4Ie6V0C su7Lf6YrkWybKDuRVZNqug67dharwEf0+U/KYL/+lSXYYm3DGvIGTzhiD+wYlYpBuju4 eQBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=h/tVtZ9GkUVaaiXEE01175qcEKY/cJoHRK1XXhkLTCg=; b=dtVcET+WOfugvJez+mtO+GRhte2sfgoFpP754WARqSwWeIMIkc2o1dJeeXGoLOJS/3 glAioS/j1jzOSBdTbh8nGk12wkWtIC+ra5Nx0r56d2ednfSGwMvxzdsnDuA7974vKVOt 80gh6WeRBooGPrbQsExrbF2G/Zs0dlOo1SLG7qcBWxryInmXhuGy4/Wkmn8neNcOxam/ gv+lv8WuSMWpOR7uCs4T2eCvLDOqiskknnInGJXWjRHxqXJ/oY+YuaSeFq+4HGcggNOX X4gK3oIH/6S7SoEAAI45FaXZ9e5Us+zGOgI792IfFLu7TIe2FkHwmE5xhs0poBEJOcJ3 EGMA== X-Gm-Message-State: AFqh2krs6WrOCQX/qdDvtzBNeiZm3icZPeaiJT1u8WxMCdwS0gv6Cn+o VxtLiyhtklJlJ0gqWjYesad0ZQ== X-Google-Smtp-Source: AMrXdXsxQxgAsO6xFltjM9Me5eBzUdCJU3ek0n71I1ORX0JuqIhcCA2pH84r2NWDqpZbD1V5WZA7rA== X-Received: by 2002:a05:6870:4b93:b0:144:e1eb:432 with SMTP id lx19-20020a0568704b9300b00144e1eb0432mr21975170oab.51.1672660383647; Mon, 02 Jan 2023 03:53:03 -0800 (PST) Received: from grind.. ([191.17.222.139]) by smtp.gmail.com with ESMTPSA id l39-20020a05687106a700b0014fb4bdc746sm11354475oao.8.2023.01.02.03.53.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 03:53:03 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 06/11] hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() Date: Mon, 2 Jan 2023 08:52:36 -0300 Message-Id: <20230102115241.25733-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230102115241.25733-1-dbarboza@ventanamicro.com> References: <20230102115241.25733-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Jan 2023 11:53:06 -0000 riscv_load_initrd() returns the initrd end addr while also writing a 'start' var to mark the addr start. These informations are being used just to write the initrd FDT node. Every existing caller of riscv_load_initrd() is writing the FDT in the same manner. We can simplify things by writing the FDT inside riscv_load_initrd(), sparing callers from having to manage start/end addrs to write the FDT themselves. An 'if (fdt)' check is already inserted at the end of the function because we'll end up using it later on with other boards that doesn´t have a FDT. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- hw/riscv/boot.c | 18 ++++++++++++------ hw/riscv/microchip_pfsoc.c | 10 ++-------- hw/riscv/sifive_u.c | 10 ++-------- hw/riscv/spike.c | 10 ++-------- hw/riscv/virt.c | 10 ++-------- include/hw/riscv/boot.h | 4 ++-- 6 files changed, 22 insertions(+), 40 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 31aa3385a0..6b948d1c9e 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -208,9 +208,10 @@ target_ulong riscv_load_kernel(const char *kernel_filename, exit(1); } -hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, - uint64_t kernel_entry, hwaddr *start) +void riscv_load_initrd(const char *filename, uint64_t mem_size, + uint64_t kernel_entry, void *fdt) { + hwaddr start, end; ssize_t size; g_assert(filename != NULL); @@ -226,18 +227,23 @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, * halfway into RAM, and for boards with 256MB of RAM or more we put * the initrd at 128MB. */ - *start = kernel_entry + MIN(mem_size / 2, 128 * MiB); + start = kernel_entry + MIN(mem_size / 2, 128 * MiB); - size = load_ramdisk(filename, *start, mem_size - *start); + size = load_ramdisk(filename, start, mem_size - start); if (size == -1) { - size = load_image_targphys(filename, *start, mem_size - *start); + size = load_image_targphys(filename, start, mem_size - start); if (size == -1) { error_report("could not load ramdisk '%s'", filename); exit(1); } } - return *start + size; + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ + if (fdt) { + end = start + size; + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); + } } uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index b10321b564..593a799549 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -633,14 +633,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) kernel_start_addr, NULL); if (machine->initrd_filename) { - hwaddr start; - hwaddr end = riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-end", end); + riscv_load_initrd(machine->initrd_filename, machine->ram_size, + kernel_entry, machine->fdt); } if (machine->kernel_cmdline && *machine->kernel_cmdline) { diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index ddceb750ea..37f5087172 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -608,14 +608,8 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr, NULL); if (machine->initrd_filename) { - hwaddr start; - hwaddr end = riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", - end); + riscv_load_initrd(machine->initrd_filename, machine->ram_size, + kernel_entry, machine->fdt); } } else { /* diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 004dfb2d5b..5668fe0694 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -316,14 +316,8 @@ static void spike_board_init(MachineState *machine) htif_symbol_callback); if (machine->initrd_filename) { - hwaddr start; - hwaddr end = riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", - end); + riscv_load_initrd(machine->initrd_filename, machine->ram_size, + kernel_entry, machine->fdt); } } else { /* diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 408f7a2256..5967b136b4 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1291,14 +1291,8 @@ static void virt_machine_done(Notifier *notifier, void *data) kernel_start_addr, NULL); if (machine->initrd_filename) { - hwaddr start; - hwaddr end = riscv_load_initrd(machine->initrd_filename, - machine->ram_size, kernel_entry, - &start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", - "linux,initrd-start", start); - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd-end", - end); + riscv_load_initrd(machine->initrd_filename, machine->ram_size, + kernel_entry, machine->fdt); } } else { /* diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index b273ab22f7..e37e1d1238 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -46,8 +46,8 @@ target_ulong riscv_load_firmware(const char *firmware_filename, target_ulong riscv_load_kernel(const char *kernel_filename, target_ulong firmware_end_addr, symbol_fn_t sym_cb); -hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, - uint64_t kernel_entry, hwaddr *start); +void riscv_load_initrd(const char *filename, uint64_t mem_size, + uint64_t kernel_entry, void *fdt); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr, -- 2.39.0 From MAILER-DAEMON Mon Jan 02 06:53:11 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pCJNP-0007Ip-3G for mharc-qemu-riscv@gnu.org; Mon, 02 Jan 2023 06:53:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pCJNN-0007II-3Z for qemu-riscv@nongnu.org; Mon, 02 Jan 2023 06:53:09 -0500 Received: from mail-oa1-x30.google.com ([2001:4860:4864:20::30]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pCJNL-0002vW-7T for qemu-riscv@nongnu.org; Mon, 02 Jan 2023 06:53:08 -0500 Received: by mail-oa1-x30.google.com with SMTP id 586e51a60fabf-144bd860fdbso33497242fac.0 for ; Mon, 02 Jan 2023 03:53:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; 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([191.17.222.139]) by smtp.gmail.com with ESMTPSA id l39-20020a05687106a700b0014fb4bdc746sm11354475oao.8.2023.01.02.03.53.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 03:53:06 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v5 07/11] hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() Date: Mon, 2 Jan 2023 08:52:37 -0300 Message-Id: <20230102115241.25733-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230102115241.25733-1-dbarboza@ventanamicro.com> References: <20230102115241.25733-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::30; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Jan 2023 11:53:09 -0000 The sifive_u, spike and virt machines are writing the 'bootargs' FDT node during their respective create_fdt(). Given that bootargs is written only when '-append' is used, and this option is only allowed with the '-kernel' option, which in turn is already being check before executing riscv_load_kernel(), write 'bootargs' in the same code path as riscv_load_kernel(). Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé --- hw/riscv/sifive_u.c | 11 +++++------ hw/riscv/spike.c | 9 +++++---- hw/riscv/virt.c | 11 +++++------ 3 files changed, 15 insertions(+), 16 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 37f5087172..3e6df87b5b 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -117,7 +117,6 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, error_report("load_device_tree() failed"); exit(1); } - goto update_bootargs; } else { fdt = ms->fdt = create_device_tree(&fdt_size); if (!fdt) { @@ -510,11 +509,6 @@ static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); g_free(nodename); - -update_bootargs: - if (cmdline && *cmdline) { - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); - } } static void sifive_u_machine_reset(void *opaque, int n, int level) @@ -611,6 +605,11 @@ static void sifive_u_machine_init(MachineState *machine) riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, machine->fdt); } + + if (machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 5668fe0694..60e2912be5 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -179,10 +179,6 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); - - if (cmdline && *cmdline) { - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); - } } static bool spike_test_elf_image(char *filename) @@ -319,6 +315,11 @@ static void spike_board_init(MachineState *machine) riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, machine->fdt); } + + if (machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 5967b136b4..6c946b6def 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1012,7 +1012,6 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, error_report("load_device_tree() failed"); exit(1); } - goto update_bootargs; } else { mc->fdt = create_device_tree(&s->fdt_size); if (!mc->fdt) { @@ -1050,11 +1049,6 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, create_fdt_fw_cfg(s, memmap); create_fdt_pmu(s); -update_bootargs: - if (cmdline && *cmdline) { - qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline); - } - /* Pass seed to RNG */ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); @@ -1294,6 +1288,11 @@ static void virt_machine_done(Notifier *notifier, void *data) riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, machine->fdt); } + + if (machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } } else { /* * If dynamic firmware is used, it doesn't know where is the next mode -- 2.39.0 From MAILER-DAEMON Mon Jan 02 06:53:13 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pCJNR-0007Jp-82 for mharc-qemu-riscv@gnu.org; Mon, 02 Jan 2023 06:53:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pCJNQ-0007JL-9r for qemu-riscv@nongnu.org; Mon, 02 Jan 2023 06:53:12 -0500 Received: from mail-oa1-x2b.google.com ([2001:4860:4864:20::2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pCJNO-0002wh-M7 for qemu-riscv@nongnu.org; Mon, 02 Jan 2023 06:53:12 -0500 Received: by mail-oa1-x2b.google.com with SMTP id 586e51a60fabf-142b72a728fso33407966fac.9 for ; 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Mon, 02 Jan 2023 03:53:09 -0800 (PST) Received: from grind.. ([191.17.222.139]) by smtp.gmail.com with ESMTPSA id l39-20020a05687106a700b0014fb4bdc746sm11354475oao.8.2023.01.02.03.53.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 03:53:09 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v5 08/11] hw/riscv/boot.c: use MachineState in riscv_load_initrd() Date: Mon, 2 Jan 2023 08:52:38 -0300 Message-Id: <20230102115241.25733-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230102115241.25733-1-dbarboza@ventanamicro.com> References: <20230102115241.25733-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::2b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Jan 2023 11:53:12 -0000 'filename', 'mem_size' and 'fdt' from riscv_load_initrd() can all be retrieved by the MachineState object for all callers. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng --- hw/riscv/boot.c | 6 ++++-- hw/riscv/microchip_pfsoc.c | 3 +-- hw/riscv/sifive_u.c | 3 +-- hw/riscv/spike.c | 3 +-- hw/riscv/virt.c | 3 +-- include/hw/riscv/boot.h | 3 +-- 6 files changed, 9 insertions(+), 12 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 6b948d1c9e..d3e780c3b6 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -208,9 +208,11 @@ target_ulong riscv_load_kernel(const char *kernel_filename, exit(1); } -void riscv_load_initrd(const char *filename, uint64_t mem_size, - uint64_t kernel_entry, void *fdt) +void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) { + const char *filename = machine->initrd_filename; + uint64_t mem_size = machine->ram_size; + void *fdt = machine->fdt; hwaddr start, end; ssize_t size; diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 593a799549..1e9b0a420e 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -633,8 +633,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) kernel_start_addr, NULL); if (machine->initrd_filename) { - riscv_load_initrd(machine->initrd_filename, machine->ram_size, - kernel_entry, machine->fdt); + riscv_load_initrd(machine, kernel_entry); } if (machine->kernel_cmdline && *machine->kernel_cmdline) { diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 3e6df87b5b..c40885ed5c 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -602,8 +602,7 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr, NULL); if (machine->initrd_filename) { - riscv_load_initrd(machine->initrd_filename, machine->ram_size, - kernel_entry, machine->fdt); + riscv_load_initrd(machine, kernel_entry); } if (machine->kernel_cmdline && *machine->kernel_cmdline) { diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 60e2912be5..99dec74fe8 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -312,8 +312,7 @@ static void spike_board_init(MachineState *machine) htif_symbol_callback); if (machine->initrd_filename) { - riscv_load_initrd(machine->initrd_filename, machine->ram_size, - kernel_entry, machine->fdt); + riscv_load_initrd(machine, kernel_entry); } if (machine->kernel_cmdline && *machine->kernel_cmdline) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 6c946b6def..02f1369843 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1285,8 +1285,7 @@ static void virt_machine_done(Notifier *notifier, void *data) kernel_start_addr, NULL); if (machine->initrd_filename) { - riscv_load_initrd(machine->initrd_filename, machine->ram_size, - kernel_entry, machine->fdt); + riscv_load_initrd(machine, kernel_entry); } if (machine->kernel_cmdline && *machine->kernel_cmdline) { diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index e37e1d1238..cfd72ecabf 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -46,8 +46,7 @@ target_ulong riscv_load_firmware(const char *firmware_filename, target_ulong riscv_load_kernel(const char *kernel_filename, target_ulong firmware_end_addr, symbol_fn_t sym_cb); -void riscv_load_initrd(const char *filename, uint64_t mem_size, - uint64_t kernel_entry, void *fdt); +void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr, -- 2.39.0 From MAILER-DAEMON Mon Jan 02 06:53:26 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pCJNd-0007N8-2F for mharc-qemu-riscv@gnu.org; Mon, 02 Jan 2023 06:53:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pCJNX-0007Kd-Bq for qemu-riscv@nongnu.org; Mon, 02 Jan 2023 06:53:20 -0500 Received: from mail-oa1-x31.google.com ([2001:4860:4864:20::31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pCJNQ-0002uY-Uv for qemu-riscv@nongnu.org; Mon, 02 Jan 2023 06:53:14 -0500 Received: by mail-oa1-x31.google.com with SMTP id 586e51a60fabf-150b06cb1aeso3860095fac.11 for ; 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([191.17.222.139]) by smtp.gmail.com with ESMTPSA id l39-20020a05687106a700b0014fb4bdc746sm11354475oao.8.2023.01.02.03.53.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 03:53:11 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v5 09/11] hw/riscv/boot.c: use MachineState in riscv_load_kernel() Date: Mon, 2 Jan 2023 08:52:39 -0300 Message-Id: <20230102115241.25733-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230102115241.25733-1-dbarboza@ventanamicro.com> References: <20230102115241.25733-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Jan 2023 11:53:21 -0000 All callers are using kernel_filename as machine->kernel_filename. This will also simplify the changes in riscv_load_kernel() that we're going to do next. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng --- hw/riscv/boot.c | 3 ++- hw/riscv/microchip_pfsoc.c | 3 +-- hw/riscv/opentitan.c | 3 +-- hw/riscv/sifive_e.c | 3 +-- hw/riscv/sifive_u.c | 3 +-- hw/riscv/spike.c | 3 +-- hw/riscv/virt.c | 3 +-- include/hw/riscv/boot.h | 2 +- 8 files changed, 9 insertions(+), 14 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index d3e780c3b6..2594276223 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -173,10 +173,11 @@ target_ulong riscv_load_firmware(const char *firmware_filename, exit(1); } -target_ulong riscv_load_kernel(const char *kernel_filename, +target_ulong riscv_load_kernel(MachineState *machine, target_ulong kernel_start_addr, symbol_fn_t sym_cb) { + const char *kernel_filename = machine->kernel_filename; uint64_t kernel_load_base, kernel_entry; g_assert(kernel_filename != NULL); diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 1e9b0a420e..82ae5e7023 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -629,8 +629,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, NULL); + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 85ffdac5be..64d5d435b9 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -101,8 +101,7 @@ static void opentitan_board_init(MachineState *machine) } if (machine->kernel_filename) { - riscv_load_kernel(machine->kernel_filename, - memmap[IBEX_DEV_RAM].base, NULL); + riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); } } diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index d65d2fd869..3e3f4b0088 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -114,8 +114,7 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); if (machine->kernel_filename) { - riscv_load_kernel(machine->kernel_filename, - memmap[SIFIVE_E_DEV_DTIM].base, NULL); + riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL); } } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index c40885ed5c..bac394c959 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -598,8 +598,7 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, NULL); + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 99dec74fe8..bff9475686 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -307,8 +307,7 @@ static void spike_board_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr); - kernel_entry = riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, htif_symbol_callback); if (machine->initrd_filename) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 02f1369843..c8e35f861e 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1281,8 +1281,7 @@ static void virt_machine_done(Notifier *notifier, void *data) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr); - kernel_entry = riscv_load_kernel(machine->kernel_filename, - kernel_start_addr, NULL); + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index cfd72ecabf..f94653a09b 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -43,7 +43,7 @@ char *riscv_find_firmware(const char *firmware_filename, target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr, symbol_fn_t sym_cb); -target_ulong riscv_load_kernel(const char *kernel_filename, +target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, symbol_fn_t sym_cb); void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); -- 2.39.0 From MAILER-DAEMON Mon Jan 02 06:53:31 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pCJNj-0007Th-EF for mharc-qemu-riscv@gnu.org; Mon, 02 Jan 2023 06:53:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pCJNb-0007Mk-9c for qemu-riscv@nongnu.org; Mon, 02 Jan 2023 06:53:24 -0500 Received: from mail-oa1-x2a.google.com ([2001:4860:4864:20::2a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pCJNX-0002xJ-54 for qemu-riscv@nongnu.org; Mon, 02 Jan 2023 06:53:22 -0500 Received: by mail-oa1-x2a.google.com with SMTP id 586e51a60fabf-1433ef3b61fso33401876fac.10 for ; Mon, 02 Jan 2023 03:53:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; 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Mon, 02 Jan 2023 03:53:17 -0800 (PST) Received: from grind.. ([191.17.222.139]) by smtp.gmail.com with ESMTPSA id l39-20020a05687106a700b0014fb4bdc746sm11354475oao.8.2023.01.02.03.53.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 03:53:17 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v5 11/11] hw/riscv/boot.c: make riscv_load_initrd() static Date: Mon, 2 Jan 2023 08:52:41 -0300 Message-Id: <20230102115241.25733-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230102115241.25733-1-dbarboza@ventanamicro.com> References: <20230102115241.25733-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::2a; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Jan 2023 11:53:25 -0000 The only remaining caller is riscv_load_kernel_and_initrd() which belongs to the same file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng --- hw/riscv/boot.c | 80 ++++++++++++++++++++--------------------- include/hw/riscv/boot.h | 1 - 2 files changed, 40 insertions(+), 41 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 4888d5c1e0..e868fb6ade 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -173,6 +173,46 @@ target_ulong riscv_load_firmware(const char *firmware_filename, exit(1); } +static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) +{ + const char *filename = machine->initrd_filename; + uint64_t mem_size = machine->ram_size; + void *fdt = machine->fdt; + hwaddr start, end; + ssize_t size; + + g_assert(filename != NULL); + + /* + * We want to put the initrd far enough into RAM that when the + * kernel is uncompressed it will not clobber the initrd. However + * on boards without much RAM we must ensure that we still leave + * enough room for a decent sized initrd, and on boards with large + * amounts of RAM we must avoid the initrd being so far up in RAM + * that it is outside lowmem and inaccessible to the kernel. + * So for boards with less than 256MB of RAM we put the initrd + * halfway into RAM, and for boards with 256MB of RAM or more we put + * the initrd at 128MB. + */ + start = kernel_entry + MIN(mem_size / 2, 128 * MiB); + + size = load_ramdisk(filename, start, mem_size - start); + if (size == -1) { + size = load_image_targphys(filename, start, mem_size - start); + if (size == -1) { + error_report("could not load ramdisk '%s'", filename); + exit(1); + } + } + + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ + if (fdt) { + end = start + size; + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); + } +} + target_ulong riscv_load_kernel(MachineState *machine, target_ulong kernel_start_addr, bool load_initrd, @@ -225,46 +265,6 @@ out: return kernel_entry; } -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) -{ - const char *filename = machine->initrd_filename; - uint64_t mem_size = machine->ram_size; - void *fdt = machine->fdt; - hwaddr start, end; - ssize_t size; - - g_assert(filename != NULL); - - /* - * We want to put the initrd far enough into RAM that when the - * kernel is uncompressed it will not clobber the initrd. However - * on boards without much RAM we must ensure that we still leave - * enough room for a decent sized initrd, and on boards with large - * amounts of RAM we must avoid the initrd being so far up in RAM - * that it is outside lowmem and inaccessible to the kernel. - * So for boards with less than 256MB of RAM we put the initrd - * halfway into RAM, and for boards with 256MB of RAM or more we put - * the initrd at 128MB. - */ - start = kernel_entry + MIN(mem_size / 2, 128 * MiB); - - size = load_ramdisk(filename, start, mem_size - start); - if (size == -1) { - size = load_image_targphys(filename, start, mem_size - start); - if (size == -1) { - error_report("could not load ramdisk '%s'", filename); - exit(1); - } - } - - /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ - if (fdt) { - end = start + size; - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); - } -} - uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) { uint64_t temp, fdt_addr; diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index c3de897371..cbd131bad7 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -47,7 +47,6 @@ target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, bool load_initrd, symbol_fn_t sym_cb); -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr, -- 2.39.0 From MAILER-DAEMON Mon Jan 02 06:53:39 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pCJNn-0007W0-9I for mharc-qemu-riscv@gnu.org; Mon, 02 Jan 2023 06:53:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pCJNb-0007Mn-BI for qemu-riscv@nongnu.org; Mon, 02 Jan 2023 06:53:24 -0500 Received: from mail-oa1-x35.google.com ([2001:4860:4864:20::35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pCJNX-0002xC-7g for qemu-riscv@nongnu.org; Mon, 02 Jan 2023 06:53:22 -0500 Received: by mail-oa1-x35.google.com with SMTP id 586e51a60fabf-15027746720so18369874fac.13 for ; Mon, 02 Jan 2023 03:53:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gYxSVYjQZGu2VngPkKm+KpuQK9qUuKEGr99kdASAZGo=; b=HzzlDPWAZCtd+ptGdcbrnLSEixOBhhPKhZlad1l3UIuJgPj2u8GvUzdpMMhYG27Vqn aAubH9nhgk/dVs9JqKmzE9F4P1ZkJZ79jvrtAMCoknnRBEzUIG9lik1l1XjQPzpL08Qs RvYROz2RgD83Sr6RhvLIXIxaFFHkfYssNr3IlkOIb5vSJ/F4zhUzZyHJmM9e0U81xK8A 5uXFLSLWIOnUxHHfETv0W+7er2qZX92tAM/a7zHanfgB5gPk9DltvPspHcjlmOFKgXZf NGtHwTg6VRVazblMpmZistDqrTmqPW427nhIohxeI+pKqBAhHmw6ZNqwhXy7VW82Ld1Z qdfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gYxSVYjQZGu2VngPkKm+KpuQK9qUuKEGr99kdASAZGo=; b=NX8rWqQeN6z1++bFCZpuDv3zdG2KXxbkqBrcL64/dtLY7++2BPdUZV/1Dc3LrLcAfw ndT3F10/Tyrw9RsndZn8z0FUn48QRurS1FOCE6KDc21bC25cK3uP06aOJsbsU786sR// 1NDDVyjwDSML5B4DbaZC9M5+vfndPnsh746GMUWjOO3oiAdVmkbsOXuHADxXsXECrnfK UeoVheBz4gLO5ExkcuwV9olXcBUcDe4535yCpv8x8OknO1LhAadrQMmXPI4r0RvaYNUH 9kqAO9sY7/j/ge0Nz2P+lAQEyWDh41hrTxB4v7fuyUo57tppmtuaBm+fBwxXCs2Caguw NsVw== X-Gm-Message-State: AFqh2krrB1NPllVrPjLHwU6bL89w6cNtw/cyAOdLfuLFqI4nhWcvcgh/ SoZLJ1cClyln1Ek9hERkAh9Blw== X-Google-Smtp-Source: AMrXdXsaJ5xg2+o2gZmwf9CIEkXvFcTZC2QVXwBQOS8NZY5G85E110aK/seAZJXCEEBXoZyzEqf0Aw== X-Received: by 2002:a05:6870:b624:b0:13b:1f84:b7d7 with SMTP id cm36-20020a056870b62400b0013b1f84b7d7mr21388452oab.13.1672660394858; Mon, 02 Jan 2023 03:53:14 -0800 (PST) Received: from grind.. ([191.17.222.139]) by smtp.gmail.com with ESMTPSA id l39-20020a05687106a700b0014fb4bdc746sm11354475oao.8.2023.01.02.03.53.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jan 2023 03:53:14 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng , Palmer Dabbelt Subject: [PATCH v5 10/11] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() Date: Mon, 2 Jan 2023 08:52:40 -0300 Message-Id: <20230102115241.25733-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230102115241.25733-1-dbarboza@ventanamicro.com> References: <20230102115241.25733-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::35; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Jan 2023 11:53:25 -0000 The microchip_icicle_kit, sifive_u, spike and virt boards are now doing the same steps when '-kernel' is used: - execute load_kernel() - load init_rd() - write kernel_cmdline Let's fold everything inside riscv_load_kernel() to avoid code repetition. To not change the behavior of boards that aren't calling riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and allow these boards to opt out from initrd loading. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 22 +++++++++++++++++++--- hw/riscv/microchip_pfsoc.c | 12 ++---------- hw/riscv/opentitan.c | 2 +- hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 12 ++---------- hw/riscv/spike.c | 11 +---------- hw/riscv/virt.c | 12 ++---------- include/hw/riscv/boot.h | 1 + 8 files changed, 30 insertions(+), 45 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 2594276223..4888d5c1e0 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -175,10 +175,12 @@ target_ulong riscv_load_firmware(const char *firmware_filename, target_ulong riscv_load_kernel(MachineState *machine, target_ulong kernel_start_addr, + bool load_initrd, symbol_fn_t sym_cb) { const char *kernel_filename = machine->kernel_filename; uint64_t kernel_load_base, kernel_entry; + void *fdt = machine->fdt; g_assert(kernel_filename != NULL); @@ -192,21 +194,35 @@ target_ulong riscv_load_kernel(MachineState *machine, if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL, &kernel_load_base, NULL, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { - return kernel_load_base; + kernel_entry = kernel_load_base; + goto out; } if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, NULL, NULL, NULL) > 0) { - return kernel_entry; + goto out; } if (load_image_targphys_as(kernel_filename, kernel_start_addr, current_machine->ram_size, NULL) > 0) { - return kernel_start_addr; + kernel_entry = kernel_start_addr; + goto out; } error_report("could not load kernel '%s'", kernel_filename); exit(1); + +out: + if (load_initrd && machine->initrd_filename) { + riscv_load_initrd(machine, kernel_entry); + } + + if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } + + return kernel_entry; } void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 82ae5e7023..c45023a2b1 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -629,16 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", - "bootargs", machine->kernel_cmdline); - } + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, + true, NULL); /* Compute the fdt load address in dram */ fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 64d5d435b9..f6fd9725a5 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -101,7 +101,7 @@ static void opentitan_board_init(MachineState *machine) } if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); + riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, false, NULL); } } diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 3e3f4b0088..6835d1c807 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL); + riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, + false, NULL); } } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index bac394c959..9a75d4aa62 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -598,16 +598,8 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, + true, NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index bff9475686..c517885e6e 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -308,16 +308,7 @@ static void spike_board_init(MachineState *machine) firmware_end_addr); kernel_entry = riscv_load_kernel(machine, kernel_start_addr, - htif_symbol_callback); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + true, htif_symbol_callback); } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c8e35f861e..a931ed05ab 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1281,16 +1281,8 @@ static void virt_machine_done(Notifier *notifier, void *data) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, + true, NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index f94653a09b..c3de897371 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -45,6 +45,7 @@ target_ulong riscv_load_firmware(const char *firmware_filename, symbol_fn_t sym_cb); target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, + bool load_initrd, symbol_fn_t sym_cb); void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); -- 2.39.0 From MAILER-DAEMON Tue Jan 03 11:13:59 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pCjvK-0006kP-V3 for mharc-qemu-riscv@gnu.org; Tue, 03 Jan 2023 11:13:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pCjvI-0006k5-GZ for qemu-riscv@nongnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::936; envelope-from=apatel@ventanamicro.com; helo=mail-ua1-x936.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 03 Jan 2023 16:13:56 -0000 Hi Alistair, On Wed, Dec 28, 2022 at 11:08 AM Alistair Francis wrote: > > On Fri, Dec 23, 2022 at 11:14 PM Anup Patel wrote: > > > > On Thu, Dec 15, 2022 at 8:55 AM Alistair Francis wrote: > > > > > > On Mon, Dec 12, 2022 at 9:12 PM Anup Patel wrote: > > > > > > > > On Mon, Dec 12, 2022 at 11:23 AM Alistair Francis wrote: > > > > > > > > > > On Thu, Dec 8, 2022 at 6:41 PM Anup Patel wrote: > > > > > > > > > > > > On Thu, Dec 8, 2022 at 9:00 AM Alistair Francis wrote: > > > > > > > > > > > > > > On Tue, Nov 8, 2022 at 11:07 PM Anup Patel wrote: > > > > > > > > > > > > > > > > The htimedelta[h] CSR has impact on the VS timer comparison so we > > > > > > > > should call riscv_timer_write_timecmp() whenever htimedelta changes. > > > > > > > > > > > > > > > > Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") > > > > > > > > Signed-off-by: Anup Patel > > > > > > > > Reviewed-by: Alistair Francis > > > > > > > > > > > > > > This patch breaks my Xvisor test. When running OpenSBI and Xvisor like this: > > > > > > > > > > > > > > qemu-system-riscv64 -machine virt \ > > > > > > > -m 1G -serial mon:stdio -serial null -nographic \ > > > > > > > -append 'vmm.console=uart@10000000 vmm.bootcmd="vfs mount initrd > > > > > > > /;vfs run /boot.xscript;vfs cat /system/banner.txt; guest kick guest0; > > > > > > > vserial bind guest0/uart0"' \ > > > > > > > -smp 4 -d guest_errors \ > > > > > > > -bios none \ > > > > > > > -device loader,file=./images/qemuriscv64/vmm.bin,addr=0x80200000 \ > > > > > > > -kernel ./images/qemuriscv64/fw_jump.elf \ > > > > > > > -initrd ./images/qemuriscv64/vmm-disk-linux.img -cpu rv64,h=true > > > > > > > > > > > > > > Running: > > > > > > > > > > > > > > Xvisor v0.3.0-129-gbc33f339 (Jan 1 1970 00:00:00) > > > > > > > > > > > > > > I see this failure: > > > > > > > > > > > > > > INIT: bootcmd: guest kick guest0 > > > > > > > > > > > > > > guest0: Kicked > > > > > > > > > > > > > > INIT: bootcmd: vserial bind guest0/uart0 > > > > > > > > > > > > > > [guest0/uart0] cpu_vcpu_stage2_map: guest_phys=0x000000003B9AC000 > > > > > > > size=0x4096 map failed > > > > > > > > > > > > > > do_error: CPU3: VCPU=guest0/vcpu0 page fault failed (error -1) > > > > > > > > > > > > > > zero=0x0000000000000000 ra=0x0000000080001B4E > > > > > > > > > > > > > > sp=0x000000008001CF80 gp=0x0000000000000000 > > > > > > > > > > > > > > tp=0x0000000000000000 s0=0x000000008001CFB0 > > > > > > > > > > > > > > s1=0x0000000000000000 a0=0x0000000010001048 > > > > > > > > > > > > > > a1=0x0000000000000000 a2=0x0000000000989680 > > > > > > > > > > > > > > a3=0x000000003B9ACA00 a4=0x0000000000000048 > > > > > > > > > > > > > > a5=0x0000000000000000 a6=0x0000000000019000 > > > > > > > > > > > > > > a7=0x0000000000000000 s2=0x0000000000000000 > > > > > > > > > > > > > > s3=0x0000000000000000 s4=0x0000000000000000 > > > > > > > > > > > > > > s5=0x0000000000000000 s6=0x0000000000000000 > > > > > > > > > > > > > > s7=0x0000000000000000 s8=0x0000000000000000 > > > > > > > > > > > > > > s9=0x0000000000000000 s10=0x0000000000000000 > > > > > > > > > > > > > > s11=0x0000000000000000 t0=0x0000000000004000 > > > > > > > > > > > > > > t1=0x0000000000000100 t2=0x0000000000000000 > > > > > > > > > > > > > > t3=0x0000000000000000 t4=0x0000000000000000 > > > > > > > > > > > > > > t5=0x0000000000000000 t6=0x0000000000000000 > > > > > > > > > > > > > > sepc=0x0000000080001918 sstatus=0x0000000200004120 > > > > > > > > > > > > > > hstatus=0x00000002002001C0 sp_exec=0x0000000010A64000 > > > > > > > > > > > > > > scause=0x0000000000000017 stval=0x000000003B9ACAF8 > > > > > > > > > > > > > > htval=0x000000000EE6B2BE htinst=0x0000000000D03021 > > > > > > > > > > > > > > I have tried updating to a newer Xvisor release, but with that I don't > > > > > > > get any serial output. > > > > > > > > > > > > > > Can you help get the Xvisor tests back up and running? > > > > > > > > > > > > I tried the latest Xvisor-next (https://github.com/avpatel/xvisor-next) > > > > > > with your QEMU riscv-to-apply.next branch and it works fine (both > > > > > > with and without Sstc). > > > > > > > > > > Does it work with the latest release? > > > > > > > > Yes, the latest Xvisor-next repo works for QEMU v7.2.0-rc4 and > > > > your riscv-to-apply.next branch (commit 51bb9de2d188) > > > > > > I can't get anything to work with this patch. I have dropped this and > > > the patches after this. > > > > > > I'm building the latest Xvisor release with: > > > > > > export CROSS_COMPILE=riscv64-linux-gnu- > > > ARCH=riscv make generic-64b-defconfig > > > make > > > > > > and running it as above, yet nothing. What am I missing here? > > > > I tried multiple times with the latest Xvisor on different machines but > > still can't reproduce the issue you are seeing. > > Odd > > > > > We generally provide pre-built binaries with every Xvisor release > > so I will share with you pre-built binaries of the upcoming Xvisor-0.3.2 > > release. Maybe that would help you ? > > That would work. Let me know when the release happens and I can update > my images. Please download the Xvisor v0.3.2 pre-built binary tarball from: https://xhypervisor.org/tarball/xvisor-0.3.2-bins.tar.xz After untarring the above tarball, you can try the following command: $ qemu-system-riscv64 -M virt -m 512M -nographic -bios opensbi/build/platform/generic/firmware/fw_jump.bin -kernel xvisor-0.3.2-bins/riscv/rv64/xvisor/vmm.bin -initrd xvisor-0.3.2-bins/riscv/rv64/guest/virt64/disk-linux-6.1.1-one_guest_virt64.ext2 -append "vmm.bootcmd=\"vfs mount initrd /;vfs run /boot.xscript;vfs cat /system/banner.txt\"" OR $ qemu-system-riscv32 -M virt -m 512M -nographic -bios opensbi/build/platform/generic/firmware/fw_jump.bin -kernel xvisor-0.3.2-bins/riscv/rv32/xvisor/vmm.bin -initrd xvisor-0.3.2-bins/riscv/rv32/guest/virt32/disk-linux-6.1.1-one_guest_virt32.ext2 -append "vmm.bootcmd=\"vfs mount initrd /;vfs run /boot.xscript;vfs cat /system/banner.txt\"" Regards, Anup From MAILER-DAEMON Wed Jan 04 17:05:18 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBss-0008Kz-Fi for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 17:05:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBsZ-0008BU-QD for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:05:04 -0500 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDBsW-0004zW-Km for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:04:59 -0500 Received: by mail-ej1-x636.google.com with SMTP id tz12so85975429ejc.9 for ; Wed, 04 Jan 2023 14:04:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=TFfnwjftSBTQtlrSBz3RLCltb8prEkxU+BRsjCrCgtQ=; b=pCKy3Vgcn9frgL1Z6PKfnlIn4yF3aXjidG7SLKuNXzFpa3mU8tY2cNUadw4pji+k0F jvpcI50AwZiG3VGGcq9ma6u2qDa7eHF+2i8kQFHVey8/mdD64bhVe9IxFoIN7pJgyEf9 2c7BWfk0pHq4Ja3VgwFKR6baxop3v5zgBfBmdwkLjZCalagvZxady8XUc2k0Biwihz8s CEJEEa6hlHhcbuSTswJ32VaW4KbPzupRCjO94mOhv0UuY/HIlezodfZJvRsu2ij2a1NM oKjxWkEjZPwRP+CDs82l4DPEDA57dMMt1e/I0mPPx/wMggcz0N8AyNqo2FMG0IOfNmG3 hv2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=TFfnwjftSBTQtlrSBz3RLCltb8prEkxU+BRsjCrCgtQ=; b=T4EUbvkoK0VepBPUTgMkYA5vagOukXBmMCWqtLUW1TV+xGIfraEbH+AkP/ffToZ8mT QRRnMAauUWv5kQcClsmhLOwcW8+E1Gtx9/woTrI6af1vTY+HomYhaNjLF6nH7bH7FzB1 bPrD+L0D1U17/lyk1yV0l3tGpfdIIuAHCFzAi2hxLC3gki6I04ZHoeGvoT+t5YYtrcYN y+yyHmyKD0hE68kL6eJ/DSlCSyhMIATLRaVkzBNqppVmcaADF1hSuyZ1LRkN64YtbVw5 thE4vpAs6UQizHG2nTl89SZRRFR/LsjdDa3Si6lxLRfkR9gUxUFw2l60vC8CtbNVGq/4 lDFw== X-Gm-Message-State: AFqh2kp+3S4arcCIQAiIyZvAbX4+XTOoPQpzzXTZOe6wBm+MhJuif6zr ZRVlRBpOYgOl4Alq9y6r1WkByA== X-Google-Smtp-Source: AMrXdXv8vYeyfvNZ6wMfRLyd7GkFBEmpWbZ4qZ0RgO9hI3ghNmrgaXrH0twPL68Bf7bsOSPFBGU6ow== X-Received: by 2002:a17:907:c48d:b0:7c0:fe60:be12 with SMTP id tp13-20020a170907c48d00b007c0fe60be12mr38960273ejc.25.1672869894693; Wed, 04 Jan 2023 14:04:54 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id i16-20020a170906115000b008373f9ea148sm15784340eja.71.2023.01.04.14.04.50 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Jan 2023 14:04:54 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 00/20] hw: Remove implicit sysbus_mmio_map() from pflash APIs Date: Wed, 4 Jan 2023 23:04:29 +0100 Message-Id: <20230104220449.41337-1-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=philmd@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:05:10 -0000 Paving the road toward heterogeneous QEMU, the limitations of having a single machine sysbus become more apparent. The sysbus_mmio_map() API forces the caller to map a sysbus device to an address on the system bus (system bus here is the root MemoryRegion returned by get_system_memory() ). This is not practical when each core has its own address space and group of cores have access to a part of the peripherals. Experimenting with the PFLASH devices. Here the fix is quite easy, we split the pflash_cfi_register() -- which does the implicit sysbus mapping -- into an explicit qdev pflash_cfi_create() followed by the sysbus_mmio_map() call. Since we were touching the PFLASH API, we restricted the PFlashCFI0X structures to their models. The API now deals with a generic qdev pointer (DeviceState*). First 15 patches deal with the CFI type 1 model, then the last 5 with the type 2. The patch logic is mostly: - extract pflash_cfi_create() from pflash_cfi_register() - open-code pflash_cfi_register() for each hw/${ARCH}/ - remove unused pflash_cfi_register() - reduce PFlashCFI0x structure scope Please review, Phil. Philippe Mathieu-Daudé (20): hw/block: Pass DeviceState to pflash_cfi01_get_blk() hw/block: Use pflash_cfi01_get_blk() in pflash_cfi01_legacy_drive() hw/block: Pass DeviceState to pflash_cfi01_get_memory() hw/arm: Use generic DeviceState instead of PFlashCFI01 hw/loongarch: Use generic DeviceState instead of PFlashCFI01 hw/riscv: Use generic DeviceState instead of PFlashCFI01 hw/i386: Use generic DeviceState instead of PFlashCFI01 hw/xtensa: Use generic DeviceState instead of PFlashCFI01 hw/block: Factor pflash_cfi01_create() out of pflash_cfi01_register() hw/arm: Open-code pflash_cfi01_register() hw/microblaze: Open-code pflash_cfi01_register() hw/mips: Open-code pflash_cfi01_register() hw/ppc: Open-code pflash_cfi01_register() hw/block: Remove unused pflash_cfi01_register() hw/block: Make PFlashCFI01 QOM declaration internal hw/block: Factor pflash_cfi02_create() out of pflash_cfi02_register() hw/arm: Open-code pflash_cfi02_register() hw/sh4: Open-code pflash_cfi02_register() hw/block: Remove unused pflash_cfi02_register() hw/block: Make PFlashCFI02 QOM declaration internal hw/arm/collie.c | 15 ++++--- hw/arm/digic_boards.c | 14 +++--- hw/arm/gumstix.c | 19 +++++--- hw/arm/mainstone.c | 13 +++--- hw/arm/musicpal.c | 13 +++--- hw/arm/omap_sx1.c | 22 +++++---- hw/arm/sbsa-ref.c | 8 ++-- hw/arm/versatilepb.c | 13 +++--- hw/arm/vexpress.c | 12 +++-- hw/arm/virt.c | 6 +-- hw/arm/xilinx_zynq.c | 10 ++--- hw/arm/z2.c | 10 +++-- hw/block/pflash_cfi01.c | 35 ++++++++------- hw/block/pflash_cfi02.c | 25 +++++------ hw/i386/pc_sysfw.c | 6 +-- hw/loongarch/virt.c | 9 ++-- hw/microblaze/petalogix_ml605_mmu.c | 8 ++-- hw/microblaze/petalogix_s3adsp1800_mmu.c | 8 ++-- hw/mips/malta.c | 13 +++--- hw/ppc/e500.c | 2 +- hw/ppc/sam460ex.c | 12 +++-- hw/ppc/virtex_ml507.c | 7 +-- hw/riscv/virt.c | 7 +-- hw/sh4/r2d.c | 9 ++-- hw/xtensa/xtfpga.c | 6 +-- include/hw/arm/virt.h | 3 +- include/hw/block/flash.h | 57 ++++++++++++------------ include/hw/i386/pc.h | 3 +- include/hw/loongarch/virt.h | 3 +- include/hw/riscv/virt.h | 3 +- 30 files changed, 200 insertions(+), 171 deletions(-) -- 2.38.1 From MAILER-DAEMON Wed Jan 04 17:05:33 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBt6-0008SS-TI for mharc-qemu-riscv@gnu.org; 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Wed, 04 Jan 2023 14:05:10 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 02/20] hw/block: Use pflash_cfi01_get_blk() in pflash_cfi01_legacy_drive() Date: Wed, 4 Jan 2023 23:04:31 +0100 Message-Id: <20230104220449.41337-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:05:18 -0000 By using pflash_cfi01_get_blk(), pflash_cfi01_legacy_drive() doesn't require any knowledge of the PFlashCFI01 structure. Thus we can pass a generic DeviceState pointer. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/sbsa-ref.c | 2 +- hw/arm/virt.c | 2 +- hw/block/pflash_cfi01.c | 6 +++--- hw/i386/pc_sysfw.c | 2 +- hw/riscv/virt.c | 2 +- include/hw/block/flash.h | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 65b9acba04..1d29e8ca7f 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -340,7 +340,7 @@ static bool sbsa_firmware_init(SBSAMachineState *sms, /* Map legacy -drive if=pflash to machine properties */ for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { - pflash_cfi01_legacy_drive(sms->flash[i], + pflash_cfi01_legacy_drive(DEVICE(sms->flash[i]), drive_get(IF_PFLASH, 0, i)); } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 954e3ca5ce..57726b0f52 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1227,7 +1227,7 @@ static bool virt_firmware_init(VirtMachineState *vms, /* Map legacy -drive if=pflash to machine properties */ for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { - pflash_cfi01_legacy_drive(vms->flash[i], + pflash_cfi01_legacy_drive(DEVICE(vms->flash[i]), drive_get(IF_PFLASH, 0, i)); } diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 458c50ec45..8beba24989 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -1002,7 +1002,7 @@ MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl) * Else if @fl's property "drive" is already set, fatal error. * Else set it to the BlockBackend with @dinfo. */ -void pflash_cfi01_legacy_drive(PFlashCFI01 *fl, DriveInfo *dinfo) +void pflash_cfi01_legacy_drive(DeviceState *dev, DriveInfo *dinfo) { Location loc; @@ -1012,11 +1012,11 @@ void pflash_cfi01_legacy_drive(PFlashCFI01 *fl, DriveInfo *dinfo) loc_push_none(&loc); qemu_opts_loc_restore(dinfo->opts); - if (fl->blk) { + if (pflash_cfi01_get_blk(dev)) { error_report("clashes with -machine"); exit(1); } - qdev_prop_set_drive_err(DEVICE(fl), "drive", blk_by_legacy_dinfo(dinfo), + qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(dinfo), &error_fatal); loc_pop(&loc); } diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c index 4b85c48ec8..c08cba6628 100644 --- a/hw/i386/pc_sysfw.c +++ b/hw/i386/pc_sysfw.c @@ -214,7 +214,7 @@ void pc_system_firmware_init(PCMachineState *pcms, /* Map legacy -drive if=pflash to machine properties */ for (i = 0; i < ARRAY_SIZE(pcms->flash); i++) { - pflash_cfi01_legacy_drive(pcms->flash[i], + pflash_cfi01_legacy_drive(DEVICE(pcms->flash[i]), drive_get(IF_PFLASH, 0, i)); pflash_blk[i] = pflash_cfi01_get_blk(DEVICE(pcms->flash[i])); } diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index a5bc7353b4..400bd9329f 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1517,7 +1517,7 @@ static void virt_machine_init(MachineState *machine) for (i = 0; i < ARRAY_SIZE(s->flash); i++) { /* Map legacy -drive if=pflash to machine properties */ - pflash_cfi01_legacy_drive(s->flash[i], + pflash_cfi01_legacy_drive(DEVICE(s->flash[i]), drive_get(IF_PFLASH, 0, i)); } virt_flash_map(s, system_memory); diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h index 961b6e9f74..701a2c1701 100644 --- a/include/hw/block/flash.h +++ b/include/hw/block/flash.h @@ -23,7 +23,7 @@ PFlashCFI01 *pflash_cfi01_register(hwaddr base, int be); BlockBackend *pflash_cfi01_get_blk(DeviceState *dev); MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl); -void pflash_cfi01_legacy_drive(PFlashCFI01 *dev, DriveInfo *dinfo); +void pflash_cfi01_legacy_drive(DeviceState *dev, DriveInfo *dinfo); /* pflash_cfi02.c */ -- 2.38.1 From MAILER-DAEMON Wed Jan 04 17:05:33 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBt7-0008Sv-2g for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 17:05:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBsg-0008GG-Be for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:05:10 -0500 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDBsd-0004zc-WF for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:05:06 -0500 Received: by mail-ej1-x632.google.com with SMTP id qk9so85775810ejc.3 for ; Wed, 04 Jan 2023 14:05:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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Wed, 04 Jan 2023 14:05:03 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id v9-20020a170906292900b0073dd8e5a39fsm15648723ejd.156.2023.01.04.14.04.59 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Jan 2023 14:05:02 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 01/20] hw/block: Pass DeviceState to pflash_cfi01_get_blk() Date: Wed, 4 Jan 2023 23:04:30 +0100 Message-Id: <20230104220449.41337-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:05:13 -0000 The point of a getter() function is to not expose the structure internal fields. Otherwise callers could simply access the PFlashCFI01::blk field. Have the callers pass a DeviceState* argument. The QOM type check is done in the callee. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/sbsa-ref.c | 2 +- hw/arm/virt.c | 2 +- hw/block/pflash_cfi01.c | 4 +++- hw/i386/pc_sysfw.c | 4 ++-- include/hw/block/flash.h | 2 +- 5 files changed, 8 insertions(+), 6 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 4bb444684f..65b9acba04 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -346,7 +346,7 @@ static bool sbsa_firmware_init(SBSAMachineState *sms, sbsa_flash_map(sms, sysmem, secure_sysmem); - pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); + pflash_blk0 = pflash_cfi01_get_blk(DEVICE(sms->flash[0])); bios_name = MACHINE(sms)->firmware; if (bios_name) { diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ea2413a0ba..954e3ca5ce 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1233,7 +1233,7 @@ static bool virt_firmware_init(VirtMachineState *vms, virt_flash_map(vms, sysmem, secure_sysmem); - pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); + pflash_blk0 = pflash_cfi01_get_blk(DEVICE(vms->flash[0])); bios_name = MACHINE(vms)->firmware; if (bios_name) { diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 0cbc2fb4cb..458c50ec45 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -984,8 +984,10 @@ PFlashCFI01 *pflash_cfi01_register(hwaddr base, return PFLASH_CFI01(dev); } -BlockBackend *pflash_cfi01_get_blk(PFlashCFI01 *fl) +BlockBackend *pflash_cfi01_get_blk(DeviceState *dev) { + PFlashCFI01 *fl = PFLASH_CFI01(dev); + return fl->blk; } diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c index c8d9e71b88..4b85c48ec8 100644 --- a/hw/i386/pc_sysfw.c +++ b/hw/i386/pc_sysfw.c @@ -152,7 +152,7 @@ static void pc_system_flash_map(PCMachineState *pcms, for (i = 0; i < ARRAY_SIZE(pcms->flash); i++) { system_flash = pcms->flash[i]; - blk = pflash_cfi01_get_blk(system_flash); + blk = pflash_cfi01_get_blk(DEVICE(system_flash)); if (!blk) { break; } @@ -216,7 +216,7 @@ void pc_system_firmware_init(PCMachineState *pcms, for (i = 0; i < ARRAY_SIZE(pcms->flash); i++) { pflash_cfi01_legacy_drive(pcms->flash[i], drive_get(IF_PFLASH, 0, i)); - pflash_blk[i] = pflash_cfi01_get_blk(pcms->flash[i]); + pflash_blk[i] = pflash_cfi01_get_blk(DEVICE(pcms->flash[i])); } /* Reject gaps */ diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h index 86d8363bb0..961b6e9f74 100644 --- a/include/hw/block/flash.h +++ b/include/hw/block/flash.h @@ -21,7 +21,7 @@ PFlashCFI01 *pflash_cfi01_register(hwaddr base, uint16_t id0, uint16_t id1, uint16_t id2, uint16_t id3, int be); -BlockBackend *pflash_cfi01_get_blk(PFlashCFI01 *fl); +BlockBackend *pflash_cfi01_get_blk(DeviceState *dev); MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl); void pflash_cfi01_legacy_drive(PFlashCFI01 *dev, DriveInfo *dinfo); -- 2.38.1 From MAILER-DAEMON Wed Jan 04 17:05:34 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBt8-0008Vj-FL for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 17:05:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBsw-0008Me-7B for qemu-riscv@nongnu.org; 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Wed, 04 Jan 2023 14:05:18 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 03/20] hw/block: Pass DeviceState to pflash_cfi01_get_memory() Date: Wed, 4 Jan 2023 23:04:32 +0100 Message-Id: <20230104220449.41337-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=philmd@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:05:30 -0000 The point of a getter() function is to not expose the structure internal fields. Otherwise callers could simply access the PFlashCFI01::mem field. Have the callers pass a DeviceState* argument. The QOM type check is done in the callee. Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi01.c | 4 +++- hw/i386/pc_sysfw.c | 2 +- hw/mips/malta.c | 3 ++- hw/ppc/e500.c | 2 +- hw/xtensa/xtfpga.c | 2 +- include/hw/block/flash.h | 2 +- 6 files changed, 9 insertions(+), 6 deletions(-) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 8beba24989..866ea596ea 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -991,8 +991,10 @@ BlockBackend *pflash_cfi01_get_blk(DeviceState *dev) return fl->blk; } -MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl) +MemoryRegion *pflash_cfi01_get_memory(DeviceState *dev) { + PFlashCFI01 *fl = PFLASH_CFI01(dev); + return &fl->mem; } diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c index c08cba6628..60db0efb41 100644 --- a/hw/i386/pc_sysfw.c +++ b/hw/i386/pc_sysfw.c @@ -187,7 +187,7 @@ static void pc_system_flash_map(PCMachineState *pcms, 0x100000000ULL - total_size); if (i == 0) { - flash_mem = pflash_cfi01_get_memory(system_flash); + flash_mem = pflash_cfi01_get_memory(DEVICE(system_flash)); pc_isa_bios_init(rom_memory, flash_mem, size); /* Encrypt the pflash boot ROM */ diff --git a/hw/mips/malta.c b/hw/mips/malta.c index c0a2e0ab04..43fbb97799 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1291,7 +1291,8 @@ void mips_malta_init(MachineState *machine) dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 65536, 4, 0x0000, 0x0000, 0x0000, 0x0000, be); - bios = pflash_cfi01_get_memory(fl); + dev = DEVICE(fl); + bios = pflash_cfi01_get_memory(dev); fl_idx++; if (kernel_filename) { ram_low_size = MIN(ram_size, 256 * MiB); diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 9fa1f8e6cf..b127068431 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -1144,7 +1144,7 @@ void ppce500_init(MachineState *machine) sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); memory_region_add_subregion(&pms->pbus_dev->mmio, 0, - pflash_cfi01_get_memory(PFLASH_CFI01(dev))); + pflash_cfi01_get_memory(dev)); } /* diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index 2a5556a35f..bce3a543b0 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -459,7 +459,7 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) } } else { if (flash) { - MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); + MemoryRegion *flash_mr = pflash_cfi01_get_memory(DEVICE(flash)); MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); uint32_t size = env->config->sysrom.location[0].size; diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h index 701a2c1701..25affdf7a5 100644 --- a/include/hw/block/flash.h +++ b/include/hw/block/flash.h @@ -22,7 +22,7 @@ PFlashCFI01 *pflash_cfi01_register(hwaddr base, uint16_t id2, uint16_t id3, int be); BlockBackend *pflash_cfi01_get_blk(DeviceState *dev); -MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl); +MemoryRegion *pflash_cfi01_get_memory(DeviceState *dev); void pflash_cfi01_legacy_drive(DeviceState *dev, DriveInfo *dinfo); /* pflash_cfi02.c */ -- 2.38.1 From MAILER-DAEMON Wed Jan 04 17:05:37 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBtB-0000Cb-Et for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 17:05:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBt7-0008UW-Lu for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:05:33 -0500 Received: from mail-ed1-x533.google.com ([2a00:1450:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDBt4-0005NC-07 for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:05:33 -0500 Received: by mail-ed1-x533.google.com with SMTP id g1so36311188edj.8 for ; Wed, 04 Jan 2023 14:05:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Qmw6mVPGSBueqZ8PeN/WPt3EaFW2iGA5QNW2jlN+kis=; b=Cn18Ln+rBBUV7QcJMsZOyJFmLFK2lBcawTwo43OtNIbV5GAVcaIZ/cSeBVaaeTqrfW GcHoSlur4IX4UaanV7v697LOCYlLJAlflesIIWWEI3AodA+3kJZxBMqxHglqCdD34Ahh GCoumHYH0BeyXnZOAOTyBKCWtfD6yt7TpXrfLLmnoj/bCA9xD32ImcGTQNpa7v/AwBcL tZEt0CRzukWztAHlkjx+wBsrRtx1rUtbDW0N6FwpKr0nn+NheHfLwxvFih4UWmiTpUQB 761AM+5t4ACtsY9vtP1Q6AkEOMEcWtYYnv+3PFiFgLFg4jeTwXgft162AXx8apyk53cs 2WMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Qmw6mVPGSBueqZ8PeN/WPt3EaFW2iGA5QNW2jlN+kis=; b=REhWK1l1nHCPGE20VPsL6m/FQYMMnYB07RRnriWu6KE3XcBJHvjcX1NFaXTku6fIJC ciIt5cTGDitXfwqbX+cYoKRA8sdrG4TfqK+9RBfFnH72xYafO4pVNOzirIxan3Y8ukto JZmBjn4qIQ5AnjZSk9bPVn8MiKNQGdsW7hkc84AHBkoXX2z6L8l8W34U/s8LcnEAj2hW 8DrtXSK0ESgHwK4hTgL5vM3UiKSyJMamBXaRV5PVjsQpY7foRRdqAi0iBrmBqnlqgtS7 tcfmlB0N9n7gvDuDc1Hk9pbvc6KNalfMVPVeN1sytI871P2NE+sXe1YLK36MQehY5Qy2 prIA== X-Gm-Message-State: AFqh2koVV7i+fRwq8kkzqvQ626oKcv2mKoLkodafHuan3mx9WVqzPI/L fL2Bqzn7+gJErc1IDqrbSb5e+A== X-Google-Smtp-Source: AMrXdXt2FKPWJ0RL3eX5vY6bOkmuLuKsfPeWtPBkzVHmZ/GehDSvSBpdOdvvdqm/XRfPYYsZ9kW5+A== X-Received: by 2002:a05:6402:2932:b0:47e:bdb8:9133 with SMTP id ee50-20020a056402293200b0047ebdb89133mr48601228edb.38.1672869927788; Wed, 04 Jan 2023 14:05:27 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id h25-20020aa7de19000000b00463b9d47e1fsm15290614edv.71.2023.01.04.14.05.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Jan 2023 14:05:27 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 04/20] hw/arm: Use generic DeviceState instead of PFlashCFI01 Date: Wed, 4 Jan 2023 23:04:33 +0100 Message-Id: <20230104220449.41337-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=philmd@linaro.org; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:05:34 -0000 Nothing here requires access to PFlashCFI01 internal fields: use the inherited generic DeviceState. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/sbsa-ref.c | 12 ++++++------ hw/arm/vexpress.c | 12 +++++------- hw/arm/virt.c | 10 +++++----- include/hw/arm/virt.h | 3 +-- 4 files changed, 17 insertions(+), 20 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 1d29e8ca7f..8e60e0e58d 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -91,7 +91,7 @@ struct SBSAMachineState { int fdt_size; int psci_conduit; DeviceState *gic; - PFlashCFI01 *flash[2]; + DeviceState *flash[2]; }; #define TYPE_SBSA_MACHINE MACHINE_TYPE_NAME("sbsa-ref") @@ -264,7 +264,7 @@ static void create_fdt(SBSAMachineState *sms) #define SBSA_FLASH_SECTOR_SIZE (256 * KiB) -static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, +static DeviceState *sbsa_flash_create1(SBSAMachineState *sms, const char *name, const char *alias_prop_name) { @@ -286,7 +286,7 @@ static PFlashCFI01 *sbsa_flash_create1(SBSAMachineState *sms, object_property_add_child(OBJECT(sms), name, OBJECT(dev)); object_property_add_alias(OBJECT(sms), alias_prop_name, OBJECT(dev), "drive"); - return PFLASH_CFI01(dev); + return dev; } static void sbsa_flash_create(SBSAMachineState *sms) @@ -295,7 +295,7 @@ static void sbsa_flash_create(SBSAMachineState *sms) sms->flash[1] = sbsa_flash_create1(sms, "sbsa.flash1", "pflash1"); } -static void sbsa_flash_map1(PFlashCFI01 *flash, +static void sbsa_flash_map1(DeviceState *flash, hwaddr base, hwaddr size, MemoryRegion *sysmem) { @@ -340,13 +340,13 @@ static bool sbsa_firmware_init(SBSAMachineState *sms, /* Map legacy -drive if=pflash to machine properties */ for (i = 0; i < ARRAY_SIZE(sms->flash); i++) { - pflash_cfi01_legacy_drive(DEVICE(sms->flash[i]), + pflash_cfi01_legacy_drive(sms->flash[i], drive_get(IF_PFLASH, 0, i)); } sbsa_flash_map(sms, sysmem, secure_sysmem); - pflash_blk0 = pflash_cfi01_get_blk(DEVICE(sms->flash[0])); + pflash_blk0 = pflash_cfi01_get_blk(sms->flash[0]); bios_name = MACHINE(sms)->firmware; if (bios_name) { diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index e1d1983ae6..94eeff73d9 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -508,7 +508,7 @@ static void vexpress_modify_dtb(const struct arm_boot_info *info, void *fdt) /* Open code a private version of pflash registration since we * need to set non-default device width for VExpress platform. */ -static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name, +static DeviceState *ve_pflash_cfi01_register(hwaddr base, const char *name, DriveInfo *di) { DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); @@ -531,7 +531,7 @@ static PFlashCFI01 *ve_pflash_cfi01_register(hwaddr base, const char *name, sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); - return PFLASH_CFI01(dev); + return dev; } static void vexpress_common_init(MachineState *machine) @@ -543,7 +543,6 @@ static void vexpress_common_init(MachineState *machine) qemu_irq pic[64]; uint32_t sys_id; DriveInfo *dinfo; - PFlashCFI01 *pflash0; I2CBus *i2c; ram_addr_t vram_size, sram_size; MemoryRegion *sysmem = get_system_memory(); @@ -657,16 +656,15 @@ static void vexpress_common_init(MachineState *machine) sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); dinfo = drive_get(IF_PFLASH, 0, 0); - pflash0 = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", - dinfo); - if (!pflash0) { + dev = ve_pflash_cfi01_register(map[VE_NORFLASH0], "vexpress.flash0", dinfo); + if (!dev) { error_report("vexpress: error registering flash 0"); exit(1); } if (map[VE_NORFLASHALIAS] != -1) { /* Map flash 0 as an alias into low memory */ - flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(pflash0), 0); + flash0mem = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); memory_region_init_alias(flashalias, NULL, "vexpress.flashalias", flash0mem, 0, VEXPRESS_FLASH_SIZE); memory_region_add_subregion(sysmem, map[VE_NORFLASHALIAS], flashalias); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 57726b0f52..e47070105d 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1105,7 +1105,7 @@ static void create_virtio_devices(const VirtMachineState *vms) #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) -static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, +static DeviceState *virt_flash_create1(VirtMachineState *vms, const char *name, const char *alias_prop_name) { @@ -1127,7 +1127,7 @@ static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, object_property_add_child(OBJECT(vms), name, OBJECT(dev)); object_property_add_alias(OBJECT(vms), alias_prop_name, OBJECT(dev), "drive"); - return PFLASH_CFI01(dev); + return dev; } static void virt_flash_create(VirtMachineState *vms) @@ -1136,7 +1136,7 @@ static void virt_flash_create(VirtMachineState *vms) vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1"); } -static void virt_flash_map1(PFlashCFI01 *flash, +static void virt_flash_map1(DeviceState *flash, hwaddr base, hwaddr size, MemoryRegion *sysmem) { @@ -1227,13 +1227,13 @@ static bool virt_firmware_init(VirtMachineState *vms, /* Map legacy -drive if=pflash to machine properties */ for (i = 0; i < ARRAY_SIZE(vms->flash); i++) { - pflash_cfi01_legacy_drive(DEVICE(vms->flash[i]), + pflash_cfi01_legacy_drive(vms->flash[i], drive_get(IF_PFLASH, 0, i)); } virt_flash_map(vms, sysmem, secure_sysmem); - pflash_blk0 = pflash_cfi01_get_blk(DEVICE(vms->flash[0])); + pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]); bios_name = MACHINE(vms)->firmware; if (bios_name) { diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index c7dd59d7f1..817b43b248 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -34,7 +34,6 @@ #include "qemu/notify.h" #include "hw/boards.h" #include "hw/arm/boot.h" -#include "hw/block/flash.h" #include "sysemu/kvm.h" #include "hw/intc/arm_gicv3_common.h" #include "qom/object.h" @@ -142,7 +141,7 @@ struct VirtMachineState { Notifier machine_done; DeviceState *platform_bus_dev; FWCfgState *fw_cfg; - PFlashCFI01 *flash[2]; + DeviceState *flash[2]; bool secure; bool highmem; bool highmem_compact; -- 2.38.1 From MAILER-DAEMON Wed Jan 04 17:05:40 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBtE-0000Na-LG for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 17:05:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBtC-0000HA-Fb for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:05:38 -0500 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDBtA-0005Bu-MM for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:05:38 -0500 Received: by mail-ej1-x636.google.com with SMTP id x22so85912636ejs.11 for ; Wed, 04 Jan 2023 14:05:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; 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Wed, 04 Jan 2023 14:05:35 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id ue3-20020a170907c68300b0084c7f96d023sm9207905ejc.147.2023.01.04.14.05.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Jan 2023 14:05:35 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 05/20] hw/loongarch: Use generic DeviceState instead of PFlashCFI01 Date: Wed, 4 Jan 2023 23:04:34 +0100 Message-Id: <20230104220449.41337-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=philmd@linaro.org; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:05:38 -0000 Nothing here requires access to PFlashCFI01 internal fields: use the inherited generic DeviceState. Signed-off-by: Philippe Mathieu-Daudé --- hw/loongarch/virt.c | 9 ++++----- include/hw/loongarch/virt.h | 3 +-- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c index c8a495ea30..cd5aa26f49 100644 --- a/hw/loongarch/virt.c +++ b/hw/loongarch/virt.c @@ -45,7 +45,7 @@ #include "sysemu/block-backend.h" #include "hw/block/flash.h" -static void virt_flash_create(LoongArchMachineState *lams) +static DeviceState *virt_flash_create(LoongArchMachineState *lams) { DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); @@ -62,14 +62,13 @@ static void virt_flash_create(LoongArchMachineState *lams) object_property_add_alias(OBJECT(lams), "pflash", OBJECT(dev), "drive"); - lams->flash = PFLASH_CFI01(dev); + return dev; } static void virt_flash_map(LoongArchMachineState *lams, MemoryRegion *sysmem) { - PFlashCFI01 *flash = lams->flash; - DeviceState *dev = DEVICE(flash); + DeviceState *dev = lams->flash; hwaddr base = VIRT_FLASH_BASE; hwaddr size = VIRT_FLASH_SIZE; @@ -899,7 +898,7 @@ static void loongarch_machine_initfn(Object *obj) lams->acpi = ON_OFF_AUTO_AUTO; lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); - virt_flash_create(lams); + lams->flash = virt_flash_create(lams); } static bool memhp_type_supported(DeviceState *dev) diff --git a/include/hw/loongarch/virt.h b/include/hw/loongarch/virt.h index f5f818894e..519b25c722 100644 --- a/include/hw/loongarch/virt.h +++ b/include/hw/loongarch/virt.h @@ -12,7 +12,6 @@ #include "hw/boards.h" #include "qemu/queue.h" #include "hw/intc/loongarch_ipi.h" -#include "hw/block/flash.h" #define LOONGARCH_MAX_VCPUS 4 @@ -52,7 +51,7 @@ struct LoongArchMachineState { int fdt_size; DeviceState *platform_bus_dev; PCIBus *pci_bus; - PFlashCFI01 *flash; + DeviceState *flash; }; #define TYPE_LOONGARCH_MACHINE MACHINE_TYPE_NAME("virt") -- 2.38.1 From MAILER-DAEMON Wed Jan 04 17:05:51 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBtO-0000eC-8s for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 17:05:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBtL-0000cK-Sh for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:05:47 -0500 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDBtJ-0004zY-8m for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:05:47 -0500 Received: by mail-ej1-x630.google.com with SMTP id t17so85835764eju.1 for ; Wed, 04 Jan 2023 14:05:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ostFdFduA8VJQbdYun/a8v7V9oLZ2nQ4qLyqomH/nUo=; b=cZ1cbmjQ9ajzsj/qRRfezodu3WDXPkdUOzcyfLhMAGZk/ZZsnQX8L58azDOnW26nY2 d77GDNdgpJpNRgzpyqOvYsPjXCT9i/J5aoH5EdSbqseARnUzFrWVm2GA9VYtWyislI8P +d9MHiwMsAtUNES2ptR/KpU1jEI7ykv/SxgED3znEp8cuE4lbh+0NIqCIlRqN6hOsVHc NBUKvTYJgFphynebyrrdNuPY2rAx1ixETvE84bufagH96rg/QteKoQNu25PnT8ao0Itk iFYhlmoXrwxKIGXX0gElKp+LoXToMt7F4Ms+lSflR+x3iy+PLgU/r1payraLhASTbpaN rtxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ostFdFduA8VJQbdYun/a8v7V9oLZ2nQ4qLyqomH/nUo=; b=Y7f+FYTPB/5ANIzuW0vX/YOibJRmGrSlxAQq+QCId+36t9nZhsjk+kdgm+JQN8u33q uYjPP8ammIbXUpQcmTECqtm6ouMDDUSm6fAZbg0qLRhHus991IL1yBYQKLB6oCvwqJoO 1hyRjazF3zohzXWXQwI9yXf8LfMrLyZswZRkmpSTO6np+TqcIXyEWkzmOKubPnxUDxCV 5DoYCFjhWa6Qgwke3o9abCCLObdOxC3ZOIy0cLdgPc5pHYAAEdghmgaM1TIADRZ4BdOT S4652apNYgPMRQZBvTFkOZu/WAMVO8zt5wuG+t5+gvlk0BuBlUbTzMsXe9UyykwbK6+H gNDw== X-Gm-Message-State: AFqh2krwTre06oKrzH/dNpKnnk5MBRYvchOyO5vn2X+CbrjFz8YbKamj dL36a6o4EO6EP423iZveWszt2w== X-Google-Smtp-Source: AMrXdXtP0Ui0b2hBx7NHtBze8v+zdSqTXs6aUE7faqv0xwYoEZhCWQ/aBwDwRmY3x3v8mwVBFvbpLA== X-Received: by 2002:a17:906:5012:b0:7c1:2e19:ba3f with SMTP id s18-20020a170906501200b007c12e19ba3fmr47063708ejj.57.1672869944488; Wed, 04 Jan 2023 14:05:44 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id b10-20020a1709063caa00b007bd28b50305sm15541696ejh.200.2023.01.04.14.05.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Jan 2023 14:05:44 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 06/20] hw/riscv: Use generic DeviceState instead of PFlashCFI01 Date: Wed, 4 Jan 2023 23:04:35 +0100 Message-Id: <20230104220449.41337-7-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=philmd@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:05:48 -0000 Nothing here requires access to PFlashCFI01 internal fields: use the inherited generic DeviceState. Signed-off-by: Philippe Mathieu-Daudé --- hw/riscv/virt.c | 9 +++++---- include/hw/riscv/virt.h | 3 +-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 400bd9329f..b421a9dc12 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -46,6 +46,7 @@ #include "sysemu/sysemu.h" #include "sysemu/kvm.h" #include "sysemu/tpm.h" +#include "hw/block/flash.h" #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" #include "hw/display/ramfb.h" @@ -106,7 +107,7 @@ static MemMapEntry virt_high_pcie_memmap; #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) -static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, +static DeviceState *virt_flash_create1(RISCVVirtState *s, const char *name, const char *alias_prop_name) { @@ -130,7 +131,7 @@ static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, object_property_add_alias(OBJECT(s), alias_prop_name, OBJECT(dev), "drive"); - return PFLASH_CFI01(dev); + return dev; } static void virt_flash_create(RISCVVirtState *s) @@ -139,7 +140,7 @@ static void virt_flash_create(RISCVVirtState *s) s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); } -static void virt_flash_map1(PFlashCFI01 *flash, +static void virt_flash_map1(DeviceState *flash, hwaddr base, hwaddr size, MemoryRegion *sysmem) { @@ -1517,7 +1518,7 @@ static void virt_machine_init(MachineState *machine) for (i = 0; i < ARRAY_SIZE(s->flash); i++) { /* Map legacy -drive if=pflash to machine properties */ - pflash_cfi01_legacy_drive(DEVICE(s->flash[i]), + pflash_cfi01_legacy_drive(s->flash[i], drive_get(IF_PFLASH, 0, i)); } virt_flash_map(s, system_memory); diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index be4ab8fe7f..b700a46763 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -21,7 +21,6 @@ #include "hw/riscv/riscv_hart.h" #include "hw/sysbus.h" -#include "hw/block/flash.h" #include "qom/object.h" #define VIRT_CPUS_MAX_BITS 9 @@ -49,7 +48,7 @@ struct RISCVVirtState { DeviceState *platform_bus_dev; RISCVHartArrayState soc[VIRT_SOCKETS_MAX]; DeviceState *irqchip[VIRT_SOCKETS_MAX]; - PFlashCFI01 *flash[2]; + DeviceState *flash[2]; FWCfgState *fw_cfg; int fdt_size; -- 2.38.1 From MAILER-DAEMON Wed Jan 04 17:06:06 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBte-0000kx-HP for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 17:06:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBtV-0000fk-PX for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:06:04 -0500 Received: from mail-ed1-x52c.google.com ([2a00:1450:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDBtR-0005VQ-KL for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:05:56 -0500 Received: by mail-ed1-x52c.google.com with SMTP id b88so43253032edf.6 for ; Wed, 04 Jan 2023 14:05:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; 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Wed, 04 Jan 2023 14:05:52 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id c4-20020aa7c984000000b004873927780bsm10065344edt.20.2023.01.04.14.05.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Jan 2023 14:05:51 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 07/20] hw/i386: Use generic DeviceState instead of PFlashCFI01 Date: Wed, 4 Jan 2023 23:04:36 +0100 Message-Id: <20230104220449.41337-8-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=philmd@linaro.org; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:06:04 -0000 Nothing here requires access to PFlashCFI01 internal fields: use the inherited generic DeviceState. Signed-off-by: Philippe Mathieu-Daudé --- hw/i386/pc_sysfw.c | 14 +++++++------- include/hw/i386/pc.h | 3 +-- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c index 60db0efb41..1a12207dd1 100644 --- a/hw/i386/pc_sysfw.c +++ b/hw/i386/pc_sysfw.c @@ -71,7 +71,7 @@ static void pc_isa_bios_init(MemoryRegion *rom_memory, memory_region_set_readonly(isa_bios, true); } -static PFlashCFI01 *pc_pflash_create(PCMachineState *pcms, +static DeviceState *pc_pflash_create(PCMachineState *pcms, const char *name, const char *alias_prop_name) { @@ -88,7 +88,7 @@ static PFlashCFI01 *pc_pflash_create(PCMachineState *pcms, * will be removed with object_unparent. */ object_unref(OBJECT(dev)); - return PFLASH_CFI01(dev); + return dev; } void pc_system_flash_create(PCMachineState *pcms) @@ -143,7 +143,7 @@ static void pc_system_flash_map(PCMachineState *pcms, int i; BlockBackend *blk; int64_t size; - PFlashCFI01 *system_flash; + DeviceState *system_flash; MemoryRegion *flash_mem; void *flash_ptr; int flash_size; @@ -152,7 +152,7 @@ static void pc_system_flash_map(PCMachineState *pcms, for (i = 0; i < ARRAY_SIZE(pcms->flash); i++) { system_flash = pcms->flash[i]; - blk = pflash_cfi01_get_blk(DEVICE(system_flash)); + blk = pflash_cfi01_get_blk(system_flash); if (!blk) { break; } @@ -187,7 +187,7 @@ static void pc_system_flash_map(PCMachineState *pcms, 0x100000000ULL - total_size); if (i == 0) { - flash_mem = pflash_cfi01_get_memory(DEVICE(system_flash)); + flash_mem = pflash_cfi01_get_memory(system_flash); pc_isa_bios_init(rom_memory, flash_mem, size); /* Encrypt the pflash boot ROM */ @@ -214,9 +214,9 @@ void pc_system_firmware_init(PCMachineState *pcms, /* Map legacy -drive if=pflash to machine properties */ for (i = 0; i < ARRAY_SIZE(pcms->flash); i++) { - pflash_cfi01_legacy_drive(DEVICE(pcms->flash[i]), + pflash_cfi01_legacy_drive(pcms->flash[i], drive_get(IF_PFLASH, 0, i)); - pflash_blk[i] = pflash_cfi01_get_blk(DEVICE(pcms->flash[i])); + pflash_blk[i] = pflash_cfi01_get_blk(pcms->flash[i]); } /* Reject gaps */ diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 991f905f5d..70abe61805 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -6,7 +6,6 @@ #include "qemu/uuid.h" #include "hw/boards.h" #include "hw/block/fdc.h" -#include "hw/block/flash.h" #include "hw/i386/x86.h" #include "hw/acpi/acpi_dev_interface.h" @@ -35,7 +34,7 @@ typedef struct PCMachineState { /* Pointers to devices and objects: */ PCIBus *bus; I2CBus *smbus; - PFlashCFI01 *flash[2]; + DeviceState *flash[2]; ISADevice *pcspk; DeviceState *iommu; -- 2.38.1 From MAILER-DAEMON Wed Jan 04 17:06:07 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBtf-0000o4-Ld for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 17:06:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBtd-0000jo-UV for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:06:06 -0500 Received: from mail-ed1-x532.google.com ([2a00:1450:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDBtc-0005Wz-4o for qemu-riscv@nongnu.org; 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Wed, 04 Jan 2023 14:06:00 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 08/20] hw/xtensa: Use generic DeviceState instead of PFlashCFI01 Date: Wed, 4 Jan 2023 23:04:37 +0100 Message-Id: <20230104220449.41337-9-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=philmd@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:06:06 -0000 Nothing here requires access to PFlashCFI01 internal fields: use the inherited generic DeviceState. Signed-off-by: Philippe Mathieu-Daudé --- hw/xtensa/xtfpga.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index bce3a543b0..b039416fde 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -165,7 +165,7 @@ static void xtfpga_net_init(MemoryRegion *address_space, memory_region_add_subregion(address_space, buffers, ram); } -static PFlashCFI01 *xtfpga_flash_init(MemoryRegion *address_space, +static DeviceState *xtfpga_flash_init(MemoryRegion *address_space, const XtfpgaBoardDesc *board, DriveInfo *dinfo, int be) { @@ -183,7 +183,7 @@ static PFlashCFI01 *xtfpga_flash_init(MemoryRegion *address_space, sysbus_realize_and_unref(s, &error_fatal); memory_region_add_subregion(address_space, board->flash->base, sysbus_mmio_get_region(s, 0)); - return PFLASH_CFI01(dev); + return dev; } static uint64_t translate_phys_addr(void *opaque, uint64_t addr) @@ -231,7 +231,7 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) XtensaMxPic *mx_pic = NULL; qemu_irq *extints; DriveInfo *dinfo; - PFlashCFI01 *flash = NULL; + DeviceState *flash = NULL; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *dtb_filename = machine->dtb; @@ -459,7 +459,7 @@ static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) } } else { if (flash) { - MemoryRegion *flash_mr = pflash_cfi01_get_memory(DEVICE(flash)); + MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); uint32_t size = env->config->sysrom.location[0].size; -- 2.38.1 From MAILER-DAEMON Wed Jan 04 17:06:20 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBts-00016C-KB for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 17:06:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBtn-00012v-EB for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:06:19 -0500 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDBtk-0005an-PG for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:06:15 -0500 Received: by mail-ej1-x635.google.com with SMTP id jo4so85999914ejb.7 for ; Wed, 04 Jan 2023 14:06:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z2g0/bIHuF6JENINR0ukwrslIoZo+6BphJxXJPFuUoA=; b=cHbFn/dI7fHDxK0+Cvs0oyq556Oz3wGu7uHHU6r+Qd8AasfMWlllthzE00jKPqqy72 QzkTgUBdFqEc0koPdE1mgQiwTcn+ST40jN9eYR9Zm4xFJgb8MkYG1xBl9jO/0muUJC4e irHCUS7u+zebYjNmSmTpn8mIAurnMUGzcxkbiQS3nlpl+F/Rtb5ct+Lb3B2ZMc6+v7q7 o3pDMCmHyKs7JT/iO4WgvhBbZDYpLLGA+NpuFxfCA+kjHjlQimNpSkKDyXyTqy9fRywy ym4apnExO41EBzYdtNdVyxrw3vN1CpXjdaYXJgumfU2D0EkpjSHTLL1p/nOAmOoPll1/ Cmvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z2g0/bIHuF6JENINR0ukwrslIoZo+6BphJxXJPFuUoA=; b=R8MNrauilBvb1SbgYGIucQdOrscb2HPmi+ypfSG5j4GmWzSn8wruIA9v1rTmKqqF0V 0muiMd5+RAWPPy+jSEP2834QPUcSC8sazZgL6fmRllTNSn1twwb7AF5bOwiy3jqCVNJx pHJINgNQltT/35oxTlmG+t0/hgT4PgVhXCb33xUtDm3kvrmBLXlNrKiwXA3TiVnaX9Ft JJx4WhFFrWy6YpTmoGS5KZUvO8V09JqWI7udZ78uAyVyy0MKQ2QucL2F0VzNu8u1Po/m WSRcQSwupiMyZAF/sWrCxkqNcRoL4eYqGpY9Xt2q1pionb+vvGeYUQc/JsWbDOT7Bp0Q 2f3w== X-Gm-Message-State: AFqh2krGXiarsrJLvJkU5Lxlv7RkFmuzrvYY6BMd5YR57+EVdHa/8KNd h7gPbwY4vvn4drHo/MELprVy1w== X-Google-Smtp-Source: AMrXdXvdTRePASLl9eMl7xbRwkPnlSIeH+UE+hYG04A/Tqgx5GyFrtVautv8eelLM+nXkVv8zhlPZQ== X-Received: by 2002:a17:906:ecf7:b0:7c4:f6e4:3e92 with SMTP id qt23-20020a170906ecf700b007c4f6e43e92mr49876646ejb.31.1672869971229; Wed, 04 Jan 2023 14:06:11 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id ky14-20020a170907778e00b007c4f8bc322asm15644296ejc.196.2023.01.04.14.06.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Jan 2023 14:06:10 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 09/20] hw/block: Factor pflash_cfi01_create() out of pflash_cfi01_register() Date: Wed, 4 Jan 2023 23:04:38 +0100 Message-Id: <20230104220449.41337-10-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=philmd@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:06:19 -0000 Currently pflash_cfi01_register(): 1/ creates a TYPE_PFLASH_CFI01 qdev instance 2/ maps the first MMIO region to the system bus The first minor issue is the implicit sysbus mapping is not obvious (the function name could mention it), and the function is not documented. Another issue is we are forced to map on sysbus, thus code wanting to simply instantiate this device are forced to open code the qdev creation. This is a problem in a heterogeneous system where not all cores has access to the sysbus, or if we want to map the pflash on different address spaces. To clarify this API, extract the qdev creation in a new helper named pflash_cfi01_create(). We don't document pflash_cfi01_register() because we are going to remove it in a few commits. Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi01.c | 34 +++++++++++++++++++++++++--------- include/hw/block/flash.h | 14 +++++++++++++- 2 files changed, 38 insertions(+), 10 deletions(-) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 866ea596ea..6a8f9e6319 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -953,15 +953,13 @@ static void pflash_cfi01_register_types(void) type_init(pflash_cfi01_register_types) -PFlashCFI01 *pflash_cfi01_register(hwaddr base, - const char *name, - hwaddr size, - BlockBackend *blk, - uint32_t sector_len, - int bank_width, - uint16_t id0, uint16_t id1, - uint16_t id2, uint16_t id3, - int be) +DeviceState *pflash_cfi01_create(const char *name, + hwaddr size, + BlockBackend *blk, uint32_t sector_len, + int bank_width, + uint16_t id0, uint16_t id1, + uint16_t id2, uint16_t id3, + int be) { DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); @@ -980,7 +978,25 @@ PFlashCFI01 *pflash_cfi01_register(hwaddr base, qdev_prop_set_string(dev, "name", name); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + return dev; +} + +PFlashCFI01 *pflash_cfi01_register(hwaddr base, + const char *name, + hwaddr size, + BlockBackend *blk, + uint32_t sector_len, + int bank_width, + uint16_t id0, uint16_t id1, + uint16_t id2, uint16_t id3, + int be) +{ + DeviceState *dev; + + dev = pflash_cfi01_create(name, size, blk, sector_len, bank_width, + id0, id1, id2, id3, be); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); + return PFLASH_CFI01(dev); } diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h index 25affdf7a5..40ba857f69 100644 --- a/include/hw/block/flash.h +++ b/include/hw/block/flash.h @@ -11,7 +11,19 @@ #define TYPE_PFLASH_CFI01 "cfi.pflash01" OBJECT_DECLARE_SIMPLE_TYPE(PFlashCFI01, PFLASH_CFI01) - +/** + * Create and realize a parallel NOR flash (CFI type 1) on the heap. + * + * Create the device state structure, initialize it, and drop the + * reference to it (the device is realized). + */ +DeviceState *pflash_cfi01_create(const char *name, + hwaddr size, + BlockBackend *blk, uint32_t sector_len, + int bank_width, + uint16_t id0, uint16_t id1, + uint16_t id2, uint16_t id3, + int be); PFlashCFI01 *pflash_cfi01_register(hwaddr base, const char *name, hwaddr size, -- 2.38.1 From MAILER-DAEMON Wed Jan 04 17:06:34 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBu5-0001Il-UK for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 17:06:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBtv-00019I-GU for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:06:23 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDBts-0005ca-7f for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:06:22 -0500 Received: by mail-ej1-x62f.google.com with SMTP id kw15so85845792ejc.10 for ; Wed, 04 Jan 2023 14:06:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; 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Wed, 04 Jan 2023 14:06:18 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id k22-20020a170906129600b007c10fe64c5dsm15736366ejb.86.2023.01.04.14.06.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Jan 2023 14:06:18 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 10/20] hw/arm: Open-code pflash_cfi01_register() Date: Wed, 4 Jan 2023 23:04:39 +0100 Message-Id: <20230104220449.41337-11-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:06:23 -0000 pflash_cfi01_register() hides an implicit sysbus mapping of MMIO region #0. This is not practical in a heterogeneous world where multiple cores use different address spaces. In order to remove to remove pflash_cfi01_register() from the pflash API, open-code it as a qdev creation call followed by an explicit sysbus mapping. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/collie.c | 15 +++++++++------ hw/arm/gumstix.c | 19 +++++++++++++------ hw/arm/mainstone.c | 13 ++++++++----- hw/arm/omap_sx1.c | 22 ++++++++++++++-------- hw/arm/versatilepb.c | 13 ++++++++----- hw/arm/z2.c | 10 +++++++--- 6 files changed, 59 insertions(+), 33 deletions(-) diff --git a/hw/arm/collie.c b/hw/arm/collie.c index 8df31e2793..1fbb1a5773 100644 --- a/hw/arm/collie.c +++ b/hw/arm/collie.c @@ -39,6 +39,7 @@ static void collie_init(MachineState *machine) DriveInfo *dinfo; MachineClass *mc = MACHINE_GET_CLASS(machine); CollieMachineState *cms = COLLIE_MACHINE(machine); + DeviceState *dev; if (machine->ram_size != mc->default_ram_size) { char *sz = size_to_str(mc->default_ram_size); @@ -52,14 +53,16 @@ static void collie_init(MachineState *machine) memory_region_add_subregion(get_system_memory(), SA_SDCS0, machine->ram); dinfo = drive_get(IF_PFLASH, 0, 0); - pflash_cfi01_register(SA_CS0, "collie.fl1", 0x02000000, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - 64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0); + dev = pflash_cfi01_create("collie.fl1", 0x02000000, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + 64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, SA_CS0); dinfo = drive_get(IF_PFLASH, 0, 1); - pflash_cfi01_register(SA_CS1, "collie.fl2", 0x02000000, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - 64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0); + dev = pflash_cfi01_create("collie.fl2", 0x02000000, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + 64 * KiB, 4, 0x00, 0x00, 0x00, 0x00, 0); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, SA_CS1); sysbus_create_simple("scoop", 0x40800000, NULL); diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c index 3a4bc332c4..7b80a7d0a4 100644 --- a/hw/arm/gumstix.c +++ b/hw/arm/gumstix.c @@ -40,6 +40,7 @@ #include "net/net.h" #include "hw/block/flash.h" #include "hw/net/smc91c111.h" +#include "hw/sysbus.h" #include "hw/boards.h" #include "exec/address-spaces.h" #include "sysemu/qtest.h" @@ -51,6 +52,7 @@ static void connex_init(MachineState *machine) { PXA2xxState *cpu; DriveInfo *dinfo; + DeviceState *dev; MemoryRegion *address_space_mem = get_system_memory(); uint32_t connex_rom = 0x01000000; @@ -65,12 +67,14 @@ static void connex_init(MachineState *machine) exit(1); } - if (!pflash_cfi01_register(0x00000000, "connext.rom", connex_rom, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - sector_len, 2, 0, 0, 0, 0, 0)) { + dev = pflash_cfi01_create("connext.rom", connex_rom, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + sector_len, 2, 0, 0, 0, 0, 0); + if (!dev) { error_report("Error registering flash memory"); exit(1); } + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x00000000); /* Interrupt line of NIC is connected to GPIO line 36 */ smc91c111_init(&nd_table[0], 0x04000300, @@ -81,6 +85,7 @@ static void verdex_init(MachineState *machine) { PXA2xxState *cpu; DriveInfo *dinfo; + DeviceState *dev; MemoryRegion *address_space_mem = get_system_memory(); uint32_t verdex_rom = 0x02000000; @@ -95,12 +100,14 @@ static void verdex_init(MachineState *machine) exit(1); } - if (!pflash_cfi01_register(0x00000000, "verdex.rom", verdex_rom, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - sector_len, 2, 0, 0, 0, 0, 0)) { + dev = pflash_cfi01_create("verdex.rom", verdex_rom, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + sector_len, 2, 0, 0, 0, 0, 0); + if (!dev) { error_report("Error registering flash memory"); exit(1); } + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x00000000); /* Interrupt line of NIC is connected to GPIO line 99 */ smc91c111_init(&nd_table[0], 0x04000300, diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c index 8454b65458..ac34be3709 100644 --- a/hw/arm/mainstone.c +++ b/hw/arm/mainstone.c @@ -129,15 +129,18 @@ static void mainstone_common_init(MemoryRegion *address_space_mem, /* There are two 32MiB flash devices on the board */ for (i = 0; i < 2; i ++) { + DeviceState *dev; + dinfo = drive_get(IF_PFLASH, 0, i); - if (!pflash_cfi01_register(mainstone_flash_base[i], - i ? "mainstone.flash1" : "mainstone.flash0", - MAINSTONE_FLASH, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - sector_len, 4, 0, 0, 0, 0, 0)) { + dev = pflash_cfi01_create(i ? "mainstone.flash1" : "mainstone.flash0", + MAINSTONE_FLASH, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + sector_len, 4, 0, 0, 0, 0, 0); + if (!dev) { error_report("Error registering flash memory"); exit(1); } + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, mainstone_flash_base[i]); } mst_irq = sysbus_create_simple("mainstone-fpga", MST_FPGA_PHYS, diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index 57829b3744..718e50c062 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -30,6 +30,7 @@ #include "ui/console.h" #include "hw/arm/omap.h" #include "hw/boards.h" +#include "hw/sysbus.h" #include "hw/arm/boot.h" #include "hw/block/flash.h" #include "sysemu/qtest.h" @@ -114,6 +115,7 @@ static void sx1_init(MachineState *machine, const int version) DriveInfo *dinfo; int fl_idx; uint32_t flash_size = flash0_size; + DeviceState *dev; if (machine->ram_size != mc->default_ram_size) { char *sz = size_to_str(mc->default_ram_size); @@ -153,10 +155,12 @@ static void sx1_init(MachineState *machine, const int version) fl_idx = 0; if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) { - if (!pflash_cfi01_register(OMAP_CS0_BASE, - "omap_sx1.flash0-1", flash_size, - blk_by_legacy_dinfo(dinfo), - sector_size, 4, 0, 0, 0, 0, 0)) { + dev = pflash_cfi01_create("omap_sx1.flash0-1", flash_size, + blk_by_legacy_dinfo(dinfo), + sector_size, 4, 0, 0, 0, 0, 0); + if (dev) { + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, OMAP_CS0_BASE); + } else { fprintf(stderr, "qemu: Error registering flash memory %d.\n", fl_idx); } @@ -175,10 +179,12 @@ static void sx1_init(MachineState *machine, const int version) memory_region_add_subregion(address_space, OMAP_CS1_BASE + flash1_size, &cs[1]); - if (!pflash_cfi01_register(OMAP_CS1_BASE, - "omap_sx1.flash1-1", flash1_size, - blk_by_legacy_dinfo(dinfo), - sector_size, 4, 0, 0, 0, 0, 0)) { + dev = pflash_cfi01_create("omap_sx1.flash1-1", flash1_size, + blk_by_legacy_dinfo(dinfo), + sector_size, 4, 0, 0, 0, 0, 0); + if (dev) { + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, OMAP_CS1_BASE); + } else { fprintf(stderr, "qemu: Error registering flash memory %d.\n", fl_idx); } diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index ecc1f6cf74..c5c7cf6dde 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -385,11 +385,14 @@ static void versatile_init(MachineState *machine, int board_id) /* 0x34000000 NOR Flash */ dinfo = drive_get(IF_PFLASH, 0, 0); - if (!pflash_cfi01_register(VERSATILE_FLASH_ADDR, "versatile.flash", - VERSATILE_FLASH_SIZE, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - VERSATILE_FLASH_SECT_SIZE, - 4, 0x0089, 0x0018, 0x0000, 0x0, 0)) { + dev = pflash_cfi01_create("versatile.flash", + VERSATILE_FLASH_SIZE, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + VERSATILE_FLASH_SECT_SIZE, + 4, 0x0089, 0x0018, 0x0000, 0x0, 0); + if (dev) { + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VERSATILE_FLASH_ADDR); + } else { fprintf(stderr, "qemu: Error registering flash memory.\n"); } diff --git a/hw/arm/z2.c b/hw/arm/z2.c index 9c1e876207..d28d75aa0f 100644 --- a/hw/arm/z2.c +++ b/hw/arm/z2.c @@ -18,6 +18,7 @@ #include "hw/irq.h" #include "hw/ssi/ssi.h" #include "migration/vmstate.h" +#include "hw/sysbus.h" #include "hw/boards.h" #include "hw/block/flash.h" #include "ui/console.h" @@ -306,17 +307,20 @@ static void z2_init(MachineState *machine) void *z2_lcd; I2CBus *bus; DeviceState *wm; + DeviceState *dev; /* Setup CPU & memory */ mpu = pxa270_init(address_space_mem, z2_binfo.ram_size, machine->cpu_type); dinfo = drive_get(IF_PFLASH, 0, 0); - if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - sector_len, 4, 0, 0, 0, 0, 0)) { + dev = pflash_cfi01_create("z2.flash0", Z2_FLASH_SIZE, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + sector_len, 4, 0, 0, 0, 0, 0); + if (!dev) { error_report("Error registering flash memory"); exit(1); } + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, Z2_FLASH_BASE); /* setup keypad */ pxa27x_register_keypad(mpu->kp, map, 0x100); -- 2.38.1 From MAILER-DAEMON Wed Jan 04 17:06:35 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBu6-0001LN-UK for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 17:06:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBu5-0001Hl-D1 for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:06:33 -0500 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDBtz-0005fT-MW for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:06:33 -0500 Received: by mail-ej1-x632.google.com with SMTP id ud5so86069447ejc.4 for ; Wed, 04 Jan 2023 14:06:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eRH2/Q6+taaY1C0mf1jUv5OrxulMB7iM/Sfo6HL2IVQ=; b=nEDbMFtYiuO1tEPpkdBXhy5oQT831LiUY2iJK+y3FXzANhPxIRXugZteugbGJtczIU wxk9hW2bT12/v8IrT5Z65Xkhd+ABeve3HRZ6aQeaw++II7ljORjep1OVHv6bURhYyF6U 2ljIr4BXQitZtVzV2B6tgLnF+lIAB1yCgrbobDTMZRoWQhDu1muauHwZg3ZVnMr78rAd t+GJa9IMINib8sQFgtLZBscBE/cKQxRSq5/+pueGDxdF8P8qIDcq3NZtYGgMJeqUzQbr QrThF7plmTpACKFaVtYnIhTP06J/IbOkPLPzOkG35qCT27eMLrHgoadrp6Vm0jFjKFx+ 2CMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eRH2/Q6+taaY1C0mf1jUv5OrxulMB7iM/Sfo6HL2IVQ=; b=GRAJ2lZ3lZQtSEUzBSl531U1yAVnxQtkIOlx53nJi/Rt52ORLnMbRdrVltpdXQasdh M6wbegrMQtBC/2GnP0RRyaKOYeHV/a2bDHLUWcstnBJU5nLsB00nT79T2UWQmrAJkQhi yny3kJ6Xk+dPvnvLpH6c3pW4PvS4WKRIuIkKiBv+q1b0l3C0EQbjTAPT6TRgz/catPYR nnRfFaXOZdaHCn6toRHYlI0BsKiw+EabyCZmmSmvjxw5BgINRHXcAWKlgmL+GWlxhEDw 2yRBZLhaosjVAEI8PZxVkWZseqSNgcS55OwJtq/Djc/g+Z9eDs3BzHRmyXcLTihrRfr6 /ycw== X-Gm-Message-State: AFqh2konx3JgkF7gnNi09NAMuuPyqD03v7rem8FhxHthHXMPPUJ5aVAE RvZbsrDp9a/awennpEPlFdQoqg== X-Google-Smtp-Source: AMrXdXvvA01RJqv8oimb3A41Jl9v5nfQM3M6y1vT9mQAXVPWc/Tif+z0vVOVkkealNwvS6JmLvFduQ== X-Received: by 2002:a17:907:3f9d:b0:7c1:1c4:5eaf with SMTP id hr29-20020a1709073f9d00b007c101c45eafmr60776998ejc.49.1672869986450; Wed, 04 Jan 2023 14:06:26 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id 10-20020a170906218a00b0073d796a1043sm15640103eju.123.2023.01.04.14.06.23 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Jan 2023 14:06:26 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 11/20] hw/microblaze: Open-code pflash_cfi01_register() Date: Wed, 4 Jan 2023 23:04:40 +0100 Message-Id: <20230104220449.41337-12-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:06:33 -0000 pflash_cfi01_register() hides an implicit sysbus mapping of MMIO region #0. This is not practical in a heterogeneous world where multiple cores use different address spaces. In order to remove to remove pflash_cfi01_register() from the pflash API, open-code it as a qdev creation call followed by an explicit sysbus mapping. Signed-off-by: Philippe Mathieu-Daudé --- hw/microblaze/petalogix_ml605_mmu.c | 8 ++++---- hw/microblaze/petalogix_s3adsp1800_mmu.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index a24fadddca..d5ff71218d 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -105,10 +105,10 @@ petalogix_ml605_init(MachineState *machine) dinfo = drive_get(IF_PFLASH, 0, 0); /* 5th parameter 2 means bank-width * 10th paremeter 0 means little-endian */ - pflash_cfi01_register(FLASH_BASEADDR, "petalogix_ml605.flash", FLASH_SIZE, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - 64 * KiB, 2, 0x89, 0x18, 0x0000, 0x0, 0); - + dev = pflash_cfi01_create("petalogix_ml605.flash", FLASH_SIZE, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + 64 * KiB, 2, 0x89, 0x18, 0x0000, 0x0, 0); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, FLASH_BASEADDR); dev = qdev_new("xlnx.xps-intc"); qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ); diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 9d959d1ad8..426ff1de93 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -84,10 +84,10 @@ petalogix_s3adsp1800_init(MachineState *machine) memory_region_add_subregion(sysmem, ddr_base, phys_ram); dinfo = drive_get(IF_PFLASH, 0, 0); - pflash_cfi01_register(FLASH_BASEADDR, - "petalogix_s3adsp1800.flash", FLASH_SIZE, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); + dev = pflash_cfi01_create("petalogix_s3adsp1800.flash", FLASH_SIZE, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, FLASH_BASEADDR); dev = qdev_new("xlnx.xps-intc"); qdev_prop_set_uint32(dev, "kind-of-intr", -- 2.38.1 From MAILER-DAEMON Wed Jan 04 17:06:41 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBuD-0001aM-JZ for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 17:06:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBuB-0001Vp-L4 for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:06:39 -0500 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDBu8-0005fU-66 for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:06:39 -0500 Received: by mail-ej1-x62d.google.com with SMTP id u9so86132128ejo.0 for ; Wed, 04 Jan 2023 14:06:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KN4KqLlugVC+0veh/qHwh2dos/FPn9LDhOhs/UvtQDw=; b=z1BU4aoIPYdDRqTnlx0V3zv0CD9t+NMAhobtS9j6dghWzkl+GBC3imIxlMpvEMyTyU lH9DINmyyjI0M06yICDcJ0uuJfyxGMn6C6buPS+HRN243d7qRriWbRLUs8VQGni7kkJ4 jsmxMl+qeS9DoEuv+rX6n/5MX7uVBrdRy33dmARiikb6K+I2xUVS44eVKFStxOZn7XQ4 4AWA5tW0P5HYeFms0rGALBKAVKOI4O/Hyvtl5b3KCEfAsaJB/O3NTHvs/bH5U18E1E7a TLhTQ95AueMkRyXyfe82e94wv8pwaHGl30G0WfbMv71x1G5BHTcLXi5SWwnRZOeDA9rh WpJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KN4KqLlugVC+0veh/qHwh2dos/FPn9LDhOhs/UvtQDw=; b=wukSoshJR5rqPWPkPGB4UKDBoZ9uW/3OJw1Kq0bCRmXu53xIywWjTLJvm+xUJu4qYU ddnr1LnHiZGcUeB8JJ9rWkuVZmXJz3qtFf9JsMquUc044Ca2hM4wPilKcWyMxuQkxJyi RTnRBJPBelweHIps6uvJuJ0ur8l2olKmp572n0xA0wwIVu42LdVKDiv9dxVKXWvMutNl B28UcEZaGu/33p6IM9WH6T5CcrRucYKBEGRuj0FVF5u08LM3dtZupVMEKpMhsBr8TeY3 oth9QUu0T6uWRz5xcVUe9hOginT4klSn6n4ZP7jer1Cbt3fqvgJnR0X0o4zkEbMQJAJh xnxQ== X-Gm-Message-State: AFqh2krqeucYp6cJrjAKcYBNzdCiOZW/g/F61kjH81PbB3XlO+6MZP+A Pj/pCbLDnoJY1dNrQpY4NZIKQg== X-Google-Smtp-Source: AMrXdXvMFX4IDRqLxsTznid+IJtag64ozPayTo6+BU6tYMCWpu4S/A12KD1SQSXRgAWs02blwKTeNA== X-Received: by 2002:a17:907:d387:b0:7c1:6fd3:1ef3 with SMTP id vh7-20020a170907d38700b007c16fd31ef3mr41602526ejc.33.1672869995411; Wed, 04 Jan 2023 14:06:35 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id co5-20020a0564020c0500b00483dd234ac6sm12958847edb.96.2023.01.04.14.06.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Jan 2023 14:06:35 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 12/20] hw/mips: Open-code pflash_cfi01_register() Date: Wed, 4 Jan 2023 23:04:41 +0100 Message-Id: <20230104220449.41337-13-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=philmd@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:06:40 -0000 pflash_cfi01_register() hides an implicit sysbus mapping of MMIO region #0. This is not practical in a heterogeneous world where multiple cores use different address spaces. In order to remove to remove pflash_cfi01_register() from the pflash API, open-code it as a qdev creation call followed by an explicit sysbus mapping. Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 43fbb97799..e690f13bdb 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -1222,7 +1222,6 @@ void mips_malta_init(MachineState *machine) const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; char *filename; - PFlashCFI01 *fl; MemoryRegion *system_memory = get_system_memory(); MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1); MemoryRegion *ram_low_postio; @@ -1286,12 +1285,11 @@ void mips_malta_init(MachineState *machine) /* Load firmware in flash / BIOS. */ dinfo = drive_get(IF_PFLASH, 0, fl_idx); - fl = pflash_cfi01_register(FLASH_ADDRESS, "mips_malta.bios", - FLASH_SIZE, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - 65536, - 4, 0x0000, 0x0000, 0x0000, 0x0000, be); - dev = DEVICE(fl); + dev = pflash_cfi01_create("mips_malta.bios", FLASH_SIZE, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + 65536, 4, + 0x0000, 0x0000, 0x0000, 0x0000, be); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, FLASH_ADDRESS); bios = pflash_cfi01_get_memory(dev); fl_idx++; if (kernel_filename) { -- 2.38.1 From MAILER-DAEMON Wed Jan 04 17:07:33 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBur-000235-GN for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 17:07:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBuJ-0001sO-J0 for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:06:58 -0500 Received: from mail-ej1-x633.google.com ([2a00:1450:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDBuH-0006Qq-B6 for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:06:47 -0500 Received: by mail-ej1-x633.google.com with SMTP id qk9so85784533ejc.3 for ; Wed, 04 Jan 2023 14:06:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zslv5ettm0BZ6lahZKOwlTaXvhF8s2DyuA1mWPRzCMs=; b=NxbffoqprVv6NlWkQCdargfgN3AeDlp6F+mpEaeWmQJ9ILjz/zFWD5ly8WRoPmkc71 4O6RFG8PVjxFBO+xcP/suLGBeAD8GRcijOfILkqzCTB7E6cA3TER+4DbOPaj3sWoPSbv cqWMRBmc4KN/9N54hPVhfJIbrWzAK3Rblemr4+XOAAPZn1po/drvH/LapmVhbEzcCDAc b/P6/+JMraod5BtNeBlYPXkLA0/atgTBPKFmzXC6BPYlBIIJLNWlIboPQ3bMaQ2Q4SpW R2IVQuu6WQAqZ8wkuTlLgqQFpMHS6GZ72Vce4/VGxWWf1Sl3j+Be2wV4njDWwcJxRfI+ 8Ubw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zslv5ettm0BZ6lahZKOwlTaXvhF8s2DyuA1mWPRzCMs=; b=jY56knFNhF9kVt7m72TC7ioWVVEjLImLaUA+SZiIXD+89cuk8n8sBDRShE6eQWpE7g RtE6mgxUEGL1BOKA+PO1fnGVct1PUY9H+G4/cm5NpiOvuQJCB/wfXkh0eJNW5lpLS2hO XCPBkuEG9VgDqu6c1fFCfzCTqWQjmyZXOUZiVOT6azKO2w5Z0alw5x8XtvYRGZ3AZY7Z Ay3R/LdiN59FkFckciNpFEm7q6hUlEV8wcQ57vUyTO4snwJ1cTK5II7s83Nj2zx55N5h 6RZvm5TAbD/aU4stlm/CrGKBQLdlvYdBaqA4+QwvVAWmp8q+Z06gGQkSgXZokD3H3+kt TjxA== X-Gm-Message-State: AFqh2kr4UaTV9fv8rPIrp6kAtpzk42GSfzMRGYiwKIy5dK78JZspZUoe c77ore2g0XywcQ4yEtCxPZ+ClQ== X-Google-Smtp-Source: AMrXdXtnKaw3mdJpb/NCzwKmXotk21jsO6EmRs6LLpgJgj2NT5YQutKoFUcGi80d2lpWO8uBFYeyJg== X-Received: by 2002:a17:906:700f:b0:7c0:b79c:7d5f with SMTP id n15-20020a170906700f00b007c0b79c7d5fmr55349078ejj.68.1672870004011; Wed, 04 Jan 2023 14:06:44 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id hz8-20020a1709072ce800b007b839689adesm15807413ejc.166.2023.01.04.14.06.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Jan 2023 14:06:43 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 13/20] hw/ppc: Open-code pflash_cfi01_register() Date: Wed, 4 Jan 2023 23:04:42 +0100 Message-Id: <20230104220449.41337-14-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=philmd@linaro.org; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:07:10 -0000 pflash_cfi01_register() hides an implicit sysbus mapping of MMIO region #0. This is not practical in a heterogeneous world where multiple cores use different address spaces. In order to remove to remove pflash_cfi01_register() from the pflash API, open-code it as a qdev creation call followed by an explicit sysbus mapping. Signed-off-by: Philippe Mathieu-Daudé --- hw/ppc/sam460ex.c | 12 ++++++++---- hw/ppc/virtex_ml507.c | 7 ++++--- 2 files changed, 12 insertions(+), 7 deletions(-) diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 4a22ce3761..a82c9e0642 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -82,6 +82,8 @@ struct boot_info { static int sam460ex_load_uboot(void) { + DeviceState *dev; + /* * This first creates 1MiB of flash memory mapped at the end of * the 32-bit address space (0xFFF00000..0xFFFFFFFF). @@ -103,14 +105,16 @@ static int sam460ex_load_uboot(void) DriveInfo *dinfo; dinfo = drive_get(IF_PFLASH, 0, 0); - if (!pflash_cfi01_register(FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32), - "sam460ex.flash", FLASH_SIZE, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1)) { + dev = pflash_cfi01_create("sam460ex.flash", FLASH_SIZE, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); + if (!dev) { error_report("Error registering flash memory"); /* XXX: return an error instead? */ exit(1); } + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, + FLASH_BASE | ((hwaddr)FLASH_BASE_H << 32)); if (!dinfo) { /*error_report("No flash image given with the 'pflash' parameter," diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index f2f81bd425..ee211664a8 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -233,9 +233,10 @@ static void virtex_init(MachineState *machine) memory_region_add_subregion(address_space_mem, ram_base, machine->ram); dinfo = drive_get(IF_PFLASH, 0, 0); - pflash_cfi01_register(PFLASH_BASEADDR, "virtex.flash", FLASH_SIZE, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); + dev = pflash_cfi01_create("virtex.flash", FLASH_SIZE, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + 64 * KiB, 1, 0x89, 0x18, 0x0000, 0x0, 1); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, PFLASH_BASEADDR); cpu_irq = qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT); dev = qdev_new("xlnx.xps-intc"); -- 2.38.1 From MAILER-DAEMON Wed Jan 04 17:07:43 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBvD-0002CL-Cu for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 17:07:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBun-0001zf-Rn for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:07:19 -0500 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDBuf-0005ax-5Z for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:07:12 -0500 Received: by mail-ej1-x62e.google.com with SMTP id m18so85788417eji.5 for ; Wed, 04 Jan 2023 14:07:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aSPCaBssOqcI16x2eeMpiNddAyoEtVRJPGPKXdjNpIQ=; b=aCZaH0vh5oj1E5E4InNiTNoAmKmy+457xeL73gS5nxOTrGV20hoWJXGVDlyusBzKe2 8pfl7iNSDuNn54XFnBajK1L5Qg8oUqJEN4fba74ENRvxdJ0DnKUsoWCE5dwKz2e1SJzg 10qmJeWfd8vmN4s3mqMMfnHSHhWx4M4ukd0MCYh7eTCGf80Nv5HrHD/fqmRAJAALfS5m 6IBpYTuRvgSWTp5S6+e/DT1jTZYAsCMns9oWvoQl16iKXNATL0ej2vQdPpIAplKG/3qd hl2z9qeh9oLUjGVjbkn8g2ZX05MMFG0+FavRmbzVZpikeaafVImNvPdEoGJ1GojPfYhH TOxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aSPCaBssOqcI16x2eeMpiNddAyoEtVRJPGPKXdjNpIQ=; b=qHtw9PIe8NHAaUtaX0qGIM/xuVPXPo3RsVhH3Z4BJVwpwfDKmZeQbt2XaWFfesP/6e VE7I9kX2L5Fhsn4tdT8q+t2qA+maAr0XF/fCWmj8gYoQDpfPFycwRsdMvwfjEu5Skbq9 EIWZhJoalCL29mZLCRaVoZiZ95oHe91d+an43PzX3luUND2nHQf8j5FHoOA/jlb2l/6v bjcnKcorwDUc0zDwMkOZIoaKKTEMMZU3QXJ2CzAVQ1A3NjPGG98zfvWl29EzYGZnsqxK vtCVTn5x+4gAk8R2BleXRYGajxN9zzN6WxuCTM9bwXalZYlR+PL7ZJy4eCzJYK4MtxlT yWrQ== X-Gm-Message-State: AFqh2kryzCphw/QDhOUvoYRqHtF6npffayuZXjiTas2g8WGXayhjLc1O RQJ6MicXPUE3o4Sr7rQRj0bA1g== X-Google-Smtp-Source: AMrXdXu0qfsSlm3Zih88aaQ/o6QEwPEpyma1jJ5BVEasDZz0Sqa8vAIckF3WveKZEJhRf68EYXsQag== X-Received: by 2002:a17:906:279a:b0:7c1:10b4:4742 with SMTP id j26-20020a170906279a00b007c110b44742mr40854672ejc.55.1672870021716; Wed, 04 Jan 2023 14:07:01 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id j2-20020a17090623e200b007add62dafbasm15551057ejg.157.2023.01.04.14.06.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Jan 2023 14:07:01 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 15/20] hw/block: Make PFlashCFI01 QOM declaration internal Date: Wed, 4 Jan 2023 23:04:44 +0100 Message-Id: <20230104220449.41337-16-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=philmd@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:07:20 -0000 Convert the QOM PFlashCFI01 to a forward/opaque pointer declaration. Only pflash_cfi01.c is able to poke at the internal fields. Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi01.c | 2 ++ include/hw/block/flash.h | 1 - 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 9df79b102b..2af9273fc1 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -59,6 +59,8 @@ #define PFLASH_BE 0 #define PFLASH_SECURE 1 +OBJECT_DECLARE_SIMPLE_TYPE(PFlashCFI01, PFLASH_CFI01) + struct PFlashCFI01 { /*< private >*/ SysBusDevice parent_obj; diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h index 858c0a1b6e..321aede8ef 100644 --- a/include/hw/block/flash.h +++ b/include/hw/block/flash.h @@ -9,7 +9,6 @@ /* pflash_cfi01.c */ #define TYPE_PFLASH_CFI01 "cfi.pflash01" -OBJECT_DECLARE_SIMPLE_TYPE(PFlashCFI01, PFLASH_CFI01) /** * Create and realize a parallel NOR flash (CFI type 1) on the heap. -- 2.38.1 From MAILER-DAEMON Wed Jan 04 17:08:05 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBvT-0002Gl-LU for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 17:08:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBuU-0001u7-8c for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:07:08 -0500 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDBuP-0005fU-Nw for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:06:56 -0500 Received: by mail-ej1-x62d.google.com with SMTP id u9so86133519ejo.0 for ; Wed, 04 Jan 2023 14:06:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/hYs50GwFMyuZfrImrAOFNvNLwGPKhd/4T6LtSg8+5M=; b=Qz7J1AazlyA7TkFmTghpBG/6vJrDSWHKbTwtiuGnzqK7ApC9+o8bNw/7/IJHgXWR3i YCLat9y+G6p6U4z1Kpg2pjsXWAofMcNf3VPViZbRDRonu5xtJoH7vehTtKxZ0iysg2TV 51nDPAhZ369/CvCFhA1wrvQLQfHE9hyi5sctpKzmJYmKPNY96QunXQUKqfNlp57ltjBX 04W3bCtp83zOPi5x/zPahdwrU1muZojnmnjz7kMhBE1Hlc9YWFGeqdUQcSxcY8J47jdI nJRQ55pvpqcBB3BqRDsxXwLv5GE5q6uWw1t37TvG/snnGG2Wc7Z7otNQf7Em3zPKfU+D xp9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/hYs50GwFMyuZfrImrAOFNvNLwGPKhd/4T6LtSg8+5M=; b=umRpqe4Lyw2aymogn2jd/uToCGl/eNnzyw2DK8Y9bfehBEYrzZ2/8jBrGXmo1JIWE3 515SuWtm5QNxmC0L2jm7YRFR6ymTNAh/EfrLdfNf7C5v0Wy3s2ebP3Ca9DJIZ56+qjCG wir3xX4ulQA2p3eZqzwpmR73OqHxaQVq12ZpS4TagQP5doinlbc47A4muFC+jYT6yI5S ECZVaRHAS2urZwMfRGL3pomQrzh7a/YYePhuNztg46EZAt+DfSv0KA5F5eR6GUd4pPHx vH6rL4esKY1UB5nEJvbbNgF55oRwoRCawpwTfbfrpF4A+bK3rGUypODhWa+sXb35NlCg r8/Q== X-Gm-Message-State: AFqh2kpt7NmcSXI1N6YJ84avH8mWFc1wRx74l3wylamVPBZDXKa8eCvP Zj96bsgYmXSoC7J+ce4MYhkfdg== X-Google-Smtp-Source: AMrXdXvEPyGP9Y3MjxA2zCJwlhAlOPOZDd4IP/hCV2z6pgb093o79PN1kYPD/lVfIFU8jTnGwHbepg== X-Received: by 2002:a17:907:908b:b0:846:cdd9:d28 with SMTP id ge11-20020a170907908b00b00846cdd90d28mr32353056ejb.30.1672870011907; Wed, 04 Jan 2023 14:06:51 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id hb1-20020a170906b88100b0078d9b967962sm15694423ejb.65.2023.01.04.14.06.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Jan 2023 14:06:51 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 14/20] hw/block: Remove unused pflash_cfi01_register() Date: Wed, 4 Jan 2023 23:04:43 +0100 Message-Id: <20230104220449.41337-15-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=philmd@linaro.org; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:07:11 -0000 We converted all caller of pflash_cfi01_register() by open coding a call to pflash_cfi01_create() followed by an explicit call to sysbus_mmio_map(); we can now remove it. Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi01.c | 19 ------------------- include/hw/block/flash.h | 9 --------- 2 files changed, 28 deletions(-) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 6a8f9e6319..9df79b102b 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -981,25 +981,6 @@ DeviceState *pflash_cfi01_create(const char *name, return dev; } -PFlashCFI01 *pflash_cfi01_register(hwaddr base, - const char *name, - hwaddr size, - BlockBackend *blk, - uint32_t sector_len, - int bank_width, - uint16_t id0, uint16_t id1, - uint16_t id2, uint16_t id3, - int be) -{ - DeviceState *dev; - - dev = pflash_cfi01_create(name, size, blk, sector_len, bank_width, - id0, id1, id2, id3, be); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); - - return PFLASH_CFI01(dev); -} - BlockBackend *pflash_cfi01_get_blk(DeviceState *dev) { PFlashCFI01 *fl = PFLASH_CFI01(dev); diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h index 40ba857f69..858c0a1b6e 100644 --- a/include/hw/block/flash.h +++ b/include/hw/block/flash.h @@ -24,15 +24,6 @@ DeviceState *pflash_cfi01_create(const char *name, uint16_t id0, uint16_t id1, uint16_t id2, uint16_t id3, int be); -PFlashCFI01 *pflash_cfi01_register(hwaddr base, - const char *name, - hwaddr size, - BlockBackend *blk, - uint32_t sector_len, - int width, - uint16_t id0, uint16_t id1, - uint16_t id2, uint16_t id3, - int be); BlockBackend *pflash_cfi01_get_blk(DeviceState *dev); MemoryRegion *pflash_cfi01_get_memory(DeviceState *dev); void pflash_cfi01_legacy_drive(DeviceState *dev, DriveInfo *dinfo); -- 2.38.1 From MAILER-DAEMON Wed Jan 04 17:08:09 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBvd-0002Om-CC for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 17:08:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBus-00023i-06 for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:07:31 -0500 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDBun-0008L6-MT for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:07:21 -0500 Received: by mail-ej1-x635.google.com with SMTP id jo4so86004901ejb.7 for ; Wed, 04 Jan 2023 14:07:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c0SPEwXyflkiw42kdbQzUDTcTHzybkAd3cMquverKqA=; b=iQ8Bfh7ypySwtQudVdpmBFo9jAOECouo6v0Mm2PY8M8ncwvAFnh0Z64MiQzv8j3lfd InWICNpqEmN/un1I+jJEL4aBPj9w/WhIYmJcvSi5Jszhlvl6oINXPlhD6JFWwiT1uawz aDTiXb3hxPztUbUMNZ8MGoUdL3Y2s5jQ8VsOsguUkxqpqe5x64z2jkrYimbuNQee1iuT HiqJueIznICGSdND3aEIK7vgz3jFjolaThFq8Lspo5tcviRDOvTVDaCGgSvL/LaOLFiz 3D2LZliMP+FpUTdTrBgiUO8J5TBHgRnCNTlOkaNcwFWaWY4aH15pg4fIBVsgZ/tgnNRC Th2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c0SPEwXyflkiw42kdbQzUDTcTHzybkAd3cMquverKqA=; b=uMtlxYqG2RsrUM2oXFLIqbriqXGNjY8UvRKT5TaZtH/iyAyWc4grpVpBGrMWhw30ye vYTMidlRFTe1uMA8GtBbB+CiTc6BkdHD6HcN9psJKPgQsKmMP0A37cf3GM+ucLHUg4Lb 7AtXeo7HNX3buzsGgs2HsmIo8wHY6o7IbRD5aJhzlZ1JDG2wPHh0unG8uNRB8LN8FR3q 5Dq7y3dCg2ilpBmKeeNiy8oUlRAV/9bFuWGXVwPXMDAibQ8U+n/2dflrdzj9IaCBsjPe bwQG4vUj2p72q0sSAEsB6woyzho7g6rxacToXjzFYVNNJ+QC9JLVh+uNB/COXAPD3BNv Dv+Q== X-Gm-Message-State: AFqh2koSdq+UK6zQVHBmnmDWr122FBtiLzes06U0iv52UrwmTJpgSHOL dskc40zNfEIeV4J8IZ2sXgOyFw== X-Google-Smtp-Source: AMrXdXuCq8Ftiv/kwTi77XpdmKSYh3K8X1mFkJsRvhMLrg6SAEkVwoXoTP8mAK74ujVXhfCq64oCvA== X-Received: by 2002:a17:907:86a6:b0:7c0:fd1a:79f0 with SMTP id qa38-20020a17090786a600b007c0fd1a79f0mr59298049ejc.21.1672870030224; Wed, 04 Jan 2023 14:07:10 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id h14-20020a1709063c0e00b00780b1979adesm15773759ejg.218.2023.01.04.14.07.06 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Jan 2023 14:07:09 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 16/20] hw/block: Factor pflash_cfi02_create() out of pflash_cfi02_register() Date: Wed, 4 Jan 2023 23:04:45 +0100 Message-Id: <20230104220449.41337-17-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=philmd@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:07:33 -0000 Currently pflash_cfi02_register(): 1/ creates a TYPE_PFLASH_CFI02 qdev instance 2/ maps the first MMIO region to the system bus The first minor issue is the implicit sysbus mapping is not obvious (the function name could mention it), and the function is not documented. Another issue is we are forced to map on sysbus, thus code wanting to simply instantiate this device are forced to open code the qdev creation. This is a problem in a heterogeneous system where not all cores has access to the sysbus, or if we want to map the pflash on different address spaces. To clarify this API, extract the qdev creation in a new helper named pflash_cfi02_create(). We don't document pflash_cfi02_register() because we are going to remove it in a pair of commits. Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi02.c | 55 ++++++++++++++++++++++++++-------------- include/hw/block/flash.h | 14 +++++++++- 2 files changed, 49 insertions(+), 20 deletions(-) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index 2a99b286b0..176f93b512 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -994,6 +994,37 @@ static void pflash_cfi02_register_types(void) type_init(pflash_cfi02_register_types) +DeviceState *pflash_cfi02_create(const char *name, hwaddr size, + BlockBackend *blk, uint32_t sector_len, + int nb_mappings, int bank_width, + uint16_t id0, uint16_t id1, + uint16_t id2, uint16_t id3, + uint16_t unlock_addr0, uint16_t unlock_addr1, + int be) +{ + DeviceState *dev = qdev_new(TYPE_PFLASH_CFI02); + + if (blk) { + qdev_prop_set_drive(dev, "drive", blk); + } + assert(QEMU_IS_ALIGNED(size, sector_len)); + qdev_prop_set_uint32(dev, "num-blocks", size / sector_len); + qdev_prop_set_uint32(dev, "sector-length", sector_len); + qdev_prop_set_uint8(dev, "width", bank_width); + qdev_prop_set_uint8(dev, "mappings", nb_mappings); + qdev_prop_set_uint8(dev, "big-endian", !!be); + qdev_prop_set_uint16(dev, "id0", id0); + qdev_prop_set_uint16(dev, "id1", id1); + qdev_prop_set_uint16(dev, "id2", id2); + qdev_prop_set_uint16(dev, "id3", id3); + qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0); + qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1); + qdev_prop_set_string(dev, "name", name); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + return dev; +} + PFlashCFI02 *pflash_cfi02_register(hwaddr base, const char *name, hwaddr size, @@ -1006,26 +1037,12 @@ PFlashCFI02 *pflash_cfi02_register(hwaddr base, uint16_t unlock_addr1, int be) { - DeviceState *dev = qdev_new(TYPE_PFLASH_CFI02); - - if (blk) { - qdev_prop_set_drive(dev, "drive", blk); - } - assert(QEMU_IS_ALIGNED(size, sector_len)); - qdev_prop_set_uint32(dev, "num-blocks", size / sector_len); - qdev_prop_set_uint32(dev, "sector-length", sector_len); - qdev_prop_set_uint8(dev, "width", width); - qdev_prop_set_uint8(dev, "mappings", nb_mappings); - qdev_prop_set_uint8(dev, "big-endian", !!be); - qdev_prop_set_uint16(dev, "id0", id0); - qdev_prop_set_uint16(dev, "id1", id1); - qdev_prop_set_uint16(dev, "id2", id2); - qdev_prop_set_uint16(dev, "id3", id3); - qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0); - qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1); - qdev_prop_set_string(dev, "name", name); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + DeviceState *dev; + dev = pflash_cfi02_create(name, size, blk, sector_len, + nb_mappings, width, id0, id1, id2, id3, + unlock_addr0, unlock_addr1, be); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); + return PFLASH_CFI02(dev); } diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h index 321aede8ef..78b078955e 100644 --- a/include/hw/block/flash.h +++ b/include/hw/block/flash.h @@ -32,7 +32,19 @@ void pflash_cfi01_legacy_drive(DeviceState *dev, DriveInfo *dinfo); #define TYPE_PFLASH_CFI02 "cfi.pflash02" OBJECT_DECLARE_SIMPLE_TYPE(PFlashCFI02, PFLASH_CFI02) - +/** + * Create and realize a parallel NOR flash (CFI type 2) on the heap. + * + * Create the device state structure, initialize it, and drop the + * reference to it (the device is realized). + */ +DeviceState *pflash_cfi02_create(const char *name, hwaddr size, + BlockBackend *blk, uint32_t sector_len, + int nb_mappings, int bank_width, + uint16_t id0, uint16_t id1, + uint16_t id2, uint16_t id3, + uint16_t unlock_addr0, uint16_t unlock_addr1, + int be); PFlashCFI02 *pflash_cfi02_register(hwaddr base, const char *name, hwaddr size, -- 2.38.1 From MAILER-DAEMON Wed Jan 04 17:08:09 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBvd-0002PR-J5 for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 17:08:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBut-00023r-D7 for qemu-riscv@nongnu.org; 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Wed, 04 Jan 2023 14:07:18 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 17/20] hw/arm: Open-code pflash_cfi02_register() Date: Wed, 4 Jan 2023 23:04:46 +0100 Message-Id: <20230104220449.41337-18-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=philmd@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:07:33 -0000 pflash_cfi02_register() hides an implicit sysbus mapping of MMIO region #0. This is not practical in a heterogeneous world where multiple cores use different address spaces. In order to remove to remove pflash_cfi02_register() from the pflash API, open-code it as a qdev creation call followed by an explicit sysbus mapping. Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/digic_boards.c | 14 ++++++++------ hw/arm/musicpal.c | 13 +++++++------ hw/arm/xilinx_zynq.c | 10 +++++----- 3 files changed, 20 insertions(+), 17 deletions(-) diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index 4093af09cb..98b0002d16 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -115,13 +115,15 @@ static void digic4_add_k8p3215uqb_rom(DigicState *s, hwaddr addr, { #define FLASH_K8P3215UQB_SIZE (4 * 1024 * 1024) #define FLASH_K8P3215UQB_SECTOR_SIZE (64 * 1024) + DeviceState *dev; - pflash_cfi02_register(addr, "pflash", FLASH_K8P3215UQB_SIZE, - NULL, FLASH_K8P3215UQB_SECTOR_SIZE, - DIGIC4_ROM_MAX_SIZE / FLASH_K8P3215UQB_SIZE, - 4, - 0x00EC, 0x007E, 0x0003, 0x0001, - 0x0555, 0x2aa, 0); + dev = pflash_cfi02_create("pflash", FLASH_K8P3215UQB_SIZE, + NULL, FLASH_K8P3215UQB_SECTOR_SIZE, + DIGIC4_ROM_MAX_SIZE / FLASH_K8P3215UQB_SIZE, + 4, + 0x00EC, 0x007E, 0x0003, 0x0001, + 0x0555, 0x2aa, 0); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); digic_load_rom(s, addr, FLASH_K8P3215UQB_SIZE, filename); } diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index b65c020115..9f75d69b7f 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -1275,12 +1275,13 @@ static void musicpal_init(MachineState *machine) * 0xFF800000 (if there is 8 MB flash). So remap flash access if the * image is smaller than 32 MB. */ - pflash_cfi02_register(0x100000000ULL - MP_FLASH_SIZE_MAX, - "musicpal.flash", flash_size, - blk, 0x10000, - MP_FLASH_SIZE_MAX / flash_size, - 2, 0x00BF, 0x236D, 0x0000, 0x0000, - 0x5555, 0x2AAA, 0); + dev = pflash_cfi02_create("musicpal.flash", flash_size, + blk, 0x10000, + MP_FLASH_SIZE_MAX / flash_size, + 2, 0x00BF, 0x236D, 0x0000, 0x0000, + 0x5555, 0x2AAA, 0); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, + 0x100000000ULL - MP_FLASH_SIZE_MAX); } sysbus_create_simple(TYPE_MV88W8618_FLASHCFG, MP_FLASHCFG_BASE, NULL); diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 3190cc0b8d..e55aff5532 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -218,11 +218,11 @@ static void zynq_init(MachineState *machine) DriveInfo *dinfo = drive_get(IF_PFLASH, 0, 0); /* AMD */ - pflash_cfi02_register(0xe2000000, "zynq.pflash", FLASH_SIZE, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - FLASH_SECTOR_SIZE, 1, - 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, - 0); + dev = pflash_cfi02_create("zynq.pflash", FLASH_SIZE, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + FLASH_SECTOR_SIZE, 1, 1, + 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, 0); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xe2000000); /* Create the main clock source, and feed slcr with it */ zynq_machine->ps_clk = CLOCK(object_new(TYPE_CLOCK)); -- 2.38.1 From MAILER-DAEMON Wed Jan 04 17:08:10 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBvd-0002QK-Qj for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 17:08:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBvC-0002B0-Nf for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:07:42 -0500 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDBv9-0000Le-Kd for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:07:42 -0500 Received: by mail-ej1-x635.google.com with SMTP id qk9so85788917ejc.3 for ; Wed, 04 Jan 2023 14:07:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1aa33f3a7n9BSTQqA7U/LbCvTvRWLOt7Nts6p8HXsEU=; b=HF8qRByTAVk8VS2Xa8Bogk8aJuJWs1R6Jucp9qhx2tprzLDSWbbvnoJYLiy9Oz3x7E qdkFnt5GpbXnBAAQvXgn/Ydp0wxSxRK8V0vfeGZtXQoWyrDqlEHRQpfKv3uGm69LEhMF uEIh95xePAgB91KA5Jc3djKwW4tGt068OiKwrxJIBG2PfdtYsLrbhUdJCVIDlztQz9/m 8u7ZC9EBr5AQYvvYsAhmhORW87fYg9g+HPLbkHIhlO2adM3HgvU1gqhyEwMqLM0jG+Xr XYR+ijDKJVJMDF5sC0HZHQzTVGetnjIvIoZBSXWgP3aUBZ5LgoYLmzGt4C9Y3lL7bQXO YUYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1aa33f3a7n9BSTQqA7U/LbCvTvRWLOt7Nts6p8HXsEU=; b=OIrgEGNJosWqpm+7r66/QgvIiIK7ks1VEnYmh2dY2NbRJS077EzOIRBJ9V761tkeBp CnsSUdCc5mJKF2ussSdXbg07GY8gjMWNgkiWDsDL0aAZ4gqN3gsrp4Oajmpz1l6wUvMq 0UwV/Y1iDYSohJDS/Ra9srEb558mzaTk/0DENtaZRZ4ZZnS3In68Ccql2Goc9miOsWHv o9Bh6rErRscK1R/0WZR/Ay/D9if+Xg73xh0ZUz9FEG5F0pgE7Gl1aUL1ueoUC/Q/5k0H D7dV5KN7gPaVTpyjo8GqAikhV/4cwTte4065FTv23KsM9o1nokdSN7auwH0jIFrjfqgB M+rQ== X-Gm-Message-State: AFqh2koru1awtj6v+qGbcWPLUdQL/2Z/CWMd7A1TxJKo7iQyHdpiIZhM /ea6BZ937O0+rS2XiiNMg8+qoA== X-Google-Smtp-Source: AMrXdXuggiq8Uz7L/duNqOAgZ/VTLKuh0RN8DCz6J5ifs76v3BLgG/8TypnZIqcASxUNSc1bdjge/Q== X-Received: by 2002:a17:907:8b98:b0:840:a6a3:41c7 with SMTP id tb24-20020a1709078b9800b00840a6a341c7mr44366000ejc.50.1672870057438; Wed, 04 Jan 2023 14:07:37 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id f11-20020a17090631cb00b0084c465709b7sm12959809ejf.74.2023.01.04.14.07.32 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Jan 2023 14:07:37 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 19/20] hw/block: Remove unused pflash_cfi02_register() Date: Wed, 4 Jan 2023 23:04:48 +0100 Message-Id: <20230104220449.41337-20-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=philmd@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:07:43 -0000 We converted all caller of pflash_cfi02_register() by open coding a call to pflash_cfi02_create() followed by an explicit call to sysbus_mmio_map(); we can now remove it. Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi02.c | 22 ---------------------- include/hw/block/flash.h | 12 ------------ 2 files changed, 34 deletions(-) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index 176f93b512..a9dcabdeb2 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -1024,25 +1024,3 @@ DeviceState *pflash_cfi02_create(const char *name, hwaddr size, return dev; } - -PFlashCFI02 *pflash_cfi02_register(hwaddr base, - const char *name, - hwaddr size, - BlockBackend *blk, - uint32_t sector_len, - int nb_mappings, int width, - uint16_t id0, uint16_t id1, - uint16_t id2, uint16_t id3, - uint16_t unlock_addr0, - uint16_t unlock_addr1, - int be) -{ - DeviceState *dev; - - dev = pflash_cfi02_create(name, size, blk, sector_len, - nb_mappings, width, id0, id1, id2, id3, - unlock_addr0, unlock_addr1, be); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); - - return PFLASH_CFI02(dev); -} diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h index 78b078955e..64ee40c561 100644 --- a/include/hw/block/flash.h +++ b/include/hw/block/flash.h @@ -45,18 +45,6 @@ DeviceState *pflash_cfi02_create(const char *name, hwaddr size, uint16_t id2, uint16_t id3, uint16_t unlock_addr0, uint16_t unlock_addr1, int be); -PFlashCFI02 *pflash_cfi02_register(hwaddr base, - const char *name, - hwaddr size, - BlockBackend *blk, - uint32_t sector_len, - int nb_mappings, - int width, - uint16_t id0, uint16_t id1, - uint16_t id2, uint16_t id3, - uint16_t unlock_addr0, - uint16_t unlock_addr1, - int be); /* nand.c */ DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id); -- 2.38.1 From MAILER-DAEMON Wed Jan 04 17:08:10 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBve-0002Sg-HM for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 17:08:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBv1-00025J-TE for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:07:33 -0500 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDBuy-0008L6-Ej for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:07:31 -0500 Received: by mail-ej1-x635.google.com with SMTP id jo4so86006395ejb.7 for ; Wed, 04 Jan 2023 14:07:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wmavs6sB32iuk0P3966mjPd+ATivEhkJqHU5LgWaQJM=; b=ZTzMbgFdAqNU+m8VRz2s+o2Vz5VeZXQ51dVr6ermRNbcO2+233UkuOZmWsdCFLihOs v0NXw4mi10RJSrjJCmmKxb8/gYg3P0mXfq+NxcpORte0pdXovaS3JVTJ25t2rLUFUfk+ mZX0m/TGcZbfZPvUip8vtzJqd8G7akAuh02cbjT1OvyfQHZHZIWsR6PbB1EW0xr+rkx+ h5m7sRBLJwiWrXIUApTFMu5D6mBbZLvYsgc22QA34RcoAddm/pQRR7S83oTSA+ZQ4osy l5slett8vvp+vKJfZK2xGrBj7EpdFGvAzv/RxR0lhebPGF/AaOHVI4mj0xNqryqEHtjI RLUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wmavs6sB32iuk0P3966mjPd+ATivEhkJqHU5LgWaQJM=; b=pMObk+Csw5DlDz4HVAkBOGB4aNkRl/xBOJwFUnQOZjq617napNBXIyii4rBMBZEg8h SK4KIj0Lo6VTe9PXSqspH0bjklPNUOwTncfFLtGmNGVbygZ0HgPunNyQyttLtBL57ZgL NvqVyjGopAV7eX8PaQmtK0BrCxVbDzxDEAkMVSsOesnCLamBa7WzZ5SQrJeEEbHCxNd2 wPsQReCH/qHQ50xf+vqW8vM8me2uQMsgwEXeHqZoSl4zYnho/KkmDZ4kgn11H6FUaijm yM1wVNjaZJ0rPa4iql8rYtUGaUIu8SacFoRMXWeaXomQwY6zOfKxD8V0lSdwY6gKCuRX c8Vg== X-Gm-Message-State: AFqh2kpdELUvx3vuSgHFqcOBUAKnDfMx22aeQNqYLhZEurDTRc8yryIh denFkWxWOBU/lci/eKaSfxigig== X-Google-Smtp-Source: AMrXdXukaIMGAoPUZxP9E447Jv73dbe7wRKGQx28j0E/6RmcT20yWBP4LJqjos7iiL226lhZ/tjlPA== X-Received: by 2002:a17:907:1385:b0:7c1:6167:7816 with SMTP id vs5-20020a170907138500b007c161677816mr35390562ejb.28.1672870047775; Wed, 04 Jan 2023 14:07:27 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id gs2-20020a170906f18200b007c491f53497sm16084240ejb.170.2023.01.04.14.07.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Jan 2023 14:07:27 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 18/20] hw/sh4: Open-code pflash_cfi02_register() Date: Wed, 4 Jan 2023 23:04:47 +0100 Message-Id: <20230104220449.41337-19-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=philmd@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:07:35 -0000 pflash_cfi02_register() hides an implicit sysbus mapping of MMIO region #0. This is not practical in a heterogeneous world where multiple cores use different address spaces. In order to remove to remove pflash_cfi02_register() from the pflash API, open-code it as a qdev creation call followed by an explicit sysbus mapping. Signed-off-by: Philippe Mathieu-Daudé --- hw/sh4/r2d.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index 39fc4f19d9..43a8c56d14 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -302,10 +302,11 @@ static void r2d_init(MachineState *machine) * addressable in words of 16bit. */ dinfo = drive_get(IF_PFLASH, 0, 0); - pflash_cfi02_register(0x0, "r2d.flash", FLASH_SIZE, - dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, - 64 * KiB, 1, 2, 0x0001, 0x227e, 0x2220, 0x2200, - 0x555, 0x2aa, 0); + dev = pflash_cfi02_create("r2d.flash", FLASH_SIZE, + dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, + 64 * KiB, 1, 2, 0x0001, 0x227e, 0x2220, 0x2200, + 0x555, 0x2aa, 0); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0x00000000); /* NIC: rtl8139 on-board, and 2 slots. */ for (i = 0; i < nb_nics; i++) -- 2.38.1 From MAILER-DAEMON Wed Jan 04 17:08:11 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDBvf-0002X0-1N for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 17:08:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDBvI-0002Eq-F4 for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:07:53 -0500 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDBvG-0005ax-Bu for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 17:07:48 -0500 Received: by mail-ej1-x62e.google.com with SMTP id m18so85792152eji.5 for ; Wed, 04 Jan 2023 14:07:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZjXAofq2INlxh6v+H74awaoGQiZxjj50d0Z5Ts91LMc=; b=YuZ/RbgeRSH2UGDgiOTNsUVPdo4mOEmyERt1MFFXdLGIKux5+lYgedDMDUlPIo7uAG HCdFl3rAFgNcCIZGBTUNWSjeIuxXs1SiPqbTU9IeJtbutnISUc9H9xCBlGh7pDhBYcPO fnJ4AnEP+2AcI7mYoLMPsKiBcnOjk0KEM51PwpFWTGU6Tf8kMF0p5DEfNOclhKW7Fy5M qxJ+VpnQH1lkJNRJQDNrfnVmt1cWnCTEr/F/YWZxcwr+HBY5ygqx6Dn3J47bOUcYtb68 BRQ/qtJ5KpLO1izOsqcCLAMqcAgzZz91mLiU3aUzkWDtfvRAB/c9/eGIJ1h7axW/YWr2 JXIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZjXAofq2INlxh6v+H74awaoGQiZxjj50d0Z5Ts91LMc=; b=xy2q1XiWj9KVcUpQUsPwSNLUWlFOhFpcdsighkY0Wt5Nk8hQMlBp0zsMLMuwIbAxu/ DOS9JoDErWzkYm5DARkCDcKVZGlD6pz09/2jPIOhZXUY9hsFNbQOlT2eyjkQ3TQX5eAN yV1WbDeNBhbzl8DOpqgg/o6U9C08p3Rnt7/x8luwXgOzcN0gE1DFVo3rO+vS81ASQwBL UfOKO6luFSwIxltXVPEssVV01N/87sbF4jYNlECscqUWqVaTMQwGBUQzAVj8Wzgku3co gJY7ejK3edA/zKzOsou3Czkhsp6eOzoPZ4d9ZxDa1+5e4a5WmCVdkmBEvCB+u/mgFpxQ /K/g== X-Gm-Message-State: AFqh2kq1PN2A3PHDKrogWax1qjopEG5F6qjxtLvU9atNG8Fbvf8ykwOP 2nIPJP2hCcbv2tluh85MomVBOA== X-Google-Smtp-Source: AMrXdXuQehTIL3AgRCtjjcqKMnh43Pr3sNqSeRnvtfYsbBIKL/6VQB/4YQR8Ogc+6YuL1DOCwGPyaA== X-Received: by 2002:a17:907:9a98:b0:7c1:d4c:f08c with SMTP id km24-20020a1709079a9800b007c10d4cf08cmr42464785ejc.4.1672870065626; Wed, 04 Jan 2023 14:07:45 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id d17-20020a170906305100b007bed316a6d9sm15915461ejd.18.2023.01.04.14.07.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 04 Jan 2023 14:07:45 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Subject: [PATCH 20/20] hw/block: Make PFlashCFI02 QOM declaration internal Date: Wed, 4 Jan 2023 23:04:49 +0100 Message-Id: <20230104220449.41337-21-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230104220449.41337-1-philmd@linaro.org> References: <20230104220449.41337-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=philmd@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Jan 2023 22:07:59 -0000 Convert the QOM PFlashCFI02 to a forward/opaque pointer declaration. Only pflash_cfi02.c is able to poke at the internal fields. Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi02.c | 2 ++ include/hw/block/flash.h | 1 - 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index a9dcabdeb2..90b5feb36c 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -63,6 +63,8 @@ enum { WCYCLE_AUTOSELECT_CFI = 8, }; +OBJECT_DECLARE_SIMPLE_TYPE(PFlashCFI02, PFLASH_CFI02) + struct PFlashCFI02 { /*< private >*/ SysBusDevice parent_obj; diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h index 64ee40c561..aefbaa9493 100644 --- a/include/hw/block/flash.h +++ b/include/hw/block/flash.h @@ -30,7 +30,6 @@ void pflash_cfi01_legacy_drive(DeviceState *dev, DriveInfo *dinfo); /* pflash_cfi02.c */ #define TYPE_PFLASH_CFI02 "cfi.pflash02" -OBJECT_DECLARE_SIMPLE_TYPE(PFlashCFI02, PFLASH_CFI02) /** * Create and realize a parallel NOR flash (CFI type 2) on the heap. -- 2.38.1 From MAILER-DAEMON Wed Jan 04 20:51:01 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDFPJ-0005Um-Qy for mharc-qemu-riscv@gnu.org; Wed, 04 Jan 2023 20:51:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDFPI-0005TV-CO for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 20:51:00 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDFPG-0007R6-2o for qemu-riscv@nongnu.org; Wed, 04 Jan 2023 20:50:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1672883457; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=Ae+m06scc8CQpVkRRjrujC7NB/xoSDz1xg6pdBHfsII=; b=X3jfdhYi3yqVwrt6azpfWV68eb8irBDZ9RlKTuzHjo7fdwLVEVjMSfJQTwXul8hSjOS+m8 eilxMY4QBLBWSWbktaftBd7J62/6NkfHwchyE9+LB88bDNMV0WySEV7qTN/SP0EvMG13NR Dhr4dLz3+Mx5/Jqh/3DUlv0DbTgZNhk= Received: from mail-ed1-f69.google.com (mail-ed1-f69.google.com [209.85.208.69]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-630-0vBOvuq4OK-e0l53qo9UXg-1; Wed, 04 Jan 2023 20:50:56 -0500 X-MC-Unique: 0vBOvuq4OK-e0l53qo9UXg-1 Received: by mail-ed1-f69.google.com with SMTP id y20-20020a056402271400b0046c9a6ec30fso22697111edd.14 for ; Wed, 04 Jan 2023 17:50:55 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=Ae+m06scc8CQpVkRRjrujC7NB/xoSDz1xg6pdBHfsII=; b=dCobXaDHyovBi0dRfllmAbe8cqZ6w85HvJkgPhH+0pVTvRKvm3LP43ZGxN0eI4uTq6 dWR8XtUUmtIxJi9uV7NIlhdW6E+p0Uw59+6rNegwm8Syl5jjueBDaF8NbZ/NTZxSIRcJ FKkeswg/0JpWqIUuVXmB6AwEohui8f8Mc6iWQsB+Lnj/FxIlASukVNzd1uFKQ8JemaDh eH/YTgGQAm3ZxZmiNe4toWD00IdT06TKM1QG5kfU4KazqWymInDkoIzD0lnzJCWGeZWg H8/g2FqDUosjwCynirkoIZ17i2G97Vj/H1dIEBq2pfde7Vp0VumlArgTgV4yPbsW7qbo rI3A== X-Gm-Message-State: AFqh2krMGJ4Ixfdip2CwhU1rKMjlgIn3xbJfn6Q1YR2slmSWdCY7j3FZ EDmtoAexoVhhcYqPDEaUy8/Fmc3/lpno8m7E1/MTi7Q7CTQw66QOd9mx75ickU3pIJn1lZNvyj6 WBKMj2OVYtcbPbS8= X-Received: by 2002:a17:907:8b09:b0:7c1:6e82:35fc with SMTP id sz9-20020a1709078b0900b007c16e8235fcmr57205434ejc.40.1672883454883; Wed, 04 Jan 2023 17:50:54 -0800 (PST) X-Google-Smtp-Source: AMrXdXueyh6LVIX2H0De8l4raSwRjPZDj2ljWKpMzf9ntNnW9w/EA7lfiCrGcIkI5XJE48p2Ru0cvA== X-Received: by 2002:a17:907:8b09:b0:7c1:6e82:35fc with SMTP id sz9-20020a1709078b0900b007c16e8235fcmr57205412ejc.40.1672883454600; Wed, 04 Jan 2023 17:50:54 -0800 (PST) Received: from redhat.com ([2.52.151.85]) by smtp.gmail.com with ESMTPSA id g26-20020a170906539a00b0073ae9ba9ba8sm15982484ejo.3.2023.01.04.17.50.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jan 2023 17:50:53 -0800 (PST) Date: Wed, 4 Jan 2023 20:50:46 -0500 From: "Michael S. Tsirkin" To: Markus Armbruster Cc: qemu-devel@nongnu.org, imammedo@redhat.com, ani@anisinha.ca, peter.maydell@linaro.org, laurent@vivier.eu, edgar.iglesias@gmail.com, Alistair.Francis@wdc.com, bin.meng@windriver.com, palmer@dabbelt.com, marcel.apfelbaum@gmail.com, yangxiaojuan@loongson.cn, gaosong@loongson.cn, richard.henderson@linaro.org, deller@gmx.de, jasowang@redhat.com, vikram.garhwal@amd.com, francisco.iglesias@amd.com, clg@kaod.org, kraxel@redhat.com, marcandre.lureau@redhat.com, riku.voipio@iki.fi, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, crwulff@gmail.com, marex@denx.de Subject: Re: [PATCH v2 0/4] Clean up includes Message-ID: <20230104205022-mutt-send-email-mst@kernel.org> References: <20221222120813.727830-1-armbru@redhat.com> MIME-Version: 1.0 In-Reply-To: <20221222120813.727830-1-armbru@redhat.com> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 01:51:00 -0000 On Thu, Dec 22, 2022 at 01:08:09PM +0100, Markus Armbruster wrote: > Back in 2016, we discussed[1] rules for headers, and these were > generally liked: > > 1. Have a carefully curated header that's included everywhere first. We > got that already thanks to Peter: osdep.h. > > 2. Headers should normally include everything they need beyond osdep.h. > If exceptions are needed for some reason, they must be documented in > the header. If all that's needed from a header is typedefs, put > those into qemu/typedefs.h instead of including the header. > > 3. Cyclic inclusion is forbidden. > > This series fixes a number of rule violations. Conflicted with some patches I'm merging so I queued this up too. Thanks! > It is based on > > [PATCH v2 0/4] hw/ppc: Clean up includes > [PATCH v2 0/7] include/hw/pci include/hw/cxl: Clean up includes > [PATCH v2 0/3] block: Clean up includes > [PATCH v3 0/5] coroutine: Clean up includes > > With all of these applied, just three inclusion loops remain reachable > from include/: > > target/microblaze/cpu.h target/microblaze/mmu.h > > target/nios2/cpu.h target/nios2/mmu.h > > target/riscv/cpu.h target/riscv/pmp.h > > Breaking them would be nice, but I'm out of steam. > > v2: > * Rebased > * PATCH 3: v1 posted separately > * PATCH 4: New > > [1] Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org> > https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html > > Based-on: <20221222104628.659681-1-armbru@redhat.com> > > Markus Armbruster (4): > include/hw/virtio: Break inclusion loop > include: Include headers where needed > include: Don't include qemu/osdep.h > docs/devel: Rules on #include in headers > > docs/devel/style.rst | 7 +++++++ > bsd-user/qemu.h | 1 - > crypto/block-luks-priv.h | 1 - > include/exec/plugin-gen.h | 1 + > include/hw/acpi/erst.h | 3 +++ > include/hw/char/cmsdk-apb-uart.h | 1 + > include/hw/char/goldfish_tty.h | 1 + > include/hw/char/xilinx_uartlite.h | 1 + > include/hw/cris/etraxfs.h | 1 + > include/hw/cxl/cxl_host.h | 1 - > include/hw/display/macfb.h | 3 ++- > include/hw/dma/sifive_pdma.h | 2 ++ > include/hw/i386/ioapic_internal.h | 1 + > include/hw/i386/sgx-epc.h | 1 + > include/hw/input/pl050.h | 1 - > include/hw/intc/goldfish_pic.h | 2 ++ > include/hw/intc/loongarch_pch_msi.h | 2 ++ > include/hw/intc/loongarch_pch_pic.h | 2 ++ > include/hw/intc/nios2_vic.h | 2 ++ > include/hw/misc/mchp_pfsoc_dmc.h | 2 ++ > include/hw/misc/mchp_pfsoc_ioscb.h | 2 ++ > include/hw/misc/mchp_pfsoc_sysreg.h | 2 ++ > include/hw/misc/pvpanic.h | 1 + > include/hw/misc/sifive_e_prci.h | 3 ++- > include/hw/misc/sifive_u_otp.h | 3 ++- > include/hw/misc/sifive_u_prci.h | 3 ++- > include/hw/misc/virt_ctrl.h | 2 ++ > include/hw/misc/xlnx-versal-pmc-iou-slcr.h | 1 + > include/hw/net/lasi_82596.h | 2 +- > include/hw/net/xlnx-zynqmp-can.h | 1 + > include/hw/ppc/pnv_psi.h | 2 +- > include/hw/riscv/boot_opensbi.h | 2 ++ > include/hw/riscv/microchip_pfsoc.h | 3 +++ > include/hw/riscv/numa.h | 1 + > include/hw/riscv/sifive_u.h | 2 ++ > include/hw/riscv/spike.h | 2 +- > include/hw/riscv/virt.h | 2 +- > include/hw/ssi/sifive_spi.h | 3 +++ > include/hw/timer/sse-timer.h | 1 + > include/hw/tricore/triboard.h | 1 - > include/hw/usb/hcd-dwc3.h | 1 + > include/hw/usb/hcd-musb.h | 2 ++ > include/hw/usb/xlnx-usb-subsystem.h | 2 ++ > include/hw/usb/xlnx-versal-usb2-ctrl-regs.h | 3 +++ > include/hw/virtio/virtio-mmio.h | 2 +- > include/hw/virtio/virtio.h | 1 - > include/qemu/plugin-memory.h | 3 +++ > include/qemu/userfaultfd.h | 1 - > include/sysemu/dirtyrate.h | 2 ++ > include/sysemu/dump.h | 1 + > include/user/syscall-trace.h | 1 + > net/vmnet_int.h | 1 - > qga/cutils.h | 1 - > target/hexagon/hex_arch_types.h | 1 - > target/hexagon/mmvec/macros.h | 1 - > target/riscv/pmu.h | 1 - > hw/virtio/virtio-qmp.c | 1 + > hw/virtio/virtio.c | 1 + > qga/cutils.c | 3 ++- > 59 files changed, 82 insertions(+), 22 deletions(-) > > -- > 2.38.1 From MAILER-DAEMON Thu Jan 05 04:16:30 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDMMQ-0003Nk-4Y for mharc-qemu-riscv@gnu.org; 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Markus Armbruster , Alistair Francis , Igor Mammedov , Ani Sinha , Laurent Vivier , "Edgar E. Iglesias" , Bin Meng , Palmer Dabbelt , Marcel Apfelbaum , Xiaojuan Yang , Song Gao , Richard Henderson , Helge Deller , Jason Wang , Vikram Garhwal , Francisco Iglesias , =?utf-8?Q?C=C3=A9dric?= Le Goater , Gerd Hoffmann , =?utf-8?Q?Marc-Andr=C3=A9?= Lureau , Riku Voipio , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org Subject: [PULL 35/51] include: Include headers where needed Message-ID: <20230105091310.263867-36-mst@redhat.com> References: <20230105091310.263867-1-mst@redhat.com> MIME-Version: 1.0 In-Reply-To: <20230105091310.263867-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 09:16:27 -0000 From: Markus Armbruster A number of headers neglect to include everything they need. They compile only if the headers they need are already included from elsewhere. Fix that. Signed-off-by: Markus Armbruster Reviewed-by: Alistair Francis Message-Id: <20221222120813.727830-3-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- include/exec/plugin-gen.h | 1 + include/hw/acpi/erst.h | 3 +++ include/hw/char/cmsdk-apb-uart.h | 1 + include/hw/char/goldfish_tty.h | 1 + include/hw/char/xilinx_uartlite.h | 1 + include/hw/cris/etraxfs.h | 1 + include/hw/display/macfb.h | 3 ++- include/hw/dma/sifive_pdma.h | 2 ++ include/hw/i386/ioapic_internal.h | 1 + include/hw/i386/sgx-epc.h | 1 + include/hw/intc/goldfish_pic.h | 2 ++ include/hw/intc/loongarch_pch_msi.h | 2 ++ include/hw/intc/loongarch_pch_pic.h | 2 ++ include/hw/intc/nios2_vic.h | 2 ++ include/hw/misc/mchp_pfsoc_dmc.h | 2 ++ include/hw/misc/mchp_pfsoc_ioscb.h | 2 ++ include/hw/misc/mchp_pfsoc_sysreg.h | 2 ++ include/hw/misc/pvpanic.h | 1 + include/hw/misc/sifive_e_prci.h | 3 ++- include/hw/misc/sifive_u_otp.h | 3 ++- include/hw/misc/sifive_u_prci.h | 3 ++- include/hw/misc/virt_ctrl.h | 2 ++ include/hw/misc/xlnx-versal-pmc-iou-slcr.h | 1 + include/hw/net/lasi_82596.h | 2 +- include/hw/net/xlnx-zynqmp-can.h | 1 + include/hw/ppc/pnv_psi.h | 2 +- include/hw/riscv/boot_opensbi.h | 2 ++ include/hw/riscv/microchip_pfsoc.h | 3 +++ include/hw/riscv/numa.h | 1 + include/hw/riscv/sifive_u.h | 2 ++ include/hw/riscv/spike.h | 2 +- include/hw/riscv/virt.h | 2 +- include/hw/ssi/sifive_spi.h | 3 +++ include/hw/timer/sse-timer.h | 1 + include/hw/usb/hcd-dwc3.h | 1 + include/hw/usb/hcd-musb.h | 2 ++ include/hw/usb/xlnx-usb-subsystem.h | 2 ++ include/hw/usb/xlnx-versal-usb2-ctrl-regs.h | 3 +++ include/hw/virtio/virtio-mmio.h | 2 +- include/qemu/plugin-memory.h | 3 +++ include/sysemu/dirtyrate.h | 2 ++ include/sysemu/dump.h | 1 + include/user/syscall-trace.h | 1 + 43 files changed, 71 insertions(+), 9 deletions(-) diff --git a/include/exec/plugin-gen.h b/include/exec/plugin-gen.h index 5004728c61..5f5506f1cc 100644 --- a/include/exec/plugin-gen.h +++ b/include/exec/plugin-gen.h @@ -12,6 +12,7 @@ #ifndef QEMU_PLUGIN_GEN_H #define QEMU_PLUGIN_GEN_H +#include "exec/cpu_ldst.h" #include "qemu/plugin.h" #include "tcg/tcg.h" diff --git a/include/hw/acpi/erst.h b/include/hw/acpi/erst.h index b747fe7739..b2ff663ddc 100644 --- a/include/hw/acpi/erst.h +++ b/include/hw/acpi/erst.h @@ -11,6 +11,9 @@ #ifndef HW_ACPI_ERST_H #define HW_ACPI_ERST_H +#include "hw/acpi/bios-linker-loader.h" +#include "qom/object.h" + void build_erst(GArray *table_data, BIOSLinker *linker, Object *erst_dev, const char *oem_id, const char *oem_table_id); diff --git a/include/hw/char/cmsdk-apb-uart.h b/include/hw/char/cmsdk-apb-uart.h index 9daff0eeee..64b0a3d534 100644 --- a/include/hw/char/cmsdk-apb-uart.h +++ b/include/hw/char/cmsdk-apb-uart.h @@ -15,6 +15,7 @@ #include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "chardev/char-fe.h" +#include "qapi/error.h" #include "qom/object.h" #define TYPE_CMSDK_APB_UART "cmsdk-apb-uart" diff --git a/include/hw/char/goldfish_tty.h b/include/hw/char/goldfish_tty.h index 7503d2fa1e..d59733e5ae 100644 --- a/include/hw/char/goldfish_tty.h +++ b/include/hw/char/goldfish_tty.h @@ -12,6 +12,7 @@ #include "qemu/fifo8.h" #include "chardev/char-fe.h" +#include "hw/sysbus.h" #define TYPE_GOLDFISH_TTY "goldfish_tty" OBJECT_DECLARE_SIMPLE_TYPE(GoldfishTTYState, GOLDFISH_TTY) diff --git a/include/hw/char/xilinx_uartlite.h b/include/hw/char/xilinx_uartlite.h index bb32d0fcb3..dd09c06801 100644 --- a/include/hw/char/xilinx_uartlite.h +++ b/include/hw/char/xilinx_uartlite.h @@ -17,6 +17,7 @@ #include "hw/qdev-properties.h" #include "hw/sysbus.h" +#include "qapi/error.h" static inline DeviceState *xilinx_uartlite_create(hwaddr addr, qemu_irq irq, diff --git a/include/hw/cris/etraxfs.h b/include/hw/cris/etraxfs.h index 8b01ed67d3..467b529dc0 100644 --- a/include/hw/cris/etraxfs.h +++ b/include/hw/cris/etraxfs.h @@ -29,6 +29,7 @@ #include "hw/cris/etraxfs_dma.h" #include "hw/qdev-properties.h" #include "hw/sysbus.h" +#include "qapi/error.h" DeviceState *etraxfs_eth_init(NICInfo *nd, hwaddr base, int phyaddr, struct etraxfs_dma_client *dma_out, diff --git a/include/hw/display/macfb.h b/include/hw/display/macfb.h index 55a50d3fb0..27cebefc9e 100644 --- a/include/hw/display/macfb.h +++ b/include/hw/display/macfb.h @@ -15,9 +15,10 @@ #include "exec/memory.h" #include "hw/irq.h" +#include "hw/nubus/nubus.h" +#include "hw/sysbus.h" #include "ui/console.h" #include "qemu/timer.h" -#include "qom/object.h" typedef enum { MACFB_DISPLAY_APPLE_21_COLOR = 0, diff --git a/include/hw/dma/sifive_pdma.h b/include/hw/dma/sifive_pdma.h index e319bbd6c4..8c6cfa7f32 100644 --- a/include/hw/dma/sifive_pdma.h +++ b/include/hw/dma/sifive_pdma.h @@ -23,6 +23,8 @@ #ifndef SIFIVE_PDMA_H #define SIFIVE_PDMA_H +#include "hw/sysbus.h" + struct sifive_pdma_chan { uint32_t control; uint32_t next_config; diff --git a/include/hw/i386/ioapic_internal.h b/include/hw/i386/ioapic_internal.h index 9880443cc7..e8ff338d7f 100644 --- a/include/hw/i386/ioapic_internal.h +++ b/include/hw/i386/ioapic_internal.h @@ -23,6 +23,7 @@ #define QEMU_IOAPIC_INTERNAL_H #include "exec/memory.h" +#include "hw/i386/ioapic.h" #include "hw/sysbus.h" #include "qemu/notify.h" #include "qom/object.h" diff --git a/include/hw/i386/sgx-epc.h b/include/hw/i386/sgx-epc.h index 581fac389a..3e00efd870 100644 --- a/include/hw/i386/sgx-epc.h +++ b/include/hw/i386/sgx-epc.h @@ -12,6 +12,7 @@ #ifndef QEMU_SGX_EPC_H #define QEMU_SGX_EPC_H +#include "hw/qdev-core.h" #include "hw/i386/hostmem-epc.h" #define TYPE_SGX_EPC "sgx-epc" diff --git a/include/hw/intc/goldfish_pic.h b/include/hw/intc/goldfish_pic.h index e9d552f796..3e79580367 100644 --- a/include/hw/intc/goldfish_pic.h +++ b/include/hw/intc/goldfish_pic.h @@ -10,6 +10,8 @@ #ifndef HW_INTC_GOLDFISH_PIC_H #define HW_INTC_GOLDFISH_PIC_H +#include "hw/sysbus.h" + #define TYPE_GOLDFISH_PIC "goldfish_pic" OBJECT_DECLARE_SIMPLE_TYPE(GoldfishPICState, GOLDFISH_PIC) diff --git a/include/hw/intc/loongarch_pch_msi.h b/include/hw/intc/loongarch_pch_msi.h index 6d67560dea..2810665ef7 100644 --- a/include/hw/intc/loongarch_pch_msi.h +++ b/include/hw/intc/loongarch_pch_msi.h @@ -5,6 +5,8 @@ * Copyright (C) 2021 Loongson Technology Corporation Limited */ +#include "hw/sysbus.h" + #define TYPE_LOONGARCH_PCH_MSI "loongarch_pch_msi" OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHMSI, LOONGARCH_PCH_MSI) diff --git a/include/hw/intc/loongarch_pch_pic.h b/include/hw/intc/loongarch_pch_pic.h index 2d4aa9ed6f..5d5dee9280 100644 --- a/include/hw/intc/loongarch_pch_pic.h +++ b/include/hw/intc/loongarch_pch_pic.h @@ -5,6 +5,8 @@ * Copyright (c) 2021 Loongson Technology Corporation Limited */ +#include "hw/sysbus.h" + #define TYPE_LOONGARCH_PCH_PIC "loongarch_pch_pic" #define PCH_PIC_NAME(name) TYPE_LOONGARCH_PCH_PIC#name OBJECT_DECLARE_SIMPLE_TYPE(LoongArchPCHPIC, LOONGARCH_PCH_PIC) diff --git a/include/hw/intc/nios2_vic.h b/include/hw/intc/nios2_vic.h index ac507b9d74..5c975a2ac4 100644 --- a/include/hw/intc/nios2_vic.h +++ b/include/hw/intc/nios2_vic.h @@ -35,6 +35,8 @@ #ifndef HW_INTC_NIOS2_VIC_H #define HW_INTC_NIOS2_VIC_H +#include "hw/sysbus.h" + #define TYPE_NIOS2_VIC "nios2-vic" OBJECT_DECLARE_SIMPLE_TYPE(Nios2VIC, NIOS2_VIC) diff --git a/include/hw/misc/mchp_pfsoc_dmc.h b/include/hw/misc/mchp_pfsoc_dmc.h index 2baa1413b0..3bc1581e0f 100644 --- a/include/hw/misc/mchp_pfsoc_dmc.h +++ b/include/hw/misc/mchp_pfsoc_dmc.h @@ -23,6 +23,8 @@ #ifndef MCHP_PFSOC_DMC_H #define MCHP_PFSOC_DMC_H +#include "hw/sysbus.h" + /* DDR SGMII PHY module */ #define MCHP_PFSOC_DDR_SGMII_PHY_REG_SIZE 0x1000 diff --git a/include/hw/misc/mchp_pfsoc_ioscb.h b/include/hw/misc/mchp_pfsoc_ioscb.h index 9235523e33..bab83a96a6 100644 --- a/include/hw/misc/mchp_pfsoc_ioscb.h +++ b/include/hw/misc/mchp_pfsoc_ioscb.h @@ -23,6 +23,8 @@ #ifndef MCHP_PFSOC_IOSCB_H #define MCHP_PFSOC_IOSCB_H +#include "hw/sysbus.h" + typedef struct MchpPfSoCIoscbState { SysBusDevice parent; MemoryRegion container; diff --git a/include/hw/misc/mchp_pfsoc_sysreg.h b/include/hw/misc/mchp_pfsoc_sysreg.h index 546ba68f6a..a2fd1c9f07 100644 --- a/include/hw/misc/mchp_pfsoc_sysreg.h +++ b/include/hw/misc/mchp_pfsoc_sysreg.h @@ -23,6 +23,8 @@ #ifndef MCHP_PFSOC_SYSREG_H #define MCHP_PFSOC_SYSREG_H +#include "hw/sysbus.h" + #define MCHP_PFSOC_SYSREG_REG_SIZE 0x2000 typedef struct MchpPfSoCSysregState { diff --git a/include/hw/misc/pvpanic.h b/include/hw/misc/pvpanic.h index e520566ab0..fab94165d0 100644 --- a/include/hw/misc/pvpanic.h +++ b/include/hw/misc/pvpanic.h @@ -15,6 +15,7 @@ #ifndef HW_MISC_PVPANIC_H #define HW_MISC_PVPANIC_H +#include "exec/memory.h" #include "qom/object.h" #define TYPE_PVPANIC_ISA_DEVICE "pvpanic" diff --git a/include/hw/misc/sifive_e_prci.h b/include/hw/misc/sifive_e_prci.h index 262ca16181..6aa949e910 100644 --- a/include/hw/misc/sifive_e_prci.h +++ b/include/hw/misc/sifive_e_prci.h @@ -18,7 +18,8 @@ #ifndef HW_SIFIVE_E_PRCI_H #define HW_SIFIVE_E_PRCI_H -#include "qom/object.h" + +#include "hw/sysbus.h" enum { SIFIVE_E_PRCI_HFROSCCFG = 0x0, diff --git a/include/hw/misc/sifive_u_otp.h b/include/hw/misc/sifive_u_otp.h index 5d0d7df455..170d2148f2 100644 --- a/include/hw/misc/sifive_u_otp.h +++ b/include/hw/misc/sifive_u_otp.h @@ -18,7 +18,8 @@ #ifndef HW_SIFIVE_U_OTP_H #define HW_SIFIVE_U_OTP_H -#include "qom/object.h" + +#include "hw/sysbus.h" #define SIFIVE_U_OTP_PA 0x00 #define SIFIVE_U_OTP_PAIO 0x04 diff --git a/include/hw/misc/sifive_u_prci.h b/include/hw/misc/sifive_u_prci.h index d9ebf40b7f..4d2491ad46 100644 --- a/include/hw/misc/sifive_u_prci.h +++ b/include/hw/misc/sifive_u_prci.h @@ -18,7 +18,8 @@ #ifndef HW_SIFIVE_U_PRCI_H #define HW_SIFIVE_U_PRCI_H -#include "qom/object.h" + +#include "hw/sysbus.h" #define SIFIVE_U_PRCI_HFXOSCCFG 0x00 #define SIFIVE_U_PRCI_COREPLLCFG0 0x04 diff --git a/include/hw/misc/virt_ctrl.h b/include/hw/misc/virt_ctrl.h index 25a237e518..81346cf017 100644 --- a/include/hw/misc/virt_ctrl.h +++ b/include/hw/misc/virt_ctrl.h @@ -7,6 +7,8 @@ #ifndef VIRT_CTRL_H #define VIRT_CTRL_H +#include "hw/sysbus.h" + #define TYPE_VIRT_CTRL "virt-ctrl" OBJECT_DECLARE_SIMPLE_TYPE(VirtCtrlState, VIRT_CTRL) diff --git a/include/hw/misc/xlnx-versal-pmc-iou-slcr.h b/include/hw/misc/xlnx-versal-pmc-iou-slcr.h index 2170420f01..f7d24c93c4 100644 --- a/include/hw/misc/xlnx-versal-pmc-iou-slcr.h +++ b/include/hw/misc/xlnx-versal-pmc-iou-slcr.h @@ -54,6 +54,7 @@ #ifndef XLNX_VERSAL_PMC_IOU_SLCR_H #define XLNX_VERSAL_PMC_IOU_SLCR_H +#include "hw/sysbus.h" #include "hw/register.h" #define TYPE_XILINX_VERSAL_PMC_IOU_SLCR "xlnx.versal-pmc-iou-slcr" diff --git a/include/hw/net/lasi_82596.h b/include/hw/net/lasi_82596.h index 7b62b04833..3ef2f47ba2 100644 --- a/include/hw/net/lasi_82596.h +++ b/include/hw/net/lasi_82596.h @@ -10,7 +10,7 @@ #include "net/net.h" #include "hw/net/i82596.h" -#include "qom/object.h" +#include "hw/sysbus.h" #define TYPE_LASI_82596 "lasi_82596" typedef struct SysBusI82596State SysBusI82596State; diff --git a/include/hw/net/xlnx-zynqmp-can.h b/include/hw/net/xlnx-zynqmp-can.h index eb1558708b..fd2aa77760 100644 --- a/include/hw/net/xlnx-zynqmp-can.h +++ b/include/hw/net/xlnx-zynqmp-can.h @@ -30,6 +30,7 @@ #ifndef XLNX_ZYNQMP_CAN_H #define XLNX_ZYNQMP_CAN_H +#include "hw/sysbus.h" #include "hw/register.h" #include "net/can_emu.h" #include "net/can_host.h" diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h index 8253469b8f..2a6f715350 100644 --- a/include/hw/ppc/pnv_psi.h +++ b/include/hw/ppc/pnv_psi.h @@ -23,7 +23,7 @@ #include "hw/sysbus.h" #include "hw/ppc/xics.h" #include "hw/ppc/xive.h" -#include "qom/object.h" +#include "hw/qdev-core.h" #define TYPE_PNV_PSI "pnv-psi" OBJECT_DECLARE_TYPE(PnvPsi, PnvPsiClass, diff --git a/include/hw/riscv/boot_opensbi.h b/include/hw/riscv/boot_opensbi.h index c19cad4818..1b749663dc 100644 --- a/include/hw/riscv/boot_opensbi.h +++ b/include/hw/riscv/boot_opensbi.h @@ -8,6 +8,8 @@ #ifndef RISCV_BOOT_OPENSBI_H #define RISCV_BOOT_OPENSBI_H +#include "exec/cpu-defs.h" + /** Expected value of info magic ('OSBI' ascii string in hex) */ #define FW_DYNAMIC_INFO_MAGIC_VALUE 0x4942534f diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchip_pfsoc.h index a757b240e0..9e806b09b1 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -22,13 +22,16 @@ #ifndef HW_MICROCHIP_PFSOC_H #define HW_MICROCHIP_PFSOC_H +#include "hw/boards.h" #include "hw/char/mchp_pfsoc_mmuart.h" +#include "hw/cpu/cluster.h" #include "hw/dma/sifive_pdma.h" #include "hw/misc/mchp_pfsoc_dmc.h" #include "hw/misc/mchp_pfsoc_ioscb.h" #include "hw/misc/mchp_pfsoc_sysreg.h" #include "hw/net/cadence_gem.h" #include "hw/sd/cadence_sdhci.h" +#include "hw/riscv/riscv_hart.h" typedef struct MicrochipPFSoCState { /*< private >*/ diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h index fcce942cee..1a9cce3344 100644 --- a/include/hw/riscv/numa.h +++ b/include/hw/riscv/numa.h @@ -19,6 +19,7 @@ #ifndef RISCV_NUMA_H #define RISCV_NUMA_H +#include "hw/boards.h" #include "hw/sysbus.h" #include "sysemu/numa.h" diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 8f63a183c4..a43304292c 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -19,6 +19,8 @@ #ifndef HW_SIFIVE_U_H #define HW_SIFIVE_U_H +#include "hw/boards.h" +#include "hw/cpu/cluster.h" #include "hw/dma/sifive_pdma.h" #include "hw/net/cadence_gem.h" #include "hw/riscv/riscv_hart.h" diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index 73d69234de..73bf2a9aad 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -19,9 +19,9 @@ #ifndef HW_RISCV_SPIKE_H #define HW_RISCV_SPIKE_H +#include "hw/boards.h" #include "hw/riscv/riscv_hart.h" #include "hw/sysbus.h" -#include "qom/object.h" #define SPIKE_CPUS_MAX 8 #define SPIKE_SOCKETS_MAX 8 diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index be4ab8fe7f..3007bb3646 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -19,10 +19,10 @@ #ifndef HW_RISCV_VIRT_H #define HW_RISCV_VIRT_H +#include "hw/boards.h" #include "hw/riscv/riscv_hart.h" #include "hw/sysbus.h" #include "hw/block/flash.h" -#include "qom/object.h" #define VIRT_CPUS_MAX_BITS 9 #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) diff --git a/include/hw/ssi/sifive_spi.h b/include/hw/ssi/sifive_spi.h index 47d0d6a47c..d0c40cdb11 100644 --- a/include/hw/ssi/sifive_spi.h +++ b/include/hw/ssi/sifive_spi.h @@ -22,6 +22,9 @@ #ifndef HW_SIFIVE_SPI_H #define HW_SIFIVE_SPI_H +#include "qemu/fifo8.h" +#include "hw/sysbus.h" + #define SIFIVE_SPI_REG_NUM (0x78 / 4) #define TYPE_SIFIVE_SPI "sifive.spi" diff --git a/include/hw/timer/sse-timer.h b/include/hw/timer/sse-timer.h index b4ee8e7f6c..265ad32400 100644 --- a/include/hw/timer/sse-timer.h +++ b/include/hw/timer/sse-timer.h @@ -25,6 +25,7 @@ #define SSE_TIMER_H #include "hw/sysbus.h" +#include "qemu/timer.h" #include "qom/object.h" #include "hw/timer/sse-counter.h" diff --git a/include/hw/usb/hcd-dwc3.h b/include/hw/usb/hcd-dwc3.h index 7c804d536d..f752a27e94 100644 --- a/include/hw/usb/hcd-dwc3.h +++ b/include/hw/usb/hcd-dwc3.h @@ -26,6 +26,7 @@ #ifndef HCD_DWC3_H #define HCD_DWC3_H +#include "hw/register.h" #include "hw/usb/hcd-xhci.h" #include "hw/usb/hcd-xhci-sysbus.h" diff --git a/include/hw/usb/hcd-musb.h b/include/hw/usb/hcd-musb.h index f30a26f7f4..4d4b1ec0fc 100644 --- a/include/hw/usb/hcd-musb.h +++ b/include/hw/usb/hcd-musb.h @@ -13,6 +13,8 @@ #ifndef HW_USB_HCD_MUSB_H #define HW_USB_HCD_MUSB_H +#include "exec/hwaddr.h" + enum musb_irq_source_e { musb_irq_suspend = 0, musb_irq_resume, diff --git a/include/hw/usb/xlnx-usb-subsystem.h b/include/hw/usb/xlnx-usb-subsystem.h index 5b730abd84..40f9e97e09 100644 --- a/include/hw/usb/xlnx-usb-subsystem.h +++ b/include/hw/usb/xlnx-usb-subsystem.h @@ -25,6 +25,8 @@ #ifndef XLNX_USB_SUBSYSTEM_H #define XLNX_USB_SUBSYSTEM_H +#include "hw/register.h" +#include "hw/sysbus.h" #include "hw/usb/xlnx-versal-usb2-ctrl-regs.h" #include "hw/usb/hcd-dwc3.h" diff --git a/include/hw/usb/xlnx-versal-usb2-ctrl-regs.h b/include/hw/usb/xlnx-versal-usb2-ctrl-regs.h index 633bf3013a..6a502006b0 100644 --- a/include/hw/usb/xlnx-versal-usb2-ctrl-regs.h +++ b/include/hw/usb/xlnx-versal-usb2-ctrl-regs.h @@ -26,6 +26,9 @@ #ifndef XLNX_VERSAL_USB2_CTRL_REGS_H #define XLNX_VERSAL_USB2_CTRL_REGS_H +#include "hw/register.h" +#include "hw/sysbus.h" + #define TYPE_XILINX_VERSAL_USB2_CTRL_REGS "xlnx.versal-usb2-ctrl-regs" #define XILINX_VERSAL_USB2_CTRL_REGS(obj) \ diff --git a/include/hw/virtio/virtio-mmio.h b/include/hw/virtio/virtio-mmio.h index 090f7730e7..aa49262022 100644 --- a/include/hw/virtio/virtio-mmio.h +++ b/include/hw/virtio/virtio-mmio.h @@ -22,8 +22,8 @@ #ifndef HW_VIRTIO_MMIO_H #define HW_VIRTIO_MMIO_H +#include "hw/sysbus.h" #include "hw/virtio/virtio-bus.h" -#include "qom/object.h" /* QOM macros */ /* virtio-mmio-bus */ diff --git a/include/qemu/plugin-memory.h b/include/qemu/plugin-memory.h index 8ad13c110c..6fd539022a 100644 --- a/include/qemu/plugin-memory.h +++ b/include/qemu/plugin-memory.h @@ -9,6 +9,9 @@ #ifndef PLUGIN_MEMORY_H #define PLUGIN_MEMORY_H +#include "exec/cpu-defs.h" +#include "exec/hwaddr.h" + struct qemu_plugin_hwaddr { bool is_io; bool is_store; diff --git a/include/sysemu/dirtyrate.h b/include/sysemu/dirtyrate.h index 4d3b9a4902..20813f303f 100644 --- a/include/sysemu/dirtyrate.h +++ b/include/sysemu/dirtyrate.h @@ -13,6 +13,8 @@ #ifndef QEMU_DIRTYRATE_H #define QEMU_DIRTYRATE_H +#include "qapi/qapi-types-migration.h" + typedef struct VcpuStat { int nvcpu; /* number of vcpu */ DirtyRateVcpu *rates; /* array of dirty rate for each vcpu */ diff --git a/include/sysemu/dump.h b/include/sysemu/dump.h index 4ffed0b659..7008d43d04 100644 --- a/include/sysemu/dump.h +++ b/include/sysemu/dump.h @@ -15,6 +15,7 @@ #define DUMP_H #include "qapi/qapi-types-dump.h" +#include "qemu/thread.h" #define MAKEDUMPFILE_SIGNATURE "makedumpfile" #define MAX_SIZE_MDF_HEADER (4096) /* max size of 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Tsirkin" To: qemu-devel@nongnu.org Cc: Peter Maydell , Markus Armbruster , Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= , Bin Meng , Taylor Simpson , Alistair Francis , Warner Losh , Kyle Evans , Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= , Ben Widawsky , Jonathan Cameron , Bastian Koppelmann , Jason Wang , Michael Roth , Konstantin Kostiuk , Palmer Dabbelt , Bin Meng , qemu-riscv@nongnu.org Subject: [PULL 36/51] include: Don't include qemu/osdep.h Message-ID: <20230105091310.263867-37-mst@redhat.com> References: <20230105091310.263867-1-mst@redhat.com> MIME-Version: 1.0 In-Reply-To: <20230105091310.263867-1-mst@redhat.com> X-Mailer: git-send-email 2.27.0.106.g8ac3dc51b1 X-Mutt-Fcc: =sent X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 09:16:30 -0000 From: Markus Armbruster docs/devel/style.rst mandates: The "qemu/osdep.h" header contains preprocessor macros that affect the behavior of core system headers like . It must be the first include so that core system headers included by external libraries get the preprocessor macros that QEMU depends on. Do not include "qemu/osdep.h" from header files since the .c file will have already included it. A few violations have crept in. Fix them. Signed-off-by: Markus Armbruster Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Reviewed-by: Taylor Simpson Reviewed-by: Alistair Francis Message-Id: <20221222120813.727830-4-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael S. Tsirkin --- bsd-user/qemu.h | 1 - crypto/block-luks-priv.h | 1 - include/hw/cxl/cxl_host.h | 1 - include/hw/input/pl050.h | 1 - include/hw/tricore/triboard.h | 1 - include/qemu/userfaultfd.h | 1 - net/vmnet_int.h | 1 - qga/cutils.h | 1 - target/hexagon/hex_arch_types.h | 1 - target/hexagon/mmvec/macros.h | 1 - target/riscv/pmu.h | 1 - qga/cutils.c | 3 ++- 12 files changed, 2 insertions(+), 12 deletions(-) diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index be6105385e..0ceecfb6df 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -17,7 +17,6 @@ #ifndef QEMU_H #define QEMU_H -#include "qemu/osdep.h" #include "cpu.h" #include "qemu/units.h" #include "exec/cpu_ldst.h" diff --git a/crypto/block-luks-priv.h b/crypto/block-luks-priv.h index 90a20d432b..1066df0307 100644 --- a/crypto/block-luks-priv.h +++ b/crypto/block-luks-priv.h @@ -18,7 +18,6 @@ * */ -#include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/bswap.h" diff --git a/include/hw/cxl/cxl_host.h b/include/hw/cxl/cxl_host.h index a1b662ce40..c9bc9c7c50 100644 --- a/include/hw/cxl/cxl_host.h +++ b/include/hw/cxl/cxl_host.h @@ -7,7 +7,6 @@ * COPYING file in the top-level directory. */ -#include "qemu/osdep.h" #include "hw/cxl/cxl.h" #include "hw/boards.h" diff --git a/include/hw/input/pl050.h b/include/hw/input/pl050.h index 89ec4fafc9..4cb8985f31 100644 --- a/include/hw/input/pl050.h +++ b/include/hw/input/pl050.h @@ -10,7 +10,6 @@ #ifndef HW_PL050_H #define HW_PL050_H -#include "qemu/osdep.h" #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/input/ps2.h" diff --git a/include/hw/tricore/triboard.h b/include/hw/tricore/triboard.h index 094c8bd563..4fdd2d7d97 100644 --- a/include/hw/tricore/triboard.h +++ b/include/hw/tricore/triboard.h @@ -18,7 +18,6 @@ * License along with this library; if not, see . */ -#include "qemu/osdep.h" #include "qapi/error.h" #include "hw/boards.h" #include "sysemu/sysemu.h" diff --git a/include/qemu/userfaultfd.h b/include/qemu/userfaultfd.h index 6b74f92792..55c95998e8 100644 --- a/include/qemu/userfaultfd.h +++ b/include/qemu/userfaultfd.h @@ -13,7 +13,6 @@ #ifndef USERFAULTFD_H #define USERFAULTFD_H -#include "qemu/osdep.h" #include "exec/hwaddr.h" #include diff --git a/net/vmnet_int.h b/net/vmnet_int.h index adf6e8c20d..d0b90594f2 100644 --- a/net/vmnet_int.h +++ b/net/vmnet_int.h @@ -10,7 +10,6 @@ #ifndef VMNET_INT_H #define VMNET_INT_H -#include "qemu/osdep.h" #include "vmnet_int.h" #include "clients.h" diff --git a/qga/cutils.h b/qga/cutils.h index f0f30a7d28..2bfaf554a8 100644 --- a/qga/cutils.h +++ b/qga/cutils.h @@ -1,7 +1,6 @@ #ifndef CUTILS_H_ #define CUTILS_H_ -#include "qemu/osdep.h" int qga_open_cloexec(const char *name, int flags, mode_t mode); diff --git a/target/hexagon/hex_arch_types.h b/target/hexagon/hex_arch_types.h index 885f68f760..52a7f2b2f3 100644 --- a/target/hexagon/hex_arch_types.h +++ b/target/hexagon/hex_arch_types.h @@ -18,7 +18,6 @@ #ifndef HEXAGON_HEX_ARCH_TYPES_H #define HEXAGON_HEX_ARCH_TYPES_H -#include "qemu/osdep.h" #include "mmvec/mmvec.h" #include "qemu/int128.h" diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index 8c864e8c68..1201d778d0 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -18,7 +18,6 @@ #ifndef HEXAGON_MMVEC_MACROS_H #define HEXAGON_MMVEC_MACROS_H -#include "qemu/osdep.h" #include "qemu/host-utils.h" #include "arch.h" #include "mmvec/system_ext_mmvec.h" diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 3004ce37b6..0c819ca983 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -16,7 +16,6 @@ * this program. If not, see . */ -#include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" #include "qemu/main-loop.h" diff --git a/qga/cutils.c b/qga/cutils.c index b8e142ef64..b21bcf3683 100644 --- a/qga/cutils.c +++ b/qga/cutils.c @@ -2,8 +2,9 @@ * This work is licensed under the terms of the GNU GPL, version 2 or later. * See the COPYING file in the top-level directory. */ -#include "cutils.h" +#include "qemu/osdep.h" +#include "cutils.h" #include "qapi/error.h" /** -- MST From MAILER-DAEMON Thu Jan 05 11:43:30 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTL0-0006tJ-6S for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 11:43:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTKy-0006rh-8r for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:43:28 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTKt-0006wM-F4 for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:43:27 -0500 Received: by mail-wm1-x32a.google.com with SMTP id z8-20020a05600c220800b003d33b0bda11so2727769wml.0 for ; Thu, 05 Jan 2023 08:43:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cVDgWVfU9UuFFIzuYyi6pmmim2xRdLyJJ3WToGnxjwc=; b=uthMc/2Q1iZ3HRZvJA8mMWbATqkfzlwfMLQQfthPEdUE45PO5xBYMSwducWMJ2TOvM 5Koq+ATLBkOtcS1nCATIC38iFhnt0/JYtwHig2x2UAF8yufpbWFq/wogmfdrwR5/rIga Snt6An5Bj7KGDb7fP2LVZpJzMp7Utzc4MOYpmSJqbQRG44aDJDHTHAB0y/eOdenTsOpO 29naaPUgVvXyCwexDN53LXCN5+ySljNqNidu3G0FZ7SfaaqMbtUwSeOJgTdxJb3f8cAL eCkgMQ3qLZ09wsemVk6LhFBAKaOJtLz3AJ8RvsUPlkfBI0QvtRcFgZzLI6A0LjC4B5ZV 48JA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cVDgWVfU9UuFFIzuYyi6pmmim2xRdLyJJ3WToGnxjwc=; b=Cs36al1uepeRlU2LLI94z5YvFiYy0phaUXY2i/Poy28FLxKLohbiyCd2DxUAOtjvBG 8ZqMlyY/NyEBZDKLf5JFNvTGzJGrHSE6dbrNu8h0KchciCFoL6Agu5tTpWv8U27NWbAB rx88aI5oL4LMMFwXlVbYVSzMieTdP5B3zT+H/cdZiM98TKt2Tv2Rd2hIDMTOd76rI80k DxawFI6DPq2b3ye4MihfPf521EvAo6fTSLx9EGbc1lpyd1b4GoO1URzRCHZgjMpAS1E7 rOmRPZX/QJQKtCYSuNv+VOvMq785O3T5rK1s2XfThhA8kpl/WEOWP4d1IexE32wiv1gZ DSuQ== X-Gm-Message-State: AFqh2kpaKjCZD9vd0PHQrcFu/eob/cMjD0PydtDVJzU5RqjLgw0Vh79u A0YqLreprBkMplk93PCH3spc5Q== X-Google-Smtp-Source: AMrXdXsvLQatva7Ex5ZRDF8FTPU2gDkvGfc0OZUrNay7bV0Yd4XvFgjgnX+VPZ/7uwnEf6BCSyrsRA== X-Received: by 2002:a7b:ca4f:0:b0:3d3:56ce:5673 with SMTP id m15-20020a7bca4f000000b003d356ce5673mr39139973wml.6.1672937001907; Thu, 05 Jan 2023 08:43:21 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id g41-20020a05600c4ca900b003cfd0bd8c0asm2675127wmp.30.2023.01.05.08.43.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:43:20 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 7C1F31FFBA; Thu, 5 Jan 2023 16:43:20 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH v2 02/21] target/arm: fix handling of HLT semihosting in system mode Date: Thu, 5 Jan 2023 16:43:01 +0000 Message-Id: <20230105164320.2164095-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:43:28 -0000 The check semihosting_enabled() wants to know if the guest is currently in user mode. Unlike the other cases the test was inverted causing us to block semihosting calls in non-EL0 modes. Fixes: 19b26317e9 (target/arm: Honour -semihosting-config userspace=on) Signed-off-by: Alex Bennée --- target/arm/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 74a903072f..1dcaefb8e7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1184,7 +1184,7 @@ static inline void gen_hlt(DisasContext *s, int imm) * semihosting, to provide some semblance of security * (and for consistency with our 32-bit semihosting). */ - if (semihosting_enabled(s->current_el != 0) && + if (semihosting_enabled(s->current_el == 0) && (imm == (s->thumb ? 0x3c : 0xf000))) { gen_exception_internal_insn(s, EXCP_SEMIHOST); return; -- 2.34.1 From MAILER-DAEMON Thu Jan 05 11:43:30 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTL0-0006th-B9 for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 11:43:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTKy-0006s2-KK for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:43:28 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTKt-0006vi-G8 for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:43:28 -0500 Received: by mail-wm1-x335.google.com with SMTP id m26-20020a05600c3b1a00b003d9811fcaafso1774087wms.5 for ; Thu, 05 Jan 2023 08:43:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JPkl1ua/jXIj//qrN71d3DFOxM8PoMBDQnDzXwdNRYQ=; b=EIE/DgcCLUkfzhMtyivozCdgrPG/pDKtQ+peiYZgWjE+DQqx9+bXf06ohG8KvhQp/T /JJm82kOcW0Suj8d1CwAFM3mX6oLBHEc7fXVXZvi2ks5dh5V6JUetaBKWFNQT1Xp14DA z84saW4tJTKyGNSfG8gvw6vznrjgi8KRizrjw0fuVcQlnIpT5hczwQvro19wN3AYcJzr gmenat8rlvcEHEEKwG++ETz/Va4awjHkhPojqmLIgAuZzzO6ymLmkTrx5zq0eeN/vmP8 LPk+70K4UNtyuGTa7lO5W6SGnf2K8oER8ogfYGZkGunRfABcsfE6hGDHnW4F9zx3XuA9 gSDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JPkl1ua/jXIj//qrN71d3DFOxM8PoMBDQnDzXwdNRYQ=; b=b5J37hPQH6M7TC7D5SKyidFk4fcsnHVpCBscTFMlaiI9fmwNKbLhwkolBrlpTF3Nk7 /B9zskLv9Ul4S3LN7aoNp6nOPT42C+D12qtYoD65+EB+ZFrU2KX4bu3bc811m/BrHd40 p3WgJyqfewICbYOyWAZUWeNobStVDcHZ/d67J7hr4xeLfGFVpiEN5qoKjrdV98axmUOn Li4u/cfnmpnZGfj0Q9yLzYWaHugAUEeWQ7w9A6cuzZ3+VRQ2eVt/shKj5o4+gVVaQO+g /NoFzGSKMcLOxwA8Gz9vSV0tFu+F0DKAAje5NVvnTdhoiJOD6dhJQDtGccNtXAzMpLuj mGqA== X-Gm-Message-State: AFqh2konOA4oT9b+2qGovZi04YsS6NsGBQVlsdk4g6zq0NzgxWIE0eC+ 5UVTBfSsKbZuAUbhA6tuO+/TcQ== X-Google-Smtp-Source: AMrXdXsgJgdyAayDcGuvCHfEMZCmIa9JozZ1tiQzcgqolYH3JUV2+BpcTL3c89a/vQxklPJXrJjk5Q== X-Received: by 2002:a05:600c:34ce:b0:3cf:614e:b587 with SMTP id d14-20020a05600c34ce00b003cf614eb587mr40207474wmq.26.1672937001167; Thu, 05 Jan 2023 08:43:21 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id j1-20020a05600c1c0100b003cfaae07f68sm3417832wms.17.2023.01.05.08.43.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:43:20 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 6C4301FFB8; Thu, 5 Jan 2023 16:43:20 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH v2 01/21] gdbstub/internals.h: clean up include guard Date: Thu, 5 Jan 2023 16:43:00 +0000 Message-Id: <20230105164320.2164095-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:43:28 -0000 Use something more specific to avoid name clashes. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée --- gdbstub/internals.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/gdbstub/internals.h b/gdbstub/internals.h index eabb0341d1..b444f24ef5 100644 --- a/gdbstub/internals.h +++ b/gdbstub/internals.h @@ -6,12 +6,12 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef _INTERNALS_H_ -#define _INTERNALS_H_ +#ifndef GDBSTUB_INTERNALS_H +#define GDBSTUB_INTERNALS_H bool gdb_supports_guest_debug(void); int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len); int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len); void gdb_breakpoint_remove_all(CPUState *cs); -#endif /* _INTERNALS_H_ */ +#endif /* GDBSTUB_INTERNALS_H */ -- 2.34.1 From MAILER-DAEMON Thu Jan 05 11:43:30 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTL0-0006uX-La for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 11:43:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTKx-0006r7-33 for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:43:27 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTKt-0006w8-DE for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:43:26 -0500 Received: by mail-wm1-x331.google.com with SMTP id ja17so28447456wmb.3 for ; Thu, 05 Jan 2023 08:43:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=andOexte/qTAbZAFNvqdK8ze6FjZMbbXg1AFTficNCU=; b=nAnw6qgJhq8wku70jVM9IaApWWFFDlQZYqXxbY7RN7xpas6S/MGksQWeGOqXcuXej6 dXrNL0zkyQwiSGVv8cXH6ctjB0NteeVMf0OCa2sqmaO54YSe9OFn3j9/uN/SlaugzI3L lvN8y+53zz2Dg6+Ve00TWR2Cgl9judNjlSxjMiuLnim/8wD3ONyxGprrGKBYXYq71JHD /YZZBWVd8xMToRgwt968Sa497PzIfN9rdZuFVu8ZeIj9VgdxK17ne8BcPuGLn0lHMb6E vDfhwXQKMkbXP9gtQ+m/GXXFbI8IaCuwpQVNw5v72tAH4jo3j3nOkfrWX/2QEj/auBcV J6yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=andOexte/qTAbZAFNvqdK8ze6FjZMbbXg1AFTficNCU=; b=EHrze1SDjuxnvviaukAT3YnTL4UoGE3VINh17T7z+sbsPLHX4fZQMCOs/cXbox7pDu rNX+dd9r1Lct1cWbshrcylHTcPa4s0+TV1r4FnshQ4IgpTsEqucYR7v1SqQ7Rt9jMqCr tnbsSbwOjvgaITL8NkdybylPnSw5MkfwJkHLNGLIVEgH/rmUYDmGCihA103WNsytRNRV d5F6O71HFNHHW06bBLDH23XgoGBL3senJtcL6B0ypI6Ust5EDNzYoURYkOJr4aIC2RLp Q883QVDzwbtaDKXRCl2BlszZYzBkCvHfGAWRox6XBAcWfvBM/6eua1NRBDr9NmsFKWns VHag== X-Gm-Message-State: AFqh2krBdlgoGowIOpnoJcaJn20dZFm9Hf85F9yhILUSFgdW0sKFPZzc 3g2pkVCsXlZXEwvasBAcOH0QGA== X-Google-Smtp-Source: AMrXdXtnZ7VEIdFtdZt9Qp+5OjHDbkCcJOTLQpDWiJeO2j1kj6RkG6jkL0YD9EZF1j2xUgFML26PPQ== X-Received: by 2002:a05:600c:1c85:b0:3d3:4b18:27c6 with SMTP id k5-20020a05600c1c8500b003d34b1827c6mr36137319wms.11.1672937001511; Thu, 05 Jan 2023 08:43:21 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id he11-20020a05600c540b00b003d359aa353csm2851006wmb.45.2023.01.05.08.43.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:43:20 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 5D4E91FFB7; Thu, 5 Jan 2023 16:43:20 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH v2 00/21] gdbstub: re-organise to for better compilation behaviour Date: Thu, 5 Jan 2023 16:42:59 +0000 Message-Id: <20230105164320.2164095-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:43:27 -0000 I was motivated to sort this out while working on my register API which is target agnostic but ran into the weeds when trying to link up with the gdbstub. This was due to us building gdbstub for every single target we support due to a few ABI sensitive bits that require CPU specific information. This series does a bunch of surgery to break the monolithic file apart into its constituent parts as well as simplify the headers to users can avoid bringing in more dependencies than they need. While the final result does increase the number of object files we reduce the total size of them all. We could go even further if we manage to build just 2 ABI binaries and sort out the magic to link them in meson. I think this requires us to removing TARGET_LONG_BITS from cpu-defs.h and exposing it to the build machinery. Before: 🕙16:36:31 alex.bennee@hackbox2:qemu.git/builds/reference on î‚  gdbstub/next [$?⇕] took 2s âžœ find . -iname "gdbstub*.o" -exec echo -n -e {}"\0" \; | du -hc --files0-from=- | tail -n 1 12M total 🕙16:36:42 alex.bennee@hackbox2:qemu.git/builds/reference on î‚  gdbstub/next [$?⇕] âžœ find . -iname "gdbstub*.o" | wc -l 68 After: âžœ find . -iname "gdbstub*.o" -exec echo -n -e {}"\0" \; | du -hc --files0-from=- | tail -n 1 4.0M total 🕙16:41:42 alex.bennee@hackbox2:qemu.git/builds/all on î‚  gdbstub/next [$?⇕] took 2s âžœ find . -iname "gdbstub*.o" | wc -l 105 The following patches need review: gdbstub: only compile gdbstub twice for whole build gdbstub: move syscall handling to new file gdbstub: move register helpers into standalone include gdbstub: don't use target_ulong while handling registers gdbstub: fix address type of gdb_set_cpu_pc gdbstub: specialise stub_can_reverse gdbstub: introduce gdb_get_max_cpus gdbstub: specialise target_memory_rw_debug gdbstub: specialise handle_query_attached gdbstub: abstract target specific details from gdb_put_packet_binary gdbstub: make various helpers visible to the rest of the module gdbstub: move fromhex/tohex routines to internals gdbstub: define separate user/system structures target/arm: fix handling of HLT semihosting in system mode Alex Bennée (20): gdbstub/internals.h: clean up include guard target/arm: fix handling of HLT semihosting in system mode gdbstub: fix-up copyright and license files gdbstub: define separate user/system structures gdbstub: move GDBState to shared internals header includes: move tb_flush into its own header gdbstub: move fromhex/tohex routines to internals gdbstub: make various helpers visible to the rest of the module gdbstub: move chunk of softmmu functionality to own file gdbstub: move chunks of user code into own files gdbstub: abstract target specific details from gdb_put_packet_binary gdbstub: specialise handle_query_attached gdbstub: specialise target_memory_rw_debug gdbstub: introduce gdb_get_max_cpus gdbstub: specialise stub_can_reverse gdbstub: fix address type of gdb_set_cpu_pc gdbstub: don't use target_ulong while handling registers gdbstub: move register helpers into standalone include gdbstub: move syscall handling to new file gdbstub: only compile gdbstub twice for whole build Philippe Mathieu-Daudé (1): gdbstub: Make syscall_complete/[gs]et_reg target-agnostic typedefs gdbstub/internals.h | 207 ++- include/exec/exec-all.h | 1 - include/exec/gdbstub.h | 208 --- include/exec/tb-flush.h | 26 + include/gdbstub/helpers.h | 103 ++ include/gdbstub/syscalls.h | 124 ++ include/gdbstub/user.h | 43 + linux-user/user-internals.h | 1 + accel/stubs/tcg-stub.c | 1 + accel/tcg/tb-maint.c | 1 + accel/tcg/translate-all.c | 1 + cpu.c | 1 + gdbstub/gdbstub.c | 1654 ++---------------------- gdbstub/softmmu.c | 589 ++++++++- gdbstub/syscalls.c | 230 ++++ gdbstub/user-target.c | 283 ++++ gdbstub/user.c | 406 +++++- hw/ppc/spapr_hcall.c | 1 + linux-user/exit.c | 2 +- linux-user/main.c | 1 + linux-user/signal.c | 2 +- plugins/core.c | 1 + plugins/loader.c | 2 +- semihosting/arm-compat-semi.c | 1 + semihosting/guestfd.c | 2 +- semihosting/syscalls.c | 3 +- softmmu/runstate.c | 2 +- target/alpha/gdbstub.c | 2 +- target/alpha/sys_helper.c | 1 + target/arm/gdbstub.c | 1 + target/arm/gdbstub64.c | 2 +- target/arm/helper-a64.c | 2 +- target/arm/m_helper.c | 2 +- target/arm/translate.c | 2 +- target/avr/gdbstub.c | 2 +- target/cris/gdbstub.c | 2 +- target/hexagon/gdbstub.c | 2 +- target/hppa/gdbstub.c | 2 +- target/i386/gdbstub.c | 2 +- target/i386/whpx/whpx-all.c | 2 +- target/loongarch/gdbstub.c | 1 + target/m68k/gdbstub.c | 2 +- target/m68k/helper.c | 1 + target/m68k/m68k-semi.c | 3 +- target/microblaze/gdbstub.c | 2 +- target/mips/gdbstub.c | 2 +- target/mips/tcg/sysemu/mips-semi.c | 3 +- target/nios2/cpu.c | 2 +- target/nios2/nios2-semi.c | 3 +- target/openrisc/gdbstub.c | 2 +- target/openrisc/interrupt.c | 2 +- target/openrisc/mmu.c | 2 +- target/ppc/cpu_init.c | 2 +- target/ppc/gdbstub.c | 1 + target/riscv/csr.c | 1 + target/riscv/gdbstub.c | 1 + target/rx/gdbstub.c | 2 +- target/s390x/gdbstub.c | 1 + target/s390x/helper.c | 2 +- target/sh4/gdbstub.c | 2 +- target/sparc/gdbstub.c | 2 +- target/tricore/gdbstub.c | 2 +- target/xtensa/core-dc232b.c | 2 +- target/xtensa/core-dc233c.c | 2 +- target/xtensa/core-de212.c | 2 +- target/xtensa/core-de233_fpu.c | 2 +- target/xtensa/core-dsp3400.c | 2 +- target/xtensa/core-fsf.c | 2 +- target/xtensa/core-lx106.c | 2 +- target/xtensa/core-sample_controller.c | 2 +- target/xtensa/core-test_kc705_be.c | 2 +- target/xtensa/core-test_mmuhifi_c3.c | 2 +- target/xtensa/gdbstub.c | 2 +- target/xtensa/helper.c | 2 +- MAINTAINERS | 1 + gdbstub/meson.build | 35 +- gdbstub/trace-events | 4 +- 77 files changed, 2250 insertions(+), 1775 deletions(-) create mode 100644 include/exec/tb-flush.h create mode 100644 include/gdbstub/helpers.h create mode 100644 include/gdbstub/syscalls.h create mode 100644 include/gdbstub/user.h create mode 100644 gdbstub/syscalls.c create mode 100644 gdbstub/user-target.c -- 2.34.1 From MAILER-DAEMON Thu Jan 05 11:43:32 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTL2-0006xd-FQ for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 11:43:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTL1-0006ve-Be for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:43:31 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTKu-0006x8-Id for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:43:31 -0500 Received: by mail-wr1-x434.google.com with SMTP id r2so1883191wrv.7 for ; Thu, 05 Jan 2023 08:43:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; 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=?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH v2 03/21] gdbstub: fix-up copyright and license files Date: Thu, 5 Jan 2023 16:43:02 +0000 Message-Id: <20230105164320.2164095-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:43:31 -0000 When I started splitting gdbstub apart I was a little too boilerplate with my file headers. Fix up to carry over Fabrice's copyright and the LGPL license header. Fixes: ae7467b1ac (gdbstub: move breakpoint logic to accel ops) Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée --- gdbstub/softmmu.c | 3 ++- gdbstub/user.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/gdbstub/softmmu.c b/gdbstub/softmmu.c index f208c6cf15..183dfb40e4 100644 --- a/gdbstub/softmmu.c +++ b/gdbstub/softmmu.c @@ -4,9 +4,10 @@ * Debug integration depends on support from the individual * accelerators so most of this involves calling the ops helpers. * + * Copyright (c) 2003-2005 Fabrice Bellard * Copyright (c) 2022 Linaro Ltd * - * SPDX-License-Identifier: GPL-2.0-or-later + * SPDX-License-Identifier: LGPL-2.0+ */ #include "qemu/osdep.h" diff --git a/gdbstub/user.c b/gdbstub/user.c index 033e5fdd71..a5f370bcf9 100644 --- a/gdbstub/user.c +++ b/gdbstub/user.c @@ -3,9 +3,10 @@ * * We know for user-mode we are using TCG so we can call stuff directly. * + * Copyright (c) 2003-2005 Fabrice Bellard * Copyright (c) 2022 Linaro Ltd * - * SPDX-License-Identifier: GPL-2.0-or-later + * SPDX-License-Identifier: LGPL-2.0+ */ #include "qemu/osdep.h" -- 2.34.1 From MAILER-DAEMON Thu Jan 05 11:43:35 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTL4-00070p-UF for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 11:43:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTL2-0006y8-JG for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:43:32 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTKu-0006xM-Sc for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:43:32 -0500 Received: by mail-wr1-x42b.google.com with SMTP id bk16so23489700wrb.11 for ; Thu, 05 Jan 2023 08:43:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Gy0/zYZetKWbyUE6WFREVjvsOrbcepCm3I2qjMJQWPs=; b=bWGIh4n5W0WXN1S+Duq3L8i3fjlHKGKmzaM11j5lC326ME8APPMaCO2+WYAbfMCv/p C6hPzerTl0i1D8oaDV8hYRpUMzolCt8X2JWmnx8FXif1Wxt48j0HwrJKEFpyRZQiFnUm m4YKa5D9Z5cCHSk4LyE/QDQ2Vsrv/vUf11TW7+5ssPiY4a7mPuI5J8GDyhbET9gKNEKw QsPWrYPHXUAogHu1uaX8oQkx1/DNifGffQbYFyx5uWxVcBYZDXijJD4OzoZBR/yjVCbO /TJEgw6RTZtc3VX+tPN+eXbIlISa3bUpMHWoNy32TEkOlv0E71CXFH1kSnabb59LyULf f6fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Gy0/zYZetKWbyUE6WFREVjvsOrbcepCm3I2qjMJQWPs=; b=JIX5VINLcqX3mfRzU8oDYD4d/ZJzqvUSJtaxpZ6MtlUVkBfDTUFljJ9h/4KPr09fRI 1G8rwDCPX6UH2rBjwp9SaRbeRRx64aL1oW/pKlDsEY71D3EHn3zlxg14/mHYNMY40V5/ 9GlylCZTl7PQmBo6OFu8EYyhSOfRGPRQhYZToSO90RSiat+FIaKPTPNWuFn9osw8oe0p 9+zwGeLXyNgCAO88/quCmzrlsXmVY6IRM8PSWzeTC9ZwCtHcxEe27OVkiFlBFLrj6jKe 9Ej+B9f56naQdWttGLVg3dFLcphDq2YtXvAkA/RRjIPNMqg86iL7wb3SwPCgkVKO8jhQ knQQ== X-Gm-Message-State: AFqh2krm/9FGCawjxE8nSzs5Bfjore6+TVBHiwmMFYJHBSFbngn2XKty DC7c2BgfB5RpVj2TdLa49RM/tg== X-Google-Smtp-Source: AMrXdXu7qU9YBK4/mrQHdpveZw8jkJM/B4BWs89GyVnrPAUqTIKKWOVKeqLyd/KpK36Rh55TN84fag== X-Received: by 2002:a5d:5b18:0:b0:28d:f043:490f with SMTP id bx24-20020a5d5b18000000b0028df043490fmr18704223wrb.71.1672937003380; Thu, 05 Jan 2023 08:43:23 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id o15-20020a5d684f000000b00286ad197346sm23886829wrw.70.2023.01.05.08.43.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:43:22 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 9A9361FFBC; Thu, 5 Jan 2023 16:43:20 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH v2 04/21] gdbstub: Make syscall_complete/[gs]et_reg target-agnostic typedefs Date: Thu, 5 Jan 2023 16:43:03 +0000 Message-Id: <20230105164320.2164095-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:43:32 -0000 From: Philippe Mathieu-Daudé Prototypes using gdb_syscall_complete_cb() or gdb_?et_reg_cb() don't depend on "cpu.h", thus are not target-specific. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20221214143659.62133-1-philmd@linaro.org> Signed-off-by: Alex Bennée --- include/exec/gdbstub.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index f667014888..1636fb3841 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -71,9 +71,6 @@ struct gdb_timeval { uint64_t tv_usec; /* microsecond */ } QEMU_PACKED; -#ifdef NEED_CPU_H -#include "cpu.h" - typedef void (*gdb_syscall_complete_cb)(CPUState *cpu, uint64_t ret, int err); /** @@ -126,6 +123,7 @@ int gdb_handlesig(CPUState *, int); void gdb_signalled(CPUArchState *, int); void gdbserver_fork(CPUState *); #endif + /* Get or set a register. Returns the size of the register. */ typedef int (*gdb_get_reg_cb)(CPUArchState *env, GByteArray *buf, int reg); typedef int (*gdb_set_reg_cb)(CPUArchState *env, uint8_t *buf, int reg); @@ -133,6 +131,9 @@ void gdb_register_coprocessor(CPUState *cpu, gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg, int num_regs, const char *xml, int g_pos); +#ifdef NEED_CPU_H +#include "cpu.h" + /* * The GDB remote protocol transfers values in target byte order. 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Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH v2 06/21] gdbstub: move GDBState to shared internals header Date: Thu, 5 Jan 2023 16:43:05 +0000 Message-Id: <20230105164320.2164095-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:43:34 -0000 We are about to split softmmu and user mode helpers into different files. To facilitate this we will need to share access to the GDBState between those files. To keep building we have to temporarily define CONFIG_USER_ONLY just before we include internals.h for the user-mode side of things. This will get removed once the state is fully moved. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée --- gdbstub/internals.h | 69 +++++++++++++++++++++++++++++++++++++++++++++ gdbstub/gdbstub.c | 60 --------------------------------------- gdbstub/softmmu.c | 2 ++ gdbstub/user.c | 2 ++ 4 files changed, 73 insertions(+), 60 deletions(-) diff --git a/gdbstub/internals.h b/gdbstub/internals.h index b444f24ef5..9784db2dc5 100644 --- a/gdbstub/internals.h +++ b/gdbstub/internals.h @@ -9,6 +9,75 @@ #ifndef GDBSTUB_INTERNALS_H #define GDBSTUB_INTERNALS_H +#define MAX_PACKET_LENGTH 4096 + +/* + * Shared structures and definitions + */ + +typedef struct GDBProcess { + uint32_t pid; + bool attached; + + char target_xml[1024]; +} GDBProcess; + +enum RSState { + RS_INACTIVE, + RS_IDLE, + RS_GETLINE, + RS_GETLINE_ESC, + RS_GETLINE_RLE, + RS_CHKSUM1, + RS_CHKSUM2, +}; + +/* Temporary home */ +#ifdef CONFIG_USER_ONLY +typedef struct { + int fd; + char *socket_path; + int running_state; +} GDBUserState; +#else +typedef struct { + CharBackend chr; + Chardev *mon_chr; +} GDBSystemState; +#endif + +typedef struct GDBState { + bool init; /* have we been initialised? */ + CPUState *c_cpu; /* current CPU for step/continue ops */ + CPUState *g_cpu; /* current CPU for other ops */ + CPUState *query_cpu; /* for q{f|s}ThreadInfo */ + enum RSState state; /* parsing state */ + char line_buf[MAX_PACKET_LENGTH]; + int line_buf_index; + int line_sum; /* running checksum */ + int line_csum; /* checksum at the end of the packet */ + GByteArray *last_packet; + int signal; +#ifdef CONFIG_USER_ONLY + GDBUserState user; +#else + GDBSystemState system; +#endif + bool multiprocess; + GDBProcess *processes; + int process_num; + char syscall_buf[256]; + gdb_syscall_complete_cb current_syscall_cb; + GString *str_buf; + GByteArray *mem_buf; + int sstep_flags; + int supported_sstep_flags; +} GDBState; + +/* + * Break/Watch point support - there is an implementation for softmmu + * and user mode. + */ bool gdb_supports_guest_debug(void); int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len); int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len); diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 42ae13b344..505beafad7 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -41,8 +41,6 @@ #include "hw/boards.h" #endif -#define MAX_PACKET_LENGTH 4096 - #include "qemu/sockets.h" #include "sysemu/hw_accel.h" #include "sysemu/runstate.h" @@ -326,64 +324,6 @@ typedef struct GDBRegisterState { struct GDBRegisterState *next; } GDBRegisterState; -typedef struct GDBProcess { - uint32_t pid; - bool attached; - - char target_xml[1024]; -} GDBProcess; - -enum RSState { - RS_INACTIVE, - RS_IDLE, - RS_GETLINE, - RS_GETLINE_ESC, - RS_GETLINE_RLE, - RS_CHKSUM1, - RS_CHKSUM2, -}; - -#ifdef CONFIG_USER_ONLY -typedef struct { - int fd; - char *socket_path; - int running_state; -} GDBUserState; -#else -typedef struct { - CharBackend chr; - Chardev *mon_chr; -} GDBSystemState; -#endif - -typedef struct GDBState { - bool init; /* have we been initialised? */ - CPUState *c_cpu; /* current CPU for step/continue ops */ - CPUState *g_cpu; /* current CPU for other ops */ - CPUState *query_cpu; /* for q{f|s}ThreadInfo */ - enum RSState state; /* parsing state */ - char line_buf[MAX_PACKET_LENGTH]; - int line_buf_index; - int line_sum; /* running checksum */ - int line_csum; /* checksum at the end of the packet */ - GByteArray *last_packet; - int signal; -#ifdef CONFIG_USER_ONLY - GDBUserState user; -#else - GDBSystemState system; -#endif - bool multiprocess; - GDBProcess *processes; - int process_num; - char syscall_buf[256]; - gdb_syscall_complete_cb current_syscall_cb; - GString *str_buf; - GByteArray *mem_buf; - int sstep_flags; - int supported_sstep_flags; -} GDBState; - static GDBState gdbserver_state; static void init_gdbserver_state(void) diff --git a/gdbstub/softmmu.c b/gdbstub/softmmu.c index 183dfb40e4..696894243b 100644 --- a/gdbstub/softmmu.c +++ b/gdbstub/softmmu.c @@ -14,6 +14,8 @@ #include "exec/gdbstub.h" #include "exec/hwaddr.h" #include "sysemu/cpus.h" +#include "chardev/char.h" +#include "chardev/char-fe.h" #include "internals.h" bool gdb_supports_guest_debug(void) diff --git a/gdbstub/user.c b/gdbstub/user.c index a5f370bcf9..4c2b41eefa 100644 --- a/gdbstub/user.c +++ b/gdbstub/user.c @@ -13,6 +13,8 @@ #include "exec/hwaddr.h" #include "exec/gdbstub.h" #include "hw/core/cpu.h" +/* temp hack */ +#define CONFIG_USER_ONLY 1 #include "internals.h" bool gdb_supports_guest_debug(void) -- 2.34.1 From MAILER-DAEMON Thu Jan 05 11:43:38 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTL8-00075g-Gm for mharc-qemu-riscv@gnu.org; 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Thu, 05 Jan 2023 08:43:22 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A9E101FFBD; Thu, 5 Jan 2023 16:43:20 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH v2 05/21] gdbstub: define separate user/system structures Date: Thu, 5 Jan 2023 16:43:04 +0000 Message-Id: <20230105164320.2164095-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:43:37 -0000 In preparation for moving user/softmmu specific bits from the main gdbstub file we need to separate the connection details into a user/softmmu state. These will eventually be defined in their own files. Signed-off-by: Alex Bennée --- gdbstub/gdbstub.c | 91 +++++++++++++++++++++++++++-------------------- 1 file changed, 53 insertions(+), 38 deletions(-) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index be88ca0d71..42ae13b344 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -342,6 +342,20 @@ enum RSState { RS_CHKSUM1, RS_CHKSUM2, }; + +#ifdef CONFIG_USER_ONLY +typedef struct { + int fd; + char *socket_path; + int running_state; +} GDBUserState; +#else +typedef struct { + CharBackend chr; + Chardev *mon_chr; +} GDBSystemState; +#endif + typedef struct GDBState { bool init; /* have we been initialised? */ CPUState *c_cpu; /* current CPU for step/continue ops */ @@ -355,12 +369,9 @@ typedef struct GDBState { GByteArray *last_packet; int signal; #ifdef CONFIG_USER_ONLY - int fd; - char *socket_path; - int running_state; + GDBUserState user; #else - CharBackend chr; - Chardev *mon_chr; + GDBSystemState system; #endif bool multiprocess; GDBProcess *processes; @@ -413,15 +424,17 @@ static int get_char(void) int ret; for(;;) { - ret = recv(gdbserver_state.fd, &ch, 1, 0); + ret = recv(gdbserver_state.user.fd, &ch, 1, 0); if (ret < 0) { - if (errno == ECONNRESET) - gdbserver_state.fd = -1; - if (errno != EINTR) + if (errno == ECONNRESET) { + gdbserver_state.user.fd = -1; + } + if (errno != EINTR) { return -1; + } } else if (ret == 0) { - close(gdbserver_state.fd); - gdbserver_state.fd = -1; + close(gdbserver_state.user.fd); + gdbserver_state.user.fd = -1; return -1; } else { break; @@ -480,7 +493,7 @@ static inline void gdb_continue(void) { #ifdef CONFIG_USER_ONLY - gdbserver_state.running_state = 1; + gdbserver_state.user.running_state = 1; trace_gdbstub_op_continue(); #else if (!runstate_needs_reset()) { @@ -509,7 +522,7 @@ static int gdb_continue_partial(char *newstates) cpu_single_step(cpu, gdbserver_state.sstep_flags); } } - gdbserver_state.running_state = 1; + gdbserver_state.user.running_state = 1; #else int flag = 0; @@ -561,7 +574,7 @@ static void put_buffer(const uint8_t *buf, int len) int ret; while (len > 0) { - ret = send(gdbserver_state.fd, buf, len, 0); + ret = send(gdbserver_state.user.fd, buf, len, 0); if (ret < 0) { if (errno != EINTR) return; @@ -573,7 +586,7 @@ static void put_buffer(const uint8_t *buf, int len) #else /* XXX this blocks entire thread. Rewrite to use * qemu_chr_fe_write and background I/O callbacks */ - qemu_chr_fe_write_all(&gdbserver_state.chr, buf, len); + qemu_chr_fe_write_all(&gdbserver_state.system.chr, buf, len); #endif } @@ -2095,7 +2108,8 @@ static void handle_query_rcmd(GArray *params, void *user_ctx) len = len / 2; hextomem(gdbserver_state.mem_buf, get_param(params, 0)->data, len); g_byte_array_append(gdbserver_state.mem_buf, &zero, 1); - qemu_chr_be_write(gdbserver_state.mon_chr, gdbserver_state.mem_buf->data, + qemu_chr_be_write(gdbserver_state.system.mon_chr, + gdbserver_state.mem_buf->data, gdbserver_state.mem_buf->len); put_packet("OK"); } @@ -3028,10 +3042,10 @@ void gdb_exit(int code) return; } #ifdef CONFIG_USER_ONLY - if (gdbserver_state.socket_path) { - unlink(gdbserver_state.socket_path); + if (gdbserver_state.user.socket_path) { + unlink(gdbserver_state.user.socket_path); } - if (gdbserver_state.fd < 0) { + if (gdbserver_state.user.fd < 0) { return; } #endif @@ -3042,7 +3056,7 @@ void gdb_exit(int code) put_packet(buf); #ifndef CONFIG_USER_ONLY - qemu_chr_fe_deinit(&gdbserver_state.chr, true); + qemu_chr_fe_deinit(&gdbserver_state.system.chr, true); #endif } @@ -3078,7 +3092,7 @@ gdb_handlesig(CPUState *cpu, int sig) char buf[256]; int n; - if (!gdbserver_state.init || gdbserver_state.fd < 0) { + if (!gdbserver_state.init || gdbserver_state.user.fd < 0) { return sig; } @@ -3096,15 +3110,15 @@ gdb_handlesig(CPUState *cpu, int sig) } /* put_packet() might have detected that the peer terminated the connection. */ - if (gdbserver_state.fd < 0) { + if (gdbserver_state.user.fd < 0) { return sig; } sig = 0; gdbserver_state.state = RS_IDLE; - gdbserver_state.running_state = 0; - while (gdbserver_state.running_state == 0) { - n = read(gdbserver_state.fd, buf, 256); + gdbserver_state.user.running_state = 0; + while (gdbserver_state.user.running_state == 0) { + n = read(gdbserver_state.user.fd, buf, 256); if (n > 0) { int i; @@ -3115,9 +3129,9 @@ gdb_handlesig(CPUState *cpu, int sig) /* XXX: Connection closed. Should probably wait for another connection before continuing. */ if (n == 0) { - close(gdbserver_state.fd); + close(gdbserver_state.user.fd); } - gdbserver_state.fd = -1; + gdbserver_state.user.fd = -1; return sig; } } @@ -3131,7 +3145,7 @@ void gdb_signalled(CPUArchState *env, int sig) { char buf[4]; - if (!gdbserver_state.init || gdbserver_state.fd < 0) { + if (!gdbserver_state.init || gdbserver_state.user.fd < 0) { return; } @@ -3146,7 +3160,7 @@ static void gdb_accept_init(int fd) gdbserver_state.processes[0].attached = true; gdbserver_state.c_cpu = gdb_first_attached_cpu(); gdbserver_state.g_cpu = gdbserver_state.c_cpu; - gdbserver_state.fd = fd; + gdbserver_state.user.fd = fd; gdb_has_xml = false; } @@ -3278,7 +3292,7 @@ int gdbserver_start(const char *port_or_path) if (port > 0 && gdb_accept_tcp(gdb_fd)) { return 0; } else if (gdb_accept_socket(gdb_fd)) { - gdbserver_state.socket_path = g_strdup(port_or_path); + gdbserver_state.user.socket_path = g_strdup(port_or_path); return 0; } @@ -3290,11 +3304,11 @@ int gdbserver_start(const char *port_or_path) /* Disable gdb stub for child processes. */ void gdbserver_fork(CPUState *cpu) { - if (!gdbserver_state.init || gdbserver_state.fd < 0) { + if (!gdbserver_state.init || gdbserver_state.user.fd < 0) { return; } - close(gdbserver_state.fd); - gdbserver_state.fd = -1; + close(gdbserver_state.user.fd); + gdbserver_state.user.fd = -1; cpu_breakpoint_remove_all(cpu, BP_GDB); cpu_watchpoint_remove_all(cpu, BP_GDB); } @@ -3488,21 +3502,22 @@ int gdbserver_start(const char *device) NULL, NULL, &error_abort); monitor_init_hmp(mon_chr, false, &error_abort); } else { - qemu_chr_fe_deinit(&gdbserver_state.chr, true); - mon_chr = gdbserver_state.mon_chr; + qemu_chr_fe_deinit(&gdbserver_state.system.chr, true); + mon_chr = gdbserver_state.system.mon_chr; reset_gdbserver_state(); } create_processes(&gdbserver_state); if (chr) { - qemu_chr_fe_init(&gdbserver_state.chr, chr, &error_abort); - qemu_chr_fe_set_handlers(&gdbserver_state.chr, gdb_chr_can_receive, + qemu_chr_fe_init(&gdbserver_state.system.chr, chr, &error_abort); + qemu_chr_fe_set_handlers(&gdbserver_state.system.chr, + gdb_chr_can_receive, gdb_chr_receive, gdb_chr_event, NULL, &gdbserver_state, NULL, true); } gdbserver_state.state = chr ? RS_IDLE : RS_INACTIVE; - gdbserver_state.mon_chr = mon_chr; + gdbserver_state.system.mon_chr = mon_chr; gdbserver_state.current_syscall_cb = NULL; return 0; -- 2.34.1 From MAILER-DAEMON Thu Jan 05 11:43:40 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTLA-0007A0-CL for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 11:43:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTL8-00077t-T8 for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:43:38 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTKw-0006yu-TF for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:43:38 -0500 Received: by mail-wm1-x330.google.com with SMTP id k22-20020a05600c1c9600b003d1ee3a6289so1777086wms.2 for ; Thu, 05 Jan 2023 08:43:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EerVrIzCjfEKyD8t5zQfya8CKSRP1ftyfpksI7gVAwM=; b=CxU5F4HjJ+2g0oQG+sF5FcV4SezpLQEE9xea3C4OjSkIjoctUdqXTkxRiSJt3hJq5O 5LPhjmugtEYEMBt/hVNBB6EjDBDkBDonmuRlxL67Zn3sf0WGX4XmglPhwxgaVTpOTopr y8xQZO0hzRiSzEJgf7NMQH7sQLuBhoobKqA1QoRiDdzCOXn9fJEvZoJuJhd/RwBYZuND giaHlkx9qzC/xFzAI7mL6WfvJA4EhzOCjHtoQeuUSIytBlC4Ydzj0TauVNjIey5M32Az GEQ8u13b1GVPSu06SWg1Tdlh1rBy7GFMTpwXZe9S5pUXL+2c+r/eoAACtSfDOHrHdMfx NpPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EerVrIzCjfEKyD8t5zQfya8CKSRP1ftyfpksI7gVAwM=; b=HBPvv4BZV77etoMMfH1/Dw5+ziGPEbXbRBHhqZukFjHaz2MllL99OC7P71++PNppws ocbMLhf8HrsuQ74UmpjiE6PkDO0Q/On8UmL3CXFKMzXeFAWVVc/mqY8lCW/x5AtPATtz ipN6YF8cRPqgQQwRzrEePFBgVT4dle1Ro8Q1GgTI8h6ttoEqXAdJ7wIDelAfsaYBccr9 3QuxdA9jzmIlW+aojjjlmOJHKXJu5s6EtdZYS6+yNjxfkWwLa8wIWEJN+hJ0vFk5muco cz8oP+epAdrJZoHthwPENQN1Euz20/jodZgc/tOg7y4P/FnHBWkaM1CPMZ/IB32UaLH/ pdjQ== X-Gm-Message-State: AFqh2kpplIW3vt0LCDp8TrYUIrp3dW22cOtPaN+z4PZvdsATFkYjstU+ frzRAOjwYOlP4JCOyE9dYjigyA== X-Google-Smtp-Source: AMrXdXu5GQDCs1bWMtTlFUIwDsLBYsYCXOLBriFth+j+29zcTa918VF3G3yJzwew37xJbfc8yOMkRg== X-Received: by 2002:a05:600c:b4d:b0:3d3:5d69:7aa5 with SMTP id k13-20020a05600c0b4d00b003d35d697aa5mr35344276wmr.25.1672937005143; Thu, 05 Jan 2023 08:43:25 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id n14-20020a05600c3b8e00b003b49bd61b19sm3366476wms.15.2023.01.05.08.43.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:43:22 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id D77B01FFC0; Thu, 5 Jan 2023 16:43:20 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH v2 08/21] gdbstub: move fromhex/tohex routines to internals Date: Thu, 5 Jan 2023 16:43:07 +0000 Message-Id: <20230105164320.2164095-9-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:43:39 -0000 These will be needed from multiple places in the code. They are declared as inline so move to the header and fix up to modern coding style. The only other place that messes with hex stuff at the moment is the URI handling in utils but that would be more code churn so leave for now. Signed-off-by: Alex Bennée --- gdbstub/internals.h | 27 +++++++++++++++++++++++++++ gdbstub/gdbstub.c | 20 -------------------- 2 files changed, 27 insertions(+), 20 deletions(-) diff --git a/gdbstub/internals.h b/gdbstub/internals.h index 9784db2dc5..c8bb85cf34 100644 --- a/gdbstub/internals.h +++ b/gdbstub/internals.h @@ -74,6 +74,33 @@ typedef struct GDBState { int supported_sstep_flags; } GDBState; + +/* + * Inline utility function, convert from int to hex and back + */ + +static inline int fromhex(int v) +{ + if (v >= '0' && v <= '9') { + return v - '0'; + } else if (v >= 'A' && v <= 'F') { + return v - 'A' + 10; + } else if (v >= 'a' && v <= 'f') { + return v - 'a' + 10; + } else { + return 0; + } +} + +static inline int tohex(int v) +{ + if (v < 10) { + return v + '0'; + } else { + return v - 10 + 'a'; + } +} + /* * Break/Watch point support - there is an implementation for softmmu * and user mode. diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 92b2f5c3db..d4ee23b51c 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -531,26 +531,6 @@ static void put_buffer(const uint8_t *buf, int len) #endif } -static inline int fromhex(int v) -{ - if (v >= '0' && v <= '9') - return v - '0'; - else if (v >= 'A' && v <= 'F') - return v - 'A' + 10; - else if (v >= 'a' && v <= 'f') - return v - 'a' + 10; - else - return 0; -} - -static inline int tohex(int v) -{ - if (v < 10) - return v + '0'; - else - return v - 10 + 'a'; -} - /* writes 2*len+1 bytes in buf */ static void memtohex(GString *buf, const uint8_t *mem, int len) { -- 2.34.1 From MAILER-DAEMON Thu Jan 05 11:43:45 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTLB-0007Bb-Ri for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 11:43:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTL8-00077z-Tw for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:43:38 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTKw-0006yR-Ra for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:43:38 -0500 Received: by mail-wm1-x330.google.com with SMTP id c65-20020a1c3544000000b003cfffd00fc0so1750092wma.1 for ; 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Thu, 05 Jan 2023 08:43:24 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id r7-20020a05600c458700b003c6b7f5567csm8330565wmo.0.2023.01.05.08.43.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:43:22 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id C91621FFBF; Thu, 5 Jan 2023 16:43:20 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH v2 07/21] includes: move tb_flush into its own header Date: Thu, 5 Jan 2023 16:43:06 +0000 Message-Id: <20230105164320.2164095-8-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:43:39 -0000 This aids subsystems (like gdbstub) that want to trigger a flush without pulling target specific headers. Reviewed-by: Richard Henderson Signed-off-by: Alex Bennée --- v2 - actually include the header and rename to tb-flush.h - better kerneldoc style comment for the function --- include/exec/exec-all.h | 1 - include/exec/tb-flush.h | 26 ++++++++++++++++++++++++++ linux-user/user-internals.h | 1 + accel/stubs/tcg-stub.c | 1 + accel/tcg/tb-maint.c | 1 + accel/tcg/translate-all.c | 1 + cpu.c | 1 + gdbstub/gdbstub.c | 1 + hw/ppc/spapr_hcall.c | 1 + plugins/core.c | 1 + plugins/loader.c | 2 +- target/alpha/sys_helper.c | 1 + target/riscv/csr.c | 1 + 13 files changed, 37 insertions(+), 2 deletions(-) create mode 100644 include/exec/tb-flush.h diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 25e11b0a8d..b4a893648c 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -685,7 +685,6 @@ void tb_invalidate_phys_addr(target_ulong addr); #else void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs); #endif -void tb_flush(CPUState *cpu); void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t end); void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); diff --git a/include/exec/tb-flush.h b/include/exec/tb-flush.h new file mode 100644 index 0000000000..d92d06565b --- /dev/null +++ b/include/exec/tb-flush.h @@ -0,0 +1,26 @@ +/* + * tb-flush prototype for use by the rest of the system. + * + * Copyright (c) 2022 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef _TB_FLUSH_H_ +#define _TB_FLUSH_H_ + +/** + * tb_flush() - flush all translation blocks + * @cs: CPUState (must be valid, but treated as anonymous pointer) + * + * Used to flush all the translation blocks in the system. Sometimes + * it is simpler to flush everything than work out which individual + * translations are now invalid and ensure they are not called + * anymore. + * + * tb_flush() takes care of running the flush in an exclusive context + * if it is not already running in one. This means no guest code will + * run until this complete. + */ +void tb_flush(CPUState *cs); + +#endif /* _TB_FLUSH_H_ */ diff --git a/linux-user/user-internals.h b/linux-user/user-internals.h index 0280e76add..ea11549c41 100644 --- a/linux-user/user-internals.h +++ b/linux-user/user-internals.h @@ -20,6 +20,7 @@ #include "exec/user/thunk.h" #include "exec/exec-all.h" +#include "exec/tb-flush.h" #include "qemu/log.h" extern char *exec_path; diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c index c1b05767c0..e0d371c3a7 100644 --- a/accel/stubs/tcg-stub.c +++ b/accel/stubs/tcg-stub.c @@ -11,6 +11,7 @@ */ #include "qemu/osdep.h" +#include "exec/tb-flush.h" #include "exec/exec-all.h" void tb_flush(CPUState *cpu) diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index 1b8e860647..1d7435bfc2 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -22,6 +22,7 @@ #include "exec/cputlb.h" #include "exec/log.h" #include "exec/exec-all.h" +#include "exec/tb-flush.h" #include "exec/translate-all.h" #include "sysemu/tcg.h" #include "tcg/tcg.h" diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 51ac1f6c84..ff7cc87f1f 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -47,6 +47,7 @@ #include "exec/cputlb.h" #include "exec/translate-all.h" #include "exec/translator.h" +#include "exec/tb-flush.h" #include "qemu/bitmap.h" #include "qemu/qemu-print.h" #include "qemu/timer.h" diff --git a/cpu.c b/cpu.c index 4a7d865427..1a374ac4a8 100644 --- a/cpu.c +++ b/cpu.c @@ -36,6 +36,7 @@ #include "sysemu/replay.h" #include "exec/cpu-common.h" #include "exec/exec-all.h" +#include "exec/tb-flush.h" #include "exec/translate-all.h" #include "exec/log.h" #include "hw/core/accel-cpu.h" diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 505beafad7..92b2f5c3db 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -46,6 +46,7 @@ #include "sysemu/runstate.h" #include "semihosting/semihost.h" #include "exec/exec-all.h" +#include "exec/tb-flush.h" #include "exec/hwaddr.h" #include "sysemu/replay.h" diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 925ff523cc..ec4def62f8 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -8,6 +8,7 @@ #include "qemu/module.h" #include "qemu/error-report.h" #include "exec/exec-all.h" +#include "exec/tb-flush.h" #include "helper_regs.h" #include "hw/ppc/ppc.h" #include "hw/ppc/spapr.h" diff --git a/plugins/core.c b/plugins/core.c index ccb770a485..584b5f3c5e 100644 --- a/plugins/core.c +++ b/plugins/core.c @@ -24,6 +24,7 @@ #include "exec/cpu-common.h" #include "exec/exec-all.h" +#include "exec/tb-flush.h" #include "exec/helper-proto.h" #include "tcg/tcg.h" #include "tcg/tcg-op.h" diff --git a/plugins/loader.c b/plugins/loader.c index 88c30bde2d..809f3f9b13 100644 --- a/plugins/loader.c +++ b/plugins/loader.c @@ -29,7 +29,7 @@ #include "qemu/plugin.h" #include "qemu/memalign.h" #include "hw/core/cpu.h" -#include "exec/exec-all.h" +#include "exec/tb-flush.h" #ifndef CONFIG_USER_ONLY #include "hw/boards.h" #endif diff --git a/target/alpha/sys_helper.c b/target/alpha/sys_helper.c index 25f6cb8894..c83c92dd4c 100644 --- a/target/alpha/sys_helper.c +++ b/target/alpha/sys_helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/exec-all.h" +#include "exec/tb-flush.h" #include "exec/helper-proto.h" #include "sysemu/runstate.h" #include "sysemu/sysemu.h" diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5c9a7ee287..b02a536bbc 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -25,6 +25,7 @@ #include "time_helper.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" +#include "exec/tb-flush.h" #include "sysemu/cpu-timers.h" #include "qemu/guest-random.h" #include "qapi/error.h" -- 2.34.1 From MAILER-DAEMON Thu Jan 05 11:43:53 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTLL-0007Ip-VT for mharc-qemu-riscv@gnu.org; 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Thu, 05 Jan 2023 08:43:23 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 0CFD01FFC2; Thu, 5 Jan 2023 16:43:21 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org, Fabiano Rosas Subject: [PATCH v2 10/21] gdbstub: move chunk of softmmu functionality to own file Date: Thu, 5 Jan 2023 16:43:09 +0000 Message-Id: <20230105164320.2164095-11-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:43:45 -0000 This is mostly code motion but a number of things needed to be done for this minimal patch set: - move shared structures to internals.h - splitting some functions into user and softmmu versions - fixing a few casting issues to keep softmmu common More CONFIG_USER_ONLY stuff will be handled in a following patches. Reviewed-by: Fabiano Rosas Signed-off-by: Alex Bennée --- gdbstub/internals.h | 48 ++++- gdbstub/gdbstub.c | 415 ++---------------------------------------- gdbstub/softmmu.c | 416 +++++++++++++++++++++++++++++++++++++++++++ gdbstub/trace-events | 4 +- 4 files changed, 469 insertions(+), 414 deletions(-) diff --git a/gdbstub/internals.h b/gdbstub/internals.h index 670bd01a1d..bbdc660233 100644 --- a/gdbstub/internals.h +++ b/gdbstub/internals.h @@ -15,6 +15,18 @@ * Shared structures and definitions */ +enum { + GDB_SIGNAL_0 = 0, + GDB_SIGNAL_INT = 2, + GDB_SIGNAL_QUIT = 3, + GDB_SIGNAL_TRAP = 5, + GDB_SIGNAL_ABRT = 6, + GDB_SIGNAL_ALRM = 14, + GDB_SIGNAL_IO = 23, + GDB_SIGNAL_XCPU = 24, + GDB_SIGNAL_UNKNOWN = 143 +}; + typedef struct GDBProcess { uint32_t pid; bool attached; @@ -39,11 +51,6 @@ typedef struct { char *socket_path; int running_state; } GDBUserState; -#else -typedef struct { - CharBackend chr; - Chardev *mon_chr; -} GDBSystemState; #endif typedef struct GDBState { @@ -60,8 +67,6 @@ typedef struct GDBState { int signal; #ifdef CONFIG_USER_ONLY GDBUserState user; -#else - GDBSystemState system; #endif bool multiprocess; GDBProcess *processes; @@ -118,7 +123,6 @@ CPUState *gdb_first_attached_cpu(void); void gdb_append_thread_id(CPUState *cpu, GString *buf); int gdb_get_cpu_index(CPUState *cpu); -void gdb_init_gdbserver_state(void); void gdb_create_default_process(GDBState *s); /* @@ -126,6 +130,34 @@ void gdb_create_default_process(GDBState *s); */ void gdb_put_buffer(const uint8_t *buf, int len); +/* + * Command handlers - either softmmu or user only + */ +void gdb_init_gdbserver_state(void); + +typedef enum GDBThreadIdKind { + GDB_ONE_THREAD = 0, + GDB_ALL_THREADS, /* One process, all threads */ + GDB_ALL_PROCESSES, + GDB_READ_THREAD_ERR +} GDBThreadIdKind; + +typedef union GdbCmdVariant { + const char *data; + uint8_t opcode; + unsigned long val_ul; + unsigned long long val_ull; + struct { + GDBThreadIdKind kind; + uint32_t pid; + uint32_t tid; + } thread_id; +} GdbCmdVariant; + +#define get_param(p, i) (&g_array_index(p, GdbCmdVariant, i)) + +void gdb_handle_query_rcmd(GArray *params, void *user_ctx); /* softmmu */ + /* * Break/Watch point support - there is an implementation for softmmu * and user mode. diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 9c347cd84b..d9afee5879 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -24,8 +24,6 @@ */ #include "qemu/osdep.h" -#include "qapi/error.h" -#include "qemu/error-report.h" #include "qemu/ctype.h" #include "qemu/cutils.h" #include "qemu/module.h" @@ -34,9 +32,6 @@ #ifdef CONFIG_USER_ONLY #include "qemu.h" #else -#include "monitor/monitor.h" -#include "chardev/char.h" -#include "chardev/char-fe.h" #include "hw/cpu/cluster.h" #include "hw/boards.h" #endif @@ -88,30 +83,15 @@ static inline int target_memory_rw_debug(CPUState *cpu, target_ulong addr, /* * Return the GDB index for a given vCPU state. * - * For user mode this is simply the thread id. In system mode GDB - * numbers CPUs from 1 as 0 is reserved as an "any cpu" index. + * For user mode this is simply the thread id. */ +#if defined(CONFIG_USER_ONLY) int gdb_get_cpu_index(CPUState *cpu) { -#if defined(CONFIG_USER_ONLY) TaskState *ts = (TaskState *) cpu->opaque; return ts ? ts->ts_tid : -1; -#else - return cpu->cpu_index + 1; -#endif } - -enum { - GDB_SIGNAL_0 = 0, - GDB_SIGNAL_INT = 2, - GDB_SIGNAL_QUIT = 3, - GDB_SIGNAL_TRAP = 5, - GDB_SIGNAL_ABRT = 6, - GDB_SIGNAL_ALRM = 14, - GDB_SIGNAL_IO = 23, - GDB_SIGNAL_XCPU = 24, - GDB_SIGNAL_UNKNOWN = 143 -}; +#endif #ifdef CONFIG_USER_ONLY @@ -326,7 +306,7 @@ typedef struct GDBRegisterState { struct GDBRegisterState *next; } GDBRegisterState; -static GDBState gdbserver_state; +GDBState gdbserver_state; void gdb_init_gdbserver_state(void) { @@ -347,15 +327,6 @@ void gdb_init_gdbserver_state(void) gdbserver_state.sstep_flags &= gdbserver_state.supported_sstep_flags; } -#ifndef CONFIG_USER_ONLY -static void reset_gdbserver_state(void) -{ - g_free(gdbserver_state.processes); - gdbserver_state.processes = NULL; - gdbserver_state.process_num = 0; -} -#endif - bool gdb_has_xml; #ifdef CONFIG_USER_ONLY @@ -431,7 +402,7 @@ static bool stub_can_reverse(void) } /* Resume execution. */ -static inline void gdb_continue(void) +static void gdb_continue(void) { #ifdef CONFIG_USER_ONLY @@ -510,9 +481,9 @@ static int gdb_continue_partial(char *newstates) return res; } +#ifdef CONFIG_USER_ONLY void gdb_put_buffer(const uint8_t *buf, int len) { -#ifdef CONFIG_USER_ONLY int ret; while (len > 0) { @@ -525,12 +496,8 @@ void gdb_put_buffer(const uint8_t *buf, int len) len -= ret; } } -#else - /* XXX this blocks entire thread. Rewrite to use - * qemu_chr_fe_write and background I/O callbacks */ - qemu_chr_fe_write_all(&gdbserver_state.system.chr, buf, len); -#endif } +#endif /* writes 2*len+1 bytes in buf */ void gdb_memtohex(GString *buf, const uint8_t *mem, int len) @@ -978,13 +945,6 @@ void gdb_append_thread_id(CPUState *cpu, GString *buf) } } -typedef enum GDBThreadIdKind { - GDB_ONE_THREAD = 0, - GDB_ALL_THREADS, /* One process, all threads */ - GDB_ALL_PROCESSES, - GDB_READ_THREAD_ERR -} GDBThreadIdKind; - static GDBThreadIdKind read_thread_id(const char *buf, const char **end_buf, uint32_t *pid, uint32_t *tid) { @@ -1165,20 +1125,6 @@ out: return res; } -typedef union GdbCmdVariant { - const char *data; - uint8_t opcode; - unsigned long val_ul; - unsigned long long val_ull; - struct { - GDBThreadIdKind kind; - uint32_t pid; - uint32_t tid; - } thread_id; -} GdbCmdVariant; - -#define get_param(p, i) (&g_array_index(p, GdbCmdVariant, i)) - static const char *cmd_next_param(const char *param, const char delimiter) { static const char all_delimiters[] = ",;:="; @@ -2009,32 +1955,6 @@ static void handle_query_offsets(GArray *params, void *user_ctx) ts->info->data_offset); gdb_put_strbuf(); } -#else -static void handle_query_rcmd(GArray *params, void *user_ctx) -{ - const guint8 zero = 0; - int len; - - if (!params->len) { - gdb_put_packet("E22"); - return; - } - - len = strlen(get_param(params, 0)->data); - if (len % 2) { - gdb_put_packet("E01"); - return; - } - - g_assert(gdbserver_state.mem_buf->len == 0); - len = len / 2; - gdb_hextomem(gdbserver_state.mem_buf, get_param(params, 0)->data, len); - g_byte_array_append(gdbserver_state.mem_buf, &zero, 1); - qemu_chr_be_write(gdbserver_state.system.mon_chr, - gdbserver_state.mem_buf->data, - gdbserver_state.mem_buf->len); - gdb_put_packet("OK"); -} #endif static void handle_query_supported(GArray *params, void *user_ctx) @@ -2248,7 +2168,7 @@ static const GdbCmdParseEntry gdb_gen_query_table[] = { }, #else { - .handler = handle_query_rcmd, + .handler = gdb_handle_query_rcmd, .cmd = "Rcmd,", .cmd_startswith = 1, .schema = "s0" @@ -2632,100 +2552,6 @@ void gdb_set_stop_cpu(CPUState *cpu) gdbserver_state.g_cpu = cpu; } -#ifndef CONFIG_USER_ONLY -static void gdb_vm_state_change(void *opaque, bool running, RunState state) -{ - CPUState *cpu = gdbserver_state.c_cpu; - g_autoptr(GString) buf = g_string_new(NULL); - g_autoptr(GString) tid = g_string_new(NULL); - const char *type; - int ret; - - if (running || gdbserver_state.state == RS_INACTIVE) { - return; - } - /* Is there a GDB syscall waiting to be sent? */ - if (gdbserver_state.current_syscall_cb) { - gdb_put_packet(gdbserver_state.syscall_buf); - return; - } - - if (cpu == NULL) { - /* No process attached */ - return; - } - - gdb_append_thread_id(cpu, tid); - - switch (state) { - case RUN_STATE_DEBUG: - if (cpu->watchpoint_hit) { - switch (cpu->watchpoint_hit->flags & BP_MEM_ACCESS) { - case BP_MEM_READ: - type = "r"; - break; - case BP_MEM_ACCESS: - type = "a"; - break; - default: - type = ""; - break; - } - trace_gdbstub_hit_watchpoint(type, gdb_get_cpu_index(cpu), - (target_ulong)cpu->watchpoint_hit->vaddr); - g_string_printf(buf, "T%02xthread:%s;%swatch:" TARGET_FMT_lx ";", - GDB_SIGNAL_TRAP, tid->str, type, - (target_ulong)cpu->watchpoint_hit->vaddr); - cpu->watchpoint_hit = NULL; - goto send_packet; - } else { - trace_gdbstub_hit_break(); - } - tb_flush(cpu); - ret = GDB_SIGNAL_TRAP; - break; - case RUN_STATE_PAUSED: - trace_gdbstub_hit_paused(); - ret = GDB_SIGNAL_INT; - break; - case RUN_STATE_SHUTDOWN: - trace_gdbstub_hit_shutdown(); - ret = GDB_SIGNAL_QUIT; - break; - case RUN_STATE_IO_ERROR: - trace_gdbstub_hit_io_error(); - ret = GDB_SIGNAL_IO; - break; - case RUN_STATE_WATCHDOG: - trace_gdbstub_hit_watchdog(); - ret = GDB_SIGNAL_ALRM; - break; - case RUN_STATE_INTERNAL_ERROR: - trace_gdbstub_hit_internal_error(); - ret = GDB_SIGNAL_ABRT; - break; - case RUN_STATE_SAVE_VM: - case RUN_STATE_RESTORE_VM: - return; - case RUN_STATE_FINISH_MIGRATE: - ret = GDB_SIGNAL_XCPU; - break; - default: - trace_gdbstub_hit_unknown(state); - ret = GDB_SIGNAL_UNKNOWN; - break; - } - gdb_set_stop_cpu(cpu); - g_string_printf(buf, "T%02xthread:%s;", ret, tid->str); - -send_packet: - gdb_put_packet(buf->str); - - /* disable single step if it was enabled */ - cpu_single_step(cpu, 0); -} -#endif - /* Send a gdb syscall request. This accepts limited printf-style format specifiers, specifically: %x - target_ulong argument printed in hex. @@ -2955,6 +2781,7 @@ void gdb_read_byte(uint8_t ch) } } +#ifdef CONFIG_USER_ONLY /* Tell the remote gdb that the process has exited. */ void gdb_exit(int code) { @@ -2963,24 +2790,19 @@ void gdb_exit(int code) if (!gdbserver_state.init) { return; } -#ifdef CONFIG_USER_ONLY if (gdbserver_state.user.socket_path) { unlink(gdbserver_state.user.socket_path); } if (gdbserver_state.user.fd < 0) { return; } -#endif trace_gdbstub_op_exiting((uint8_t)code); snprintf(buf, sizeof(buf), "W%02x", (uint8_t)code); gdb_put_packet(buf); - -#ifndef CONFIG_USER_ONLY - qemu_chr_fe_deinit(&gdbserver_state.system.chr, true); -#endif } +#endif /* * Create the process that will contain all the "orphan" CPUs (that are not @@ -3234,221 +3056,4 @@ void gdbserver_fork(CPUState *cpu) cpu_breakpoint_remove_all(cpu, BP_GDB); cpu_watchpoint_remove_all(cpu, BP_GDB); } -#else -static int gdb_chr_can_receive(void *opaque) -{ - /* We can handle an arbitrarily large amount of data. - Pick the maximum packet size, which is as good as anything. */ - return MAX_PACKET_LENGTH; -} - -static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size) -{ - int i; - - for (i = 0; i < size; i++) { - gdb_read_byte(buf[i]); - } -} - -static void gdb_chr_event(void *opaque, QEMUChrEvent event) -{ - int i; - GDBState *s = (GDBState *) opaque; - - switch (event) { - case CHR_EVENT_OPENED: - /* Start with first process attached, others detached */ - for (i = 0; i < s->process_num; i++) { - s->processes[i].attached = !i; - } - - s->c_cpu = gdb_first_attached_cpu(); - s->g_cpu = s->c_cpu; - - vm_stop(RUN_STATE_PAUSED); - replay_gdb_attached(); - gdb_has_xml = false; - break; - default: - break; - } -} - -static int gdb_monitor_write(Chardev *chr, const uint8_t *buf, int len) -{ - g_autoptr(GString) hex_buf = g_string_new("O"); - gdb_memtohex(hex_buf, buf, len); - gdb_put_packet(hex_buf->str); - return len; -} - -#ifndef _WIN32 -static void gdb_sigterm_handler(int signal) -{ - if (runstate_is_running()) { - vm_stop(RUN_STATE_PAUSED); - } -} -#endif - -static void gdb_monitor_open(Chardev *chr, ChardevBackend *backend, - bool *be_opened, Error **errp) -{ - *be_opened = false; -} - -static void char_gdb_class_init(ObjectClass *oc, void *data) -{ - ChardevClass *cc = CHARDEV_CLASS(oc); - - cc->internal = true; - cc->open = gdb_monitor_open; - cc->chr_write = gdb_monitor_write; -} - -#define TYPE_CHARDEV_GDB "chardev-gdb" - -static const TypeInfo char_gdb_type_info = { - .name = TYPE_CHARDEV_GDB, - .parent = TYPE_CHARDEV, - .class_init = char_gdb_class_init, -}; - -static int find_cpu_clusters(Object *child, void *opaque) -{ - if (object_dynamic_cast(child, TYPE_CPU_CLUSTER)) { - GDBState *s = (GDBState *) opaque; - CPUClusterState *cluster = CPU_CLUSTER(child); - GDBProcess *process; - - s->processes = g_renew(GDBProcess, s->processes, ++s->process_num); - - process = &s->processes[s->process_num - 1]; - - /* - * GDB process IDs -1 and 0 are reserved. To avoid subtle errors at - * runtime, we enforce here that the machine does not use a cluster ID - * that would lead to PID 0. - */ - assert(cluster->cluster_id != UINT32_MAX); - process->pid = cluster->cluster_id + 1; - process->attached = false; - process->target_xml[0] = '\0'; - - return 0; - } - - return object_child_foreach(child, find_cpu_clusters, opaque); -} - -static int pid_order(const void *a, const void *b) -{ - GDBProcess *pa = (GDBProcess *) a; - GDBProcess *pb = (GDBProcess *) b; - - if (pa->pid < pb->pid) { - return -1; - } else if (pa->pid > pb->pid) { - return 1; - } else { - return 0; - } -} - -static void create_processes(GDBState *s) -{ - object_child_foreach(object_get_root(), find_cpu_clusters, s); - - if (gdbserver_state.processes) { - /* Sort by PID */ - qsort(gdbserver_state.processes, gdbserver_state.process_num, sizeof(gdbserver_state.processes[0]), pid_order); - } - - gdb_create_default_process(s); -} - -int gdbserver_start(const char *device) -{ - trace_gdbstub_op_start(device); - - char gdbstub_device_name[128]; - Chardev *chr = NULL; - Chardev *mon_chr; - - if (!first_cpu) { - error_report("gdbstub: meaningless to attach gdb to a " - "machine without any CPU."); - return -1; - } - - if (!gdb_supports_guest_debug()) { - error_report("gdbstub: current accelerator doesn't support guest debugging"); - return -1; - } - - if (!device) - return -1; - if (strcmp(device, "none") != 0) { - if (strstart(device, "tcp:", NULL)) { - /* enforce required TCP attributes */ - snprintf(gdbstub_device_name, sizeof(gdbstub_device_name), - "%s,wait=off,nodelay=on,server=on", device); - device = gdbstub_device_name; - } -#ifndef _WIN32 - else if (strcmp(device, "stdio") == 0) { - struct sigaction act; - - memset(&act, 0, sizeof(act)); - act.sa_handler = gdb_sigterm_handler; - sigaction(SIGINT, &act, NULL); - } -#endif - /* - * FIXME: it's a bit weird to allow using a mux chardev here - * and implicitly setup a monitor. We may want to break this. - */ - chr = qemu_chr_new_noreplay("gdb", device, true, NULL); - if (!chr) - return -1; - } - - if (!gdbserver_state.init) { - gdb_init_gdbserver_state(); - - qemu_add_vm_change_state_handler(gdb_vm_state_change, NULL); - - /* Initialize a monitor terminal for gdb */ - mon_chr = qemu_chardev_new(NULL, TYPE_CHARDEV_GDB, - NULL, NULL, &error_abort); - monitor_init_hmp(mon_chr, false, &error_abort); - } else { - qemu_chr_fe_deinit(&gdbserver_state.system.chr, true); - mon_chr = gdbserver_state.system.mon_chr; - reset_gdbserver_state(); - } - - create_processes(&gdbserver_state); - - if (chr) { - qemu_chr_fe_init(&gdbserver_state.system.chr, chr, &error_abort); - qemu_chr_fe_set_handlers(&gdbserver_state.system.chr, - gdb_chr_can_receive, - gdb_chr_receive, gdb_chr_event, - NULL, &gdbserver_state, NULL, true); - } - gdbserver_state.state = chr ? RS_IDLE : RS_INACTIVE; - gdbserver_state.system.mon_chr = mon_chr; - gdbserver_state.current_syscall_cb = NULL; - - return 0; -} - -static void register_types(void) -{ - type_register_static(&char_gdb_type_info); -} - -type_init(register_types); #endif diff --git a/gdbstub/softmmu.c b/gdbstub/softmmu.c index 696894243b..3a88d0ebb4 100644 --- a/gdbstub/softmmu.c +++ b/gdbstub/softmmu.c @@ -11,13 +11,429 @@ */ #include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/cutils.h" #include "exec/gdbstub.h" #include "exec/hwaddr.h" +#include "exec/tb-flush.h" #include "sysemu/cpus.h" +#include "sysemu/runstate.h" +#include "sysemu/replay.h" +#include "hw/core/cpu.h" +#include "hw/cpu/cluster.h" +#include "hw/boards.h" #include "chardev/char.h" #include "chardev/char-fe.h" +#include "monitor/monitor.h" +#include "trace.h" #include "internals.h" +/* Common state */ +extern GDBState gdbserver_state; + +/* System emulation specific state */ +typedef struct { + CharBackend chr; + Chardev *mon_chr; +} GDBSystemState; + +GDBSystemState gdbserver_system_state; + +static void reset_gdbserver_state(void) +{ + g_free(gdbserver_state.processes); + gdbserver_state.processes = NULL; + gdbserver_state.process_num = 0; +} + +/* + * Return the GDB index for a given vCPU state. + * + * In system mode GDB numbers CPUs from 1 as 0 is reserved as an "any + * cpu" index. + */ +int gdb_get_cpu_index(CPUState *cpu) +{ + return cpu->cpu_index + 1; +} + +/* + * GDB Connection management. For system emulation we do all of this + * via our existing Chardev infrastructure which allows us to support + * network and unix sockets. + */ + +void gdb_put_buffer(const uint8_t *buf, int len) +{ + /* XXX this blocks entire thread. Rewrite to use + * qemu_chr_fe_write and background I/O callbacks */ + qemu_chr_fe_write_all(&gdbserver_system_state.chr, buf, len); +} + +static void gdb_chr_event(void *opaque, QEMUChrEvent event) +{ + int i; + GDBState *s = (GDBState *) opaque; + + switch (event) { + case CHR_EVENT_OPENED: + /* Start with first process attached, others detached */ + for (i = 0; i < s->process_num; i++) { + s->processes[i].attached = !i; + } + + s->c_cpu = gdb_first_attached_cpu(); + s->g_cpu = s->c_cpu; + + vm_stop(RUN_STATE_PAUSED); + replay_gdb_attached(); + gdb_has_xml = false; + break; + default: + break; + } +} + +static void gdb_vm_state_change(void *opaque, bool running, RunState state) +{ + CPUState *cpu = gdbserver_state.c_cpu; + g_autoptr(GString) buf = g_string_new(NULL); + g_autoptr(GString) tid = g_string_new(NULL); + const char *type; + int ret; + + if (running || gdbserver_state.state == RS_INACTIVE) { + return; + } + /* Is there a GDB syscall waiting to be sent? */ + if (gdbserver_state.current_syscall_cb) { + gdb_put_packet(gdbserver_state.syscall_buf); + return; + } + + if (cpu == NULL) { + /* No process attached */ + return; + } + + gdb_append_thread_id(cpu, tid); + + switch (state) { + case RUN_STATE_DEBUG: + if (cpu->watchpoint_hit) { + switch (cpu->watchpoint_hit->flags & BP_MEM_ACCESS) { + case BP_MEM_READ: + type = "r"; + break; + case BP_MEM_ACCESS: + type = "a"; + break; + default: + type = ""; + break; + } + trace_gdbstub_hit_watchpoint(type, + gdb_get_cpu_index(cpu), + cpu->watchpoint_hit->vaddr); + g_string_printf(buf, "T%02xthread:%s;%swatch:%" VADDR_PRIx ";", + GDB_SIGNAL_TRAP, tid->str, type, + cpu->watchpoint_hit->vaddr); + cpu->watchpoint_hit = NULL; + goto send_packet; + } else { + trace_gdbstub_hit_break(); + } + tb_flush(cpu); + ret = GDB_SIGNAL_TRAP; + break; + case RUN_STATE_PAUSED: + trace_gdbstub_hit_paused(); + ret = GDB_SIGNAL_INT; + break; + case RUN_STATE_SHUTDOWN: + trace_gdbstub_hit_shutdown(); + ret = GDB_SIGNAL_QUIT; + break; + case RUN_STATE_IO_ERROR: + trace_gdbstub_hit_io_error(); + ret = GDB_SIGNAL_IO; + break; + case RUN_STATE_WATCHDOG: + trace_gdbstub_hit_watchdog(); + ret = GDB_SIGNAL_ALRM; + break; + case RUN_STATE_INTERNAL_ERROR: + trace_gdbstub_hit_internal_error(); + ret = GDB_SIGNAL_ABRT; + break; + case RUN_STATE_SAVE_VM: + case RUN_STATE_RESTORE_VM: + return; + case RUN_STATE_FINISH_MIGRATE: + ret = GDB_SIGNAL_XCPU; + break; + default: + trace_gdbstub_hit_unknown(state); + ret = GDB_SIGNAL_UNKNOWN; + break; + } + gdb_set_stop_cpu(cpu); + g_string_printf(buf, "T%02xthread:%s;", ret, tid->str); + +send_packet: + gdb_put_packet(buf->str); + + /* disable single step if it was enabled */ + cpu_single_step(cpu, 0); +} + +#ifndef _WIN32 +static void gdb_sigterm_handler(int signal) +{ + if (runstate_is_running()) { + vm_stop(RUN_STATE_PAUSED); + } +} +#endif + +static int gdb_monitor_write(Chardev *chr, const uint8_t *buf, int len) +{ + g_autoptr(GString) hex_buf = g_string_new("O"); + gdb_memtohex(hex_buf, buf, len); + gdb_put_packet(hex_buf->str); + return len; +} + +static void gdb_monitor_open(Chardev *chr, ChardevBackend *backend, + bool *be_opened, Error **errp) +{ + *be_opened = false; +} + +static void char_gdb_class_init(ObjectClass *oc, void *data) +{ + ChardevClass *cc = CHARDEV_CLASS(oc); + + cc->internal = true; + cc->open = gdb_monitor_open; + cc->chr_write = gdb_monitor_write; +} + +#define TYPE_CHARDEV_GDB "chardev-gdb" + +static const TypeInfo char_gdb_type_info = { + .name = TYPE_CHARDEV_GDB, + .parent = TYPE_CHARDEV, + .class_init = char_gdb_class_init, +}; + +static int gdb_chr_can_receive(void *opaque) +{ + /* We can handle an arbitrarily large amount of data. + Pick the maximum packet size, which is as good as anything. */ + return MAX_PACKET_LENGTH; +} + +static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size) +{ + int i; + + for (i = 0; i < size; i++) { + gdb_read_byte(buf[i]); + } +} + +static int find_cpu_clusters(Object *child, void *opaque) +{ + if (object_dynamic_cast(child, TYPE_CPU_CLUSTER)) { + GDBState *s = (GDBState *) opaque; + CPUClusterState *cluster = CPU_CLUSTER(child); + GDBProcess *process; + + s->processes = g_renew(GDBProcess, s->processes, ++s->process_num); + + process = &s->processes[s->process_num - 1]; + + /* + * GDB process IDs -1 and 0 are reserved. To avoid subtle errors at + * runtime, we enforce here that the machine does not use a cluster ID + * that would lead to PID 0. + */ + assert(cluster->cluster_id != UINT32_MAX); + process->pid = cluster->cluster_id + 1; + process->attached = false; + process->target_xml[0] = '\0'; + + return 0; + } + + return object_child_foreach(child, find_cpu_clusters, opaque); +} + +static int pid_order(const void *a, const void *b) +{ + GDBProcess *pa = (GDBProcess *) a; + GDBProcess *pb = (GDBProcess *) b; + + if (pa->pid < pb->pid) { + return -1; + } else if (pa->pid > pb->pid) { + return 1; + } else { + return 0; + } +} + +static void create_processes(GDBState *s) +{ + object_child_foreach(object_get_root(), find_cpu_clusters, s); + + if (gdbserver_state.processes) { + /* Sort by PID */ + qsort(gdbserver_state.processes, + gdbserver_state.process_num, + sizeof(gdbserver_state.processes[0]), + pid_order); + } + + gdb_create_default_process(s); +} + +int gdbserver_start(const char *device) +{ + trace_gdbstub_op_start(device); + + char gdbstub_device_name[128]; + Chardev *chr = NULL; + Chardev *mon_chr; + + if (!first_cpu) { + error_report("gdbstub: meaningless to attach gdb to a " + "machine without any CPU."); + return -1; + } + + if (!gdb_supports_guest_debug()) { + error_report("gdbstub: current accelerator doesn't support guest debugging"); + return -1; + } + + if (!device) + return -1; + if (strcmp(device, "none") != 0) { + if (strstart(device, "tcp:", NULL)) { + /* enforce required TCP attributes */ + snprintf(gdbstub_device_name, sizeof(gdbstub_device_name), + "%s,wait=off,nodelay=on,server=on", device); + device = gdbstub_device_name; + } +#ifndef _WIN32 + else if (strcmp(device, "stdio") == 0) { + struct sigaction act; + + memset(&act, 0, sizeof(act)); + act.sa_handler = gdb_sigterm_handler; + sigaction(SIGINT, &act, NULL); + } +#endif + /* + * FIXME: it's a bit weird to allow using a mux chardev here + * and implicitly setup a monitor. We may want to break this. + */ + chr = qemu_chr_new_noreplay("gdb", device, true, NULL); + if (!chr) + return -1; + } + + if (!gdbserver_state.init) { + gdb_init_gdbserver_state(); + + qemu_add_vm_change_state_handler(gdb_vm_state_change, NULL); + + /* Initialize a monitor terminal for gdb */ + mon_chr = qemu_chardev_new(NULL, TYPE_CHARDEV_GDB, + NULL, NULL, &error_abort); + monitor_init_hmp(mon_chr, false, &error_abort); + } else { + qemu_chr_fe_deinit(&gdbserver_system_state.chr, true); + mon_chr = gdbserver_system_state.mon_chr; + reset_gdbserver_state(); + } + + create_processes(&gdbserver_state); + + if (chr) { + qemu_chr_fe_init(&gdbserver_system_state.chr, chr, &error_abort); + qemu_chr_fe_set_handlers(&gdbserver_system_state.chr, + gdb_chr_can_receive, + gdb_chr_receive, gdb_chr_event, + NULL, &gdbserver_state, NULL, true); + } + gdbserver_state.state = chr ? RS_IDLE : RS_INACTIVE; + gdbserver_system_state.mon_chr = mon_chr; + gdbserver_state.current_syscall_cb = NULL; + + return 0; +} + +static void register_types(void) +{ + type_register_static(&char_gdb_type_info); +} + +type_init(register_types); + +/* Tell the remote gdb that the process has exited. */ +void gdb_exit(int code) +{ + char buf[4]; + + if (!gdbserver_state.init) { + return; + } + + trace_gdbstub_op_exiting((uint8_t)code); + + snprintf(buf, sizeof(buf), "W%02x", (uint8_t)code); + gdb_put_packet(buf); + + qemu_chr_fe_deinit(&gdbserver_system_state.chr, true); +} + +/* + * Softmmu specific command helpers + */ +void gdb_handle_query_rcmd(GArray *params, void *user_ctx) +{ + const guint8 zero = 0; + int len; + + if (!params->len) { + gdb_put_packet("E22"); + return; + } + + len = strlen(get_param(params, 0)->data); + if (len % 2) { + gdb_put_packet("E01"); + return; + } + + g_assert(gdbserver_state.mem_buf->len == 0); + len = len / 2; + gdb_hextomem(gdbserver_state.mem_buf, get_param(params, 0)->data, len); + g_byte_array_append(gdbserver_state.mem_buf, &zero, 1); + qemu_chr_be_write(gdbserver_system_state.mon_chr, + gdbserver_state.mem_buf->data, + gdbserver_state.mem_buf->len); + gdb_put_packet("OK"); +} + +/* + * Break/Watch point helpers + */ + bool gdb_supports_guest_debug(void) { const AccelOpsClass *ops = cpus_get_accel(); diff --git a/gdbstub/trace-events b/gdbstub/trace-events index 03f0c303bf..0c18a4d70a 100644 --- a/gdbstub/trace-events +++ b/gdbstub/trace-events @@ -7,7 +7,6 @@ gdbstub_op_continue(void) "Continuing all CPUs" gdbstub_op_continue_cpu(int cpu_index) "Continuing CPU %d" gdbstub_op_stepping(int cpu_index) "Stepping CPU %d" gdbstub_op_extra_info(const char *info) "Thread extra info: %s" -gdbstub_hit_watchpoint(const char *type, int cpu_gdb_index, uint64_t vaddr) "Watchpoint hit, type=\"%s\" cpu=%d, vaddr=0x%" PRIx64 "" gdbstub_hit_internal_error(void) "RUN_STATE_INTERNAL_ERROR" gdbstub_hit_break(void) "RUN_STATE_DEBUG" gdbstub_hit_paused(void) "RUN_STATE_PAUSED" @@ -27,3 +26,6 @@ gdbstub_err_invalid_repeat(uint8_t ch) "got invalid RLE count: 0x%02x" gdbstub_err_invalid_rle(void) "got invalid RLE sequence" gdbstub_err_checksum_invalid(uint8_t ch) "got invalid command checksum digit: 0x%02x" gdbstub_err_checksum_incorrect(uint8_t expected, uint8_t got) "got command packet with incorrect checksum, expected=0x%02x, received=0x%02x" + +# softmmu.c +gdbstub_hit_watchpoint(const char *type, int cpu_gdb_index, uint64_t vaddr) "Watchpoint hit, type=\"%s\" cpu=%d, vaddr=0x%" PRIx64 "" -- 2.34.1 From MAILER-DAEMON Thu Jan 05 11:43:55 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTLN-0007Ju-Uj for mharc-qemu-riscv@gnu.org; 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Thu, 05 Jan 2023 08:43:23 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id EBB611FFC1; Thu, 5 Jan 2023 16:43:20 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH v2 09/21] gdbstub: make various helpers visible to the rest of the module Date: Thu, 5 Jan 2023 16:43:08 +0000 Message-Id: <20230105164320.2164095-10-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:43:47 -0000 We will be needing to use these helpers between the user and softmmu files so declare them in the headers, add a system prefix and remove static from the implementations. Signed-off-by: Alex Bennée --- gdbstub/internals.h | 25 ++++ gdbstub/gdbstub.c | 271 ++++++++++++++++++++++---------------------- 2 files changed, 161 insertions(+), 135 deletions(-) diff --git a/gdbstub/internals.h b/gdbstub/internals.h index c8bb85cf34..670bd01a1d 100644 --- a/gdbstub/internals.h +++ b/gdbstub/internals.h @@ -101,6 +101,31 @@ static inline int tohex(int v) } } +/* + * Connection helpers for both softmmu and user backends + */ + +void gdb_put_strbuf(void); +int gdb_put_packet(const char *buf); +int gdb_put_packet_binary(const char *buf, int len, bool dump); +void gdb_hextomem(GByteArray *mem, const char *buf, int len); +void gdb_memtohex(GString *buf, const uint8_t *mem, int len); +void gdb_memtox(GString *buf, const char *mem, int len); +void gdb_read_byte(uint8_t ch); + +/* utility helpers */ +CPUState *gdb_first_attached_cpu(void); +void gdb_append_thread_id(CPUState *cpu, GString *buf); +int gdb_get_cpu_index(CPUState *cpu); + +void gdb_init_gdbserver_state(void); +void gdb_create_default_process(GDBState *s); + +/* + * Helpers with separate softmmu and user implementations + */ +void gdb_put_buffer(const uint8_t *buf, int len); + /* * Break/Watch point support - there is an implementation for softmmu * and user mode. diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index d4ee23b51c..9c347cd84b 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -85,12 +85,13 @@ static inline int target_memory_rw_debug(CPUState *cpu, target_ulong addr, return cpu_memory_rw_debug(cpu, addr, buf, len, is_write); } -/* Return the GDB index for a given vCPU state. +/* + * Return the GDB index for a given vCPU state. * * For user mode this is simply the thread id. In system mode GDB * numbers CPUs from 1 as 0 is reserved as an "any cpu" index. */ -static inline int cpu_gdb_index(CPUState *cpu) +int gdb_get_cpu_index(CPUState *cpu) { #if defined(CONFIG_USER_ONLY) TaskState *ts = (TaskState *) cpu->opaque; @@ -327,7 +328,7 @@ typedef struct GDBRegisterState { static GDBState gdbserver_state; -static void init_gdbserver_state(void) +void gdb_init_gdbserver_state(void) { g_assert(!gdbserver_state.init); memset(&gdbserver_state, 0, sizeof(GDBState)); @@ -509,7 +510,7 @@ static int gdb_continue_partial(char *newstates) return res; } -static void put_buffer(const uint8_t *buf, int len) +void gdb_put_buffer(const uint8_t *buf, int len) { #ifdef CONFIG_USER_ONLY int ret; @@ -532,7 +533,7 @@ static void put_buffer(const uint8_t *buf, int len) } /* writes 2*len+1 bytes in buf */ -static void memtohex(GString *buf, const uint8_t *mem, int len) +void gdb_memtohex(GString *buf, const uint8_t *mem, int len) { int i, c; for(i = 0; i < len; i++) { @@ -543,7 +544,7 @@ static void memtohex(GString *buf, const uint8_t *mem, int len) g_string_append_c(buf, '\0'); } -static void hextomem(GByteArray *mem, const char *buf, int len) +void gdb_hextomem(GByteArray *mem, const char *buf, int len) { int i; @@ -588,7 +589,7 @@ static void hexdump(const char *buf, int len, } /* return -1 if error, 0 if OK */ -static int put_packet_binary(const char *buf, int len, bool dump) +int gdb_put_packet_binary(const char *buf, int len, bool dump) { int csum, i; uint8_t footer[3]; @@ -612,7 +613,7 @@ static int put_packet_binary(const char *buf, int len, bool dump) footer[2] = tohex((csum) & 0xf); g_byte_array_append(gdbserver_state.last_packet, footer, 3); - put_buffer(gdbserver_state.last_packet->data, + gdb_put_buffer(gdbserver_state.last_packet->data, gdbserver_state.last_packet->len); #ifdef CONFIG_USER_ONLY @@ -629,20 +630,20 @@ static int put_packet_binary(const char *buf, int len, bool dump) } /* return -1 if error, 0 if OK */ -static int put_packet(const char *buf) +int gdb_put_packet(const char *buf) { trace_gdbstub_io_reply(buf); - return put_packet_binary(buf, strlen(buf), false); + return gdb_put_packet_binary(buf, strlen(buf), false); } -static void put_strbuf(void) +void gdb_put_strbuf(void) { - put_packet(gdbserver_state.str_buf->str); + gdb_put_packet(gdbserver_state.str_buf->str); } /* Encode data using the encoding for 'x' packets. */ -static void memtox(GString *buf, const char *mem, int len) +void gdb_memtox(GString *buf, const char *mem, int len) { char c; @@ -699,7 +700,7 @@ static CPUState *find_cpu(uint32_t thread_id) CPUState *cpu; CPU_FOREACH(cpu) { - if (cpu_gdb_index(cpu) == thread_id) { + if (gdb_get_cpu_index(cpu) == thread_id) { return cpu; } } @@ -753,7 +754,7 @@ static CPUState *gdb_next_attached_cpu(CPUState *cpu) } /* Return the first attached cpu */ -static CPUState *gdb_first_attached_cpu(void) +CPUState *gdb_first_attached_cpu(void) { CPUState *cpu = first_cpu; GDBProcess *process = gdb_get_cpu_process(cpu); @@ -967,13 +968,13 @@ static void gdb_set_cpu_pc(target_ulong pc) cpu_set_pc(cpu, pc); } -static void gdb_append_thread_id(CPUState *cpu, GString *buf) +void gdb_append_thread_id(CPUState *cpu, GString *buf) { if (gdbserver_state.multiprocess) { g_string_append_printf(buf, "p%02x.%02x", - gdb_get_cpu_pid(cpu), cpu_gdb_index(cpu)); + gdb_get_cpu_pid(cpu), gdb_get_cpu_index(cpu)); } else { - g_string_append_printf(buf, "%02x", cpu_gdb_index(cpu)); + g_string_append_printf(buf, "%02x", gdb_get_cpu_index(cpu)); } } @@ -1344,7 +1345,7 @@ static void run_cmd_parser(const char *data, const GdbCmdParseEntry *cmd) /* In case there was an error during the command parsing we must * send a NULL packet to indicate the command is not supported */ if (process_string_cmd(NULL, data, cmd, 1)) { - put_packet(""); + gdb_put_packet(""); } } @@ -1355,7 +1356,7 @@ static void handle_detach(GArray *params, void *user_ctx) if (gdbserver_state.multiprocess) { if (!params->len) { - put_packet("E22"); + gdb_put_packet("E22"); return; } @@ -1379,7 +1380,7 @@ static void handle_detach(GArray *params, void *user_ctx) gdb_syscall_mode = GDB_SYS_DISABLED; gdb_continue(); } - put_packet("OK"); + gdb_put_packet("OK"); } static void handle_thread_alive(GArray *params, void *user_ctx) @@ -1387,23 +1388,23 @@ static void handle_thread_alive(GArray *params, void *user_ctx) CPUState *cpu; if (!params->len) { - put_packet("E22"); + gdb_put_packet("E22"); return; } if (get_param(params, 0)->thread_id.kind == GDB_READ_THREAD_ERR) { - put_packet("E22"); + gdb_put_packet("E22"); return; } cpu = gdb_get_cpu(get_param(params, 0)->thread_id.pid, get_param(params, 0)->thread_id.tid); if (!cpu) { - put_packet("E22"); + gdb_put_packet("E22"); return; } - put_packet("OK"); + gdb_put_packet("OK"); } static void handle_continue(GArray *params, void *user_ctx) @@ -1440,24 +1441,24 @@ static void handle_set_thread(GArray *params, void *user_ctx) CPUState *cpu; if (params->len != 2) { - put_packet("E22"); + gdb_put_packet("E22"); return; } if (get_param(params, 1)->thread_id.kind == GDB_READ_THREAD_ERR) { - put_packet("E22"); + gdb_put_packet("E22"); return; } if (get_param(params, 1)->thread_id.kind != GDB_ONE_THREAD) { - put_packet("OK"); + gdb_put_packet("OK"); return; } cpu = gdb_get_cpu(get_param(params, 1)->thread_id.pid, get_param(params, 1)->thread_id.tid); if (!cpu) { - put_packet("E22"); + gdb_put_packet("E22"); return; } @@ -1468,14 +1469,14 @@ static void handle_set_thread(GArray *params, void *user_ctx) switch (get_param(params, 0)->opcode) { case 'c': gdbserver_state.c_cpu = cpu; - put_packet("OK"); + gdb_put_packet("OK"); break; case 'g': gdbserver_state.g_cpu = cpu; - put_packet("OK"); + gdb_put_packet("OK"); break; default: - put_packet("E22"); + gdb_put_packet("E22"); break; } } @@ -1485,7 +1486,7 @@ static void handle_insert_bp(GArray *params, void *user_ctx) int res; if (params->len != 3) { - put_packet("E22"); + gdb_put_packet("E22"); return; } @@ -1494,14 +1495,14 @@ static void handle_insert_bp(GArray *params, void *user_ctx) get_param(params, 1)->val_ull, get_param(params, 2)->val_ull); if (res >= 0) { - put_packet("OK"); + gdb_put_packet("OK"); return; } else if (res == -ENOSYS) { - put_packet(""); + gdb_put_packet(""); return; } - put_packet("E22"); + gdb_put_packet("E22"); } static void handle_remove_bp(GArray *params, void *user_ctx) @@ -1509,7 +1510,7 @@ static void handle_remove_bp(GArray *params, void *user_ctx) int res; if (params->len != 3) { - put_packet("E22"); + gdb_put_packet("E22"); return; } @@ -1518,14 +1519,14 @@ static void handle_remove_bp(GArray *params, void *user_ctx) get_param(params, 1)->val_ull, get_param(params, 2)->val_ull); if (res >= 0) { - put_packet("OK"); + gdb_put_packet("OK"); return; } else if (res == -ENOSYS) { - put_packet(""); + gdb_put_packet(""); return; } - put_packet("E22"); + gdb_put_packet("E22"); } /* @@ -1544,20 +1545,20 @@ static void handle_set_reg(GArray *params, void *user_ctx) int reg_size; if (!gdb_has_xml) { - put_packet(""); + gdb_put_packet(""); return; } if (params->len != 2) { - put_packet("E22"); + gdb_put_packet("E22"); return; } reg_size = strlen(get_param(params, 1)->data) / 2; - hextomem(gdbserver_state.mem_buf, get_param(params, 1)->data, reg_size); + gdb_hextomem(gdbserver_state.mem_buf, get_param(params, 1)->data, reg_size); gdb_write_register(gdbserver_state.g_cpu, gdbserver_state.mem_buf->data, get_param(params, 0)->val_ull); - put_packet("OK"); + gdb_put_packet("OK"); } static void handle_get_reg(GArray *params, void *user_ctx) @@ -1565,12 +1566,12 @@ static void handle_get_reg(GArray *params, void *user_ctx) int reg_size; if (!gdb_has_xml) { - put_packet(""); + gdb_put_packet(""); return; } if (!params->len) { - put_packet("E14"); + gdb_put_packet("E14"); return; } @@ -1578,53 +1579,53 @@ static void handle_get_reg(GArray *params, void *user_ctx) gdbserver_state.mem_buf, get_param(params, 0)->val_ull); if (!reg_size) { - put_packet("E14"); + gdb_put_packet("E14"); return; } else { g_byte_array_set_size(gdbserver_state.mem_buf, reg_size); } - memtohex(gdbserver_state.str_buf, gdbserver_state.mem_buf->data, reg_size); - put_strbuf(); + gdb_memtohex(gdbserver_state.str_buf, gdbserver_state.mem_buf->data, reg_size); + gdb_put_strbuf(); } static void handle_write_mem(GArray *params, void *user_ctx) { if (params->len != 3) { - put_packet("E22"); + gdb_put_packet("E22"); return; } - /* hextomem() reads 2*len bytes */ + /* gdb_hextomem() reads 2*len bytes */ if (get_param(params, 1)->val_ull > strlen(get_param(params, 2)->data) / 2) { - put_packet("E22"); + gdb_put_packet("E22"); return; } - hextomem(gdbserver_state.mem_buf, get_param(params, 2)->data, + gdb_hextomem(gdbserver_state.mem_buf, get_param(params, 2)->data, get_param(params, 1)->val_ull); if (target_memory_rw_debug(gdbserver_state.g_cpu, get_param(params, 0)->val_ull, gdbserver_state.mem_buf->data, gdbserver_state.mem_buf->len, true)) { - put_packet("E14"); + gdb_put_packet("E14"); return; } - put_packet("OK"); + gdb_put_packet("OK"); } static void handle_read_mem(GArray *params, void *user_ctx) { if (params->len != 2) { - put_packet("E22"); + gdb_put_packet("E22"); return; } - /* memtohex() doubles the required space */ + /* gdb_memtohex() doubles the required space */ if (get_param(params, 1)->val_ull > MAX_PACKET_LENGTH / 2) { - put_packet("E22"); + gdb_put_packet("E22"); return; } @@ -1635,13 +1636,13 @@ static void handle_read_mem(GArray *params, void *user_ctx) get_param(params, 0)->val_ull, gdbserver_state.mem_buf->data, gdbserver_state.mem_buf->len, false)) { - put_packet("E14"); + gdb_put_packet("E14"); return; } - memtohex(gdbserver_state.str_buf, gdbserver_state.mem_buf->data, + gdb_memtohex(gdbserver_state.str_buf, gdbserver_state.mem_buf->data, gdbserver_state.mem_buf->len); - put_strbuf(); + gdb_put_strbuf(); } static void handle_write_all_regs(GArray *params, void *user_ctx) @@ -1656,7 +1657,7 @@ static void handle_write_all_regs(GArray *params, void *user_ctx) cpu_synchronize_state(gdbserver_state.g_cpu); len = strlen(get_param(params, 0)->data) / 2; - hextomem(gdbserver_state.mem_buf, get_param(params, 0)->data, len); + gdb_hextomem(gdbserver_state.mem_buf, get_param(params, 0)->data, len); registers = gdbserver_state.mem_buf->data; for (addr = 0; addr < gdbserver_state.g_cpu->gdb_num_g_regs && len > 0; addr++) { @@ -1664,7 +1665,7 @@ static void handle_write_all_regs(GArray *params, void *user_ctx) len -= reg_size; registers += reg_size; } - put_packet("OK"); + gdb_put_packet("OK"); } static void handle_read_all_regs(GArray *params, void *user_ctx) @@ -1681,8 +1682,8 @@ static void handle_read_all_regs(GArray *params, void *user_ctx) } g_assert(len == gdbserver_state.mem_buf->len); - memtohex(gdbserver_state.str_buf, gdbserver_state.mem_buf->data, len); - put_strbuf(); + gdb_memtohex(gdbserver_state.str_buf, gdbserver_state.mem_buf->data, len); + gdb_put_strbuf(); } static void handle_file_io(GArray *params, void *user_ctx) @@ -1733,7 +1734,7 @@ static void handle_file_io(GArray *params, void *user_ctx) } if (params->len >= 3 && get_param(params, 2)->opcode == (uint8_t)'C') { - put_packet("T02"); + gdb_put_packet("T02"); return; } @@ -1753,7 +1754,7 @@ static void handle_step(GArray *params, void *user_ctx) static void handle_backward(GArray *params, void *user_ctx) { if (!stub_can_reverse()) { - put_packet("E22"); + gdb_put_packet("E22"); } if (params->len == 1) { switch (get_param(params, 0)->opcode) { @@ -1761,26 +1762,26 @@ static void handle_backward(GArray *params, void *user_ctx) if (replay_reverse_step()) { gdb_continue(); } else { - put_packet("E14"); + gdb_put_packet("E14"); } return; case 'c': if (replay_reverse_continue()) { gdb_continue(); } else { - put_packet("E14"); + gdb_put_packet("E14"); } return; } } /* Default invalid command */ - put_packet(""); + gdb_put_packet(""); } static void handle_v_cont_query(GArray *params, void *user_ctx) { - put_packet("vCont;c;C;s;S"); + gdb_put_packet("vCont;c;C;s;S"); } static void handle_v_cont(GArray *params, void *user_ctx) @@ -1793,9 +1794,9 @@ static void handle_v_cont(GArray *params, void *user_ctx) res = gdb_handle_vcont(get_param(params, 0)->data); if ((res == -EINVAL) || (res == -ERANGE)) { - put_packet("E22"); + gdb_put_packet("E22"); } else if (res) { - put_packet(""); + gdb_put_packet(""); } } @@ -1827,13 +1828,13 @@ static void handle_v_attach(GArray *params, void *user_ctx) gdb_append_thread_id(cpu, gdbserver_state.str_buf); g_string_append_c(gdbserver_state.str_buf, ';'); cleanup: - put_strbuf(); + gdb_put_strbuf(); } static void handle_v_kill(GArray *params, void *user_ctx) { /* Kill the target */ - put_packet("OK"); + gdb_put_packet("OK"); error_report("QEMU: Terminated via GDBstub"); gdb_exit(0); exit(0); @@ -1874,7 +1875,7 @@ static void handle_v_commands(GArray *params, void *user_ctx) if (process_string_cmd(NULL, get_param(params, 0)->data, gdb_v_commands_table, ARRAY_SIZE(gdb_v_commands_table))) { - put_packet(""); + gdb_put_packet(""); } } @@ -1892,7 +1893,7 @@ static void handle_query_qemu_sstepbits(GArray *params, void *user_ctx) SSTEP_NOTIMER); } - put_strbuf(); + gdb_put_strbuf(); } static void handle_set_qemu_sstep(GArray *params, void *user_ctx) @@ -1906,19 +1907,19 @@ static void handle_set_qemu_sstep(GArray *params, void *user_ctx) new_sstep_flags = get_param(params, 0)->val_ul; if (new_sstep_flags & ~gdbserver_state.supported_sstep_flags) { - put_packet("E22"); + gdb_put_packet("E22"); return; } gdbserver_state.sstep_flags = new_sstep_flags; - put_packet("OK"); + gdb_put_packet("OK"); } static void handle_query_qemu_sstep(GArray *params, void *user_ctx) { g_string_printf(gdbserver_state.str_buf, "0x%x", gdbserver_state.sstep_flags); - put_strbuf(); + gdb_put_strbuf(); } static void handle_query_curr_tid(GArray *params, void *user_ctx) @@ -1935,19 +1936,19 @@ static void handle_query_curr_tid(GArray *params, void *user_ctx) cpu = get_first_cpu_in_process(process); g_string_assign(gdbserver_state.str_buf, "QC"); gdb_append_thread_id(cpu, gdbserver_state.str_buf); - put_strbuf(); + gdb_put_strbuf(); } static void handle_query_threads(GArray *params, void *user_ctx) { if (!gdbserver_state.query_cpu) { - put_packet("l"); + gdb_put_packet("l"); return; } g_string_assign(gdbserver_state.str_buf, "m"); gdb_append_thread_id(gdbserver_state.query_cpu, gdbserver_state.str_buf); - put_strbuf(); + gdb_put_strbuf(); gdbserver_state.query_cpu = gdb_next_attached_cpu(gdbserver_state.query_cpu); } @@ -1964,7 +1965,7 @@ static void handle_query_thread_extra(GArray *params, void *user_ctx) if (!params->len || get_param(params, 0)->thread_id.kind == GDB_READ_THREAD_ERR) { - put_packet("E22"); + gdb_put_packet("E22"); return; } @@ -1989,8 +1990,8 @@ static void handle_query_thread_extra(GArray *params, void *user_ctx) cpu->halted ? "halted " : "running"); } trace_gdbstub_op_extra_info(rs->str); - memtohex(gdbserver_state.str_buf, (uint8_t *)rs->str, rs->len); - put_strbuf(); + gdb_memtohex(gdbserver_state.str_buf, (uint8_t *)rs->str, rs->len); + gdb_put_strbuf(); } #ifdef CONFIG_USER_ONLY @@ -2006,7 +2007,7 @@ static void handle_query_offsets(GArray *params, void *user_ctx) ts->info->code_offset, ts->info->data_offset, ts->info->data_offset); - put_strbuf(); + gdb_put_strbuf(); } #else static void handle_query_rcmd(GArray *params, void *user_ctx) @@ -2015,24 +2016,24 @@ static void handle_query_rcmd(GArray *params, void *user_ctx) int len; if (!params->len) { - put_packet("E22"); + gdb_put_packet("E22"); return; } len = strlen(get_param(params, 0)->data); if (len % 2) { - put_packet("E01"); + gdb_put_packet("E01"); return; } g_assert(gdbserver_state.mem_buf->len == 0); len = len / 2; - hextomem(gdbserver_state.mem_buf, get_param(params, 0)->data, len); + gdb_hextomem(gdbserver_state.mem_buf, get_param(params, 0)->data, len); g_byte_array_append(gdbserver_state.mem_buf, &zero, 1); qemu_chr_be_write(gdbserver_state.system.mon_chr, gdbserver_state.mem_buf->data, gdbserver_state.mem_buf->len); - put_packet("OK"); + gdb_put_packet("OK"); } #endif @@ -2063,7 +2064,7 @@ static void handle_query_supported(GArray *params, void *user_ctx) } g_string_append(gdbserver_state.str_buf, ";vContSupported+;multiprocess+"); - put_strbuf(); + gdb_put_strbuf(); } static void handle_query_xfer_features(GArray *params, void *user_ctx) @@ -2075,14 +2076,14 @@ static void handle_query_xfer_features(GArray *params, void *user_ctx) const char *p; if (params->len < 3) { - put_packet("E22"); + gdb_put_packet("E22"); return; } process = gdb_get_cpu_process(gdbserver_state.g_cpu); cc = CPU_GET_CLASS(gdbserver_state.g_cpu); if (!cc->gdb_core_xml_file) { - put_packet(""); + gdb_put_packet(""); return; } @@ -2090,7 +2091,7 @@ static void handle_query_xfer_features(GArray *params, void *user_ctx) p = get_param(params, 0)->data; xml = get_feature_xml(p, &p, process); if (!xml) { - put_packet("E00"); + gdb_put_packet("E00"); return; } @@ -2098,7 +2099,7 @@ static void handle_query_xfer_features(GArray *params, void *user_ctx) len = get_param(params, 2)->val_ul; total_len = strlen(xml); if (addr > total_len) { - put_packet("E00"); + gdb_put_packet("E00"); return; } @@ -2108,13 +2109,13 @@ static void handle_query_xfer_features(GArray *params, void *user_ctx) if (len < total_len - addr) { g_string_assign(gdbserver_state.str_buf, "m"); - memtox(gdbserver_state.str_buf, xml + addr, len); + gdb_memtox(gdbserver_state.str_buf, xml + addr, len); } else { g_string_assign(gdbserver_state.str_buf, "l"); - memtox(gdbserver_state.str_buf, xml + addr, total_len - addr); + gdb_memtox(gdbserver_state.str_buf, xml + addr, total_len - addr); } - put_packet_binary(gdbserver_state.str_buf->str, + gdb_put_packet_binary(gdbserver_state.str_buf->str, gdbserver_state.str_buf->len, true); } @@ -2125,7 +2126,7 @@ static void handle_query_xfer_auxv(GArray *params, void *user_ctx) unsigned long offset, len, saved_auxv, auxv_len; if (params->len < 2) { - put_packet("E22"); + gdb_put_packet("E22"); return; } @@ -2136,7 +2137,7 @@ static void handle_query_xfer_auxv(GArray *params, void *user_ctx) auxv_len = ts->info->auxv_len; if (offset >= auxv_len) { - put_packet("E00"); + gdb_put_packet("E00"); return; } @@ -2154,20 +2155,20 @@ static void handle_query_xfer_auxv(GArray *params, void *user_ctx) g_byte_array_set_size(gdbserver_state.mem_buf, len); if (target_memory_rw_debug(gdbserver_state.g_cpu, saved_auxv + offset, gdbserver_state.mem_buf->data, len, false)) { - put_packet("E14"); + gdb_put_packet("E14"); return; } - memtox(gdbserver_state.str_buf, - (const char *)gdbserver_state.mem_buf->data, len); - put_packet_binary(gdbserver_state.str_buf->str, - gdbserver_state.str_buf->len, true); + gdb_memtox(gdbserver_state.str_buf, + (const char *)gdbserver_state.mem_buf->data, len); + gdb_put_packet_binary(gdbserver_state.str_buf->str, + gdbserver_state.str_buf->len, true); } #endif static void handle_query_attached(GArray *params, void *user_ctx) { - put_packet(GDB_ATTACHED); + gdb_put_packet(GDB_ATTACHED); } static void handle_query_qemu_supported(GArray *params, void *user_ctx) @@ -2176,7 +2177,7 @@ static void handle_query_qemu_supported(GArray *params, void *user_ctx) #ifndef CONFIG_USER_ONLY g_string_append(gdbserver_state.str_buf, ";PhyMemMode"); #endif - put_strbuf(); + gdb_put_strbuf(); } #ifndef CONFIG_USER_ONLY @@ -2184,13 +2185,13 @@ static void handle_query_qemu_phy_mem_mode(GArray *params, void *user_ctx) { g_string_printf(gdbserver_state.str_buf, "%d", phy_memory_mode); - put_strbuf(); + gdb_put_strbuf(); } static void handle_set_qemu_phy_mem_mode(GArray *params, void *user_ctx) { if (!params->len) { - put_packet("E22"); + gdb_put_packet("E22"); return; } @@ -2199,7 +2200,7 @@ static void handle_set_qemu_phy_mem_mode(GArray *params, void *user_ctx) } else { phy_memory_mode = 1; } - put_packet("OK"); + gdb_put_packet("OK"); } #endif @@ -2332,7 +2333,7 @@ static void handle_gen_query(GArray *params, void *user_ctx) if (process_string_cmd(NULL, get_param(params, 0)->data, gdb_gen_query_table, ARRAY_SIZE(gdb_gen_query_table))) { - put_packet(""); + gdb_put_packet(""); } } @@ -2351,7 +2352,7 @@ static void handle_gen_set(GArray *params, void *user_ctx) if (process_string_cmd(NULL, get_param(params, 0)->data, gdb_gen_set_table, ARRAY_SIZE(gdb_gen_set_table))) { - put_packet(""); + gdb_put_packet(""); } } @@ -2360,7 +2361,7 @@ static void handle_target_halt(GArray *params, void *user_ctx) g_string_printf(gdbserver_state.str_buf, "T%02xthread:", GDB_SIGNAL_TRAP); gdb_append_thread_id(gdbserver_state.c_cpu, gdbserver_state.str_buf); g_string_append_c(gdbserver_state.str_buf, ';'); - put_strbuf(); + gdb_put_strbuf(); /* * Remove all the breakpoints when this query is issued, * because gdb is doing an initial connect and the state @@ -2377,7 +2378,7 @@ static int gdb_handle_packet(const char *line_buf) switch (line_buf[0]) { case '!': - put_packet("OK"); + gdb_put_packet("OK"); break; case '?': { @@ -2604,7 +2605,7 @@ static int gdb_handle_packet(const char *line_buf) break; default: /* put empty packet */ - put_packet(""); + gdb_put_packet(""); break; } @@ -2645,7 +2646,7 @@ static void gdb_vm_state_change(void *opaque, bool running, RunState state) } /* Is there a GDB syscall waiting to be sent? */ if (gdbserver_state.current_syscall_cb) { - put_packet(gdbserver_state.syscall_buf); + gdb_put_packet(gdbserver_state.syscall_buf); return; } @@ -2670,7 +2671,7 @@ static void gdb_vm_state_change(void *opaque, bool running, RunState state) type = ""; break; } - trace_gdbstub_hit_watchpoint(type, cpu_gdb_index(cpu), + trace_gdbstub_hit_watchpoint(type, gdb_get_cpu_index(cpu), (target_ulong)cpu->watchpoint_hit->vaddr); g_string_printf(buf, "T%02xthread:%s;%swatch:" TARGET_FMT_lx ";", GDB_SIGNAL_TRAP, tid->str, type, @@ -2718,7 +2719,7 @@ static void gdb_vm_state_change(void *opaque, bool running, RunState state) g_string_printf(buf, "T%02xthread:%s;", ret, tid->str); send_packet: - put_packet(buf->str); + gdb_put_packet(buf->str); /* disable single step if it was enabled */ cpu_single_step(cpu, 0); @@ -2779,7 +2780,7 @@ void gdb_do_syscallv(gdb_syscall_complete_cb cb, const char *fmt, va_list va) } *p = 0; #ifdef CONFIG_USER_ONLY - put_packet(gdbserver_state.syscall_buf); + gdb_put_packet(gdbserver_state.syscall_buf); /* Return control to gdb for it to process the syscall request. * Since the protocol requires that gdb hands control back to us * using a "here are the results" F packet, we don't need to check @@ -2807,7 +2808,7 @@ void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...) va_end(va); } -static void gdb_read_byte(uint8_t ch) +void gdb_read_byte(uint8_t ch) { uint8_t reply; @@ -2817,7 +2818,7 @@ static void gdb_read_byte(uint8_t ch) of a new command then abandon the previous response. */ if (ch == '-') { trace_gdbstub_err_got_nack(); - put_buffer(gdbserver_state.last_packet->data, + gdb_put_buffer(gdbserver_state.last_packet->data, gdbserver_state.last_packet->len); } else if (ch == '+') { trace_gdbstub_io_got_ack(); @@ -2939,12 +2940,12 @@ static void gdb_read_byte(uint8_t ch) trace_gdbstub_err_checksum_incorrect(gdbserver_state.line_sum, gdbserver_state.line_csum); /* send NAK reply */ reply = '-'; - put_buffer(&reply, 1); + gdb_put_buffer(&reply, 1); gdbserver_state.state = RS_IDLE; } else { /* send ACK reply */ reply = '+'; - put_buffer(&reply, 1); + gdb_put_buffer(&reply, 1); gdbserver_state.state = gdb_handle_packet(gdbserver_state.line_buf); } break; @@ -2974,7 +2975,7 @@ void gdb_exit(int code) trace_gdbstub_op_exiting((uint8_t)code); snprintf(buf, sizeof(buf), "W%02x", (uint8_t)code); - put_packet(buf); + gdb_put_packet(buf); #ifndef CONFIG_USER_ONLY qemu_chr_fe_deinit(&gdbserver_state.system.chr, true); @@ -2986,7 +2987,7 @@ void gdb_exit(int code) * part of a CPU cluster). Note that if this process contains no CPUs, it won't * be attachable and thus will be invisible to the user. */ -static void create_default_process(GDBState *s) +void gdb_create_default_process(GDBState *s) { GDBProcess *process; int max_pid = 0; @@ -3027,9 +3028,9 @@ gdb_handlesig(CPUState *cpu, int sig) "T%02xthread:", target_signal_to_gdb(sig)); gdb_append_thread_id(cpu, gdbserver_state.str_buf); g_string_append_c(gdbserver_state.str_buf, ';'); - put_strbuf(); + gdb_put_strbuf(); } - /* put_packet() might have detected that the peer terminated the + /* gdb_put_packet() might have detected that the peer terminated the connection. */ if (gdbserver_state.user.fd < 0) { return sig; @@ -3071,13 +3072,13 @@ void gdb_signalled(CPUArchState *env, int sig) } snprintf(buf, sizeof(buf), "X%02x", target_signal_to_gdb(sig)); - put_packet(buf); + gdb_put_packet(buf); } static void gdb_accept_init(int fd) { - init_gdbserver_state(); - create_default_process(&gdbserver_state); + gdb_init_gdbserver_state(); + gdb_create_default_process(&gdbserver_state); gdbserver_state.processes[0].attached = true; gdbserver_state.c_cpu = gdb_first_attached_cpu(); gdbserver_state.g_cpu = gdbserver_state.c_cpu; @@ -3277,8 +3278,8 @@ static void gdb_chr_event(void *opaque, QEMUChrEvent event) static int gdb_monitor_write(Chardev *chr, const uint8_t *buf, int len) { g_autoptr(GString) hex_buf = g_string_new("O"); - memtohex(hex_buf, buf, len); - put_packet(hex_buf->str); + gdb_memtohex(hex_buf, buf, len); + gdb_put_packet(hex_buf->str); return len; } @@ -3364,7 +3365,7 @@ static void create_processes(GDBState *s) qsort(gdbserver_state.processes, gdbserver_state.process_num, sizeof(gdbserver_state.processes[0]), pid_order); } - create_default_process(s); + gdb_create_default_process(s); } int gdbserver_start(const char *device) @@ -3414,7 +3415,7 @@ int gdbserver_start(const char *device) } if (!gdbserver_state.init) { - init_gdbserver_state(); + gdb_init_gdbserver_state(); qemu_add_vm_change_state_handler(gdb_vm_state_change, NULL); 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Thu, 05 Jan 2023 08:43:26 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id iv14-20020a05600c548e00b003b47b80cec3sm3432195wmb.42.2023.01.05.08.43.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:43:25 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 2FC341FFC4; Thu, 5 Jan 2023 16:43:21 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH v2 12/21] gdbstub: abstract target specific details from gdb_put_packet_binary Date: Thu, 5 Jan 2023 16:43:11 +0000 Message-Id: <20230105164320.2164095-13-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:43:47 -0000 We unfortunately handle the checking of packet acknowledgement differently for user and softmmu modes. Abstract the user mode stuff behind gdb_got_immediate_ack with a stub for softmmu. Signed-off-by: Alex Bennée --- gdbstub/internals.h | 15 +++++++++++++++ gdbstub/gdbstub.c | 10 ++-------- gdbstub/softmmu.c | 8 ++++++++ gdbstub/user.c | 19 +++++++++++++++++++ 4 files changed, 44 insertions(+), 8 deletions(-) diff --git a/gdbstub/internals.h b/gdbstub/internals.h index 568b432220..8d260e2481 100644 --- a/gdbstub/internals.h +++ b/gdbstub/internals.h @@ -106,6 +106,21 @@ void gdb_memtohex(GString *buf, const uint8_t *mem, int len); void gdb_memtox(GString *buf, const char *mem, int len); void gdb_read_byte(uint8_t ch); +/* + * Packet acknowledgement - we handle this slightly differently + * between user and softmmu mode, mainly to deal with the differences + * between the flexible chardev and the direct fd approaches. + * + * We currently don't support a negotiated QStartNoAckMode + */ + +/** + * gdb_got_immediate_ack() - check ok to continue + * + * Returns true to continue, false to re-transmit for user only, the + * softmmu stub always returns true. + */ +bool gdb_got_immediate_ack(void); /* utility helpers */ CPUState *gdb_first_attached_cpu(void); void gdb_append_thread_id(CPUState *cpu, GString *buf); diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 4bf99783a6..76c24b7cb6 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -239,15 +239,9 @@ int gdb_put_packet_binary(const char *buf, int len, bool dump) gdb_put_buffer(gdbserver_state.last_packet->data, gdbserver_state.last_packet->len); -#ifdef CONFIG_USER_ONLY - i = gdb_get_char(); - if (i < 0) - return -1; - if (i == '+') + if (gdb_got_immediate_ack()) { break; -#else - break; -#endif + } } return 0; } diff --git a/gdbstub/softmmu.c b/gdbstub/softmmu.c index ee5daad0cf..534370081d 100644 --- a/gdbstub/softmmu.c +++ b/gdbstub/softmmu.c @@ -58,6 +58,14 @@ int gdb_get_cpu_index(CPUState *cpu) return cpu->cpu_index + 1; } +/* + * We check the status of the last message in the chardev receive code + */ +bool gdb_got_immediate_ack(void) +{ + return true; +} + /* * GDB Connection management. For system emulation we do all of this * via our existing Chardev infrastructure which allows us to support diff --git a/gdbstub/user.c b/gdbstub/user.c index 4898f16c90..fa19ec5263 100644 --- a/gdbstub/user.c +++ b/gdbstub/user.c @@ -57,6 +57,25 @@ int gdb_get_char(void) return ch; } +bool gdb_got_immediate_ack(void) +{ + int i; + + i = gdb_get_char(); + if (i < 0) { + /* no response, continue anyway */ + return true; + } + + if (i == '+') { + /* received correctly, continue */ + return true; + } + + /* anything else, including '-' then try again */ + return false; +} + void gdb_put_buffer(const uint8_t *buf, int len) { int ret; -- 2.34.1 From MAILER-DAEMON Thu Jan 05 11:43:57 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTLR-0007T4-ME for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 11:43:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTLP-0007MM-Is for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:43:55 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTL0-00072Z-7W for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:43:54 -0500 Received: by mail-wr1-x42f.google.com with SMTP id z16so20216030wrw.1 for ; Thu, 05 Jan 2023 08:43:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8lMJgjm1DvK1wLgcUqU/S1XJA9L6jfYX3fmzxSNKcYA=; b=K9aYT+Ech1VA7Vzll9S5stHUFVnUBqi2CxjynyXAMpotngTRqLGLRBm+/BcaqOXz+d lGjihXtYfLk1uYVy6PymNIQ6yW3puCRhvjNI0xuIaH+xrDRG91haacTImhLwnlLc470T SqdSQPRtj+hDsA2H3d3iSJ/odVGf6wE25vJslv4qta9zV4OMP7LFaey6JtdGBfJX+ty/ 2Z/aeoXSog5TeTWPUANCAifaPNCD9IrStFGcbd4dR0efRKJLTdnLZZrHjRtZxSwaUFdJ klG144UdA8P0UFX5p6vB/juBM+A6Jb+dcxH3PI2ouimoZ9/ANupnePX8VbEkFb747sgo DdRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8lMJgjm1DvK1wLgcUqU/S1XJA9L6jfYX3fmzxSNKcYA=; b=kooSUwf0qfQGmLjY49N8wTXJhUT61JjbWiyFSWUhKrQuCSWvRgyDXlupzti1HmtZl8 QCncTRfmrU6k86KymBRNzfWvRy9H11CAtTrO563nShVfeRburkk3xnh9Ue8hDyXfYdDd r39W5mNbQh2tmOg3jX0/veydWTJrI5MDpcMDJ5T1NfsoIaDa6Ytejei/lykzco0QRzrY 0Vbown3KjNaaAs7dqYNyWm8EwFrRl/4fZLgEeMd4ZDGZYpIJpuyMv4J/mNTZzIDbVLZ0 r+Ph/usbn/TEiLl3stHjS2arLYaQRY3jI+hm/fBuD2gP2L+tAXWPoAw7f3p7AmdJ3UD5 kkvg== X-Gm-Message-State: AFqh2krQE8z68c7L1N86EJK08M/U4NsrLArEKkobALVgDqeJdteAH2kq DgJcun/VKFAvowWE1WlL2Yggfw== X-Google-Smtp-Source: AMrXdXtBpRGasXG645y3Si0iD+NiZ5BM3DOkgfDeT3h2du/8jKfyT878h8Lq3dpg20hRYn9wWrgLXQ== X-Received: by 2002:adf:e5c7:0:b0:270:de92:7962 with SMTP id a7-20020adfe5c7000000b00270de927962mr31319470wrn.60.1672937008513; Thu, 05 Jan 2023 08:43:28 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id h10-20020a5d4fca000000b00281eab50380sm31319287wrw.117.2023.01.05.08.43.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:43:27 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 7D4F01FFC8; Thu, 5 Jan 2023 16:43:21 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH v2 17/21] gdbstub: fix address type of gdb_set_cpu_pc Date: Thu, 5 Jan 2023 16:43:16 +0000 Message-Id: <20230105164320.2164095-18-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:43:56 -0000 The underlying call uses vaddr and the comms API uses unsigned long long which will always fit. We don't need to deal in target_ulong here. Signed-off-by: Alex Bennée --- gdbstub/gdbstub.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index c293b8e43c..4547ca3367 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -535,7 +535,7 @@ static void gdb_process_breakpoint_remove_all(GDBProcess *p) } -static void gdb_set_cpu_pc(target_ulong pc) +static void gdb_set_cpu_pc(vaddr pc) { CPUState *cpu = gdbserver_state.c_cpu; @@ -1289,7 +1289,7 @@ static void handle_file_io(GArray *params, void *user_ctx) static void handle_step(GArray *params, void *user_ctx) { if (params->len) { - gdb_set_cpu_pc((target_ulong)get_param(params, 0)->val_ull); + gdb_set_cpu_pc(get_param(params, 0)->val_ull); } cpu_single_step(gdbserver_state.c_cpu, gdbserver_state.sstep_flags); -- 2.34.1 From MAILER-DAEMON Thu Jan 05 11:43:59 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTLS-0007ZV-Rw for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 11:43:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTLL-0007Ib-FJ for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:43:51 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTKz-00071v-7u for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:43:51 -0500 Received: by mail-wm1-x32d.google.com with SMTP id i17-20020a05600c355100b003d99434b1cfso1784526wmq.1 for ; Thu, 05 Jan 2023 08:43:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EICdGWLsvXUGSvCQECtKXiiCgC5xfnqqeSvmSsV0FWg=; b=T7444JiQSpzOLG9TJR9Tie7g1Yr0S4+rVUYGPpIOagMeCfXDnOnRME9mNj9LJkAOQs 2lVTagkoGnCqdsDP8OMwSgOKP0oC35S6UWRTGqX5hkHFizJ7zdPRjHdx1YCWUTaVjP2Z GARjbf3coQVlhTo06lO/kV6W7Nq+A5qDZo/0Fps15gcB6/eVrmyoQ8ojHwo7X/74mhAg TTc7mE081Va04+ij+NK2w8EvQs+w0ftR/0YcFk2+VitKw7xELSKnkuvefaFFjdLuXerV LlPMZbGOoc9xcH6+6w5fBW2IIHRWixFeipqT/hn052cAmHK+ltea8mJa10GkC5DE05f3 ry6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EICdGWLsvXUGSvCQECtKXiiCgC5xfnqqeSvmSsV0FWg=; b=EtynWf50GboWhkmuyPZK4vaiMi/WzD6/QrdtfkOX94v/L9j7/dObmEK3024Iuom57D mv5PSvlyzwAEAsSgxqW6GkdHbf+ImsZJeHxlvuLZHUnJuclnMMkB/vFB5UKZT6OYX7/O LemQOU323rEByFwqTl7RKiy23rfD2piSHcbtg7atwEVsl6TeRGT/BqEOnocbFF7dq7hN duP0etfSxgOEX4XEz+iBD39ZtG/4R+ZbCrU+z3raWmvSV7qmQbNIWPwxREDWX7fnI7Ib GY5jnaUxtj4ns9A/QedXELab8MGpUwVgZIfXQBnW2Y1rSmgfBRUn7PWDYT+9Rh8Uzr3S K+BA== X-Gm-Message-State: AFqh2kqpMASGHD9MOkOw5oI7U7SWhe3kFrpaFBoQZKJRiBjn62kXyR4l JJZ9nkibEkwm+29A8KoPIFLHIg== X-Google-Smtp-Source: AMrXdXsBuDZ76NHnP259lHETBC5MhlMBkJlMsb97ujNVQx893dNn3Ro4thEB4O8neTtbhDushk/g+g== X-Received: by 2002:a05:600c:601e:b0:3c6:e61e:ae71 with SMTP id az30-20020a05600c601e00b003c6e61eae71mr44523803wmb.1.1672937007684; Thu, 05 Jan 2023 08:43:27 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id u13-20020a05600c19cd00b003c6f1732f65sm3317242wmq.38.2023.01.05.08.43.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:43:25 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 1CAB01FFC3; Thu, 5 Jan 2023 16:43:21 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org, Fabiano Rosas Subject: [PATCH v2 11/21] gdbstub: move chunks of user code into own files Date: Thu, 5 Jan 2023 16:43:10 +0000 Message-Id: <20230105164320.2164095-12-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:43:53 -0000 The process was pretty similar to the softmmu move except we take the time to split stuff between user.c and user-target.c to avoid as much target specific compilation as possible. We also start to make use of our shiny new header scheme so the user-only helpers can be included without the rest of the exec/gsbstub.h cruft. As before we split some functions into user and softmmu versions Reviewed-by: Fabiano Rosas Signed-off-by: Alex Bennée --- v2 - separate splitting of functions - create user.h here --- gdbstub/internals.h | 30 +- include/exec/gdbstub.h | 21 -- include/gdbstub/user.h | 43 +++ gdbstub/gdbstub.c | 667 +---------------------------------------- gdbstub/softmmu.c | 89 ++++++ gdbstub/user-target.c | 283 +++++++++++++++++ gdbstub/user.c | 343 ++++++++++++++++++++- linux-user/main.c | 1 + linux-user/signal.c | 2 +- MAINTAINERS | 1 + gdbstub/meson.build | 3 + 11 files changed, 784 insertions(+), 699 deletions(-) create mode 100644 include/gdbstub/user.h create mode 100644 gdbstub/user-target.c diff --git a/gdbstub/internals.h b/gdbstub/internals.h index bbdc660233..568b432220 100644 --- a/gdbstub/internals.h +++ b/gdbstub/internals.h @@ -44,15 +44,6 @@ enum RSState { RS_CHKSUM2, }; -/* Temporary home */ -#ifdef CONFIG_USER_ONLY -typedef struct { - int fd; - char *socket_path; - int running_state; -} GDBUserState; -#endif - typedef struct GDBState { bool init; /* have we been initialised? */ CPUState *c_cpu; /* current CPU for step/continue ops */ @@ -65,9 +56,6 @@ typedef struct GDBState { int line_csum; /* checksum at the end of the packet */ GByteArray *last_packet; int signal; -#ifdef CONFIG_USER_ONLY - GDBUserState user; -#endif bool multiprocess; GDBProcess *processes; int process_num; @@ -125,6 +113,22 @@ int gdb_get_cpu_index(CPUState *cpu); void gdb_create_default_process(GDBState *s); +/* signal mapping, common for softmmu, specialised for user-mode */ +int gdb_signal_to_target(int sig); +int gdb_target_signal_to_gdb(int sig); + +int gdb_get_char(void); /* user only */ + +/** + * gdb_continue() - handle continue in mode specific way. + */ +void gdb_continue(void); + +/** + * gdb_continue_partial() - handle partial continue in mode specific way. + */ +int gdb_continue_partial(char *newstates); + /* * Helpers with separate softmmu and user implementations */ @@ -157,6 +161,8 @@ typedef union GdbCmdVariant { #define get_param(p, i) (&g_array_index(p, GdbCmdVariant, i)) void gdb_handle_query_rcmd(GArray *params, void *user_ctx); /* softmmu */ +void gdb_handle_query_offsets(GArray *params, void *user_ctx); /* user */ +void gdb_handle_query_xfer_auxv(GArray *params, void *user_ctx); /*user */ /* * Break/Watch point support - there is an implementation for softmmu diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index 1636fb3841..8fff5450ed 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -103,27 +103,6 @@ void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...); void gdb_do_syscallv(gdb_syscall_complete_cb cb, const char *fmt, va_list va); int use_gdb_syscalls(void); -#ifdef CONFIG_USER_ONLY -/** - * gdb_handlesig: yield control to gdb - * @cpu: CPU - * @sig: if non-zero, the signal number which caused us to stop - * - * This function yields control to gdb, when a user-mode-only target - * needs to stop execution. If @sig is non-zero, then we will send a - * stop packet to tell gdb that we have stopped because of this signal. - * - * This function will block (handling protocol requests from gdb) - * until gdb tells us to continue target execution. When it does - * return, the return value is a signal to deliver to the target, - * or 0 if no signal should be delivered, ie the signal that caused - * us to stop should be ignored. - */ -int gdb_handlesig(CPUState *, int); -void gdb_signalled(CPUArchState *, int); -void gdbserver_fork(CPUState *); -#endif - /* Get or set a register. Returns the size of the register. */ typedef int (*gdb_get_reg_cb)(CPUArchState *env, GByteArray *buf, int reg); typedef int (*gdb_set_reg_cb)(CPUArchState *env, uint8_t *buf, int reg); diff --git a/include/gdbstub/user.h b/include/gdbstub/user.h new file mode 100644 index 0000000000..d392e510c5 --- /dev/null +++ b/include/gdbstub/user.h @@ -0,0 +1,43 @@ +/* + * gdbstub user-mode only APIs + * + * Copyright (c) 2022 Linaro Ltd + * + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef GDBSTUB_USER_H +#define GDBSTUB_USER_H + +/** + * gdb_handlesig() - yield control to gdb + * @cpu: CPU + * @sig: if non-zero, the signal number which caused us to stop + * + * This function yields control to gdb, when a user-mode-only target + * needs to stop execution. If @sig is non-zero, then we will send a + * stop packet to tell gdb that we have stopped because of this signal. + * + * This function will block (handling protocol requests from gdb) + * until gdb tells us to continue target execution. When it does + * return, the return value is a signal to deliver to the target, + * or 0 if no signal should be delivered, ie the signal that caused + * us to stop should be ignored. + */ +int gdb_handlesig(CPUState *, int); + +/** + * gdb_signalled() - inform remote gdb of sig exit + * @as: current CPUArchState + * @sig: signal number + */ +void gdb_signalled(CPUArchState *as, int sig); + +/** + * gdbserver_fork() - disable gdb stub for child processes. + * @cs: CPU + */ +void gdbserver_fork(CPUState *cs); + + +#endif /* GDBSTUB_USER_H */ diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index d9afee5879..4bf99783a6 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -30,13 +30,12 @@ #include "trace.h" #include "exec/gdbstub.h" #ifdef CONFIG_USER_ONLY -#include "qemu.h" +#include "gdbstub/user.h" #else #include "hw/cpu/cluster.h" #include "hw/boards.h" #endif -#include "qemu/sockets.h" #include "sysemu/hw_accel.h" #include "sysemu/runstate.h" #include "semihosting/semihost.h" @@ -80,223 +79,6 @@ static inline int target_memory_rw_debug(CPUState *cpu, target_ulong addr, return cpu_memory_rw_debug(cpu, addr, buf, len, is_write); } -/* - * Return the GDB index for a given vCPU state. - * - * For user mode this is simply the thread id. - */ -#if defined(CONFIG_USER_ONLY) -int gdb_get_cpu_index(CPUState *cpu) -{ - TaskState *ts = (TaskState *) cpu->opaque; - return ts ? ts->ts_tid : -1; -} -#endif - -#ifdef CONFIG_USER_ONLY - -/* Map target signal numbers to GDB protocol signal numbers and vice - * versa. For user emulation's currently supported systems, we can - * assume most signals are defined. - */ - -static int gdb_signal_table[] = { - 0, - TARGET_SIGHUP, - TARGET_SIGINT, - TARGET_SIGQUIT, - TARGET_SIGILL, - TARGET_SIGTRAP, - TARGET_SIGABRT, - -1, /* SIGEMT */ - TARGET_SIGFPE, - TARGET_SIGKILL, - TARGET_SIGBUS, - TARGET_SIGSEGV, - TARGET_SIGSYS, - TARGET_SIGPIPE, - TARGET_SIGALRM, - TARGET_SIGTERM, - TARGET_SIGURG, - TARGET_SIGSTOP, - TARGET_SIGTSTP, - TARGET_SIGCONT, - TARGET_SIGCHLD, - TARGET_SIGTTIN, - TARGET_SIGTTOU, - TARGET_SIGIO, - TARGET_SIGXCPU, - TARGET_SIGXFSZ, - TARGET_SIGVTALRM, - TARGET_SIGPROF, - TARGET_SIGWINCH, - -1, /* SIGLOST */ - TARGET_SIGUSR1, - TARGET_SIGUSR2, -#ifdef TARGET_SIGPWR - TARGET_SIGPWR, -#else - -1, -#endif - -1, /* SIGPOLL */ - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, - -1, -#ifdef __SIGRTMIN - __SIGRTMIN + 1, - __SIGRTMIN + 2, - __SIGRTMIN + 3, - __SIGRTMIN + 4, - __SIGRTMIN + 5, - __SIGRTMIN + 6, - __SIGRTMIN + 7, - __SIGRTMIN + 8, - __SIGRTMIN + 9, - __SIGRTMIN + 10, - __SIGRTMIN + 11, - __SIGRTMIN + 12, - __SIGRTMIN + 13, - __SIGRTMIN + 14, - __SIGRTMIN + 15, - __SIGRTMIN + 16, - __SIGRTMIN + 17, - __SIGRTMIN + 18, - __SIGRTMIN + 19, - __SIGRTMIN + 20, - __SIGRTMIN + 21, - __SIGRTMIN + 22, - __SIGRTMIN + 23, - __SIGRTMIN + 24, - __SIGRTMIN + 25, - __SIGRTMIN + 26, - __SIGRTMIN + 27, - __SIGRTMIN + 28, - __SIGRTMIN + 29, - __SIGRTMIN + 30, - __SIGRTMIN + 31, - -1, /* SIGCANCEL */ - __SIGRTMIN, - __SIGRTMIN + 32, - __SIGRTMIN + 33, - __SIGRTMIN + 34, - __SIGRTMIN + 35, - __SIGRTMIN + 36, - __SIGRTMIN + 37, - __SIGRTMIN + 38, - __SIGRTMIN + 39, - __SIGRTMIN + 40, - __SIGRTMIN + 41, - __SIGRTMIN + 42, - __SIGRTMIN + 43, - __SIGRTMIN + 44, - __SIGRTMIN + 45, - __SIGRTMIN + 46, - __SIGRTMIN + 47, - __SIGRTMIN + 48, - __SIGRTMIN + 49, - __SIGRTMIN + 50, - __SIGRTMIN + 51, - __SIGRTMIN + 52, - __SIGRTMIN + 53, - __SIGRTMIN + 54, - __SIGRTMIN + 55, - __SIGRTMIN + 56, - __SIGRTMIN + 57, - __SIGRTMIN + 58, - __SIGRTMIN + 59, - __SIGRTMIN + 60, - __SIGRTMIN + 61, - __SIGRTMIN + 62, - __SIGRTMIN + 63, - __SIGRTMIN + 64, - __SIGRTMIN + 65, - __SIGRTMIN + 66, - __SIGRTMIN + 67, - __SIGRTMIN + 68, - __SIGRTMIN + 69, - __SIGRTMIN + 70, - __SIGRTMIN + 71, - __SIGRTMIN + 72, - __SIGRTMIN + 73, - __SIGRTMIN + 74, - __SIGRTMIN + 75, - __SIGRTMIN + 76, - __SIGRTMIN + 77, - __SIGRTMIN + 78, - __SIGRTMIN + 79, - __SIGRTMIN + 80, - __SIGRTMIN + 81, - __SIGRTMIN + 82, - __SIGRTMIN + 83, - __SIGRTMIN + 84, - __SIGRTMIN + 85, - __SIGRTMIN + 86, - __SIGRTMIN + 87, - __SIGRTMIN + 88, - __SIGRTMIN + 89, - __SIGRTMIN + 90, - __SIGRTMIN + 91, - __SIGRTMIN + 92, - __SIGRTMIN + 93, - __SIGRTMIN + 94, - __SIGRTMIN + 95, - -1, /* SIGINFO */ - -1, /* UNKNOWN */ - -1, /* DEFAULT */ - -1, - -1, - -1, - -1, - -1, - -1 -#endif -}; -#else -/* In system mode we only need SIGINT and SIGTRAP; other signals - are not yet supported. */ - -enum { - TARGET_SIGINT = 2, - TARGET_SIGTRAP = 5 -}; - -static int gdb_signal_table[] = { - -1, - -1, - TARGET_SIGINT, - -1, - -1, - TARGET_SIGTRAP -}; -#endif - -#ifdef CONFIG_USER_ONLY -static int target_signal_to_gdb (int sig) -{ - int i; - for (i = 0; i < ARRAY_SIZE (gdb_signal_table); i++) - if (gdb_signal_table[i] == sig) - return i; - return GDB_SIGNAL_UNKNOWN; -} -#endif - -static int gdb_signal_to_target (int sig) -{ - if (sig < ARRAY_SIZE (gdb_signal_table)) - return gdb_signal_table[sig]; - else - return -1; -} - typedef struct GDBRegisterState { int base_reg; int num_regs; @@ -329,34 +111,6 @@ void gdb_init_gdbserver_state(void) bool gdb_has_xml; -#ifdef CONFIG_USER_ONLY - -static int get_char(void) -{ - uint8_t ch; - int ret; - - for(;;) { - ret = recv(gdbserver_state.user.fd, &ch, 1, 0); - if (ret < 0) { - if (errno == ECONNRESET) { - gdbserver_state.user.fd = -1; - } - if (errno != EINTR) { - return -1; - } - } else if (ret == 0) { - close(gdbserver_state.user.fd); - gdbserver_state.user.fd = -1; - return -1; - } else { - break; - } - } - return ch; -} -#endif - /* * Return true if there is a GDB currently connected to the stub * and attached to a CPU @@ -401,104 +155,6 @@ static bool stub_can_reverse(void) #endif } -/* Resume execution. */ -static void gdb_continue(void) -{ - -#ifdef CONFIG_USER_ONLY - gdbserver_state.user.running_state = 1; - trace_gdbstub_op_continue(); -#else - if (!runstate_needs_reset()) { - trace_gdbstub_op_continue(); - vm_start(); - } -#endif -} - -/* - * Resume execution, per CPU actions. For user-mode emulation it's - * equivalent to gdb_continue. - */ -static int gdb_continue_partial(char *newstates) -{ - CPUState *cpu; - int res = 0; -#ifdef CONFIG_USER_ONLY - /* - * This is not exactly accurate, but it's an improvement compared to the - * previous situation, where only one CPU would be single-stepped. - */ - CPU_FOREACH(cpu) { - if (newstates[cpu->cpu_index] == 's') { - trace_gdbstub_op_stepping(cpu->cpu_index); - cpu_single_step(cpu, gdbserver_state.sstep_flags); - } - } - gdbserver_state.user.running_state = 1; -#else - int flag = 0; - - if (!runstate_needs_reset()) { - bool step_requested = false; - CPU_FOREACH(cpu) { - if (newstates[cpu->cpu_index] == 's') { - step_requested = true; - break; - } - } - - if (vm_prepare_start(step_requested)) { - return 0; - } - - CPU_FOREACH(cpu) { - switch (newstates[cpu->cpu_index]) { - case 0: - case 1: - break; /* nothing to do here */ - case 's': - trace_gdbstub_op_stepping(cpu->cpu_index); - cpu_single_step(cpu, gdbserver_state.sstep_flags); - cpu_resume(cpu); - flag = 1; - break; - case 'c': - trace_gdbstub_op_continue_cpu(cpu->cpu_index); - cpu_resume(cpu); - flag = 1; - break; - default: - res = -1; - break; - } - } - } - if (flag) { - qemu_clock_enable(QEMU_CLOCK_VIRTUAL, true); - } -#endif - return res; -} - -#ifdef CONFIG_USER_ONLY -void gdb_put_buffer(const uint8_t *buf, int len) -{ - int ret; - - while (len > 0) { - ret = send(gdbserver_state.user.fd, buf, len, 0); - if (ret < 0) { - if (errno != EINTR) - return; - } else { - buf += ret; - len -= ret; - } - } -} -#endif - /* writes 2*len+1 bytes in buf */ void gdb_memtohex(GString *buf, const uint8_t *mem, int len) { @@ -584,7 +240,7 @@ int gdb_put_packet_binary(const char *buf, int len, bool dump) gdbserver_state.last_packet->len); #ifdef CONFIG_USER_ONLY - i = get_char(); + i = gdb_get_char(); if (i < 0) return -1; if (i == '+') @@ -1940,23 +1596,6 @@ static void handle_query_thread_extra(GArray *params, void *user_ctx) gdb_put_strbuf(); } -#ifdef CONFIG_USER_ONLY -static void handle_query_offsets(GArray *params, void *user_ctx) -{ - TaskState *ts; - - ts = gdbserver_state.c_cpu->opaque; - g_string_printf(gdbserver_state.str_buf, - "Text=" TARGET_ABI_FMT_lx - ";Data=" TARGET_ABI_FMT_lx - ";Bss=" TARGET_ABI_FMT_lx, - ts->info->code_offset, - ts->info->data_offset, - ts->info->data_offset); - gdb_put_strbuf(); -} -#endif - static void handle_query_supported(GArray *params, void *user_ctx) { CPUClass *cc; @@ -2039,53 +1678,6 @@ static void handle_query_xfer_features(GArray *params, void *user_ctx) gdbserver_state.str_buf->len, true); } -#if defined(CONFIG_USER_ONLY) && defined(CONFIG_LINUX_USER) -static void handle_query_xfer_auxv(GArray *params, void *user_ctx) -{ - TaskState *ts; - unsigned long offset, len, saved_auxv, auxv_len; - - if (params->len < 2) { - gdb_put_packet("E22"); - return; - } - - offset = get_param(params, 0)->val_ul; - len = get_param(params, 1)->val_ul; - ts = gdbserver_state.c_cpu->opaque; - saved_auxv = ts->info->saved_auxv; - auxv_len = ts->info->auxv_len; - - if (offset >= auxv_len) { - gdb_put_packet("E00"); - return; - } - - if (len > (MAX_PACKET_LENGTH - 5) / 2) { - len = (MAX_PACKET_LENGTH - 5) / 2; - } - - if (len < auxv_len - offset) { - g_string_assign(gdbserver_state.str_buf, "m"); - } else { - g_string_assign(gdbserver_state.str_buf, "l"); - len = auxv_len - offset; - } - - g_byte_array_set_size(gdbserver_state.mem_buf, len); - if (target_memory_rw_debug(gdbserver_state.g_cpu, saved_auxv + offset, - gdbserver_state.mem_buf->data, len, false)) { - gdb_put_packet("E14"); - return; - } - - gdb_memtox(gdbserver_state.str_buf, - (const char *)gdbserver_state.mem_buf->data, len); - gdb_put_packet_binary(gdbserver_state.str_buf->str, - gdbserver_state.str_buf->len, true); -} -#endif - static void handle_query_attached(GArray *params, void *user_ctx) { gdb_put_packet(GDB_ATTACHED); @@ -2163,7 +1755,7 @@ static const GdbCmdParseEntry gdb_gen_query_table[] = { }, #ifdef CONFIG_USER_ONLY { - .handler = handle_query_offsets, + .handler = gdb_handle_query_offsets, .cmd = "Offsets", }, #else @@ -2193,7 +1785,7 @@ static const GdbCmdParseEntry gdb_gen_query_table[] = { }, #if defined(CONFIG_USER_ONLY) && defined(CONFIG_LINUX_USER) { - .handler = handle_query_xfer_auxv, + .handler = gdb_handle_query_xfer_auxv, .cmd = "Xfer:auxv:read::", .cmd_startswith = 1, .schema = "l,l0" @@ -2781,29 +2373,6 @@ void gdb_read_byte(uint8_t ch) } } -#ifdef CONFIG_USER_ONLY -/* Tell the remote gdb that the process has exited. */ -void gdb_exit(int code) -{ - char buf[4]; - - if (!gdbserver_state.init) { - return; - } - if (gdbserver_state.user.socket_path) { - unlink(gdbserver_state.user.socket_path); - } - if (gdbserver_state.user.fd < 0) { - return; - } - - trace_gdbstub_op_exiting((uint8_t)code); - - snprintf(buf, sizeof(buf), "W%02x", (uint8_t)code); - gdb_put_packet(buf); -} -#endif - /* * Create the process that will contain all the "orphan" CPUs (that are not * part of a CPU cluster). Note that if this process contains no CPUs, it won't @@ -2829,231 +2398,3 @@ void gdb_create_default_process(GDBState *s) process->target_xml[0] = '\0'; } -#ifdef CONFIG_USER_ONLY -int -gdb_handlesig(CPUState *cpu, int sig) -{ - char buf[256]; - int n; - - if (!gdbserver_state.init || gdbserver_state.user.fd < 0) { - return sig; - } - - /* disable single step if it was enabled */ - cpu_single_step(cpu, 0); - tb_flush(cpu); - - if (sig != 0) { - gdb_set_stop_cpu(cpu); - g_string_printf(gdbserver_state.str_buf, - "T%02xthread:", target_signal_to_gdb(sig)); - gdb_append_thread_id(cpu, gdbserver_state.str_buf); - g_string_append_c(gdbserver_state.str_buf, ';'); - gdb_put_strbuf(); - } - /* gdb_put_packet() might have detected that the peer terminated the - connection. */ - if (gdbserver_state.user.fd < 0) { - return sig; - } - - sig = 0; - gdbserver_state.state = RS_IDLE; - gdbserver_state.user.running_state = 0; - while (gdbserver_state.user.running_state == 0) { - n = read(gdbserver_state.user.fd, buf, 256); - if (n > 0) { - int i; - - for (i = 0; i < n; i++) { - gdb_read_byte(buf[i]); - } - } else { - /* XXX: Connection closed. Should probably wait for another - connection before continuing. */ - if (n == 0) { - close(gdbserver_state.user.fd); - } - gdbserver_state.user.fd = -1; - return sig; - } - } - sig = gdbserver_state.signal; - gdbserver_state.signal = 0; - return sig; -} - -/* Tell the remote gdb that the process has exited due to SIG. */ -void gdb_signalled(CPUArchState *env, int sig) -{ - char buf[4]; - - if (!gdbserver_state.init || gdbserver_state.user.fd < 0) { - return; - } - - snprintf(buf, sizeof(buf), "X%02x", target_signal_to_gdb(sig)); - gdb_put_packet(buf); -} - -static void gdb_accept_init(int fd) -{ - gdb_init_gdbserver_state(); - gdb_create_default_process(&gdbserver_state); - gdbserver_state.processes[0].attached = true; - gdbserver_state.c_cpu = gdb_first_attached_cpu(); - gdbserver_state.g_cpu = gdbserver_state.c_cpu; - gdbserver_state.user.fd = fd; - gdb_has_xml = false; -} - -static bool gdb_accept_socket(int gdb_fd) -{ - int fd; - - for(;;) { - fd = accept(gdb_fd, NULL, NULL); - if (fd < 0 && errno != EINTR) { - perror("accept socket"); - return false; - } else if (fd >= 0) { - qemu_set_cloexec(fd); - break; - } - } - - gdb_accept_init(fd); - return true; -} - -static int gdbserver_open_socket(const char *path) -{ - struct sockaddr_un sockaddr = {}; - int fd, ret; - - fd = socket(AF_UNIX, SOCK_STREAM, 0); - if (fd < 0) { - perror("create socket"); - return -1; - } - - sockaddr.sun_family = AF_UNIX; - pstrcpy(sockaddr.sun_path, sizeof(sockaddr.sun_path) - 1, path); - ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr)); - if (ret < 0) { - perror("bind socket"); - close(fd); - return -1; - } - ret = listen(fd, 1); - if (ret < 0) { - perror("listen socket"); - close(fd); - return -1; - } - - return fd; -} - -static bool gdb_accept_tcp(int gdb_fd) -{ - struct sockaddr_in sockaddr = {}; - socklen_t len; - int fd; - - for(;;) { - len = sizeof(sockaddr); - fd = accept(gdb_fd, (struct sockaddr *)&sockaddr, &len); - if (fd < 0 && errno != EINTR) { - perror("accept"); - return false; - } else if (fd >= 0) { - qemu_set_cloexec(fd); - break; - } - } - - /* set short latency */ - if (socket_set_nodelay(fd)) { - perror("setsockopt"); - close(fd); - return false; - } - - gdb_accept_init(fd); - return true; -} - -static int gdbserver_open_port(int port) -{ - struct sockaddr_in sockaddr; - int fd, ret; - - fd = socket(PF_INET, SOCK_STREAM, 0); - if (fd < 0) { - perror("socket"); - return -1; - } - qemu_set_cloexec(fd); - - socket_set_fast_reuse(fd); - - sockaddr.sin_family = AF_INET; - sockaddr.sin_port = htons(port); - sockaddr.sin_addr.s_addr = 0; - ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr)); - if (ret < 0) { - perror("bind"); - close(fd); - return -1; - } - ret = listen(fd, 1); - if (ret < 0) { - perror("listen"); - close(fd); - return -1; - } - - return fd; -} - -int gdbserver_start(const char *port_or_path) -{ - int port = g_ascii_strtoull(port_or_path, NULL, 10); - int gdb_fd; - - if (port > 0) { - gdb_fd = gdbserver_open_port(port); - } else { - gdb_fd = gdbserver_open_socket(port_or_path); - } - - if (gdb_fd < 0) { - return -1; - } - - if (port > 0 && gdb_accept_tcp(gdb_fd)) { - return 0; - } else if (gdb_accept_socket(gdb_fd)) { - gdbserver_state.user.socket_path = g_strdup(port_or_path); - return 0; - } - - /* gone wrong */ - close(gdb_fd); - return -1; -} - -/* Disable gdb stub for child processes. */ -void gdbserver_fork(CPUState *cpu) -{ - if (!gdbserver_state.init || gdbserver_state.user.fd < 0) { - return; - } - close(gdbserver_state.user.fd); - gdbserver_state.user.fd = -1; - cpu_breakpoint_remove_all(cpu, BP_GDB); - cpu_watchpoint_remove_all(cpu, BP_GDB); -} -#endif diff --git a/gdbstub/softmmu.c b/gdbstub/softmmu.c index 3a88d0ebb4..ee5daad0cf 100644 --- a/gdbstub/softmmu.c +++ b/gdbstub/softmmu.c @@ -430,6 +430,95 @@ void gdb_handle_query_rcmd(GArray *params, void *user_ctx) gdb_put_packet("OK"); } +/* + * Execution state helpers + */ + +void gdb_continue(void) +{ + if (!runstate_needs_reset()) { + trace_gdbstub_op_continue(); + vm_start(); + } +} + +/* + * Resume execution, per CPU actions. + */ +int gdb_continue_partial(char *newstates) +{ + CPUState *cpu; + int res = 0; + int flag = 0; + + if (!runstate_needs_reset()) { + bool step_requested = false; + CPU_FOREACH(cpu) { + if (newstates[cpu->cpu_index] == 's') { + step_requested = true; + break; + } + } + + if (vm_prepare_start(step_requested)) { + return 0; + } + + CPU_FOREACH(cpu) { + switch (newstates[cpu->cpu_index]) { + case 0: + case 1: + break; /* nothing to do here */ + case 's': + trace_gdbstub_op_stepping(cpu->cpu_index); + cpu_single_step(cpu, gdbserver_state.sstep_flags); + cpu_resume(cpu); + flag = 1; + break; + case 'c': + trace_gdbstub_op_continue_cpu(cpu->cpu_index); + cpu_resume(cpu); + flag = 1; + break; + default: + res = -1; + break; + } + } + } + if (flag) { + qemu_clock_enable(QEMU_CLOCK_VIRTUAL, true); + } + return res; +} + +/* + * Signal Handling - in system mode we only need SIGINT and SIGTRAP; other + * signals are not yet supported. + */ + +enum { + TARGET_SIGINT = 2, + TARGET_SIGTRAP = 5 +}; + +static int gdb_signal_table[] = { + -1, + -1, + TARGET_SIGINT, + -1, + -1, + TARGET_SIGTRAP +}; + +int gdb_signal_to_target (int sig) +{ + if (sig < ARRAY_SIZE (gdb_signal_table)) + return gdb_signal_table[sig]; + else + return -1; +} + /* * Break/Watch point helpers */ diff --git a/gdbstub/user-target.c b/gdbstub/user-target.c new file mode 100644 index 0000000000..83e04e1c23 --- /dev/null +++ b/gdbstub/user-target.c @@ -0,0 +1,283 @@ +/* + * Target specific user-mode handling + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2022 Linaro Ltd + * + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#include "qemu/osdep.h" +#include "exec/gdbstub.h" +#include "qemu.h" +#include "internals.h" + +extern GDBState gdbserver_state; + +/* + * Map target signal numbers to GDB protocol signal numbers and vice + * versa. For user emulation's currently supported systems, we can + * assume most signals are defined. + */ + +static int gdb_signal_table[] = { + 0, + TARGET_SIGHUP, + TARGET_SIGINT, + TARGET_SIGQUIT, + TARGET_SIGILL, + TARGET_SIGTRAP, + TARGET_SIGABRT, + -1, /* SIGEMT */ + TARGET_SIGFPE, + TARGET_SIGKILL, + TARGET_SIGBUS, + TARGET_SIGSEGV, + TARGET_SIGSYS, + TARGET_SIGPIPE, + TARGET_SIGALRM, + TARGET_SIGTERM, + TARGET_SIGURG, + TARGET_SIGSTOP, + TARGET_SIGTSTP, + TARGET_SIGCONT, + TARGET_SIGCHLD, + TARGET_SIGTTIN, + TARGET_SIGTTOU, + TARGET_SIGIO, + TARGET_SIGXCPU, + TARGET_SIGXFSZ, + TARGET_SIGVTALRM, + TARGET_SIGPROF, + TARGET_SIGWINCH, + -1, /* SIGLOST */ + TARGET_SIGUSR1, + TARGET_SIGUSR2, +#ifdef TARGET_SIGPWR + TARGET_SIGPWR, +#else + -1, +#endif + -1, /* SIGPOLL */ + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, + -1, +#ifdef __SIGRTMIN + __SIGRTMIN + 1, + __SIGRTMIN + 2, + __SIGRTMIN + 3, + __SIGRTMIN + 4, + __SIGRTMIN + 5, + __SIGRTMIN + 6, + __SIGRTMIN + 7, + __SIGRTMIN + 8, + __SIGRTMIN + 9, + __SIGRTMIN + 10, + __SIGRTMIN + 11, + __SIGRTMIN + 12, + __SIGRTMIN + 13, + __SIGRTMIN + 14, + __SIGRTMIN + 15, + __SIGRTMIN + 16, + __SIGRTMIN + 17, + __SIGRTMIN + 18, + __SIGRTMIN + 19, + __SIGRTMIN + 20, + __SIGRTMIN + 21, + __SIGRTMIN + 22, + __SIGRTMIN + 23, + __SIGRTMIN + 24, + __SIGRTMIN + 25, + __SIGRTMIN + 26, + __SIGRTMIN + 27, + __SIGRTMIN + 28, + __SIGRTMIN + 29, + __SIGRTMIN + 30, + __SIGRTMIN + 31, + -1, /* SIGCANCEL */ + __SIGRTMIN, + __SIGRTMIN + 32, + __SIGRTMIN + 33, + __SIGRTMIN + 34, + __SIGRTMIN + 35, + __SIGRTMIN + 36, + __SIGRTMIN + 37, + __SIGRTMIN + 38, + __SIGRTMIN + 39, + __SIGRTMIN + 40, + __SIGRTMIN + 41, + __SIGRTMIN + 42, + __SIGRTMIN + 43, + __SIGRTMIN + 44, + __SIGRTMIN + 45, + __SIGRTMIN + 46, + __SIGRTMIN + 47, + __SIGRTMIN + 48, + __SIGRTMIN + 49, + __SIGRTMIN + 50, + __SIGRTMIN + 51, + __SIGRTMIN + 52, + __SIGRTMIN + 53, + __SIGRTMIN + 54, + __SIGRTMIN + 55, + __SIGRTMIN + 56, + __SIGRTMIN + 57, + __SIGRTMIN + 58, + __SIGRTMIN + 59, + __SIGRTMIN + 60, + __SIGRTMIN + 61, + __SIGRTMIN + 62, + __SIGRTMIN + 63, + __SIGRTMIN + 64, + __SIGRTMIN + 65, + __SIGRTMIN + 66, + __SIGRTMIN + 67, + __SIGRTMIN + 68, + __SIGRTMIN + 69, + __SIGRTMIN + 70, + __SIGRTMIN + 71, + __SIGRTMIN + 72, + __SIGRTMIN + 73, + __SIGRTMIN + 74, + __SIGRTMIN + 75, + __SIGRTMIN + 76, + __SIGRTMIN + 77, + __SIGRTMIN + 78, + __SIGRTMIN + 79, + __SIGRTMIN + 80, + __SIGRTMIN + 81, + __SIGRTMIN + 82, + __SIGRTMIN + 83, + __SIGRTMIN + 84, + __SIGRTMIN + 85, + __SIGRTMIN + 86, + __SIGRTMIN + 87, + __SIGRTMIN + 88, + __SIGRTMIN + 89, + __SIGRTMIN + 90, + __SIGRTMIN + 91, + __SIGRTMIN + 92, + __SIGRTMIN + 93, + __SIGRTMIN + 94, + __SIGRTMIN + 95, + -1, /* SIGINFO */ + -1, /* UNKNOWN */ + -1, /* DEFAULT */ + -1, + -1, + -1, + -1, + -1, + -1 +#endif +}; + +int gdb_signal_to_target (int sig) +{ + if (sig < ARRAY_SIZE (gdb_signal_table)) + return gdb_signal_table[sig]; + else + return -1; +} + +int gdb_target_signal_to_gdb(int sig) +{ + int i; + for (i = 0; i < ARRAY_SIZE (gdb_signal_table); i++) + if (gdb_signal_table[i] == sig) + return i; + return GDB_SIGNAL_UNKNOWN; +} + +int gdb_get_cpu_index(CPUState *cpu) +{ + TaskState *ts = (TaskState *) cpu->opaque; + return ts ? ts->ts_tid : -1; +} + +/* + * User-mode specific command helpers + */ + +void gdb_handle_query_offsets(GArray *params, void *user_ctx) +{ + TaskState *ts; + + ts = gdbserver_state.c_cpu->opaque; + g_string_printf(gdbserver_state.str_buf, + "Text=" TARGET_ABI_FMT_lx + ";Data=" TARGET_ABI_FMT_lx + ";Bss=" TARGET_ABI_FMT_lx, + ts->info->code_offset, + ts->info->data_offset, + ts->info->data_offset); + gdb_put_strbuf(); +} + +/* Partial user only duplicate of helper in gdbstub.c */ +static inline int target_memory_rw_debug(CPUState *cpu, target_ulong addr, + uint8_t *buf, int len, bool is_write) +{ + CPUClass *cc; + cc = CPU_GET_CLASS(cpu); + if (cc->memory_rw_debug) { + return cc->memory_rw_debug(cpu, addr, buf, len, is_write); + } + return cpu_memory_rw_debug(cpu, addr, buf, len, is_write); +} + + +#if defined(CONFIG_LINUX_USER) +void gdb_handle_query_xfer_auxv(GArray *params, void *user_ctx) +{ + TaskState *ts; + unsigned long offset, len, saved_auxv, auxv_len; + + if (params->len < 2) { + gdb_put_packet("E22"); + return; + } + + offset = get_param(params, 0)->val_ul; + len = get_param(params, 1)->val_ul; + ts = gdbserver_state.c_cpu->opaque; + saved_auxv = ts->info->saved_auxv; + auxv_len = ts->info->auxv_len; + + if (offset >= auxv_len) { + gdb_put_packet("E00"); + return; + } + + if (len > (MAX_PACKET_LENGTH - 5) / 2) { + len = (MAX_PACKET_LENGTH - 5) / 2; + } + + if (len < auxv_len - offset) { + g_string_assign(gdbserver_state.str_buf, "m"); + } else { + g_string_assign(gdbserver_state.str_buf, "l"); + len = auxv_len - offset; + } + + g_byte_array_set_size(gdbserver_state.mem_buf, len); + if (target_memory_rw_debug(gdbserver_state.g_cpu, saved_auxv + offset, + gdbserver_state.mem_buf->data, len, false)) { + gdb_put_packet("E14"); + return; + } + + gdb_memtox(gdbserver_state.str_buf, + (const char *)gdbserver_state.mem_buf->data, len); + gdb_put_packet_binary(gdbserver_state.str_buf->str, + gdbserver_state.str_buf->len, true); +} +#endif diff --git a/gdbstub/user.c b/gdbstub/user.c index 4c2b41eefa..4898f16c90 100644 --- a/gdbstub/user.c +++ b/gdbstub/user.c @@ -10,13 +10,352 @@ */ #include "qemu/osdep.h" +#include "qemu/cutils.h" +#include "qemu/sockets.h" #include "exec/hwaddr.h" +#include "exec/tb-flush.h" #include "exec/gdbstub.h" +#include "gdbstub/user.h" #include "hw/core/cpu.h" -/* temp hack */ -#define CONFIG_USER_ONLY 1 +#include "trace.h" #include "internals.h" +/* Common state */ +extern GDBState gdbserver_state; + +/* User-mode specific state */ +typedef struct { + int fd; + char *socket_path; + int running_state; +} GDBUserState; + +static GDBUserState gdbserver_user_state; + +int gdb_get_char(void) +{ + uint8_t ch; + int ret; + + for(;;) { + ret = recv(gdbserver_user_state.fd, &ch, 1, 0); + if (ret < 0) { + if (errno == ECONNRESET) { + gdbserver_user_state.fd = -1; + } + if (errno != EINTR) { + return -1; + } + } else if (ret == 0) { + close(gdbserver_user_state.fd); + gdbserver_user_state.fd = -1; + return -1; + } else { + break; + } + } + return ch; +} + +void gdb_put_buffer(const uint8_t *buf, int len) +{ + int ret; + + while (len > 0) { + ret = send(gdbserver_user_state.fd, buf, len, 0); + if (ret < 0) { + if (errno != EINTR) + return; + } else { + buf += ret; + len -= ret; + } + } +} + +/* Tell the remote gdb that the process has exited. */ +void gdb_exit(int code) +{ + char buf[4]; + + if (!gdbserver_state.init) { + return; + } + if (gdbserver_user_state.socket_path) { + unlink(gdbserver_user_state.socket_path); + } + if (gdbserver_user_state.fd < 0) { + return; + } + + trace_gdbstub_op_exiting((uint8_t)code); + + snprintf(buf, sizeof(buf), "W%02x", (uint8_t)code); + gdb_put_packet(buf); +} + +int gdb_handlesig(CPUState *cpu, int sig) +{ + char buf[256]; + int n; + + if (!gdbserver_state.init || gdbserver_user_state.fd < 0) { + return sig; + } + + /* disable single step if it was enabled */ + cpu_single_step(cpu, 0); + tb_flush(cpu); + + if (sig != 0) { + gdb_set_stop_cpu(cpu); + g_string_printf(gdbserver_state.str_buf, + "T%02xthread:", gdb_target_signal_to_gdb(sig)); + gdb_append_thread_id(cpu, gdbserver_state.str_buf); + g_string_append_c(gdbserver_state.str_buf, ';'); + gdb_put_strbuf(); + } + /* gdb_put_packet() might have detected that the peer terminated the + connection. */ + if (gdbserver_user_state.fd < 0) { + return sig; + } + + sig = 0; + gdbserver_state.state = RS_IDLE; + gdbserver_user_state.running_state = 0; + while (gdbserver_user_state.running_state == 0) { + n = read(gdbserver_user_state.fd, buf, 256); + if (n > 0) { + int i; + + for (i = 0; i < n; i++) { + gdb_read_byte(buf[i]); + } + } else { + /* XXX: Connection closed. Should probably wait for another + connection before continuing. */ + if (n == 0) { + close(gdbserver_user_state.fd); + } + gdbserver_user_state.fd = -1; + return sig; + } + } + sig = gdbserver_state.signal; + gdbserver_state.signal = 0; + return sig; +} + +/* Tell the remote gdb that the process has exited due to SIG. */ +void gdb_signalled(CPUArchState *env, int sig) +{ + char buf[4]; + + if (!gdbserver_state.init || gdbserver_user_state.fd < 0) { + return; + } + + snprintf(buf, sizeof(buf), "X%02x", gdb_target_signal_to_gdb(sig)); + gdb_put_packet(buf); +} + +static void gdb_accept_init(int fd) +{ + gdb_init_gdbserver_state(); + gdb_create_default_process(&gdbserver_state); + gdbserver_state.processes[0].attached = true; + gdbserver_state.c_cpu = gdb_first_attached_cpu(); + gdbserver_state.g_cpu = gdbserver_state.c_cpu; + gdbserver_user_state.fd = fd; + gdb_has_xml = false; +} + +static bool gdb_accept_socket(int gdb_fd) +{ + int fd; + + for(;;) { + fd = accept(gdb_fd, NULL, NULL); + if (fd < 0 && errno != EINTR) { + perror("accept socket"); + return false; + } else if (fd >= 0) { + qemu_set_cloexec(fd); + break; + } + } + + gdb_accept_init(fd); + return true; +} + +static int gdbserver_open_socket(const char *path) +{ + struct sockaddr_un sockaddr = {}; + int fd, ret; + + fd = socket(AF_UNIX, SOCK_STREAM, 0); + if (fd < 0) { + perror("create socket"); + return -1; + } + + sockaddr.sun_family = AF_UNIX; + pstrcpy(sockaddr.sun_path, sizeof(sockaddr.sun_path) - 1, path); + ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr)); + if (ret < 0) { + perror("bind socket"); + close(fd); + return -1; + } + ret = listen(fd, 1); + if (ret < 0) { + perror("listen socket"); + close(fd); + return -1; + } + + return fd; +} + +static bool gdb_accept_tcp(int gdb_fd) +{ + struct sockaddr_in sockaddr = {}; + socklen_t len; + int fd; + + for(;;) { + len = sizeof(sockaddr); + fd = accept(gdb_fd, (struct sockaddr *)&sockaddr, &len); + if (fd < 0 && errno != EINTR) { + perror("accept"); + return false; + } else if (fd >= 0) { + qemu_set_cloexec(fd); + break; + } + } + + /* set short latency */ + if (socket_set_nodelay(fd)) { + perror("setsockopt"); + close(fd); + return false; + } + + gdb_accept_init(fd); + return true; +} + +static int gdbserver_open_port(int port) +{ + struct sockaddr_in sockaddr; + int fd, ret; + + fd = socket(PF_INET, SOCK_STREAM, 0); + if (fd < 0) { + perror("socket"); + return -1; + } + qemu_set_cloexec(fd); + + socket_set_fast_reuse(fd); + + sockaddr.sin_family = AF_INET; + sockaddr.sin_port = htons(port); + sockaddr.sin_addr.s_addr = 0; + ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr)); + if (ret < 0) { + perror("bind"); + close(fd); + return -1; + } + ret = listen(fd, 1); + if (ret < 0) { + perror("listen"); + close(fd); + return -1; + } + + return fd; +} + +int gdbserver_start(const char *port_or_path) +{ + int port = g_ascii_strtoull(port_or_path, NULL, 10); + int gdb_fd; + + if (port > 0) { + gdb_fd = gdbserver_open_port(port); + } else { + gdb_fd = gdbserver_open_socket(port_or_path); + } + + if (gdb_fd < 0) { + return -1; + } + + if (port > 0 && gdb_accept_tcp(gdb_fd)) { + return 0; + } else if (gdb_accept_socket(gdb_fd)) { + gdbserver_user_state.socket_path = g_strdup(port_or_path); + return 0; + } + + /* gone wrong */ + close(gdb_fd); + return -1; +} + +/* Disable gdb stub for child processes. */ +void gdbserver_fork(CPUState *cpu) +{ + if (!gdbserver_state.init || gdbserver_user_state.fd < 0) { + return; + } + close(gdbserver_user_state.fd); + gdbserver_user_state.fd = -1; + cpu_breakpoint_remove_all(cpu, BP_GDB); + /* no cpu_watchpoint_remove_all for user-mode */ +} + +/* + * Execution state helpers + */ + +void gdb_continue(void) +{ + gdbserver_user_state.running_state = 1; + trace_gdbstub_op_continue(); +} + +/* + * Resume execution, for user-mode emulation it's equivalent to + * gdb_continue. + */ +int gdb_continue_partial(char *newstates) +{ + CPUState *cpu; + int res = 0; + /* + * This is not exactly accurate, but it's an improvement compared to the + * previous situation, where only one CPU would be single-stepped. + */ + CPU_FOREACH(cpu) { + if (newstates[cpu->cpu_index] == 's') { + trace_gdbstub_op_stepping(cpu->cpu_index); + cpu_single_step(cpu, gdbserver_state.sstep_flags); + } + } + gdbserver_user_state.running_state = 1; + return res; +} + +/* + * Break/Watch point helpers + */ + bool gdb_supports_guest_debug(void) { /* user-mode == TCG == supported */ diff --git a/linux-user/main.c b/linux-user/main.c index a17fed045b..68aaf4bd58 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -40,6 +40,7 @@ #include "qemu/plugin.h" #include "exec/exec-all.h" #include "exec/gdbstub.h" +#include "gdbstub/user.h" #include "tcg/tcg.h" #include "qemu/timer.h" #include "qemu/envlist.h" diff --git a/linux-user/signal.c b/linux-user/signal.c index 61c6fa3fcf..84f06043d8 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -18,7 +18,7 @@ */ #include "qemu/osdep.h" #include "qemu/bitops.h" -#include "exec/gdbstub.h" +#include "gdbstub/user.h" #include "hw/core/tcg-cpu-ops.h" #include diff --git a/MAINTAINERS b/MAINTAINERS index 7a40d4d865..0b5d660bda 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2715,6 +2715,7 @@ S: Maintained F: docs/system/gdb.rst F: gdbstub/* F: include/exec/gdbstub.h +F: include/gdbstub/* F: gdb-xml/ F: tests/tcg/multiarch/gdbstub/ F: scripts/feature_to_c.sh diff --git a/gdbstub/meson.build b/gdbstub/meson.build index fc895a2c39..827f062af6 100644 --- a/gdbstub/meson.build +++ b/gdbstub/meson.build @@ -7,3 +7,6 @@ specific_ss.add(files('gdbstub.c')) softmmu_ss.add(files('softmmu.c')) user_ss.add(files('user.c')) + +# and BSD? +specific_ss.add(when: 'CONFIG_LINUX_USER', if_true: files('user-target.c')) -- 2.34.1 From MAILER-DAEMON Thu Jan 05 11:44:00 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTLU-0007cN-9K for mharc-qemu-riscv@gnu.org; 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Thu, 05 Jan 2023 08:43:25 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 4EEC31FFB8; Thu, 5 Jan 2023 16:43:21 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH v2 14/21] gdbstub: specialise target_memory_rw_debug Date: Thu, 5 Jan 2023 16:43:13 +0000 Message-Id: <20230105164320.2164095-15-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:43:54 -0000 The two implementations are different enough to encourage having a specialisation and we can move some of the softmmu only stuff out of gdbstub. Signed-off-by: Alex Bennée --- gdbstub/internals.h | 19 ++++++++++++ gdbstub/gdbstub.c | 73 +++++++-------------------------------------- gdbstub/softmmu.c | 51 +++++++++++++++++++++++++++++++ gdbstub/user.c | 15 ++++++++++ 4 files changed, 96 insertions(+), 62 deletions(-) diff --git a/gdbstub/internals.h b/gdbstub/internals.h index 646d2c4e82..55f3d820aa 100644 --- a/gdbstub/internals.h +++ b/gdbstub/internals.h @@ -181,6 +181,10 @@ void gdb_handle_query_xfer_auxv(GArray *params, void *user_ctx); /*user */ void gdb_handle_query_attached(GArray *params, void *user_ctx); /* both */ +/* softmmu only */ +void gdb_handle_query_qemu_phy_mem_mode(GArray *params, void *user_ctx); +void gdb_handle_set_qemu_phy_mem_mode(GArray *params, void *user_ctx); + /* * Break/Watch point support - there is an implementation for softmmu * and user mode. @@ -190,4 +194,19 @@ int gdb_breakpoint_insert(CPUState *cs, int type, hwaddr addr, hwaddr len); int gdb_breakpoint_remove(CPUState *cs, int type, hwaddr addr, hwaddr len); void gdb_breakpoint_remove_all(CPUState *cs); +/** + * gdb_target_memory_rw_debug() - handle debug access to memory + * @cs: CPUState + * @addr: nominal address, could be an entire physical address + * @buf: data + * @len: length of access + * @is_write: is it a write operation + * + * This function is specialised depending on the mode we are running + * in. For softmmu guests we can switch the interpretation of the + * address to a physical address. + */ +int gdb_target_memory_rw_debug(CPUState *cs, hwaddr addr, + uint8_t *buf, int len, bool is_write); + #endif /* GDBSTUB_INTERNALS_H */ diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 0d90685c72..91021859a1 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -46,33 +46,6 @@ #include "internals.h" -#ifndef CONFIG_USER_ONLY -static int phy_memory_mode; -#endif - -static inline int target_memory_rw_debug(CPUState *cpu, target_ulong addr, - uint8_t *buf, int len, bool is_write) -{ - CPUClass *cc; - -#ifndef CONFIG_USER_ONLY - if (phy_memory_mode) { - if (is_write) { - cpu_physical_memory_write(addr, buf, len); - } else { - cpu_physical_memory_read(addr, buf, len); - } - return 0; - } -#endif - - cc = CPU_GET_CLASS(cpu); - if (cc->memory_rw_debug) { - return cc->memory_rw_debug(cpu, addr, buf, len, is_write); - } - return cpu_memory_rw_debug(cpu, addr, buf, len, is_write); -} - typedef struct GDBRegisterState { int base_reg; int num_regs; @@ -1194,11 +1167,11 @@ static void handle_write_mem(GArray *params, void *user_ctx) } gdb_hextomem(gdbserver_state.mem_buf, get_param(params, 2)->data, - get_param(params, 1)->val_ull); - if (target_memory_rw_debug(gdbserver_state.g_cpu, - get_param(params, 0)->val_ull, - gdbserver_state.mem_buf->data, - gdbserver_state.mem_buf->len, true)) { + get_param(params, 1)->val_ull); + if (gdb_target_memory_rw_debug(gdbserver_state.g_cpu, + get_param(params, 0)->val_ull, + gdbserver_state.mem_buf->data, + gdbserver_state.mem_buf->len, true)) { gdb_put_packet("E14"); return; } @@ -1222,10 +1195,10 @@ static void handle_read_mem(GArray *params, void *user_ctx) g_byte_array_set_size(gdbserver_state.mem_buf, get_param(params, 1)->val_ull); - if (target_memory_rw_debug(gdbserver_state.g_cpu, - get_param(params, 0)->val_ull, - gdbserver_state.mem_buf->data, - gdbserver_state.mem_buf->len, false)) { + if (gdb_target_memory_rw_debug(gdbserver_state.g_cpu, + get_param(params, 0)->val_ull, + gdbserver_state.mem_buf->data, + gdbserver_state.mem_buf->len, false)) { gdb_put_packet("E14"); return; } @@ -1675,30 +1648,6 @@ static void handle_query_qemu_supported(GArray *params, void *user_ctx) gdb_put_strbuf(); } -#ifndef CONFIG_USER_ONLY -static void handle_query_qemu_phy_mem_mode(GArray *params, - void *user_ctx) -{ - g_string_printf(gdbserver_state.str_buf, "%d", phy_memory_mode); - gdb_put_strbuf(); -} - -static void handle_set_qemu_phy_mem_mode(GArray *params, void *user_ctx) -{ - if (!params->len) { - gdb_put_packet("E22"); - return; - } - - if (!get_param(params, 0)->val_ul) { - phy_memory_mode = 0; - } else { - phy_memory_mode = 1; - } - gdb_put_packet("OK"); -} -#endif - static const GdbCmdParseEntry gdb_gen_query_set_common_table[] = { /* Order is important if has same prefix */ { @@ -1789,7 +1738,7 @@ static const GdbCmdParseEntry gdb_gen_query_table[] = { }, #ifndef CONFIG_USER_ONLY { - .handler = handle_query_qemu_phy_mem_mode, + .handler = gdb_handle_query_qemu_phy_mem_mode, .cmd = "qemu.PhyMemMode", }, #endif @@ -1805,7 +1754,7 @@ static const GdbCmdParseEntry gdb_gen_set_table[] = { }, #ifndef CONFIG_USER_ONLY { - .handler = handle_set_qemu_phy_mem_mode, + .handler = gdb_handle_set_qemu_phy_mem_mode, .cmd = "qemu.PhyMemMode:", .cmd_startswith = 1, .schema = "l0" diff --git a/gdbstub/softmmu.c b/gdbstub/softmmu.c index 19fcb3be7d..c42230acca 100644 --- a/gdbstub/softmmu.c +++ b/gdbstub/softmmu.c @@ -409,9 +409,60 @@ void gdb_exit(int code) qemu_chr_fe_deinit(&gdbserver_system_state.chr, true); } +/* + * Memory access + */ +static int phy_memory_mode; + +int gdb_target_memory_rw_debug(CPUState *cpu, hwaddr addr, + uint8_t *buf, int len, bool is_write) +{ + CPUClass *cc; + + if (phy_memory_mode) { + if (is_write) { + cpu_physical_memory_write(addr, buf, len); + } else { + cpu_physical_memory_read(addr, buf, len); + } + return 0; + } + + cc = CPU_GET_CLASS(cpu); + if (cc->memory_rw_debug) { + return cc->memory_rw_debug(cpu, addr, buf, len, is_write); + } + + return cpu_memory_rw_debug(cpu, addr, buf, len, is_write); +} + + /* * Softmmu specific command helpers */ + +void gdb_handle_query_qemu_phy_mem_mode(GArray *params, + void *user_ctx) +{ + g_string_printf(gdbserver_state.str_buf, "%d", phy_memory_mode); + gdb_put_strbuf(); +} + +void gdb_handle_set_qemu_phy_mem_mode(GArray *params, void *user_ctx) +{ + if (!params->len) { + gdb_put_packet("E22"); + return; + } + + if (!get_param(params, 0)->val_ul) { + phy_memory_mode = 0; + } else { + phy_memory_mode = 1; + } + gdb_put_packet("OK"); +} + void gdb_handle_query_rcmd(GArray *params, void *user_ctx) { const guint8 zero = 0; diff --git a/gdbstub/user.c b/gdbstub/user.c index a668b16952..74f541223c 100644 --- a/gdbstub/user.c +++ b/gdbstub/user.c @@ -376,6 +376,21 @@ int gdb_continue_partial(char *newstates) return res; } +/* + * Memory access helpers + */ +int gdb_target_memory_rw_debug(CPUState *cpu, hwaddr addr, + uint8_t *buf, int len, bool is_write) +{ + CPUClass *cc; + + cc = CPU_GET_CLASS(cpu); + if (cc->memory_rw_debug) { + return cc->memory_rw_debug(cpu, addr, buf, len, is_write); + } + return cpu_memory_rw_debug(cpu, addr, buf, len, is_write); +} + /* * Break/Watch point helpers */ -- 2.34.1 From MAILER-DAEMON Thu Jan 05 11:44:00 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTLU-0007db-Kd for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 11:44:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTLQ-0007OV-2A for qemu-riscv@nongnu.org; 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Thu, 05 Jan 2023 08:43:27 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id B7CBF1FFCB; Thu, 5 Jan 2023 16:43:21 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH v2 21/21] gdbstub: only compile gdbstub twice for whole build Date: Thu, 5 Jan 2023 16:43:20 +0000 Message-Id: <20230105164320.2164095-22-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:43:56 -0000 Now we have removed any target specific bits from the core gdbstub code we only need to build it twice. We have to jump a few meson hoops to manually define the CONFIG_USER_ONLY symbol but it seems to work. Signed-off-by: Alex Bennée --- gdbstub/gdbstub.c | 3 +-- gdbstub/user-target.c | 2 +- gdbstub/meson.build | 32 ++++++++++++++++++++++++++++---- 3 files changed, 30 insertions(+), 7 deletions(-) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 57bbda3505..0dbb9f5338 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -39,7 +39,6 @@ #include "sysemu/hw_accel.h" #include "sysemu/runstate.h" -#include "exec/exec-all.h" #include "exec/tb-flush.h" #include "exec/hwaddr.h" #include "sysemu/replay.h" @@ -1611,7 +1610,7 @@ static const GdbCmdParseEntry gdb_gen_query_table[] = { .cmd_startswith = 1, .schema = "s:l,l0" }, -#if defined(CONFIG_USER_ONLY) && defined(CONFIG_LINUX_USER) +#if defined(CONFIG_USER_ONLY) && defined(CONFIG_LINUX) { .handler = gdb_handle_query_xfer_auxv, .cmd = "Xfer:auxv:read::", diff --git a/gdbstub/user-target.c b/gdbstub/user-target.c index 83e04e1c23..46f5729999 100644 --- a/gdbstub/user-target.c +++ b/gdbstub/user-target.c @@ -235,7 +235,7 @@ static inline int target_memory_rw_debug(CPUState *cpu, target_ulong addr, } -#if defined(CONFIG_LINUX_USER) +#if defined(CONFIG_LINUX) void gdb_handle_query_xfer_auxv(GArray *params, void *user_ctx) { TaskState *ts; diff --git a/gdbstub/meson.build b/gdbstub/meson.build index 56c40c25ef..193c20203d 100644 --- a/gdbstub/meson.build +++ b/gdbstub/meson.build @@ -4,13 +4,37 @@ # types such as hwaddr. # -specific_ss.add(files('gdbstub.c')) +# We need to build the core gdb code via a library to be able to tweak +# cflags so: -# These have to built to the target ABI -specific_ss.add(files('syscalls.c')) +gdb_user_ss = ss.source_set() +gdb_softmmu_ss = ss.source_set() -softmmu_ss.add(files('softmmu.c')) +# We build two versions of gdbstub, one for each mode +gdb_user_ss.add(files('gdbstub.c')) +gdb_softmmu_ss.add(files('gdbstub.c')) + +gdb_user_ss = gdb_user_ss.apply(config_host, strict: false) +gdb_softmmu_ss = gdb_softmmu_ss.apply(config_host, strict: false) + +libgdb_user = static_library('gdb_user', gdb_user_ss.sources(), + name_suffix: 'fa', + c_args: '-DCONFIG_USER_ONLY') + +libgdb_softmmu = static_library('gdb_softmmu', gdb_softmmu_ss.sources(), + name_suffix: 'fa') + +gdb_user = declare_dependency(link_whole: libgdb_user) +user_ss.add(gdb_user) +gdb_softmmu = declare_dependency(link_whole: libgdb_softmmu) +softmmu_ss.add(gdb_softmmu) + +# The rest of the mode specific code can be added directly user_ss.add(files('user.c')) +softmmu_ss.add(files('softmmu.c')) + +# These have to built to the target ABI +specific_ss.add(files('syscalls.c')) # and BSD? specific_ss.add(when: 'CONFIG_LINUX_USER', if_true: files('user-target.c')) -- 2.34.1 From MAILER-DAEMON Thu Jan 05 11:44:01 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTLU-0007eG-Tu for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 11:44:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTLE-0007Bs-UQ for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:43:45 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTKy-0006wA-5x for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:43:44 -0500 Received: by mail-wm1-x336.google.com with SMTP id ay40so28484943wmb.2 for ; Thu, 05 Jan 2023 08:43:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tQSx+09nLzhSfINVlmlSsVlVWwh5VHah16/HRlU/6+s=; b=mZjwh923HJ3Yck8Q1EvJXmtWKTzqbJNYrjHfnFnQgw9sUdysbvZMXi+Jo3vsfJLF7R 5OL65eclnzT1hQYPVtegKq+w3bsygwnUbMDtKAZf2AMk/ScYaTzUu271+SLTBSnAi0RW 6+R/caZ/IPuwLU1czAc0pL4hMvofLWGepJb0h0I+tQJa2rwxUUpE4TEZ/79Fah0uV29R y2GnHwKXZI8cPfZ8x6PPY1Hj+wOLfhhPtW5Tz6VQ1XFieON92rZgnKhkL6ULEMnvpE5I xGsctN1NyXpUSikAiipV8dcbLH4aCtQgZtNBJLAdylF8eaZ+ul0SxF900uvARj5D+cD4 +j0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tQSx+09nLzhSfINVlmlSsVlVWwh5VHah16/HRlU/6+s=; b=Xyz+i7BfO5o7tdJZvYcpybtoEGQuL4zf71gjXcQSSUR5ZmExfhIZ2HFGJT+0fDneYW PkgNQk1VPwOwL6tAKMR/YUjULGET1SngY3q3HhljzMqJPkprS/z39pili7aXkOi5mFPQ Qa2pKyKlqeaxHKV5bNL1mMQAw9PmwTFnFJUHr5jRyl8LA9iq2qrpa37tIzwtlSVqji5z rzVRplByLTH8AeCrAMKO7PxuN9hGgGcMtU41JYCcjCseZqn9nxFrhuv/5cJDuFUt4pio Oy/wW/3c29o2pSSdx25suho33jp7muhqPrAa1AE2Uiqv2K4/9tOoSH3BKrRJiQ8tS9yR 7x2A== X-Gm-Message-State: AFqh2kqgjgy4xB1TAi9wjEcC/h7JKvoIyvB9Zfx2U1NiTe5hQj5xO5kX Zb8H5nfJ1eyyf5kfFAl+oYfYMA== X-Google-Smtp-Source: AMrXdXvQv1Cv5k2QqFBfEk47dZKvh2yvrlkXXuA2NzBk+EuZIIqZxX/4/4mGnegLCnQHXBAs82CvzQ== X-Received: by 2002:a05:600c:4a9b:b0:3d1:dc6f:b1a4 with SMTP id b27-20020a05600c4a9b00b003d1dc6fb1a4mr45015263wmp.5.1672937007331; Thu, 05 Jan 2023 08:43:27 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id m18-20020a05600c4f5200b003c71358a42dsm3993488wmq.18.2023.01.05.08.43.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:43:25 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 3F2B81FFC5; Thu, 5 Jan 2023 16:43:21 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH v2 13/21] gdbstub: specialise handle_query_attached Date: Thu, 5 Jan 2023 16:43:12 +0000 Message-Id: <20230105164320.2164095-14-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:43:47 -0000 In both user and softmmu cases we are just replying with a constant. If the linker is paying attention it may even be able to sort optimise the call. Signed-off-by: Alex Bennée --- gdbstub/internals.h | 4 +++- gdbstub/gdbstub.c | 15 ++------------- gdbstub/softmmu.c | 5 +++++ gdbstub/user.c | 5 +++++ 4 files changed, 15 insertions(+), 14 deletions(-) diff --git a/gdbstub/internals.h b/gdbstub/internals.h index 8d260e2481..646d2c4e82 100644 --- a/gdbstub/internals.h +++ b/gdbstub/internals.h @@ -150,7 +150,7 @@ int gdb_continue_partial(char *newstates); void gdb_put_buffer(const uint8_t *buf, int len); /* - * Command handlers - either softmmu or user only + * Command handlers - either specialised or softmmu or user only */ void gdb_init_gdbserver_state(void); @@ -179,6 +179,8 @@ void gdb_handle_query_rcmd(GArray *params, void *user_ctx); /* softmmu */ void gdb_handle_query_offsets(GArray *params, void *user_ctx); /* user */ void gdb_handle_query_xfer_auxv(GArray *params, void *user_ctx); /*user */ +void gdb_handle_query_attached(GArray *params, void *user_ctx); /* both */ + /* * Break/Watch point support - there is an implementation for softmmu * and user mode. diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 76c24b7cb6..0d90685c72 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -46,12 +46,6 @@ #include "internals.h" -#ifdef CONFIG_USER_ONLY -#define GDB_ATTACHED "0" -#else -#define GDB_ATTACHED "1" -#endif - #ifndef CONFIG_USER_ONLY static int phy_memory_mode; #endif @@ -1672,11 +1666,6 @@ static void handle_query_xfer_features(GArray *params, void *user_ctx) gdbserver_state.str_buf->len, true); } -static void handle_query_attached(GArray *params, void *user_ctx) -{ - gdb_put_packet(GDB_ATTACHED); -} - static void handle_query_qemu_supported(GArray *params, void *user_ctx) { g_string_printf(gdbserver_state.str_buf, "sstepbits;sstep"); @@ -1786,12 +1775,12 @@ static const GdbCmdParseEntry gdb_gen_query_table[] = { }, #endif { - .handler = handle_query_attached, + .handler = gdb_handle_query_attached, .cmd = "Attached:", .cmd_startswith = 1 }, { - .handler = handle_query_attached, + .handler = gdb_handle_query_attached, .cmd = "Attached", }, { diff --git a/gdbstub/softmmu.c b/gdbstub/softmmu.c index 534370081d..19fcb3be7d 100644 --- a/gdbstub/softmmu.c +++ b/gdbstub/softmmu.c @@ -442,6 +442,11 @@ void gdb_handle_query_rcmd(GArray *params, void *user_ctx) * Execution state helpers */ +void gdb_handle_query_attached(GArray *params, void *user_ctx) +{ + gdb_put_packet("1"); +} + void gdb_continue(void) { if (!runstate_needs_reset()) { diff --git a/gdbstub/user.c b/gdbstub/user.c index fa19ec5263..a668b16952 100644 --- a/gdbstub/user.c +++ b/gdbstub/user.c @@ -343,6 +343,11 @@ void gdbserver_fork(CPUState *cpu) * Execution state helpers */ +void gdb_handle_query_attached(GArray *params, void *user_ctx) +{ + gdb_put_packet("0"); +} + void gdb_continue(void) { gdbserver_user_state.running_state = 1; -- 2.34.1 From MAILER-DAEMON Thu Jan 05 11:52:02 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTTG-0006v3-OT for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 11:52:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTTF-0006u9-Mj for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:52:01 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTTB-00016l-FM for qemu-riscv@nongnu.org; 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Thu, 5 Jan 2023 16:43:21 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH v2 15/21] gdbstub: introduce gdb_get_max_cpus Date: Thu, 5 Jan 2023 16:43:14 +0000 Message-Id: <20230105164320.2164095-16-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:52:01 -0000 This is needed for handling vcont packets as the way of calculating max cpus vhanges between user and softmmu mode. Signed-off-by: Alex Bennée --- gdbstub/internals.h | 1 + gdbstub/gdbstub.c | 11 +---------- gdbstub/softmmu.c | 9 +++++++++ gdbstub/user.c | 17 +++++++++++++++++ 4 files changed, 28 insertions(+), 10 deletions(-) diff --git a/gdbstub/internals.h b/gdbstub/internals.h index 55f3d820aa..a371373c1d 100644 --- a/gdbstub/internals.h +++ b/gdbstub/internals.h @@ -125,6 +125,7 @@ bool gdb_got_immediate_ack(void); CPUState *gdb_first_attached_cpu(void); void gdb_append_thread_id(CPUState *cpu, GString *buf); int gdb_get_cpu_index(CPUState *cpu); +unsigned int gdb_get_max_cpus(void); /* both */ void gdb_create_default_process(GDBState *s); diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 91021859a1..f9950200b8 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -624,16 +624,7 @@ static int gdb_handle_vcont(const char *p) GDBProcess *process; CPUState *cpu; GDBThreadIdKind kind; -#ifdef CONFIG_USER_ONLY - int max_cpus = 1; /* global variable max_cpus exists only in system mode */ - - CPU_FOREACH(cpu) { - max_cpus = max_cpus <= cpu->cpu_index ? cpu->cpu_index + 1 : max_cpus; - } -#else - MachineState *ms = MACHINE(qdev_get_machine()); - unsigned int max_cpus = ms->smp.max_cpus; -#endif + unsigned int max_cpus = gdb_get_max_cpus(); /* uninitialised CPUs stay 0 */ newstates = g_new0(char, max_cpus); diff --git a/gdbstub/softmmu.c b/gdbstub/softmmu.c index c42230acca..015848358a 100644 --- a/gdbstub/softmmu.c +++ b/gdbstub/softmmu.c @@ -436,6 +436,15 @@ int gdb_target_memory_rw_debug(CPUState *cpu, hwaddr addr, return cpu_memory_rw_debug(cpu, addr, buf, len, is_write); } +/* + * cpu helpers + */ + +unsigned int gdb_get_max_cpus(void) +{ + MachineState *ms = MACHINE(qdev_get_machine()); + return ms->smp.max_cpus; +} /* * Softmmu specific command helpers diff --git a/gdbstub/user.c b/gdbstub/user.c index 74f541223c..9556a272d7 100644 --- a/gdbstub/user.c +++ b/gdbstub/user.c @@ -391,6 +391,23 @@ int gdb_target_memory_rw_debug(CPUState *cpu, hwaddr addr, return cpu_memory_rw_debug(cpu, addr, buf, len, is_write); } +/* + * cpu helpers + */ + +unsigned int gdb_get_max_cpus(void) +{ + CPUState *cpu; + unsigned int max_cpus = 1; /* global variable max_cpus exists only in system mode */ + + CPU_FOREACH(cpu) { + max_cpus = max_cpus <= cpu->cpu_index ? cpu->cpu_index + 1 : max_cpus; + } + + return max_cpus; +} + + /* * Break/Watch point helpers */ -- 2.34.1 From MAILER-DAEMON Thu Jan 05 11:52:04 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTTI-0006xO-3n for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 11:52:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTTG-0006vM-Qp for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:52:02 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTTB-00016d-Ip for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:52:02 -0500 Received: by mail-wm1-x333.google.com with SMTP id g10so14675453wmo.1 for ; Thu, 05 Jan 2023 08:51:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NDdf4UWRF61GNUgMwfJ+g0rGybMbaOrqfqaFUxYF2gk=; b=rFW1A6DzD0C2iDWkmMmUhLMtRYqR1ISIGld6Zj/Q4GjylCE7dlHtAObh1RYHRWORS6 MEbGC93jbgrlyPhp5OP9VDgSwz/RNlxv94lLEvSW8XlOY71gbhalA8vMSXsVAiUEbcKK Pn3hH3VYuLKK90XHMSlW9GnPXJB/nFMfcCJ+0jz7sJqvLZeNuDr5x2i2knhtrfuCIVgw 2jyAmVi8J0wYfa901EXtTZpVHWN7RWekRbJili0vR3FB7dqWA0HKXELcZFTzUQcQ3kYk E+VYuW8eJ4dMDOrqxUDbp45Dow9OAX3HwGbDMWVjluyxo808LLlcddMP+KIOMSNvpEuf hMwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NDdf4UWRF61GNUgMwfJ+g0rGybMbaOrqfqaFUxYF2gk=; b=uyIjS6RAX94jx5Ikb8Z/f1AN8HWt+GNB+BOnsDS/c1MRxcCMggeBuVcqV4OGEFYOra dANv11qUQIfX2Zm4hGUQtDCuROs4crKz1e8pd/XWJjdLqcbSEuB4J/Z+ZcJLgtgc31ZD RoV/pS0zlYoEoc24FsEm17Ru/q0O+bzc/XXwwMC2KWYhy/vMABtR1eJtF1Ha9vWFGv9S X4t5mPuxeM6rpbuUuWkKp8OYTRbkdttZWwzuElkALd29ZphQ99OoFQjrpOc1wRzLZG4Z 4hSss+TM+i8kHwkdeMwXsOoFksFLMFvLiLczdrsg+7Mz/xkAvomygriuEyK6S2n8+G1F WMQw== X-Gm-Message-State: AFqh2kr8Jdu4s5vwXRAIAeZLOPmWP+Q3h7N0q7fjjXmDMXJHS/wOshTu dLMtV2r5UhZPxHyu7LbiWDqQsg== X-Google-Smtp-Source: AMrXdXutHexv6rwTXhO7FXr15GZy3LuDOHRtRk2AUNSvvYEeGLw0u81qVl4A/7j+p3BQmDhVulvO9A== X-Received: by 2002:a05:600c:4995:b0:3d3:4f43:fbc2 with SMTP id h21-20020a05600c499500b003d34f43fbc2mr37347589wmp.41.1672937515856; Thu, 05 Jan 2023 08:51:55 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id j1-20020a05600c1c0100b003cfaae07f68sm3447341wms.17.2023.01.05.08.51.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:51:55 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 6CF4E1FFC7; Thu, 5 Jan 2023 16:43:21 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH v2 16/21] gdbstub: specialise stub_can_reverse Date: Thu, 5 Jan 2023 16:43:15 +0000 Message-Id: <20230105164320.2164095-17-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:52:03 -0000 Currently we only support replay for softmmu mode so it is a constant false for user-mode. Signed-off-by: Alex Bennée --- gdbstub/internals.h | 1 + gdbstub/gdbstub.c | 13 ++----------- gdbstub/softmmu.c | 5 +++++ gdbstub/user.c | 5 +++++ 4 files changed, 13 insertions(+), 11 deletions(-) diff --git a/gdbstub/internals.h b/gdbstub/internals.h index a371373c1d..1def9dfc9c 100644 --- a/gdbstub/internals.h +++ b/gdbstub/internals.h @@ -126,6 +126,7 @@ CPUState *gdb_first_attached_cpu(void); void gdb_append_thread_id(CPUState *cpu, GString *buf); int gdb_get_cpu_index(CPUState *cpu); unsigned int gdb_get_max_cpus(void); /* both */ +bool gdb_stub_can_reverse(void); /* softmmu, stub for user */ void gdb_create_default_process(GDBState *s); diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index f9950200b8..c293b8e43c 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -113,15 +113,6 @@ int use_gdb_syscalls(void) return gdb_syscall_mode == GDB_SYS_ENABLED; } -static bool stub_can_reverse(void) -{ -#ifdef CONFIG_USER_ONLY - return false; -#else - return replay_mode == REPLAY_MODE_PLAY; -#endif -} - /* writes 2*len+1 bytes in buf */ void gdb_memtohex(GString *buf, const uint8_t *mem, int len) { @@ -1307,7 +1298,7 @@ static void handle_step(GArray *params, void *user_ctx) static void handle_backward(GArray *params, void *user_ctx) { - if (!stub_can_reverse()) { + if (!gdb_stub_can_reverse()) { gdb_put_packet("E22"); } if (params->len == 1) { @@ -1558,7 +1549,7 @@ static void handle_query_supported(GArray *params, void *user_ctx) g_string_append(gdbserver_state.str_buf, ";qXfer:features:read+"); } - if (stub_can_reverse()) { + if (gdb_stub_can_reverse()) { g_string_append(gdbserver_state.str_buf, ";ReverseStep+;ReverseContinue+"); } diff --git a/gdbstub/softmmu.c b/gdbstub/softmmu.c index 015848358a..ff18611ce7 100644 --- a/gdbstub/softmmu.c +++ b/gdbstub/softmmu.c @@ -446,6 +446,11 @@ unsigned int gdb_get_max_cpus(void) return ms->smp.max_cpus; } +bool gdb_stub_can_reverse(void) +{ + return replay_mode == REPLAY_MODE_PLAY; +} + /* * Softmmu specific command helpers */ diff --git a/gdbstub/user.c b/gdbstub/user.c index 9556a272d7..ccc73683de 100644 --- a/gdbstub/user.c +++ b/gdbstub/user.c @@ -407,6 +407,11 @@ unsigned int gdb_get_max_cpus(void) return max_cpus; } +/* replay not supported for user-mode */ +bool gdb_stub_can_reverse(void) +{ + return false; +} /* * Break/Watch point helpers -- 2.34.1 From MAILER-DAEMON Thu Jan 05 11:52:06 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTTJ-00072p-Rh for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 11:52:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTTI-0006yK-B0 for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:52:04 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTTC-00017C-CS for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 11:52:04 -0500 Received: by mail-wr1-x429.google.com with SMTP id z16so20238717wrw.1 for ; Thu, 05 Jan 2023 08:51:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; 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Thu, 05 Jan 2023 08:51:56 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id f1-20020a5d5681000000b002714b3d2348sm37438617wrv.25.2023.01.05.08.51.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:51:55 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 8B51E1FFC9; Thu, 5 Jan 2023 16:43:21 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH v2 18/21] gdbstub: don't use target_ulong while handling registers Date: Thu, 5 Jan 2023 16:43:17 +0000 Message-Id: <20230105164320.2164095-19-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:52:04 -0000 This is a hangover from the original code. addr is misleading as it is only a really a register id. While len will never exceed MAX_PACKET_LENGTH I've used size_t as that is what strlen returns. Signed-off-by: Alex Bennée --- gdbstub/gdbstub.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index 4547ca3367..c50c2f8e0f 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -1192,7 +1192,8 @@ static void handle_read_mem(GArray *params, void *user_ctx) static void handle_write_all_regs(GArray *params, void *user_ctx) { - target_ulong addr, len; + int reg_id; + size_t len; uint8_t *registers; int reg_size; @@ -1204,9 +1205,10 @@ static void handle_write_all_regs(GArray *params, void *user_ctx) len = strlen(get_param(params, 0)->data) / 2; gdb_hextomem(gdbserver_state.mem_buf, get_param(params, 0)->data, len); registers = gdbserver_state.mem_buf->data; - for (addr = 0; addr < gdbserver_state.g_cpu->gdb_num_g_regs && len > 0; - addr++) { - reg_size = gdb_write_register(gdbserver_state.g_cpu, registers, addr); + for (reg_id = 0; + reg_id < gdbserver_state.g_cpu->gdb_num_g_regs && len > 0; + reg_id++) { + reg_size = gdb_write_register(gdbserver_state.g_cpu, registers, reg_id); len -= reg_size; registers += reg_size; } @@ -1215,15 +1217,16 @@ static void handle_write_all_regs(GArray *params, void *user_ctx) static void handle_read_all_regs(GArray *params, void *user_ctx) { - target_ulong addr, len; + int reg_id; + size_t len; cpu_synchronize_state(gdbserver_state.g_cpu); g_byte_array_set_size(gdbserver_state.mem_buf, 0); len = 0; - for (addr = 0; addr < gdbserver_state.g_cpu->gdb_num_g_regs; addr++) { + for (reg_id = 0; reg_id < gdbserver_state.g_cpu->gdb_num_g_regs; reg_id++) { len += gdb_read_register(gdbserver_state.g_cpu, gdbserver_state.mem_buf, - addr); + reg_id); } g_assert(len == gdbserver_state.mem_buf->len); -- 2.34.1 From MAILER-DAEMON Thu Jan 05 11:52:09 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTTN-00075t-NA for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 11:52:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTTL-00074I-8E for qemu-riscv@nongnu.org; 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Thu, 05 Jan 2023 08:51:55 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 9A3CC1FFCA; Thu, 5 Jan 2023 16:43:21 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH v2 19/21] gdbstub: move register helpers into standalone include Date: Thu, 5 Jan 2023 16:43:18 +0000 Message-Id: <20230105164320.2164095-20-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:52:07 -0000 These inline helpers are all used by target specific code so move them out of the general header so we don't needlessly pollute the rest of the API with target specific stuff. Note we have to include cpu.h in semihosting as it was relying on a side effect before. Signed-off-by: Alex Bennée --- include/exec/gdbstub.h | 86 --------------------- include/gdbstub/helpers.h | 103 +++++++++++++++++++++++++ semihosting/syscalls.c | 1 + target/alpha/gdbstub.c | 2 +- target/arm/gdbstub.c | 1 + target/arm/gdbstub64.c | 2 +- target/arm/helper-a64.c | 2 +- target/arm/m_helper.c | 2 +- target/avr/gdbstub.c | 2 +- target/cris/gdbstub.c | 2 +- target/hexagon/gdbstub.c | 2 +- target/hppa/gdbstub.c | 2 +- target/i386/gdbstub.c | 2 +- target/i386/whpx/whpx-all.c | 2 +- target/loongarch/gdbstub.c | 1 + target/m68k/gdbstub.c | 2 +- target/m68k/helper.c | 1 + target/m68k/m68k-semi.c | 1 + target/microblaze/gdbstub.c | 2 +- target/mips/gdbstub.c | 2 +- target/mips/tcg/sysemu/mips-semi.c | 1 + target/nios2/cpu.c | 2 +- target/nios2/nios2-semi.c | 1 + target/openrisc/gdbstub.c | 2 +- target/openrisc/interrupt.c | 2 +- target/openrisc/mmu.c | 2 +- target/ppc/cpu_init.c | 2 +- target/ppc/gdbstub.c | 1 + target/riscv/gdbstub.c | 1 + target/rx/gdbstub.c | 2 +- target/s390x/gdbstub.c | 1 + target/s390x/helper.c | 2 +- target/sh4/gdbstub.c | 2 +- target/sparc/gdbstub.c | 2 +- target/tricore/gdbstub.c | 2 +- target/xtensa/core-dc232b.c | 2 +- target/xtensa/core-dc233c.c | 2 +- target/xtensa/core-de212.c | 2 +- target/xtensa/core-de233_fpu.c | 2 +- target/xtensa/core-dsp3400.c | 2 +- target/xtensa/core-fsf.c | 2 +- target/xtensa/core-lx106.c | 2 +- target/xtensa/core-sample_controller.c | 2 +- target/xtensa/core-test_kc705_be.c | 2 +- target/xtensa/core-test_mmuhifi_c3.c | 2 +- target/xtensa/gdbstub.c | 2 +- target/xtensa/helper.c | 2 +- 47 files changed, 148 insertions(+), 121 deletions(-) create mode 100644 include/gdbstub/helpers.h diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index 8fff5450ed..bb8a3928dd 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -110,92 +110,6 @@ void gdb_register_coprocessor(CPUState *cpu, gdb_get_reg_cb get_reg, gdb_set_reg_cb set_reg, int num_regs, const char *xml, int g_pos); -#ifdef NEED_CPU_H -#include "cpu.h" - -/* - * The GDB remote protocol transfers values in target byte order. As - * the gdbstub may be batching up several register values we always - * append to the array. - */ - -static inline int gdb_get_reg8(GByteArray *buf, uint8_t val) -{ - g_byte_array_append(buf, &val, 1); - return 1; -} - -static inline int gdb_get_reg16(GByteArray *buf, uint16_t val) -{ - uint16_t to_word = tswap16(val); - g_byte_array_append(buf, (uint8_t *) &to_word, 2); - return 2; -} - -static inline int gdb_get_reg32(GByteArray *buf, uint32_t val) -{ - uint32_t to_long = tswap32(val); - g_byte_array_append(buf, (uint8_t *) &to_long, 4); - return 4; -} - -static inline int gdb_get_reg64(GByteArray *buf, uint64_t val) -{ - uint64_t to_quad = tswap64(val); - g_byte_array_append(buf, (uint8_t *) &to_quad, 8); - return 8; -} - -static inline int gdb_get_reg128(GByteArray *buf, uint64_t val_hi, - uint64_t val_lo) -{ - uint64_t to_quad; -#if TARGET_BIG_ENDIAN - to_quad = tswap64(val_hi); - g_byte_array_append(buf, (uint8_t *) &to_quad, 8); - to_quad = tswap64(val_lo); - g_byte_array_append(buf, (uint8_t *) &to_quad, 8); -#else - to_quad = tswap64(val_lo); - g_byte_array_append(buf, (uint8_t *) &to_quad, 8); - to_quad = tswap64(val_hi); - g_byte_array_append(buf, (uint8_t *) &to_quad, 8); -#endif - return 16; -} - -static inline int gdb_get_zeroes(GByteArray *array, size_t len) -{ - guint oldlen = array->len; - g_byte_array_set_size(array, oldlen + len); - memset(array->data + oldlen, 0, len); - - return len; -} - -/** - * gdb_get_reg_ptr: get pointer to start of last element - * @len: length of element - * - * This is a helper function to extract the pointer to the last - * element for additional processing. Some front-ends do additional - * dynamic swapping of the elements based on CPU state. - */ -static inline uint8_t * gdb_get_reg_ptr(GByteArray *buf, int len) -{ - return buf->data + buf->len - len; -} - -#if TARGET_LONG_BITS == 64 -#define gdb_get_regl(buf, val) gdb_get_reg64(buf, val) -#define ldtul_p(addr) ldq_p(addr) -#else -#define gdb_get_regl(buf, val) gdb_get_reg32(buf, val) -#define ldtul_p(addr) ldl_p(addr) -#endif - -#endif /* NEED_CPU_H */ - /** * gdbserver_start: start the gdb server * @port_or_device: connection spec for gdb diff --git a/include/gdbstub/helpers.h b/include/gdbstub/helpers.h new file mode 100644 index 0000000000..dfaef2b9dd --- /dev/null +++ b/include/gdbstub/helpers.h @@ -0,0 +1,103 @@ +/* + * gdbstub helpers + * + * These are all used by the various frontends and have to be host + * aware to ensure things are store in target order. + * + * Copyright (c) 2022 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef _GDBSTUB_HELPERS_H_ +#define _GDBSTUB_HELPERS_H_ + +#ifdef NEED_CPU_H +#include "cpu.h" + +/* + * The GDB remote protocol transfers values in target byte order. As + * the gdbstub may be batching up several register values we always + * append to the array. + */ + +static inline int gdb_get_reg8(GByteArray *buf, uint8_t val) +{ + g_byte_array_append(buf, &val, 1); + return 1; +} + +static inline int gdb_get_reg16(GByteArray *buf, uint16_t val) +{ + uint16_t to_word = tswap16(val); + g_byte_array_append(buf, (uint8_t *) &to_word, 2); + return 2; +} + +static inline int gdb_get_reg32(GByteArray *buf, uint32_t val) +{ + uint32_t to_long = tswap32(val); + g_byte_array_append(buf, (uint8_t *) &to_long, 4); + return 4; +} + +static inline int gdb_get_reg64(GByteArray *buf, uint64_t val) +{ + uint64_t to_quad = tswap64(val); + g_byte_array_append(buf, (uint8_t *) &to_quad, 8); + return 8; +} + +static inline int gdb_get_reg128(GByteArray *buf, uint64_t val_hi, + uint64_t val_lo) +{ + uint64_t to_quad; +#if TARGET_BIG_ENDIAN + to_quad = tswap64(val_hi); + g_byte_array_append(buf, (uint8_t *) &to_quad, 8); + to_quad = tswap64(val_lo); + g_byte_array_append(buf, (uint8_t *) &to_quad, 8); +#else + to_quad = tswap64(val_lo); + g_byte_array_append(buf, (uint8_t *) &to_quad, 8); + to_quad = tswap64(val_hi); + g_byte_array_append(buf, (uint8_t *) &to_quad, 8); +#endif + return 16; +} + +static inline int gdb_get_zeroes(GByteArray *array, size_t len) +{ + guint oldlen = array->len; + g_byte_array_set_size(array, oldlen + len); + memset(array->data + oldlen, 0, len); + + return len; +} + +/** + * gdb_get_reg_ptr: get pointer to start of last element + * @len: length of element + * + * This is a helper function to extract the pointer to the last + * element for additional processing. Some front-ends do additional + * dynamic swapping of the elements based on CPU state. + */ +static inline uint8_t * gdb_get_reg_ptr(GByteArray *buf, int len) +{ + return buf->data + buf->len - len; +} + +#if TARGET_LONG_BITS == 64 +#define gdb_get_regl(buf, val) gdb_get_reg64(buf, val) +#define ldtul_p(addr) ldq_p(addr) +#else +#define gdb_get_regl(buf, val) gdb_get_reg32(buf, val) +#define ldtul_p(addr) ldl_p(addr) +#endif + +#else +#error "gdbstub helpers should only be included by target specific code" +#endif + +#endif /* _GDBSTUB_HELPERS_H_ */ diff --git a/semihosting/syscalls.c b/semihosting/syscalls.c index 508a0ad88c..e20241b6b4 100644 --- a/semihosting/syscalls.c +++ b/semihosting/syscalls.c @@ -8,6 +8,7 @@ #include "qemu/osdep.h" #include "exec/gdbstub.h" +#include "cpu.h" #include "semihosting/guestfd.h" #include "semihosting/syscalls.h" #include "semihosting/console.h" diff --git a/target/alpha/gdbstub.c b/target/alpha/gdbstub.c index 7db14f4431..0f8fa150f8 100644 --- a/target/alpha/gdbstub.c +++ b/target/alpha/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" int alpha_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 2f806512d0..05d6eb802a 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "internals.h" #include "cpregs.h" diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 07a6746944..48d2888b6f 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -20,7 +20,7 @@ #include "qemu/log.h" #include "cpu.h" #include "internals.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 77a8502b6b..b52d381043 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "qemu/log.h" diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 355cd4d60a..53f1b38ec4 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -12,7 +12,7 @@ #include "trace.h" #include "cpu.h" #include "internals.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "qemu/main-loop.h" diff --git a/target/avr/gdbstub.c b/target/avr/gdbstub.c index 1c1b908c92..150344d8b9 100644 --- a/target/avr/gdbstub.c +++ b/target/avr/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" int avr_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/cris/gdbstub.c b/target/cris/gdbstub.c index 2418d575b1..25c0ca33a5 100644 --- a/target/cris/gdbstub.c +++ b/target/cris/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" int crisv10_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c index d152d01bfe..46083da620 100644 --- a/target/hexagon/gdbstub.c +++ b/target/hexagon/gdbstub.c @@ -16,7 +16,7 @@ */ #include "qemu/osdep.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "cpu.h" #include "internal.h" diff --git a/target/hppa/gdbstub.c b/target/hppa/gdbstub.c index 729c37b2ca..48a514384f 100644 --- a/target/hppa/gdbstub.c +++ b/target/hppa/gdbstub.c @@ -19,7 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" int hppa_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/i386/gdbstub.c b/target/i386/gdbstub.c index c3a2cf6f28..255faa70f6 100644 --- a/target/i386/gdbstub.c +++ b/target/i386/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "include/gdbstub/helpers.h" #ifdef TARGET_X86_64 static const int gpr_map[16] = { diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index e738d83e81..430da38778 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -12,7 +12,7 @@ #include "cpu.h" #include "exec/address-spaces.h" #include "exec/ioport.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/accel.h" #include "sysemu/whpx.h" #include "sysemu/cpus.h" diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c index a4d1e28e36..fa3e034d15 100644 --- a/target/loongarch/gdbstub.c +++ b/target/loongarch/gdbstub.c @@ -10,6 +10,7 @@ #include "cpu.h" #include "internals.h" #include "exec/gdbstub.h" +#include "gdbstub/helpers.h" uint64_t read_fcc(CPULoongArchState *env) { diff --git a/target/m68k/gdbstub.c b/target/m68k/gdbstub.c index eb2d030e14..1e5f033a12 100644 --- a/target/m68k/gdbstub.c +++ b/target/m68k/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" int m68k_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/m68k/helper.c b/target/m68k/helper.c index 4621cf2402..3b3a6ea8bd 100644 --- a/target/m68k/helper.c +++ b/target/m68k/helper.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "exec/gdbstub.h" #include "exec/helper-proto.h" +#include "gdbstub/helpers.h" #include "fpu/softfloat.h" #include "qemu/qemu-print.h" diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c index 87b1314925..f753710d7d 100644 --- a/target/m68k/m68k-semi.c +++ b/target/m68k/m68k-semi.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "semihosting/syscalls.h" #include "semihosting/softmmu-uaccess.h" #include "hw/boards.h" diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index 2e6e070051..ad2e0b27cb 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" /* * GDB expects SREGs in the following order: diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index f1c2a2cf6d..62d7b72407 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internal.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "fpu_helper.h" int mips_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) diff --git a/target/mips/tcg/sysemu/mips-semi.c b/target/mips/tcg/sysemu/mips-semi.c index 85f0567a7f..4e6e759057 100644 --- a/target/mips/tcg/sysemu/mips-semi.c +++ b/target/mips/tcg/sysemu/mips-semi.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "qemu/log.h" #include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "semihosting/softmmu-uaccess.h" #include "semihosting/semihost.h" #include "semihosting/console.h" diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index cff30823da..bc5cbf81c2 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -23,7 +23,7 @@ #include "qapi/error.h" #include "cpu.h" #include "exec/log.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "hw/qdev-properties.h" static void nios2_cpu_set_pc(CPUState *cs, vaddr value) diff --git a/target/nios2/nios2-semi.c b/target/nios2/nios2-semi.c index f76e8588c5..113b3f22aa 100644 --- a/target/nios2/nios2-semi.c +++ b/target/nios2/nios2-semi.c @@ -24,6 +24,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "semihosting/syscalls.h" #include "semihosting/softmmu-uaccess.h" #include "qemu/log.h" diff --git a/target/openrisc/gdbstub.c b/target/openrisc/gdbstub.c index 095bf76c12..d1074a0581 100644 --- a/target/openrisc/gdbstub.c +++ b/target/openrisc/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" int openrisc_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c index c31c6f12c4..3887812810 100644 --- a/target/openrisc/interrupt.c +++ b/target/openrisc/interrupt.c @@ -21,7 +21,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #ifndef CONFIG_USER_ONLY #include "hw/loader.h" diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c index 0b8afdbacf..603c26715e 100644 --- a/target/openrisc/mmu.c +++ b/target/openrisc/mmu.c @@ -22,7 +22,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "hw/loader.h" diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index abee71d407..78c5c48b04 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "disas/dis-asm.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "kvm_ppc.h" #include "sysemu/cpus.h" #include "sysemu/hw_accel.h" diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index 1a0b9ca82c..d2bc1d7c53 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "internal.h" static int ppc_gdb_register_len_apple(int n) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 6e7bbdbd5e..a542683901 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -18,6 +18,7 @@ #include "qemu/osdep.h" #include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "cpu.h" struct TypeSize { diff --git a/target/rx/gdbstub.c b/target/rx/gdbstub.c index 7eb2059a84..d7e0e6689b 100644 --- a/target/rx/gdbstub.c +++ b/target/rx/gdbstub.c @@ -17,7 +17,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" int rx_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) { diff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c index a5d69d0e0b..0cb69395b4 100644 --- a/target/s390x/gdbstub.c +++ b/target/s390x/gdbstub.c @@ -23,6 +23,7 @@ #include "s390x-internal.h" #include "exec/exec-all.h" #include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/bitops.h" #include "sysemu/hw_accel.h" #include "sysemu/tcg.h" diff --git a/target/s390x/helper.c b/target/s390x/helper.c index 473c8e51b0..2b363aa959 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -21,7 +21,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "s390x-internal.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/timer.h" #include "hw/s390x/ioinst.h" #include "hw/s390x/pv.h" diff --git a/target/sh4/gdbstub.c b/target/sh4/gdbstub.c index 3488f68e32..d8e199fc06 100644 --- a/target/sh4/gdbstub.c +++ b/target/sh4/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" /* Hint: Use "set architecture sh4" in GDB to see fpu registers */ /* FIXME: We should use XML for this. */ diff --git a/target/sparc/gdbstub.c b/target/sparc/gdbstub.c index 5d1e808e8c..a1c8fdc4d5 100644 --- a/target/sparc/gdbstub.c +++ b/target/sparc/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #ifdef TARGET_ABI32 #define gdb_get_rega(buf, val) gdb_get_reg32(buf, val) diff --git a/target/tricore/gdbstub.c b/target/tricore/gdbstub.c index 3a27a7e65d..e8f8e5e6ea 100644 --- a/target/tricore/gdbstub.c +++ b/target/tricore/gdbstub.c @@ -18,7 +18,7 @@ */ #include "qemu/osdep.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #define LCX_REGNUM 32 diff --git a/target/xtensa/core-dc232b.c b/target/xtensa/core-dc232b.c index c982d09c24..9aba2667e3 100644 --- a/target/xtensa/core-dc232b.c +++ b/target/xtensa/core-dc232b.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "qemu/timer.h" diff --git a/target/xtensa/core-dc233c.c b/target/xtensa/core-dc233c.c index 595ab9a90f..9b0a625063 100644 --- a/target/xtensa/core-dc233c.c +++ b/target/xtensa/core-dc233c.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "core-dc233c/core-isa.h" diff --git a/target/xtensa/core-de212.c b/target/xtensa/core-de212.c index 50c995ba79..b08fe22e65 100644 --- a/target/xtensa/core-de212.c +++ b/target/xtensa/core-de212.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "core-de212/core-isa.h" diff --git a/target/xtensa/core-de233_fpu.c b/target/xtensa/core-de233_fpu.c index 41af8057fb..8845cdb592 100644 --- a/target/xtensa/core-de233_fpu.c +++ b/target/xtensa/core-de233_fpu.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "core-de233_fpu/core-isa.h" diff --git a/target/xtensa/core-dsp3400.c b/target/xtensa/core-dsp3400.c index 81e425c568..c0f94b9e27 100644 --- a/target/xtensa/core-dsp3400.c +++ b/target/xtensa/core-dsp3400.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "core-dsp3400/core-isa.h" diff --git a/target/xtensa/core-fsf.c b/target/xtensa/core-fsf.c index 3327c50b4f..310be8d61f 100644 --- a/target/xtensa/core-fsf.c +++ b/target/xtensa/core-fsf.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "core-fsf/core-isa.h" diff --git a/target/xtensa/core-lx106.c b/target/xtensa/core-lx106.c index 7a771d09a6..7f71d088f3 100644 --- a/target/xtensa/core-lx106.c +++ b/target/xtensa/core-lx106.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "core-lx106/core-isa.h" diff --git a/target/xtensa/core-sample_controller.c b/target/xtensa/core-sample_controller.c index fd5de5576b..8867001aac 100644 --- a/target/xtensa/core-sample_controller.c +++ b/target/xtensa/core-sample_controller.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "core-sample_controller/core-isa.h" diff --git a/target/xtensa/core-test_kc705_be.c b/target/xtensa/core-test_kc705_be.c index 294c16f2f4..bd082f49aa 100644 --- a/target/xtensa/core-test_kc705_be.c +++ b/target/xtensa/core-test_kc705_be.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "core-test_kc705_be/core-isa.h" diff --git a/target/xtensa/core-test_mmuhifi_c3.c b/target/xtensa/core-test_mmuhifi_c3.c index c0e5d32d1e..3090dd01ed 100644 --- a/target/xtensa/core-test_mmuhifi_c3.c +++ b/target/xtensa/core-test_mmuhifi_c3.c @@ -27,7 +27,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/host-utils.h" #include "core-test_mmuhifi_c3/core-isa.h" diff --git a/target/xtensa/gdbstub.c b/target/xtensa/gdbstub.c index b6696063e5..4b3bfb7e59 100644 --- a/target/xtensa/gdbstub.c +++ b/target/xtensa/gdbstub.c @@ -19,7 +19,7 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "qemu/log.h" enum { diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 2aa9777a8e..dbeb97a953 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -29,7 +29,7 @@ #include "qemu/log.h" #include "cpu.h" #include "exec/exec-all.h" -#include "exec/gdbstub.h" +#include "gdbstub/helpers.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" -- 2.34.1 From MAILER-DAEMON Thu Jan 05 11:52:11 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTTP-00077N-79 for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 11:52:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTTN-00075p-IK for qemu-riscv@nongnu.org; Thu, 05 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id fj7-20020a05600c0c8700b003d973fb8aaamr27287401wmb.8.1672937517431; Thu, 05 Jan 2023 08:51:57 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id o11-20020a05600c4fcb00b003c6f3f6675bsm3358368wmq.26.2023.01.05.08.51.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jan 2023 08:51:55 -0800 (PST) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A93AC1FFB7; Thu, 5 Jan 2023 16:43:21 +0000 (GMT) From: =?UTF-8?q?Alex=20Benn=C3=A9e?= To: qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH v2 20/21] gdbstub: move syscall handling to new file Date: Thu, 5 Jan 2023 16:43:19 +0000 Message-Id: <20230105164320.2164095-21-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230105164320.2164095-1-alex.bennee@linaro.org> References: <20230105164320.2164095-1-alex.bennee@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 16:52:09 -0000 Our GDB syscall support is the last chunk of code that needs target specific support so move it to a new file. We take the opportunity to move the syscall state into its own singleton instance and add in a few helpers for the main gdbstub to interact with the module. I also moved the gdb_exit() declaration into syscalls.h as it feels pretty related and most of the callers of it treat it as such. Signed-off-by: Alex Bennée --- gdbstub/internals.h | 8 +- include/exec/gdbstub.h | 102 ------------- include/gdbstub/syscalls.h | 124 ++++++++++++++++ gdbstub/gdbstub.c | 177 +--------------------- gdbstub/softmmu.c | 7 +- gdbstub/syscalls.c | 230 +++++++++++++++++++++++++++++ gdbstub/user.c | 1 + linux-user/exit.c | 2 +- semihosting/arm-compat-semi.c | 1 + semihosting/guestfd.c | 2 +- semihosting/syscalls.c | 2 +- softmmu/runstate.c | 2 +- target/m68k/m68k-semi.c | 2 +- target/mips/tcg/sysemu/mips-semi.c | 2 +- target/nios2/nios2-semi.c | 2 +- gdbstub/meson.build | 4 + 16 files changed, 380 insertions(+), 288 deletions(-) create mode 100644 include/gdbstub/syscalls.h create mode 100644 gdbstub/syscalls.c diff --git a/gdbstub/internals.h b/gdbstub/internals.h index 1def9dfc9c..6404e0a15d 100644 --- a/gdbstub/internals.h +++ b/gdbstub/internals.h @@ -59,8 +59,6 @@ typedef struct GDBState { bool multiprocess; GDBProcess *processes; int process_num; - char syscall_buf[256]; - gdb_syscall_complete_cb current_syscall_cb; GString *str_buf; GByteArray *mem_buf; int sstep_flags; @@ -187,6 +185,12 @@ void gdb_handle_query_attached(GArray *params, void *user_ctx); /* both */ void gdb_handle_query_qemu_phy_mem_mode(GArray *params, void *user_ctx); void gdb_handle_set_qemu_phy_mem_mode(GArray *params, void *user_ctx); +/* sycall handling */ +void gdb_handle_file_io(GArray *params, void *user_ctx); +bool gdb_handled_syscall(void); +void gdb_disable_syscalls(void); +void gdb_syscall_reset(void); + /* * Break/Watch point support - there is an implementation for softmmu * and user mode. diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index bb8a3928dd..7d743fe1e9 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -10,98 +10,6 @@ #define GDB_WATCHPOINT_READ 3 #define GDB_WATCHPOINT_ACCESS 4 -/* For gdb file i/o remote protocol open flags. */ -#define GDB_O_RDONLY 0 -#define GDB_O_WRONLY 1 -#define GDB_O_RDWR 2 -#define GDB_O_APPEND 8 -#define GDB_O_CREAT 0x200 -#define GDB_O_TRUNC 0x400 -#define GDB_O_EXCL 0x800 - -/* For gdb file i/o remote protocol errno values */ -#define GDB_EPERM 1 -#define GDB_ENOENT 2 -#define GDB_EINTR 4 -#define GDB_EBADF 9 -#define GDB_EACCES 13 -#define GDB_EFAULT 14 -#define GDB_EBUSY 16 -#define GDB_EEXIST 17 -#define GDB_ENODEV 19 -#define GDB_ENOTDIR 20 -#define GDB_EISDIR 21 -#define GDB_EINVAL 22 -#define GDB_ENFILE 23 -#define GDB_EMFILE 24 -#define GDB_EFBIG 27 -#define GDB_ENOSPC 28 -#define GDB_ESPIPE 29 -#define GDB_EROFS 30 -#define GDB_ENAMETOOLONG 91 -#define GDB_EUNKNOWN 9999 - -/* For gdb file i/o remote protocol lseek whence. */ -#define GDB_SEEK_SET 0 -#define GDB_SEEK_CUR 1 -#define GDB_SEEK_END 2 - -/* For gdb file i/o stat/fstat. */ -typedef uint32_t gdb_mode_t; -typedef uint32_t gdb_time_t; - -struct gdb_stat { - uint32_t gdb_st_dev; /* device */ - uint32_t gdb_st_ino; /* inode */ - gdb_mode_t gdb_st_mode; /* protection */ - uint32_t gdb_st_nlink; /* number of hard links */ - uint32_t gdb_st_uid; /* user ID of owner */ - uint32_t gdb_st_gid; /* group ID of owner */ - uint32_t gdb_st_rdev; /* device type (if inode device) */ - uint64_t gdb_st_size; /* total size, in bytes */ - uint64_t gdb_st_blksize; /* blocksize for filesystem I/O */ - uint64_t gdb_st_blocks; /* number of blocks allocated */ - gdb_time_t gdb_st_atime; /* time of last access */ - gdb_time_t gdb_st_mtime; /* time of last modification */ - gdb_time_t gdb_st_ctime; /* time of last change */ -} QEMU_PACKED; - -struct gdb_timeval { - gdb_time_t tv_sec; /* second */ - uint64_t tv_usec; /* microsecond */ -} QEMU_PACKED; - -typedef void (*gdb_syscall_complete_cb)(CPUState *cpu, uint64_t ret, int err); - -/** - * gdb_do_syscall: - * @cb: function to call when the system call has completed - * @fmt: gdb syscall format string - * ...: list of arguments to interpolate into @fmt - * - * Send a GDB syscall request. This function will return immediately; - * the callback function will be called later when the remote system - * call has completed. - * - * @fmt should be in the 'call-id,parameter,parameter...' format documented - * for the F request packet in the GDB remote protocol. A limited set of - * printf-style format specifiers is supported: - * %x - target_ulong argument printed in hex - * %lx - 64-bit argument printed in hex - * %s - string pointer (target_ulong) and length (int) pair - */ -void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...); -/** - * gdb_do_syscallv: - * @cb: function to call when the system call has completed - * @fmt: gdb syscall format string - * @va: arguments to interpolate into @fmt - * - * As gdb_do_syscall, but taking a va_list rather than a variable - * argument list. - */ -void gdb_do_syscallv(gdb_syscall_complete_cb cb, const char *fmt, va_list va); -int use_gdb_syscalls(void); /* Get or set a register. Returns the size of the register. */ typedef int (*gdb_get_reg_cb)(CPUArchState *env, GByteArray *buf, int reg); @@ -120,16 +28,6 @@ void gdb_register_coprocessor(CPUState *cpu, */ int gdbserver_start(const char *port_or_device); -/** - * gdb_exit: exit gdb session, reporting inferior status - * @code: exit code reported - * - * This closes the session and sends a final packet to GDB reporting - * the exit status of the program. It also cleans up any connections - * detritus before returning. - */ -void gdb_exit(int code); - void gdb_set_stop_cpu(CPUState *cpu); /** diff --git a/include/gdbstub/syscalls.h b/include/gdbstub/syscalls.h new file mode 100644 index 0000000000..5851a2c706 --- /dev/null +++ b/include/gdbstub/syscalls.h @@ -0,0 +1,124 @@ +/* + * GDB Syscall support + * + * Copyright (c) 2023 Linaro Ltd + * + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#ifndef _SYSCALLS_H_ +#define _SYSCALLS_H_ + +/* For gdb file i/o remote protocol open flags. */ +#define GDB_O_RDONLY 0 +#define GDB_O_WRONLY 1 +#define GDB_O_RDWR 2 +#define GDB_O_APPEND 8 +#define GDB_O_CREAT 0x200 +#define GDB_O_TRUNC 0x400 +#define GDB_O_EXCL 0x800 + +/* For gdb file i/o remote protocol errno values */ +#define GDB_EPERM 1 +#define GDB_ENOENT 2 +#define GDB_EINTR 4 +#define GDB_EBADF 9 +#define GDB_EACCES 13 +#define GDB_EFAULT 14 +#define GDB_EBUSY 16 +#define GDB_EEXIST 17 +#define GDB_ENODEV 19 +#define GDB_ENOTDIR 20 +#define GDB_EISDIR 21 +#define GDB_EINVAL 22 +#define GDB_ENFILE 23 +#define GDB_EMFILE 24 +#define GDB_EFBIG 27 +#define GDB_ENOSPC 28 +#define GDB_ESPIPE 29 +#define GDB_EROFS 30 +#define GDB_ENAMETOOLONG 91 +#define GDB_EUNKNOWN 9999 + +/* For gdb file i/o remote protocol lseek whence. */ +#define GDB_SEEK_SET 0 +#define GDB_SEEK_CUR 1 +#define GDB_SEEK_END 2 + +/* For gdb file i/o stat/fstat. */ +typedef uint32_t gdb_mode_t; +typedef uint32_t gdb_time_t; + +struct gdb_stat { + uint32_t gdb_st_dev; /* device */ + uint32_t gdb_st_ino; /* inode */ + gdb_mode_t gdb_st_mode; /* protection */ + uint32_t gdb_st_nlink; /* number of hard links */ + uint32_t gdb_st_uid; /* user ID of owner */ + uint32_t gdb_st_gid; /* group ID of owner */ + uint32_t gdb_st_rdev; /* device type (if inode device) */ + uint64_t gdb_st_size; /* total size, in bytes */ + uint64_t gdb_st_blksize; /* blocksize for filesystem I/O */ + uint64_t gdb_st_blocks; /* number of blocks allocated */ + gdb_time_t gdb_st_atime; /* time of last access */ + gdb_time_t gdb_st_mtime; /* time of last modification */ + gdb_time_t gdb_st_ctime; /* time of last change */ +} QEMU_PACKED; + +struct gdb_timeval { + gdb_time_t tv_sec; /* second */ + uint64_t tv_usec; /* microsecond */ +} QEMU_PACKED; + +typedef void (*gdb_syscall_complete_cb)(CPUState *cpu, uint64_t ret, int err); + +/** + * gdb_do_syscall: + * @cb: function to call when the system call has completed + * @fmt: gdb syscall format string + * ...: list of arguments to interpolate into @fmt + * + * Send a GDB syscall request. This function will return immediately; + * the callback function will be called later when the remote system + * call has completed. + * + * @fmt should be in the 'call-id,parameter,parameter...' format documented + * for the F request packet in the GDB remote protocol. A limited set of + * printf-style format specifiers is supported: + * %x - target_ulong argument printed in hex + * %lx - 64-bit argument printed in hex + * %s - string pointer (target_ulong) and length (int) pair + */ +void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...); + +/** + * gdb_do_syscallv: + * @cb: function to call when the system call has completed + * @fmt: gdb syscall format string + * @va: arguments to interpolate into @fmt + * + * As gdb_do_syscall, but taking a va_list rather than a variable + * argument list. + */ +void gdb_do_syscallv(gdb_syscall_complete_cb cb, const char *fmt, va_list va); + +/** + * use_gdb_syscalls() - report if GDB should be used for syscalls + * + * This is mostly driven by the semihosting mode the user configures + * but assuming GDB is allowed by that we report true if GDB is + * connected to the stub. + */ +int use_gdb_syscalls(void); + +/** + * gdb_exit: exit gdb session, reporting inferior status + * @code: exit code reported + * + * This closes the session and sends a final packet to GDB reporting + * the exit status of the program. It also cleans up any connections + * detritus before returning. + */ +void gdb_exit(int code); + +#endif /* _SYSCALLS_H_ */ diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c index c50c2f8e0f..57bbda3505 100644 --- a/gdbstub/gdbstub.c +++ b/gdbstub/gdbstub.c @@ -29,6 +29,7 @@ #include "qemu/module.h" #include "trace.h" #include "exec/gdbstub.h" +#include "gdbstub/syscalls.h" #ifdef CONFIG_USER_ONLY #include "gdbstub/user.h" #else @@ -38,7 +39,6 @@ #include "sysemu/hw_accel.h" #include "sysemu/runstate.h" -#include "semihosting/semihost.h" #include "exec/exec-all.h" #include "exec/tb-flush.h" #include "exec/hwaddr.h" @@ -78,41 +78,6 @@ void gdb_init_gdbserver_state(void) bool gdb_has_xml; -/* - * Return true if there is a GDB currently connected to the stub - * and attached to a CPU - */ -static bool gdb_attached(void) -{ - return gdbserver_state.init && gdbserver_state.c_cpu; -} - -static enum { - GDB_SYS_UNKNOWN, - GDB_SYS_ENABLED, - GDB_SYS_DISABLED, -} gdb_syscall_mode; - -/* Decide if either remote gdb syscalls or native file IO should be used. */ -int use_gdb_syscalls(void) -{ - SemihostingTarget target = semihosting_get_target(); - if (target == SEMIHOSTING_TARGET_NATIVE) { - /* -semihosting-config target=native */ - return false; - } else if (target == SEMIHOSTING_TARGET_GDB) { - /* -semihosting-config target=gdb */ - return true; - } - - /* -semihosting-config target=auto */ - /* On the first call check if gdb is connected and remember. */ - if (gdb_syscall_mode == GDB_SYS_UNKNOWN) { - gdb_syscall_mode = gdb_attached() ? GDB_SYS_ENABLED : GDB_SYS_DISABLED; - } - return gdb_syscall_mode == GDB_SYS_ENABLED; -} - /* writes 2*len+1 bytes in buf */ void gdb_memtohex(GString *buf, const uint8_t *mem, int len) { @@ -922,7 +887,7 @@ static void handle_detach(GArray *params, void *user_ctx) if (!gdbserver_state.c_cpu) { /* No more process attached */ - gdb_syscall_mode = GDB_SYS_DISABLED; + gdb_disable_syscalls(); gdb_continue(); } gdb_put_packet("OK"); @@ -1234,60 +1199,6 @@ static void handle_read_all_regs(GArray *params, void *user_ctx) gdb_put_strbuf(); } -static void handle_file_io(GArray *params, void *user_ctx) -{ - if (params->len >= 1 && gdbserver_state.current_syscall_cb) { - uint64_t ret; - int err; - - ret = get_param(params, 0)->val_ull; - if (params->len >= 2) { - err = get_param(params, 1)->val_ull; - } else { - err = 0; - } - - /* Convert GDB error numbers back to host error numbers. */ -#define E(X) case GDB_E##X: err = E##X; break - switch (err) { - case 0: - break; - E(PERM); - E(NOENT); - E(INTR); - E(BADF); - E(ACCES); - E(FAULT); - E(BUSY); - E(EXIST); - E(NODEV); - E(NOTDIR); - E(ISDIR); - E(INVAL); - E(NFILE); - E(MFILE); - E(FBIG); - E(NOSPC); - E(SPIPE); - E(ROFS); - E(NAMETOOLONG); - default: - err = EINVAL; - break; - } -#undef E - - gdbserver_state.current_syscall_cb(gdbserver_state.c_cpu, ret, err); - gdbserver_state.current_syscall_cb = NULL; - } - - if (params->len >= 3 && get_param(params, 2)->opcode == (uint8_t)'C') { - gdb_put_packet("T02"); - return; - } - - gdb_continue(); -} static void handle_step(GArray *params, void *user_ctx) { @@ -1893,7 +1804,7 @@ static int gdb_handle_packet(const char *line_buf) case 'F': { static const GdbCmdParseEntry file_io_cmd_desc = { - .handler = handle_file_io, + .handler = gdb_handle_file_io, .cmd = "F", .cmd_startswith = 1, .schema = "L,L,o0" @@ -2061,88 +1972,6 @@ void gdb_set_stop_cpu(CPUState *cpu) gdbserver_state.g_cpu = cpu; } -/* Send a gdb syscall request. - This accepts limited printf-style format specifiers, specifically: - %x - target_ulong argument printed in hex. - %lx - 64-bit argument printed in hex. - %s - string pointer (target_ulong) and length (int) pair. */ -void gdb_do_syscallv(gdb_syscall_complete_cb cb, const char *fmt, va_list va) -{ - char *p; - char *p_end; - target_ulong addr; - uint64_t i64; - - if (!gdb_attached()) { - return; - } - - gdbserver_state.current_syscall_cb = cb; -#ifndef CONFIG_USER_ONLY - vm_stop(RUN_STATE_DEBUG); -#endif - p = &gdbserver_state.syscall_buf[0]; - p_end = &gdbserver_state.syscall_buf[sizeof(gdbserver_state.syscall_buf)]; - *(p++) = 'F'; - while (*fmt) { - if (*fmt == '%') { - fmt++; - switch (*fmt++) { - case 'x': - addr = va_arg(va, target_ulong); - p += snprintf(p, p_end - p, TARGET_FMT_lx, addr); - break; - case 'l': - if (*(fmt++) != 'x') - goto bad_format; - i64 = va_arg(va, uint64_t); - p += snprintf(p, p_end - p, "%" PRIx64, i64); - break; - case 's': - addr = va_arg(va, target_ulong); - p += snprintf(p, p_end - p, TARGET_FMT_lx "/%x", - addr, va_arg(va, int)); - break; - default: - bad_format: - error_report("gdbstub: Bad syscall format string '%s'", - fmt - 1); - break; - } - } else { - *(p++) = *(fmt++); - } - } - *p = 0; -#ifdef CONFIG_USER_ONLY - gdb_put_packet(gdbserver_state.syscall_buf); - /* Return control to gdb for it to process the syscall request. - * Since the protocol requires that gdb hands control back to us - * using a "here are the results" F packet, we don't need to check - * gdb_handlesig's return value (which is the signal to deliver if - * execution was resumed via a continue packet). - */ - gdb_handlesig(gdbserver_state.c_cpu, 0); -#else - /* In this case wait to send the syscall packet until notification that - the CPU has stopped. This must be done because if the packet is sent - now the reply from the syscall request could be received while the CPU - is still in the running state, which can cause packets to be dropped - and state transition 'T' packets to be sent while the syscall is still - being processed. */ - qemu_cpu_kick(gdbserver_state.c_cpu); -#endif -} - -void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...) -{ - va_list va; - - va_start(va, fmt); - gdb_do_syscallv(cb, fmt, va); - va_end(va); -} - void gdb_read_byte(uint8_t ch) { uint8_t reply; diff --git a/gdbstub/softmmu.c b/gdbstub/softmmu.c index ff18611ce7..373b6b4d61 100644 --- a/gdbstub/softmmu.c +++ b/gdbstub/softmmu.c @@ -15,6 +15,7 @@ #include "qemu/error-report.h" #include "qemu/cutils.h" #include "exec/gdbstub.h" +#include "gdbstub/syscalls.h" #include "exec/hwaddr.h" #include "exec/tb-flush.h" #include "sysemu/cpus.h" @@ -114,9 +115,9 @@ static void gdb_vm_state_change(void *opaque, bool running, RunState state) if (running || gdbserver_state.state == RS_INACTIVE) { return; } + /* Is there a GDB syscall waiting to be sent? */ - if (gdbserver_state.current_syscall_cb) { - gdb_put_packet(gdbserver_state.syscall_buf); + if (gdb_handled_syscall()) { return; } @@ -380,7 +381,7 @@ int gdbserver_start(const char *device) } gdbserver_state.state = chr ? RS_IDLE : RS_INACTIVE; gdbserver_system_state.mon_chr = mon_chr; - gdbserver_state.current_syscall_cb = NULL; + gdb_syscall_reset(); return 0; } diff --git a/gdbstub/syscalls.c b/gdbstub/syscalls.c new file mode 100644 index 0000000000..04ea0163ab --- /dev/null +++ b/gdbstub/syscalls.c @@ -0,0 +1,230 @@ +/* + * GDB Syscall Handling + * + * GDB can execute syscalls on the guests behalf, currently used by + * the various semihosting extensions. As this interfaces with a guest + * ABI we need to build it per-guest (although in reality its a 32 or + * 64 bit target_ulong that is the only difference). + * + * Copyright (c) 2003-2005 Fabrice Bellard + * Copyright (c) 2023 Linaro Ltd + * + * SPDX-License-Identifier: LGPL-2.0+ + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "semihosting/semihost.h" +#include "sysemu/runstate.h" +#include "gdbstub/user.h" +#include "gdbstub/syscalls.h" +#include "trace.h" +#include "internals.h" + +/* Common state */ +extern GDBState gdbserver_state; + +/* Syscall specific state */ +typedef struct { + char syscall_buf[256]; + gdb_syscall_complete_cb current_syscall_cb; +} GDBSyscallState; + +static GDBSyscallState gdbserver_syscall_state; + +/* + * Return true if there is a GDB currently connected to the stub + * and attached to a CPU + */ +static bool gdb_attached(void) +{ + return gdbserver_state.init && gdbserver_state.c_cpu; +} + +static enum { + GDB_SYS_UNKNOWN, + GDB_SYS_ENABLED, + GDB_SYS_DISABLED, +} gdb_syscall_mode; + +/* Decide if either remote gdb syscalls or native file IO should be used. */ +int use_gdb_syscalls(void) +{ + SemihostingTarget target = semihosting_get_target(); + if (target == SEMIHOSTING_TARGET_NATIVE) { + /* -semihosting-config target=native */ + return false; + } else if (target == SEMIHOSTING_TARGET_GDB) { + /* -semihosting-config target=gdb */ + return true; + } + + /* -semihosting-config target=auto */ + /* On the first call check if gdb is connected and remember. */ + if (gdb_syscall_mode == GDB_SYS_UNKNOWN) { + gdb_syscall_mode = gdb_attached() ? GDB_SYS_ENABLED : GDB_SYS_DISABLED; + } + return gdb_syscall_mode == GDB_SYS_ENABLED; +} + +/* called when the stub detaches */ +void gdb_disable_syscalls(void) +{ + gdb_syscall_mode = GDB_SYS_DISABLED; +} + +void gdb_syscall_reset(void) +{ + gdbserver_syscall_state.current_syscall_cb = NULL; +} + +bool gdb_handled_syscall(void) +{ + if (gdbserver_syscall_state.current_syscall_cb) { + gdb_put_packet(gdbserver_syscall_state.syscall_buf); + return true; + } + + return false; +} + +/* Send a gdb syscall request. + This accepts limited printf-style format specifiers, specifically: + %x - target_ulong argument printed in hex. + %lx - 64-bit argument printed in hex. + %s - string pointer (target_ulong) and length (int) pair. */ +void gdb_do_syscallv(gdb_syscall_complete_cb cb, const char *fmt, va_list va) +{ + char *p; + char *p_end; + target_ulong addr; + uint64_t i64; + + if (!gdb_attached()) { + return; + } + + gdbserver_syscall_state.current_syscall_cb = cb; +#ifndef CONFIG_USER_ONLY + vm_stop(RUN_STATE_DEBUG); +#endif + p = &gdbserver_syscall_state.syscall_buf[0]; + p_end = &gdbserver_syscall_state.syscall_buf[sizeof(gdbserver_syscall_state.syscall_buf)]; + *(p++) = 'F'; + while (*fmt) { + if (*fmt == '%') { + fmt++; + switch (*fmt++) { + case 'x': + addr = va_arg(va, target_ulong); + p += snprintf(p, p_end - p, TARGET_FMT_lx, addr); + break; + case 'l': + if (*(fmt++) != 'x') + goto bad_format; + i64 = va_arg(va, uint64_t); + p += snprintf(p, p_end - p, "%" PRIx64, i64); + break; + case 's': + addr = va_arg(va, target_ulong); + p += snprintf(p, p_end - p, TARGET_FMT_lx "/%x", + addr, va_arg(va, int)); + break; + default: + bad_format: + error_report("gdbstub: Bad syscall format string '%s'", + fmt - 1); + break; + } + } else { + *(p++) = *(fmt++); + } + } + *p = 0; +#ifdef CONFIG_USER_ONLY + gdb_put_packet(gdbserver_syscall_state.syscall_buf); + /* Return control to gdb for it to process the syscall request. + * Since the protocol requires that gdb hands control back to us + * using a "here are the results" F packet, we don't need to check + * gdb_handlesig's return value (which is the signal to deliver if + * execution was resumed via a continue packet). + */ + gdb_handlesig(gdbserver_state.c_cpu, 0); +#else + /* In this case wait to send the syscall packet until notification that + the CPU has stopped. This must be done because if the packet is sent + now the reply from the syscall request could be received while the CPU + is still in the running state, which can cause packets to be dropped + and state transition 'T' packets to be sent while the syscall is still + being processed. */ + qemu_cpu_kick(gdbserver_state.c_cpu); +#endif +} + +void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...) +{ + va_list va; + + va_start(va, fmt); + gdb_do_syscallv(cb, fmt, va); + va_end(va); +} + +/* + * GDB Command Handlers + */ + +void gdb_handle_file_io(GArray *params, void *user_ctx) +{ + if (params->len >= 1 && gdbserver_syscall_state.current_syscall_cb) { + uint64_t ret; + int err; + + ret = get_param(params, 0)->val_ull; + if (params->len >= 2) { + err = get_param(params, 1)->val_ull; + } else { + err = 0; + } + + /* Convert GDB error numbers back to host error numbers. */ +#define E(X) case GDB_E##X: err = E##X; break + switch (err) { + case 0: + break; + E(PERM); + E(NOENT); + E(INTR); + E(BADF); + E(ACCES); + E(FAULT); + E(BUSY); + E(EXIST); + E(NODEV); + E(NOTDIR); + E(ISDIR); + E(INVAL); + E(NFILE); + E(MFILE); + E(FBIG); + E(NOSPC); + E(SPIPE); + E(ROFS); + E(NAMETOOLONG); + default: + err = EINVAL; + break; + } +#undef E + + gdbserver_syscall_state.current_syscall_cb(gdbserver_state.c_cpu, ret, err); + gdbserver_syscall_state.current_syscall_cb = NULL; + } + + if (params->len >= 3 && get_param(params, 2)->opcode == (uint8_t)'C') { + gdb_put_packet("T02"); + return; + } + + gdb_continue(); +} diff --git a/gdbstub/user.c b/gdbstub/user.c index ccc73683de..50a47e6931 100644 --- a/gdbstub/user.c +++ b/gdbstub/user.c @@ -15,6 +15,7 @@ #include "exec/hwaddr.h" #include "exec/tb-flush.h" #include "exec/gdbstub.h" +#include "gdbstub/syscalls.h" #include "gdbstub/user.h" #include "hw/core/cpu.h" #include "trace.h" diff --git a/linux-user/exit.c b/linux-user/exit.c index fa6ef0b9b4..2bb8ae9231 100644 --- a/linux-user/exit.c +++ b/linux-user/exit.c @@ -17,7 +17,7 @@ * along with this program; if not, see . */ #include "qemu/osdep.h" -#include "exec/gdbstub.h" +#include "gdbstub/syscalls.h" #include "qemu.h" #include "user-internals.h" #ifdef CONFIG_GPROF diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index 62d8bae97f..564fe17f75 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -34,6 +34,7 @@ #include "qemu/osdep.h" #include "qemu/timer.h" #include "exec/gdbstub.h" +#include "gdbstub/syscalls.h" #include "semihosting/semihost.h" #include "semihosting/console.h" #include "semihosting/common-semi.h" diff --git a/semihosting/guestfd.c b/semihosting/guestfd.c index b05c52f26f..acb86b50dd 100644 --- a/semihosting/guestfd.c +++ b/semihosting/guestfd.c @@ -9,7 +9,7 @@ */ #include "qemu/osdep.h" -#include "exec/gdbstub.h" +#include "gdbstub/syscalls.h" #include "semihosting/semihost.h" #include "semihosting/guestfd.h" #ifdef CONFIG_USER_ONLY diff --git a/semihosting/syscalls.c b/semihosting/syscalls.c index e20241b6b4..565adfc1e9 100644 --- a/semihosting/syscalls.c +++ b/semihosting/syscalls.c @@ -7,8 +7,8 @@ */ #include "qemu/osdep.h" -#include "exec/gdbstub.h" #include "cpu.h" +#include "gdbstub/syscalls.h" #include "semihosting/guestfd.h" #include "semihosting/syscalls.h" #include "semihosting/console.h" diff --git a/softmmu/runstate.c b/softmmu/runstate.c index cab9f6fc07..d4c5758e43 100644 --- a/softmmu/runstate.c +++ b/softmmu/runstate.c @@ -30,7 +30,7 @@ #include "crypto/cipher.h" #include "crypto/init.h" #include "exec/cpu-common.h" -#include "exec/gdbstub.h" +#include "gdbstub/syscalls.h" #include "hw/boards.h" #include "migration/misc.h" #include "migration/postcopy-ram.h" diff --git a/target/m68k/m68k-semi.c b/target/m68k/m68k-semi.c index f753710d7d..88ad9ba814 100644 --- a/target/m68k/m68k-semi.c +++ b/target/m68k/m68k-semi.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/syscalls.h" #include "gdbstub/helpers.h" #include "semihosting/syscalls.h" #include "semihosting/softmmu-uaccess.h" diff --git a/target/mips/tcg/sysemu/mips-semi.c b/target/mips/tcg/sysemu/mips-semi.c index 4e6e759057..f3735df7b9 100644 --- a/target/mips/tcg/sysemu/mips-semi.c +++ b/target/mips/tcg/sysemu/mips-semi.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "cpu.h" #include "qemu/log.h" -#include "exec/gdbstub.h" +#include "gdbstub/syscalls.h" #include "gdbstub/helpers.h" #include "semihosting/softmmu-uaccess.h" #include "semihosting/semihost.h" diff --git a/target/nios2/nios2-semi.c b/target/nios2/nios2-semi.c index 113b3f22aa..3738774976 100644 --- a/target/nios2/nios2-semi.c +++ b/target/nios2/nios2-semi.c @@ -23,7 +23,7 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/gdbstub.h" +#include "gdbstub/syscalls.h" #include "gdbstub/helpers.h" #include "semihosting/syscalls.h" #include "semihosting/softmmu-uaccess.h" diff --git a/gdbstub/meson.build b/gdbstub/meson.build index 827f062af6..56c40c25ef 100644 --- a/gdbstub/meson.build +++ b/gdbstub/meson.build @@ -5,6 +5,10 @@ # specific_ss.add(files('gdbstub.c')) + +# These have to built to the target ABI +specific_ss.add(files('syscalls.c')) + softmmu_ss.add(files('softmmu.c')) user_ss.add(files('user.c')) -- 2.34.1 From MAILER-DAEMON Thu Jan 05 11:57:52 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTYu-0006j6-2z for mharc-qemu-riscv@gnu.org; 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Iglesias" , Bastian Koppelmann , Jiaxun Yang , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org References: <20230105164320.2164095-1-alex.bennee@linaro.org> <20230105164320.2164095-2-alex.bennee@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230105164320.2164095-2-alex.bennee@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.939, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 17:02:07 -0000 On 5/1/23 17:43, Alex Bennée wrote: > Use something more specific to avoid name clashes. > > Reviewed-by: Richard Henderson > Signed-off-by: Alex Bennée > --- > gdbstub/internals.h | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 05 12:02:55 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTdn-0003Wc-J3 for mharc-qemu-riscv@gnu.org; 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Thu, 05 Jan 2023 09:02:47 -0800 (PST) Message-ID: Date: Thu, 5 Jan 2023 18:02:43 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v2 03/21] gdbstub: fix-up copyright and license files Content-Language: en-US To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org References: <20230105164320.2164095-1-alex.bennee@linaro.org> <20230105164320.2164095-4-alex.bennee@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230105164320.2164095-4-alex.bennee@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=philmd@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.939, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 17:02:52 -0000 On 5/1/23 17:43, Alex Bennée wrote: > When I started splitting gdbstub apart I was a little too boilerplate > with my file headers. Fix up to carry over Fabrice's copyright and the > LGPL license header. > > Fixes: ae7467b1ac (gdbstub: move breakpoint logic to accel ops) > Reviewed-by: Richard Henderson > Signed-off-by: Alex Bennée > --- > gdbstub/softmmu.c | 3 ++- > gdbstub/user.c | 3 ++- > 2 files changed, 4 insertions(+), 2 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 05 12:09:25 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTk5-0002Hn-NK for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 12:09:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTk4-0002Dw-07 for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 12:09:24 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTk1-0007C2-3R for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 12:09:23 -0500 Received: by mail-wm1-x32f.google.com with SMTP id k22-20020a05600c1c9600b003d1ee3a6289so1834138wms.2 for ; Thu, 05 Jan 2023 09:09:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=CWmgURgVvT3HkVgRo206lKNbnitmtJNybOYPrf7FVHA=; b=t0RahvRtCKTVBiC3ODDBBpwR2I4ctkh78vTjxkDFo9mxLY4Ni6dlq0nO35xlnCTIDn wHpWm5pe0eQcvHxvxl9mqogm7lY0Ww28CngjiHEf9nxR7jPGqhd1KE3EK83WivqjEZVy 0O3XLjrxMpUkfEV2C9x4FizprG6GRlmGeGTksKdwDahrT3qh5PUxQm0od1vGfK/nznR0 d86PpVEnzRk8Dxi7QXbONqSIeuiHyCzO0FLtbSu028XPCOtjGUiV2Rg6qrq0ByHOJXl/ oRXgGyuc7KTc/aOFvSAB1JqVyA1qBsveB1lTU6qX+ttN1+LSU7lOY4zNc3v+jF0Wj+3T IDoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=CWmgURgVvT3HkVgRo206lKNbnitmtJNybOYPrf7FVHA=; b=m5jvY/b64fS3X0y/1iQbfw3ALO2DZBxW//hLbc+S2dJDs3Kx1l8Hlx3i3y7UvoZOq/ sl51GBlaaKH+UioDqN0VZvhIhLEhAcSz88mCrMcdr5ZHKLy8mHvXqTNqGHnUxKJ1k6wF kMsaFEclqs8hk2Zc7s2VSROSD9AKe9A1eSh373prpMEx+2EExONaG4t9N2qBS58PwGRG qkLXGwPlNvx4Z94sVhLEzjgsP5Fb66zK4YE8GPhelceHeYeDO7gHICZotrKQn71OsJdV FSNGaYj8MhfoP+ef0Dq9qE2XpCx2Tl2Bd9lb8odU9v0ZjzRrql/QIViVQ3cNq4ybbBcH on1g== X-Gm-Message-State: AFqh2kpDvZsp7uSsUnhMJcOc78Xo8sRtX40ckpliJ9H7W+87XbG2AVfs pwSBrUz4AoqcGdRbk0FjiG3urQ== X-Google-Smtp-Source: AMrXdXvHkOYnZr7eQ/ugslrmQ+p+ngw764iMWu0RkcvptaEQkwPEVd43YAIXhbHAJWd9egKMqsen9A== X-Received: by 2002:a05:600c:1911:b0:3d9:8635:a916 with SMTP id j17-20020a05600c191100b003d98635a916mr31504778wmq.9.1672938559250; Thu, 05 Jan 2023 09:09:19 -0800 (PST) Received: from [192.168.30.216] ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id o5-20020a05600c510500b003b4ff30e566sm7814600wms.3.2023.01.05.09.09.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Jan 2023 09:09:18 -0800 (PST) Message-ID: <65ef72d7-1d7d-d6d4-a10f-fe854a34d39a@linaro.org> Date: Thu, 5 Jan 2023 18:09:15 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v2 09/21] gdbstub: make various helpers visible to the rest of the module Content-Language: en-US To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org References: <20230105164320.2164095-1-alex.bennee@linaro.org> <20230105164320.2164095-10-alex.bennee@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230105164320.2164095-10-alex.bennee@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.939, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 17:09:24 -0000 On 5/1/23 17:43, Alex Bennée wrote: > We will be needing to use these helpers between the user and softmmu > files so declare them in the headers, add a system prefix and remove "system prefix" -> "'gdb_' prefix" > static from the implementations. > > Signed-off-by: Alex Bennée > --- > gdbstub/internals.h | 25 ++++ > gdbstub/gdbstub.c | 271 ++++++++++++++++++++++---------------------- > 2 files changed, 161 insertions(+), 135 deletions(-) Reviewed-by: Philippe Mathieu-Daudé > +/* > + * Connection helpers for both softmmu and user backends > + */ > + > +void gdb_put_strbuf(void); > +int gdb_put_packet(const char *buf); > +int gdb_put_packet_binary(const char *buf, int len, bool dump); > +void gdb_hextomem(GByteArray *mem, const char *buf, int len); > +void gdb_memtohex(GString *buf, const uint8_t *mem, int len); > +void gdb_memtox(GString *buf, const char *mem, int len); > +void gdb_read_byte(uint8_t ch); > + > +/* utility helpers */ > +CPUState *gdb_first_attached_cpu(void); > +void gdb_append_thread_id(CPUState *cpu, GString *buf); > +int gdb_get_cpu_index(CPUState *cpu); > + > +void gdb_init_gdbserver_state(void); > +void gdb_create_default_process(GDBState *s); > + > +/* > + * Helpers with separate softmmu and user implementations > + */ > +void gdb_put_buffer(const uint8_t *buf, int len); From MAILER-DAEMON Thu Jan 05 12:14:13 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDToj-0000aP-E1 for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 12:14:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDToc-0000TK-Ma for qemu-riscv@nongnu.org; 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Thu, 05 Jan 2023 09:14:00 -0800 (PST) Message-ID: <27a8f6ef-b78e-31ae-6bba-eb3f106de9f7@linaro.org> Date: Thu, 5 Jan 2023 18:13:57 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v2 12/21] gdbstub: abstract target specific details from gdb_put_packet_binary Content-Language: en-US To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org References: <20230105164320.2164095-1-alex.bennee@linaro.org> <20230105164320.2164095-13-alex.bennee@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230105164320.2164095-13-alex.bennee@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.939, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 17:14:11 -0000 On 5/1/23 17:43, Alex Bennée wrote: > We unfortunately handle the checking of packet acknowledgement > differently for user and softmmu modes. Abstract the user mode stuff > behind gdb_got_immediate_ack with a stub for softmmu. > > Signed-off-by: Alex Bennée > --- > gdbstub/internals.h | 15 +++++++++++++++ > gdbstub/gdbstub.c | 10 ++-------- > gdbstub/softmmu.c | 8 ++++++++ > gdbstub/user.c | 19 +++++++++++++++++++ > 4 files changed, 44 insertions(+), 8 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 05 12:22:57 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDTxB-0007hd-F7 for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 12:22:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDTxA-0007hE-CM for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 12:22:56 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDTx8-0007Uu-Pe for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 12:22:56 -0500 Received: by mail-wm1-x330.google.com with SMTP id c65-20020a1c3544000000b003cfffd00fc0so1841018wma.1 for ; Thu, 05 Jan 2023 09:22:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=ylKcpkWHZgkHqciFS3PTc6pROI+nTj0vsfG4lupU4fc=; b=Qtak04rDs48iN0UbCFzj6sXIS7Qf/4vd8+ZYPRl7qUEI2qkDAuGraPFkMW72WV9dyC XK/4BswCGE1EJq8kGp1RJPwtiewgFtSfWlSzjZNUvUVzmVpPR9x+31W00IcFjgtWZNsi nwj4WdKjtJYTsfJCd8HSjnXlGHwhhu9TFwz5UwY9pVZsNqK8p3qO0KqS2TAfMnE515VA e67hNR1sW1Q9tgN3U7VwNVR/A2vQtVK4bkteholyPmnRoNWkCi9DRzAAcVpE57SWE82i Mdc9yJmNXgRiyhiy85dlj+9uDNNy8zEJqfTftJ9B0Vfba0BeQVjuQcxVlp+lL7tC96vQ aQxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=ylKcpkWHZgkHqciFS3PTc6pROI+nTj0vsfG4lupU4fc=; b=2MNQqeCNRuxTriLYCDbvtS5jSP/F0cMAuHzUXbRCNZCbyjvuxDzJDUaaj+Rw5BBRUr itPAd9GsUVr99wmy/rW0sPr3ZnaOXPVeBFgcv0so9ZEdPV3aVR1RIzNbduXJOUOh+tLA JZij9C0sTo1l7BWUnlNDbv7dMzi/ASR0D3mfih11SvywVprnbt9PupTvIRLkse259c9p y8UzomuImD2JM5LBK5fYHnvabToVnwORyv/O9I6iEAZ9zbda+9/lyWUsAK98cBOOfjCS eMtXVdheHvbWZMVfYgWUJjngMREbjYUWgdRCd+KIH60uCJKVBq3o14HiacL805a7pX+h p2hA== X-Gm-Message-State: AFqh2krw/c8ZmkkllRBENwjNPpUuBRCECKz9fU0+oJHetIE2WanEUjbc DE2GuC13VWerhz4dJ9yHlG05yg== X-Google-Smtp-Source: AMrXdXvEeWn7Xu7HP8yM4dJdtXlej7ArIR+fWdPsZg+GugRgOgv1vRf8kEtdaVGKN6RzWw2EgFN/WQ== X-Received: by 2002:a05:600c:34d4:b0:3cf:a39f:eb2a with SMTP id d20-20020a05600c34d400b003cfa39feb2amr36839330wmq.11.1672939373107; Thu, 05 Jan 2023 09:22:53 -0800 (PST) Received: from [192.168.30.216] ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id l14-20020a05600c4f0e00b003d96c811d6dsm3321992wmq.30.2023.01.05.09.22.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Jan 2023 09:22:52 -0800 (PST) Message-ID: <3aed1547-aedd-7856-7ab4-4d2ee9176c1b@linaro.org> Date: Thu, 5 Jan 2023 18:22:48 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v2 13/21] gdbstub: specialise handle_query_attached Content-Language: en-US To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org References: <20230105164320.2164095-1-alex.bennee@linaro.org> <20230105164320.2164095-14-alex.bennee@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230105164320.2164095-14-alex.bennee@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.939, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 17:22:56 -0000 On 5/1/23 17:43, Alex Bennée wrote: > In both user and softmmu cases we are just replying with a constant. > If the linker is paying attention it may even be able to sort optimise > the call. > > Signed-off-by: Alex Bennée > --- > gdbstub/internals.h | 4 +++- > gdbstub/gdbstub.c | 15 ++------------- > gdbstub/softmmu.c | 5 +++++ > gdbstub/user.c | 5 +++++ > 4 files changed, 15 insertions(+), 14 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 05 12:25:57 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDU05-0001SC-LV for mharc-qemu-riscv@gnu.org; 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Thu, 05 Jan 2023 09:25:51 -0800 (PST) Message-ID: <460dc896-f3bf-26ac-5c0d-95ebe1e3ecfd@linaro.org> Date: Thu, 5 Jan 2023 18:25:48 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v2 16/21] gdbstub: specialise stub_can_reverse Content-Language: en-US To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org References: <20230105164320.2164095-1-alex.bennee@linaro.org> <20230105164320.2164095-17-alex.bennee@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230105164320.2164095-17-alex.bennee@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.939, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 17:25:56 -0000 On 5/1/23 17:43, Alex Bennée wrote: > Currently we only support replay for softmmu mode so it is a constant > false for user-mode. > > Signed-off-by: Alex Bennée > --- > gdbstub/internals.h | 1 + > gdbstub/gdbstub.c | 13 ++----------- > gdbstub/softmmu.c | 5 +++++ > gdbstub/user.c | 5 +++++ > 4 files changed, 13 insertions(+), 11 deletions(-) > > diff --git a/gdbstub/internals.h b/gdbstub/internals.h > index a371373c1d..1def9dfc9c 100644 > --- a/gdbstub/internals.h > +++ b/gdbstub/internals.h > @@ -126,6 +126,7 @@ CPUState *gdb_first_attached_cpu(void); > void gdb_append_thread_id(CPUState *cpu, GString *buf); > int gdb_get_cpu_index(CPUState *cpu); > unsigned int gdb_get_max_cpus(void); /* both */ > +bool gdb_stub_can_reverse(void); /* softmmu, stub for user */ Maybe without the 'stub', gdb_can_reverse()? Anyhow, Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 05 12:26:52 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDU0y-0002Pm-5j for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 12:26:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDU0t-0002NM-Dy for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 12:26:47 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDU0p-00006T-7D for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 12:26:46 -0500 Received: by mail-wm1-x32e.google.com with SMTP id ja17so28536840wmb.3 for ; Thu, 05 Jan 2023 09:26:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=YJ9R9RXtjscsZqJEnjO20+62buuIfhCqeryuH+omc1U=; b=x2O4i4Yvt+VOEEhJTeqBAX2ZZH9HOGHi9BCYO2B50iDwu9plmEH/dXFX7RX+6DkTQZ LG/Rc2Zh7NiQ67BpEaQLXVD/0HqDo0LN/+1tuXesvbunNeSDxpZgWqziHbRUpAYw1Zbp 7BxZYB2X1PrHDUnPCTvLWG4B+R/AcJDXcectJ4H7LlEqKsn8SScgsjr11E8F/dGwtA1y YfwiKIVHokOgU2rIdBnkExAT7D9hLv0+73nBMzwJItqTHF6qHApQgIqxszEBFWL8tYZ/ YPWxlQNSmnmgUMtu9hcJm80mt/FbwQYL0hT0cPRf4nhnPJiPw1fHxud3TLtCz3S84qYQ 6Y8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=YJ9R9RXtjscsZqJEnjO20+62buuIfhCqeryuH+omc1U=; b=RMOEjPPuv9dut6yDx91bac0jkBzcriKpHMk6lpaT0yZ/1ec92X0tUFX5Gv3u9dvLAF dbf9iMm+6Cetg2nPmen9sfu1tzIHz+IIURXXsyiP9sOk86kbmbPGKAde7+u+G+56v3ok h2hMqcRvmA8kRtEbWOHZHTDkVncx86WE00IhbHgTAJd1gaB796+h3zhQBtW44+h7g4y8 c20NxPVwPuP5FKE29nPjxo39n00OyjYrnis61riYcV4ebuQLETpa+EusqCeR732hWF84 PN0ruEeHEG8Rz5Yr+CDc2Xhba/ppUQXGnKoT3DaY5nbFrOsdf8lrRaGkX258CyloaKZr RU/w== X-Gm-Message-State: AFqh2krfxrmPNbQEDrha1Q8DIBBjBI2wESXkSPv/5gDvmo2mRYm1AhZp 4z5Xjya03xNEscUrSmvKJU4umA== X-Google-Smtp-Source: AMrXdXt4tXUQ+WgtBP8T0TQkuq3QEoOCebVqsYx3qjzPi4ZeiOLcHp/FfaFFQkJQIJhddq/US5ii7g== X-Received: by 2002:a05:600c:d1:b0:3d3:4d21:704d with SMTP id u17-20020a05600c00d100b003d34d21704dmr37046020wmm.14.1672939601883; Thu, 05 Jan 2023 09:26:41 -0800 (PST) Received: from [192.168.30.216] ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id h10-20020a05600c2caa00b003cfd58409desm3158151wmc.13.2023.01.05.09.26.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Jan 2023 09:26:41 -0800 (PST) Message-ID: Date: Thu, 5 Jan 2023 18:26:38 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v2 17/21] gdbstub: fix address type of gdb_set_cpu_pc Content-Language: en-US To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org References: <20230105164320.2164095-1-alex.bennee@linaro.org> <20230105164320.2164095-18-alex.bennee@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230105164320.2164095-18-alex.bennee@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.939, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 17:26:48 -0000 On 5/1/23 17:43, Alex Bennée wrote: > The underlying call uses vaddr and the comms API uses unsigned long > long which will always fit. We don't need to deal in target_ulong > here. > > Signed-off-by: Alex Bennée > --- > gdbstub/gdbstub.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) Yay \o/ Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 05 12:28:46 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDU2n-0005cn-Jq for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 12:28:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDU2k-0005PC-97 for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 12:28:42 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDU2i-00017s-K1 for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 12:28:41 -0500 Received: by mail-wm1-x32f.google.com with SMTP id ja17so28540125wmb.3 for ; Thu, 05 Jan 2023 09:28:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=xLc3h8yqPnvvcE3JzSjb8mPuQCKVOGDC88RCNMEdEBI=; b=KwSIzupnOaRjU7pDIFTrJ/Gs8FzxZk9o6Ayv+7BqF+1P7MKPtPAaTjFNO+O7KncIRt wpSiNyWy5ibCAdKlsoxsvUsuocAhA1Ilz4m+xGOpeMNNw08vhqNjj5CN7GdyEb03PE5F tfZHnRGb/F6JGUuO1yo45zPTrcR2vRsa/T7+h7O+aWvqgCsTjPR/BP/T+mHO+mbIyJeG I5nxi4zOEeYJZz47k1CHN998L56TY0Ajc1dM68Dg8B9KFF3dh0RY3KaTQEdWKyX0P8IF FnAbNVkJxYC65weSWL9xpVKqBxRTg2eM7nkjv/T9WFuQ5eUNrk6xhY+bmQ88SKqjwRPo njsw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=xLc3h8yqPnvvcE3JzSjb8mPuQCKVOGDC88RCNMEdEBI=; b=Dwcu0xRiXGBKnjnG0BQChMXlZRbCOrDv09Qj5S/cg1iv3Bl0I/UA7+P3Cdg///SCDN wftEOPi9McepcEtQpp3hlJaC3Gwpkn5cG77SHmohRqK8jmiUauQEo7DMe/LL/I7Naxir xIf6bOkqGgSLi5YutguqZIRC2HaMMSQ9TLkZUFfMhGScfvpHgSE3eioa6f0xxCiXoQIb e9L8+KWIo1ntc/0cMuVNIzOUlMwBuFh0ofxVcDqvb659O7J6egWVzKQaiql4t0idMTM6 R09u1Edspa+T2/7mxROeSek6w8Uh+Dz462yJVIuwaGxtMv0GRB3ewnqeWdQcaMYnh59Z KXEg== X-Gm-Message-State: AFqh2kpfS3aS0+lTm5Omb/DkuLek3o8F2jZjdviiTdfMG2W4pfUp5xdr us7uyd6NWcc0YbVsHuRsKGr9Eg== X-Google-Smtp-Source: AMrXdXsF0Bc9tPrumh0aEI/VQiagz31RjL4K54DzQvbwkaUt8OmYanPtii91U7p06dGyCd8PCxDItg== X-Received: by 2002:a05:600c:3b93:b0:3d3:43ae:4d10 with SMTP id n19-20020a05600c3b9300b003d343ae4d10mr39659064wms.11.1672939719323; Thu, 05 Jan 2023 09:28:39 -0800 (PST) Received: from [192.168.30.216] ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id h15-20020a05600c314f00b003d99469ece1sm3410678wmo.24.2023.01.05.09.28.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Jan 2023 09:28:38 -0800 (PST) Message-ID: <7d8fc0af-93ba-c79f-4c53-0cb52db40fa5@linaro.org> Date: Thu, 5 Jan 2023 18:28:35 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v2 18/21] gdbstub: don't use target_ulong while handling registers Content-Language: en-US To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org References: <20230105164320.2164095-1-alex.bennee@linaro.org> <20230105164320.2164095-19-alex.bennee@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230105164320.2164095-19-alex.bennee@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.939, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 17:28:43 -0000 On 5/1/23 17:43, Alex Bennée wrote: > This is a hangover from the original code. addr is misleading as it is > only a really a register id. While len will never exceed "a really"? > MAX_PACKET_LENGTH I've used size_t as that is what strlen returns. > > Signed-off-by: Alex Bennée > --- > gdbstub/gdbstub.c | 17 ++++++++++------- > 1 file changed, 10 insertions(+), 7 deletions(-) > > diff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c > index 4547ca3367..c50c2f8e0f 100644 > --- a/gdbstub/gdbstub.c > +++ b/gdbstub/gdbstub.c > @@ -1192,7 +1192,8 @@ static void handle_read_mem(GArray *params, void *user_ctx) > > static void handle_write_all_regs(GArray *params, void *user_ctx) > { > - target_ulong addr, len; > + int reg_id; 'unsigned'? > + size_t len; > uint8_t *registers; > int reg_size; > > @@ -1204,9 +1205,10 @@ static void handle_write_all_regs(GArray *params, void *user_ctx) > len = strlen(get_param(params, 0)->data) / 2; > gdb_hextomem(gdbserver_state.mem_buf, get_param(params, 0)->data, len); > registers = gdbserver_state.mem_buf->data; > - for (addr = 0; addr < gdbserver_state.g_cpu->gdb_num_g_regs && len > 0; > - addr++) { > - reg_size = gdb_write_register(gdbserver_state.g_cpu, registers, addr); > + for (reg_id = 0; > + reg_id < gdbserver_state.g_cpu->gdb_num_g_regs && len > 0; > + reg_id++) { Regardless: Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 05 12:30:56 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDU4u-0000qF-MG for mharc-qemu-riscv@gnu.org; Thu, 05 Jan 2023 12:30:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDU4t-0000l8-ER for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 12:30:55 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDU4q-0001zH-BU for qemu-riscv@nongnu.org; Thu, 05 Jan 2023 12:30:55 -0500 Received: by mail-wm1-x329.google.com with SMTP id l26so26954169wme.5 for ; Thu, 05 Jan 2023 09:30:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=1XSMKE/5EB1bpbXcBjrkxqRLay8QBqdRXQ4g4OxlKas=; b=IF3iR0QlAzQbtNh5PZvukBynNxG6WmcjaC+y5AYGPVFiffqpNkPNurBB6n+7OUKaMS RhtBuGxJyN0rFlS4EFpLP0ipdciXkBniWFAy9l3/luaNTohi1FyZPtCJ36SAB1BNZ51m sinBBGFINSlLcfemBVSuhwiYPc+KLpC1HpSzeAtqHeHzQWxgOIr45+txY4Jcy6EN9jGH X9UZA2QGtkvAaCtVzLI1vQLr9y7h75+9qSF23NvCVGV+0Gd+2/wgRArQJiHO9BHEjEvk 52NBZVFki1sW+LFiAJuiQj9CUrG0HB9ZDsW/mF4IjbWdTXvbbZqvOxJPGtoFP9v6KYtv SS4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=1XSMKE/5EB1bpbXcBjrkxqRLay8QBqdRXQ4g4OxlKas=; b=y0aODpVjbg1BcFlPy7Ds4imJmwgWz7Zds0+BDQ6iioaxUsJEAwFQAap0NYt6eLpm9v T7yvYRoIYmww2nZ4OSue2PeFvOKSxpQUH4MktuNjVkUbp279/1Hk71lFMui6LiCJ8v46 VSZ0gzJtsa9BeKcFz3BL0PElU993ZyWIt2b1Kc+rShi4Zza1ZOV39w9MGSwn8dmxSnZV Yr3GO6MhBldUfInHc6yHb/7Eh1vYNXCDo2G1+Gr6TC98VB8Q8h+OunKrhPRnLl9N6Zrc l3+kKW6X901oGHl0DJPTroI13QZsKiZuCkmUxRHJi0/xem2HazvRrXLxJ1Zw8Ykg7Hsv HV8Q== X-Gm-Message-State: AFqh2kr5OWetpaXc6fMbIyD/1YoXPhd/TJZxvtnrkTTpZlqe+PePepb0 I8DE4WjVuCtZwQESYY2qTG9Grg== X-Google-Smtp-Source: AMrXdXullybworR9QQQLRTJsj7FIQUrHdLLVkmcuoAHB2iNZk9CVkB0nL7sUfBxwS0clQa/mjPWYBg== X-Received: by 2002:a05:600c:8a9:b0:3cf:6e85:eda7 with SMTP id l41-20020a05600c08a900b003cf6e85eda7mr37622567wmp.14.1672939850822; Thu, 05 Jan 2023 09:30:50 -0800 (PST) Received: from [192.168.30.216] ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id s35-20020a05600c31a300b003cfa81e2eb4sm2886611wmp.38.2023.01.05.09.30.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 05 Jan 2023 09:30:50 -0800 (PST) Message-ID: <63479354-031b-add3-72b5-f32719f33f3a@linaro.org> Date: Thu, 5 Jan 2023 18:30:47 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v2 19/21] gdbstub: move register helpers into standalone include Content-Language: en-US To: =?UTF-8?Q?Alex_Benn=c3=a9e?= , qemu-devel@nongnu.org, alex.bennee@gmail.com Cc: David Hildenbrand , Sunil Muthuswamy , Aurelien Jarno , Michael Rolnik , Aleksandar Rikalo , Greg Kurz , Ilya Leoshkevich , Thomas Huth , qemu-ppc@nongnu.org, Laurent Vivier , Max Filippov , Yanan Wang , Marek Vasut , Stafford Horne , Peter Maydell , Daniel Henrique Barboza , Palmer Dabbelt , Taylor Simpson , Marcel Apfelbaum , Alexandre Iooss , Chris Wulff , Richard Henderson , Eduardo Habkost , Song Gao , Mark Cave-Ayland , =?UTF-8?Q?C=c3=a9dric_Le_Goater?= , Artyom Tarasenko , Paolo Bonzini , qemu-riscv@nongnu.org, qemu-s390x@nongnu.org, Alistair Francis , "Edgar E. Iglesias" , Bastian Koppelmann , Jiaxun Yang , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org References: <20230105164320.2164095-1-alex.bennee@linaro.org> <20230105164320.2164095-20-alex.bennee@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230105164320.2164095-20-alex.bennee@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.939, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 17:30:56 -0000 On 5/1/23 17:43, Alex Bennée wrote: > These inline helpers are all used by target specific code so move them > out of the general header so we don't needlessly pollute the rest of > the API with target specific stuff. > > Note we have to include cpu.h in semihosting as it was relying on a > side effect before. > > Signed-off-by: Alex Bennée > --- > include/exec/gdbstub.h | 86 --------------------- > include/gdbstub/helpers.h | 103 +++++++++++++++++++++++++ > semihosting/syscalls.c | 1 + > target/alpha/gdbstub.c | 2 +- > target/arm/gdbstub.c | 1 + > target/arm/gdbstub64.c | 2 +- > target/arm/helper-a64.c | 2 +- > target/arm/m_helper.c | 2 +- > target/avr/gdbstub.c | 2 +- > target/cris/gdbstub.c | 2 +- > target/hexagon/gdbstub.c | 2 +- > target/hppa/gdbstub.c | 2 +- > target/i386/gdbstub.c | 2 +- > target/i386/whpx/whpx-all.c | 2 +- > target/loongarch/gdbstub.c | 1 + > target/m68k/gdbstub.c | 2 +- > target/m68k/helper.c | 1 + > target/m68k/m68k-semi.c | 1 + > target/microblaze/gdbstub.c | 2 +- > target/mips/gdbstub.c | 2 +- > target/mips/tcg/sysemu/mips-semi.c | 1 + > target/nios2/cpu.c | 2 +- > target/nios2/nios2-semi.c | 1 + > target/openrisc/gdbstub.c | 2 +- > target/openrisc/interrupt.c | 2 +- > target/openrisc/mmu.c | 2 +- > target/ppc/cpu_init.c | 2 +- > target/ppc/gdbstub.c | 1 + > target/riscv/gdbstub.c | 1 + > target/rx/gdbstub.c | 2 +- > target/s390x/gdbstub.c | 1 + > target/s390x/helper.c | 2 +- > target/sh4/gdbstub.c | 2 +- > target/sparc/gdbstub.c | 2 +- > target/tricore/gdbstub.c | 2 +- > target/xtensa/core-dc232b.c | 2 +- > target/xtensa/core-dc233c.c | 2 +- > target/xtensa/core-de212.c | 2 +- > target/xtensa/core-de233_fpu.c | 2 +- > target/xtensa/core-dsp3400.c | 2 +- > target/xtensa/core-fsf.c | 2 +- > target/xtensa/core-lx106.c | 2 +- > target/xtensa/core-sample_controller.c | 2 +- > target/xtensa/core-test_kc705_be.c | 2 +- > target/xtensa/core-test_mmuhifi_c3.c | 2 +- > target/xtensa/gdbstub.c | 2 +- > target/xtensa/helper.c | 2 +- > 47 files changed, 148 insertions(+), 121 deletions(-) > create mode 100644 include/gdbstub/helpers.h Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 05 14:05:52 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDVYm-0001G4-8v for mharc-qemu-riscv@gnu.org; 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Iglesias" , Bastian Koppelmann , Jiaxun Yang , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Bin Meng , Mahmoud Mandour , David Gibson , Yoshinori Sato , Xiaojuan Yang , qemu-arm@nongnu.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::b32; envelope-from=jcmvbkbc@gmail.com; helo=mail-yb1-xb32.google.com X-Spam_score_int: -5 X-Spam_score: -0.6 X-Spam_bar: / X-Spam_report: (-0.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FROM_LOCAL_NOVOWEL=0.5, HK_RANDOM_ENVFROM=0.001, HK_RANDOM_FROM=0.999, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 05 Jan 2023 19:05:51 -0000 On Thu, Jan 5, 2023 at 8:51 AM Alex Benn=C3=A9e wr= ote: > > These inline helpers are all used by target specific code so move them > out of the general header so we don't needlessly pollute the rest of > the API with target specific stuff. > > Note we have to include cpu.h in semihosting as it was relying on a > side effect before. > > Signed-off-by: Alex Benn=C3=A9e > --- > target/xtensa/core-dc232b.c | 2 +- > target/xtensa/core-dc233c.c | 2 +- > target/xtensa/core-de212.c | 2 +- > target/xtensa/core-de233_fpu.c | 2 +- > target/xtensa/core-dsp3400.c | 2 +- > target/xtensa/core-fsf.c | 2 +- > target/xtensa/core-lx106.c | 2 +- > target/xtensa/core-sample_controller.c | 2 +- > target/xtensa/core-test_kc705_be.c | 2 +- > target/xtensa/core-test_mmuhifi_c3.c | 2 +- > target/xtensa/gdbstub.c | 2 +- > target/xtensa/helper.c | 2 +- Please update the target/xtensa/import_core.sh as well. --=20 Thanks. -- Max From MAILER-DAEMON Fri Jan 06 02:56:56 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDhay-0007ky-1Z for mharc-qemu-riscv@gnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=ACxHmhXqM9tBrGCPxU6JCLt/VIu1J8zYpocNI9eO7O0=; b=g73VmEgXxmQodDcAqWwfRxELKJ867Ji9GvA6M9BR9d37ruGP60PrQ3GU/QK4NeIIMx L1CbP2jxBFHYbXTTl/IBYv47xv7IVbygvW8uwW+18Fv2NbobbKIfnMZ+dsJ3+TOqCtHB IhZkeD0puoyldGexqnGA5Vn02dUB+Qq90xVCRnsD00z3rn3v7Z5hPwicMiKDhZrb3SI5 pVSaZSvgZ568zu2uZFpWW3GxqyOgv2E5OfEod9LHEhE9m0ZVHbinkxyjUCI8UhWFCyu+ qu3bxkILITxTzUF8Odt32wiAXOv8yO6p8ittRkEL5c4pL9G5bvQQa7Z95du/pdIloC1G CfHw== X-Gm-Message-State: AFqh2kqcDU5/yh8w3suiRkpZGuJ+sDgwzFXk0aq9xdWKDAZWQ/RWzbjA BuNHpwf5JEBkMIZeZiPnPhe9J4NIDq4Ne/kh4mSSJg== X-Google-Smtp-Source: AMrXdXsMt2sCSkE336M+KMQX+fPI+Sj5tOVsys9pNq6r6W2AcNsCjdzZGSqbQrXwJYoqFvQOFYERopiuJJCtYFg/tS8= X-Received: by 2002:a05:600c:1e0d:b0:3d1:e710:9905 with SMTP id ay13-20020a05600c1e0d00b003d1e7109905mr2094686wmb.81.1672991804156; Thu, 05 Jan 2023 23:56:44 -0800 (PST) MIME-Version: 1.0 References: <20221212102250.3365948-1-alexghiti@rivosinc.com> In-Reply-To: From: Alexandre Ghiti Date: Fri, 6 Jan 2023 08:56:33 +0100 Message-ID: Subject: Re: [PATCH v4] riscv: Allow user to set the satp mode To: Frank Chang Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Jan 2023 07:56:51 -0000 On Fri, Dec 16, 2022 at 2:03 PM Alexandre Ghiti wrote: > > Hi Frank, > > On Fri, Dec 16, 2022 at 10:32 AM Frank Chang wrote: > > > > Hi Alexandre, > > > > Thanks for the contribution. This is really helpful. > > > > It seems like if we want to specify the SATP mode for the "named" CPUs, > > we have to do, e.g.: > > cpu->cfg.satp_mode.map |= (1 << idx_satp_mode_from_str("sv39")); > > in each CPU's init function. > > > > Can we add another helper function to wrap this for the "named" CPUs? > > Yes sure, I'll add some helpers for the bit operations in general, > that will be cleaner. And I'll set the default satp mode for the > current cpus in each cpu init function too. > > Thanks for your remarks, > > Alex > > > > > Regards, > > Frank Chang > > > > > > On Mon, Dec 12, 2022 at 6:23 PM Alexandre Ghiti wrote: > >> > >> RISC-V specifies multiple sizes for addressable memory and Linux probes for > >> the machine's support at startup via the satp CSR register (done in > >> csr.c:validate_vm). > >> > >> As per the specification, sv64 must support sv57, which in turn must > >> support sv48...etc. So we can restrict machine support by simply setting the > >> "highest" supported mode and the bare mode is always supported. > >> > >> You can set the satp mode using the new properties "mbare", "sv32", > >> "sv39", "sv48", "sv57" and "sv64" as follows: > >> -cpu rv64,sv57=on # Linux will boot using sv57 scheme > >> -cpu rv64,sv39=on # Linux will boot using sv39 scheme > >> > >> We take the highest level set by the user: > >> -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme > >> > >> We make sure that invalid configurations are rejected: > >> -cpu rv64,sv32=on # Can't enable 32-bit satp mode in 64-bit > >> -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are > >> # enabled > >> > >> We accept "redundant" configurations: > >> -cpu rv64,sv48=on,sv57=off # sv39 must be supported if higher modes are > >> > >> In addition, we now correctly set the device-tree entry 'mmu-type' using > >> those new properties. > >> > >> Co-Developed-by: Ludovic Henry > >> Signed-off-by: Ludovic Henry > >> Signed-off-by: Alexandre Ghiti > >> --- > >> v4: > >> - Use custom boolean properties instead of OnOffAuto properties, based > >> on ARMVQMap, as suggested by Andrew > >> > >> v3: > >> - Free sv_name as pointed by Bin > >> - Replace satp-mode with boolean properties as suggested by Andrew > >> - Removed RB from Atish as the patch considerably changed > >> > >> v2: > >> - Use error_setg + return as suggested by Alistair > >> - Add RB from Atish > >> - Fixed checkpatch issues missed in v1 > >> - Replaced Ludovic email address with the rivos one > >> > >> hw/riscv/virt.c | 20 +++-- > >> target/riscv/cpu.c | 217 +++++++++++++++++++++++++++++++++++++++++++-- > >> target/riscv/cpu.h | 25 ++++++ > >> target/riscv/csr.c | 13 ++- > >> 4 files changed, 256 insertions(+), 19 deletions(-) > >> > >> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > >> index a5bc7353b4..9bb5ba7366 100644 > >> --- a/hw/riscv/virt.c > >> +++ b/hw/riscv/virt.c > >> @@ -228,7 +228,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > >> int cpu; > >> uint32_t cpu_phandle; > >> MachineState *mc = MACHINE(s); > >> - char *name, *cpu_name, *core_name, *intc_name; > >> + uint8_t satp_mode_max; > >> + char *name, *cpu_name, *core_name, *intc_name, *sv_name; > >> > >> for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { > >> cpu_phandle = (*phandle)++; > >> @@ -236,14 +237,15 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > >> cpu_name = g_strdup_printf("/cpus/cpu@%d", > >> s->soc[socket].hartid_base + cpu); > >> qemu_fdt_add_subnode(mc->fdt, cpu_name); > >> - if (riscv_feature(&s->soc[socket].harts[cpu].env, > >> - RISCV_FEATURE_MMU)) { > >> - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > >> - (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); > >> - } else { > >> - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > >> - "riscv,none"); > >> - } > >> + > >> + satp_mode_max = satp_mode_max_from_map( > >> + s->soc[socket].harts[cpu].cfg.satp_mode.map, > >> + is_32_bit); > >> + sv_name = g_strdup_printf("riscv,%s", > >> + satp_mode_str(satp_mode_max, is_32_bit)); > >> + qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", sv_name); > >> + g_free(sv_name); > >> + > >> name = riscv_isa_string(&s->soc[socket].harts[cpu]); > >> qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); > >> g_free(name); > >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > >> index d14e95c9dc..639231ce2e 100644 > >> --- a/target/riscv/cpu.c > >> +++ b/target/riscv/cpu.c > >> @@ -27,6 +27,7 @@ > >> #include "time_helper.h" > >> #include "exec/exec-all.h" > >> #include "qapi/error.h" > >> +#include "qapi/visitor.h" > >> #include "qemu/error-report.h" > >> #include "hw/qdev-properties.h" > >> #include "migration/vmstate.h" > >> @@ -199,7 +200,7 @@ static const char * const riscv_intr_names[] = { > >> "reserved" > >> }; > >> > >> -static void register_cpu_props(DeviceState *dev); > >> +static void register_cpu_props(Object *obj); > >> > >> const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) > >> { > >> @@ -237,7 +238,7 @@ static void riscv_any_cpu_init(Object *obj) > >> set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > >> #endif > >> set_priv_version(env, PRIV_VERSION_1_12_0); > >> - register_cpu_props(DEVICE(obj)); > >> + register_cpu_props(obj); > >> } > >> > >> #if defined(TARGET_RISCV64) > >> @@ -246,7 +247,7 @@ static void rv64_base_cpu_init(Object *obj) > >> CPURISCVState *env = &RISCV_CPU(obj)->env; > >> /* We set this in the realise function */ > >> set_misa(env, MXL_RV64, 0); > >> - register_cpu_props(DEVICE(obj)); > >> + register_cpu_props(obj); > >> /* Set latest version of privileged specification */ > >> set_priv_version(env, PRIV_VERSION_1_12_0); > >> } > >> @@ -279,7 +280,7 @@ static void rv128_base_cpu_init(Object *obj) > >> CPURISCVState *env = &RISCV_CPU(obj)->env; > >> /* We set this in the realise function */ > >> set_misa(env, MXL_RV128, 0); > >> - register_cpu_props(DEVICE(obj)); > >> + register_cpu_props(obj); > >> /* Set latest version of privileged specification */ > >> set_priv_version(env, PRIV_VERSION_1_12_0); > >> } > >> @@ -289,7 +290,7 @@ static void rv32_base_cpu_init(Object *obj) > >> CPURISCVState *env = &RISCV_CPU(obj)->env; > >> /* We set this in the realise function */ > >> set_misa(env, MXL_RV32, 0); > >> - register_cpu_props(DEVICE(obj)); > >> + register_cpu_props(obj); > >> /* Set latest version of privileged specification */ > >> set_priv_version(env, PRIV_VERSION_1_12_0); > >> } > >> @@ -342,7 +343,7 @@ static void riscv_host_cpu_init(Object *obj) > >> #elif defined(TARGET_RISCV64) > >> set_misa(env, MXL_RV64, 0); > >> #endif > >> - register_cpu_props(DEVICE(obj)); > >> + register_cpu_props(obj); > >> } > >> #endif > >> > >> @@ -612,6 +613,71 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > >> } > >> } > >> > >> +#define OFFSET_SATP_MODE_64 16 > >> + > >> +static uint8_t idx_satp_mode_from_str(const char *satp_mode_str) > >> +{ > >> + if (!strncmp(satp_mode_str, "mbare", 5)) { > >> + return VM_1_10_MBARE; > >> + } > >> + > >> + if (!strncmp(satp_mode_str, "sv32", 4)) { > >> + return VM_1_10_SV32; > >> + } > >> + > >> + if (!strncmp(satp_mode_str, "sv39", 4)) { > >> + return VM_1_10_SV39 + OFFSET_SATP_MODE_64; > >> + } > >> + > >> + if (!strncmp(satp_mode_str, "sv48", 4)) { > >> + return VM_1_10_SV48 + OFFSET_SATP_MODE_64; > >> + } > >> + > >> + if (!strncmp(satp_mode_str, "sv57", 4)) { > >> + return VM_1_10_SV57 + OFFSET_SATP_MODE_64; > >> + } > >> + > >> + if (!strncmp(satp_mode_str, "sv64", 4)) { > >> + return VM_1_10_SV64 + OFFSET_SATP_MODE_64; > >> + } > >> + > >> + /* Will never get there */ > >> + return -1; > >> +} > >> + > >> +uint8_t satp_mode_max_from_map(uint32_t map, bool is_32_bit) > >> +{ > >> + return is_32_bit ? > >> + (31 - __builtin_clz(map & 0xFFFF)) : (31 - __builtin_clz(map >> 16)); > >> +} > >> + > >> +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > >> +{ > >> + if (is_32_bit) { > >> + switch (satp_mode) { > >> + case VM_1_10_SV32: > >> + return "sv32"; > >> + case VM_1_10_MBARE: > >> + return "none"; > >> + } > >> + } else { > >> + switch (satp_mode) { > >> + case VM_1_10_SV64: > >> + return "sv64"; > >> + case VM_1_10_SV57: > >> + return "sv57"; > >> + case VM_1_10_SV48: > >> + return "sv48"; > >> + case VM_1_10_SV39: > >> + return "sv39"; > >> + case VM_1_10_MBARE: > >> + return "none"; > >> + } > >> + } > >> + > >> + return NULL; > >> +} > >> + > >> static void riscv_cpu_realize(DeviceState *dev, Error **errp) > >> { > >> CPUState *cs = CPU(dev); > >> @@ -907,6 +973,30 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > >> } > >> #endif > >> > >> + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > >> + > >> + /* > >> + * If unset by both the user and the cpu, we fallback to sv32 for 32-bit > >> + * or sv57 for 64-bit when a MMU is present, and bare otherwise. > >> + */ > >> + if (cpu->cfg.satp_mode.map == 0) { > >> + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > >> + if (rv32) { > >> + cpu->cfg.satp_mode.map |= (1 << idx_satp_mode_from_str("sv32")); > >> + } else { > >> + cpu->cfg.satp_mode.map |= (1 << idx_satp_mode_from_str("sv57")); > >> + } > >> + } else { > >> + cpu->cfg.satp_mode.map |= (1 << idx_satp_mode_from_str("mbare")); > >> + } > >> + } > >> + > >> + riscv_cpu_finalize_features(cpu, &local_err); > >> + if (local_err != NULL) { > >> + error_propagate(errp, local_err); > >> + return; > >> + } > >> + > >> riscv_cpu_register_gdb_regs_for_features(cs); > >> > >> qemu_init_vcpu(cs); > >> @@ -915,6 +1005,115 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > >> mcc->parent_realize(dev, errp); > >> } > >> > >> +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, > >> + void *opaque, Error **errp) > >> +{ > >> + RISCVSATPMap *satp_map = opaque; > >> + uint8_t idx_satp = idx_satp_mode_from_str(name); > >> + bool value; > >> + > >> + value = (satp_map->map & (1 << idx_satp)); > >> + > >> + visit_type_bool(v, name, &value, errp); > >> +} > >> + > >> +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, > >> + void *opaque, Error **errp) > >> +{ > >> + RISCVSATPMap *satp_map = opaque; > >> + uint8_t idx_satp = idx_satp_mode_from_str(name); > >> + bool value; > >> + > >> + if (!visit_type_bool(v, name, &value, errp)) { > >> + return; > >> + } > >> + > >> + if (value) { > >> + satp_map->map |= 1 << idx_satp; > >> + } > >> + > >> + satp_map->init |= 1 << idx_satp; > >> +} > >> + > >> +static void riscv_add_satp_mode_properties(Object *obj) > >> +{ > >> + RISCVCPU *cpu = RISCV_CPU(obj); > >> + > >> + object_property_add(obj, "mbare", "bool", cpu_riscv_get_satp, > >> + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > >> + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, > >> + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > >> + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, > >> + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > >> + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, > >> + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > >> + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, > >> + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > >> + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, > >> + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > >> +} > >> + > >> +#define error_append_or_setg(errp, str, ...) ({ \ > >> + if (*errp) \ > >> + error_append_hint(errp, str"\n", ##__VA_ARGS__);\ > >> + else \ > >> + error_setg(errp, str, ##__VA_ARGS__); \ > >> + }) > >> + > >> +void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > >> +{ > >> + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > >> + > >> + /* Get rid of 32-bit/64-bit incompatibility */ > >> + if (rv32) { > >> + if (cpu->cfg.satp_mode.map >= (1 << OFFSET_SATP_MODE_64)) > >> + error_append_or_setg(errp, "cannot enable 64-bit satp modes " > >> + "(sv39/sv48/sv57/sv64) if cpu is in 32-bit " > >> + "mode"); > >> + } else { > >> + if (cpu->cfg.satp_mode.map & (1 << VM_1_10_SV32)) > >> + error_append_or_setg(errp, "cannot enable 32-bit satp mode (sv32) " > >> + "if cpu is in 64-bit mode"); > >> + } > >> + > >> + /* > >> + * Then make sure the user did not ask for an invalid configuration as per > >> + * the specification. > >> + */ > >> + if (rv32) { > >> + if (cpu->cfg.satp_mode.map & (1 << VM_1_10_SV32)) { > >> + if (!(cpu->cfg.satp_mode.map & (1 << VM_1_10_MBARE)) && > >> + (cpu->cfg.satp_mode.init & (1 << VM_1_10_MBARE))) > >> + error_append_or_setg(errp, "cannot disable mbare satp mode if " > >> + "sv32 is enabled"); > >> + } > >> + } else { > >> + uint8_t satp_mode_max; > >> + > >> + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map, false); > >> + > >> + for (int i = satp_mode_max - 1; i >= 0; --i) { > >> + if (!(cpu->cfg.satp_mode.map & (1 << (i + OFFSET_SATP_MODE_64))) && > >> + (cpu->cfg.satp_mode.init & (1 << (i + OFFSET_SATP_MODE_64)))) > >> + error_append_or_setg(errp, "cannot disable %s satp mode if %s " > >> + "is enabled", > >> + satp_mode_str(i, false), > >> + satp_mode_str(satp_mode_max, false)); > >> + } > >> + } > >> +} > >> + > >> +void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > >> +{ > >> + Error *local_err = NULL; > >> + > >> + riscv_cpu_satp_mode_finalize(cpu, &local_err); > >> + if (local_err != NULL) { > >> + error_propagate(errp, local_err); > >> + return; > >> + } > >> +} > >> + > >> #ifndef CONFIG_USER_ONLY > >> static void riscv_cpu_set_irq(void *opaque, int irq, int level) > >> { > >> @@ -1070,13 +1269,16 @@ static Property riscv_cpu_extensions[] = { > >> DEFINE_PROP_END_OF_LIST(), > >> }; > >> > >> -static void register_cpu_props(DeviceState *dev) > >> +static void register_cpu_props(Object *obj) > >> { > >> Property *prop; > >> + DeviceState *dev = DEVICE(obj); > >> > >> for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > >> qdev_property_add_static(dev, prop); > >> } > >> + > >> + riscv_add_satp_mode_properties(obj); > >> } > >> > >> static Property riscv_cpu_properties[] = { > >> @@ -1094,6 +1296,7 @@ static Property riscv_cpu_properties[] = { > >> > >> DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), > >> DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), > >> + > >> DEFINE_PROP_END_OF_LIST(), > >> }; > >> > >> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > >> index 3a9e25053f..1717b33321 100644 > >> --- a/target/riscv/cpu.h > >> +++ b/target/riscv/cpu.h > >> @@ -27,6 +27,7 @@ > >> #include "qom/object.h" > >> #include "qemu/int128.h" > >> #include "cpu_bits.h" > >> +#include "qapi/qapi-types-common.h" > >> > >> #define TCG_GUEST_DEFAULT_MO 0 > >> > >> @@ -407,6 +408,22 @@ struct RISCVCPUClass { > >> DeviceReset parent_reset; > >> }; > >> > >> +/* > >> + * map and init are divided into two 16bit bitmaps: the upper one is for rv64 > >> + * and the lower one is for rv32, this is because the value for sv32 (ie. 1) > >> + * may be reused later for another purpose for rv64 (see the specification which > >> + * states that it is "reserved for standard use"). > >> + * > >> + * In a 16bit bitmap in map, the most significant set bit is the maximum > >> + * satp mode that is supported. > >> + * > >> + * Both 16bit bitmaps in init are used to make sure the user selected a correct > >> + * combination as per the specification. > >> + */ > >> +typedef struct { > >> + uint32_t map, init; > >> +} RISCVSATPMap; > >> + > >> struct RISCVCPUConfig { > >> bool ext_i; > >> bool ext_e; > >> @@ -480,6 +497,8 @@ struct RISCVCPUConfig { > >> bool debug; > >> > >> bool short_isa_string; > >> + > >> + RISCVSATPMap satp_mode; > >> }; > >> > >> typedef struct RISCVCPUConfig RISCVCPUConfig; > >> @@ -789,4 +808,10 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); > >> > >> void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); > >> > >> +uint8_t satp_mode_max_from_map(uint32_t map, bool is_32_bit); > >> +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); > >> + > >> +void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp); > >> +void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); > >> + > >> #endif /* RISCV_CPU_H */ > >> diff --git a/target/riscv/csr.c b/target/riscv/csr.c > >> index 5c9a7ee287..5c732653b2 100644 > >> --- a/target/riscv/csr.c > >> +++ b/target/riscv/csr.c > >> @@ -1109,10 +1109,17 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, > >> > >> static int validate_vm(CPURISCVState *env, target_ulong vm) > >> { > >> - if (riscv_cpu_mxl(env) == MXL_RV32) { > >> - return valid_vm_1_10_32[vm & 0xf]; > >> + uint8_t satp_mode_max; > >> + RISCVCPU *cpu = RISCV_CPU(env_cpu(env)); > >> + bool is_32_bit = riscv_cpu_mxl(env) == MXL_RV32; > >> + > >> + vm &= 0xf; > >> + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map, is_32_bit); > >> + > >> + if (is_32_bit) { > >> + return valid_vm_1_10_32[vm] && (vm <= satp_mode_max); > >> } else { > >> - return valid_vm_1_10_64[vm & 0xf]; > >> + return valid_vm_1_10_64[vm] && (vm <= satp_mode_max); > >> } > >> } > >> > >> -- > >> 2.37.2 > >> > >> @Andrew: Please let me know when you have some cycles to review this, Thanks, Alex From MAILER-DAEMON Fri Jan 06 03:53:41 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDiTt-0003nm-Pk for mharc-qemu-riscv@gnu.org; Fri, 06 Jan 2023 03:53:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDiTs-0003ls-3C for qemu-riscv@nongnu.org; Fri, 06 Jan 2023 03:53:40 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDiTq-0001ZC-Bu for qemu-riscv@nongnu.org; Fri, 06 Jan 2023 03:53:39 -0500 Received: by mail-wm1-x333.google.com with SMTP id m26-20020a05600c3b1a00b003d9811fcaafso607670wms.5 for ; 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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id j1-20020a05600c1c0100b003cfaae07f68sm6031470wms.17.2023.01.06.00.53.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jan 2023 00:53:35 -0800 (PST) Date: Fri, 6 Jan 2023 09:53:34 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Frank Chang , Palmer Dabbelt , Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Subject: Re: [PATCH v4] riscv: Allow user to set the satp mode Message-ID: <20230106085334.vz4kbm3lleut7c6m@orel> References: <20221212102250.3365948-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Jan 2023 08:53:40 -0000 On Fri, Jan 06, 2023 at 08:56:33AM +0100, Alexandre Ghiti wrote: > On Fri, Dec 16, 2022 at 2:03 PM Alexandre Ghiti wrote: ... > @Andrew: Please let me know when you have some cycles to review this, I'll try to get to this yet today. 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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id t11-20020a5d49cb000000b002420d51e581sm1550042wrs.67.2023.01.06.08.30.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Jan 2023 08:30:46 -0800 (PST) Date: Fri, 6 Jan 2023 17:30:45 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Subject: Re: [PATCH v4] riscv: Allow user to set the satp mode Message-ID: <20230106163045.jerqbds3mgi3ri4e@orel> References: <20221212102250.3365948-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221212102250.3365948-1-alexghiti@rivosinc.com> Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Jan 2023 16:30:57 -0000 On Mon, Dec 12, 2022 at 11:22:50AM +0100, Alexandre Ghiti wrote: > RISC-V specifies multiple sizes for addressable memory and Linux probes for > the machine's support at startup via the satp CSR register (done in > csr.c:validate_vm). > > As per the specification, sv64 must support sv57, which in turn must > support sv48...etc. So we can restrict machine support by simply setting the > "highest" supported mode and the bare mode is always supported. > > You can set the satp mode using the new properties "mbare", "sv32", > "sv39", "sv48", "sv57" and "sv64" as follows: > -cpu rv64,sv57=on # Linux will boot using sv57 scheme > -cpu rv64,sv39=on # Linux will boot using sv39 scheme > > We take the highest level set by the user: > -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme > > We make sure that invalid configurations are rejected: > -cpu rv64,sv32=on # Can't enable 32-bit satp mode in 64-bit > -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are > # enabled > > We accept "redundant" configurations: > -cpu rv64,sv48=on,sv57=off # sv39 must be supported if higher modes are ^ from this #, it looks like a copy+paste mistake > > In addition, we now correctly set the device-tree entry 'mmu-type' using > those new properties. > > Co-Developed-by: Ludovic Henry > Signed-off-by: Ludovic Henry > Signed-off-by: Alexandre Ghiti > --- > v4: > - Use custom boolean properties instead of OnOffAuto properties, based > on ARMVQMap, as suggested by Andrew > > v3: > - Free sv_name as pointed by Bin > - Replace satp-mode with boolean properties as suggested by Andrew > - Removed RB from Atish as the patch considerably changed > > v2: > - Use error_setg + return as suggested by Alistair > - Add RB from Atish > - Fixed checkpatch issues missed in v1 > - Replaced Ludovic email address with the rivos one > > hw/riscv/virt.c | 20 +++-- > target/riscv/cpu.c | 217 +++++++++++++++++++++++++++++++++++++++++++-- > target/riscv/cpu.h | 25 ++++++ > target/riscv/csr.c | 13 ++- > 4 files changed, 256 insertions(+), 19 deletions(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index a5bc7353b4..9bb5ba7366 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -228,7 +228,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > int cpu; > uint32_t cpu_phandle; > MachineState *mc = MACHINE(s); > - char *name, *cpu_name, *core_name, *intc_name; > + uint8_t satp_mode_max; > + char *name, *cpu_name, *core_name, *intc_name, *sv_name; > > for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { > cpu_phandle = (*phandle)++; > @@ -236,14 +237,15 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > cpu_name = g_strdup_printf("/cpus/cpu@%d", > s->soc[socket].hartid_base + cpu); > qemu_fdt_add_subnode(mc->fdt, cpu_name); > - if (riscv_feature(&s->soc[socket].harts[cpu].env, > - RISCV_FEATURE_MMU)) { > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > - (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); > - } else { > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > - "riscv,none"); > - } > + > + satp_mode_max = satp_mode_max_from_map( > + s->soc[socket].harts[cpu].cfg.satp_mode.map, > + is_32_bit); > + sv_name = g_strdup_printf("riscv,%s", > + satp_mode_str(satp_mode_max, is_32_bit)); > + qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", sv_name); > + g_free(sv_name); > + > name = riscv_isa_string(&s->soc[socket].harts[cpu]); > qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); > g_free(name); > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index d14e95c9dc..639231ce2e 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -27,6 +27,7 @@ > #include "time_helper.h" > #include "exec/exec-all.h" > #include "qapi/error.h" > +#include "qapi/visitor.h" > #include "qemu/error-report.h" > #include "hw/qdev-properties.h" > #include "migration/vmstate.h" > @@ -199,7 +200,7 @@ static const char * const riscv_intr_names[] = { > "reserved" > }; > > -static void register_cpu_props(DeviceState *dev); > +static void register_cpu_props(Object *obj); Please do this dev -> obj change in a separate ("no functional change intended") patch. > > const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) > { > @@ -237,7 +238,7 @@ static void riscv_any_cpu_init(Object *obj) > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > #endif > set_priv_version(env, PRIV_VERSION_1_12_0); > - register_cpu_props(DEVICE(obj)); > + register_cpu_props(obj); > } > > #if defined(TARGET_RISCV64) > @@ -246,7 +247,7 @@ static void rv64_base_cpu_init(Object *obj) > CPURISCVState *env = &RISCV_CPU(obj)->env; > /* We set this in the realise function */ > set_misa(env, MXL_RV64, 0); > - register_cpu_props(DEVICE(obj)); > + register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > } > @@ -279,7 +280,7 @@ static void rv128_base_cpu_init(Object *obj) > CPURISCVState *env = &RISCV_CPU(obj)->env; > /* We set this in the realise function */ > set_misa(env, MXL_RV128, 0); > - register_cpu_props(DEVICE(obj)); > + register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > } > @@ -289,7 +290,7 @@ static void rv32_base_cpu_init(Object *obj) > CPURISCVState *env = &RISCV_CPU(obj)->env; > /* We set this in the realise function */ > set_misa(env, MXL_RV32, 0); > - register_cpu_props(DEVICE(obj)); > + register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > } > @@ -342,7 +343,7 @@ static void riscv_host_cpu_init(Object *obj) > #elif defined(TARGET_RISCV64) > set_misa(env, MXL_RV64, 0); > #endif > - register_cpu_props(DEVICE(obj)); > + register_cpu_props(obj); > } > #endif > > @@ -612,6 +613,71 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > } > } > > +#define OFFSET_SATP_MODE_64 16 It's not clear to me why we need this offset. Looking below it seems to be for helping to distinguish rv64-only modes when sanity checking modes for rv32, but can't we just do that with valid_vm_1_10_32/64[]? > + > +static uint8_t idx_satp_mode_from_str(const char *satp_mode_str) nit: I'd drop the 'idx_' prefix. > +{ > + if (!strncmp(satp_mode_str, "mbare", 5)) { > + return VM_1_10_MBARE; > + } Do we need a property for mbare? It should always be present, no? > + > + if (!strncmp(satp_mode_str, "sv32", 4)) { > + return VM_1_10_SV32; > + } > + > + if (!strncmp(satp_mode_str, "sv39", 4)) { > + return VM_1_10_SV39 + OFFSET_SATP_MODE_64; > + } > + > + if (!strncmp(satp_mode_str, "sv48", 4)) { > + return VM_1_10_SV48 + OFFSET_SATP_MODE_64; > + } > + > + if (!strncmp(satp_mode_str, "sv57", 4)) { > + return VM_1_10_SV57 + OFFSET_SATP_MODE_64; > + } > + > + if (!strncmp(satp_mode_str, "sv64", 4)) { > + return VM_1_10_SV64 + OFFSET_SATP_MODE_64; > + } > + > + /* Will never get there */ > + return -1; g_assert_not_reached() > +} > + > +uint8_t satp_mode_max_from_map(uint32_t map, bool is_32_bit) We shouldn't need is_32_bit. > +{ > + return is_32_bit ? > + (31 - __builtin_clz(map & 0xFFFF)) : (31 - __builtin_clz(map >> 16)); __builtin_clz is undefined when its input is zero, so we should either use the clz32() wrapper or handle zero ourselves. How about { /* * map is always valid when this is called. It's either zero or * only valid mode bits are set. */ return map ? __builtin_clz(map) : 0; } > +} > + > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) This function is not used outside this file, so can be static. Since we pass is_32_bit in here, then I don't think we need OFFSET_SATP_MODE_64 > +{ > + if (is_32_bit) { > + switch (satp_mode) { > + case VM_1_10_SV32: > + return "sv32"; > + case VM_1_10_MBARE: > + return "none"; > + } > + } else { > + switch (satp_mode) { > + case VM_1_10_SV64: > + return "sv64"; > + case VM_1_10_SV57: > + return "sv57"; > + case VM_1_10_SV48: > + return "sv48"; > + case VM_1_10_SV39: > + return "sv39"; > + case VM_1_10_MBARE: > + return "none"; > + } > + } > + > + return NULL; g_assert_not_reached() > +} > + > static void riscv_cpu_realize(DeviceState *dev, Error **errp) > { > CPUState *cs = CPU(dev); > @@ -907,6 +973,30 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > #endif > > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > + > + /* > + * If unset by both the user and the cpu, we fallback to sv32 for 32-bit > + * or sv57 for 64-bit when a MMU is present, and bare otherwise. > + */ > + if (cpu->cfg.satp_mode.map == 0) { > + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > + if (rv32) { > + cpu->cfg.satp_mode.map |= (1 << idx_satp_mode_from_str("sv32")); > + } else { > + cpu->cfg.satp_mode.map |= (1 << idx_satp_mode_from_str("sv57")); > + } > + } else { > + cpu->cfg.satp_mode.map |= (1 << idx_satp_mode_from_str("mbare")); If we can drop the mbare property then it's implied and we don't need to add it to the map. > + } > + } > + > + riscv_cpu_finalize_features(cpu, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > + } > + > riscv_cpu_register_gdb_regs_for_features(cs); > > qemu_init_vcpu(cs); > @@ -915,6 +1005,115 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > mcc->parent_realize(dev, errp); > } > > +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + RISCVSATPMap *satp_map = opaque; > + uint8_t idx_satp = idx_satp_mode_from_str(name); > + bool value; > + > + value = (satp_map->map & (1 << idx_satp)); > + > + visit_type_bool(v, name, &value, errp); > +} > + > +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + RISCVSATPMap *satp_map = opaque; > + uint8_t idx_satp = idx_satp_mode_from_str(name); > + bool value; > + > + if (!visit_type_bool(v, name, &value, errp)) { > + return; > + } > + > + if (value) { > + satp_map->map |= 1 << idx_satp; > + } If the user does e.g. sv32=on,sv32=off, which is pointless but valid, then unless we have an else { satp_map->map &= ~(1 << idx_satp); } we won't properly disable sv32. It's best to use deposit32. > + > + satp_map->init |= 1 << idx_satp; > +} > + > +static void riscv_add_satp_mode_properties(Object *obj) > +{ > + RISCVCPU *cpu = RISCV_CPU(obj); > + > + object_property_add(obj, "mbare", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > +} > + > +#define error_append_or_setg(errp, str, ...) ({ \ > + if (*errp) \ > + error_append_hint(errp, str"\n", ##__VA_ARGS__);\ > + else \ > + error_setg(errp, str, ##__VA_ARGS__); \ > + }) Missing {} on the if/else and the if should be if (errp && *errp), but I'd rather not have this macro at all. Why not just do error_setg and return on the first error? I realize the user will only get one error per try, but why not, at least they won't get confused as to what to fix each try. > + > +void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) This is only called from one place in the same file, so it can be static. > +{ > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > + > + /* Get rid of 32-bit/64-bit incompatibility */ > + if (rv32) { > + if (cpu->cfg.satp_mode.map >= (1 << OFFSET_SATP_MODE_64)) Missing {} > + error_append_or_setg(errp, "cannot enable 64-bit satp modes " > + "(sv39/sv48/sv57/sv64) if cpu is in 32-bit " I'd drop the "(sv39/sv48/sv57/sv64)" rather than introduce another place to maintain when the list changes. > + "mode"); > + } else { > + if (cpu->cfg.satp_mode.map & (1 << VM_1_10_SV32)) > + error_append_or_setg(errp, "cannot enable 32-bit satp mode (sv32) " > + "if cpu is in 64-bit mode"); > + } > + > + /* > + * Then make sure the user did not ask for an invalid configuration as per > + * the specification. > + */ > + if (rv32) { > + if (cpu->cfg.satp_mode.map & (1 << VM_1_10_SV32)) { > + if (!(cpu->cfg.satp_mode.map & (1 << VM_1_10_MBARE)) && > + (cpu->cfg.satp_mode.init & (1 << VM_1_10_MBARE))) Missing {} > + error_append_or_setg(errp, "cannot disable mbare satp mode if " > + "sv32 is enabled"); } else if ((cpu->cfg.satp_mode.map & (1 << VM_1_10_MBARE)) && !(cpu->cfg.satp_mode.init & (1 << VM_1_10_MBARE))) { cpu->cfg.satp_mode.map |= (1 << VM_1_10_MBARE); } > + } > + } else { > + uint8_t satp_mode_max; > + > + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map, false); > + > + for (int i = satp_mode_max - 1; i >= 0; --i) { > + if (!(cpu->cfg.satp_mode.map & (1 << (i + OFFSET_SATP_MODE_64))) && > + (cpu->cfg.satp_mode.init & (1 << (i + OFFSET_SATP_MODE_64)))) Missing {} > + error_append_or_setg(errp, "cannot disable %s satp mode if %s " > + "is enabled", > + satp_mode_str(i, false), > + satp_mode_str(satp_mode_max, false)); Same else-if concept needed here. Since I'd think we'd want to populate the map with all the implicit modes. > + } > + } Additionally I'd think we want to try and work valid_vm_1_10_32/64[] checks into this function in order to be sure that map is fully populated with valid bits when we're done. > +} > + > +void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > +{ > + Error *local_err = NULL; > + > + riscv_cpu_satp_mode_finalize(cpu, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > + } > +} > + > #ifndef CONFIG_USER_ONLY > static void riscv_cpu_set_irq(void *opaque, int irq, int level) > { > @@ -1070,13 +1269,16 @@ static Property riscv_cpu_extensions[] = { > DEFINE_PROP_END_OF_LIST(), > }; > > -static void register_cpu_props(DeviceState *dev) > +static void register_cpu_props(Object *obj) > { > Property *prop; > + DeviceState *dev = DEVICE(obj); > > for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > qdev_property_add_static(dev, prop); > } > + > + riscv_add_satp_mode_properties(obj); > } > > static Property riscv_cpu_properties[] = { > @@ -1094,6 +1296,7 @@ static Property riscv_cpu_properties[] = { > > DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), > DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), > + Stray change > DEFINE_PROP_END_OF_LIST(), > }; > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 3a9e25053f..1717b33321 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -27,6 +27,7 @@ > #include "qom/object.h" > #include "qemu/int128.h" > #include "cpu_bits.h" > +#include "qapi/qapi-types-common.h" > > #define TCG_GUEST_DEFAULT_MO 0 > > @@ -407,6 +408,22 @@ struct RISCVCPUClass { > DeviceReset parent_reset; > }; > > +/* > + * map and init are divided into two 16bit bitmaps: the upper one is for rv64 > + * and the lower one is for rv32, this is because the value for sv32 (ie. 1) > + * may be reused later for another purpose for rv64 (see the specification which > + * states that it is "reserved for standard use"). I understand this, but I'm not sure why we can't use the same bit1 for rv32 to mean one thing and for rv64 another. We can have another define for rv64 that is also 1 and valid_vm_1_10_64[] is the authority. > + * > + * In a 16bit bitmap in map, the most significant set bit is the maximum > + * satp mode that is supported. > + * > + * Both 16bit bitmaps in init are used to make sure the user selected a correct > + * combination as per the specification. > + */ > +typedef struct { > + uint32_t map, init; > +} RISCVSATPMap; > + > struct RISCVCPUConfig { > bool ext_i; > bool ext_e; > @@ -480,6 +497,8 @@ struct RISCVCPUConfig { > bool debug; > > bool short_isa_string; > + > + RISCVSATPMap satp_mode; > }; > > typedef struct RISCVCPUConfig RISCVCPUConfig; > @@ -789,4 +808,10 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); > > void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); > > +uint8_t satp_mode_max_from_map(uint32_t map, bool is_32_bit); > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); > + > +void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp); satp_mode_str and riscv_cpu_satp_mode_finalize should be static so they should be dropped from here. > +void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); > + > #endif /* RISCV_CPU_H */ > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 5c9a7ee287..5c732653b2 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1109,10 +1109,17 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, > > static int validate_vm(CPURISCVState *env, target_ulong vm) > { > - if (riscv_cpu_mxl(env) == MXL_RV32) { > - return valid_vm_1_10_32[vm & 0xf]; > + uint8_t satp_mode_max; > + RISCVCPU *cpu = RISCV_CPU(env_cpu(env)); > + bool is_32_bit = riscv_cpu_mxl(env) == MXL_RV32; > + > + vm &= 0xf; > + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map, is_32_bit); > + > + if (is_32_bit) { > + return valid_vm_1_10_32[vm] && (vm <= satp_mode_max); > } else { > - return valid_vm_1_10_64[vm & 0xf]; > + return valid_vm_1_10_64[vm] && (vm <= satp_mode_max); > } > } > > -- > 2.37.2 > Thanks, drew From MAILER-DAEMON Fri Jan 06 12:51:59 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDqsp-0003oU-Pf for mharc-qemu-riscv@gnu.org; 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Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=peter.maydell@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Jan 2023 17:51:54 -0000 On Wed, 4 Jan 2023 at 22:04, Philippe Mathieu-Daud=C3=A9 wrote: > > Paving the road toward heterogeneous QEMU, the limitations of > having a single machine sysbus become more apparent. > > The sysbus_mmio_map() API forces the caller to map a sysbus > device to an address on the system bus (system bus here is > the root MemoryRegion returned by get_system_memory() ). > > This is not practical when each core has its own address > space and group of cores have access to a part of the > peripherals. > > Experimenting with the PFLASH devices. Here the fix is > quite easy, we split the pflash_cfi_register() -- which > does the implicit sysbus mapping -- into an explicit qdev > pflash_cfi_create() followed by the sysbus_mmio_map() call. pflash_cfi_register() is a legacy convenience function. If you don't like the sysbus_mmio_map() it does then you can create, configure, realize and map the device directly. This is what hw/arm/virt.c does, for instance (it wants to map the flash devices into either secure or non secure RAM). (This also lets you embed the device struct into some other struct if you want rather than using qdev_new(), though we don't have any code that does that currently.) thanks -- PMM From MAILER-DAEMON Fri Jan 06 15:34:09 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pDtPl-00008l-7h for mharc-qemu-riscv@gnu.org; Fri, 06 Jan 2023 15:34:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pDtPj-00007t-73 for qemu-riscv@nongnu.org; Fri, 06 Jan 2023 15:34:07 -0500 Received: from mail-oa1-x31.google.com ([2001:4860:4864:20::31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pDtPe-0006mj-1Y for qemu-riscv@nongnu.org; Fri, 06 Jan 2023 15:34:04 -0500 Received: by mail-oa1-x31.google.com with SMTP id 586e51a60fabf-15085b8a2f7so2823595fac.2 for ; Fri, 06 Jan 2023 12:34:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=XuXZcy6N667ycFLluxXP+pMYomBRgoHWk5jqhZH4j6I=; b=BGMo9YkHOzYyEhUupbVzhpz4A4yXpn2PBGWA//Wc4lifEEIOSNMuM7Xg38k1R5d3Ue mbhCCATsoyXabRTRK6OeIHhERDBQ33gjLWA3QCWU/vJVFjkiXYqKlTLRHRAqmXEqop26 7qzI/L4cFg1fiNC4jjjrlR+jJLB/fhCaACQaqmz7jHNwbhwX9lbfOMIa4yS10wj+1jID 7SxsLL5IYcVvV0CsZQa+zdw8EoZF2fGWD2AQZR3CyZ2/9KNQHlOuyX564g/vepvSnqQp SPL1hNxyG+k/WyGhOtX95PbvQH951qOnR3CILQ9Gvd8/McCzgnWh+eob9O/oVC8eXaqQ j54g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=XuXZcy6N667ycFLluxXP+pMYomBRgoHWk5jqhZH4j6I=; b=aFgOIKmjAE2zUB1QxUcovgSFzughr1r/EOQOzNPW+RY4mXx3jwWgU2f6jmSFs5cdip MTdqLPRkmmkaw3myEVju87kYhePl+PcET9m+Ajny5RcNZXHEf/7qttZxv6xm6moreql3 6mFTFkigisaoXyMpD6zsUIVmUaCScXFIuFPxTBm+K5iI2y5YtTcymxBmkrCc89zLlY8D 4Wj3I/w5RTE/c5CHkr4q+ljUsJNNEL3m850tQNF9+248oI15gcN6Wj8v5+48fCLXe8q0 JXqUcaEG9PQIys4rCDZX/2nvyDgZyWNOmGvnVLsro4omCy057h/NhTmeuG+N7W4MBo9R 0qhw== X-Gm-Message-State: AFqh2krMbKPzNvgLSZQwxlIYSpRWwmdyO8PIJw9nJZKMoLEFg7KB8qfb 7O3/Y4JnK5PP9qgrV0H70OImVg== X-Google-Smtp-Source: AMrXdXuXJ4BFcxkjuZXL4d+g03vH7mz9t0RhD4mWsmM3XPz74eyy7wEH+7xD0AQAjJHyxGbvWSkKdw== X-Received: by 2002:a05:6870:4689:b0:148:2257:50cf with SMTP id a9-20020a056870468900b00148225750cfmr30786124oap.2.1673037239396; Fri, 06 Jan 2023 12:33:59 -0800 (PST) Received: from [192.168.68.107] ([152.250.93.24]) by smtp.gmail.com with ESMTPSA id i8-20020a056870344800b0013b92b3ac64sm1006586oah.3.2023.01.06.12.33.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 06 Jan 2023 12:33:58 -0800 (PST) Message-ID: Date: Fri, 6 Jan 2023 17:33:49 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH 06/20] hw/riscv: Use generic DeviceState instead of PFlashCFI01 To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf References: <20230104220449.41337-1-philmd@linaro.org> <20230104220449.41337-7-philmd@linaro.org> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20230104220449.41337-7-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x31.google.com X-Spam_score_int: -49 X-Spam_score: -5.0 X-Spam_bar: ----- X-Spam_report: (-5.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-2.939, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Jan 2023 20:34:07 -0000 On 1/4/23 19:04, Philippe Mathieu-Daudé wrote: > Nothing here requires access to PFlashCFI01 internal fields: > use the inherited generic DeviceState. > > Signed-off-by: Philippe Mathieu-Daudé > --- Reviewed-by: Daniel Henrique Barboza > hw/riscv/virt.c | 9 +++++---- > include/hw/riscv/virt.h | 3 +-- > 2 files changed, 6 insertions(+), 6 deletions(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 400bd9329f..b421a9dc12 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -46,6 +46,7 @@ > #include "sysemu/sysemu.h" > #include "sysemu/kvm.h" > #include "sysemu/tpm.h" > +#include "hw/block/flash.h" > #include "hw/pci/pci.h" > #include "hw/pci-host/gpex.h" > #include "hw/display/ramfb.h" > @@ -106,7 +107,7 @@ static MemMapEntry virt_high_pcie_memmap; > > #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) > > -static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, > +static DeviceState *virt_flash_create1(RISCVVirtState *s, > const char *name, > const char *alias_prop_name) > { > @@ -130,7 +131,7 @@ static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, > object_property_add_alias(OBJECT(s), alias_prop_name, > OBJECT(dev), "drive"); > > - return PFLASH_CFI01(dev); > + return dev; > } > > static void virt_flash_create(RISCVVirtState *s) > @@ -139,7 +140,7 @@ static void virt_flash_create(RISCVVirtState *s) > s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); > } > > -static void virt_flash_map1(PFlashCFI01 *flash, > +static void virt_flash_map1(DeviceState *flash, > hwaddr base, hwaddr size, > MemoryRegion *sysmem) > { > @@ -1517,7 +1518,7 @@ static void virt_machine_init(MachineState *machine) > > for (i = 0; i < ARRAY_SIZE(s->flash); i++) { > /* Map legacy -drive if=pflash to machine properties */ > - pflash_cfi01_legacy_drive(DEVICE(s->flash[i]), > + pflash_cfi01_legacy_drive(s->flash[i], > drive_get(IF_PFLASH, 0, i)); > } > virt_flash_map(s, system_memory); > diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h > index be4ab8fe7f..b700a46763 100644 > --- a/include/hw/riscv/virt.h > +++ b/include/hw/riscv/virt.h > @@ -21,7 +21,6 @@ > > #include "hw/riscv/riscv_hart.h" > #include "hw/sysbus.h" > -#include "hw/block/flash.h" > #include "qom/object.h" > > #define VIRT_CPUS_MAX_BITS 9 > @@ -49,7 +48,7 @@ struct RISCVVirtState { > DeviceState *platform_bus_dev; > RISCVHartArrayState soc[VIRT_SOCKETS_MAX]; > DeviceState *irqchip[VIRT_SOCKETS_MAX]; > - PFlashCFI01 *flash[2]; > + DeviceState *flash[2]; > FWCfgState *fw_cfg; > > int fdt_size; From MAILER-DAEMON Sat Jan 07 21:37:33 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELYz-0004c7-EX for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:37:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELYy-0004bU-34 for qemu-riscv@nongnu.org; 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 00/36] tcg: Support for Int128 with helpers Date: Sat, 7 Jan 2023 18:36:43 -0800 Message-Id: <20230108023719.2466341-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:37:32 -0000 Changes for v4: * About half of the v3 series has been merged, * AArch64 host requires even argument register. * target/{arm,ppc,s390x,i386} uses included here. Patches requiring review: 01-tcg-Define-TCG_TYPE_I128-and-related-helper-macro.patch 02-tcg-Handle-dh_typecode_i128-with-TCG_CALL_-RET-AR.patch 03-tcg-Allocate-objects-contiguously-in-temp_allocat.patch 05-tcg-Add-TCG_CALL_-RET-ARG-_BY_REF.patch 07-tcg-Add-TCG_CALL_RET_BY_VEC.patch 08-include-qemu-int128-Use-Int128-structure-for-TCI.patch 09-tcg-i386-Add-TCG_TARGET_CALL_-RET-ARG-_I128.patch 10-tcg-tci-Fix-big-endian-return-register-ordering.patch 11-tcg-tci-Add-TCG_TARGET_CALL_-RET-ARG-_I128.patch 13-tcg-Add-temp-allocation-for-TCGv_i128.patch 14-tcg-Add-basic-data-movement-for-TCGv_i128.patch 15-tcg-Add-guest-load-store-primitives-for-TCGv_i128.patch 16-tcg-Add-tcg_gen_-non-atomic_cmpxchg_i128.patch 17-tcg-Split-out-tcg_gen_nonatomic_cmpxchg_i-32-64.patch 24-target-s390x-Use-a-single-return-for-helper_divs3.patch 31-target-s390x-Use-Int128-for-passing-float128.patch 32-target-s390x-Use-tcg_gen_atomic_cmpxchg_i128-for-.patch 33-target-s390x-Implement-CC_OP_NZ-in-gen_op_calc_cc.patch 34-target-i386-Split-out-gen_cmpxchg8b-gen_cmpxchg16.patch 35-target-i386-Inline-cmpxchg8b.patch 36-target-i386-Inline-cmpxchg16b.patch r~ Ilya Leoshkevich (2): tests/tcg/s390x: Add div.c tests/tcg/s390x: Add clst.c Richard Henderson (34): tcg: Define TCG_TYPE_I128 and related helper macros tcg: Handle dh_typecode_i128 with TCG_CALL_{RET,ARG}_NORMAL tcg: Allocate objects contiguously in temp_allocate_frame tcg: Introduce tcg_out_addi_ptr tcg: Add TCG_CALL_{RET,ARG}_BY_REF tcg: Introduce tcg_target_call_oarg_reg tcg: Add TCG_CALL_RET_BY_VEC include/qemu/int128: Use Int128 structure for TCI tcg/i386: Add TCG_TARGET_CALL_{RET,ARG}_I128 tcg/tci: Fix big-endian return register ordering tcg/tci: Add TCG_TARGET_CALL_{RET,ARG}_I128 tcg: Add TCG_TARGET_CALL_{RET,ARG}_I128 tcg: Add temp allocation for TCGv_i128 tcg: Add basic data movement for TCGv_i128 tcg: Add guest load/store primitives for TCGv_i128 tcg: Add tcg_gen_{non}atomic_cmpxchg_i128 tcg: Split out tcg_gen_nonatomic_cmpxchg_i{32,64} target/arm: Use tcg_gen_atomic_cmpxchg_i128 for STXP target/arm: Use tcg_gen_atomic_cmpxchg_i128 for CASP target/ppc: Use tcg_gen_atomic_cmpxchg_i128 for STQCX tests/tcg/s390x: Add long-double.c target/s390x: Use a single return for helper_divs32/u32 target/s390x: Use a single return for helper_divs64/u64 target/s390x: Use Int128 for return from CLST target/s390x: Use Int128 for return from CKSM target/s390x: Use Int128 for return from TRE target/s390x: Copy wout_x1 to wout_x1_P target/s390x: Use Int128 for returning float128 target/s390x: Use Int128 for passing float128 target/s390x: Use tcg_gen_atomic_cmpxchg_i128 for CDSG target/s390x: Implement CC_OP_NZ in gen_op_calc_cc target/i386: Split out gen_cmpxchg8b, gen_cmpxchg16b target/i386: Inline cmpxchg8b target/i386: Inline cmpxchg16b accel/tcg/tcg-runtime.h | 11 + include/exec/cpu_ldst.h | 10 + include/exec/helper-head.h | 7 + include/qemu/atomic128.h | 29 ++- include/qemu/int128.h | 25 +- include/tcg/tcg-op.h | 15 ++ include/tcg/tcg.h | 49 +++- target/arm/helper-a64.h | 8 - target/i386/helper.h | 6 - target/ppc/helper.h | 2 - target/s390x/helper.h | 54 ++--- tcg/aarch64/tcg-target.h | 2 + tcg/arm/tcg-target.h | 2 + tcg/i386/tcg-target.h | 10 + tcg/loongarch64/tcg-target.h | 2 + tcg/mips/tcg-target.h | 2 + tcg/riscv/tcg-target.h | 3 + tcg/s390x/tcg-target.h | 2 + tcg/sparc64/tcg-target.h | 2 + tcg/tcg-internal.h | 17 ++ tcg/tci/tcg-target.h | 3 + target/s390x/tcg/insn-data.h.inc | 60 ++--- accel/tcg/cputlb.c | 112 +++++++++ accel/tcg/user-exec.c | 66 ++++++ target/arm/helper-a64.c | 147 ------------ target/arm/translate-a64.c | 121 +++++----- target/i386/tcg/mem_helper.c | 126 ---------- target/i386/tcg/translate.c | 126 ++++++++-- target/ppc/mem_helper.c | 44 ---- target/ppc/translate.c | 102 ++++---- target/s390x/tcg/fpu_helper.c | 103 ++++---- target/s390x/tcg/int_helper.c | 64 ++--- target/s390x/tcg/mem_helper.c | 77 +----- target/s390x/tcg/translate.c | 217 +++++++++++------ tcg/tcg-op.c | 393 ++++++++++++++++++++++++++----- tcg/tcg.c | 303 +++++++++++++++++++++--- tcg/tci.c | 65 ++--- tests/tcg/s390x/clst.c | 82 +++++++ tests/tcg/s390x/div.c | 75 ++++++ tests/tcg/s390x/long-double.c | 24 ++ util/int128.c | 42 ++++ accel/tcg/atomic_common.c.inc | 45 ++++ tcg/aarch64/tcg-target.c.inc | 17 +- tcg/arm/tcg-target.c.inc | 30 ++- tcg/i386/tcg-target.c.inc | 52 +++- tcg/loongarch64/tcg-target.c.inc | 17 +- tcg/mips/tcg-target.c.inc | 17 +- tcg/ppc/tcg-target.c.inc | 20 +- tcg/riscv/tcg-target.c.inc | 17 +- tcg/s390x/tcg-target.c.inc | 16 +- tcg/sparc64/tcg-target.c.inc | 19 +- tcg/tci/tcg-target.c.inc | 27 ++- tests/tcg/s390x/Makefile.target | 3 + 53 files changed, 1936 insertions(+), 954 deletions(-) create mode 100644 tests/tcg/s390x/clst.c create mode 100644 tests/tcg/s390x/div.c create mode 100644 tests/tcg/s390x/long-double.c -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:37:33 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELYz-0004ca-M8 for mharc-qemu-riscv@gnu.org; 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 01/36] tcg: Define TCG_TYPE_I128 and related helper macros Date: Sat, 7 Jan 2023 18:36:44 -0800 Message-Id: <20230108023719.2466341-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:37:32 -0000 Begin staging in support for TCGv_i128 with Int128. Define the type enumerator, the typedef, and the helper-head.h macros. This cannot yet be used, because you can't allocate temporaries of this new type. Signed-off-by: Richard Henderson --- include/exec/helper-head.h | 7 +++++++ include/tcg/tcg.h | 17 ++++++++++------- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index bc6698b19f..b8d1140dc7 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -26,6 +26,7 @@ #define dh_alias_int i32 #define dh_alias_i64 i64 #define dh_alias_s64 i64 +#define dh_alias_i128 i128 #define dh_alias_f16 i32 #define dh_alias_f32 i32 #define dh_alias_f64 i64 @@ -40,6 +41,7 @@ #define dh_ctype_int int #define dh_ctype_i64 uint64_t #define dh_ctype_s64 int64_t +#define dh_ctype_i128 Int128 #define dh_ctype_f16 uint32_t #define dh_ctype_f32 float32 #define dh_ctype_f64 float64 @@ -71,6 +73,7 @@ #define dh_retvar_decl0_noreturn void #define dh_retvar_decl0_i32 TCGv_i32 retval #define dh_retvar_decl0_i64 TCGv_i64 retval +#define dh_retval_decl0_i128 TCGv_i128 retval #define dh_retvar_decl0_ptr TCGv_ptr retval #define dh_retvar_decl0(t) glue(dh_retvar_decl0_, dh_alias(t)) @@ -78,6 +81,7 @@ #define dh_retvar_decl_noreturn #define dh_retvar_decl_i32 TCGv_i32 retval, #define dh_retvar_decl_i64 TCGv_i64 retval, +#define dh_retvar_decl_i128 TCGv_i128 retval, #define dh_retvar_decl_ptr TCGv_ptr retval, #define dh_retvar_decl(t) glue(dh_retvar_decl_, dh_alias(t)) @@ -85,6 +89,7 @@ #define dh_retvar_noreturn NULL #define dh_retvar_i32 tcgv_i32_temp(retval) #define dh_retvar_i64 tcgv_i64_temp(retval) +#define dh_retvar_i128 tcgv_i128_temp(retval) #define dh_retvar_ptr tcgv_ptr_temp(retval) #define dh_retvar(t) glue(dh_retvar_, dh_alias(t)) @@ -95,6 +100,7 @@ #define dh_typecode_i64 4 #define dh_typecode_s64 5 #define dh_typecode_ptr 6 +#define dh_typecode_i128 7 #define dh_typecode_int dh_typecode_s32 #define dh_typecode_f16 dh_typecode_i32 #define dh_typecode_f32 dh_typecode_i32 @@ -104,6 +110,7 @@ #define dh_callflag_i32 0 #define dh_callflag_i64 0 +#define dh_callflag_i128 0 #define dh_callflag_ptr 0 #define dh_callflag_void 0 #define dh_callflag_noreturn TCG_CALL_NO_RETURN diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index b949d75fdd..7d346192ca 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -277,6 +277,7 @@ typedef struct TCGPool { typedef enum TCGType { TCG_TYPE_I32, TCG_TYPE_I64, + TCG_TYPE_I128, TCG_TYPE_V64, TCG_TYPE_V128, @@ -358,13 +359,14 @@ typedef tcg_target_ulong TCGArg; in tcg/README. Target CPU front-end code uses these types to deal with TCG variables as it emits TCG code via the tcg_gen_* functions. They come in several flavours: - * TCGv_i32 : 32 bit integer type - * TCGv_i64 : 64 bit integer type - * TCGv_ptr : a host pointer type - * TCGv_vec : a host vector type; the exact size is not exposed - to the CPU front-end code. - * TCGv : an integer type the same size as target_ulong - (an alias for either TCGv_i32 or TCGv_i64) + * TCGv_i32 : 32 bit integer type + * TCGv_i64 : 64 bit integer type + * TCGv_i128 : 128 bit integer type + * TCGv_ptr : a host pointer type + * TCGv_vec : a host vector type; the exact size is not exposed + to the CPU front-end code. + * TCGv : an integer type the same size as target_ulong + (an alias for either TCGv_i32 or TCGv_i64) The compiler's type checking will complain if you mix them up and pass the wrong sized TCGv to a function. @@ -384,6 +386,7 @@ typedef tcg_target_ulong TCGArg; typedef struct TCGv_i32_d *TCGv_i32; typedef struct TCGv_i64_d *TCGv_i64; +typedef struct TCGv_i128_d *TCGv_i128; typedef struct TCGv_ptr_d *TCGv_ptr; typedef struct TCGv_vec_d *TCGv_vec; typedef TCGv_ptr TCGv_env; -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:37:34 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELZ0-0004dT-NR for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:37:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELYz-0004c5-Ar for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:37:33 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELYr-0004VH-DF for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:37:33 -0500 Received: by mail-pj1-x1031.google.com with SMTP id bj3so2175044pjb.0 for ; Sat, 07 Jan 2023 18:37:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uy+1LYtKetQWFHYH8PaN7/XbqnFh4isIp+PwWLyalNo=; b=gTpYFrptaAB6DVGm8liAVvYlvcGaeThZF2mSsuwEqS4MEeWIVtzmrjxAPkfyqo81wt Wf/8VzoDmI7kIwUgNmIojeIsEiDh0lPa9YTDX4ihp52j2MYtu8zzNnn/+ypAM4+6pCuP s1KGmVCKigKUA7/mWjpExzTJvNbyFQZ7yjF+kd/xYJtvOjZyvG8e0RxwLSKuGd40GEzm wOF6s3JhjJt0rkH3ZTkzyvvrZ/tUWmpfOK+Hxm4CAEyEH3lV6A+jD3hZyJARCsxC1owi eq8kyYx4F6v2rnsMHgRxqROpU85Tx+xa9ES1PhMKKRdhGHJyxaXqMAVMI1ImrlanDKrp xOew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uy+1LYtKetQWFHYH8PaN7/XbqnFh4isIp+PwWLyalNo=; b=1sxKqJMwuHcyclly9kAfyWmhoR6KEDLiVk9wiL3UC+1PVvrxTEwPFJLKAdSXhTTzGQ Ms0pc8y05KgqJCL+oPdV4r3BCk8HVzlaGcsjLNhsfC0GUp6WCIq2moPKjOhFf+YlYajW HICELhYKvcp37+UemPKeskDGUSVZNpv7EXAzUtp3BGyEpTKcAxZhN3cc8hxOvkejyrvL 50XpA7a5QsuJNcZyzJoOa9rdg8VnQ3qSlrD0WvF2XgVeKad2K4I4XPOOo8yohvfFUdml AIxqOD+39QMZjTzECEIXYkPLytpai0O7a6EdDE0+kjv/V5rh24pTDuBv9RoCU6PeFMbY idYA== X-Gm-Message-State: AFqh2kq6OnKaZ0zNEiIE7gHGhAm1MYJZDFa1gnuiYGg6yYPIJ1DPgveQ CtgaG9Mg2ECRwVRClDoXSE9SXTTNOBK4iBc0 X-Google-Smtp-Source: AMrXdXuXQ9EW1XNokSvls9hPBC8/jQRcqSDMFCWua55675KWLzN/6yZkEbH8hlUYpYsRQ9NSl90IfQ== X-Received: by 2002:a17:902:aa8e:b0:189:abdd:400a with SMTP id d14-20020a170902aa8e00b00189abdd400amr62371783plr.15.1673145443887; Sat, 07 Jan 2023 18:37:23 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 02/36] tcg: Handle dh_typecode_i128 with TCG_CALL_{RET, ARG}_NORMAL Date: Sat, 7 Jan 2023 18:36:45 -0800 Message-Id: <20230108023719.2466341-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:37:33 -0000 Many hosts pass and return 128-bit quantities like sequential 64-bit quantities. Treat this just like we currently break down 64-bit quantities for a 32-bit host. Signed-off-by: Richard Henderson --- tcg/tcg.c | 37 +++++++++++++++++++++++++++++++++---- 1 file changed, 33 insertions(+), 4 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index da91779890..99e6e4e1a8 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -686,11 +686,22 @@ static void init_call_layout(TCGHelperInfo *info) case dh_typecode_s64: info->nr_out = 64 / TCG_TARGET_REG_BITS; info->out_kind = TCG_CALL_RET_NORMAL; + assert(info->nr_out <= ARRAY_SIZE(tcg_target_call_oarg_regs)); + break; + case dh_typecode_i128: + info->nr_out = 128 / TCG_TARGET_REG_BITS; + info->out_kind = TCG_CALL_RET_NORMAL; /* TODO */ + switch (/* TODO */ TCG_CALL_RET_NORMAL) { + case TCG_CALL_RET_NORMAL: + assert(info->nr_out <= ARRAY_SIZE(tcg_target_call_oarg_regs)); + break; + default: + qemu_build_not_reached(); + } break; default: g_assert_not_reached(); } - assert(info->nr_out <= ARRAY_SIZE(tcg_target_call_oarg_regs)); /* * Parse and place function arguments. @@ -712,6 +723,9 @@ static void init_call_layout(TCGHelperInfo *info) case dh_typecode_ptr: type = TCG_TYPE_PTR; break; + case dh_typecode_i128: + type = TCG_TYPE_I128; + break; default: g_assert_not_reached(); } @@ -751,6 +765,19 @@ static void init_call_layout(TCGHelperInfo *info) } break; + case TCG_TYPE_I128: + switch (/* TODO */ TCG_CALL_ARG_NORMAL) { + case TCG_CALL_ARG_EVEN: + layout_arg_even(&cum); + /* fall through */ + case TCG_CALL_ARG_NORMAL: + layout_arg_normal_n(&cum, info, 128 / TCG_TARGET_REG_BITS); + break; + default: + qemu_build_not_reached(); + } + break; + default: g_assert_not_reached(); } @@ -1668,11 +1695,13 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) op->args[pi++] = temp_arg(ret); break; case 2: + case 4: tcg_debug_assert(ret != NULL); - tcg_debug_assert(ret->base_type == ret->type + 1); + tcg_debug_assert(ret->base_type == ret->type + ctz32(n)); tcg_debug_assert(ret->temp_subindex == 0); - op->args[pi++] = temp_arg(ret); - op->args[pi++] = temp_arg(ret + 1); + for (i = 0; i < n; ++i) { + op->args[pi++] = temp_arg(ret + i); + } break; default: g_assert_not_reached(); -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:37:39 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELZ5-0004gc-6C for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:37:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZ3-0004fR-NR for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:37:37 -0500 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELYs-0004Ve-4N for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:37:37 -0500 Received: by mail-pl1-x62a.google.com with SMTP id jl4so5863622plb.8 for ; Sat, 07 Jan 2023 18:37:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ie3FlFBACJeq4X/M6VQiwe1m8Ml1Kbx+Yprz1q0XbrA=; b=Z15r7KZxo6FKWk9NQI5CRhE+8/7Y/WGTW39Y29D4hKJUkIKkC6fUGY6fDsLJ8Uj1OJ 4mkSehnvjsUrwpkvvSOFrB4ULe04PPEt3eE3rSS805ppw6s3/6g8JHQ+31MHlEQx5kBb dRB/QdEIL49sKWQYZNzMtgInpZdQdeeeq7pkejuZNfbUS8YNAZCEswSTW4IuCvt6DEsl nOpvnNbv1DWAwEycMigmUBmJmYJNKN1eJiL6K8HHZfAYtBWVmnJRduLAIEegXGE1qY+U Sh9HdkSX4qeIbwI34dmRNaKjKuBbGOQn9t7zVOAxGpOtYz/oj5b5pSXEsvyJl07ruErH HaRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ie3FlFBACJeq4X/M6VQiwe1m8Ml1Kbx+Yprz1q0XbrA=; b=73FQTUd1kfUWNBSepmJCKYSuK6yMkcrX6LY3hNOGPwyKhl8djY9CLeNaAeAJiAIDMU I2qwyJMeboEr2mi6qcdoDpfvC3NEc7fEK+CBXJqp6XgDaMxmdgGTOzo1MWSkv6G3xxrd Pn4egDGE0gKx9PDSZVo39ViyA0jwwqiHZAIU0hek952ALdWhLKfTG6M6NpM+KHSrtmFj 7ViRK0MhfL6nHuxd3v1q90bQtXLjQ2gAVOBADAR78GCZGY11kYumA+KykGmMvZjRWamD pKgPtdohckb2TUjM7cKyEDAmCGYLzgzcusKw171/s4S8SlV30rdBlxvJJ8DwffhIzqc4 wZfw== X-Gm-Message-State: AFqh2kq88pep7IK/qZysCCnoVMnBdlzD8zsdMZDbQFmF+8AqF+v/VRLl MVLLMTGJ4nBIEMInf22BaJI1nw== X-Google-Smtp-Source: AMrXdXsW2CjhvWbAVrh8ulwzsWWWefeDvIT9tKykiaRfAk2sc1JVK/ybfqkQeHdkKP5VPKJQ2TrvKw== X-Received: by 2002:a05:6a20:a584:b0:ad:a5fd:b664 with SMTP id bc4-20020a056a20a58400b000ada5fdb664mr68551943pzb.37.1673145444802; Sat, 07 Jan 2023 18:37:24 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:24 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 03/36] tcg: Allocate objects contiguously in temp_allocate_frame Date: Sat, 7 Jan 2023 18:36:46 -0800 Message-Id: <20230108023719.2466341-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:37:37 -0000 When allocating a temp to the stack frame, consider the base type and allocate all parts at once. Signed-off-by: Richard Henderson --- tcg/tcg.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 99e6e4e1a8..7e69e2c9fd 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -3242,11 +3242,12 @@ static bool liveness_pass_2(TCGContext *s) static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) { - int size = tcg_type_size(ts->type); - int align; intptr_t off; + int size, align; - switch (ts->type) { + /* When allocating an object, look at the full type. */ + size = tcg_type_size(ts->base_type); + switch (ts->base_type) { case TCG_TYPE_I32: align = 4; break; @@ -3277,13 +3278,26 @@ static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) tcg_raise_tb_overflow(s); } s->current_frame_offset = off + size; - - ts->mem_offset = off; #if defined(__sparc__) - ts->mem_offset += TCG_TARGET_STACK_BIAS; + off += TCG_TARGET_STACK_BIAS; #endif - ts->mem_base = s->frame_temp; - ts->mem_allocated = 1; + + /* If the object was subdivided, assign memory to all the parts. */ + if (ts->base_type != ts->type) { + int part_size = tcg_type_size(ts->type); + int part_count = size / part_size; + + ts -= ts->temp_subindex; + for (int i = 0; i < part_count; ++i) { + ts[i].mem_offset = off + i * part_size; + ts[i].mem_base = s->frame_temp; + ts[i].mem_allocated = 1; + } + } else { + ts->mem_offset = off; + ts->mem_base = s->frame_temp; + ts->mem_allocated = 1; + } } /* Assign @reg to @ts, and update reg_to_temp[]. */ -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:37:41 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELZ7-0004jW-Oy for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:37:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZ6-0004hV-DG for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:37:40 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELYt-0004WL-J9 for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:37:40 -0500 Received: by mail-pl1-x62c.google.com with SMTP id c6so5884450pls.4 for ; Sat, 07 Jan 2023 18:37:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9Rv856N+OWstGUl7U1vP59WucQCWPrxG6fVCW7RDz4k=; b=fwnqtv2jC1ESO6lC5Y/IX69fD2uiohbh2dlaBhqIJbRImITXE5f0gRRB53LvD4+qGu eb2v1+Y6NM8MKVEFWYxwb+tUCD7RhgA2Iy/qxjlqNUxMTgIX4tPkOnz0BnrDLNMKgx1z YucwxKi04pkBHZaeCjtaFjgw6NOZO0m1GUijODP5btf5r5+H/+0sPcqhY4pBy6TUSZ5Z rW3lYxxsxu97umMu+3Jm+LxaGkpgeFtsK4+z/R5MeDfKuWaN9bZE+uXnm+iH141I3+kJ dcg17m1mguxXmpTaBR6I0gzQJ0WCZW2LsTzGfAhWFR8TGe/tUunOpdah7qQBCfyDTuej 3wCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9Rv856N+OWstGUl7U1vP59WucQCWPrxG6fVCW7RDz4k=; b=n79oEuxOPczoL9Rja3hWBH5P+Ht/LwTFoJK/uXBI9gqbVEYsrzO1IzFGjyR8b35QpH doQrmtEFClBWTs5uhM38NU5UpfvzVJ5QhyWCbfg9UmzOHVkj41hZUewrz3uC2cvdfQT6 WGIesjFo/bph7xgTBm8TR0mLPVNX1+kVIsFbFM9ozYpe3z/muiIJ3bIJ1g1hUllR94gC NTLzBxWRGo+1ivp8NW+HqwcF12L1L3ErF1Lit8Kk+M4tuFfTWjXgmgYdoHN6Yjhzd56w 5Vv36Oenolf8/hC2tNSypNoIkJVKgSLkhBkLWF0DPGfb38luh030zag4IkX5H6u/3OUC Jieg== X-Gm-Message-State: AFqh2krdJVxpr4qy7+1gYjwzpOkR2a9ssIKoKZkccwwseTgDgT87ocKX S5H0w0usHYxNb0agvOWIVJ0nvQ== X-Google-Smtp-Source: AMrXdXuz9rPfuEcj89rl2AbxoiX8/IJTVUDvrXji45IGqXFo8r5ub0hZzb9mYsQ2kUJQVzuAzgBDMw== X-Received: by 2002:a17:902:ccc4:b0:186:e434:6265 with SMTP id z4-20020a170902ccc400b00186e4346265mr73347806ple.2.1673145445962; Sat, 07 Jan 2023 18:37:25 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Daniel Henrique Barboza Subject: [PATCH v4 04/36] tcg: Introduce tcg_out_addi_ptr Date: Sat, 7 Jan 2023 18:36:47 -0800 Message-Id: <20230108023719.2466341-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:37:40 -0000 Implement the function for arm, i386, and s390x, which will use it. Add stubs for all other backends. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/tcg.c | 2 ++ tcg/aarch64/tcg-target.c.inc | 7 +++++++ tcg/arm/tcg-target.c.inc | 20 ++++++++++++++++++++ tcg/i386/tcg-target.c.inc | 8 ++++++++ tcg/loongarch64/tcg-target.c.inc | 7 +++++++ tcg/mips/tcg-target.c.inc | 7 +++++++ tcg/ppc/tcg-target.c.inc | 7 +++++++ tcg/riscv/tcg-target.c.inc | 7 +++++++ tcg/s390x/tcg-target.c.inc | 7 +++++++ tcg/sparc64/tcg-target.c.inc | 7 +++++++ tcg/tci/tcg-target.c.inc | 7 +++++++ 11 files changed, 86 insertions(+) diff --git a/tcg/tcg.c b/tcg/tcg.c index 7e69e2c9fd..a6c2783285 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -103,6 +103,8 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); +static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long) + __attribute__((unused)); static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]); diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index ad1816e32d..2279a14c11 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1102,6 +1102,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, tcg_out_insn(s, 3305, LDR, 0, rd); } +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + /* Define something more legible for general use. */ #define tcg_out_ldst_r tcg_out_insn_3310 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 9245ea86d0..8b24481d8c 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -2540,6 +2540,26 @@ static void tcg_out_movi(TCGContext *s, TCGType type, tcg_out_movi32(s, COND_AL, ret, arg); } +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + int enc, opc = ARITH_ADD; + + /* All of the easiest immediates to encode are positive. */ + if (imm < 0) { + imm = -imm; + opc = ARITH_SUB; + } + enc = encode_imm(imm); + if (enc >= 0) { + tcg_out_dat_imm(s, COND_AL, opc, rd, rs, enc); + } else { + tcg_out_movi32(s, COND_AL, TCG_REG_TMP, imm); + tcg_out_dat_reg(s, COND_AL, opc, rd, rs, + TCG_REG_TMP, SHIFT_IMM_LSL(0)); + } +} + /* Type is always V128, with I64 elements. */ static void tcg_out_dup2_vec(TCGContext *s, TCGReg rd, TCGReg rl, TCGReg rh) { diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 58bd5873f5..6a021dda8b 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1069,6 +1069,14 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + tcg_debug_assert(TCG_TARGET_REG_BITS == 32); + tcg_out_modrm_offset(s, OPC_LEA, rd, rs, imm); +} + static inline void tcg_out_pushi(TCGContext *s, tcg_target_long val) { if (val == (int8_t)val) { diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index c9e99e8ec3..54b1dcd911 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -389,6 +389,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, } } +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) { tcg_out_opc_andi(s, ret, arg, 0xff); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 292e490b5c..22b5463f0f 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -550,6 +550,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) { /* ret and arg can't be register tmp0 */ diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index e0621463f6..bf3812eb8d 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -1125,6 +1125,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, } } +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static bool mask_operand(uint32_t c, int *mb, int *me) { uint32_t lsb, test; diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index f741e0582d..b961972b9f 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -558,6 +558,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, tcg_out_opc_imm(s, OPC_LD, rd, rd, 0); } +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) { tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff); diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index b9ba7b605e..d65cd79899 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1020,6 +1020,13 @@ static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, return false; } +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + tcg_out_mem(s, RX_LA, RXY_LAY, rd, rs, TCG_REG_NONE, imm); +} + /* load data from an absolute host address */ static void tcg_out_ld_abs(TCGContext *s, TCGType type, TCGReg dest, const void *abs) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index eb913f33c8..f6a8a8e605 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -497,6 +497,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, tcg_out_movi_int(s, type, ret, arg, false, TCG_REG_T2); } +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); +} + static void tcg_out_ldst_rr(TCGContext *s, TCGReg data, TCGReg a1, TCGReg a2, int op) { diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index d36a7ebdd1..633345d74b 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -557,6 +557,13 @@ static void tcg_out_movi(TCGContext *s, TCGType type, } } +static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, + tcg_target_long imm) +{ + /* This function is only used for passing structs by reference. */ + g_assert_not_reached(); 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 05/36] tcg: Add TCG_CALL_{RET,ARG}_BY_REF Date: Sat, 7 Jan 2023 18:36:48 -0800 Message-Id: <20230108023719.2466341-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:37:41 -0000 These will be used by some hosts, both 32 and 64-bit, to pass and return i128. Not yet used, because allocation is not yet enabled. Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 3 + tcg/tcg.c | 135 ++++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 135 insertions(+), 3 deletions(-) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 6e50aeba3a..2ec1ea01df 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -36,6 +36,7 @@ */ typedef enum { TCG_CALL_RET_NORMAL, /* by registers */ + TCG_CALL_RET_BY_REF, /* for i128, by reference */ } TCGCallReturnKind; typedef enum { @@ -44,6 +45,8 @@ typedef enum { TCG_CALL_ARG_EXTEND, /* for i32, as a sign/zero-extended i64 */ TCG_CALL_ARG_EXTEND_U, /* ... as a zero-extended i64 */ TCG_CALL_ARG_EXTEND_S, /* ... as a sign-extended i64 */ + TCG_CALL_ARG_BY_REF, /* for i128, by reference, first */ + TCG_CALL_ARG_BY_REF_N, /* ... by reference, subsequent */ } TCGCallArgumentKind; typedef struct TCGCallArgumentLoc { diff --git a/tcg/tcg.c b/tcg/tcg.c index a6c2783285..93d1331f93 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -103,8 +103,7 @@ static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1, static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg); static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, tcg_target_long arg); -static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long) - __attribute__((unused)); +static void tcg_out_addi_ptr(TCGContext *s, TCGReg, TCGReg, tcg_target_long); static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]); @@ -662,6 +661,38 @@ static void layout_arg_normal_n(TCGCumulativeArgs *cum, cum->arg_slot += n; } +static void layout_arg_by_ref(TCGCumulativeArgs *cum, TCGHelperInfo *info) +{ + TCGCallArgumentLoc *loc = &info->in[cum->info_in_idx]; + int n = 128 / TCG_TARGET_REG_BITS; + + /* The first subindex carries the pointer. */ + layout_arg_1(cum, info, TCG_CALL_ARG_BY_REF); + + /* + * The callee is allowed to clobber memory associated with + * structure pass by-reference. Therefore we must make copies. + * Allocate space from "ref_slot", which will be adjusted to + * follow the parameters on the stack. + */ + loc[0].ref_slot = cum->ref_slot; + + /* + * Subsequent words also go into the reference slot, but + * do not accumulate into the regular arguments. + */ + for (int i = 1; i < n; ++i) { + loc[i] = (TCGCallArgumentLoc){ + .kind = TCG_CALL_ARG_BY_REF_N, + .arg_idx = cum->arg_idx, + .tmp_subindex = i, + .ref_slot = cum->ref_slot + i, + }; + } + cum->info_in_idx += n; + cum->ref_slot += n; +} + static void init_call_layout(TCGHelperInfo *info) { int max_reg_slots = ARRAY_SIZE(tcg_target_call_iarg_regs); @@ -697,6 +728,14 @@ static void init_call_layout(TCGHelperInfo *info) case TCG_CALL_RET_NORMAL: assert(info->nr_out <= ARRAY_SIZE(tcg_target_call_oarg_regs)); break; + case TCG_CALL_RET_BY_REF: + /* + * Allocate the first argument to the output. + * We don't need to store this anywhere, just make it + * unavailable for use in the input loop below. + */ + cum.arg_slot = 1; + break; default: qemu_build_not_reached(); } @@ -775,6 +814,9 @@ static void init_call_layout(TCGHelperInfo *info) case TCG_CALL_ARG_NORMAL: layout_arg_normal_n(&cum, info, 128 / TCG_TARGET_REG_BITS); break; + case TCG_CALL_ARG_BY_REF: + layout_arg_by_ref(&cum, info); + break; default: qemu_build_not_reached(); } @@ -790,7 +832,39 @@ static void init_call_layout(TCGHelperInfo *info) assert(cum.info_in_idx <= ARRAY_SIZE(info->in)); /* Validate the backend has enough argument space. */ assert(cum.arg_slot <= max_reg_slots + max_stk_slots); - assert(cum.ref_slot <= max_stk_slots); + + /* + * Relocate the "ref_slot" area to the end of the parameters. + * Minimizing this stack offset helps code size for x86, + * which has a signed 8-bit offset encoding. + */ + if (cum.ref_slot != 0) { + int ref_base = 0; + + if (cum.arg_slot > max_reg_slots) { + int align = __alignof(Int128) / sizeof(tcg_target_long); + + ref_base = cum.arg_slot - max_reg_slots; + if (align > 1) { + ref_base = ROUND_UP(ref_base, align); + } + } + assert(ref_base + cum.ref_slot <= max_stk_slots); + + if (ref_base != 0) { + for (int i = cum.info_in_idx - 1; i >= 0; --i) { + TCGCallArgumentLoc *loc = &info->in[i]; + switch (loc->kind) { + case TCG_CALL_ARG_BY_REF: + case TCG_CALL_ARG_BY_REF_N: + loc->ref_slot += ref_base; + break; + default: + break; + } + } + } + } } static int indirect_reg_alloc_order[ARRAY_SIZE(tcg_target_reg_alloc_order)]; @@ -1716,6 +1790,8 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) switch (loc->kind) { case TCG_CALL_ARG_NORMAL: + case TCG_CALL_ARG_BY_REF: + case TCG_CALL_ARG_BY_REF_N: op->args[pi++] = temp_arg(ts); break; @@ -4382,6 +4458,27 @@ static void load_arg_normal(TCGContext *s, const TCGCallArgumentLoc *l, } } +static void load_arg_ref(TCGContext *s, int arg_slot, TCGReg ref_base, + intptr_t ref_off, TCGRegSet *allocated_regs) +{ + TCGReg reg; + int stk_slot = arg_slot - ARRAY_SIZE(tcg_target_call_iarg_regs); + + if (stk_slot < 0) { + reg = tcg_target_call_iarg_regs[arg_slot]; + tcg_reg_free(s, reg, *allocated_regs); + tcg_out_addi_ptr(s, reg, ref_base, ref_off); + tcg_regset_set_reg(*allocated_regs, reg); + } else { + reg = tcg_reg_alloc(s, tcg_target_available_regs[TCG_TYPE_PTR], + *allocated_regs, 0, false); + tcg_out_addi_ptr(s, reg, ref_base, ref_off); + tcg_out_st(s, TCG_TYPE_PTR, reg, TCG_REG_CALL_STACK, + TCG_TARGET_CALL_STACK_OFFSET + + stk_slot * sizeof(tcg_target_long)); + } +} + static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) { const int nb_oargs = TCGOP_CALLO(op); @@ -4405,6 +4502,16 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) case TCG_CALL_ARG_EXTEND_S: load_arg_normal(s, loc, ts, &allocated_regs); break; + case TCG_CALL_ARG_BY_REF: + load_arg_stk(s, loc->ref_slot, ts, allocated_regs); + load_arg_ref(s, loc->arg_slot, TCG_REG_CALL_STACK, + TCG_TARGET_CALL_STACK_OFFSET + + loc->ref_slot * sizeof(tcg_target_long), + &allocated_regs); + break; + case TCG_CALL_ARG_BY_REF_N: + load_arg_stk(s, loc->ref_slot, ts, allocated_regs); + break; default: g_assert_not_reached(); } @@ -4436,6 +4543,19 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) save_globals(s, allocated_regs); } + /* + * If the ABI passes a pointer to the returned struct as the first + * argument, load that now. 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:27 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Daniel Henrique Barboza Subject: [PATCH v4 06/36] tcg: Introduce tcg_target_call_oarg_reg Date: Sat, 7 Jan 2023 18:36:49 -0800 Message-Id: <20230108023719.2466341-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:37:43 -0000 Replace the flat array tcg_target_call_oarg_regs[] with a function call including the TCGCallReturnKind. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/tcg.c | 9 ++++++--- tcg/aarch64/tcg-target.c.inc | 10 +++++++--- tcg/arm/tcg-target.c.inc | 10 +++++++--- tcg/i386/tcg-target.c.inc | 16 ++++++++++------ tcg/loongarch64/tcg-target.c.inc | 10 ++++++---- tcg/mips/tcg-target.c.inc | 10 ++++++---- tcg/ppc/tcg-target.c.inc | 10 ++++++---- tcg/riscv/tcg-target.c.inc | 10 ++++++---- tcg/s390x/tcg-target.c.inc | 9 ++++++--- tcg/sparc64/tcg-target.c.inc | 12 ++++++------ tcg/tci/tcg-target.c.inc | 12 ++++++------ 11 files changed, 72 insertions(+), 46 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index 93d1331f93..092cdaf422 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -148,6 +148,7 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, TCGReg base, intptr_t ofs); static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, const TCGHelperInfo *info); +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot); static bool tcg_target_const_match(int64_t val, TCGType type, int ct); #ifdef TCG_TARGET_NEED_LDST_LABELS static int tcg_out_ldst_finalize(TCGContext *s); @@ -719,14 +720,16 @@ static void init_call_layout(TCGHelperInfo *info) case dh_typecode_s64: info->nr_out = 64 / TCG_TARGET_REG_BITS; info->out_kind = TCG_CALL_RET_NORMAL; - assert(info->nr_out <= ARRAY_SIZE(tcg_target_call_oarg_regs)); + /* Query the last register now to trigger any assert early. */ + tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); break; case dh_typecode_i128: info->nr_out = 128 / TCG_TARGET_REG_BITS; info->out_kind = TCG_CALL_RET_NORMAL; /* TODO */ switch (/* TODO */ TCG_CALL_RET_NORMAL) { case TCG_CALL_RET_NORMAL: - assert(info->nr_out <= ARRAY_SIZE(tcg_target_call_oarg_regs)); + /* Query the last register now to trigger any assert early. */ + tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); break; case TCG_CALL_RET_BY_REF: /* @@ -4563,7 +4566,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) case TCG_CALL_RET_NORMAL: for (i = 0; i < nb_oargs; i++) { TCGTemp *ts = arg_temp(op->args[i]); - TCGReg reg = tcg_target_call_oarg_regs[i]; + TCGReg reg = tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL, i); /* ENV should not be modified. */ tcg_debug_assert(!temp_readonly(ts)); diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 2279a14c11..dfe569dd8c 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -63,9 +63,13 @@ static const int tcg_target_call_iarg_regs[8] = { TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7 }; -static const int tcg_target_call_oarg_regs[1] = { - TCG_REG_X0 -}; + +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >= 0 && slot <= 1); + return TCG_REG_X0 + slot; +} #define TCG_REG_TMP TCG_REG_X30 #define TCG_VEC_TMP TCG_REG_V31 diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 8b24481d8c..4e1d06dcd8 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -79,9 +79,13 @@ static const int tcg_target_reg_alloc_order[] = { static const int tcg_target_call_iarg_regs[4] = { TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 }; -static const int tcg_target_call_oarg_regs[2] = { - TCG_REG_R0, TCG_REG_R1 -}; + +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >= 0 && slot <= 3); + return TCG_REG_R0 + slot; +} #define TCG_REG_TMP TCG_REG_R12 #define TCG_VEC_TMP TCG_REG_Q15 diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 6a021dda8b..ab6881a4f3 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -109,12 +109,16 @@ static const int tcg_target_call_iarg_regs[] = { #endif }; -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_EAX, -#if TCG_TARGET_REG_BITS == 32 - TCG_REG_EDX -#endif -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + switch (kind) { + case TCG_CALL_RET_NORMAL: + tcg_debug_assert(slot >= 0 && slot <= 1); + return slot ? TCG_REG_EDX : TCG_REG_EAX; + default: + g_assert_not_reached(); + } +} /* Constants we accept. */ #define TCG_CT_CONST_S32 0x100 diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 54b1dcd911..f6b0ed00bb 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -114,10 +114,12 @@ static const int tcg_target_call_iarg_regs[] = { TCG_REG_A7, }; -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_A0, - TCG_REG_A1, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >= 0 && slot <= 1); + return TCG_REG_A0 + slot; +} #ifndef CONFIG_SOFTMMU #define USE_GUEST_BASE (guest_base != 0) diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 22b5463f0f..92883176c6 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -136,10 +136,12 @@ static const TCGReg tcg_target_call_iarg_regs[] = { #endif }; -static const TCGReg tcg_target_call_oarg_regs[2] = { - TCG_REG_V0, - TCG_REG_V1 -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >= 0 && slot <= 1); + return TCG_REG_V0 + slot; +} static const tcg_insn_unit *tb_ret_addr; static const tcg_insn_unit *bswap32_addr; diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index bf3812eb8d..d31e6c3de4 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -186,10 +186,12 @@ static const int tcg_target_call_iarg_regs[] = { TCG_REG_R10 }; -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_R3, - TCG_REG_R4 -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >= 0 && slot <= 1); + return TCG_REG_R3 + slot; +} static const int tcg_target_callee_save_regs[] = { #ifdef _CALL_DARWIN diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index b961972b9f..7cfd35e753 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -113,10 +113,12 @@ static const int tcg_target_call_iarg_regs[] = { TCG_REG_A7, }; -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_A0, - TCG_REG_A1, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >= 0 && slot <= 1); + return TCG_REG_A0 + slot; +} #define TCG_CT_CONST_ZERO 0x100 #define TCG_CT_CONST_S12 0x200 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index d65cd79899..cebf180777 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -390,9 +390,12 @@ static const int tcg_target_call_iarg_regs[] = { TCG_REG_R6, }; -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_R2, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot == 0); + return TCG_REG_R2; +} #define S390_CC_EQ 8 #define S390_CC_LT 4 diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index f6a8a8e605..9b5afb8248 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -133,12 +133,12 @@ static const int tcg_target_call_iarg_regs[6] = { TCG_REG_O5, }; -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_O0, - TCG_REG_O1, - TCG_REG_O2, - TCG_REG_O3, -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >= 0 && slot <= 3); + return TCG_REG_O0 + slot; +} #define INSN_OP(x) ((x) << 30) #define INSN_OP2(x) ((x) << 22) diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 633345d74b..cd53cb6b6b 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -200,12 +200,12 @@ static const int tcg_target_reg_alloc_order[] = { /* No call arguments via registers. All will be stored on the "stack". */ static const int tcg_target_call_iarg_regs[] = { }; -static const int tcg_target_call_oarg_regs[] = { - TCG_REG_R0, -#if TCG_TARGET_REG_BITS == 32 - TCG_REG_R1 -#endif -}; +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) +{ + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); + tcg_debug_assert(slot >= 0 && slot < 64 / TCG_TARGET_REG_BITS); + return TCG_REG_R0 + slot; +} #ifdef CONFIG_DEBUG_TCG static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:37:49 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELZF-0004pL-Io for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:37:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZD-0004o8-V6 for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:37:47 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELYw-0004Xz-6W for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:37:47 -0500 Received: by mail-pj1-x102b.google.com with SMTP id o13so1885303pjg.2 for ; Sat, 07 Jan 2023 18:37:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KwGYqVGD9ayC3AoH0H/svPpb9D46lwJjNWaf8TUEnLU=; b=wo92Lmrg8YD5vmSAR4Njag3d7RjIflVg0qFT/FuisA8HWhC99wUN6pl72nAHTHIXC1 m9qx2+ZH893MqiWmY+ZKAOMKIMOybMJ+CNP82Wn/2U7Ihku+KQJz9oddghm+k6QqLbY+ /T+hysSGmq6i9kOGePI8M25ZlcAb3W0eub1ZvUInIqI3bK8DMIOukN2Y2RUEWTjchQPr YPp/mdD+aqWKlC8zPhN1Xn7PbIGuuyXS3Q8tzsHSWvU836rbpVaBHHKMEpfeySPrJps2 kY/3EqK4L5ZHCyGHndh7yLAvasBEFFEYxYjbAs4XolIH+si8uitooS3Bh0G+wzyi4RCp 6tzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KwGYqVGD9ayC3AoH0H/svPpb9D46lwJjNWaf8TUEnLU=; b=BnbtnNtxuHJmKzGKbXfiB3RZQaFouSS4rkIfTDe4A+WDffomCmDFkM9Ef8C4AdxNUl 6PmKGVgl4lUTG91vrRJdgaoDulxwl/N7KyYHWbXZ9i8kW63zCNRvQQbv9Azy9JXhgRkI /VFeg6HWjeJTC9xBp43dawW41XTqPZByL700a8kdJS/7Z7mBZ4NP+E6KJilivAYQPILO 3KQO5B0LIvMeHbtGvgoUQqCz61/AOHC7GPMY7IxDrsaM9saR96vvRqTzwL7mUqq6qOH4 2wOOPJbkNVyAPY7JRU9QEOoplPKtDrUsQrjTdOkXDSLeuLJb7sdbr3WTwwB9xM2+LZUn RqRQ== X-Gm-Message-State: AFqh2koLy3U6C4iA3Ir5O2G6BC1ECL7mP8wdtr/4dSN+HqfsMnIX5j9U WbW/BG/+4Fp/GLwrftxIZCLyqY8TYVfghrui X-Google-Smtp-Source: AMrXdXuvchFuNHxD5uxFyiEdD06AjVAaZQm4Sg+cipC99x3zOt9lqSTMkfEKHS3DFSMNh8ifrvfB2Q== X-Received: by 2002:a17:902:7c08:b0:193:13fc:8840 with SMTP id x8-20020a1709027c0800b0019313fc8840mr6381304pll.21.1673145448869; Sat, 07 Jan 2023 18:37:28 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 07/36] tcg: Add TCG_CALL_RET_BY_VEC Date: Sat, 7 Jan 2023 18:36:50 -0800 Message-Id: <20230108023719.2466341-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:37:48 -0000 This will be used by _WIN64 to return i128. Not yet used, because allocation is not yet enabled. Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 1 + tcg/tcg.c | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 2ec1ea01df..33f1d8b411 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -37,6 +37,7 @@ typedef enum { TCG_CALL_RET_NORMAL, /* by registers */ TCG_CALL_RET_BY_REF, /* for i128, by reference */ + TCG_CALL_RET_BY_VEC, /* for i128, by vector register */ } TCGCallReturnKind; typedef enum { diff --git a/tcg/tcg.c b/tcg/tcg.c index 092cdaf422..c032606b21 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -731,6 +731,10 @@ static void init_call_layout(TCGHelperInfo *info) /* Query the last register now to trigger any assert early. */ tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); break; + case TCG_CALL_RET_BY_VEC: + /* Query the single register now to trigger any assert early. */ + tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0); + break; case TCG_CALL_RET_BY_REF: /* * Allocate the first argument to the output. @@ -4576,6 +4580,21 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) } break; + case TCG_CALL_RET_BY_VEC: + { + TCGTemp *ts = arg_temp(op->args[0]); + + tcg_debug_assert(ts->base_type == TCG_TYPE_I128); + tcg_debug_assert(ts->temp_subindex == 0); + if (!ts->mem_allocated) { + temp_allocate_frame(s, ts); + } + tcg_out_st(s, TCG_TYPE_V128, + tcg_target_call_oarg_reg(TCG_CALL_RET_BY_VEC, 0), + ts->mem_base->reg, ts->mem_offset); + } + /* fall through to mark all parts in memory */ + case TCG_CALL_RET_BY_REF: /* The callee has performed a write through the reference. */ for (i = 0; i < nb_oargs; i++) { -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:37:50 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELZG-0004pw-J4 for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:37:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZF-0004p7-3g for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:37:49 -0500 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELYw-0004UV-SC for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:37:48 -0500 Received: by mail-pj1-x102e.google.com with SMTP id m7-20020a17090a730700b00225ebb9cd01so9263330pjk.3 for ; Sat, 07 Jan 2023 18:37:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WlfgTKwjPzR9xe9xdxRaR9DbAja99BeWVoRkY0FKPGQ=; b=e+v4MiVwddxBp2l39jIW6RzLdqvz5YNLBQIU7Y9Gn3yNmqKxhyiMJNExnpzQZprhki FeoH8b66BVuwewFCwvguHlvdebxJ8pnskAzLruSDArkmkR3gqR+58SI19WATcmAErkkW rD++O8ptdlvusHuUk/+nu8awE5Jb6xTWBl7JKkn65eFzq7ONaV4yluVx64o5lhcMmRL+ 6suYI9cKVUEg4MHJX1vUDfubFLTP1B1D+BKUZpsoYLdEgc9TcBUDGMbJ0DsNsUr/SnoF eHowhcb8tsMN1AOzO9lJ4LpYtWDaV7/ifWKcV75eLNDu/wYncUtRbOfBN4PCdNIgwgtt CZzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WlfgTKwjPzR9xe9xdxRaR9DbAja99BeWVoRkY0FKPGQ=; b=c9cvLjNHLneF1PMsej2VgYJs1jMVZei4mo0PGoaekXTCsrR0NE2tMFa768vEK5+MF0 iZ5KiUxdLMhyA53mNg0Kiddj0wM9Xxrfi9ZIIBvPWpvlD0U7Ait9wkB3T+U60O8LEDtd TBytB7+j1ZJlqc69toLsbi/O71ptURe5JPdTm6bTZLZsl1L813PsBQDn2uLLINKRGD4c AecuNUfywpLIO6LXF2zTeiWKSNJKpPRYoKkzrzS9Ip48NUr5cTECSOKKJmlH6Gjm1UfL fZWmaHjFbCC6RyHNv3buUCTKaRhgzh9aNzL00PCdsO/b21U0QOmzsSDWBDF8l0Euqz8P eaFQ== X-Gm-Message-State: AFqh2kojxoYoYWBfTnGALieCDu3JJj0k3dB5Q+6Cgp5wVK6Mr+EOENHv mWGLHWV1JvQhucb//dNVgr96zQ== X-Google-Smtp-Source: AMrXdXsOLRLhUgqTsaAtzFwaH1QwckHBo7X0260/iPPIE7n7FpKtPadT+ACSyQrQE/159C3r09bS7A== X-Received: by 2002:a17:902:a5ca:b0:191:3aad:cf33 with SMTP id t10-20020a170902a5ca00b001913aadcf33mr58019695plq.55.1673145450098; Sat, 07 Jan 2023 18:37:30 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 08/36] include/qemu/int128: Use Int128 structure for TCI Date: Sat, 7 Jan 2023 18:36:51 -0800 Message-Id: <20230108023719.2466341-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:37:49 -0000 We are about to allow passing Int128 to/from tcg helper functions, but libffi doesn't support __int128_t, so use the structure. In order for atomic128.h to continue working, we must provide a mechanism to frob between real __int128_t and the structure. Provide a new union, Int128Alias, for this. We cannot modify Int128 itself, as any changed alignment would also break libffi. Signed-off-by: Richard Henderson --- include/qemu/atomic128.h | 29 +++++++++++++++++++++------ include/qemu/int128.h | 25 +++++++++++++++++++++--- util/int128.c | 42 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 87 insertions(+), 9 deletions(-) diff --git a/include/qemu/atomic128.h b/include/qemu/atomic128.h index adb9a1a260..d0ba0b9c65 100644 --- a/include/qemu/atomic128.h +++ b/include/qemu/atomic128.h @@ -44,13 +44,23 @@ #if defined(CONFIG_ATOMIC128) static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) { - return qatomic_cmpxchg__nocheck(ptr, cmp, new); + Int128Alias r, c, n; + + c.s = cmp; + n.s = new; + r.i = qatomic_cmpxchg__nocheck((__int128_t *)ptr, c.i, n.i); + return r.s; } # define HAVE_CMPXCHG128 1 #elif defined(CONFIG_CMPXCHG128) static inline Int128 atomic16_cmpxchg(Int128 *ptr, Int128 cmp, Int128 new) { - return __sync_val_compare_and_swap_16(ptr, cmp, new); + Int128Alias r, c, n; + + c.s = cmp; + n.s = new; + r.i = __sync_val_compare_and_swap_16((__int128_t *)ptr, c.i, n.i); + return r.s; } # define HAVE_CMPXCHG128 1 #elif defined(__aarch64__) @@ -89,12 +99,18 @@ Int128 QEMU_ERROR("unsupported atomic") #if defined(CONFIG_ATOMIC128) static inline Int128 atomic16_read(Int128 *ptr) { - return qatomic_read__nocheck(ptr); + Int128Alias r; + + r.i = qatomic_read__nocheck((__int128_t *)ptr); + return r.s; } static inline void atomic16_set(Int128 *ptr, Int128 val) { - qatomic_set__nocheck(ptr, val); + Int128Alias v; + + v.s = val; + qatomic_set__nocheck((__int128_t *)ptr, v.i); } # define HAVE_ATOMIC128 1 @@ -132,7 +148,8 @@ static inline void atomic16_set(Int128 *ptr, Int128 val) static inline Int128 atomic16_read(Int128 *ptr) { /* Maybe replace 0 with 0, returning the old value. */ - return atomic16_cmpxchg(ptr, 0, 0); + Int128 z = int128_make64(0); + return atomic16_cmpxchg(ptr, z, z); } static inline void atomic16_set(Int128 *ptr, Int128 val) @@ -141,7 +158,7 @@ static inline void atomic16_set(Int128 *ptr, Int128 val) do { cmp = old; old = atomic16_cmpxchg(ptr, cmp, val); - } while (old != cmp); + } while (int128_ne(old, cmp)); } # define HAVE_ATOMIC128 1 diff --git a/include/qemu/int128.h b/include/qemu/int128.h index d2b76ca6ac..f62a46b48c 100644 --- a/include/qemu/int128.h +++ b/include/qemu/int128.h @@ -3,7 +3,12 @@ #include "qemu/bswap.h" -#ifdef CONFIG_INT128 +/* + * With TCI, we need to use libffi for interfacing with TCG helpers. + * But libffi does not support __int128_t, and therefore cannot pass + * or return values of this type, force use of the Int128 struct. + */ +#if defined(CONFIG_INT128) && !defined(CONFIG_TCG_INTERPRETER) typedef __int128_t Int128; static inline Int128 int128_make64(uint64_t a) @@ -460,8 +465,7 @@ Int128 int128_divu(Int128, Int128); Int128 int128_remu(Int128, Int128); Int128 int128_divs(Int128, Int128); Int128 int128_rems(Int128, Int128); - -#endif /* CONFIG_INT128 */ +#endif /* CONFIG_INT128 && !CONFIG_TCG_INTERPRETER */ static inline void bswap128s(Int128 *s) { @@ -472,4 +476,19 @@ static inline void bswap128s(Int128 *s) #define INT128_MAX int128_make128(UINT64_MAX, INT64_MAX) #define INT128_MIN int128_make128(0, INT64_MIN) +/* + * When compiler supports a 128-bit type, define a combination of + * a possible structure and the native types. Ease parameter passing + * via use of the transparent union extension. + */ +#ifdef CONFIG_INT128 +typedef union { + Int128 s; + __int128_t i; + __uint128_t u; +} Int128Alias __attribute__((transparent_union)); +#else +typedef Int128 Int128Alias; +#endif /* CONFIG_INT128 */ + #endif /* INT128_H */ diff --git a/util/int128.c b/util/int128.c index ed8f25fef1..df6c6331bd 100644 --- a/util/int128.c +++ b/util/int128.c @@ -144,4 +144,46 @@ Int128 int128_rems(Int128 a, Int128 b) return r; } +#elif defined(CONFIG_TCG_INTERPRETER) + +Int128 int128_divu(Int128 a_s, Int128 b_s) +{ + Int128Alias r, a, b; + + a.s = a_s; + b.s = b_s; + r.u = a.u / b.u; + return r.s; +} + +Int128 int128_remu(Int128 a_s, Int128 b_s) +{ + Int128Alias r, a, b; + + a.s = a_s; + b.s = b_s; + r.u = a.u % b.u; + return r.s; +} + +Int128 int128_divs(Int128 a_s, Int128 b_s) +{ + Int128Alias r, a, b; + + a.s = a_s; + b.s = b_s; + r.i = a.i / b.i; + return r.s; +} + +Int128 int128_rems(Int128 a_s, Int128 b_s) +{ + Int128Alias r, a, b; + + a.s = a_s; + b.s = b_s; + r.i = a.i % b.i; + return r.s; +} + #endif -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:37:53 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELZJ-0004sB-2T for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:37:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZH-0004rI-Qs for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:37:51 -0500 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELYy-0004Yy-8e for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:37:51 -0500 Received: by mail-pl1-x62f.google.com with SMTP id c4so5880970plc.5 for ; Sat, 07 Jan 2023 18:37:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xWtD/TEe250UHjk6klCm4KJGVjq9QANqtB38KitJ/cg=; b=H71P5HjcjjY9BV2F+Dlma7KDkuHyDeXp3KNRbW/tziJni06kJBEC5OW13d4PNcyNcV 6DfelLA5jmSd0gkKdRuW9acjj8HoYxZnRCgZwh4qTMo6XPS7BIGM1sE1bSkA5iigGglx KKL0FeGLhC5wBlex2xT3W43GUuffxP/NWZ4xJQDsMjXFkPhW48xDRN2ddQDQ67+Imj5r hA2iKzH3dnt6j7MtlnE/OGBK9twOqR9WAkVB+dvBxcWnsmjC3kK+ZKxcO0a9qR438lqC BwhEcnNswVahg8IqHvxsysfI0MRc8ociGYFLGKpeZ/ExHnUaQCj3qsFNRtnI502tVJg4 ApKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xWtD/TEe250UHjk6klCm4KJGVjq9QANqtB38KitJ/cg=; b=7Rx9Z8r1KiJ9lWo+PAoWdFNq3kCVgEy9WXYr1Arf/TSG6+24eQBkh77g2xEoZyOXca qHvHD40oo4paf4NENyAEZ5otpjYk0gLEUmwXr1usXAa7Gy7a6V5E2KgNay+cFVAEz+r3 tokNn6cPutMYy1iweCz6zYjNHCFj2X7n7BU6ZgwupNgdmlp3EsWyE/DFrxGNqpMcGi4n WwZdpwCihbT1XIh9ooniKIecHfbv5tC/O2gmv6AEPqMbh5UnvnqK+BdaMgytXT1sxNY0 VxEEbldwvPr4IJ1tlPfDKxXlcmgpUsD0qcWhMqKET9iL4OuieILQOJ973eGTPqvEHAe3 zTZA== X-Gm-Message-State: AFqh2krdBTpQWqBOwJbso4AP598+cfzFQ4cnTJyCZTmsQgipZjg95BsA 0cDqYm+9PWTuzUoc7dWP8kbMLXzpUMpy8dWr X-Google-Smtp-Source: AMrXdXuteIDC/nhFnd3xhoSK4LQbIhQOSs2gg8voRi2TXc1aqi+nJ2V5NkckHMhOzCVGDQhDw/Jc9w== X-Received: by 2002:a17:903:230c:b0:192:64a9:62f5 with SMTP id d12-20020a170903230c00b0019264a962f5mr76931754plh.29.1673145450991; Sat, 07 Jan 2023 18:37:30 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 09/36] tcg/i386: Add TCG_TARGET_CALL_{RET,ARG}_I128 Date: Sat, 7 Jan 2023 18:36:52 -0800 Message-Id: <20230108023719.2466341-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:37:52 -0000 Fill in the parameters for the host ABI for Int128. Adjust tcg_target_call_oarg_reg for _WIN64, and tcg_out_call for i386 sysv. Allow TCG_TYPE_V128 stores without AVX enabled. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 10 ++++++++++ tcg/i386/tcg-target.c.inc | 30 +++++++++++++++++++++++++++++- 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 7edb7f1d9a..9e0e82d80a 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -100,6 +100,16 @@ typedef enum { #endif #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#if defined(_WIN64) +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF +# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_VEC +#elif TCG_TARGET_REG_BITS == 64 +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL +#else +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF +#endif extern bool have_bmi1; extern bool have_popcnt; diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index ab6881a4f3..c96b5a6f43 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -115,6 +115,11 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) case TCG_CALL_RET_NORMAL: tcg_debug_assert(slot >= 0 && slot <= 1); return slot ? TCG_REG_EDX : TCG_REG_EAX; +#ifdef _WIN64 + case TCG_CALL_RET_BY_VEC: + tcg_debug_assert(slot == 0); + return TCG_REG_XMM0; +#endif default: g_assert_not_reached(); } @@ -1188,9 +1193,16 @@ static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, * The gvec infrastructure is asserts that v128 vector loads * and stores use a 16-byte aligned offset. Validate that the * final pointer is aligned by using an insn that will SIGSEGV. + * + * This specific instance is also used by TCG_CALL_RET_BY_VEC, + * for _WIN64, which must have SSE2 but may not have AVX. */ tcg_debug_assert(arg >= 16); - tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg2); + if (have_avx1) { + tcg_out_vex_modrm_offset(s, OPC_MOVDQA_WxVx, arg, 0, arg1, arg2); + } else { + tcg_out_modrm_offset(s, OPC_MOVDQA_WxVx, arg, arg1, arg2); + } break; case TCG_TYPE_V256: /* @@ -1677,6 +1689,22 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *dest, const TCGHelperInfo *info) { tcg_out_branch(s, 1, dest); + +#ifndef _WIN32 + if (TCG_TARGET_REG_BITS == 32 && info->out_kind == TCG_CALL_RET_BY_REF) { + /* + * The sysv i386 abi for struct return places a reference as the + * first argument of the stack, and pops that argument with the + * return statement. Since we want to retain the aligned stack + * pointer for the callee, we do not want to actually push that + * argument before the call but rely on the normal store to the + * stack slot. But we do need to compensate for the pop in order + * to reset our correct stack pointer value. + * Pushing a garbage value back onto the stack is quickest. + */ + tcg_out_push(s, TCG_REG_EAX); + } +#endif } static void tcg_out_jmp(TCGContext *s, const tcg_insn_unit *dest) -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:37:56 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELZM-0004uR-Ej for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:37:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZL-0004u9-RH for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:37:55 -0500 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELYy-0004UT-PS for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:37:55 -0500 Received: by mail-pl1-x62d.google.com with SMTP id d9so5859426pll.9 for ; Sat, 07 Jan 2023 18:37:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vaZgOeSJc5X20dDhSfYmqdZAzqI99H2R1i2kilXRvO0=; b=zfcdQM4/5q2ta7iuqZJrCCSzlJEXqS0WhwPx4k2uaLccpH7A3ev/saSPpc+LYwyd0J AgrpsdRZIn2LzaDQb7iloaUOiQHpAtZA2+Yx5ujE8QjfSECJA1y8Ul7Fuftx36LL4UDr 1nPYjlb50GAEO+JSU1QP4LOjqH7F+b0yu0EEiekrmaMZOX+R46lczBguI9VnwXd3hpxC BEzpB8Y+jHE650tRX9R7SqkvtIbUXLhh9TGPgCDk3VbExPINozRY927zKsmZc2y2DGvm 695kj/+z4hboxGHIU6LzH/UrqmsVrfqqX3QDNCn4pa/AH59Y9M62pU1cgXtpKf4gNOv8 chow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vaZgOeSJc5X20dDhSfYmqdZAzqI99H2R1i2kilXRvO0=; b=P9YV9PEQMPfT4eOUquEAcEMaS1JiszibpGPgkVXQhcYn5g2q7O+hAC5WyIXnRitS52 6JtpxSJ56RHF0GR0ScISWwbT8HU333Xovk+ycFc0Q0AX3XFwVRDMc8gf71HnuX9JeaGH DBkvMCfDOW17Mte2X8zf+XkTKCii5Sw26/QILcRKr5LBVi3DnrJUO5X97JZgwndGPVXt UlLv1rDHqwmcuaqke2vR4xVQXm8Gu9CyuD4Xms5vrV/jhvR74ZZF6aBAf6Crn+Bah+E6 C3n1oqVyi0imIsbmEsIKFLjhxh8rTWn+5tdK618LIYM4c3SjtV4BR2pGqhfQICb7ZQl+ uOOw== X-Gm-Message-State: AFqh2kpwOFVqG4msH0sCCYNBWWMa5DWUH/qoQNEkVDImRM17x09G9/wf nUZ8HO+pMKbaJOslZUkS1JSq4g== X-Google-Smtp-Source: AMrXdXunXck1RbJjtxPZRS4Fns32CadcdIyHqyR4VBZfg8T+f4zdjP7ao1DXYsALrVylTfbC76QznQ== X-Received: by 2002:a17:903:451:b0:192:820d:d1 with SMTP id iw17-20020a170903045100b00192820d00d1mr51051507plb.25.1673145452040; Sat, 07 Jan 2023 18:37:32 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 10/36] tcg/tci: Fix big-endian return register ordering Date: Sat, 7 Jan 2023 18:36:53 -0800 Message-Id: <20230108023719.2466341-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:37:56 -0000 We expect the backend to require register pairs in host-endian ordering, thus for big-endian the first register of a pair contains the high part. We were forcing R0 to contain the low part for calls. Signed-off-by: Richard Henderson --- tcg/tci.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/tcg/tci.c b/tcg/tci.c index 05a24163d3..eeccdde8bc 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -520,27 +520,28 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, ffi_call(pptr[1], pptr[0], stack, call_slots); } - /* Any result winds up "left-aligned" in the stack[0] slot. */ switch (len) { case 0: /* void */ break; case 1: /* uint32_t */ /* + * The result winds up "left-aligned" in the stack[0] slot. * Note that libffi has an odd special case in that it will * always widen an integral result to ffi_arg. */ - if (sizeof(ffi_arg) == 4) { - regs[TCG_REG_R0] = *(uint32_t *)stack; - break; - } - /* fall through */ - case 2: /* uint64_t */ - if (TCG_TARGET_REG_BITS == 32) { - tci_write_reg64(regs, TCG_REG_R1, TCG_REG_R0, stack[0]); + if (sizeof(ffi_arg) == 8) { + regs[TCG_REG_R0] = (uint32_t)stack[0]; } else { - regs[TCG_REG_R0] = stack[0]; + regs[TCG_REG_R0] = *(uint32_t *)stack; } break; + case 2: /* uint64_t */ + /* + * For TCG_TARGET_REG_BITS == 32, the register pair + * must stay in host memory order. + */ + memcpy(®s[TCG_REG_R0], stack, 8); + break; default: g_assert_not_reached(); } -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:37:59 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELZP-0004wF-H7 for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:37:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZO-0004vZ-CK for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:37:58 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELYz-0004Ur-UC for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:37:58 -0500 Received: by mail-pj1-x1030.google.com with SMTP id z9-20020a17090a468900b00226b6e7aeeaso5837164pjf.1 for ; Sat, 07 Jan 2023 18:37:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lb1zdPDt2cXDP2uVEHjfwAEEiR/vLZlM3+YRRoy+01g=; b=g1ePDDqFj2G6YHcZNLvj5WFVz4qK2f8FLFqzMf7+cf3Yp4/wMbTjSh6aaVpQ+PNfgR V03xuAGeQ5PHxHHExiG7M4Bgj2bcKSrlkydUKs5hkMTgov3VSmoPyDcRd1+Rfis6I8WH 2NhU/sA85MX+DAawF0m6b5cVYoEwDPIoQi2d3EybkWLzR7Mojoj+Dt3RtPtOsw8M9zBd ndwXLIAEMrU8tN2PMJubPsEMx0Vs5JFkPRt10KOk09HPFnFPFviUj/eYHVo8WTdtJVmd k+7gqNo2gC2g23LWfviAuDwughcnfJSzApTXH9888+9kfNWq5EvdKGFqCxqhg4wrqSmg vJ2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lb1zdPDt2cXDP2uVEHjfwAEEiR/vLZlM3+YRRoy+01g=; b=StKADlqTdu6WmurtFTiK9H5VNBhWp57tJhuPsfqGgYajvLMANkkSFgVXuxpBtKkHrR JTzfgO9zR3L5lMk35Yqgwtb4wms+2El2L7He0RhvhEloo7CkM54SMWRuXAEWsrjFd0/D bEGgdDXHYHGl7ukCn6hGPEhIiWNH/mSUOeZMVZSTT1Dgjn0YWCFQ631Kv9FdlVUUfavB 0vHEiJkrBsYmDeMtu4irE2u+sJyZzj1J6B1MPx9Q3ZfEg9sW9lN3DzRQwVr8r4IxeWEI PaZ9vaO7xCr34wnuSmwKQPPz1NVRDRtr4UrKZMx311b77IIfM5bLZNQvuJATUYrnZA3v oe+Q== X-Gm-Message-State: AFqh2kqzhVbe4IDGVABZnn20Rnka9CJxRCbmunpMNpZRjNnYFxc6hWj5 +wwqr0H6Wk1KLzC2wGx8JdsDnA== X-Google-Smtp-Source: AMrXdXtU22bKLYqtLjqmSKL8wJxOtEXKHoK2cKx6usN8OqH3mKXOdRFtxnog9XbB84W3A0UvhmW/Uw== X-Received: by 2002:a17:902:864a:b0:193:ab5:39c7 with SMTP id y10-20020a170902864a00b001930ab539c7mr7840520plt.11.1673145453160; Sat, 07 Jan 2023 18:37:33 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 11/36] tcg/tci: Add TCG_TARGET_CALL_{RET,ARG}_I128 Date: Sat, 7 Jan 2023 18:36:54 -0800 Message-Id: <20230108023719.2466341-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:37:58 -0000 Fill in the parameters for libffi for Int128. Adjust the interpreter to allow for 16-byte return values. Adjust tcg_out_call to record the return value length. Call parameters are no longer all the same size, so we cannot reuse the same call_slots array for every function. Compute it each time now, but only fill in slots required for the call we're about to make. Signed-off-by: Richard Henderson --- tcg/tci/tcg-target.h | 3 +++ tcg/tcg.c | 19 +++++++++++++++++ tcg/tci.c | 44 ++++++++++++++++++++-------------------- tcg/tci/tcg-target.c.inc | 10 ++++----- 4 files changed, 49 insertions(+), 27 deletions(-) diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 94ec541b4e..9d569c9e04 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -161,10 +161,13 @@ typedef enum { #if TCG_TARGET_REG_BITS == 32 # define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EVEN # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN #else # define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL #endif +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL #define HAVE_TCG_QEMU_TB_EXEC #define TCG_TARGET_NEED_POOL_LABELS diff --git a/tcg/tcg.c b/tcg/tcg.c index c032606b21..6f72d4157a 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -549,6 +549,22 @@ static GHashTable *helper_table; #ifdef CONFIG_TCG_INTERPRETER static ffi_type *typecode_to_ffi(int argmask) { + /* + * libffi does not support __int128_t, so we have forced Int128 + * to use the structure definition instead of the builtin type. + */ + static ffi_type *ffi_type_i128_elements[3] = { + &ffi_type_uint64, + &ffi_type_uint64, + NULL + }; + static ffi_type ffi_type_i128 = { + .size = 16, + .alignment = __alignof__(Int128), + .type = FFI_TYPE_STRUCT, + .elements = ffi_type_i128_elements, + }; + switch (argmask) { case dh_typecode_void: return &ffi_type_void; @@ -562,6 +578,8 @@ static ffi_type *typecode_to_ffi(int argmask) return &ffi_type_sint64; case dh_typecode_ptr: return &ffi_type_pointer; + case dh_typecode_i128: + return &ffi_type_i128; } g_assert_not_reached(); } @@ -592,6 +610,7 @@ static void init_ffi_layouts(void) /* Ignoring the return type, find the last non-zero field. */ nargs = 32 - clz32(typemask >> 3); nargs = DIV_ROUND_UP(nargs, 3); + assert(nargs <= MAX_CALL_IARGS); ca = g_malloc0(sizeof(*ca) + nargs * sizeof(ffi_type *)); ca->cif.rtype = typecode_to_ffi(typemask & 7); diff --git a/tcg/tci.c b/tcg/tci.c index eeccdde8bc..022fe9d0f8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -470,12 +470,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tcg_target_ulong regs[TCG_TARGET_NB_REGS]; uint64_t stack[(TCG_STATIC_CALL_ARGS_SIZE + TCG_STATIC_FRAME_SIZE) / sizeof(uint64_t)]; - void *call_slots[TCG_STATIC_CALL_ARGS_SIZE / sizeof(uint64_t)]; regs[TCG_AREG0] = (tcg_target_ulong)env; regs[TCG_REG_CALL_STACK] = (uintptr_t)stack; - /* Other call_slots entries initialized at first use (see below). */ - call_slots[0] = NULL; tci_assert(tb_ptr); for (;;) { @@ -498,26 +495,26 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, switch (opc) { case INDEX_op_call: - /* - * Set up the ffi_avalue array once, delayed until now - * because many TB's do not make any calls. In tcg_gen_callN, - * we arranged for every real argument to be "left-aligned" - * in each 64-bit slot. - */ - if (unlikely(call_slots[0] == NULL)) { - for (int i = 0; i < ARRAY_SIZE(call_slots); ++i) { - call_slots[i] = &stack[i]; - } - } - - tci_args_nl(insn, tb_ptr, &len, &ptr); - - /* Helper functions may need to access the "return address" */ - tci_tb_ptr = (uintptr_t)tb_ptr; - { - void **pptr = ptr; - ffi_call(pptr[1], pptr[0], stack, call_slots); + void *call_slots[MAX_CALL_IARGS]; + ffi_cif *cif; + void *func; + unsigned i, s, n; + + tci_args_nl(insn, tb_ptr, &len, &ptr); + func = ((void **)ptr)[0]; + cif = ((void **)ptr)[1]; + + n = cif->nargs; + for (i = s = 0; i < n; ++i) { + ffi_type *t = cif->arg_types[i]; + call_slots[i] = &stack[s]; + s += DIV_ROUND_UP(t->size, 8); + } + + /* Helper functions may need to access the "return address" */ + tci_tb_ptr = (uintptr_t)tb_ptr; + ffi_call(cif, func, stack, call_slots); } switch (len) { @@ -542,6 +539,9 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, */ memcpy(®s[TCG_REG_R0], stack, 8); break; + case 3: /* Int128 */ + memcpy(®s[TCG_REG_R0], stack, 16); + break; default: g_assert_not_reached(); } diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index cd53cb6b6b..357888a532 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -203,7 +203,7 @@ static const int tcg_target_call_iarg_regs[] = { }; static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) { tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); - tcg_debug_assert(slot >= 0 && slot < 64 / TCG_TARGET_REG_BITS); + tcg_debug_assert(slot >= 0 && slot < 128 / TCG_TARGET_REG_BITS); return TCG_REG_R0 + slot; } @@ -573,11 +573,11 @@ static void tcg_out_call(TCGContext *s, const tcg_insn_unit *func, if (cif->rtype == &ffi_type_void) { which = 0; - } else if (cif->rtype->size == 4) { - which = 1; } else { - tcg_debug_assert(cif->rtype->size == 8); - which = 2; + tcg_debug_assert(cif->rtype->size == 4 || + cif->rtype->size == 8 || + cif->rtype->size == 16); + which = ctz32(cif->rtype->size) - 1; } new_pool_l2(s, 20, s->code_ptr, 0, (uintptr_t)func, (uintptr_t)cif); insn = deposit32(insn, 0, 8, INDEX_op_call); -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:38:11 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELZa-00058N-2P for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:38:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZU-00050l-Na for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:04 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZ1-0004au-CZ for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:04 -0500 Received: by mail-pj1-x102b.google.com with SMTP id v23so5381834pju.3 for ; Sat, 07 Jan 2023 18:37:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SYNYnzLrz9KCAUVy04IP4XZxPYGmUgBISTp436OAjA8=; b=i0jDnogA64Due9yw/UDbb1XKEp/8G1rQe0SaHxorUsaF11wfqxf2D78zX4+c/iSkpe U2HuRf9lbbYpXQuhKEi5e/JeCsqXyGYToOUNjJcGEoREWs4zSkQqYDhJuQRGQBLyuhTP sWvzK5Pu0m9nLIC5JBUvT2hQHnGMQ38bKUqB6ZbZrehHaB/Ok9Sn0Xe9D0vYRWlWloqL WO8zGyrhSrCDg2dqR167owWWUoSQ174hORLN2nETjlm9l7MTxDsyqfQ/MYgLyN4OHyV0 ewSwS25qCpIa5sFWzv6JSzUfrsuvstTsFB6U0t40mB/mc6AXLARQmI2U6gJZ3wguXdEf ea3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SYNYnzLrz9KCAUVy04IP4XZxPYGmUgBISTp436OAjA8=; b=ZZaGCvzprI09It271J7d5r0mdBxMvR5bEG4eNnEQebM7ncnBE8T2tSbwD+gxqfeLIx YI8kArQU/yB1btNwZOqIuoQ7o8BbuCNpq5Idm7wqCS3BkZtTA1Sl44ZS0rdybAtxfpCV SdMB/iy3cQLV2ur9tr+pERCJBdUIeqDqr81y0QtOFgSseRxF98jvWfhCuFgSxldQe37L P+ku9z1NmKgzBLjnURmw2fDhqP+X0xOt/13l4Tw9kEizXK05gLEnZCedYoPlw+vqvZDZ JA/MHiu+hVkqJsrH7Vmp85I7UxKFIcxEHe/yb8P7lSgHPiIhthQvmPlIWlYguNxZMuoW gB6Q== X-Gm-Message-State: AFqh2kr3TzJ+82pOcyIacMc5Ld1Ue/IJTbTb0jML9QX7BqXcP+rapY0J I27UVvxUF8V4uPcP2lPprJeRwQ== X-Google-Smtp-Source: AMrXdXs+3gNs3Ev1jM9l4SMzyEnMrkvzF+53ye41hrfMd88yxy3I30G6bAQ+am7WJuy6sJ4EX/6FsQ== X-Received: by 2002:a05:6a20:320e:b0:b5:6ebf:754c with SMTP id y14-20020a056a20320e00b000b56ebf754cmr12336057pzc.37.1673145454134; Sat, 07 Jan 2023 18:37:34 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Daniel Henrique Barboza Subject: [PATCH v4 12/36] tcg: Add TCG_TARGET_CALL_{RET,ARG}_I128 Date: Sat, 7 Jan 2023 18:36:55 -0800 Message-Id: <20230108023719.2466341-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:38:05 -0000 Fill in the parameters for the host ABI for Int128 for those backends which require no extra modification. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 2 ++ tcg/loongarch64/tcg-target.h | 2 ++ tcg/mips/tcg-target.h | 2 ++ tcg/riscv/tcg-target.h | 3 +++ tcg/s390x/tcg-target.h | 2 ++ tcg/sparc64/tcg-target.h | 2 ++ tcg/tcg.c | 6 +++--- tcg/ppc/tcg-target.c.inc | 3 +++ 9 files changed, 21 insertions(+), 3 deletions(-) diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 413a5410c5..0253e226d1 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -54,6 +54,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL /* optional instructions */ #define TCG_TARGET_HAS_div_i32 1 diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index b7843d2d54..6613d3d791 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -91,6 +91,8 @@ extern bool use_neon_instructions; #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF /* optional instructions */ #define TCG_TARGET_HAS_ext8s_i32 1 diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index e5f7a1f09d..9d0db8fdfe 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -95,6 +95,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL /* optional instructions */ #define TCG_TARGET_HAS_movcond_i32 0 diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 15721c3e42..b235cba8ba 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -89,6 +89,8 @@ typedef enum { # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #endif #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL /* MOVN/MOVZ instructions detection */ #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \ diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 232537ccea..d61ca902d3 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -85,9 +85,12 @@ typedef enum { #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL #if TCG_TARGET_REG_BITS == 32 #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN #else #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL #endif +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL /* optional instructions */ #define TCG_TARGET_HAS_movcond_i32 0 diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h index 22d70d431b..aca22efeb8 100644 --- a/tcg/s390x/tcg-target.h +++ b/tcg/s390x/tcg-target.h @@ -168,6 +168,8 @@ extern uint64_t s390_facilities[3]; #define TCG_TARGET_CALL_STACK_OFFSET 160 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF #define TCG_TARGET_HAS_MEMORY_BSWAP 1 diff --git a/tcg/sparc64/tcg-target.h b/tcg/sparc64/tcg-target.h index 0044ac8d78..53cfa843da 100644 --- a/tcg/sparc64/tcg-target.h +++ b/tcg/sparc64/tcg-target.h @@ -73,6 +73,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET (128 + 6*8 + TCG_TARGET_STACK_BIAS) #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL #if defined(__VIS__) && __VIS__ >= 0x300 #define use_vis3_instructions 1 diff --git a/tcg/tcg.c b/tcg/tcg.c index 6f72d4157a..e9bb1f329f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -744,8 +744,8 @@ static void init_call_layout(TCGHelperInfo *info) break; case dh_typecode_i128: info->nr_out = 128 / TCG_TARGET_REG_BITS; - info->out_kind = TCG_CALL_RET_NORMAL; /* TODO */ - switch (/* TODO */ TCG_CALL_RET_NORMAL) { + info->out_kind = TCG_TARGET_CALL_RET_I128; + switch (TCG_TARGET_CALL_RET_I128) { case TCG_CALL_RET_NORMAL: /* Query the last register now to trigger any assert early. */ tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); @@ -833,7 +833,7 @@ static void init_call_layout(TCGHelperInfo *info) break; case TCG_TYPE_I128: - switch (/* TODO */ TCG_CALL_ARG_NORMAL) { + switch (TCG_TARGET_CALL_ARG_I128) { case TCG_CALL_ARG_EVEN: layout_arg_even(&cum); /* fall through */ diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index d31e6c3de4..38d6e2ed21 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -54,6 +54,9 @@ #else # define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL #endif +/* Note sysv arg alignment applies only to 2-word types, not more. */ +#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL +#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL /* For some memory operations, we need a scratch that isn't R0. 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 14/36] tcg: Add basic data movement for TCGv_i128 Date: Sat, 7 Jan 2023 18:36:57 -0800 Message-Id: <20230108023719.2466341-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:38:13 -0000 Add code generation functions for data movement between TCGv_i128 (mov) and to/from TCGv_i64 (concat, extract). Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 4 ++++ tcg/tcg-internal.h | 13 +++++++++++++ tcg/tcg-op.c | 20 ++++++++++++++++++++ 3 files changed, 37 insertions(+) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 79b1cf786f..c4276767d1 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -712,6 +712,10 @@ void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg); void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg); void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg); +void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src); +void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg); +void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi); + static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi) { tcg_gen_deposit_i64(ret, lo, hi, 32, 32); diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 33f1d8b411..e542a4e9b7 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -117,4 +117,17 @@ extern TCGv_i32 TCGV_LOW(TCGv_i64) QEMU_ERROR("32-bit code path is reachable"); extern TCGv_i32 TCGV_HIGH(TCGv_i64) QEMU_ERROR("32-bit code path is reachable"); #endif +static inline TCGv_i64 TCGV128_LOW(TCGv_i128 t) +{ + /* For 32-bit, offset by 2, which may then have TCGV_{LOW,HIGH} applied. */ + int o = HOST_BIG_ENDIAN ? 64 / TCG_TARGET_REG_BITS : 0; + return temp_tcgv_i64(tcgv_i128_temp(t) + o); +} + +static inline TCGv_i64 TCGV128_HIGH(TCGv_i128 t) +{ + int o = HOST_BIG_ENDIAN ? 0 : 64 / TCG_TARGET_REG_BITS; + return temp_tcgv_i64(tcgv_i128_temp(t) + o); +} + #endif /* TCG_INTERNAL_H */ diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index cd1cd4e736..658cee7d6c 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -2745,6 +2745,26 @@ void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg) tcg_gen_shri_i64(hi, arg, 32); } +void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg) +{ + tcg_gen_mov_i64(lo, TCGV128_LOW(arg)); + tcg_gen_mov_i64(hi, TCGV128_HIGH(arg)); +} + +void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi) +{ + tcg_gen_mov_i64(TCGV128_LOW(ret), lo); + tcg_gen_mov_i64(TCGV128_HIGH(ret), hi); +} + +void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src) +{ + if (dst != src) { + tcg_gen_mov_i64(TCGV128_LOW(dst), TCGV128_LOW(src)); + tcg_gen_mov_i64(TCGV128_HIGH(dst), TCGV128_HIGH(src)); + } +} + /* QEMU specific operations. */ void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx) -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:38:19 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELZh-0005GL-2T for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:38:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZc-0005Ax-HD for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:13 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZ2-0004bO-Lq for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:12 -0500 Received: by mail-pj1-x1034.google.com with SMTP id v13-20020a17090a6b0d00b00219c3be9830so5819153pjj.4 for ; Sat, 07 Jan 2023 18:37:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aqGBKhQ5AgkdFtp5J1OJW+jsP9G85axr6xXMVQ+qicY=; b=QefVl/VVnrGkxsT2QTgsW/LhAU89JsLZVSkjOSX/LreGzAMlXna4UQ6vk0EaHAX77q Ut637GZHonFO+qNseAieDkWh4xlO0pB4JW1VFT7ibxuJmB/bqZr2mbUAXbFzZv6CM0XF dddeCmSO8a/pZK4mKlyxODOK0EdO6X7X+Q+M5Yq/WOp/DzJ2bu7pO+cXBxrmXfZhCh5S nW2q2lYPj/x6q+RFePUII07bjK3nwkU+2YkoHbAN3CkoYCHf0NMLV5DoFAfLeJAAEQbe FgkHrJ5Dm4+UZjS+3jkKp2bc28ab2lvB8spjJQgkjcV7WwPmv1RXVDf7sWzN6z4LKPlM NRlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aqGBKhQ5AgkdFtp5J1OJW+jsP9G85axr6xXMVQ+qicY=; b=7g27wJdnGD81XXeNIlHs9541JU07SXvZwIuWrWgcA5KJizxHzIzR5dtwDUgCvDA1SU uu4fBB84NTWBayG9+KbCOKZFniAfqwKj6eYH4l9O25TdCtgds6LPK7Xr+uuk6H3CXEnp lrxfUdHsuKtnM/rB71Wl6D1DRtj2+jOr92J0fSbg5IovuOUXpG5xhitGqHdcwk5pxSLi sMU0PY3xF7AhjaZqKEF+VqVrvXoOZ2OF80q1loHLJ/GEQsDNA8n11sfL/0evBrgV67zH sqnhgNfvMhJo1t3jCXTyk38xX2M8EDOhOJfB/C3TzJm3tZD4giyRMdQPPHAZ9FiI5jmy k/sQ== X-Gm-Message-State: AFqh2kqI7sf1DeEpuuOfXlTEfs6KWOhNoZwq1qXYodKqCica07PgWAu5 CX6mjIcoB0Mk9keTHhUoKo8IfdeZemcW82l7 X-Google-Smtp-Source: AMrXdXvPx5V0nWs3XUZjBLeT0ki8TLbXHr+9q7xtTCl3hU+bSDtNoW+bFe6bjMROFXzto5wOqbxdSQ== X-Received: by 2002:a17:902:a510:b0:192:48d1:f06c with SMTP id s16-20020a170902a51000b0019248d1f06cmr55734540plq.35.1673145455267; Sat, 07 Jan 2023 18:37:35 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 13/36] tcg: Add temp allocation for TCGv_i128 Date: Sat, 7 Jan 2023 18:36:56 -0800 Message-Id: <20230108023719.2466341-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:38:13 -0000 This enables allocation of i128. The type is not yet usable, as we have not yet added data movement ops. Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 32 +++++++++++++++++++++++++ tcg/tcg.c | 60 +++++++++++++++++++++++++++++++++-------------- 2 files changed, 74 insertions(+), 18 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 7d346192ca..a996da60b5 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -697,6 +697,11 @@ static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) return tcgv_i32_temp((TCGv_i32)v); } +static inline TCGTemp *tcgv_i128_temp(TCGv_i128 v) +{ + return tcgv_i32_temp((TCGv_i32)v); +} + static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) { return tcgv_i32_temp((TCGv_i32)v); @@ -717,6 +722,11 @@ static inline TCGArg tcgv_i64_arg(TCGv_i64 v) return temp_arg(tcgv_i64_temp(v)); } +static inline TCGArg tcgv_i128_arg(TCGv_i128 v) +{ + return temp_arg(tcgv_i128_temp(v)); +} + static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) { return temp_arg(tcgv_ptr_temp(v)); @@ -738,6 +748,11 @@ static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) return (TCGv_i64)temp_tcgv_i32(t); } +static inline TCGv_i128 temp_tcgv_i128(TCGTemp *t) +{ + return (TCGv_i128)temp_tcgv_i32(t); +} + static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) { return (TCGv_ptr)temp_tcgv_i32(t); @@ -860,6 +875,11 @@ static inline void tcg_temp_free_i64(TCGv_i64 arg) tcg_temp_free_internal(tcgv_i64_temp(arg)); } +static inline void tcg_temp_free_i128(TCGv_i128 arg) +{ + tcg_temp_free_internal(tcgv_i128_temp(arg)); +} + static inline void tcg_temp_free_ptr(TCGv_ptr arg) { tcg_temp_free_internal(tcgv_ptr_temp(arg)); @@ -908,6 +928,18 @@ static inline TCGv_i64 tcg_temp_local_new_i64(void) return temp_tcgv_i64(t); } +static inline TCGv_i128 tcg_temp_new_i128(void) +{ + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, false); + return temp_tcgv_i128(t); +} + +static inline TCGv_i128 tcg_temp_local_new_i128(void) +{ + TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, true); + return temp_tcgv_i128(t); +} + static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, const char *name) { diff --git a/tcg/tcg.c b/tcg/tcg.c index e9bb1f329f..2ab012a095 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1251,26 +1251,45 @@ TCGTemp *tcg_temp_new_internal(TCGType type, bool temp_local) tcg_debug_assert(ts->base_type == type); tcg_debug_assert(ts->kind == kind); } else { + int i, n; + + switch (type) { + case TCG_TYPE_I32: + case TCG_TYPE_V64: + case TCG_TYPE_V128: + case TCG_TYPE_V256: + n = 1; + break; + case TCG_TYPE_I64: + n = 64 / TCG_TARGET_REG_BITS; + break; + case TCG_TYPE_I128: + n = 128 / TCG_TARGET_REG_BITS; + break; + default: + g_assert_not_reached(); + } + ts = tcg_temp_alloc(s); - if (TCG_TARGET_REG_BITS == 32 && type == TCG_TYPE_I64) { - TCGTemp *ts2 = tcg_temp_alloc(s); + ts->base_type = type; + ts->temp_allocated = 1; + ts->kind = kind; - ts->base_type = type; - ts->type = TCG_TYPE_I32; - ts->temp_allocated = 1; - ts->kind = kind; - - tcg_debug_assert(ts2 == ts + 1); - ts2->base_type = TCG_TYPE_I64; - ts2->type = TCG_TYPE_I32; - ts2->temp_allocated = 1; - ts2->temp_subindex = 1; - ts2->kind = kind; - } else { - ts->base_type = type; + if (n == 1) { ts->type = type; - ts->temp_allocated = 1; - ts->kind = kind; + } else { + ts->type = TCG_TYPE_REG; + + for (i = 1; i < n; ++i) { + TCGTemp *ts2 = tcg_temp_alloc(s); + + tcg_debug_assert(ts2 == ts + i); + ts2->base_type = type; + ts2->type = TCG_TYPE_REG; + ts2->temp_allocated = 1; + ts2->temp_subindex = i; + ts2->kind = kind; + } } } @@ -3359,9 +3378,14 @@ static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) case TCG_TYPE_V64: align = 8; break; + case TCG_TYPE_I128: case TCG_TYPE_V128: case TCG_TYPE_V256: - /* Note that we do not require aligned storage for V256. */ + /* + * Note that we do not require aligned storage for V256, + * and that we provide alignment for I128 to match V128, + * even if that's above what the host ABI requires. + */ align = 16; break; default: -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:38:24 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELZm-0005Ir-LD for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:38:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZf-0005D3-4M for qemu-riscv@nongnu.org; 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 15/36] tcg: Add guest load/store primitives for TCGv_i128 Date: Sat, 7 Jan 2023 18:36:58 -0800 Message-Id: <20230108023719.2466341-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:38:15 -0000 These are not yet considering atomicity of the 16-byte value; this is a direct replacement for the current target code which uses a pair of 8-byte operations. Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 10 +++ include/tcg/tcg-op.h | 2 + accel/tcg/cputlb.c | 112 +++++++++++++++++++++++++++++++++ accel/tcg/user-exec.c | 66 ++++++++++++++++++++ tcg/tcg-op.c | 134 ++++++++++++++++++++++++++++++++++++++++ 5 files changed, 324 insertions(+) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index d0c7c0d5fe..09b55cc0ee 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -220,6 +220,11 @@ uint32_t cpu_ldl_le_mmu(CPUArchState *env, abi_ptr ptr, uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr ptr, MemOpIdx oi, uintptr_t ra); +Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra); +Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra); + void cpu_stb_mmu(CPUArchState *env, abi_ptr ptr, uint8_t val, MemOpIdx oi, uintptr_t ra); void cpu_stw_be_mmu(CPUArchState *env, abi_ptr ptr, uint16_t val, @@ -235,6 +240,11 @@ void cpu_stl_le_mmu(CPUArchState *env, abi_ptr ptr, uint32_t val, void cpu_stq_le_mmu(CPUArchState *env, abi_ptr ptr, uint64_t val, MemOpIdx oi, uintptr_t ra); +void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr, Int128 val, + MemOpIdx oi, uintptr_t ra); +void cpu_st16_le_mmu(CPUArchState *env, abi_ptr addr, Int128 val, + MemOpIdx oi, uintptr_t ra); + uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, uint32_t cmpv, uint32_t newv, MemOpIdx oi, uintptr_t retaddr); diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index c4276767d1..e5f5b63c37 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -845,6 +845,8 @@ void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, MemOp); void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, MemOp); void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, MemOp); void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, MemOp); +void tcg_gen_qemu_ld_i128(TCGv_i128, TCGv, TCGArg, MemOp); +void tcg_gen_qemu_st_i128(TCGv_i128, TCGv, TCGArg, MemOp); static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index) { diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 4948729917..79101306a3 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2187,6 +2187,64 @@ uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr addr, return cpu_load_helper(env, addr, oi, ra, helper_le_ldq_mmu); } +Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop = get_memop(oi); + int mmu_idx = get_mmuidx(oi); + MemOpIdx new_oi; + unsigned a_bits; + uint64_t h, l; + + tcg_debug_assert((mop & (MO_BSWAP|MO_SSIZE)) == (MO_BE|MO_128)); + a_bits = get_alignment_bits(mop); + + /* Handle CPU specific unaligned behaviour */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_LOAD, + mmu_idx, ra); + } + + /* Construct an unaligned 64-bit replacement MemOpIdx. */ + mop = (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; + new_oi = make_memop_idx(mop, mmu_idx); + + h = helper_be_ldq_mmu(env, addr, new_oi, ra); + l = helper_be_ldq_mmu(env, addr + 8, new_oi, ra); + + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + return int128_make128(l, h); +} + +Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop = get_memop(oi); + int mmu_idx = get_mmuidx(oi); + MemOpIdx new_oi; + unsigned a_bits; + uint64_t h, l; + + tcg_debug_assert((mop & (MO_BSWAP|MO_SSIZE)) == (MO_LE|MO_128)); + a_bits = get_alignment_bits(mop); + + /* Handle CPU specific unaligned behaviour */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_LOAD, + mmu_idx, ra); + } + + /* Construct an unaligned 64-bit replacement MemOpIdx. */ + mop = (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; + new_oi = make_memop_idx(mop, mmu_idx); + + l = helper_le_ldq_mmu(env, addr, new_oi, ra); + h = helper_le_ldq_mmu(env, addr + 8, new_oi, ra); + + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + return int128_make128(l, h); +} + /* * Store Helpers */ @@ -2541,6 +2599,60 @@ void cpu_stq_le_mmu(CPUArchState *env, target_ulong addr, uint64_t val, cpu_store_helper(env, addr, val, oi, retaddr, helper_le_stq_mmu); } +void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr, Int128 val, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop = get_memop(oi); + int mmu_idx = get_mmuidx(oi); + MemOpIdx new_oi; + unsigned a_bits; + + tcg_debug_assert((mop & (MO_BSWAP|MO_SSIZE)) == (MO_BE|MO_128)); + a_bits = get_alignment_bits(mop); + + /* Handle CPU specific unaligned behaviour */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, + mmu_idx, ra); + } + + /* Construct an unaligned 64-bit replacement MemOpIdx. */ + mop = (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; + new_oi = make_memop_idx(mop, mmu_idx); + + helper_be_stq_mmu(env, addr, int128_gethi(val), new_oi, ra); + helper_be_stq_mmu(env, addr + 8, int128_getlo(val), new_oi, ra); + + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); +} + +void cpu_st16_le_mmu(CPUArchState *env, abi_ptr addr, Int128 val, + MemOpIdx oi, uintptr_t ra) +{ + MemOp mop = get_memop(oi); + int mmu_idx = get_mmuidx(oi); + MemOpIdx new_oi; + unsigned a_bits; + + tcg_debug_assert((mop & (MO_BSWAP|MO_SSIZE)) == (MO_LE|MO_128)); + a_bits = get_alignment_bits(mop); + + /* Handle CPU specific unaligned behaviour */ + if (addr & ((1 << a_bits) - 1)) { + cpu_unaligned_access(env_cpu(env), addr, MMU_DATA_STORE, + mmu_idx, ra); + } + + /* Construct an unaligned 64-bit replacement MemOpIdx. */ + mop = (mop & ~(MO_SIZE | MO_AMASK)) | MO_64 | MO_UNALN; + new_oi = make_memop_idx(mop, mmu_idx); + + helper_le_stq_mmu(env, addr, int128_getlo(val), new_oi, ra); + helper_le_stq_mmu(env, addr + 8, int128_gethi(val), new_oi, ra); + + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); +} + #include "ldst_common.c.inc" /* diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index a8eb63ab96..ae67d84638 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1031,6 +1031,42 @@ uint64_t cpu_ldq_le_mmu(CPUArchState *env, abi_ptr addr, return ret; } +Int128 cpu_ld16_be_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + void *haddr; + Int128 ret; + + validate_memop(oi, MO_128 | MO_BE); + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + memcpy(&ret, haddr, 16); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + + if (!HOST_BIG_ENDIAN) { + ret = bswap128(ret); + } + return ret; +} + +Int128 cpu_ld16_le_mmu(CPUArchState *env, abi_ptr addr, + MemOpIdx oi, uintptr_t ra) +{ + void *haddr; + Int128 ret; + + validate_memop(oi, MO_128 | MO_LE); + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_LOAD); + memcpy(&ret, haddr, 16); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_R); + + if (HOST_BIG_ENDIAN) { + ret = bswap128(ret); + } + return ret; +} + void cpu_stb_mmu(CPUArchState *env, abi_ptr addr, uint8_t val, MemOpIdx oi, uintptr_t ra) { @@ -1115,6 +1151,36 @@ void cpu_stq_le_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); } +void cpu_st16_be_mmu(CPUArchState *env, abi_ptr addr, + Int128 val, MemOpIdx oi, uintptr_t ra) +{ + void *haddr; + + validate_memop(oi, MO_128 | MO_BE); + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + if (!HOST_BIG_ENDIAN) { + val = bswap128(val); + } + memcpy(haddr, &val, 16); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); +} + +void cpu_st16_le_mmu(CPUArchState *env, abi_ptr addr, + Int128 val, MemOpIdx oi, uintptr_t ra) +{ + void *haddr; + + validate_memop(oi, MO_128 | MO_LE); + haddr = cpu_mmu_lookup(env, addr, oi, ra, MMU_DATA_STORE); + if (HOST_BIG_ENDIAN) { + val = bswap128(val); + } + memcpy(haddr, &val, 16); + clear_helper_retaddr(); + qemu_plugin_vcpu_mem_cb(env_cpu(env), addr, oi, QEMU_PLUGIN_MEM_W); +} + uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr ptr) { uint32_t ret; diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 658cee7d6c..55ecedb66f 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -3107,6 +3107,140 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop) } } +static void canonicalize_memop_i128_as_i64(MemOp ret[2], MemOp orig) +{ + MemOp mop_1 = orig, mop_2; + + tcg_debug_assert((orig & MO_SIZE) == MO_128); + tcg_debug_assert((orig & MO_SIGN) == 0); + + /* Use a memory ordering implemented by the host. */ + if (!TCG_TARGET_HAS_MEMORY_BSWAP && (orig & MO_BSWAP)) { + mop_1 &= ~MO_BSWAP; + } + + /* Reduce the size to 64-bit. */ + mop_1 = (mop_1 & ~MO_SIZE) | MO_64; + + /* Retain the alignment constraints of the original. */ + switch (orig & MO_AMASK) { + case MO_UNALN: + case MO_ALIGN_2: + case MO_ALIGN_4: + mop_2 = mop_1; + break; + case MO_ALIGN_8: + /* Prefer MO_ALIGN+MO_64 to MO_ALIGN_8+MO_64. */ + mop_1 = (mop_1 & ~MO_AMASK) | MO_ALIGN; + mop_2 = mop_1; + break; + case MO_ALIGN: + /* Second has 8-byte alignment; first has 16-byte alignment. */ + mop_2 = mop_1; + mop_1 = (mop_1 & ~MO_AMASK) | MO_ALIGN_16; + break; + case MO_ALIGN_16: + case MO_ALIGN_32: + case MO_ALIGN_64: + /* Second has 8-byte alignment; first retains original. */ + mop_2 = (mop_1 & ~MO_AMASK) | MO_ALIGN; + break; + default: + g_assert_not_reached(); + } + ret[0] = mop_1; + ret[1] = mop_2; +} + +void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memop) +{ + MemOp mop[2]; + TCGv addr_p8; + TCGv_i64 x, y; + + canonicalize_memop_i128_as_i64(mop, memop); + + tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); + addr = plugin_prep_mem_callbacks(addr); + + /* TODO: respect atomicity of the operation. */ + /* TODO: allow the tcg backend to see the whole operation. */ + + /* + * Since there are no global TCGv_i128, there is no visible state + * changed if the second load faults. Load directly into the two + * subwords. + */ + if ((memop & MO_BSWAP) == MO_LE) { + x = TCGV128_LOW(val); + y = TCGV128_HIGH(val); + } else { + x = TCGV128_HIGH(val); + y = TCGV128_LOW(val); + } + + gen_ldst_i64(INDEX_op_qemu_ld_i64, x, addr, mop[0], idx); + + if ((mop[0] ^ memop) & MO_BSWAP) { + tcg_gen_bswap64_i64(x, x); + } + + addr_p8 = tcg_temp_new(); + tcg_gen_addi_tl(addr_p8, addr, 8); + gen_ldst_i64(INDEX_op_qemu_ld_i64, y, addr_p8, mop[1], idx); + tcg_temp_free(addr_p8); + + if ((mop[0] ^ memop) & MO_BSWAP) { + tcg_gen_bswap64_i64(y, y); + } + + plugin_gen_mem_callbacks(addr, make_memop_idx(memop, idx), + QEMU_PLUGIN_MEM_R); +} + +void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memop) +{ + MemOp mop[2]; + TCGv addr_p8; + TCGv_i64 x, y; + + canonicalize_memop_i128_as_i64(mop, memop); + + tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); + addr = plugin_prep_mem_callbacks(addr); + + /* TODO: respect atomicity of the operation. */ + /* TODO: allow the tcg backend to see the whole operation. */ + + if ((memop & MO_BSWAP) == MO_LE) { + x = TCGV128_LOW(val); + y = TCGV128_HIGH(val); + } else { + x = TCGV128_HIGH(val); + y = TCGV128_LOW(val); + } + + addr_p8 = tcg_temp_new(); + if ((mop[0] ^ memop) & MO_BSWAP) { + TCGv_i64 t = tcg_temp_new_i64(); + + tcg_gen_bswap64_i64(t, x); + gen_ldst_i64(INDEX_op_qemu_st_i64, t, addr, mop[0], idx); + tcg_gen_bswap64_i64(t, y); + tcg_gen_addi_tl(addr_p8, addr, 8); + gen_ldst_i64(INDEX_op_qemu_st_i64, t, addr_p8, mop[1], idx); + tcg_temp_free_i64(t); + } else { + gen_ldst_i64(INDEX_op_qemu_st_i64, x, addr, mop[0], idx); + tcg_gen_addi_tl(addr_p8, addr, 8); + gen_ldst_i64(INDEX_op_qemu_st_i64, y, addr_p8, mop[1], idx); + } + tcg_temp_free(addr_p8); + + plugin_gen_mem_callbacks(addr, make_memop_idx(memop, idx), + QEMU_PLUGIN_MEM_W); +} + static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc) { switch (opc & MO_SSIZE) { -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:38:24 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELZo-0005JV-6U for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:38:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZf-0005EC-O6 for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:15 -0500 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZ5-0004d1-LA for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:15 -0500 Received: by mail-pj1-x1032.google.com with SMTP id m7-20020a17090a730700b00225ebb9cd01so9263479pjk.3 for ; Sat, 07 Jan 2023 18:37:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tmU0MjgiKsSxPUHRGzRVInhdiWEFNbDXapXPwryhCsg=; b=dVPjSWSVfw3dl+K0WrjZQUtWVtasW1reVIEELlM9F/TvOFEnsRyHTV7neQKKF0yDq0 zWZ7VC8avBIbay8SO1uxz1pN7XNarj00p0ljqQio0+igPCW075mN1y3Kk+BVFZ/TVkl1 H14q04qgtIopeXhtxBT82aELAfULRloENIut2Uk/8piyu4a+jMIvsLkCTj06VNuJOcGA vQtUBveoUTqvGYhZkytToXTi/1sweQfKDUV4TOGHFkFbI7Ddby6iIhVB6fkmJLJV8EsH 2Q05RxM9udcCSC493hceEzCq3fyyQWSKrpPuAgOZ7a6VATnDEo+9zDl6MbsEeJwfpb2W 1z/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tmU0MjgiKsSxPUHRGzRVInhdiWEFNbDXapXPwryhCsg=; b=VOkEEV9WacWQTNQxD9Bu9ge0i4PkqJlxWBZNuv1IaGry1lFyUEFveQXDYc2ZFPSRgK sScIoL3rzJIXuwGN/jtnOyEBku9wCTGxKRoIhE0em1opSNs6W/ppe9K18EHvKvFAo55G 7bpZcOrsHwLoHh2Kku3d5gqsn4QG/sL9FRZ4kjNOQWSoQexdQ6tWHyAkO/JFL9Es2Fij K4pCzoAEOxK2NnNm2kt/8patHQt6pGV47SnILVDdSPyfdatJr1cmNcJTU8vZcF7M0o/I uxniqJbC6WQ8lpMmHuEDT/Q6AnxSFbJzS+76VPMRZzefBGHjn+eFSzrys1xfPcPupS3e iaDQ== X-Gm-Message-State: AFqh2kom/QBvHsKyEUE+DfA1H4t1jETpMNdkwQROJ9szpU+rpg+s3luw GYbyK7BzAIyBSUWW7uphGiPZ/w== X-Google-Smtp-Source: AMrXdXtQAF1iIe2yb+kn0a3+q+s7wVHxHtEe1ezf/KHN5Ycay/z3DWneG/bBUmfvL2X0omsUa/PkLA== X-Received: by 2002:a17:902:8e86:b0:192:b43e:272 with SMTP id bg6-20020a1709028e8600b00192b43e0272mr28292109plb.53.1673145458376; Sat, 07 Jan 2023 18:37:38 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 16/36] tcg: Add tcg_gen_{non}atomic_cmpxchg_i128 Date: Sat, 7 Jan 2023 18:36:59 -0800 Message-Id: <20230108023719.2466341-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:38:16 -0000 This will allow targets to avoid rolling their own. Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 11 +++++ include/tcg/tcg-op.h | 5 +++ tcg/tcg-op.c | 85 +++++++++++++++++++++++++++++++++++ accel/tcg/atomic_common.c.inc | 45 +++++++++++++++++++ 4 files changed, 146 insertions(+) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index 37cbd722bf..e141a6ab24 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -55,6 +55,17 @@ DEF_HELPER_FLAGS_5(atomic_cmpxchgq_be, TCG_CALL_NO_WG, DEF_HELPER_FLAGS_5(atomic_cmpxchgq_le, TCG_CALL_NO_WG, i64, env, tl, i64, i64, i32) #endif +#ifdef CONFIG_CMPXCHG128 +DEF_HELPER_FLAGS_5(atomic_cmpxchgo_be, TCG_CALL_NO_WG, + i128, env, tl, i128, i128, i32) +DEF_HELPER_FLAGS_5(atomic_cmpxchgo_le, TCG_CALL_NO_WG, + i128, env, tl, i128, i128, i32) +#endif + +DEF_HELPER_FLAGS_5(nonatomic_cmpxchgo_be, TCG_CALL_NO_WG, + i128, env, tl, i128, i128, i32) +DEF_HELPER_FLAGS_5(nonatomic_cmpxchgo_le, TCG_CALL_NO_WG, + i128, env, tl, i128, i128, i32) #ifdef CONFIG_ATOMIC64 #define GEN_ATOMIC_HELPERS(NAME) \ diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index e5f5b63c37..31bf3d287e 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -907,6 +907,11 @@ void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32, TCGArg, MemOp); void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, TCGArg, MemOp); +void tcg_gen_atomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, + TCGArg, MemOp); + +void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, + TCGArg, MemOp); void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp); void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 55ecedb66f..66f9c894ad 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -3293,6 +3293,8 @@ typedef void (*gen_atomic_cx_i32)(TCGv_i32, TCGv_env, TCGv, TCGv_i32, TCGv_i32, TCGv_i32); typedef void (*gen_atomic_cx_i64)(TCGv_i64, TCGv_env, TCGv, TCGv_i64, TCGv_i64, TCGv_i32); +typedef void (*gen_atomic_cx_i128)(TCGv_i128, TCGv_env, TCGv, + TCGv_i128, TCGv_i128, TCGv_i32); typedef void (*gen_atomic_op_i32)(TCGv_i32, TCGv_env, TCGv, TCGv_i32, TCGv_i32); typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv, @@ -3303,6 +3305,11 @@ typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env, TCGv, #else # define WITH_ATOMIC64(X) #endif +#ifdef CONFIG_CMPXCHG128 +# define WITH_ATOMIC128(X) X, +#else +# define WITH_ATOMIC128(X) +#endif static void * const table_cmpxchg[(MO_SIZE | MO_BSWAP) + 1] = { [MO_8] = gen_helper_atomic_cmpxchgb, @@ -3312,6 +3319,8 @@ static void * const table_cmpxchg[(MO_SIZE | MO_BSWAP) + 1] = { [MO_32 | MO_BE] = gen_helper_atomic_cmpxchgl_be, WITH_ATOMIC64([MO_64 | MO_LE] = gen_helper_atomic_cmpxchgq_le) WITH_ATOMIC64([MO_64 | MO_BE] = gen_helper_atomic_cmpxchgq_be) + WITH_ATOMIC128([MO_128 | MO_LE] = gen_helper_atomic_cmpxchgo_le) + WITH_ATOMIC128([MO_128 | MO_BE] = gen_helper_atomic_cmpxchgo_be) }; void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, @@ -3410,6 +3419,82 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, } } +void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128 retv, TCGv addr, TCGv_i128 cmpv, + TCGv_i128 newv, TCGArg idx, MemOp memop) +{ + if (TCG_TARGET_REG_BITS == 32) { + /* Inline expansion below is simply too large for 32-bit hosts. */ + gen_atomic_cx_i128 gen = ((memop & MO_BSWAP) == MO_LE + ? gen_helper_nonatomic_cmpxchgo_le + : gen_helper_nonatomic_cmpxchgo_be); + MemOpIdx oi = make_memop_idx(memop, idx); + + tcg_debug_assert((memop & MO_SIZE) == MO_128); + tcg_debug_assert((memop & MO_SIGN) == 0); + + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + } else { + TCGv_i128 oldv = tcg_temp_new_i128(); + TCGv_i128 tmpv = tcg_temp_new_i128(); + TCGv_i64 t0 = tcg_temp_new_i64(); + TCGv_i64 t1 = tcg_temp_new_i64(); + TCGv_i64 z = tcg_constant_i64(0); + + tcg_gen_qemu_ld_i128(oldv, addr, idx, memop); + + /* Compare i128 */ + tcg_gen_xor_i64(t0, TCGV128_LOW(oldv), TCGV128_LOW(cmpv)); + tcg_gen_xor_i64(t1, TCGV128_HIGH(oldv), TCGV128_HIGH(cmpv)); + tcg_gen_or_i64(t0, t0, t1); + + /* tmpv = equal ? newv : oldv */ + tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_LOW(tmpv), t0, z, + TCGV128_LOW(newv), TCGV128_LOW(oldv)); + tcg_gen_movcond_i64(TCG_COND_EQ, TCGV128_HIGH(tmpv), t0, z, + TCGV128_HIGH(newv), TCGV128_HIGH(oldv)); + + /* Unconditional writeback. */ + tcg_gen_qemu_st_i128(tmpv, addr, idx, memop); + tcg_gen_mov_i128(retv, oldv); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i128(tmpv); + tcg_temp_free_i128(oldv); + } +} + +void tcg_gen_atomic_cmpxchg_i128(TCGv_i128 retv, TCGv addr, TCGv_i128 cmpv, + TCGv_i128 newv, TCGArg idx, MemOp memop) +{ + gen_atomic_cx_i128 gen; + + if (!(tcg_ctx->tb_cflags & CF_PARALLEL)) { + tcg_gen_nonatomic_cmpxchg_i128(retv, addr, cmpv, newv, idx, memop); + return; + } + + tcg_debug_assert((memop & MO_SIZE) == MO_128); + tcg_debug_assert((memop & MO_SIGN) == 0); + gen = table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; + + if (gen) { + MemOpIdx oi = make_memop_idx(memop, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + return; + } + + gen_helper_exit_atomic(cpu_env); + + /* + * Produce a result for a well-formed opcode stream. This satisfies + * liveness for set before used, which happens before this dead code + * is removed. + */ + tcg_gen_movi_i64(TCGV128_LOW(retv), 0); + tcg_gen_movi_i64(TCGV128_HIGH(retv), 0); +} + static void do_nonatomic_op_i32(TCGv_i32 ret, TCGv addr, TCGv_i32 val, TCGArg idx, MemOp memop, bool new_val, void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32)) diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc index 6602d7689f..8f2ce43ee6 100644 --- a/accel/tcg/atomic_common.c.inc +++ b/accel/tcg/atomic_common.c.inc @@ -55,8 +55,53 @@ CMPXCHG_HELPER(cmpxchgq_be, uint64_t) CMPXCHG_HELPER(cmpxchgq_le, uint64_t) #endif +#ifdef CONFIG_CMPXCHG128 +CMPXCHG_HELPER(cmpxchgo_be, Int128) +CMPXCHG_HELPER(cmpxchgo_le, Int128) +#endif + #undef CMPXCHG_HELPER +Int128 HELPER(nonatomic_cmpxchgo_be)(CPUArchState *env, target_ulong addr, + Int128 cmpv, Int128 newv, uint32_t oi) +{ +#if TCG_TARGET_REG_BITS == 32 + uintptr_t ra = GETPC(); + Int128 oldv; + + oldv = cpu_ld16_be_mmu(env, addr, oi, ra); + if (int128_eq(oldv, cmpv)) { + cpu_st16_be_mmu(env, addr, newv, oi, ra); + } else { + /* Even with comparison failure, still need a write cycle. */ + probe_write(env, addr, 16, get_mmuidx(oi), ra); + } + return oldv; +#else + g_assert_not_reached(); +#endif +} + +Int128 HELPER(nonatomic_cmpxchgo_le)(CPUArchState *env, target_ulong addr, + Int128 cmpv, Int128 newv, uint32_t oi) +{ +#if TCG_TARGET_REG_BITS == 32 + uintptr_t ra = GETPC(); + Int128 oldv; + + oldv = cpu_ld16_le_mmu(env, addr, oi, ra); + if (int128_eq(oldv, cmpv)) { + cpu_st16_le_mmu(env, addr, newv, oi, ra); + } else { + /* Even with comparison failure, still need a write cycle. */ + probe_write(env, addr, 16, get_mmuidx(oi), ra); + } + return oldv; +#else + g_assert_not_reached(); +#endif +} + #define ATOMIC_HELPER(OP, TYPE) \ TYPE HELPER(glue(atomic_,OP))(CPUArchState *env, target_ulong addr, \ TYPE val, uint32_t oi) \ -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:38:26 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELZq-0005Np-2Q for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:38:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZo-0005JF-03 for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:24 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZ8-0004eT-4i for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:23 -0500 Received: by mail-pl1-x629.google.com with SMTP id b2so5869421pld.7 for ; Sat, 07 Jan 2023 18:37:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fBe81AYf+h+ZBpFhnMwhRAiDvhJXmvmqR7+o6P3dQKY=; b=HqXY6QIZgmvawjIMl3xMJ+aoWYtOfrLlUlA0s5tRnenWNZLVzfkHXGy7jwBYQUN6++ Ed6Tm901X5LaW/9Y3Hdq/hgXD2gyAlBRaGe0LPwU5aQVpBBdM70dqGH4sXoEIOGHIVZ+ ruR8vQl+ahTo0jdu62U5XjA+ks5UjaPSZXEeAP4NcpIZdurGIfyJcb6jfdyMblM+7vMG uRcU+cWFX245qQLmY4ASYJalf/Ludn4UBjOfmhFP8uyxppxy0qQ0ymbOiZpTQoYgfbBD 0op5yO6l1U6/k7sk62SxzevKl66RzUSrYRInOhfxwHhpQZ+Ux3CzqO50NJjThU4q4SfQ 3JvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fBe81AYf+h+ZBpFhnMwhRAiDvhJXmvmqR7+o6P3dQKY=; b=iF3h20WsTxeQnk+VErJHr2FvbFnaIU9ygYxLrYvW7eEihFqlgvGgnA14+zJ3BvLwgo PuzM8+ps7pnHTzaMON5ndnKHm6zFF7UOuY8Br/JcEJI85MXGBfRA3Yh8T1waokmz5mMB zvzuDuOSaFj9EQgJqYySabLAw0PLWfzg8v2MVKp1pieMcDIaK7x8BRaypk+t0mx7iFzr NacaKwcW0kjQxApJRkE8m3dBWwAmr3wxbsSprxBYIw5zgY68TM/WFXbAWw7NuoAkl7Ym uodbDiURV7vbwy8Wb1tcRTRH5qSiT37qK+mlIpZMnQXkLLqxkczoCt1QioVDSn0BtqzP r1zw== X-Gm-Message-State: AFqh2kpAhQeIXFe6eIcRrNUMClttnFomY1RseLKWgFDq6TDf1urbysE8 H8Fb1WxQj0MPedW5o27+4T6Nkw== X-Google-Smtp-Source: AMrXdXu9WbTIehrcLnC9zTxNY2PRsME1mrOkgpADNMYOsfQtdQMwvDweeTeOPHJ670PkKIo5VGMeRw== X-Received: by 2002:a17:902:f80c:b0:185:441e:90dd with SMTP id ix12-20020a170902f80c00b00185441e90ddmr67708680plb.67.1673145460792; Sat, 07 Jan 2023 18:37:40 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Peter Maydell Subject: [PATCH v4 18/36] target/arm: Use tcg_gen_atomic_cmpxchg_i128 for STXP Date: Sat, 7 Jan 2023 18:37:01 -0800 Message-Id: <20230108023719.2466341-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:38:24 -0000 Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20221112042555.2622152-2-richard.henderson@linaro.org> --- target/arm/helper-a64.h | 6 --- target/arm/helper-a64.c | 104 ------------------------------------- target/arm/translate-a64.c | 60 ++++++++++++--------- 3 files changed, 35 insertions(+), 135 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 7b706571bb..94065d1917 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -50,12 +50,6 @@ DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, ptr) DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env) DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) -DEF_HELPER_FLAGS_4(paired_cmpxchg64_le, TCG_CALL_NO_WG, i64, env, i64, i64, i64) -DEF_HELPER_FLAGS_4(paired_cmpxchg64_le_parallel, TCG_CALL_NO_WG, - i64, env, i64, i64, i64) -DEF_HELPER_FLAGS_4(paired_cmpxchg64_be, TCG_CALL_NO_WG, i64, env, i64, i64, i64) -DEF_HELPER_FLAGS_4(paired_cmpxchg64_be_parallel, TCG_CALL_NO_WG, - i64, env, i64, i64, i64) DEF_HELPER_5(casp_le_parallel, void, env, i32, i64, i64, i64) DEF_HELPER_5(casp_be_parallel, void, env, i32, i64, i64, i64) DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 77a8502b6b..7dbdb2c233 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -505,110 +505,6 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes) return crc32c(acc, buf, bytes) ^ 0xffffffff; } -uint64_t HELPER(paired_cmpxchg64_le)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) -{ - Int128 cmpv = int128_make128(env->exclusive_val, env->exclusive_high); - Int128 newv = int128_make128(new_lo, new_hi); - Int128 oldv; - uintptr_t ra = GETPC(); - uint64_t o0, o1; - bool success; - int mem_idx = cpu_mmu_index(env, false); - MemOpIdx oi0 = make_memop_idx(MO_LEUQ | MO_ALIGN_16, mem_idx); - MemOpIdx oi1 = make_memop_idx(MO_LEUQ, mem_idx); - - o0 = cpu_ldq_le_mmu(env, addr + 0, oi0, ra); - o1 = cpu_ldq_le_mmu(env, addr + 8, oi1, ra); - oldv = int128_make128(o0, o1); - - success = int128_eq(oldv, cmpv); - if (success) { - cpu_stq_le_mmu(env, addr + 0, int128_getlo(newv), oi1, ra); - cpu_stq_le_mmu(env, addr + 8, int128_gethi(newv), oi1, ra); - } - - return !success; -} - -uint64_t HELPER(paired_cmpxchg64_le_parallel)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) -{ - Int128 oldv, cmpv, newv; - uintptr_t ra = GETPC(); - bool success; - int mem_idx; - MemOpIdx oi; - - assert(HAVE_CMPXCHG128); - - mem_idx = cpu_mmu_index(env, false); - oi = make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); - - cmpv = int128_make128(env->exclusive_val, env->exclusive_high); - newv = int128_make128(new_lo, new_hi); - oldv = cpu_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra); - - success = int128_eq(oldv, cmpv); - return !success; -} - -uint64_t HELPER(paired_cmpxchg64_be)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) -{ - /* - * High and low need to be switched here because this is not actually a - * 128bit store but two doublewords stored consecutively - */ - Int128 cmpv = int128_make128(env->exclusive_high, env->exclusive_val); - Int128 newv = int128_make128(new_hi, new_lo); - Int128 oldv; - uintptr_t ra = GETPC(); - uint64_t o0, o1; - bool success; - int mem_idx = cpu_mmu_index(env, false); - MemOpIdx oi0 = make_memop_idx(MO_BEUQ | MO_ALIGN_16, mem_idx); - MemOpIdx oi1 = make_memop_idx(MO_BEUQ, mem_idx); - - o1 = cpu_ldq_be_mmu(env, addr + 0, oi0, ra); - o0 = cpu_ldq_be_mmu(env, addr + 8, oi1, ra); - oldv = int128_make128(o0, o1); - - success = int128_eq(oldv, cmpv); - if (success) { - cpu_stq_be_mmu(env, addr + 0, int128_gethi(newv), oi1, ra); - cpu_stq_be_mmu(env, addr + 8, int128_getlo(newv), oi1, ra); - } - - return !success; -} - -uint64_t HELPER(paired_cmpxchg64_be_parallel)(CPUARMState *env, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) -{ - Int128 oldv, cmpv, newv; - uintptr_t ra = GETPC(); - bool success; - int mem_idx; - MemOpIdx oi; - - assert(HAVE_CMPXCHG128); - - mem_idx = cpu_mmu_index(env, false); - oi = make_memop_idx(MO_BE | MO_128 | MO_ALIGN, mem_idx); - - /* - * High and low need to be switched here because this is not actually a - * 128bit store but two doublewords stored consecutively - */ - cmpv = int128_make128(env->exclusive_high, env->exclusive_val); - newv = int128_make128(new_hi, new_lo); - oldv = cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); - - success = int128_eq(oldv, cmpv); - return !success; -} - /* Writes back the old data into Rs. */ void HELPER(casp_le_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, uint64_t new_lo, uint64_t new_hi) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 2ee171f249..dffd7ee737 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2580,32 +2580,42 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, get_mem_index(s), MO_64 | MO_ALIGN | s->be_data); tcg_gen_setcond_i64(TCG_COND_NE, tmp, tmp, cpu_exclusive_val); - } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { - if (!HAVE_CMPXCHG128) { - gen_helper_exit_atomic(cpu_env); - /* - * Produce a result so we have a well-formed opcode - * stream when the following (dead) code uses 'tmp'. - * TCG will remove the dead ops for us. - */ - tcg_gen_movi_i64(tmp, 0); - } else if (s->be_data == MO_LE) { - gen_helper_paired_cmpxchg64_le_parallel(tmp, cpu_env, - cpu_exclusive_addr, - cpu_reg(s, rt), - cpu_reg(s, rt2)); - } else { - gen_helper_paired_cmpxchg64_be_parallel(tmp, cpu_env, - cpu_exclusive_addr, - cpu_reg(s, rt), - cpu_reg(s, rt2)); - } - } else if (s->be_data == MO_LE) { - gen_helper_paired_cmpxchg64_le(tmp, cpu_env, cpu_exclusive_addr, - cpu_reg(s, rt), cpu_reg(s, rt2)); } else { - gen_helper_paired_cmpxchg64_be(tmp, cpu_env, cpu_exclusive_addr, - cpu_reg(s, rt), cpu_reg(s, rt2)); + TCGv_i128 t16 = tcg_temp_new_i128(); + TCGv_i128 c16 = tcg_temp_new_i128(); + TCGv_i64 a, b; + + if (s->be_data == MO_LE) { + tcg_gen_concat_i64_i128(t16, cpu_reg(s, rt), cpu_reg(s, rt2)); + tcg_gen_concat_i64_i128(c16, cpu_exclusive_val, + cpu_exclusive_high); + } else { + tcg_gen_concat_i64_i128(t16, cpu_reg(s, rt2), cpu_reg(s, rt)); + tcg_gen_concat_i64_i128(c16, cpu_exclusive_high, + cpu_exclusive_val); + } + + tcg_gen_atomic_cmpxchg_i128(t16, cpu_exclusive_addr, c16, t16, + get_mem_index(s), + MO_128 | MO_ALIGN | s->be_data); + tcg_temp_free_i128(c16); + + a = tcg_temp_new_i64(); + b = tcg_temp_new_i64(); + if (s->be_data == MO_LE) { + tcg_gen_extr_i128_i64(a, b, t16); + } else { + tcg_gen_extr_i128_i64(b, a, t16); + } + + tcg_gen_xor_i64(a, a, cpu_exclusive_val); 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 17/36] tcg: Split out tcg_gen_nonatomic_cmpxchg_i{32,64} Date: Sat, 7 Jan 2023 18:37:00 -0800 Message-Id: <20230108023719.2466341-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:38:19 -0000 Normally this is automatically handled by the CF_PARALLEL checks with in tcg_gen_atomic_cmpxchg_i{32,64}, but x86 has a special case of !PREFIX_LOCK where it always wants the non-atomic version. Split these out so that x86 does not have to roll its own. Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 4 ++ tcg/tcg-op.c | 154 +++++++++++++++++++++++++++---------------- 2 files changed, 101 insertions(+), 57 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 31bf3d287e..839d91c0c7 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -910,6 +910,10 @@ void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, void tcg_gen_atomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, TCGArg, MemOp); +void tcg_gen_nonatomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32, + TCGArg, MemOp); +void tcg_gen_nonatomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64, + TCGArg, MemOp); void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128, TCGArg, MemOp); diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 66f9c894ad..e7e4951a3c 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -3323,82 +3323,122 @@ static void * const table_cmpxchg[(MO_SIZE | MO_BSWAP) + 1] = { WITH_ATOMIC128([MO_128 | MO_BE] = gen_helper_atomic_cmpxchgo_be) }; +void tcg_gen_nonatomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, + TCGv_i32 newv, TCGArg idx, MemOp memop) +{ + TCGv_i32 t1 = tcg_temp_new_i32(); + TCGv_i32 t2 = tcg_temp_new_i32(); + + tcg_gen_ext_i32(t2, cmpv, memop & MO_SIZE); + + tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN); + tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, t2, newv, t1); + tcg_gen_qemu_st_i32(t2, addr, idx, memop); + tcg_temp_free_i32(t2); + + if (memop & MO_SIGN) { + tcg_gen_ext_i32(retv, t1, memop); + } else { + tcg_gen_mov_i32(retv, t1); + } + tcg_temp_free_i32(t1); +} + void tcg_gen_atomic_cmpxchg_i32(TCGv_i32 retv, TCGv addr, TCGv_i32 cmpv, TCGv_i32 newv, TCGArg idx, MemOp memop) { - memop = tcg_canonicalize_memop(memop, 0, 0); + gen_atomic_cx_i32 gen; + MemOpIdx oi; if (!(tcg_ctx->tb_cflags & CF_PARALLEL)) { - TCGv_i32 t1 = tcg_temp_new_i32(); - TCGv_i32 t2 = tcg_temp_new_i32(); - - tcg_gen_ext_i32(t2, cmpv, memop & MO_SIZE); - - tcg_gen_qemu_ld_i32(t1, addr, idx, memop & ~MO_SIGN); - tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, t2, newv, t1); - tcg_gen_qemu_st_i32(t2, addr, idx, memop); - tcg_temp_free_i32(t2); - - if (memop & MO_SIGN) { - tcg_gen_ext_i32(retv, t1, memop); - } else { - tcg_gen_mov_i32(retv, t1); - } - tcg_temp_free_i32(t1); - } else { - gen_atomic_cx_i32 gen; - MemOpIdx oi; - - gen = table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; - tcg_debug_assert(gen != NULL); - - oi = make_memop_idx(memop & ~MO_SIGN, idx); - gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); - - if (memop & MO_SIGN) { - tcg_gen_ext_i32(retv, retv, memop); - } + tcg_gen_nonatomic_cmpxchg_i32(retv, addr, cmpv, newv, idx, memop); + return; } + + memop = tcg_canonicalize_memop(memop, 0, 0); + gen = table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; + tcg_debug_assert(gen != NULL); + + oi = make_memop_idx(memop & ~MO_SIGN, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + + if (memop & MO_SIGN) { + tcg_gen_ext_i32(retv, retv, memop); + } +} + +void tcg_gen_nonatomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, + TCGv_i64 newv, TCGArg idx, MemOp memop) +{ + TCGv_i64 t1, t2; + + if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) { + tcg_gen_nonatomic_cmpxchg_i32(TCGV_LOW(retv), addr, TCGV_LOW(cmpv), + TCGV_LOW(newv), idx, memop); + if (memop & MO_SIGN) { + tcg_gen_sari_i32(TCGV_HIGH(retv), TCGV_LOW(retv), 31); + } else { + tcg_gen_movi_i32(TCGV_HIGH(retv), 0); + } + return; + } + + t1 = tcg_temp_new_i64(); + t2 = tcg_temp_new_i64(); + + tcg_gen_ext_i64(t2, cmpv, memop & MO_SIZE); + + tcg_gen_qemu_ld_i64(t1, addr, idx, memop & ~MO_SIGN); + tcg_gen_movcond_i64(TCG_COND_EQ, t2, t1, t2, newv, t1); + tcg_gen_qemu_st_i64(t2, addr, idx, memop); + tcg_temp_free_i64(t2); + + if (memop & MO_SIGN) { + tcg_gen_ext_i64(retv, t1, memop); + } else { + tcg_gen_mov_i64(retv, t1); + } + tcg_temp_free_i64(t1); } void tcg_gen_atomic_cmpxchg_i64(TCGv_i64 retv, TCGv addr, TCGv_i64 cmpv, TCGv_i64 newv, TCGArg idx, MemOp memop) { - memop = tcg_canonicalize_memop(memop, 1, 0); - if (!(tcg_ctx->tb_cflags & CF_PARALLEL)) { - TCGv_i64 t1 = tcg_temp_new_i64(); - TCGv_i64 t2 = tcg_temp_new_i64(); + tcg_gen_nonatomic_cmpxchg_i64(retv, addr, cmpv, newv, idx, memop); + return; + } - tcg_gen_ext_i64(t2, cmpv, memop & MO_SIZE); - - tcg_gen_qemu_ld_i64(t1, addr, idx, memop & ~MO_SIGN); - tcg_gen_movcond_i64(TCG_COND_EQ, t2, t1, t2, newv, t1); - tcg_gen_qemu_st_i64(t2, addr, idx, memop); - tcg_temp_free_i64(t2); - - if (memop & MO_SIGN) { - tcg_gen_ext_i64(retv, t1, memop); - } else { - tcg_gen_mov_i64(retv, t1); - } - tcg_temp_free_i64(t1); - } else if ((memop & MO_SIZE) == MO_64) { -#ifdef CONFIG_ATOMIC64 + if ((memop & MO_SIZE) == MO_64) { gen_atomic_cx_i64 gen; - MemOpIdx oi; + memop = tcg_canonicalize_memop(memop, 1, 0); gen = table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; - tcg_debug_assert(gen != NULL); + if (gen) { + MemOpIdx oi = make_memop_idx(memop, idx); + gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); + return; + } - oi = make_memop_idx(memop, idx); - gen(retv, cpu_env, addr, cmpv, newv, tcg_constant_i32(oi)); -#else gen_helper_exit_atomic(cpu_env); - /* Produce a result, so that we have a well-formed opcode stream - with respect to uses of the result in the (dead) code following. */ + + /* + * Produce a result for a well-formed opcode stream. This satisfies + * liveness for set before used, which happens before this dead code + * is removed. + */ tcg_gen_movi_i64(retv, 0); -#endif /* CONFIG_ATOMIC64 */ + return; + } + + if (TCG_TARGET_REG_BITS == 32) { + tcg_gen_atomic_cmpxchg_i32(TCGV_LOW(retv), addr, TCGV_LOW(cmpv), + TCGV_LOW(newv), idx, memop); + if (memop & MO_SIGN) { + tcg_gen_sari_i32(TCGV_HIGH(retv), TCGV_LOW(retv), 31); + } else { + tcg_gen_movi_i32(TCGV_HIGH(retv), 0); + } } else { TCGv_i32 c32 = tcg_temp_new_i32(); TCGv_i32 n32 = tcg_temp_new_i32(); -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:38:28 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELZs-0005RH-58 for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:38:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZp-0005Mk-Mc for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:25 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZ9-0004f0-43 for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:25 -0500 Received: by mail-pj1-x1034.google.com with SMTP id z9-20020a17090a468900b00226b6e7aeeaso5837291pjf.1 for ; Sat, 07 Jan 2023 18:37:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EgxuSdPulrPMHCTUSKnjnP4PI9hwsRuy0+wqX8AU1CQ=; b=f3SMTt+WLR5ouzy57nJZLXY4AWsf1mngf+VQFFBAobDmq542Ct9cnD5NMLx8mG+FbA UQxq0Lz5MyFuMCNhiCXdgStVf2k9t3Rbf7bgE9L5zK/2zSGb+oHeBF3RnaI6SyNd0muw KSnWJZE9bE1pIK7AOJJriJbkzYZFAASq0rKDspvhRjuoDkh7Mil0M+DzahYnqBIvitEC XEoqdaum54NE/9TO/345ATR+dWyULXVtBucMw1Kj8w28S4K855xfAqaXrtkD/BfXI76g 2nDCxMWil0qpjnjmpKferEwRMvW35UfrqODolplHSwlyfAu9/722R5CFORC6cBNdH05N pQLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EgxuSdPulrPMHCTUSKnjnP4PI9hwsRuy0+wqX8AU1CQ=; b=KBNFD64JznfCkUlR9yAQ4MQTqKh5sFxJvAaD+JCX7BiVTNLrOT+2LOa9OyVza+XSYp LW2ifeIq6ah3OT75GhRrHddZd19j3lDG4vmKooys8TkUKeyyrJOnfpSmC0T5nhOtWQmZ eME14n5y1AaTOCAQPDHC+QhgUuWKUXT7hbXJ4qMh6EOOx/B+Fxenmbj0A9Huz62xkHHv x9+f6XZW/JLSRkfsDhl4q+kDS4eL0+50o2mJMGtoIpD4bG3XALgCWs1er8WaODTazcyU 4Njp91wpsA21IxNb63dk4Efl5QiLcOaDUsmgtc+3BnCHQvmmJwrMg9h671mlMbOxfRiq RH6w== X-Gm-Message-State: AFqh2koSBcrMf9fI2skLlzZinNIXRT3nTucT2LCN3F7xEv5Oky+BuiE7 ZqgJRWKDWFL1SaNTAxzooZTZdg== X-Google-Smtp-Source: AMrXdXvh+qpWx9LiM1Cv/Ebs6DGtMWe7umK8RtF/wHBSKs7LGcaPQisbYjB9RaEE+Fy8kwWrxrpJ5g== X-Received: by 2002:a17:902:e291:b0:192:fc7b:2bc0 with SMTP id o17-20020a170902e29100b00192fc7b2bc0mr9822909plc.13.1673145461854; Sat, 07 Jan 2023 18:37:41 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Peter Maydell Subject: [PATCH v4 19/36] target/arm: Use tcg_gen_atomic_cmpxchg_i128 for CASP Date: Sat, 7 Jan 2023 18:37:02 -0800 Message-Id: <20230108023719.2466341-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:38:26 -0000 Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-Id: <20221112042555.2622152-3-richard.henderson@linaro.org> --- target/arm/helper-a64.h | 2 -- target/arm/helper-a64.c | 43 --------------------------- target/arm/translate-a64.c | 61 +++++++++++--------------------------- 3 files changed, 18 insertions(+), 88 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 94065d1917..ff56807247 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -50,8 +50,6 @@ DEF_HELPER_FLAGS_2(frecpx_f16, TCG_CALL_NO_RWG, f16, f16, ptr) DEF_HELPER_FLAGS_2(fcvtx_f64_to_f32, TCG_CALL_NO_RWG, f32, f64, env) DEF_HELPER_FLAGS_3(crc32_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) DEF_HELPER_FLAGS_3(crc32c_64, TCG_CALL_NO_RWG_SE, i64, i64, i64, i32) -DEF_HELPER_5(casp_le_parallel, void, env, i32, i64, i64, i64) -DEF_HELPER_5(casp_be_parallel, void, env, i32, i64, i64, i64) DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 7dbdb2c233..0972a4bdd0 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -505,49 +505,6 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes) return crc32c(acc, buf, bytes) ^ 0xffffffff; } -/* Writes back the old data into Rs. */ -void HELPER(casp_le_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, - uint64_t new_lo, uint64_t new_hi) -{ - Int128 oldv, cmpv, newv; - uintptr_t ra = GETPC(); - int mem_idx; - MemOpIdx oi; - - assert(HAVE_CMPXCHG128); - - mem_idx = cpu_mmu_index(env, false); - oi = make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); - - cmpv = int128_make128(env->xregs[rs], env->xregs[rs + 1]); - newv = int128_make128(new_lo, new_hi); - oldv = cpu_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, oi, ra); - - env->xregs[rs] = int128_getlo(oldv); - env->xregs[rs + 1] = int128_gethi(oldv); -} - -void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr, - uint64_t new_hi, uint64_t new_lo) -{ - Int128 oldv, cmpv, newv; - uintptr_t ra = GETPC(); - int mem_idx; - MemOpIdx oi; - - assert(HAVE_CMPXCHG128); - - mem_idx = cpu_mmu_index(env, false); - oi = make_memop_idx(MO_LE | MO_128 | MO_ALIGN, mem_idx); - - cmpv = int128_make128(env->xregs[rs + 1], env->xregs[rs]); - newv = int128_make128(new_lo, new_hi); - oldv = cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); - - env->xregs[rs + 1] = int128_getlo(oldv); - env->xregs[rs] = int128_gethi(oldv); -} - /* * AdvSIMD half-precision */ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index dffd7ee737..067426baef 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -2688,53 +2688,28 @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, tcg_gen_extr32_i64(s2, s1, cmp); } tcg_temp_free_i64(cmp); - } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { - if (HAVE_CMPXCHG128) { - TCGv_i32 tcg_rs = tcg_constant_i32(rs); - if (s->be_data == MO_LE) { - gen_helper_casp_le_parallel(cpu_env, tcg_rs, - clean_addr, t1, t2); - } else { - gen_helper_casp_be_parallel(cpu_env, tcg_rs, - clean_addr, t1, t2); - } - } else { - gen_helper_exit_atomic(cpu_env); - s->base.is_jmp = DISAS_NORETURN; - } } else { - TCGv_i64 d1 = tcg_temp_new_i64(); - TCGv_i64 d2 = tcg_temp_new_i64(); - TCGv_i64 a2 = tcg_temp_new_i64(); - TCGv_i64 c1 = tcg_temp_new_i64(); - TCGv_i64 c2 = tcg_temp_new_i64(); - TCGv_i64 zero = tcg_constant_i64(0); + TCGv_i128 cmp = tcg_temp_new_i128(); + TCGv_i128 val = tcg_temp_new_i128(); - /* Load the two words, in memory order. */ - tcg_gen_qemu_ld_i64(d1, clean_addr, memidx, - MO_64 | MO_ALIGN_16 | s->be_data); - tcg_gen_addi_i64(a2, clean_addr, 8); - tcg_gen_qemu_ld_i64(d2, a2, memidx, MO_64 | s->be_data); + if (s->be_data == MO_LE) { + tcg_gen_concat_i64_i128(val, t1, t2); + tcg_gen_concat_i64_i128(cmp, s1, s2); + } else { + tcg_gen_concat_i64_i128(val, t2, t1); + tcg_gen_concat_i64_i128(cmp, s2, s1); + } - /* Compare the two words, also in memory order. */ - tcg_gen_setcond_i64(TCG_COND_EQ, c1, d1, s1); - tcg_gen_setcond_i64(TCG_COND_EQ, c2, d2, s2); - tcg_gen_and_i64(c2, c2, c1); + tcg_gen_atomic_cmpxchg_i128(cmp, clean_addr, cmp, val, memidx, + MO_128 | MO_ALIGN | s->be_data); + tcg_temp_free_i128(val); - /* If compare equal, write back new data, else write back old data. */ - tcg_gen_movcond_i64(TCG_COND_NE, c1, c2, zero, t1, d1); - tcg_gen_movcond_i64(TCG_COND_NE, c2, c2, zero, t2, d2); - tcg_gen_qemu_st_i64(c1, clean_addr, memidx, MO_64 | s->be_data); - tcg_gen_qemu_st_i64(c2, a2, memidx, MO_64 | s->be_data); - tcg_temp_free_i64(a2); - tcg_temp_free_i64(c1); - tcg_temp_free_i64(c2); - - /* Write back the data from memory to Rs. */ - tcg_gen_mov_i64(s1, d1); - tcg_gen_mov_i64(s2, d2); - tcg_temp_free_i64(d1); - tcg_temp_free_i64(d2); + if (s->be_data == MO_LE) { + tcg_gen_extr_i128_i64(s1, s2, cmp); + } else { + tcg_gen_extr_i128_i64(s2, s1, cmp); + } + tcg_temp_free_i128(cmp); } } -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:38:31 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELZu-0005Vc-UX for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:38:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZs-0005S3-Pc for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:28 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZA-0004Wm-GE for qemu-riscv@nongnu.org; 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Ilya Leoshkevich Subject: [PATCH v4 21/36] tests/tcg/s390x: Add div.c Date: Sat, 7 Jan 2023 18:37:04 -0800 Message-Id: <20230108023719.2466341-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:38:29 -0000 From: Ilya Leoshkevich Add a basic test to prevent regressions. Signed-off-by: Ilya Leoshkevich Message-Id: <20221101111300.2539919-1-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/s390x/div.c | 40 +++++++++++++++++++++++++++++++++ tests/tcg/s390x/Makefile.target | 1 + 2 files changed, 41 insertions(+) create mode 100644 tests/tcg/s390x/div.c diff --git a/tests/tcg/s390x/div.c b/tests/tcg/s390x/div.c new file mode 100644 index 0000000000..5807295614 --- /dev/null +++ b/tests/tcg/s390x/div.c @@ -0,0 +1,40 @@ +#include +#include + +static void test_dr(void) +{ + register int32_t r0 asm("r0") = -1; + register int32_t r1 asm("r1") = -4241; + int32_t b = 101, q, r; + + asm("dr %[r0],%[b]" + : [r0] "+r" (r0), [r1] "+r" (r1) + : [b] "r" (b) + : "cc"); + q = r1; + r = r0; + assert(q == -41); + assert(r == -100); +} + +static void test_dlr(void) +{ + register uint32_t r0 asm("r0") = 0; + register uint32_t r1 asm("r1") = 4243; + uint32_t b = 101, q, r; + + asm("dlr %[r0],%[b]" + : [r0] "+r" (r0), [r1] "+r" (r1) + : [b] "r" (b) + : "cc"); + q = r1; + r = r0; + assert(q == 42); + assert(r == 1); +} + +int main(void) +{ + test_dr(); + test_dlr(); +} diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.target index 07fcc6d0ce..ab7a3bcfb2 100644 --- a/tests/tcg/s390x/Makefile.target +++ b/tests/tcg/s390x/Makefile.target @@ -24,6 +24,7 @@ TESTS+=trap TESTS+=signals-s390x TESTS+=branch-relative-long TESTS+=noexec +TESTS+=div Z13_TESTS=vistr $(Z13_TESTS): CFLAGS+=-march=z13 -O2 -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:38:32 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELZw-0005YQ-FW for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:38:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZu-0005VJ-ON for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:30 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZA-0004fV-5q for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:30 -0500 Received: by mail-pl1-x631.google.com with SMTP id 17so5917755pll.0 for ; Sat, 07 Jan 2023 18:37:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NtJttwUEQyaD1SfJG+fgMdQwRfXm20UeXRRXlRvUEX4=; b=VbUwq7tlCgfO36Oth8TSVLgJMqybrSeTGcCl1IdamNJ23TJWhQ4pTLvHnSb03OwH6J Mm/6nx+5eD3sc+wxXLs71NKAX1IgVAkWjZk92johrHQn6y0JRUeOZZ3Sq9iR+MzaO7u5 Bw462YzSnUIF4NKdYRk5WS+E2kKtrY58N6p7QjB+240Bp0jBsE2pjy74amXiYv69jok6 6G8MSAnOLenX4K9LeF8dw47SvoZfwYBSkhi2jgZ2lBn9Em+xBbFRHrTDoD22KkeFKJbh WagiRbfFpyu4UKiDpkcb9rZPKfft/l1xAjARHDOs9Wrv9AupBbtOf6hh3J/f8chlq7Ay rXYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NtJttwUEQyaD1SfJG+fgMdQwRfXm20UeXRRXlRvUEX4=; b=GWz//Cq5zfgHL4H79jRAsaK/1of+sEjpMHkqXpEK1Kvc7JrgR/CrRO6NT8wGWqZuuA uMrEujGJz2HNdcKy42GpuMHIGAJumvOEw3EuXB4xGEdeVzLfuaMGyw4tASkJ8GHadiOZ tCYTudLaLkYqcspLTICB0aqTWb/W7Hi/DAndB+v5SNnei8DOD8ZH2UyhhCWq4mi0ZLAV tj3sPGoaZcyxom9QUOK56H7qF5QmnkVHMt2fMkV/JQSVlYK7VzCh93db/THyC6I57PGG GtJtoU0ZMk9chNVeuEgnSt5A0gEnnOwl+3FYeq6SoXj3sVaJS6rVNp6MrJ+ruhVwo5Cl FBgg== X-Gm-Message-State: AFqh2kpq/jN2ElwRktz71Z+mtEgmdEsr03HWt3jpSPKNVp5BOv6Uik0g /6CLksmSB6eSlCr7c7lMdbBGdg== X-Google-Smtp-Source: AMrXdXss8BGh5z3qj8f331v9I9FqYqmKAcV0MdGfTWZIzcd4RsPN3FtitSKJFZnDvXI4KVFEPADw+w== X-Received: by 2002:a17:902:c10c:b0:192:b5b1:eb1a with SMTP id 12-20020a170902c10c00b00192b5b1eb1amr29033572pli.69.1673145462728; Sat, 07 Jan 2023 18:37:42 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Daniel Henrique Barboza Subject: [PATCH v4 20/36] target/ppc: Use tcg_gen_atomic_cmpxchg_i128 for STQCX Date: Sat, 7 Jan 2023 18:37:03 -0800 Message-Id: <20230108023719.2466341-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:38:31 -0000 Note that the previous direct reference to reserve_val, - tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode - ? offsetof(CPUPPCState, reserve_val2) - : offsetof(CPUPPCState, reserve_val))); was incorrect because all references should have gone through cpu_reserve_val. Create a cpu_reserve_val2 tcg temp to fix this. Signed-off-by: Richard Henderson Reviewed-by: Daniel Henrique Barboza Message-Id: <20221112061122.2720163-2-richard.henderson@linaro.org> --- target/ppc/helper.h | 2 - target/ppc/mem_helper.c | 44 ----------------- target/ppc/translate.c | 102 ++++++++++++++++++---------------------- 3 files changed, 47 insertions(+), 101 deletions(-) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 8dd22a35e4..0beaca5c7a 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -818,6 +818,4 @@ DEF_HELPER_FLAGS_5(stq_le_parallel, TCG_CALL_NO_WG, void, env, tl, i64, i64, i32) DEF_HELPER_FLAGS_5(stq_be_parallel, TCG_CALL_NO_WG, void, env, tl, i64, i64, i32) -DEF_HELPER_5(stqcx_le_parallel, i32, env, tl, i64, i64, i32) -DEF_HELPER_5(stqcx_be_parallel, i32, env, tl, i64, i64, i32) #endif diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index d1163f316c..1578887a8f 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -413,50 +413,6 @@ void helper_stq_be_parallel(CPUPPCState *env, target_ulong addr, val = int128_make128(lo, hi); cpu_atomic_sto_be_mmu(env, addr, val, opidx, GETPC()); } - -uint32_t helper_stqcx_le_parallel(CPUPPCState *env, target_ulong addr, - uint64_t new_lo, uint64_t new_hi, - uint32_t opidx) -{ - bool success = false; - - /* We will have raised EXCP_ATOMIC from the translator. */ - assert(HAVE_CMPXCHG128); - - if (likely(addr == env->reserve_addr)) { - Int128 oldv, cmpv, newv; - - cmpv = int128_make128(env->reserve_val2, env->reserve_val); - newv = int128_make128(new_lo, new_hi); - oldv = cpu_atomic_cmpxchgo_le_mmu(env, addr, cmpv, newv, - opidx, GETPC()); - success = int128_eq(oldv, cmpv); - } - env->reserve_addr = -1; - return env->so + success * CRF_EQ_BIT; -} - -uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr, - uint64_t new_lo, uint64_t new_hi, - uint32_t opidx) -{ - bool success = false; - - /* We will have raised EXCP_ATOMIC from the translator. */ - assert(HAVE_CMPXCHG128); - - if (likely(addr == env->reserve_addr)) { - Int128 oldv, cmpv, newv; - - cmpv = int128_make128(env->reserve_val2, env->reserve_val); - newv = int128_make128(new_lo, new_hi); - oldv = cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, - opidx, GETPC()); - success = int128_eq(oldv, cmpv); - } - env->reserve_addr = -1; - return env->so + success * CRF_EQ_BIT; -} #endif /*****************************************************************************/ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index edb3daa9b5..1c17d5a558 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -72,6 +72,7 @@ static TCGv cpu_cfar; static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; static TCGv cpu_reserve; static TCGv cpu_reserve_val; +static TCGv cpu_reserve_val2; static TCGv cpu_fpscr; static TCGv_i32 cpu_access_type; @@ -141,8 +142,11 @@ void ppc_translate_init(void) offsetof(CPUPPCState, reserve_addr), "reserve_addr"); cpu_reserve_val = tcg_global_mem_new(cpu_env, - offsetof(CPUPPCState, reserve_val), - "reserve_val"); + offsetof(CPUPPCState, reserve_val), + "reserve_val"); + cpu_reserve_val2 = tcg_global_mem_new(cpu_env, + offsetof(CPUPPCState, reserve_val2), + "reserve_val2"); cpu_fpscr = tcg_global_mem_new(cpu_env, offsetof(CPUPPCState, fpscr), "fpscr"); @@ -3998,78 +4002,66 @@ static void gen_lqarx(DisasContext *ctx) /* stqcx. */ static void gen_stqcx_(DisasContext *ctx) { + TCGLabel *lab_fail, *lab_over; int rs = rS(ctx->opcode); - TCGv EA, hi, lo; + TCGv EA, t0, t1; + TCGv_i128 cmp, val; if (unlikely(rs & 1)) { gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); return; } + lab_fail = gen_new_label(); + lab_over = gen_new_label(); + gen_set_access_type(ctx, ACCESS_RES); EA = tcg_temp_new(); gen_addr_reg_index(ctx, EA); + tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); + tcg_temp_free(EA); + + cmp = tcg_temp_new_i128(); + val = tcg_temp_new_i128(); + + tcg_gen_concat_i64_i128(cmp, cpu_reserve_val2, cpu_reserve_val); + /* Note that the low part is always in RS+1, even in LE mode. */ - lo = cpu_gpr[rs + 1]; - hi = cpu_gpr[rs]; + tcg_gen_concat_i64_i128(val, cpu_gpr[rs + 1], cpu_gpr[rs]); - if (tb_cflags(ctx->base.tb) & CF_PARALLEL) { - if (HAVE_CMPXCHG128) { - TCGv_i32 oi = tcg_const_i32(DEF_MEMOP(MO_128) | MO_ALIGN); - if (ctx->le_mode) { - gen_helper_stqcx_le_parallel(cpu_crf[0], cpu_env, - EA, lo, hi, oi); - } else { - gen_helper_stqcx_be_parallel(cpu_crf[0], cpu_env, - EA, lo, hi, oi); - } - tcg_temp_free_i32(oi); - } else { - /* Restart with exclusive lock. */ - gen_helper_exit_atomic(cpu_env); - ctx->base.is_jmp = DISAS_NORETURN; - } - tcg_temp_free(EA); - } else { - TCGLabel *lab_fail = gen_new_label(); - TCGLabel *lab_over = gen_new_label(); - TCGv_i64 t0 = tcg_temp_new_i64(); - TCGv_i64 t1 = tcg_temp_new_i64(); + tcg_gen_atomic_cmpxchg_i128(val, cpu_reserve, cmp, val, ctx->mem_idx, + DEF_MEMOP(MO_128 | MO_ALIGN)); + tcg_temp_free_i128(cmp); - tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lab_fail); - tcg_temp_free(EA); + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + tcg_gen_extr_i128_i64(t1, t0, val); + tcg_temp_free_i128(val); - gen_qemu_ld64_i64(ctx, t0, cpu_reserve); - tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode - ? offsetof(CPUPPCState, reserve_val2) - : offsetof(CPUPPCState, reserve_val))); - tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); + tcg_gen_xor_tl(t1, t1, cpu_reserve_val2); + tcg_gen_xor_tl(t0, t0, cpu_reserve_val); + tcg_gen_or_tl(t0, t0, t1); + tcg_temp_free(t1); - tcg_gen_addi_i64(t0, cpu_reserve, 8); - gen_qemu_ld64_i64(ctx, t0, t0); - tcg_gen_ld_i64(t1, cpu_env, (ctx->le_mode - ? offsetof(CPUPPCState, reserve_val) - : offsetof(CPUPPCState, reserve_val2))); - tcg_gen_brcond_i64(TCG_COND_NE, t0, t1, lab_fail); + tcg_gen_setcondi_tl(TCG_COND_EQ, t0, t0, 0); + tcg_gen_shli_tl(t0, t0, CRF_EQ_BIT); + tcg_gen_or_tl(t0, t0, cpu_so); + tcg_gen_trunc_tl_i32(cpu_crf[0], t0); + tcg_temp_free(t0); - /* Success */ - gen_qemu_st64_i64(ctx, ctx->le_mode ? lo : hi, cpu_reserve); - tcg_gen_addi_i64(t0, cpu_reserve, 8); - gen_qemu_st64_i64(ctx, ctx->le_mode ? hi : lo, t0); + tcg_gen_br(lab_over); + gen_set_label(lab_fail); - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); - tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], CRF_EQ); - tcg_gen_br(lab_over); + /* + * Address mismatch implies failure. But we still need to provide + * the memory barrier semantics of the instruction. + */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); - gen_set_label(lab_fail); - tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so); - - gen_set_label(lab_over); - tcg_gen_movi_tl(cpu_reserve, -1); - tcg_temp_free_i64(t0); - tcg_temp_free_i64(t1); - } + gen_set_label(lab_over); + tcg_gen_movi_tl(cpu_reserve, -1); } #endif /* defined(TARGET_PPC64) */ -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:38:34 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELZy-0005bK-2K for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:38:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELZw-0005Yt-Ia for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:32 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZB-0004gb-W8 for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:32 -0500 Received: by mail-pl1-x631.google.com with SMTP id c6so5884813pls.4 for ; Sat, 07 Jan 2023 18:37:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LHzGWvWFa4q7FhR/Zjnl6sZxcznG5V94Bca4nmBi0Ko=; b=YTwxzUVTIaPoRoMrrMr3xZVtTxHkxcoWUY/Z2XQDOSB9OBwIAea0LWF4lZprz0utdL bz8oAXkZ3pbK8ENWVfDUPWyMxSf5qcWI7FdLHPzVhOdyqjkbnc7RYerBxQdmB9Sd4SNc W53FcipIv/fYzM1CT+uvFYlDuvdAk2/kogBSiHH30yV1gAPucUS4CmvT7tD6r8j3GoeP e3C4JRG6yLBzathSHildNLFQ87fxBqI7WxbiZTxvKKqIeunYgevwxILHvH32/SSN3Z4G nJwT+chTNLjwGHbuETD1YlinuW3PASIxxePuuoD/RrS4xa3rYjivcBCSGBfLjUJGJLuQ MlWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LHzGWvWFa4q7FhR/Zjnl6sZxcznG5V94Bca4nmBi0Ko=; b=xmqhWeQRt72zFFxHqztAByEhHUOyaVKBYjIvYHIO6u6QjDTubhLbd4qptejQVj6wza TqGpEmzlhb9K50twowJXYIL08TQiKjGKkUWX/Mkk4JY/jQcuqt3w3Grd18JL3v2BEJu1 YeVakKhR51GaHScAqGG+yJG+I7NR1Q8aOUP9NhEhWb110wvHhLwgBQs+C9AQII9pwXgq hWJM6By94qulzIUKWH646E5CqtBnfr8Pk6FmQ5jhU13TFnH+KZeCf5KJALuHdfqcCSFv loe5Cn37F26UEONaND+7x3A39ZMhulcoBFqc6ypUSlA6XJ89+Kj+bMc1ZniwWff5ErCv jDrA== X-Gm-Message-State: AFqh2kqr6DgWL102i6ZYIdlfm76pe8LpHI5ElO0R9rDKR66Ozo/YRVC4 Mzjez+lHxieN1OLtFtXvX4hAGw== X-Google-Smtp-Source: AMrXdXtWkkVxrDI5jAepvQBu55pf/8Pkk8TEqq3iuXCppr2qwzq8jDajDuGDsPrBDdPoMgPJH321zw== X-Received: by 2002:a17:902:fe0c:b0:192:5c3e:8939 with SMTP id g12-20020a170902fe0c00b001925c3e8939mr52348852plj.0.1673145464761; Sat, 07 Jan 2023 18:37:44 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Ilya Leoshkevich Subject: [PATCH v4 22/36] tests/tcg/s390x: Add clst.c Date: Sat, 7 Jan 2023 18:37:05 -0800 Message-Id: <20230108023719.2466341-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:38:32 -0000 From: Ilya Leoshkevich Add a basic test to prevent regressions. Signed-off-by: Ilya Leoshkevich Message-Id: <20221025213008.2209006-2-iii@linux.ibm.com> Signed-off-by: Richard Henderson --- tests/tcg/s390x/clst.c | 82 +++++++++++++++++++++++++++++++++ tests/tcg/s390x/Makefile.target | 1 + 2 files changed, 83 insertions(+) create mode 100644 tests/tcg/s390x/clst.c diff --git a/tests/tcg/s390x/clst.c b/tests/tcg/s390x/clst.c new file mode 100644 index 0000000000..ed2fe7326c --- /dev/null +++ b/tests/tcg/s390x/clst.c @@ -0,0 +1,82 @@ +#define _GNU_SOURCE +#include +#include + +static int clst(char sep, const char **s1, const char **s2) +{ + const char *r1 = *s1; + const char *r2 = *s2; + int cc; + + do { + register int r0 asm("r0") = sep; + + asm("clst %[r1],%[r2]\n" + "ipm %[cc]\n" + "srl %[cc],28" + : [r1] "+r" (r1), [r2] "+r" (r2), "+r" (r0), [cc] "=r" (cc) + : + : "cc"); + *s1 = r1; + *s2 = r2; + } while (cc == 3); + + return cc; +} + +static const struct test { + const char *name; + char sep; + const char *s1; + const char *s2; + int exp_cc; + int exp_off; +} tests[] = { + { + .name = "cc0", + .sep = 0, + .s1 = "aa", + .s2 = "aa", + .exp_cc = 0, + .exp_off = 0, + }, + { + .name = "cc1", + .sep = 1, + .s1 = "a\x01", + .s2 = "aa\x01", + .exp_cc = 1, + .exp_off = 1, + }, + { + .name = "cc2", + .sep = 2, + .s1 = "abc\x02", + .s2 = "abb\x02", + .exp_cc = 2, + .exp_off = 2, + }, +}; + +int main(void) +{ + const struct test *t; + const char *s1, *s2; + size_t i; + int cc; + + for (i = 0; i < sizeof(tests) / sizeof(tests[0]); i++) { + t = &tests[i]; + s1 = t->s1; + s2 = t->s2; + cc = clst(t->sep, &s1, &s2); + if (cc != t->exp_cc || + s1 != t->s1 + t->exp_off || + s2 != t->s2 + t->exp_off) { + fprintf(stderr, "%s\n", t->name); + return EXIT_FAILURE; + } + } + + return EXIT_SUCCESS; +} diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.target index ab7a3bcfb2..79250f31dd 100644 --- a/tests/tcg/s390x/Makefile.target +++ b/tests/tcg/s390x/Makefile.target @@ -25,6 +25,7 @@ TESTS+=signals-s390x TESTS+=branch-relative-long TESTS+=noexec TESTS+=div +TESTS+=clst Z13_TESTS=vistr $(Z13_TESTS): CFLAGS+=-march=z13 -O2 -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:38:43 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELa7-0005r9-6Y for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:38:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELa2-0005jv-B7 for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:38 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZC-0004Vf-Ql for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:38 -0500 Received: by mail-pj1-x102d.google.com with SMTP id fz16-20020a17090b025000b002269d6c2d83so8701501pjb.0 for ; Sat, 07 Jan 2023 18:37:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wHZLFNNm0ZFp31ulDF75QeL44+XwFwYbg39T7b6YDuI=; b=yz/Vv9hfx11fLSInlmwJJ1MiPWzE7D/6OdyIY8MRsTs5VPjdFjXiWqOie9g2r6ox8f xOqANbE5cvmgQPJkBPDFqa5M2lDwRmrPO5Ps35nPdBDp/2jfCaf6CekDebjqcusMcNtI e7wjIooMErSThlYi6DKx+5bT78BY7IWdlWjBAxF/xzojETPLYpH5Z/I+a8obKDiWp/ee bJzNJbVRYOKS6Q8NF8c1Y86wXQ9zdyEsto8R0ACvTaT20gzVGLqEhlTB+5Y/1jRRtwpr V35qfYdz/Kax42wBGbUZfcRkscrNi0Rw4aNaCmMirA+Hmopcpyj06pGB8fvY153nHJ0P tosw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wHZLFNNm0ZFp31ulDF75QeL44+XwFwYbg39T7b6YDuI=; b=nNtIpJLvcFtCs1DBvfq38trGWcWS6Yfe+fS8nNQhg0AauKYnYZdorIvSrjjAnH5GKq bd7aXX8ifzr7Cvhcu+0Y7c+Ig81sQGCLDEI0tWQUi5yJEyqhrWvqMu9+h/btcMmpFkvY FqCxiX7DoHLgw9WZ8t5u4NbjDqje5LjU2FY4j8bSKDA+fttqze6PpUz5KEgUDmL2eL0A it2K9Ns8WO4M7hrltzkz28lpji6VWkA6S+g4VS8QJwZ+0a0RI1umXcNID4FrQFZyU6jb aQAMQRH1BntXW//Zm78DtAdMOAoPieDFG247JdprcvlKLjU7wBwA3ijuioovScA+czlA ZxSw== X-Gm-Message-State: AFqh2kq6o5Dp9fE+3C12BpNHSIj4uYHT24/dG5Y8cCUJkzIBkQDfnB94 hHo9C4yF1hUORJ1iF/qfeujdKQ== X-Google-Smtp-Source: AMrXdXsidKN8kV3QYovayg1TOWMn+v7UTYaTQDgzkZLYCWEoLtEOwPlF3xckO4uBp2FDg1YRVww9LQ== X-Received: by 2002:a17:902:f791:b0:192:5ec4:6656 with SMTP id q17-20020a170902f79100b001925ec46656mr61538487pln.3.1673145466046; Sat, 07 Jan 2023 18:37:46 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Ilya Leoshkevich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 23/36] tests/tcg/s390x: Add long-double.c Date: Sat, 7 Jan 2023 18:37:06 -0800 Message-Id: <20230108023719.2466341-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:38:38 -0000 Acked-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tests/tcg/s390x/long-double.c | 24 ++++++++++++++++++++++++ tests/tcg/s390x/Makefile.target | 1 + 2 files changed, 25 insertions(+) create mode 100644 tests/tcg/s390x/long-double.c diff --git a/tests/tcg/s390x/long-double.c b/tests/tcg/s390x/long-double.c new file mode 100644 index 0000000000..757a6262fd --- /dev/null +++ b/tests/tcg/s390x/long-double.c @@ -0,0 +1,24 @@ +/* + * Perform some basic arithmetic with long double, as a sanity check. + * With small integral numbers, we can cross-check with integers. + */ + +#include + +int main() +{ + int i, j; + + for (i = 1; i < 5; i++) { + for (j = 1; j < 5; j++) { + long double la = (long double)i + j; + long double lm = (long double)i * j; + long double ls = (long double)i - j; + + assert(la == i + j); + assert(lm == i * j); + assert(ls == i - j); + } + } + return 0; +} diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.target index 79250f31dd..1d454270c0 100644 --- a/tests/tcg/s390x/Makefile.target +++ b/tests/tcg/s390x/Makefile.target @@ -26,6 +26,7 @@ TESTS+=branch-relative-long TESTS+=noexec TESTS+=div TESTS+=clst +TESTS+=long-double Z13_TESTS=vistr $(Z13_TESTS): CFLAGS+=-march=z13 -O2 -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:38:45 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELa9-0005vZ-GL for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:38:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELa6-0005qT-TW for qemu-riscv@nongnu.org; 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v4 25/36] target/s390x: Use a single return for helper_divs64/u64 Date: Sat, 7 Jan 2023 18:37:08 -0800 Message-Id: <20230108023719.2466341-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:38:43 -0000 Pack the quotient and remainder into a single Int128. Use the divu128 primitive to remove the cpu_abort on 32-bit hosts. Reviewed-by: Philippe Mathieu-Daudé Acked-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- v2: Extended div test case to cover these insns. --- target/s390x/helper.h | 4 ++-- target/s390x/tcg/int_helper.c | 38 +++++++++-------------------------- target/s390x/tcg/translate.c | 14 +++++++++---- tests/tcg/s390x/div.c | 35 ++++++++++++++++++++++++++++++++ 4 files changed, 56 insertions(+), 35 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index bc828d976b..593f3c8bee 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -12,8 +12,8 @@ DEF_HELPER_3(clcl, i32, env, i32, i32) DEF_HELPER_FLAGS_4(clm, TCG_CALL_NO_WG, i32, env, i32, i32, i64) DEF_HELPER_FLAGS_3(divs32, TCG_CALL_NO_WG, i64, env, s64, s64) DEF_HELPER_FLAGS_3(divu32, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, s64, env, s64, s64) -DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, i128, env, s64, s64) +DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i128, env, i64, i64, i64) DEF_HELPER_3(srst, void, env, i32, i32) DEF_HELPER_3(srstu, void, env, i32, i32) DEF_HELPER_4(clst, i64, env, i64, i64, i64) diff --git a/target/s390x/tcg/int_helper.c b/target/s390x/tcg/int_helper.c index 7260583cf2..eb8e6dd1b5 100644 --- a/target/s390x/tcg/int_helper.c +++ b/target/s390x/tcg/int_helper.c @@ -76,46 +76,26 @@ uint64_t HELPER(divu32)(CPUS390XState *env, uint64_t a, uint64_t b64) } /* 64/64 -> 64 signed division */ -int64_t HELPER(divs64)(CPUS390XState *env, int64_t a, int64_t b) +Int128 HELPER(divs64)(CPUS390XState *env, int64_t a, int64_t b) { /* Catch divide by zero, and non-representable quotient (MIN / -1). */ if (b == 0 || (b == -1 && a == (1ll << 63))) { tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } - env->retxl = a % b; - return a / b; + return int128_make128(a / b, a % b); } /* 128 -> 64/64 unsigned division */ -uint64_t HELPER(divu64)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t b) +Int128 HELPER(divu64)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t b) { - uint64_t ret; - /* Signal divide by zero. */ - if (b == 0) { - tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); - } - if (ah == 0) { - /* 64 -> 64/64 case */ - env->retxl = al % b; - ret = al / b; - } else { - /* ??? Move i386 idivq helper to host-utils. */ -#ifdef CONFIG_INT128 - __uint128_t a = ((__uint128_t)ah << 64) | al; - __uint128_t q = a / b; - env->retxl = a % b; - ret = q; - if (ret != q) { - tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); + if (b != 0) { + uint64_t r = divu128(&al, &ah, b); + if (ah == 0) { + return int128_make128(al, r); } -#else - /* 32-bit hosts would need special wrapper functionality - just abort if - we encounter such a case; it's very unlikely anyways. */ - cpu_abort(env_cpu(env), "128 -> 64/64 division not implemented\n"); -#endif } - return ret; + /* divide by zero or overflow */ + tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } uint64_t HELPER(cvd)(int32_t reg) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 169f7ee1b2..6953b81de7 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2409,15 +2409,21 @@ static DisasJumpType op_divu32(DisasContext *s, DisasOps *o) static DisasJumpType op_divs64(DisasContext *s, DisasOps *o) { - gen_helper_divs64(o->out2, cpu_env, o->in1, o->in2); - return_low128(o->out); + TCGv_i128 t = tcg_temp_new_i128(); + + gen_helper_divs64(t, cpu_env, o->in1, o->in2); + tcg_gen_extr_i128_i64(o->out2, o->out, t); + tcg_temp_free_i128(t); return DISAS_NEXT; } static DisasJumpType op_divu64(DisasContext *s, DisasOps *o) { - gen_helper_divu64(o->out2, cpu_env, o->out, o->out2, o->in2); - return_low128(o->out); + TCGv_i128 t = tcg_temp_new_i128(); + + gen_helper_divu64(t, cpu_env, o->out, o->out2, o->in2); + tcg_gen_extr_i128_i64(o->out2, o->out, t); + tcg_temp_free_i128(t); return DISAS_NEXT; } diff --git a/tests/tcg/s390x/div.c b/tests/tcg/s390x/div.c index 5807295614..6ad9900e08 100644 --- a/tests/tcg/s390x/div.c +++ b/tests/tcg/s390x/div.c @@ -33,8 +33,43 @@ static void test_dlr(void) assert(r == 1); } +static void test_dsgr(void) +{ + register int64_t r0 asm("r0") = -1; + register int64_t r1 asm("r1") = -4241; + int64_t b = 101, q, r; + + asm("dsgr %[r0],%[b]" + : [r0] "+r" (r0), [r1] "+r" (r1) + : [b] "r" (b) + : "cc"); + q = r1; + r = r0; + assert(q == -41); + assert(r == -100); +} + +static void test_dlgr(void) +{ + register uint64_t r0 asm("r0") = 0; + register uint64_t r1 asm("r1") = 4243; + uint64_t b = 101, q, r; + + asm("dlgr %[r0],%[b]" + : [r0] "+r" (r0), [r1] "+r" (r1) + : [b] "r" (b) + : "cc"); + q = r1; + r = r0; + assert(q == 42); + assert(r == 1); +} + int main(void) { test_dr(); test_dlr(); + test_dsgr(); + test_dlgr(); + return 0; } -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:38:46 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELaA-00062X-Br for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:38:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELa6-0005qP-Rp for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:42 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZE-0004i2-L9 for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:38 -0500 Received: by mail-pl1-x632.google.com with SMTP id jl4so5864085plb.8 for ; Sat, 07 Jan 2023 18:37:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0m37yJViirw0Wc/T2o6kI/jHDeYjleRW0O5TzNJ6/Gw=; b=h4+cxeTYl00k+rgoM0vv41/Usl7td91koPjOdPmbIrk9Ea10TDSD1uGzQBwgxvqv48 OsoS1rK0TA8yfiadWo4InJ+9YJ3xPMKYi5rxK0YG4SyEJK9yPu8ZtnmSo6J79MaJbzBc wjQvhWqFw4mTmUFfLQc6eZbWD7QbT/ByITs7ttr6HJ7GThC0EbQkEq+kVYiawTXFKTV+ h1jSXt5sM3RMsEhpU8r1OB7CiJiAtFwROctYRt3qP1RmJjmvP5/wYUKqt4En2ocWs4UK c1Qvt/KAy8hd2ecxd8W+Swd/WGhGKr7RonpbqmsH6mI/EPiHlxD+KurTJIjmsCoDd3Ct hU6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0m37yJViirw0Wc/T2o6kI/jHDeYjleRW0O5TzNJ6/Gw=; b=DITFXC5O8yGA649CyRi5Vc41frsS3F6GjNs4XsoFTKS2u8Z+Gekkda4WZR3gY45LaE JUb6kk3crI4vIFiyF45z++a3ayzgoYqEEbsNGMUBfBUcafHDQvxadO0RzaY1mU8Z9L0k TwuqnRy40qqZJi+CnV/tHBfQM0k4AaTDlZp/oRIlc2rbvG9mIitgGGf4UsjYksIWVSna 5QaT2T/Z7LGBFHcfvOynGmKqy/JjhU8qWhhksQi4WZi3C+/VNx9Igc1SUpCzFR5/JuY5 BUxOFpHwwWDQn5enfU3IIzi/tfc9CRK2b3IHnTnWtsIxVmLmvMh/5YB4x895fsRjv04x k0Kg== X-Gm-Message-State: AFqh2kqTlKGwgPf1nYXLTjuF4lTSDJOFOThP1N/rbJt8NOQ4CVxHm6I0 n4zg5k0OTczKLVitxYVbwuXTAA== X-Google-Smtp-Source: AMrXdXuWbDFrK2c7CNgFID6FzP7cLwTU9VSqrQ7/GmJ/yBTUQ1xfxnwlqiQisWjVWs96GZGs2VCj1Q== X-Received: by 2002:a17:903:40c4:b0:193:197e:494f with SMTP id t4-20020a17090340c400b00193197e494fmr5227036pld.27.1673145467340; Sat, 07 Jan 2023 18:37:47 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 24/36] target/s390x: Use a single return for helper_divs32/u32 Date: Sat, 7 Jan 2023 18:37:07 -0800 Message-Id: <20230108023719.2466341-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:38:43 -0000 Pack the quotient and remainder into a single uint64_t. Signed-off-by: Richard Henderson --- v2: Fix operand ordering; use tcg_extr32_i64. --- target/s390x/helper.h | 2 +- target/s390x/tcg/int_helper.c | 26 +++++++++++++------------- target/s390x/tcg/translate.c | 8 ++++---- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 93923ca153..bc828d976b 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -10,7 +10,7 @@ DEF_HELPER_FLAGS_4(clc, TCG_CALL_NO_WG, i32, env, i32, i64, i64) DEF_HELPER_3(mvcl, i32, env, i32, i32) DEF_HELPER_3(clcl, i32, env, i32, i32) DEF_HELPER_FLAGS_4(clm, TCG_CALL_NO_WG, i32, env, i32, i32, i64) -DEF_HELPER_FLAGS_3(divs32, TCG_CALL_NO_WG, s64, env, s64, s64) +DEF_HELPER_FLAGS_3(divs32, TCG_CALL_NO_WG, i64, env, s64, s64) DEF_HELPER_FLAGS_3(divu32, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, s64, env, s64, s64) DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i64, env, i64, i64, i64) diff --git a/target/s390x/tcg/int_helper.c b/target/s390x/tcg/int_helper.c index 954542388a..7260583cf2 100644 --- a/target/s390x/tcg/int_helper.c +++ b/target/s390x/tcg/int_helper.c @@ -34,45 +34,45 @@ #endif /* 64/32 -> 32 signed division */ -int64_t HELPER(divs32)(CPUS390XState *env, int64_t a, int64_t b64) +uint64_t HELPER(divs32)(CPUS390XState *env, int64_t a, int64_t b64) { - int32_t ret, b = b64; - int64_t q; + int32_t b = b64; + int64_t q, r; if (b == 0) { tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } - ret = q = a / b; - env->retxl = a % b; + q = a / b; + r = a % b; /* Catch non-representable quotient. */ - if (ret != q) { + if (q != (int32_t)q) { tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } - return ret; + return deposit64(q, 32, 32, r); } /* 64/32 -> 32 unsigned division */ uint64_t HELPER(divu32)(CPUS390XState *env, uint64_t a, uint64_t b64) { - uint32_t ret, b = b64; - uint64_t q; + uint32_t b = b64; + uint64_t q, r; if (b == 0) { tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } - ret = q = a / b; - env->retxl = a % b; + q = a / b; + r = a % b; /* Catch non-representable quotient. */ - if (ret != q) { + if (q != (uint32_t)q) { tcg_s390_program_interrupt(env, PGM_FIXPT_DIVIDE, GETPC()); } - return ret; + return deposit64(q, 32, 32, r); } /* 64/64 -> 64 signed division */ diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index a339b277e9..169f7ee1b2 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2395,15 +2395,15 @@ static DisasJumpType op_diag(DisasContext *s, DisasOps *o) static DisasJumpType op_divs32(DisasContext *s, DisasOps *o) { - gen_helper_divs32(o->out2, cpu_env, o->in1, o->in2); - return_low128(o->out); + gen_helper_divs32(o->out, cpu_env, o->in1, o->in2); + tcg_gen_extr32_i64(o->out2, o->out, o->out); return DISAS_NEXT; } static DisasJumpType op_divu32(DisasContext *s, DisasOps *o) { - gen_helper_divu32(o->out2, cpu_env, o->in1, o->in2); - return_low128(o->out); + gen_helper_divu32(o->out, cpu_env, o->in1, o->in2); + tcg_gen_extr32_i64(o->out2, o->out, o->out); return DISAS_NEXT; } -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:38:47 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELaA-00064m-RF for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:38:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELa6-0005qa-Uu for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:42 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZH-0004Y0-EH for qemu-riscv@nongnu.org; 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Ilya Leoshkevich Subject: [PATCH v4 26/36] target/s390x: Use Int128 for return from CLST Date: Sat, 7 Jan 2023 18:37:09 -0800 Message-Id: <20230108023719.2466341-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:38:43 -0000 Reviewed-by: Philippe Mathieu-Daudé Acked-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 +- target/s390x/tcg/mem_helper.c | 11 ++++------- target/s390x/tcg/translate.c | 8 ++++++-- 3 files changed, 11 insertions(+), 10 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 593f3c8bee..25c2dd0b3c 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -16,7 +16,7 @@ DEF_HELPER_FLAGS_3(divs64, TCG_CALL_NO_WG, i128, env, s64, s64) DEF_HELPER_FLAGS_4(divu64, TCG_CALL_NO_WG, i128, env, i64, i64, i64) DEF_HELPER_3(srst, void, env, i32, i32) DEF_HELPER_3(srstu, void, env, i32, i32) -DEF_HELPER_4(clst, i64, env, i64, i64, i64) +DEF_HELPER_4(clst, i128, env, i64, i64, i64) DEF_HELPER_FLAGS_4(mvn, TCG_CALL_NO_WG, void, env, i32, i64, i64) DEF_HELPER_FLAGS_4(mvo, TCG_CALL_NO_WG, void, env, i32, i64, i64) DEF_HELPER_FLAGS_4(mvpg, TCG_CALL_NO_WG, i32, env, i64, i32, i32) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index cb82cd1c1d..9be42851d8 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -886,7 +886,7 @@ void HELPER(srstu)(CPUS390XState *env, uint32_t r1, uint32_t r2) } /* unsigned string compare (c is string terminator) */ -uint64_t HELPER(clst)(CPUS390XState *env, uint64_t c, uint64_t s1, uint64_t s2) +Int128 HELPER(clst)(CPUS390XState *env, uint64_t c, uint64_t s1, uint64_t s2) { uintptr_t ra = GETPC(); uint32_t len; @@ -904,23 +904,20 @@ uint64_t HELPER(clst)(CPUS390XState *env, uint64_t c, uint64_t s1, uint64_t s2) if (v1 == c) { /* Equal. CC=0, and don't advance the registers. */ env->cc_op = 0; - env->retxl = s2; - return s1; + return int128_make128(s2, s1); } } else { /* Unequal. CC={1,2}, and advance the registers. Note that the terminator need not be zero, but the string that contains the terminator is by definition "low". */ env->cc_op = (v1 == c ? 1 : v2 == c ? 2 : v1 < v2 ? 1 : 2); - env->retxl = s2 + len; - return s1 + len; + return int128_make128(s2 + len, s1 + len); } } /* CPU-determined bytes equal; advance the registers. */ env->cc_op = 3; - env->retxl = s2 + len; - return s1 + len; + return int128_make128(s2 + len, s1 + len); } /* move page */ diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 6953b81de7..8397fe2bd8 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2164,9 +2164,13 @@ static DisasJumpType op_clm(DisasContext *s, DisasOps *o) static DisasJumpType op_clst(DisasContext *s, DisasOps *o) { - gen_helper_clst(o->in1, cpu_env, regs[0], o->in1, o->in2); + TCGv_i128 pair = tcg_temp_new_i128(); + + gen_helper_clst(pair, cpu_env, regs[0], o->in1, o->in2); + tcg_gen_extr_i128_i64(o->in2, o->in1, pair); + tcg_temp_free_i128(pair); + set_cc_static(s); - return_low128(o->in2); return DISAS_NEXT; } -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:38:48 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELaB-00067h-HI for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:38:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELa9-0005vw-Na for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:45 -0500 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZH-0004jm-U8 for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:45 -0500 Received: by mail-pj1-x1032.google.com with SMTP id v13-20020a17090a6b0d00b00219c3be9830so5819401pjj.4 for ; Sat, 07 Jan 2023 18:37:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eH8QC2IFkRWe6pofdb+MHZgnEhO+cdUQERbeKdouJGM=; b=TegwglnL6q7iVTSGCpZcoM+tVYYCB0J+zT6QfcVW8A3uqu9fs9/M/S7aIYXTb9MeCq 6dAGsHTy/eqwhddJoWnJcioaLlzMzqXE8wwz9dgy5CIYcZuaaFqXuIVFmTXn76ZmOS7I GaPS5AFZt3FGUrr5CqsMUhPdM4gu1mGkSO9qRjiafE2nqMnN8XWaAcJ1Pbg9mAYxDT84 1ZGu4l/knxUXydyMvkAlbE9mnv021BghbD8jZUXdlittqV6cmkxoylWR0F20J4Z6nSyT RqCM/WbUSfr+fyaLfHdwxfSRQubpUcbI2T2TDki/jkvoylrffqxMV6s7FCq3nuxo7Dpr 7kqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eH8QC2IFkRWe6pofdb+MHZgnEhO+cdUQERbeKdouJGM=; b=GXi0tWqRkB2n8DamDAfnDNTCezqxCS4HNdm1ELKhEluowydWvHVVv//w9TLqo4hKt3 geb1fBXej45W//RoF4PlBG/J4YDj7YpJ/PyH3OuzFOGgggkdouUwP/TpOEjuZdF0v0Jl J0CAoBZELRavvSZtSVe6zxvfncYQR300785mSDkQ2ldMl1JiaQmbuqOhwIGdet7GPP5+ 2nXaV7T0yvwS4+dsf/4Sb0DZi6ItVJ1nfsy/lVyji/8B67KDMmU7Tlt7KBa/6/Qb9u0C TNjVXSkcOu3v82BTOelHMkA0lXlhFa/vct7eiyOc/Bss5itzctZxf+jcNwoWDjUoC8Pe Nixw== X-Gm-Message-State: AFqh2kqeKrXJGhfFGzkf+15Wrz5Q7gcot9IAgfibJKGHets3V2hyiAKm 2jwv3C7kQvIcD2ZGnQPPVbRLcw== X-Google-Smtp-Source: AMrXdXupJwah+yPV5ipT071gNOmgS29NLVbHgjh5KW4ngV3P2mAtXvN3lAMXz5T2PiLtQZbGfiPjVg== X-Received: by 2002:a17:903:189:b0:189:ba1f:b178 with SMTP id z9-20020a170903018900b00189ba1fb178mr97835919plg.9.1673145470705; Sat, 07 Jan 2023 18:37:50 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Ilya Leoshkevich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 27/36] target/s390x: Use Int128 for return from CKSM Date: Sat, 7 Jan 2023 18:37:10 -0800 Message-Id: <20230108023719.2466341-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:38:46 -0000 Acked-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 +- target/s390x/tcg/mem_helper.c | 7 +++---- target/s390x/tcg/translate.c | 6 ++++-- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 25c2dd0b3c..03b29efa3e 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -103,7 +103,7 @@ DEF_HELPER_4(tre, i64, env, i64, i64, i64) DEF_HELPER_4(trt, i32, env, i32, i64, i64) DEF_HELPER_4(trtr, i32, env, i32, i64, i64) DEF_HELPER_5(trXX, i32, env, i32, i32, i32, i32) -DEF_HELPER_4(cksm, i64, env, i64, i64, i64) +DEF_HELPER_4(cksm, i128, env, i64, i64, i64) DEF_HELPER_FLAGS_5(calc_cc, TCG_CALL_NO_RWG_SE, i32, env, i32, i64, i64, i64) DEF_HELPER_FLAGS_2(sfpc, TCG_CALL_NO_WG, void, env, i64) DEF_HELPER_FLAGS_2(sfas, TCG_CALL_NO_WG, void, env, i64) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 9be42851d8..b0b403e23a 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1350,8 +1350,8 @@ uint32_t HELPER(clclu)(CPUS390XState *env, uint32_t r1, uint64_t a2, } /* checksum */ -uint64_t HELPER(cksm)(CPUS390XState *env, uint64_t r1, - uint64_t src, uint64_t src_len) +Int128 HELPER(cksm)(CPUS390XState *env, uint64_t r1, + uint64_t src, uint64_t src_len) { uintptr_t ra = GETPC(); uint64_t max_len, len; @@ -1392,8 +1392,7 @@ uint64_t HELPER(cksm)(CPUS390XState *env, uint64_t r1, env->cc_op = (len == src_len ? 0 : 3); /* Return both cksm and processed length. */ - env->retxl = cksm; - return len; + return int128_make128(cksm, len); } void HELPER(pack)(CPUS390XState *env, uint32_t len, uint64_t dest, uint64_t src) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 8397fe2bd8..1a7aa9e4ae 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2041,11 +2041,13 @@ static DisasJumpType op_cxlgb(DisasContext *s, DisasOps *o) static DisasJumpType op_cksm(DisasContext *s, DisasOps *o) { int r2 = get_field(s, r2); + TCGv_i128 pair = tcg_temp_new_i128(); TCGv_i64 len = tcg_temp_new_i64(); - gen_helper_cksm(len, cpu_env, o->in1, o->in2, regs[r2 + 1]); + gen_helper_cksm(pair, cpu_env, o->in1, o->in2, regs[r2 + 1]); set_cc_static(s); - return_low128(o->out); + tcg_gen_extr_i128_i64(o->out, len, pair); + tcg_temp_free_i128(pair); tcg_gen_add_i64(regs[r2], regs[r2], len); tcg_gen_sub_i64(regs[r2 + 1], regs[r2 + 1], len); -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:38:49 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELaD-0006EE-7p for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:38:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELaB-00067q-PA for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:47 -0500 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZJ-0004kW-5c for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:47 -0500 Received: by mail-pl1-x636.google.com with SMTP id jl4so5864177plb.8 for ; Sat, 07 Jan 2023 18:37:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=U/HSkpGEvHbItuZnMKBTZy7j63PzLUxQ950pxrJaTtQ=; b=Cabsn7PefcqmPGGmkreUHmuZqTbdJT501NMjsX90Okc5g3KqmMzGE95eDzNKFphZ49 EtqsmzjmXCkbiQPPWfvHOcHAkNmm5pQrnNVoCUiSh5XPONfR3jwSJCaeZYWS7jfknop0 2m0h8l2goW7YQyMwq6I2tFHoXe1EmV2CJ2D3r1YVYaryu7ppXZl9ZpbT4P2i5/syC9/o RJm92msy/NrziUaHc0FoIfKl3CESE9VTgKpo5ZhAYySfyrBmF0R7XpYLlwO6kmdRDECm MpYqkG92xxDyjALHr0sTaDqlM5RmUocQeQ2rQjv4xzYXo2O5BBf7npN8+3XsBfcgG5mS 3rdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=U/HSkpGEvHbItuZnMKBTZy7j63PzLUxQ950pxrJaTtQ=; b=jumizvZkh+obMjLtTqv2iutXmzHg0P6juKqQGjN5dtq3x5Ld+XS68PXH+SVW2TZt01 nfPJfHQUdUMq5D8tzdYspQVReL0IaUzgRb+3Llt2JA6gbQEalKFPDx06Soi+4/q1WibR +yTnu+WDiinA2vlmIwAHPFl2rtrHd/6fEv+puZRp+b0REfNWt7vrVKC+ducOychSwU77 VewIY/jqFX/dKIeawyWbGL8Kl1w78d7skKEsHokXiPOmegTwp9eIho+moIpe0VU6BU3T m2tE3Q3NCHJ5UBiyGjewCmlKK7GaLvWDDn7lEObQM8AEaDB3l/9F3RQcIf03ud9RPfwH JRAg== X-Gm-Message-State: AFqh2ko4Ow2ToTqYO0nzfk1uAyYoB0T/obCdHDGU+0vawlDAs8MU0PcC b1grxn/L4uBrrzY2bg1PRFjbLw== X-Google-Smtp-Source: AMrXdXvIf7OOxb/PpscaAZCQPmbwZzR6roE+2SGtqXco7lTFIuD8c4seNc4FNzs7hcGPAnsqgOPW+Q== X-Received: by 2002:a17:903:110d:b0:192:8b0e:98e1 with SMTP id n13-20020a170903110d00b001928b0e98e1mr53826505plh.54.1673145471955; Sat, 07 Jan 2023 18:37:51 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Ilya Leoshkevich , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 28/36] target/s390x: Use Int128 for return from TRE Date: Sat, 7 Jan 2023 18:37:11 -0800 Message-Id: <20230108023719.2466341-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:38:48 -0000 Acked-by: Ilya Leoshkevich Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 +- target/s390x/tcg/mem_helper.c | 7 +++---- target/s390x/tcg/translate.c | 7 +++++-- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index 03b29efa3e..b4170a4256 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -99,7 +99,7 @@ DEF_HELPER_FLAGS_4(unpka, TCG_CALL_NO_WG, i32, env, i64, i32, i64) DEF_HELPER_FLAGS_4(unpku, TCG_CALL_NO_WG, i32, env, i64, i32, i64) DEF_HELPER_FLAGS_3(tp, TCG_CALL_NO_WG, i32, env, i64, i32) DEF_HELPER_FLAGS_4(tr, TCG_CALL_NO_WG, void, env, i32, i64, i64) -DEF_HELPER_4(tre, i64, env, i64, i64, i64) +DEF_HELPER_4(tre, i128, env, i64, i64, i64) DEF_HELPER_4(trt, i32, env, i32, i64, i64) DEF_HELPER_4(trtr, i32, env, i32, i64, i64) DEF_HELPER_5(trXX, i32, env, i32, i32, i32, i32) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index b0b403e23a..49969abda7 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1632,8 +1632,8 @@ void HELPER(tr)(CPUS390XState *env, uint32_t len, uint64_t array, do_helper_tr(env, len, array, trans, GETPC()); } -uint64_t HELPER(tre)(CPUS390XState *env, uint64_t array, - uint64_t len, uint64_t trans) +Int128 HELPER(tre)(CPUS390XState *env, uint64_t array, + uint64_t len, uint64_t trans) { uintptr_t ra = GETPC(); uint8_t end = env->regs[0] & 0xff; @@ -1668,8 +1668,7 @@ uint64_t HELPER(tre)(CPUS390XState *env, uint64_t array, } env->cc_op = cc; - env->retxl = len - i; - return array + i; + return int128_make128(len - i, array + i); } static inline uint32_t do_helper_trt(CPUS390XState *env, int len, diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 1a7aa9e4ae..f3e4b70ed9 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -4905,8 +4905,11 @@ static DisasJumpType op_tr(DisasContext *s, DisasOps *o) static DisasJumpType op_tre(DisasContext *s, DisasOps *o) { - gen_helper_tre(o->out, cpu_env, o->out, o->out2, o->in2); - return_low128(o->out2); + TCGv_i128 pair = tcg_temp_new_i128(); + + gen_helper_tre(pair, cpu_env, o->out, o->out2, o->in2); + tcg_gen_extr_i128_i64(o->out2, o->out, pair); + tcg_temp_free_i128(pair); set_cc_static(s); return DISAS_NEXT; } -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:38:51 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELaF-0006IW-N5 for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:38:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELaE-0006GB-8N for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:50 -0500 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZK-0004l6-8f for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:49 -0500 Received: by mail-pl1-x629.google.com with SMTP id jl4so5864198plb.8 for ; Sat, 07 Jan 2023 18:37:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Ilya Leoshkevich Subject: [PATCH v4 29/36] target/s390x: Copy wout_x1 to wout_x1_P Date: Sat, 7 Jan 2023 18:37:12 -0800 Message-Id: <20230108023719.2466341-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:38:50 -0000 Make a copy of wout_x1 before modifying it, as wout_x1_P emphasizing that it operates on the out/out2 pair. The insns that use x1_P are data movement that will not change to Int128. Acked-by: Ilya Leoshkevich Signed-off-by: Richard Henderson --- target/s390x/tcg/insn-data.h.inc | 12 ++++++------ target/s390x/tcg/translate.c | 8 ++++++++ 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc index 79c6ab509a..d0814cb218 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -422,7 +422,7 @@ F(0x3800, LER, RR_a, Z, 0, e2, 0, cond_e1e2, mov2, 0, IF_AFP1 | IF_AFP2) F(0x7800, LE, RX_a, Z, 0, m2_32u, 0, e1, mov2, 0, IF_AFP1) F(0xed64, LEY, RXY_a, LD, 0, m2_32u, 0, e1, mov2, 0, IF_AFP1) - F(0xb365, LXR, RRE, Z, x2h, x2l, 0, x1, movx, 0, IF_AFP1) + F(0xb365, LXR, RRE, Z, x2h, x2l, 0, x1_P, movx, 0, IF_AFP1) /* LOAD IMMEDIATE */ C(0xc001, LGFI, RIL_a, EI, 0, i2, 0, r1, mov2, 0) /* LOAD RELATIVE LONG */ @@ -461,7 +461,7 @@ C(0xe332, LTGF, RXY_a, GIE, 0, a2, r1, 0, ld32s, s64) F(0xb302, LTEBR, RRE, Z, 0, e2, 0, cond_e1e2, mov2, f32, IF_BFP) F(0xb312, LTDBR, RRE, Z, 0, f2, 0, f1, mov2, f64, IF_BFP) - F(0xb342, LTXBR, RRE, Z, x2h, x2l, 0, x1, movx, f128, IF_BFP) + F(0xb342, LTXBR, RRE, Z, x2h, x2l, 0, x1_P, movx, f128, IF_BFP) /* LOAD AND TRAP */ C(0xe39f, LAT, RXY_a, LAT, 0, m2_32u, r1, 0, lat, 0) C(0xe385, LGAT, RXY_a, LAT, 0, a2, r1, 0, lgat, 0) @@ -483,7 +483,7 @@ C(0xb913, LCGFR, RRE, Z, 0, r2_32s, r1, 0, neg, neg64) F(0xb303, LCEBR, RRE, Z, 0, e2, new, e1, negf32, f32, IF_BFP) F(0xb313, LCDBR, RRE, Z, 0, f2, new, f1, negf64, f64, IF_BFP) - F(0xb343, LCXBR, RRE, Z, x2h, x2l, new_P, x1, negf128, f128, IF_BFP) + F(0xb343, LCXBR, RRE, Z, x2h, x2l, new_P, x1_P, negf128, f128, IF_BFP) F(0xb373, LCDFR, RRE, FPSSH, 0, f2, new, f1, negf64, 0, IF_AFP1 | IF_AFP2) /* LOAD COUNT TO BLOCK BOUNDARY */ C(0xe727, LCBB, RXE, V, la2, 0, r1, 0, lcbb, 0) @@ -552,7 +552,7 @@ C(0xb911, LNGFR, RRE, Z, 0, r2_32s, r1, 0, nabs, nabs64) F(0xb301, LNEBR, RRE, Z, 0, e2, new, e1, nabsf32, f32, IF_BFP) F(0xb311, LNDBR, RRE, Z, 0, f2, new, f1, nabsf64, f64, IF_BFP) - F(0xb341, LNXBR, RRE, Z, x2h, x2l, new_P, x1, nabsf128, f128, IF_BFP) + F(0xb341, LNXBR, RRE, Z, x2h, x2l, new_P, x1_P, nabsf128, f128, IF_BFP) F(0xb371, LNDFR, RRE, FPSSH, 0, f2, new, f1, nabsf64, 0, IF_AFP1 | IF_AFP2) /* LOAD ON CONDITION */ C(0xb9f2, LOCR, RRF_c, LOC, r1, r2, new, r1_32, loc, 0) @@ -577,7 +577,7 @@ C(0xb910, LPGFR, RRE, Z, 0, r2_32s, r1, 0, abs, abs64) F(0xb300, LPEBR, RRE, Z, 0, e2, new, e1, absf32, f32, IF_BFP) F(0xb310, LPDBR, RRE, Z, 0, f2, new, f1, absf64, f64, IF_BFP) - F(0xb340, LPXBR, RRE, Z, x2h, x2l, new_P, x1, absf128, f128, IF_BFP) + F(0xb340, LPXBR, RRE, Z, x2h, x2l, new_P, x1_P, absf128, f128, IF_BFP) F(0xb370, LPDFR, RRE, FPSSH, 0, f2, new, f1, absf64, 0, IF_AFP1 | IF_AFP2) /* LOAD REVERSED */ C(0xb91f, LRVR, RRE, Z, 0, r2_32u, new, r1_32, rev32, 0) @@ -588,7 +588,7 @@ /* LOAD ZERO */ F(0xb374, LZER, RRE, Z, 0, 0, 0, e1, zero, 0, IF_AFP1) F(0xb375, LZDR, RRE, Z, 0, 0, 0, f1, zero, 0, IF_AFP1) - F(0xb376, LZXR, RRE, Z, 0, 0, 0, x1, zero2, 0, IF_AFP1) + F(0xb376, LZXR, RRE, Z, 0, 0, 0, x1_P, zero2, 0, IF_AFP1) /* LOAD FPC */ F(0xb29d, LFPC, S, Z, 0, m2_32u, 0, 0, sfpc, 0, IF_BFP) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index f3e4b70ed9..d25b6f3c03 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -5518,6 +5518,14 @@ static void wout_x1(DisasContext *s, DisasOps *o) } #define SPEC_wout_x1 SPEC_r1_f128 +static void wout_x1_P(DisasContext *s, DisasOps *o) +{ + int f1 = get_field(s, r1); + store_freg(f1, o->out); + store_freg(f1 + 2, o->out2); +} +#define SPEC_wout_x1_P SPEC_r1_f128 + static void wout_cond_r1r2_32(DisasContext *s, DisasOps *o) { if (get_field(s, r1) != get_field(s, r2)) { -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:39:03 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELaR-0006Wy-39 for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:39:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELaK-0006LQ-Ly for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:56 -0500 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZL-0004lg-Ap for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:38:53 -0500 Received: by mail-pj1-x1036.google.com with SMTP id dw9so3960098pjb.5 for ; Sat, 07 Jan 2023 18:37:54 -0800 (PST) DKIM-Signature: v=1; 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Sat, 07 Jan 2023 18:37:54 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 30/36] target/s390x: Use Int128 for returning float128 Date: Sat, 7 Jan 2023 18:37:13 -0800 Message-Id: <20230108023719.2466341-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:38:57 -0000 Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- v2: Remove extraneous return_low128. --- target/s390x/helper.h | 22 +++++++------- target/s390x/tcg/insn-data.h.inc | 20 ++++++------- target/s390x/tcg/fpu_helper.c | 29 +++++++++--------- target/s390x/tcg/translate.c | 51 +++++++++++++++++--------------- 4 files changed, 63 insertions(+), 59 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index b4170a4256..d40aeb471f 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -31,32 +31,32 @@ DEF_HELPER_4(clcle, i32, env, i32, i64, i32) DEF_HELPER_4(clclu, i32, env, i32, i64, i32) DEF_HELPER_3(cegb, i64, env, s64, i32) DEF_HELPER_3(cdgb, i64, env, s64, i32) -DEF_HELPER_3(cxgb, i64, env, s64, i32) +DEF_HELPER_3(cxgb, i128, env, s64, i32) DEF_HELPER_3(celgb, i64, env, i64, i32) DEF_HELPER_3(cdlgb, i64, env, i64, i32) -DEF_HELPER_3(cxlgb, i64, env, i64, i32) +DEF_HELPER_3(cxlgb, i128, env, i64, i32) DEF_HELPER_4(cdsg, void, env, i64, i32, i32) DEF_HELPER_4(cdsg_parallel, void, env, i64, i32, i32) DEF_HELPER_4(csst, i32, env, i32, i64, i64) DEF_HELPER_4(csst_parallel, i32, env, i32, i64, i64) DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(adb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) DEF_HELPER_FLAGS_3(seb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(sdb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(sxb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_5(sxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) DEF_HELPER_FLAGS_3(deb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(ddb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(dxb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_5(dxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) DEF_HELPER_FLAGS_3(meeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(mdeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(mdb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(mxb, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i64) -DEF_HELPER_FLAGS_4(mxdb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_5(mxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_4(mxdb, TCG_CALL_NO_WG, i128, env, i64, i64, i64) DEF_HELPER_FLAGS_2(ldeb, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_4(ldxb, TCG_CALL_NO_WG, i64, env, i64, i64, i32) -DEF_HELPER_FLAGS_2(lxdb, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_2(lxeb, TCG_CALL_NO_WG, i64, env, i64) +DEF_HELPER_FLAGS_2(lxdb, TCG_CALL_NO_WG, i128, env, i64) +DEF_HELPER_FLAGS_2(lxeb, TCG_CALL_NO_WG, i128, env, i64) DEF_HELPER_FLAGS_3(ledb, TCG_CALL_NO_WG, i64, env, i64, i32) DEF_HELPER_FLAGS_4(lexb, TCG_CALL_NO_WG, i64, env, i64, i64, i32) DEF_HELPER_FLAGS_3(ceb, TCG_CALL_NO_WG_SE, i32, env, i64, i64) @@ -79,7 +79,7 @@ DEF_HELPER_3(clfdb, i64, env, i64, i32) DEF_HELPER_4(clfxb, i64, env, i64, i64, i32) DEF_HELPER_FLAGS_3(fieb, TCG_CALL_NO_WG, i64, env, i64, i32) DEF_HELPER_FLAGS_3(fidb, TCG_CALL_NO_WG, i64, env, i64, i32) -DEF_HELPER_FLAGS_4(fixb, TCG_CALL_NO_WG, i64, env, i64, i64, i32) +DEF_HELPER_FLAGS_4(fixb, TCG_CALL_NO_WG, i128, env, i64, i64, i32) DEF_HELPER_FLAGS_4(maeb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(madb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(mseb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) @@ -89,7 +89,7 @@ DEF_HELPER_FLAGS_3(tcdb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64) DEF_HELPER_FLAGS_4(tcxb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64, i64) DEF_HELPER_FLAGS_2(sqeb, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(sqdb, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_3(sqxb, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(sqxb, TCG_CALL_NO_WG, i128, env, i64, i64) DEF_HELPER_FLAGS_1(cvd, TCG_CALL_NO_RWG_SE, i64, s32) DEF_HELPER_FLAGS_4(pack, TCG_CALL_NO_WG, void, env, i32, i64, i64) DEF_HELPER_FLAGS_4(pka, TCG_CALL_NO_WG, void, env, i64, i64, i32) diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc index d0814cb218..517a4500ae 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -306,10 +306,10 @@ /* CONVERT FROM FIXED */ F(0xb394, CEFBR, RRF_e, Z, 0, r2_32s, new, e1, cegb, 0, IF_BFP) F(0xb395, CDFBR, RRF_e, Z, 0, r2_32s, new, f1, cdgb, 0, IF_BFP) - F(0xb396, CXFBR, RRF_e, Z, 0, r2_32s, new_P, x1, cxgb, 0, IF_BFP) + F(0xb396, CXFBR, RRF_e, Z, 0, r2_32s, new_x, x1, cxgb, 0, IF_BFP) F(0xb3a4, CEGBR, RRF_e, Z, 0, r2_o, new, e1, cegb, 0, IF_BFP) F(0xb3a5, CDGBR, RRF_e, Z, 0, r2_o, new, f1, cdgb, 0, IF_BFP) - F(0xb3a6, CXGBR, RRF_e, Z, 0, r2_o, new_P, x1, cxgb, 0, IF_BFP) + F(0xb3a6, CXGBR, RRF_e, Z, 0, r2_o, new_x, x1, cxgb, 0, IF_BFP) /* CONVERT TO LOGICAL */ F(0xb39c, CLFEBR, RRF_e, FPE, 0, e2, new, r1_32, clfeb, 0, IF_BFP) F(0xb39d, CLFDBR, RRF_e, FPE, 0, f2, new, r1_32, clfdb, 0, IF_BFP) @@ -320,10 +320,10 @@ /* CONVERT FROM LOGICAL */ F(0xb390, CELFBR, RRF_e, FPE, 0, r2_32u, new, e1, celgb, 0, IF_BFP) F(0xb391, CDLFBR, RRF_e, FPE, 0, r2_32u, new, f1, cdlgb, 0, IF_BFP) - F(0xb392, CXLFBR, RRF_e, FPE, 0, r2_32u, new_P, x1, cxlgb, 0, IF_BFP) + F(0xb392, CXLFBR, RRF_e, FPE, 0, r2_32u, new_x, x1, cxlgb, 0, IF_BFP) F(0xb3a0, CELGBR, RRF_e, FPE, 0, r2_o, new, e1, celgb, 0, IF_BFP) F(0xb3a1, CDLGBR, RRF_e, FPE, 0, r2_o, new, f1, cdlgb, 0, IF_BFP) - F(0xb3a2, CXLGBR, RRF_e, FPE, 0, r2_o, new_P, x1, cxlgb, 0, IF_BFP) + F(0xb3a2, CXLGBR, RRF_e, FPE, 0, r2_o, new_x, x1, cxlgb, 0, IF_BFP) /* CONVERT UTF-8 TO UTF-16 */ D(0xb2a7, CU12, RRF_c, Z, 0, 0, 0, 0, cuXX, 0, 12) @@ -597,15 +597,15 @@ /* LOAD FP INTEGER */ F(0xb357, FIEBR, RRF_e, Z, 0, e2, new, e1, fieb, 0, IF_BFP) F(0xb35f, FIDBR, RRF_e, Z, 0, f2, new, f1, fidb, 0, IF_BFP) - F(0xb347, FIXBR, RRF_e, Z, x2h, x2l, new_P, x1, fixb, 0, IF_BFP) + F(0xb347, FIXBR, RRF_e, Z, x2h, x2l, new_x, x1, fixb, 0, IF_BFP) /* LOAD LENGTHENED */ F(0xb304, LDEBR, RRE, Z, 0, e2, new, f1, ldeb, 0, IF_BFP) - F(0xb305, LXDBR, RRE, Z, 0, f2, new_P, x1, lxdb, 0, IF_BFP) - F(0xb306, LXEBR, RRE, Z, 0, e2, new_P, x1, lxeb, 0, IF_BFP) + F(0xb305, LXDBR, RRE, Z, 0, f2, new_x, x1, lxdb, 0, IF_BFP) + F(0xb306, LXEBR, RRE, Z, 0, e2, new_x, x1, lxeb, 0, IF_BFP) F(0xed04, LDEB, RXE, Z, 0, m2_32u, new, f1, ldeb, 0, IF_BFP) - F(0xed05, LXDB, RXE, Z, 0, m2_64, new_P, x1, lxdb, 0, IF_BFP) - F(0xed06, LXEB, RXE, Z, 0, m2_32u, new_P, x1, lxeb, 0, IF_BFP) + F(0xed05, LXDB, RXE, Z, 0, m2_64, new_x, x1, lxdb, 0, IF_BFP) + F(0xed06, LXEB, RXE, Z, 0, m2_32u, new_x, x1, lxeb, 0, IF_BFP) F(0xb324, LDER, RXE, Z, 0, e2, new, f1, lde, 0, IF_AFP1) F(0xed24, LDE, RXE, Z, 0, m2_32u, new, f1, lde, 0, IF_AFP1) /* LOAD ROUNDED */ @@ -835,7 +835,7 @@ /* SQUARE ROOT */ F(0xb314, SQEBR, RRE, Z, 0, e2, new, e1, sqeb, 0, IF_BFP) F(0xb315, SQDBR, RRE, Z, 0, f2, new, f1, sqdb, 0, IF_BFP) - F(0xb316, SQXBR, RRE, Z, x2h, x2l, new_P, x1, sqxb, 0, IF_BFP) + F(0xb316, SQXBR, RRE, Z, x2h, x2l, new_x, x1, sqxb, 0, IF_BFP) F(0xed14, SQEB, RXE, Z, 0, m2_32u, new, e1, sqeb, 0, IF_BFP) F(0xed15, SQDB, RXE, Z, 0, m2_64, new, f1, sqdb, 0, IF_BFP) diff --git a/target/s390x/tcg/fpu_helper.c b/target/s390x/tcg/fpu_helper.c index be80b2373c..13be44499b 100644 --- a/target/s390x/tcg/fpu_helper.c +++ b/target/s390x/tcg/fpu_helper.c @@ -34,7 +34,10 @@ #define HELPER_LOG(x...) #endif -#define RET128(F) (env->retxl = F.low, F.high) +static inline Int128 RET128(float128 f) +{ + return int128_make128(f.low, f.high); +} uint8_t s390_softfloat_exc_to_ieee(unsigned int exc) { @@ -224,7 +227,7 @@ uint64_t HELPER(adb)(CPUS390XState *env, uint64_t f1, uint64_t f2) } /* 128-bit FP addition */ -uint64_t HELPER(axb)(CPUS390XState *env, uint64_t ah, uint64_t al, +Int128 HELPER(axb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl) { float128 ret = float128_add(make_float128(ah, al), @@ -251,7 +254,7 @@ uint64_t HELPER(sdb)(CPUS390XState *env, uint64_t f1, uint64_t f2) } /* 128-bit FP subtraction */ -uint64_t HELPER(sxb)(CPUS390XState *env, uint64_t ah, uint64_t al, +Int128 HELPER(sxb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl) { float128 ret = float128_sub(make_float128(ah, al), @@ -278,7 +281,7 @@ uint64_t HELPER(ddb)(CPUS390XState *env, uint64_t f1, uint64_t f2) } /* 128-bit FP division */ -uint64_t HELPER(dxb)(CPUS390XState *env, uint64_t ah, uint64_t al, +Int128 HELPER(dxb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl) { float128 ret = float128_div(make_float128(ah, al), @@ -314,7 +317,7 @@ uint64_t HELPER(mdeb)(CPUS390XState *env, uint64_t f1, uint64_t f2) } /* 128-bit FP multiplication */ -uint64_t HELPER(mxb)(CPUS390XState *env, uint64_t ah, uint64_t al, +Int128 HELPER(mxb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl) { float128 ret = float128_mul(make_float128(ah, al), @@ -325,8 +328,7 @@ uint64_t HELPER(mxb)(CPUS390XState *env, uint64_t ah, uint64_t al, } /* 128/64-bit FP multiplication */ -uint64_t HELPER(mxdb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t f2) +Int128 HELPER(mxdb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t f2) { float128 ret = float64_to_float128(f2, &env->fpu_status); ret = float128_mul(make_float128(ah, al), ret, &env->fpu_status); @@ -355,7 +357,7 @@ uint64_t HELPER(ldxb)(CPUS390XState *env, uint64_t ah, uint64_t al, } /* convert 64-bit float to 128-bit float */ -uint64_t HELPER(lxdb)(CPUS390XState *env, uint64_t f2) +Int128 HELPER(lxdb)(CPUS390XState *env, uint64_t f2) { float128 ret = float64_to_float128(f2, &env->fpu_status); handle_exceptions(env, false, GETPC()); @@ -363,7 +365,7 @@ uint64_t HELPER(lxdb)(CPUS390XState *env, uint64_t f2) } /* convert 32-bit float to 128-bit float */ -uint64_t HELPER(lxeb)(CPUS390XState *env, uint64_t f2) +Int128 HELPER(lxeb)(CPUS390XState *env, uint64_t f2) { float128 ret = float32_to_float128(f2, &env->fpu_status); handle_exceptions(env, false, GETPC()); @@ -486,7 +488,7 @@ uint64_t HELPER(cdgb)(CPUS390XState *env, int64_t v2, uint32_t m34) } /* convert 64-bit int to 128-bit float */ -uint64_t HELPER(cxgb)(CPUS390XState *env, int64_t v2, uint32_t m34) +Int128 HELPER(cxgb)(CPUS390XState *env, int64_t v2, uint32_t m34) { int old_mode = s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); float128 ret = int64_to_float128(v2, &env->fpu_status); @@ -519,7 +521,7 @@ uint64_t HELPER(cdlgb)(CPUS390XState *env, uint64_t v2, uint32_t m34) } /* convert 64-bit uint to 128-bit float */ -uint64_t HELPER(cxlgb)(CPUS390XState *env, uint64_t v2, uint32_t m34) +Int128 HELPER(cxlgb)(CPUS390XState *env, uint64_t v2, uint32_t m34) { int old_mode = s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); float128 ret = uint64_to_float128(v2, &env->fpu_status); @@ -748,8 +750,7 @@ uint64_t HELPER(fidb)(CPUS390XState *env, uint64_t f2, uint32_t m34) } /* round to integer 128-bit */ -uint64_t HELPER(fixb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint32_t m34) +Int128 HELPER(fixb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint32_t m34) { int old_mode = s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); float128 ret = float128_round_to_int(make_float128(ah, al), @@ -890,7 +891,7 @@ uint64_t HELPER(sqdb)(CPUS390XState *env, uint64_t f2) } /* square root 128-bit */ -uint64_t HELPER(sqxb)(CPUS390XState *env, uint64_t ah, uint64_t al) +Int128 HELPER(sqxb)(CPUS390XState *env, uint64_t ah, uint64_t al) { float128 ret = float128_sqrt(make_float128(ah, al), &env->fpu_status); handle_exceptions(env, false, GETPC()); diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index d25b6f3c03..0a750a5467 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1103,6 +1103,7 @@ typedef struct { bool g_out, g_out2, g_in1, g_in2; TCGv_i64 out, out2, in1, in2; TCGv_i64 addr1; + TCGv_i128 out_128; } DisasOps; /* Instructions can place constraints on their operands, raising specification @@ -1461,8 +1462,7 @@ static DisasJumpType op_adb(DisasContext *s, DisasOps *o) static DisasJumpType op_axb(DisasContext *s, DisasOps *o) { - gen_helper_axb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2); - return_low128(o->out2); + gen_helper_axb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); return DISAS_NEXT; } @@ -1995,9 +1995,8 @@ static DisasJumpType op_cxgb(DisasContext *s, DisasOps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cxgb(o->out, cpu_env, o->in2, m34); + gen_helper_cxgb(o->out_128, cpu_env, o->in2, m34); tcg_temp_free_i32(m34); - return_low128(o->out2); return DISAS_NEXT; } @@ -2032,9 +2031,8 @@ static DisasJumpType op_cxlgb(DisasContext *s, DisasOps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cxlgb(o->out, cpu_env, o->in2, m34); + gen_helper_cxlgb(o->out_128, cpu_env, o->in2, m34); tcg_temp_free_i32(m34); - return_low128(o->out2); return DISAS_NEXT; } @@ -2447,8 +2445,7 @@ static DisasJumpType op_ddb(DisasContext *s, DisasOps *o) static DisasJumpType op_dxb(DisasContext *s, DisasOps *o) { - gen_helper_dxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2); - return_low128(o->out2); + gen_helper_dxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); return DISAS_NEXT; } @@ -2553,8 +2550,7 @@ static DisasJumpType op_fixb(DisasContext *s, DisasOps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_fixb(o->out, cpu_env, o->in1, o->in2, m34); - return_low128(o->out2); + gen_helper_fixb(o->out_128, cpu_env, o->in1, o->in2, m34); tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2866,15 +2862,13 @@ static DisasJumpType op_lexb(DisasContext *s, DisasOps *o) static DisasJumpType op_lxdb(DisasContext *s, DisasOps *o) { - gen_helper_lxdb(o->out, cpu_env, o->in2); - return_low128(o->out2); + gen_helper_lxdb(o->out_128, cpu_env, o->in2); return DISAS_NEXT; } static DisasJumpType op_lxeb(DisasContext *s, DisasOps *o) { - gen_helper_lxeb(o->out, cpu_env, o->in2); - return_low128(o->out2); + gen_helper_lxeb(o->out_128, cpu_env, o->in2); return DISAS_NEXT; } @@ -3590,15 +3584,13 @@ static DisasJumpType op_mdb(DisasContext *s, DisasOps *o) static DisasJumpType op_mxb(DisasContext *s, DisasOps *o) { - gen_helper_mxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2); - return_low128(o->out2); + gen_helper_mxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); return DISAS_NEXT; } static DisasJumpType op_mxdb(DisasContext *s, DisasOps *o) { - gen_helper_mxdb(o->out, cpu_env, o->out, o->out2, o->in2); - return_low128(o->out2); + gen_helper_mxdb(o->out_128, cpu_env, o->out, o->out2, o->in2); return DISAS_NEXT; } @@ -4063,8 +4055,7 @@ static DisasJumpType op_sdb(DisasContext *s, DisasOps *o) static DisasJumpType op_sxb(DisasContext *s, DisasOps *o) { - gen_helper_sxb(o->out, cpu_env, o->out, o->out2, o->in1, o->in2); - return_low128(o->out2); + gen_helper_sxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); return DISAS_NEXT; } @@ -4082,8 +4073,7 @@ static DisasJumpType op_sqdb(DisasContext *s, DisasOps *o) static DisasJumpType op_sqxb(DisasContext *s, DisasOps *o) { - gen_helper_sqxb(o->out, cpu_env, o->in1, o->in2); - return_low128(o->out2); + gen_helper_sqxb(o->out_128, cpu_env, o->in1, o->in2); return DISAS_NEXT; } @@ -5395,6 +5385,14 @@ static void prep_new_P(DisasContext *s, DisasOps *o) } #define SPEC_prep_new_P 0 +static void prep_new_x(DisasContext *s, DisasOps *o) +{ + o->out = tcg_temp_new_i64(); + o->out2 = tcg_temp_new_i64(); + o->out_128 = tcg_temp_new_i128(); +} +#define SPEC_prep_new_x 0 + static void prep_r1(DisasContext *s, DisasOps *o) { o->out = regs[get_field(s, r1)]; @@ -5411,11 +5409,12 @@ static void prep_r1_P(DisasContext *s, DisasOps *o) } #define SPEC_prep_r1_P SPEC_r1_even -/* Whenever we need x1 in addition to other inputs, we'll load it to out/out2 */ static void prep_x1(DisasContext *s, DisasOps *o) { o->out = load_freg(get_field(s, r1)); o->out2 = load_freg(get_field(s, r1) + 2); + o->out_128 = tcg_temp_new_i128(); + tcg_gen_concat_i64_i128(o->out_128, o->out2, o->out); } #define SPEC_prep_x1 SPEC_r1_f128 @@ -5513,6 +5512,8 @@ static void wout_f1(DisasContext *s, DisasOps *o) static void wout_x1(DisasContext *s, DisasOps *o) { int f1 = get_field(s, r1); + + tcg_gen_extr_i128_i64(o->out2, o->out, o->out_128); store_freg(f1, o->out); store_freg(f1 + 2, o->out2); } @@ -6588,7 +6589,9 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) if (o.addr1) { tcg_temp_free_i64(o.addr1); } - + if (o.out_128) { + tcg_temp_free_i128(o.out_128); + } /* io should be the last instruction in tb when icount is enabled */ if (unlikely(icount && ret == DISAS_NEXT)) { ret = DISAS_TOO_MANY; -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:39:15 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELac-0006js-Ks for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:39:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELaP-0006RK-IO for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:39:02 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZM-0004mK-Kz for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:39:01 -0500 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 31/36] target/s390x: Use Int128 for passing float128 Date: Sat, 7 Jan 2023 18:37:14 -0800 Message-Id: <20230108023719.2466341-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:39:03 -0000 Signed-off-by: Richard Henderson --- v2: Fix SPEC_in1_x1. --- target/s390x/helper.h | 32 ++++++------ target/s390x/tcg/insn-data.h.inc | 30 +++++------ target/s390x/tcg/fpu_helper.c | 88 ++++++++++++++------------------ target/s390x/tcg/translate.c | 76 ++++++++++++++++++--------- 4 files changed, 121 insertions(+), 105 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index d40aeb471f..bccd3bfca6 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -41,55 +41,55 @@ DEF_HELPER_4(csst, i32, env, i32, i64, i64) DEF_HELPER_4(csst_parallel, i32, env, i32, i64, i64) DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(adb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(axb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(axb, TCG_CALL_NO_WG, i128, env, i128, i128) DEF_HELPER_FLAGS_3(seb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(sdb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(sxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(sxb, TCG_CALL_NO_WG, i128, env, i128, i128) DEF_HELPER_FLAGS_3(deb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(ddb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(dxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(dxb, TCG_CALL_NO_WG, i128, env, i128, i128) DEF_HELPER_FLAGS_3(meeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(mdeb, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_3(mdb, TCG_CALL_NO_WG, i64, env, i64, i64) -DEF_HELPER_FLAGS_5(mxb, TCG_CALL_NO_WG, i128, env, i64, i64, i64, i64) -DEF_HELPER_FLAGS_4(mxdb, TCG_CALL_NO_WG, i128, env, i64, i64, i64) +DEF_HELPER_FLAGS_3(mxb, TCG_CALL_NO_WG, i128, env, i128, i128) +DEF_HELPER_FLAGS_3(mxdb, TCG_CALL_NO_WG, i128, env, i128, i64) DEF_HELPER_FLAGS_2(ldeb, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_4(ldxb, TCG_CALL_NO_WG, i64, env, i64, i64, i32) +DEF_HELPER_FLAGS_3(ldxb, TCG_CALL_NO_WG, i64, env, i128, i32) DEF_HELPER_FLAGS_2(lxdb, TCG_CALL_NO_WG, i128, env, i64) DEF_HELPER_FLAGS_2(lxeb, TCG_CALL_NO_WG, i128, env, i64) DEF_HELPER_FLAGS_3(ledb, TCG_CALL_NO_WG, i64, env, i64, i32) -DEF_HELPER_FLAGS_4(lexb, TCG_CALL_NO_WG, i64, env, i64, i64, i32) +DEF_HELPER_FLAGS_3(lexb, TCG_CALL_NO_WG, i64, env, i128, i32) DEF_HELPER_FLAGS_3(ceb, TCG_CALL_NO_WG_SE, i32, env, i64, i64) DEF_HELPER_FLAGS_3(cdb, TCG_CALL_NO_WG_SE, i32, env, i64, i64) -DEF_HELPER_FLAGS_5(cxb, TCG_CALL_NO_WG_SE, i32, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(cxb, TCG_CALL_NO_WG_SE, i32, env, i128, i128) DEF_HELPER_FLAGS_3(keb, TCG_CALL_NO_WG, i32, env, i64, i64) DEF_HELPER_FLAGS_3(kdb, TCG_CALL_NO_WG, i32, env, i64, i64) -DEF_HELPER_FLAGS_5(kxb, TCG_CALL_NO_WG, i32, env, i64, i64, i64, i64) +DEF_HELPER_FLAGS_3(kxb, TCG_CALL_NO_WG, i32, env, i128, i128) DEF_HELPER_3(cgeb, i64, env, i64, i32) DEF_HELPER_3(cgdb, i64, env, i64, i32) -DEF_HELPER_4(cgxb, i64, env, i64, i64, i32) +DEF_HELPER_3(cgxb, i64, env, i128, i32) DEF_HELPER_3(cfeb, i64, env, i64, i32) DEF_HELPER_3(cfdb, i64, env, i64, i32) -DEF_HELPER_4(cfxb, i64, env, i64, i64, i32) +DEF_HELPER_3(cfxb, i64, env, i128, i32) DEF_HELPER_3(clgeb, i64, env, i64, i32) DEF_HELPER_3(clgdb, i64, env, i64, i32) -DEF_HELPER_4(clgxb, i64, env, i64, i64, i32) +DEF_HELPER_3(clgxb, i64, env, i128, i32) DEF_HELPER_3(clfeb, i64, env, i64, i32) DEF_HELPER_3(clfdb, i64, env, i64, i32) -DEF_HELPER_4(clfxb, i64, env, i64, i64, i32) +DEF_HELPER_3(clfxb, i64, env, i128, i32) DEF_HELPER_FLAGS_3(fieb, TCG_CALL_NO_WG, i64, env, i64, i32) DEF_HELPER_FLAGS_3(fidb, TCG_CALL_NO_WG, i64, env, i64, i32) -DEF_HELPER_FLAGS_4(fixb, TCG_CALL_NO_WG, i128, env, i64, i64, i32) +DEF_HELPER_FLAGS_3(fixb, TCG_CALL_NO_WG, i128, env, i128, i32) DEF_HELPER_FLAGS_4(maeb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(madb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(mseb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_4(msdb, TCG_CALL_NO_WG, i64, env, i64, i64, i64) DEF_HELPER_FLAGS_3(tceb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64) DEF_HELPER_FLAGS_3(tcdb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64) -DEF_HELPER_FLAGS_4(tcxb, TCG_CALL_NO_RWG_SE, i32, env, i64, i64, i64) +DEF_HELPER_FLAGS_3(tcxb, TCG_CALL_NO_RWG_SE, i32, env, i128, i64) DEF_HELPER_FLAGS_2(sqeb, TCG_CALL_NO_WG, i64, env, i64) DEF_HELPER_FLAGS_2(sqdb, TCG_CALL_NO_WG, i64, env, i64) -DEF_HELPER_FLAGS_3(sqxb, TCG_CALL_NO_WG, i128, env, i64, i64) +DEF_HELPER_FLAGS_2(sqxb, TCG_CALL_NO_WG, i128, env, i128) DEF_HELPER_FLAGS_1(cvd, TCG_CALL_NO_RWG_SE, i64, s32) DEF_HELPER_FLAGS_4(pack, TCG_CALL_NO_WG, void, env, i32, i64, i64) DEF_HELPER_FLAGS_4(pka, TCG_CALL_NO_WG, void, env, i64, i64, i32) diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc index 517a4500ae..893f4b48db 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -34,7 +34,7 @@ C(0xe318, AGF, RXY_a, Z, r1, m2_32s, r1, 0, add, adds64) F(0xb30a, AEBR, RRE, Z, e1, e2, new, e1, aeb, f32, IF_BFP) F(0xb31a, ADBR, RRE, Z, f1, f2, new, f1, adb, f64, IF_BFP) - F(0xb34a, AXBR, RRE, Z, x2h, x2l, x1, x1, axb, f128, IF_BFP) + F(0xb34a, AXBR, RRE, Z, x1, x2, new_x, x1, axb, f128, IF_BFP) F(0xed0a, AEB, RXE, Z, e1, m2_32u, new, e1, aeb, f32, IF_BFP) F(0xed1a, ADB, RXE, Z, f1, m2_64, new, f1, adb, f64, IF_BFP) /* ADD HIGH */ @@ -172,13 +172,13 @@ C(0xe330, CGF, RXY_a, Z, r1_o, m2_32s, 0, 0, 0, cmps64) F(0xb309, CEBR, RRE, Z, e1, e2, 0, 0, ceb, 0, IF_BFP) F(0xb319, CDBR, RRE, Z, f1, f2, 0, 0, cdb, 0, IF_BFP) - F(0xb349, CXBR, RRE, Z, x2h, x2l, x1, 0, cxb, 0, IF_BFP) + F(0xb349, CXBR, RRE, Z, x1, x2, 0, 0, cxb, 0, IF_BFP) F(0xed09, CEB, RXE, Z, e1, m2_32u, 0, 0, ceb, 0, IF_BFP) F(0xed19, CDB, RXE, Z, f1, m2_64, 0, 0, cdb, 0, IF_BFP) /* COMPARE AND SIGNAL */ F(0xb308, KEBR, RRE, Z, e1, e2, 0, 0, keb, 0, IF_BFP) F(0xb318, KDBR, RRE, Z, f1, f2, 0, 0, kdb, 0, IF_BFP) - F(0xb348, KXBR, RRE, Z, x2h, x2l, x1, 0, kxb, 0, IF_BFP) + F(0xb348, KXBR, RRE, Z, x1, x2, 0, 0, kxb, 0, IF_BFP) F(0xed08, KEB, RXE, Z, e1, m2_32u, 0, 0, keb, 0, IF_BFP) F(0xed18, KDB, RXE, Z, f1, m2_64, 0, 0, kdb, 0, IF_BFP) /* COMPARE IMMEDIATE */ @@ -299,10 +299,10 @@ /* CONVERT TO FIXED */ F(0xb398, CFEBR, RRF_e, Z, 0, e2, new, r1_32, cfeb, 0, IF_BFP) F(0xb399, CFDBR, RRF_e, Z, 0, f2, new, r1_32, cfdb, 0, IF_BFP) - F(0xb39a, CFXBR, RRF_e, Z, x2h, x2l, new, r1_32, cfxb, 0, IF_BFP) + F(0xb39a, CFXBR, RRF_e, Z, 0, x2, new, r1_32, cfxb, 0, IF_BFP) F(0xb3a8, CGEBR, RRF_e, Z, 0, e2, r1, 0, cgeb, 0, IF_BFP) F(0xb3a9, CGDBR, RRF_e, Z, 0, f2, r1, 0, cgdb, 0, IF_BFP) - F(0xb3aa, CGXBR, RRF_e, Z, x2h, x2l, r1, 0, cgxb, 0, IF_BFP) + F(0xb3aa, CGXBR, RRF_e, Z, 0, x2, r1, 0, cgxb, 0, IF_BFP) /* CONVERT FROM FIXED */ F(0xb394, CEFBR, RRF_e, Z, 0, r2_32s, new, e1, cegb, 0, IF_BFP) F(0xb395, CDFBR, RRF_e, Z, 0, r2_32s, new, f1, cdgb, 0, IF_BFP) @@ -313,10 +313,10 @@ /* CONVERT TO LOGICAL */ F(0xb39c, CLFEBR, RRF_e, FPE, 0, e2, new, r1_32, clfeb, 0, IF_BFP) F(0xb39d, CLFDBR, RRF_e, FPE, 0, f2, new, r1_32, clfdb, 0, IF_BFP) - F(0xb39e, CLFXBR, RRF_e, FPE, x2h, x2l, new, r1_32, clfxb, 0, IF_BFP) + F(0xb39e, CLFXBR, RRF_e, FPE, 0, x2, new, r1_32, clfxb, 0, IF_BFP) F(0xb3ac, CLGEBR, RRF_e, FPE, 0, e2, r1, 0, clgeb, 0, IF_BFP) F(0xb3ad, CLGDBR, RRF_e, FPE, 0, f2, r1, 0, clgdb, 0, IF_BFP) - F(0xb3ae, CLGXBR, RRF_e, FPE, x2h, x2l, r1, 0, clgxb, 0, IF_BFP) + F(0xb3ae, CLGXBR, RRF_e, FPE, 0, x2, r1, 0, clgxb, 0, IF_BFP) /* CONVERT FROM LOGICAL */ F(0xb390, CELFBR, RRF_e, FPE, 0, r2_32u, new, e1, celgb, 0, IF_BFP) F(0xb391, CDLFBR, RRF_e, FPE, 0, r2_32u, new, f1, cdlgb, 0, IF_BFP) @@ -343,7 +343,7 @@ C(0x5d00, D, RX_a, Z, r1_D32, m2_32s, new_P, r1_P32, divs32, 0) F(0xb30d, DEBR, RRE, Z, e1, e2, new, e1, deb, 0, IF_BFP) F(0xb31d, DDBR, RRE, Z, f1, f2, new, f1, ddb, 0, IF_BFP) - F(0xb34d, DXBR, RRE, Z, x2h, x2l, x1, x1, dxb, 0, IF_BFP) + F(0xb34d, DXBR, RRE, Z, x1, x2, new_x, x1, dxb, 0, IF_BFP) F(0xed0d, DEB, RXE, Z, e1, m2_32u, new, e1, deb, 0, IF_BFP) F(0xed1d, DDB, RXE, Z, f1, m2_64, new, f1, ddb, 0, IF_BFP) /* DIVIDE LOGICAL */ @@ -597,7 +597,7 @@ /* LOAD FP INTEGER */ F(0xb357, FIEBR, RRF_e, Z, 0, e2, new, e1, fieb, 0, IF_BFP) F(0xb35f, FIDBR, RRF_e, Z, 0, f2, new, f1, fidb, 0, IF_BFP) - F(0xb347, FIXBR, RRF_e, Z, x2h, x2l, new_x, x1, fixb, 0, IF_BFP) + F(0xb347, FIXBR, RRF_e, Z, 0, x2, new_x, x1, fixb, 0, IF_BFP) /* LOAD LENGTHENED */ F(0xb304, LDEBR, RRE, Z, 0, e2, new, f1, ldeb, 0, IF_BFP) @@ -610,8 +610,8 @@ F(0xed24, LDE, RXE, Z, 0, m2_32u, new, f1, lde, 0, IF_AFP1) /* LOAD ROUNDED */ F(0xb344, LEDBR, RRF_e, Z, 0, f2, new, e1, ledb, 0, IF_BFP) - F(0xb345, LDXBR, RRF_e, Z, x2h, x2l, new, f1, ldxb, 0, IF_BFP) - F(0xb346, LEXBR, RRF_e, Z, x2h, x2l, new, e1, lexb, 0, IF_BFP) + F(0xb345, LDXBR, RRF_e, Z, 0, x2, new, f1, ldxb, 0, IF_BFP) + F(0xb346, LEXBR, RRF_e, Z, 0, x2, new, e1, lexb, 0, IF_BFP) /* LOAD MULTIPLE */ C(0x9800, LM, RS_a, Z, 0, a2, 0, 0, lm32, 0) @@ -666,7 +666,7 @@ C(0xe384, MG, RXY_a, MIE2,r1p1_o, m2_64, r1_P, 0, muls128, 0) F(0xb317, MEEBR, RRE, Z, e1, e2, new, e1, meeb, 0, IF_BFP) F(0xb31c, MDBR, RRE, Z, f1, f2, new, f1, mdb, 0, IF_BFP) - F(0xb34c, MXBR, RRE, Z, x2h, x2l, x1, x1, mxb, 0, IF_BFP) + F(0xb34c, MXBR, RRE, Z, x1, x2, new_x, x1, mxb, 0, IF_BFP) F(0xb30c, MDEBR, RRE, Z, f1, e2, new, f1, mdeb, 0, IF_BFP) F(0xb307, MXDBR, RRE, Z, 0, f2, x1, x1, mxdb, 0, IF_BFP) F(0xed17, MEEB, RXE, Z, e1, m2_32u, new, e1, meeb, 0, IF_BFP) @@ -835,7 +835,7 @@ /* SQUARE ROOT */ F(0xb314, SQEBR, RRE, Z, 0, e2, new, e1, sqeb, 0, IF_BFP) F(0xb315, SQDBR, RRE, Z, 0, f2, new, f1, sqdb, 0, IF_BFP) - F(0xb316, SQXBR, RRE, Z, x2h, x2l, new_x, x1, sqxb, 0, IF_BFP) + F(0xb316, SQXBR, RRE, Z, 0, x2, new_x, x1, sqxb, 0, IF_BFP) F(0xed14, SQEB, RXE, Z, 0, m2_32u, new, e1, sqeb, 0, IF_BFP) F(0xed15, SQDB, RXE, Z, 0, m2_64, new, f1, sqdb, 0, IF_BFP) @@ -913,7 +913,7 @@ C(0xe319, SGF, RXY_a, Z, r1, m2_32s, r1, 0, sub, subs64) F(0xb30b, SEBR, RRE, Z, e1, e2, new, e1, seb, f32, IF_BFP) F(0xb31b, SDBR, RRE, Z, f1, f2, new, f1, sdb, f64, IF_BFP) - F(0xb34b, SXBR, RRE, Z, x2h, x2l, x1, x1, sxb, f128, IF_BFP) + F(0xb34b, SXBR, RRE, Z, x1, x2, new_x, x1, sxb, f128, IF_BFP) F(0xed0b, SEB, RXE, Z, e1, m2_32u, new, e1, seb, f32, IF_BFP) F(0xed1b, SDB, RXE, Z, f1, m2_64, new, f1, sdb, f64, IF_BFP) /* SUBTRACT HALFWORD */ @@ -957,7 +957,7 @@ /* TEST DATA CLASS */ F(0xed10, TCEB, RXE, Z, e1, a2, 0, 0, tceb, 0, IF_BFP) F(0xed11, TCDB, RXE, Z, f1, a2, 0, 0, tcdb, 0, IF_BFP) - F(0xed12, TCXB, RXE, Z, 0, a2, x1, 0, tcxb, 0, IF_BFP) + F(0xed12, TCXB, RXE, Z, x1, a2, 0, 0, tcxb, 0, IF_BFP) /* TEST DECIMAL */ C(0xebc0, TP, RSL, E2, la1, 0, 0, 0, tp, 0) diff --git a/target/s390x/tcg/fpu_helper.c b/target/s390x/tcg/fpu_helper.c index 13be44499b..0bdab5bcf7 100644 --- a/target/s390x/tcg/fpu_helper.c +++ b/target/s390x/tcg/fpu_helper.c @@ -39,6 +39,11 @@ static inline Int128 RET128(float128 f) return int128_make128(f.low, f.high); } +static inline float128 ARG128(Int128 i) +{ + return make_float128(int128_gethi(i), int128_getlo(i)); +} + uint8_t s390_softfloat_exc_to_ieee(unsigned int exc) { uint8_t s390_exc = 0; @@ -227,12 +232,9 @@ uint64_t HELPER(adb)(CPUS390XState *env, uint64_t f1, uint64_t f2) } /* 128-bit FP addition */ -Int128 HELPER(axb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +Int128 HELPER(axb)(CPUS390XState *env, Int128 a, Int128 b) { - float128 ret = float128_add(make_float128(ah, al), - make_float128(bh, bl), - &env->fpu_status); + float128 ret = float128_add(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } @@ -254,12 +256,9 @@ uint64_t HELPER(sdb)(CPUS390XState *env, uint64_t f1, uint64_t f2) } /* 128-bit FP subtraction */ -Int128 HELPER(sxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +Int128 HELPER(sxb)(CPUS390XState *env, Int128 a, Int128 b) { - float128 ret = float128_sub(make_float128(ah, al), - make_float128(bh, bl), - &env->fpu_status); + float128 ret = float128_sub(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } @@ -281,12 +280,9 @@ uint64_t HELPER(ddb)(CPUS390XState *env, uint64_t f1, uint64_t f2) } /* 128-bit FP division */ -Int128 HELPER(dxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +Int128 HELPER(dxb)(CPUS390XState *env, Int128 a, Int128 b) { - float128 ret = float128_div(make_float128(ah, al), - make_float128(bh, bl), - &env->fpu_status); + float128 ret = float128_div(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } @@ -317,21 +313,18 @@ uint64_t HELPER(mdeb)(CPUS390XState *env, uint64_t f1, uint64_t f2) } /* 128-bit FP multiplication */ -Int128 HELPER(mxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +Int128 HELPER(mxb)(CPUS390XState *env, Int128 a, Int128 b) { - float128 ret = float128_mul(make_float128(ah, al), - make_float128(bh, bl), - &env->fpu_status); + float128 ret = float128_mul(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } /* 128/64-bit FP multiplication */ -Int128 HELPER(mxdb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t f2) +Int128 HELPER(mxdb)(CPUS390XState *env, Int128 a, uint64_t f2) { float128 ret = float64_to_float128(f2, &env->fpu_status); - ret = float128_mul(make_float128(ah, al), ret, &env->fpu_status); + ret = float128_mul(ARG128(a), ret, &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } @@ -345,11 +338,10 @@ uint64_t HELPER(ldeb)(CPUS390XState *env, uint64_t f2) } /* convert 128-bit float to 64-bit float */ -uint64_t HELPER(ldxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint32_t m34) +uint64_t HELPER(ldxb)(CPUS390XState *env, Int128 a, uint32_t m34) { int old_mode = s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float64 ret = float128_to_float64(make_float128(ah, al), &env->fpu_status); + float64 ret = float128_to_float64(ARG128(a), &env->fpu_status); s390_restore_bfp_rounding_mode(env, old_mode); handle_exceptions(env, xxc_from_m34(m34), GETPC()); @@ -384,11 +376,10 @@ uint64_t HELPER(ledb)(CPUS390XState *env, uint64_t f2, uint32_t m34) } /* convert 128-bit float to 32-bit float */ -uint64_t HELPER(lexb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint32_t m34) +uint64_t HELPER(lexb)(CPUS390XState *env, Int128 a, uint32_t m34) { int old_mode = s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float32 ret = float128_to_float32(make_float128(ah, al), &env->fpu_status); + float32 ret = float128_to_float32(ARG128(a), &env->fpu_status); s390_restore_bfp_rounding_mode(env, old_mode); handle_exceptions(env, xxc_from_m34(m34), GETPC()); @@ -412,11 +403,9 @@ uint32_t HELPER(cdb)(CPUS390XState *env, uint64_t f1, uint64_t f2) } /* 128-bit FP compare */ -uint32_t HELPER(cxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +uint32_t HELPER(cxb)(CPUS390XState *env, Int128 a, Int128 b) { - FloatRelation cmp = float128_compare_quiet(make_float128(ah, al), - make_float128(bh, bl), + FloatRelation cmp = float128_compare_quiet(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return float_comp_to_cc(env, cmp); @@ -564,10 +553,10 @@ uint64_t HELPER(cgdb)(CPUS390XState *env, uint64_t v2, uint32_t m34) } /* convert 128-bit float to 64-bit int */ -uint64_t HELPER(cgxb)(CPUS390XState *env, uint64_t h, uint64_t l, uint32_t m34) +uint64_t HELPER(cgxb)(CPUS390XState *env, Int128 i2, uint32_t m34) { int old_mode = s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float128 v2 = make_float128(h, l); + float128 v2 = ARG128(i2); int64_t ret = float128_to_int64(v2, &env->fpu_status); uint32_t cc = set_cc_conv_f128(v2, &env->fpu_status); @@ -613,10 +602,10 @@ uint64_t HELPER(cfdb)(CPUS390XState *env, uint64_t v2, uint32_t m34) } /* convert 128-bit float to 32-bit int */ -uint64_t HELPER(cfxb)(CPUS390XState *env, uint64_t h, uint64_t l, uint32_t m34) +uint64_t HELPER(cfxb)(CPUS390XState *env, Int128 i2, uint32_t m34) { int old_mode = s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float128 v2 = make_float128(h, l); + float128 v2 = ARG128(i2); int32_t ret = float128_to_int32(v2, &env->fpu_status); uint32_t cc = set_cc_conv_f128(v2, &env->fpu_status); @@ -662,10 +651,10 @@ uint64_t HELPER(clgdb)(CPUS390XState *env, uint64_t v2, uint32_t m34) } /* convert 128-bit float to 64-bit uint */ -uint64_t HELPER(clgxb)(CPUS390XState *env, uint64_t h, uint64_t l, uint32_t m34) +uint64_t HELPER(clgxb)(CPUS390XState *env, Int128 i2, uint32_t m34) { int old_mode = s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float128 v2 = make_float128(h, l); + float128 v2 = ARG128(i2); uint64_t ret = float128_to_uint64(v2, &env->fpu_status); uint32_t cc = set_cc_conv_f128(v2, &env->fpu_status); @@ -711,10 +700,10 @@ uint64_t HELPER(clfdb)(CPUS390XState *env, uint64_t v2, uint32_t m34) } /* convert 128-bit float to 32-bit uint */ -uint64_t HELPER(clfxb)(CPUS390XState *env, uint64_t h, uint64_t l, uint32_t m34) +uint64_t HELPER(clfxb)(CPUS390XState *env, Int128 i2, uint32_t m34) { int old_mode = s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float128 v2 = make_float128(h, l); + float128 v2 = ARG128(i2); uint32_t ret = float128_to_uint32(v2, &env->fpu_status); uint32_t cc = set_cc_conv_f128(v2, &env->fpu_status); @@ -750,11 +739,10 @@ uint64_t HELPER(fidb)(CPUS390XState *env, uint64_t f2, uint32_t m34) } /* round to integer 128-bit */ -Int128 HELPER(fixb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint32_t m34) +Int128 HELPER(fixb)(CPUS390XState *env, Int128 a, uint32_t m34) { int old_mode = s390_swap_bfp_rounding_mode(env, round_from_m34(m34)); - float128 ret = float128_round_to_int(make_float128(ah, al), - &env->fpu_status); + float128 ret = float128_round_to_int(ARG128(a), &env->fpu_status); s390_restore_bfp_rounding_mode(env, old_mode); handle_exceptions(env, xxc_from_m34(m34), GETPC()); @@ -778,11 +766,9 @@ uint32_t HELPER(kdb)(CPUS390XState *env, uint64_t f1, uint64_t f2) } /* 128-bit FP compare and signal */ -uint32_t HELPER(kxb)(CPUS390XState *env, uint64_t ah, uint64_t al, - uint64_t bh, uint64_t bl) +uint32_t HELPER(kxb)(CPUS390XState *env, Int128 a, Int128 b) { - FloatRelation cmp = float128_compare(make_float128(ah, al), - make_float128(bh, bl), + FloatRelation cmp = float128_compare(ARG128(a), ARG128(b), &env->fpu_status); handle_exceptions(env, false, GETPC()); return float_comp_to_cc(env, cmp); @@ -869,9 +855,9 @@ uint32_t HELPER(tcdb)(CPUS390XState *env, uint64_t v1, uint64_t m2) } /* test data class 128-bit */ -uint32_t HELPER(tcxb)(CPUS390XState *env, uint64_t ah, uint64_t al, uint64_t m2) +uint32_t HELPER(tcxb)(CPUS390XState *env, Int128 a, uint64_t m2) { - return (m2 & float128_dcmask(env, make_float128(ah, al))) != 0; + return (m2 & float128_dcmask(env, ARG128(a))) != 0; } /* square root 32-bit */ @@ -891,9 +877,9 @@ uint64_t HELPER(sqdb)(CPUS390XState *env, uint64_t f2) } /* square root 128-bit */ -Int128 HELPER(sqxb)(CPUS390XState *env, uint64_t ah, uint64_t al) +Int128 HELPER(sqxb)(CPUS390XState *env, Int128 a) { - float128 ret = float128_sqrt(make_float128(ah, al), &env->fpu_status); + float128 ret = float128_sqrt(ARG128(a), &env->fpu_status); handle_exceptions(env, false, GETPC()); return RET128(ret); } diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 0a750a5467..d422a1e62b 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -305,6 +305,18 @@ static TCGv_i64 load_freg32_i64(int reg) return r; } +static TCGv_i128 load_freg_128(int reg) +{ + TCGv_i64 h = load_freg(reg); + TCGv_i64 l = load_freg(reg + 2); + TCGv_i128 r = tcg_temp_new_i128(); + + tcg_gen_concat_i64_i128(r, l, h); + tcg_temp_free_i64(h); + tcg_temp_free_i64(l); + return r; +} + static void store_reg(int reg, TCGv_i64 v) { tcg_gen_mov_i64(regs[reg], v); @@ -1103,7 +1115,7 @@ typedef struct { bool g_out, g_out2, g_in1, g_in2; TCGv_i64 out, out2, in1, in2; TCGv_i64 addr1; - TCGv_i128 out_128; + TCGv_i128 out_128, in1_128, in2_128; } DisasOps; /* Instructions can place constraints on their operands, raising specification @@ -1462,7 +1474,7 @@ static DisasJumpType op_adb(DisasContext *s, DisasOps *o) static DisasJumpType op_axb(DisasContext *s, DisasOps *o) { - gen_helper_axb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_axb(o->out_128, cpu_env, o->in1_128, o->in2_128); return DISAS_NEXT; } @@ -1778,7 +1790,7 @@ static DisasJumpType op_cdb(DisasContext *s, DisasOps *o) static DisasJumpType op_cxb(DisasContext *s, DisasOps *o) { - gen_helper_cxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_cxb(cc_op, cpu_env, o->in1_128, o->in2_128); set_cc_static(s); return DISAS_NEXT; } @@ -1841,7 +1853,7 @@ static DisasJumpType op_cfxb(DisasContext *s, DisasOps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cfxb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_cfxb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; @@ -1880,7 +1892,7 @@ static DisasJumpType op_cgxb(DisasContext *s, DisasOps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_cgxb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_cgxb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; @@ -1919,7 +1931,7 @@ static DisasJumpType op_clfxb(DisasContext *s, DisasOps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_clfxb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_clfxb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; @@ -1958,7 +1970,7 @@ static DisasJumpType op_clgxb(DisasContext *s, DisasOps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_clgxb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_clgxb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); set_cc_static(s); return DISAS_NEXT; @@ -2445,7 +2457,7 @@ static DisasJumpType op_ddb(DisasContext *s, DisasOps *o) static DisasJumpType op_dxb(DisasContext *s, DisasOps *o) { - gen_helper_dxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_dxb(o->out_128, cpu_env, o->in1_128, o->in2_128); return DISAS_NEXT; } @@ -2550,7 +2562,7 @@ static DisasJumpType op_fixb(DisasContext *s, DisasOps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_fixb(o->out_128, cpu_env, o->in1, o->in2, m34); + gen_helper_fixb(o->out_128, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2769,7 +2781,7 @@ static DisasJumpType op_kdb(DisasContext *s, DisasOps *o) static DisasJumpType op_kxb(DisasContext *s, DisasOps *o) { - gen_helper_kxb(cc_op, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_kxb(cc_op, cpu_env, o->in1_128, o->in2_128); set_cc_static(s); return DISAS_NEXT; } @@ -2843,7 +2855,7 @@ static DisasJumpType op_ldxb(DisasContext *s, DisasOps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_ldxb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_ldxb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -2855,7 +2867,7 @@ static DisasJumpType op_lexb(DisasContext *s, DisasOps *o) if (!m34) { return DISAS_NORETURN; } - gen_helper_lexb(o->out, cpu_env, o->in1, o->in2, m34); + gen_helper_lexb(o->out, cpu_env, o->in2_128, m34); tcg_temp_free_i32(m34); return DISAS_NEXT; } @@ -3584,13 +3596,13 @@ static DisasJumpType op_mdb(DisasContext *s, DisasOps *o) static DisasJumpType op_mxb(DisasContext *s, DisasOps *o) { - gen_helper_mxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_mxb(o->out_128, cpu_env, o->in1_128, o->in2_128); return DISAS_NEXT; } static DisasJumpType op_mxdb(DisasContext *s, DisasOps *o) { - gen_helper_mxdb(o->out_128, cpu_env, o->out, o->out2, o->in2); + gen_helper_mxdb(o->out_128, cpu_env, o->in1_128, o->in2); return DISAS_NEXT; } @@ -4055,7 +4067,7 @@ static DisasJumpType op_sdb(DisasContext *s, DisasOps *o) static DisasJumpType op_sxb(DisasContext *s, DisasOps *o) { - gen_helper_sxb(o->out_128, cpu_env, o->out, o->out2, o->in1, o->in2); + gen_helper_sxb(o->out_128, cpu_env, o->in1_128, o->in2_128); return DISAS_NEXT; } @@ -4073,7 +4085,7 @@ static DisasJumpType op_sqdb(DisasContext *s, DisasOps *o) static DisasJumpType op_sqxb(DisasContext *s, DisasOps *o) { - gen_helper_sqxb(o->out_128, cpu_env, o->in1, o->in2); + gen_helper_sqxb(o->out_128, cpu_env, o->in2_128); return DISAS_NEXT; } @@ -4852,7 +4864,7 @@ static DisasJumpType op_tcdb(DisasContext *s, DisasOps *o) static DisasJumpType op_tcxb(DisasContext *s, DisasOps *o) { - gen_helper_tcxb(cc_op, cpu_env, o->out, o->out2, o->in2); + gen_helper_tcxb(cc_op, cpu_env, o->in1_128, o->in2); set_cc_static(s); return DISAS_NEXT; } @@ -5387,8 +5399,6 @@ static void prep_new_P(DisasContext *s, DisasOps *o) static void prep_new_x(DisasContext *s, DisasOps *o) { - o->out = tcg_temp_new_i64(); - o->out2 = tcg_temp_new_i64(); o->out_128 = tcg_temp_new_i128(); } #define SPEC_prep_new_x 0 @@ -5411,10 +5421,7 @@ static void prep_r1_P(DisasContext *s, DisasOps *o) static void prep_x1(DisasContext *s, DisasOps *o) { - o->out = load_freg(get_field(s, r1)); - o->out2 = load_freg(get_field(s, r1) + 2); - o->out_128 = tcg_temp_new_i128(); - tcg_gen_concat_i64_i128(o->out_128, o->out2, o->out); + o->out_128 = load_freg_128(get_field(s, r1)); } #define SPEC_prep_x1 SPEC_r1_f128 @@ -5513,6 +5520,11 @@ static void wout_x1(DisasContext *s, DisasOps *o) { int f1 = get_field(s, r1); + /* Split out_128 into out+out2 for cout_f128. */ + tcg_debug_assert(o->out == NULL); + o->out = tcg_temp_new_i64(); + o->out2 = tcg_temp_new_i64(); + tcg_gen_extr_i128_i64(o->out2, o->out, o->out_128); store_freg(f1, o->out); store_freg(f1 + 2, o->out2); @@ -5755,6 +5767,12 @@ static void in1_f1(DisasContext *s, DisasOps *o) } #define SPEC_in1_f1 0 +static void in1_x1(DisasContext *s, DisasOps *o) +{ + o->in1_128 = load_freg_128(get_field(s, r1)); +} +#define SPEC_in1_x1 SPEC_r1_f128 + /* Load the high double word of an extended (128-bit) format FP number */ static void in1_x2h(DisasContext *s, DisasOps *o) { @@ -5964,6 +5982,12 @@ static void in2_f2(DisasContext *s, DisasOps *o) } #define SPEC_in2_f2 0 +static void in2_x2(DisasContext *s, DisasOps *o) +{ + o->in2_128 = load_freg_128(get_field(s, r2)); +} +#define SPEC_in2_x2 SPEC_r2_f128 + /* Load the low double word of an extended (128-bit) format FP number */ static void in2_x2l(DisasContext *s, DisasOps *o) { @@ -6592,6 +6616,12 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) if (o.out_128) { tcg_temp_free_i128(o.out_128); } + if (o.in1_128) { + tcg_temp_free_i128(o.in1_128); + } + if (o.in2_128) { + tcg_temp_free_i128(o.in2_128); + } /* io should be the last instruction in tb when icount is enabled */ if (unlikely(icount && ret == DISAS_NEXT)) { ret = DISAS_TOO_MANY; -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:39:15 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELad-0006kw-Aw for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:39:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELaO-0006QT-Q0 for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:39:01 -0500 Received: from mail-pj1-x102c.google.com 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 32/36] target/s390x: Use tcg_gen_atomic_cmpxchg_i128 for CDSG Date: Sat, 7 Jan 2023 18:37:15 -0800 Message-Id: <20230108023719.2466341-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:39:01 -0000 Signed-off-by: Richard Henderson --- target/s390x/helper.h | 2 -- target/s390x/tcg/insn-data.h.inc | 2 +- target/s390x/tcg/mem_helper.c | 52 --------------------------- target/s390x/tcg/translate.c | 60 ++++++++++++++++++++------------ 4 files changed, 38 insertions(+), 78 deletions(-) diff --git a/target/s390x/helper.h b/target/s390x/helper.h index bccd3bfca6..341bc51ec2 100644 --- a/target/s390x/helper.h +++ b/target/s390x/helper.h @@ -35,8 +35,6 @@ DEF_HELPER_3(cxgb, i128, env, s64, i32) DEF_HELPER_3(celgb, i64, env, i64, i32) DEF_HELPER_3(cdlgb, i64, env, i64, i32) DEF_HELPER_3(cxlgb, i128, env, i64, i32) -DEF_HELPER_4(cdsg, void, env, i64, i32, i32) -DEF_HELPER_4(cdsg_parallel, void, env, i64, i32, i32) DEF_HELPER_4(csst, i32, env, i32, i64, i64) DEF_HELPER_4(csst_parallel, i32, env, i32, i64, i64) DEF_HELPER_FLAGS_3(aeb, TCG_CALL_NO_WG, i64, env, i64, i64) diff --git a/target/s390x/tcg/insn-data.h.inc b/target/s390x/tcg/insn-data.h.inc index 893f4b48db..ea34b4a277 100644 --- a/target/s390x/tcg/insn-data.h.inc +++ b/target/s390x/tcg/insn-data.h.inc @@ -276,7 +276,7 @@ /* COMPARE DOUBLE AND SWAP */ D(0xbb00, CDS, RS_a, Z, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_TEUQ) D(0xeb31, CDSY, RSY_a, LD, r3_D32, r1_D32, new, r1_D32, cs, 0, MO_TEUQ) - C(0xeb3e, CDSG, RSY_a, Z, 0, 0, 0, 0, cdsg, 0) + C(0xeb3e, CDSG, RSY_a, Z, la2, r3_D64, r1_D64, r1_D64, cdsg, 0) /* COMPARE AND SWAP AND STORE */ C(0xc802, CSST, SSF, CASS, la1, a2, 0, 0, csst, 0) diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index 49969abda7..d6725fd18c 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1771,58 +1771,6 @@ uint32_t HELPER(trXX)(CPUS390XState *env, uint32_t r1, uint32_t r2, return cc; } -void HELPER(cdsg)(CPUS390XState *env, uint64_t addr, - uint32_t r1, uint32_t r3) -{ - uintptr_t ra = GETPC(); - Int128 cmpv = int128_make128(env->regs[r1 + 1], env->regs[r1]); - Int128 newv = int128_make128(env->regs[r3 + 1], env->regs[r3]); - Int128 oldv; - uint64_t oldh, oldl; - bool fail; - - check_alignment(env, addr, 16, ra); - - oldh = cpu_ldq_data_ra(env, addr + 0, ra); - oldl = cpu_ldq_data_ra(env, addr + 8, ra); - - oldv = int128_make128(oldl, oldh); - fail = !int128_eq(oldv, cmpv); - if (fail) { - newv = oldv; - } - - cpu_stq_data_ra(env, addr + 0, int128_gethi(newv), ra); - cpu_stq_data_ra(env, addr + 8, int128_getlo(newv), ra); - - env->cc_op = fail; - env->regs[r1] = int128_gethi(oldv); - env->regs[r1 + 1] = int128_getlo(oldv); -} - -void HELPER(cdsg_parallel)(CPUS390XState *env, uint64_t addr, - uint32_t r1, uint32_t r3) -{ - uintptr_t ra = GETPC(); - Int128 cmpv = int128_make128(env->regs[r1 + 1], env->regs[r1]); - Int128 newv = int128_make128(env->regs[r3 + 1], env->regs[r3]); - int mem_idx; - MemOpIdx oi; - Int128 oldv; - bool fail; - - assert(HAVE_CMPXCHG128); - - mem_idx = cpu_mmu_index(env, false); - oi = make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx); - oldv = cpu_atomic_cmpxchgo_be_mmu(env, addr, cmpv, newv, oi, ra); - fail = !int128_eq(oldv, cmpv); - - env->cc_op = fail; - env->regs[r1] = int128_gethi(oldv); - env->regs[r1 + 1] = int128_getlo(oldv); -} - static uint32_t do_csst(CPUS390XState *env, uint32_t r3, uint64_t a1, uint64_t a2, bool parallel) { diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index d422a1e62b..0dafa27dab 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -2224,31 +2224,22 @@ static DisasJumpType op_cs(DisasContext *s, DisasOps *o) static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o) { int r1 = get_field(s, r1); - int r3 = get_field(s, r3); - int d2 = get_field(s, d2); - int b2 = get_field(s, b2); - DisasJumpType ret = DISAS_NEXT; - TCGv_i64 addr; - TCGv_i32 t_r1, t_r3; - /* Note that R1:R1+1 = expected value and R3:R3+1 = new value. */ - addr = get_address(s, 0, b2, d2); - t_r1 = tcg_const_i32(r1); - t_r3 = tcg_const_i32(r3); - if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cdsg(cpu_env, addr, t_r1, t_r3); - } else if (HAVE_CMPXCHG128) { - gen_helper_cdsg_parallel(cpu_env, addr, t_r1, t_r3); - } else { - gen_helper_exit_atomic(cpu_env); - ret = DISAS_NORETURN; - } - tcg_temp_free_i64(addr); - tcg_temp_free_i32(t_r1); - tcg_temp_free_i32(t_r3); + /* Note out (R1:R1+1) = expected value and in2 (R3:R3+1) = new value. */ + tcg_gen_atomic_cmpxchg_i128(o->out_128, o->addr1, o->out_128, o->in2_128, + get_mem_index(s), MO_BE | MO_128 | MO_ALIGN); - set_cc_static(s); - return ret; + /* + * Extract result into cc_dst:cc_src, compare vs the expected value + * in the as yet unmodified input registers, then update CC_OP. + */ + tcg_gen_extr_i128_i64(cc_src, cc_dst, o->out_128); + tcg_gen_xor_i64(cc_dst, cc_dst, regs[r1]); + tcg_gen_xor_i64(cc_src, cc_src, regs[r1 + 1]); + tcg_gen_or_i64(cc_dst, cc_dst, cc_src); + set_cc_nz_u64(s, cc_dst); + + return DISAS_NEXT; } static DisasJumpType op_csst(DisasContext *s, DisasOps *o) @@ -5419,6 +5410,14 @@ static void prep_r1_P(DisasContext *s, DisasOps *o) } #define SPEC_prep_r1_P SPEC_r1_even +static void prep_r1_D64(DisasContext *s, DisasOps *o) +{ + int r1 = get_field(s, r1); + o->out_128 = tcg_temp_new_i128(); + tcg_gen_concat_i64_i128(o->out_128, regs[r1 + 1], regs[r1]); +} +#define SPEC_prep_r1_D64 SPEC_r1_even + static void prep_x1(DisasContext *s, DisasOps *o) { o->out_128 = load_freg_128(get_field(s, r1)); @@ -5488,6 +5487,13 @@ static void wout_r1_D32(DisasContext *s, DisasOps *o) } #define SPEC_wout_r1_D32 SPEC_r1_even +static void wout_r1_D64(DisasContext *s, DisasOps *o) +{ + int r1 = get_field(s, r1); + tcg_gen_extr_i128_i64(regs[r1 + 1], regs[r1], o->out_128); +} +#define SPEC_wout_r1_D64 SPEC_r1_even + static void wout_r3_P32(DisasContext *s, DisasOps *o) { int r3 = get_field(s, r3); @@ -5935,6 +5941,14 @@ static void in2_r3(DisasContext *s, DisasOps *o) } #define SPEC_in2_r3 0 +static void in2_r3_D64(DisasContext *s, DisasOps *o) +{ + int r3 = get_field(s, r3); + o->in2_128 = tcg_temp_new_i128(); + tcg_gen_concat_i64_i128(o->in2_128, regs[r3 + 1], regs[r3]); +} +#define SPEC_in2_r3_D64 SPEC_r3_even + static void in2_r3_sr32(DisasContext *s, DisasOps *o) { o->in2 = tcg_temp_new_i64(); -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:39:16 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELad-0006m4-Vo for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:39:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELaQ-0006UN-0i for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:39:02 -0500 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZP-0004nR-9Q for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:39:01 -0500 Received: by mail-pl1-x632.google.com with SMTP id 17so5918035pll.0 for ; Sat, 07 Jan 2023 18:37:58 -0800 (PST) DKIM-Signature: v=1; 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([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 33/36] target/s390x: Implement CC_OP_NZ in gen_op_calc_cc Date: Sat, 7 Jan 2023 18:37:16 -0800 Message-Id: <20230108023719.2466341-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:39:03 -0000 This case is trivial to implement inline. Signed-off-by: Richard Henderson --- target/s390x/tcg/translate.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 0dafa27dab..b8cb21c395 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -625,6 +625,9 @@ static void gen_op_calc_cc(DisasContext *s) /* env->cc_op already is the cc value */ break; case CC_OP_NZ: + tcg_gen_setcondi_i64(TCG_COND_NE, cc_dst, cc_dst, 0); + tcg_gen_extrl_i64_i32(cc_op, cc_dst); + break; case CC_OP_ABS_64: case CC_OP_NABS_64: case CC_OP_ABS_32: -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:39:21 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELaj-0006pR-EE for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:39:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELaa-0006hq-Tf for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:39:13 -0500 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZR-0004oO-7O for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:39:06 -0500 Received: by mail-pj1-x102e.google.com with SMTP id h7-20020a17090aa88700b00225f3e4c992so9304108pjq.1 for ; Sat, 07 Jan 2023 18:38:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3xrOaDJVPE/CmdkY8im+Dl4QkQvUXux7CRjkgzX7WCc=; b=Vr7pPQ0Vc0da8CqPlxQPFJ4iAo8IUHkomwGS3CyijOiziB7ECFHyQEeK4aFoJZLz7q S7fxY59hce7PqHpOkqVNUeTFwZhS68Ef/TTfCLwopjG29LAqTX11JnCX8LwO5kM35E1V 8quXLh8FYORyUirF3vO/1PscXa6siTIIGsVEo5mKLkZGi7qUEpM0F8jFU07I9LKKcZ5z GEQXkvMEhf2hqOCeUsvErTt0UVDnFsP5Ptwj9BG9TiuF/NoknW2RcIGlj0J+Wb7W61oR 53AvWjCV22JwemnUIvnYW10INtjETRKRGAfOYCpmhiee/jsqvFySxNy3s1OQEGSfKed2 sdyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3xrOaDJVPE/CmdkY8im+Dl4QkQvUXux7CRjkgzX7WCc=; b=3Oehl+gNn/S7XHCWb3vkUyx3tmN20Wfy/cqZtkGJxpYHQOfJvHpK25Me6zyjnM2RsA U9mZy4eOFdjtpmdD1ykrTtH2yyiU79Zrwm4QHgqHpeiuU+XmPP1658dXAMFO4KNnGKVG mHjsRb3KxlMKn0aabTiI60eY/UAwxTmOZXt7Fh8sJBeC0oVxWZe/KUGNSIcsYCE3cVrY B4GJVvWbBvzE/whzLKAkSySBlD6ffp+ZXxX1EMWo5/5BMRjnaH432GPNjgN6LccAZhT6 S3Fka31uPCLrOUMo3q0eQVmVXsuVz1j0n8XIcy4fZUPyk5e5B6DOC/msElMU3ddUNC9O s/CQ== X-Gm-Message-State: AFqh2kqATy65xtR08luM0UUBbtHHlHFrAb1h7rrcu/cIxijXgqSFrcl3 mE3J3T4a+FOsopWVi/rM4R6FFg== X-Google-Smtp-Source: AMrXdXs6zlYtsN5O8W75nSeo0sOtBsn4uHgAwLvWjHAUGY8YABkDmResS2O353GK6NBU4IEM9CVcvw== X-Received: by 2002:a17:902:b609:b0:192:4ed2:7509 with SMTP id b9-20020a170902b60900b001924ed27509mr62839722pls.15.1673145480024; Sat, 07 Jan 2023 18:38:00 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 35/36] target/i386: Inline cmpxchg8b Date: Sat, 7 Jan 2023 18:37:18 -0800 Message-Id: <20230108023719.2466341-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:39:14 -0000 Use tcg_gen_atomic_cmpxchg_i64 for the atomic case, and tcg_gen_nonatomic_cmpxchg_i64 otherwise. Signed-off-by: Richard Henderson --- target/i386/helper.h | 2 -- target/i386/tcg/mem_helper.c | 57 ------------------------------------ target/i386/tcg/translate.c | 54 ++++++++++++++++++++++++++++++---- 3 files changed, 49 insertions(+), 64 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index b7de5429ef..2df8049f91 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -66,8 +66,6 @@ DEF_HELPER_1(rsm, void, env) #endif /* !CONFIG_USER_ONLY */ DEF_HELPER_2(into, void, env, int) -DEF_HELPER_2(cmpxchg8b_unlocked, void, env, tl) -DEF_HELPER_2(cmpxchg8b, void, env, tl) #ifdef TARGET_X86_64 DEF_HELPER_2(cmpxchg16b_unlocked, void, env, tl) DEF_HELPER_2(cmpxchg16b, void, env, tl) diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index e3cdafd2d4..814786bb87 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -27,63 +27,6 @@ #include "tcg/tcg.h" #include "helper-tcg.h" -void helper_cmpxchg8b_unlocked(CPUX86State *env, target_ulong a0) -{ - uintptr_t ra = GETPC(); - uint64_t oldv, cmpv, newv; - int eflags; - - eflags = cpu_cc_compute_all(env, CC_OP); - - cmpv = deposit64(env->regs[R_EAX], 32, 32, env->regs[R_EDX]); - newv = deposit64(env->regs[R_EBX], 32, 32, env->regs[R_ECX]); - - oldv = cpu_ldq_data_ra(env, a0, ra); - newv = (cmpv == oldv ? newv : oldv); - /* always do the store */ - cpu_stq_data_ra(env, a0, newv, ra); - - if (oldv == cmpv) { - eflags |= CC_Z; - } else { - env->regs[R_EAX] = (uint32_t)oldv; - env->regs[R_EDX] = (uint32_t)(oldv >> 32); - eflags &= ~CC_Z; - } - CC_SRC = eflags; -} - -void helper_cmpxchg8b(CPUX86State *env, target_ulong a0) -{ -#ifdef CONFIG_ATOMIC64 - uint64_t oldv, cmpv, newv; - int eflags; - - eflags = cpu_cc_compute_all(env, CC_OP); - - cmpv = deposit64(env->regs[R_EAX], 32, 32, env->regs[R_EDX]); - newv = deposit64(env->regs[R_EBX], 32, 32, env->regs[R_ECX]); - - { - uintptr_t ra = GETPC(); - int mem_idx = cpu_mmu_index(env, false); - MemOpIdx oi = make_memop_idx(MO_TEUQ, mem_idx); - oldv = cpu_atomic_cmpxchgq_le_mmu(env, a0, cmpv, newv, oi, ra); - } - - if (oldv == cmpv) { - eflags |= CC_Z; - } else { - env->regs[R_EAX] = (uint32_t)oldv; - env->regs[R_EDX] = (uint32_t)(oldv >> 32); - eflags &= ~CC_Z; - } - CC_SRC = eflags; -#else - cpu_loop_exit_atomic(env_cpu(env), GETPC()); -#endif /* CONFIG_ATOMIC64 */ -} - #ifdef TARGET_X86_64 void helper_cmpxchg16b_unlocked(CPUX86State *env, target_ulong a0) { diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index a82131d635..b542b084a6 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2995,15 +2995,59 @@ static void gen_sty_env_A0(DisasContext *s, int offset, bool align) static void gen_cmpxchg8b(DisasContext *s, CPUX86State *env, int modrm) { + TCGv_i64 cmp, val, old; + TCGv Z; + gen_lea_modrm(env, s, modrm); - if ((s->prefix & PREFIX_LOCK) && - (tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cmpxchg8b(cpu_env, s->A0); + cmp = tcg_temp_new_i64(); + val = tcg_temp_new_i64(); + old = tcg_temp_new_i64(); + + /* Construct the comparison values from the register pair. */ + tcg_gen_concat_tl_i64(cmp, cpu_regs[R_EAX], cpu_regs[R_EDX]); + tcg_gen_concat_tl_i64(val, cpu_regs[R_EBX], cpu_regs[R_ECX]); + + /* Only require atomic with LOCK; non-parallel handled in generator. */ + if (s->prefix & PREFIX_LOCK) { + tcg_gen_atomic_cmpxchg_i64(old, s->A0, cmp, val, s->mem_index, MO_TEUQ); } else { - gen_helper_cmpxchg8b_unlocked(cpu_env, s->A0); + tcg_gen_nonatomic_cmpxchg_i64(old, s->A0, cmp, val, + s->mem_index, MO_TEUQ); } - set_cc_op(s, CC_OP_EFLAGS); + tcg_temp_free_i64(val); + + /* Set tmp0 to match the required value of Z. */ + tcg_gen_setcond_i64(TCG_COND_EQ, cmp, old, cmp); + Z = tcg_temp_new(); + tcg_gen_trunc_i64_tl(Z, cmp); + tcg_temp_free_i64(cmp); + + /* + * Extract the result values for the register pair. + * For 32-bit, we may do this unconditionally, because on success (Z=1), + * the old value matches the previous value in EDX:EAX. For x86_64, + * the store must be conditional, because we must leave the source + * registers unchanged on success, and zero-extend the writeback + * on failure (Z=0). + */ + if (TARGET_LONG_BITS == 32) { + tcg_gen_extr_i64_tl(cpu_regs[R_EAX], cpu_regs[R_EDX], old); + } else { + TCGv zero = tcg_constant_tl(0); + + tcg_gen_extr_i64_tl(s->T0, s->T1, old); + tcg_gen_movcond_tl(TCG_COND_EQ, cpu_regs[R_EAX], Z, zero, + s->T0, cpu_regs[R_EAX]); + tcg_gen_movcond_tl(TCG_COND_EQ, cpu_regs[R_EDX], Z, zero, + s->T1, cpu_regs[R_EDX]); + } + tcg_temp_free_i64(old); + + /* Update Z. */ + gen_compute_eflags(s); + tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, Z, ctz32(CC_Z), 1); + tcg_temp_free(Z); } #ifdef TARGET_X86_64 -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:39:22 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELak-0006sK-Du for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:39:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELaT-0006bd-39 for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:39:09 -0500 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZP-0004Ur-Pi for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:39:04 -0500 Received: by mail-pj1-x1030.google.com with SMTP id z9-20020a17090a468900b00226b6e7aeeaso5837623pjf.1 for ; Sat, 07 Jan 2023 18:37:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9ScRTiCetY4GULFmLSkWpnFNmGzWjdbMDLDjsbqu5fo=; b=TOAXi5LNjIeY1nkvmNKr1LLyMMYFpHORFQuq1LndUTcqcW19FupH/WNFkTSqWN4rLE 4wt69j5xi2rQiFDqzem5zig+c29iLZJ3+RjDM4qc0pGvl0RBfz5lt/FgLanpFmqCMnVe PozALU5VBxd7h63o5rnKun4r2UJG/Wy2z0TlXW7JJRWi9wle9q9/gq05rab5xS7J1Gjw 93X6ifPoHPkeQy5TEZmmbUb3P0BufSHolivO079loX6zKFFFQM6E3Uvl4A4rLZ/DhVlz OJbGCtNekzyKOBmqHMtlCB+qWSqO+ZvqbLTVvFBXDigWzanuETn8rNH70KE30/ywiPds AbTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9ScRTiCetY4GULFmLSkWpnFNmGzWjdbMDLDjsbqu5fo=; b=CDodyj76pc5R6KzeJOyFZcQ5NF3e1iT5PfTavL/fRIsU7Rit8EoxC/eKDdb03QCeOn LrwVMl7tWObt7VL52W2CdaP6zThVoSoBoApcwxUvtNka9ncXboMRrE/igMbYKDW9YlBT OEUTMnMBUWZLswaOfTiMA4gwm4HPtm8iwNQ1rLykxMspthkWO63fXkrJG5lu386N1pd4 T3xdnZ+SwJB3HXjYjJf9kurgsKluLezeT3nhLfgKw3kKEis9jlV+PBpY3ZjwoDqL6uyV hwMdYEP90FMrvND2Km68jnL1IOddhPxDFv1G8F0BjocDWBGZpxSiuX23UrY1vEdaEl1t qQYA== X-Gm-Message-State: AFqh2kqhaNnK21PHhnTglu+gSeObQy3BUK1ANCHx5V8vKdJlGCCcbSDi OBfziGSeoTMjzp90Wo3wOPpqzg== X-Google-Smtp-Source: AMrXdXsffHGUNC1FPVOOyvPzoLG6DHbo1HOOC+3BkFPxIrPU8WfHrlZT9WG8uGe2vb/VQSUvC69/2w== X-Received: by 2002:a17:902:cf09:b0:191:3e64:a5ff with SMTP id i9-20020a170902cf0900b001913e64a5ffmr83605253plg.68.1673145479006; Sat, 07 Jan 2023 18:37:59 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.37.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:37:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 34/36] target/i386: Split out gen_cmpxchg8b, gen_cmpxchg16b Date: Sat, 7 Jan 2023 18:37:17 -0800 Message-Id: <20230108023719.2466341-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:39:11 -0000 Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 48 ++++++++++++++++++++++++------------- 1 file changed, 31 insertions(+), 17 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 7e0b2a709a..a82131d635 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2993,6 +2993,34 @@ static void gen_sty_env_A0(DisasContext *s, int offset, bool align) #include "emit.c.inc" #include "decode-new.c.inc" +static void gen_cmpxchg8b(DisasContext *s, CPUX86State *env, int modrm) +{ + gen_lea_modrm(env, s, modrm); + + if ((s->prefix & PREFIX_LOCK) && + (tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_helper_cmpxchg8b(cpu_env, s->A0); + } else { + gen_helper_cmpxchg8b_unlocked(cpu_env, s->A0); + } + set_cc_op(s, CC_OP_EFLAGS); +} + +#ifdef TARGET_X86_64 +static void gen_cmpxchg16b(DisasContext *s, CPUX86State *env, int modrm) +{ + gen_lea_modrm(env, s, modrm); + + if ((s->prefix & PREFIX_LOCK) && + (tb_cflags(s->base.tb) & CF_PARALLEL)) { + gen_helper_cmpxchg16b(cpu_env, s->A0); + } else { + gen_helper_cmpxchg16b_unlocked(cpu_env, s->A0); + } + set_cc_op(s, CC_OP_EFLAGS); +} +#endif + /* convert one instruction. s->base.is_jmp is set if the translation must be stopped. Return the next pc value */ static bool disas_insn(DisasContext *s, CPUState *cpu) @@ -3844,28 +3872,14 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (!(s->cpuid_ext_features & CPUID_EXT_CX16)) { goto illegal_op; } - gen_lea_modrm(env, s, modrm); - if ((s->prefix & PREFIX_LOCK) && - (tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cmpxchg16b(cpu_env, s->A0); - } else { - gen_helper_cmpxchg16b_unlocked(cpu_env, s->A0); - } - set_cc_op(s, CC_OP_EFLAGS); + gen_cmpxchg16b(s, env, modrm); break; } -#endif +#endif if (!(s->cpuid_features & CPUID_CX8)) { goto illegal_op; } - gen_lea_modrm(env, s, modrm); - if ((s->prefix & PREFIX_LOCK) && - (tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cmpxchg8b(cpu_env, s->A0); - } else { - gen_helper_cmpxchg8b_unlocked(cpu_env, s->A0); - } - set_cc_op(s, CC_OP_EFLAGS); + gen_cmpxchg8b(s, env, modrm); break; case 7: /* RDSEED */ -- 2.34.1 From MAILER-DAEMON Sat Jan 07 21:39:24 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pELal-0006xg-VX for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 21:39:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pELab-0006hu-0J for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:39:13 -0500 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pELZR-0004aN-Uz for qemu-riscv@nongnu.org; Sat, 07 Jan 2023 21:39:09 -0500 Received: by mail-pl1-x62c.google.com with SMTP id b2so5869800pld.7 for ; Sat, 07 Jan 2023 18:38:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Mhr3QIUQO1GxMkIggU7JbqoOmehoWj07MLx7q6K4qDk=; b=hYrKynyZZDUSofsJs+xXcMB7/0fMnugQQY67q1cmym7W3997wg5VycoQ2RkOmRpSZt QdSdaHQDlpuna7ZYoyiqCBVAfxxxttbloqn8SXWa9g8Q4BgJTRs5gmdyPwgbwLFtQesM uL5f2e49JZVqm3/o2RRsPLPyXWR0xKVL3uk1bk1vJFaxquAGmD36KprD3yZn/BkzLGU5 DtwkqDeAdyMQOZDO7lwqhG1GahbRhVh6B0LZ44P2eRiDWtmVEHDAfBZj3qRTSwxY0GYC olI4A6VwTXVt/n4SXwwwHhFHZ882snHmHDJP38qXKstVeLZEzweh96+KYL5Igdb7wd83 1a6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Mhr3QIUQO1GxMkIggU7JbqoOmehoWj07MLx7q6K4qDk=; b=VABYECmjtWdMYe52miDz9GFJNH6vaM8CtN5rpT0iftcEMwovLP6jmYFdD66P2wBUXE kV3hgptpEC7SIHioXpqtyXQH9W1hh2Rdlsk1KC63rsrfw/Rek9VTFz6z7OFIJ4Jp8W1y LSU4kMhCfl3nLDBn+HgI3aB0Yj8IY6zBotNaDepjVwLsPFaWTuvUarc4G+0Ar2hMHYIv nIMioI1ZRnId5zg00JnD0cZA7ypl3VjjlKhK4oXOuOMYKLoCygjABDDqlczuFpEgbIpz 4jyNTOKueWmzP7XuNctHIE2wkxlBc50M7lkj2RaBvFdU/AXVhwr4TbFDPyT1ZLKJMkzw qZ4Q== X-Gm-Message-State: AFqh2kruvStZTOYrX6lrG+2is/P7Go+87O9DjM8+kKB4RTf9OR/VX3zx 8hMSz+7txbyuRk2qc6gjyM7j8n59T8Tyxgkr X-Google-Smtp-Source: AMrXdXuTipe2JW3Lp97w1VhX2lUzlidEeI3sBYhB+s+uPaVq5nPRmTqf3B1ngjjIHB7MP7xL0SSVMA== X-Received: by 2002:a17:903:2312:b0:192:8c7f:2654 with SMTP id d18-20020a170903231200b001928c7f2654mr53462869plh.0.1673145481048; Sat, 07 Jan 2023 18:38:01 -0800 (PST) Received: from stoup.. ([2602:47:d48c:8101:8a2d:2011:f402:6f82]) by smtp.gmail.com with ESMTPSA id o17-20020a170902d4d100b00189d4c666c8sm3394775plg.153.2023.01.07.18.38.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 18:38:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net Subject: [PATCH v4 36/36] target/i386: Inline cmpxchg16b Date: Sat, 7 Jan 2023 18:37:19 -0800 Message-Id: <20230108023719.2466341-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> References: <20230108023719.2466341-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 02:39:14 -0000 Use tcg_gen_atomic_cmpxchg_i128 for the atomic case, and tcg_gen_qemu_ld/st_i128 otherwise. Signed-off-by: Richard Henderson --- target/i386/helper.h | 4 --- target/i386/tcg/mem_helper.c | 69 ------------------------------------ target/i386/tcg/translate.c | 44 ++++++++++++++++++++--- 3 files changed, 39 insertions(+), 78 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index 2df8049f91..e627a93107 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -66,10 +66,6 @@ DEF_HELPER_1(rsm, void, env) #endif /* !CONFIG_USER_ONLY */ DEF_HELPER_2(into, void, env, int) -#ifdef TARGET_X86_64 -DEF_HELPER_2(cmpxchg16b_unlocked, void, env, tl) -DEF_HELPER_2(cmpxchg16b, void, env, tl) -#endif DEF_HELPER_FLAGS_1(single_step, TCG_CALL_NO_WG, noreturn, env) DEF_HELPER_1(rechecking_single_step, void, env) DEF_HELPER_1(cpuid, void, env) diff --git a/target/i386/tcg/mem_helper.c b/target/i386/tcg/mem_helper.c index 814786bb87..3ef84e90d9 100644 --- a/target/i386/tcg/mem_helper.c +++ b/target/i386/tcg/mem_helper.c @@ -27,75 +27,6 @@ #include "tcg/tcg.h" #include "helper-tcg.h" -#ifdef TARGET_X86_64 -void helper_cmpxchg16b_unlocked(CPUX86State *env, target_ulong a0) -{ - uintptr_t ra = GETPC(); - Int128 oldv, cmpv, newv; - uint64_t o0, o1; - int eflags; - bool success; - - if ((a0 & 0xf) != 0) { - raise_exception_ra(env, EXCP0D_GPF, GETPC()); - } - eflags = cpu_cc_compute_all(env, CC_OP); - - cmpv = int128_make128(env->regs[R_EAX], env->regs[R_EDX]); - newv = int128_make128(env->regs[R_EBX], env->regs[R_ECX]); - - o0 = cpu_ldq_data_ra(env, a0 + 0, ra); - o1 = cpu_ldq_data_ra(env, a0 + 8, ra); - - oldv = int128_make128(o0, o1); - success = int128_eq(oldv, cmpv); - if (!success) { - newv = oldv; - } - - cpu_stq_data_ra(env, a0 + 0, int128_getlo(newv), ra); - cpu_stq_data_ra(env, a0 + 8, int128_gethi(newv), ra); - - if (success) { - eflags |= CC_Z; - } else { - env->regs[R_EAX] = int128_getlo(oldv); - env->regs[R_EDX] = int128_gethi(oldv); - eflags &= ~CC_Z; - } - CC_SRC = eflags; -} - -void helper_cmpxchg16b(CPUX86State *env, target_ulong a0) -{ - uintptr_t ra = GETPC(); - - if ((a0 & 0xf) != 0) { - raise_exception_ra(env, EXCP0D_GPF, ra); - } else if (HAVE_CMPXCHG128) { - int eflags = cpu_cc_compute_all(env, CC_OP); - - Int128 cmpv = int128_make128(env->regs[R_EAX], env->regs[R_EDX]); - Int128 newv = int128_make128(env->regs[R_EBX], env->regs[R_ECX]); - - int mem_idx = cpu_mmu_index(env, false); - MemOpIdx oi = make_memop_idx(MO_TE | MO_128 | MO_ALIGN, mem_idx); - Int128 oldv = cpu_atomic_cmpxchgo_le_mmu(env, a0, cmpv, newv, oi, ra); - - if (int128_eq(oldv, cmpv)) { - eflags |= CC_Z; - } else { - env->regs[R_EAX] = int128_getlo(oldv); - env->regs[R_EDX] = int128_gethi(oldv); - eflags &= ~CC_Z; - } - CC_SRC = eflags; - } else { - cpu_loop_exit_atomic(env_cpu(env), ra); - } -} -#endif - void helper_boundw(CPUX86State *env, target_ulong a0, int v) { int low, high; diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index b542b084a6..9d9392b009 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -3053,15 +3053,49 @@ static void gen_cmpxchg8b(DisasContext *s, CPUX86State *env, int modrm) #ifdef TARGET_X86_64 static void gen_cmpxchg16b(DisasContext *s, CPUX86State *env, int modrm) { + MemOp mop = MO_TE | MO_128 | MO_ALIGN; + TCGv_i64 t0, t1; + TCGv_i128 cmp, val; + gen_lea_modrm(env, s, modrm); - if ((s->prefix & PREFIX_LOCK) && - (tb_cflags(s->base.tb) & CF_PARALLEL)) { - gen_helper_cmpxchg16b(cpu_env, s->A0); + cmp = tcg_temp_new_i128(); + val = tcg_temp_new_i128(); + tcg_gen_concat_i64_i128(cmp, cpu_regs[R_EAX], cpu_regs[R_EDX]); + tcg_gen_concat_i64_i128(val, cpu_regs[R_EBX], cpu_regs[R_ECX]); + + /* Only require atomic with LOCK; non-parallel handled in generator. */ + if (s->prefix & PREFIX_LOCK) { + tcg_gen_atomic_cmpxchg_i128(val, s->A0, cmp, val, s->mem_index, mop); } else { - gen_helper_cmpxchg16b_unlocked(cpu_env, s->A0); + tcg_gen_nonatomic_cmpxchg_i128(val, s->A0, cmp, val, s->mem_index, mop); } - set_cc_op(s, CC_OP_EFLAGS); + + tcg_gen_extr_i128_i64(s->T0, s->T1, val); + tcg_temp_free_i128(cmp); + tcg_temp_free_i128(val); + + /* Determine success after the fact. */ + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + tcg_gen_xor_i64(t0, s->T0, cpu_regs[R_EAX]); + tcg_gen_xor_i64(t1, s->T1, cpu_regs[R_EDX]); + tcg_gen_or_i64(t0, t0, t1); + tcg_temp_free_i64(t1); + + /* Update Z. */ + gen_compute_eflags(s); + tcg_gen_setcondi_i64(TCG_COND_EQ, t0, t0, 0); + tcg_gen_deposit_tl(cpu_cc_src, cpu_cc_src, t0, ctz32(CC_Z), 1); + tcg_temp_free_i64(t0); + + /* + * Extract the result values for the register pair. We may do this + * unconditionally, because on success (Z=1), the old value matches + * the previous value in RDX:RAX. + */ + tcg_gen_mov_i64(cpu_regs[R_EAX], s->T0); + tcg_gen_mov_i64(cpu_regs[R_EDX], s->T1); } #endif -- 2.34.1 From MAILER-DAEMON Sat Jan 07 22:30:44 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pEMOR-0000tM-U9 for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 22:30:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEMOQ-0000sm-2F; Sat, 07 Jan 2023 22:30:42 -0500 Received: from mail-ed1-x530.google.com ([2a00:1450:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEMOJ-0002Qv-WF; Sat, 07 Jan 2023 22:30:41 -0500 Received: by mail-ed1-x530.google.com with SMTP id z11so7719625ede.1; Sat, 07 Jan 2023 19:30:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=RMYQVCrCY7oa8m6P8HZtqr54QkW0vIb4olvZBCakXRA=; b=SKh47xUqM/rFbv54PD2/Wwb/bMo1kTXdjlz6ibpNRX/5hyGhgAnrbXqZEstwmejDYD Vg4gcJ/fzUwjgj3TZmpdtSxzzPXnh+CCvkmpoyE7tSxOUh5YRjLHn9pSeIDP0ApfsdfI rlpS0z746aC/xuqzDzHG67rukTG8Gt5rYnvECf/AUQVMki6gI/5o+zDLNpUH+42a8gNT IfMlEjvhMIdF74BrZz0W24lL2JBIdKxIx1nWW1qz9jiLiM8qpF/kjr8Z7VoKLFIOv/V2 giy3BgBAkDCTBNLIjHSNrM8prjlj+0s8R7dsPq2WB1hL51wlzsQwK2VwkLU5aR/wX+OV /kxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RMYQVCrCY7oa8m6P8HZtqr54QkW0vIb4olvZBCakXRA=; b=qeULvcdRWQyQZu/RbvF0neleFqJ4Xjrytq+1shj4aFlqoGyUOkydUPqzQH1tbAFdY+ 1UDNQn4sIPwAft2pqlJDswIKxgMryWZKkCqUrq3McUSRDb4/ubrKMOnQeXOCaBwFhX0p 42afi0tTjsur9F4Hb9GqhmFZK3J+q7hIihUM1GdJbUVhmKOSKK34ifKfiIYmsNkfdIBt SD+R+DhrsXPTCzEPuJ5nXmBbbpnCSfC5BJI5wvqzafw8SwluXH2W89jDu9RiAdLSwMRj MSQ9q9m4izYuI8qOQNPwQD59wakUoXfPpXj531euXoB84Bz3ofMqdMYNPbijAenuGIpC LUgA== X-Gm-Message-State: AFqh2kp/eOSvTm7IUJ/b3QhAuxfQ60k8+QVyHdknI++9idRKUUtVY7j7 jN7AeA9fqDyqoE7Zbg3kCD2a38pJfOFisIt7NPA= X-Google-Smtp-Source: AMrXdXuB5E0XjfuCvocCQPtVFZ7wvL3Mz48aVqw5V20qC/sd0v6w2r537JGUoUBsiWcTaGAdsOUH5xTDhZn6MpyZQks= X-Received: by 2002:aa7:d80f:0:b0:499:dfa:1c6b with SMTP id v15-20020aa7d80f000000b004990dfa1c6bmr249675edq.202.1673148633826; Sat, 07 Jan 2023 19:30:33 -0800 (PST) MIME-Version: 1.0 References: <20230102115241.25733-1-dbarboza@ventanamicro.com> <20230102115241.25733-5-dbarboza@ventanamicro.com> In-Reply-To: <20230102115241.25733-5-dbarboza@ventanamicro.com> From: Bin Meng Date: Sun, 8 Jan 2023 11:30:23 +0800 Message-ID: Subject: Re: [PATCH v5 04/11] hw/riscv/boot.c: exit early if filename is NULL in load functions To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng , =?UTF-8?B?QWxleCBCZW5uw6ll?= , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=bmeng.cn@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 03:30:42 -0000 On Mon, Jan 2, 2023 at 7:54 PM Daniel Henrique Barboza wrote: > > riscv_load_firmware(), riscv_load_initrd() and riscv_load_kernel() works > under the assumption that a 'filename' parameter is always not NULL. > > This is currently the case since all callers of these functions are > checking for NULL before calling them. Add an g_assert() to make sure > that a NULL value in these cases are to be considered a bug. > > Suggested-by: Alex Benn=C3=A9e > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/boot.c | 6 ++++++ > 1 file changed, 6 insertions(+) > Reviewed-by: Bin Meng From MAILER-DAEMON Sat Jan 07 22:34:02 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pEMRe-0001mZ-OT for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 22:34:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEMRd-0001mF-6O; Sat, 07 Jan 2023 22:34:01 -0500 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEMRZ-0002rn-Vk; Sat, 07 Jan 2023 22:34:00 -0500 Received: by mail-ed1-x52b.google.com with SMTP id j16so7662986edw.11; Sat, 07 Jan 2023 19:33:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=o1oFPtFyKAhBTQvfqqjrhngFuAaO5XhD7x1bAFZHIvA=; b=kkPiViqBmsu+MI4GavyzoQkOqiFqbFX0+2ZS1XUYIJ5hSCMl3e3ybGkCWOLyT6+BqZ Cd8ztN/LRUj1XyKlitYF+dMFJrzYft1kXLaNTviWx8qyc/INFYsn+RLVxCsQHlPE/gIr wwQMcyCSRVr4v0+pGUGf0r6WilulzPaNAqjkxASo7VfRPyGrnpx6B+EWAafC6xRBlv7o 7JWeUHSGIHWHrLbPreNqEQ7owxz4gWqzT0Q7lkWAHf5lsRa2gAQOqrUOGkReChYdpmMD FlCQ8uollYWah8w82X6lruN7aqnD04mDNu/A3XT7lKCBd3+E0mNfkxNRR23QjR8VOsRk acug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=o1oFPtFyKAhBTQvfqqjrhngFuAaO5XhD7x1bAFZHIvA=; b=NMIsjGnPZK4wqLps93acuVynTouLI+4s49h/M29ZSsGHfcdGO0fUrza8G6NFdq/eA4 kMUUe+/QDFsN6yoTCzXaKv2BcHYq4XfCse7WRiLy9zGsWu1w1rASnGFPmMlKJyxSCaZN tf7BcemXF/johQPsYVjI0+Yj43ikjGXyZbaCIyJd2BpQXnt8RKIhiFq6hsiBU7805lSy lJWdqzbOE4NJAusi57/inf/UejFF8RWsQIgObnqe5GNuuWPNS8KfOHRYZgpF08VdWBaC 5KbC0i5zp3D4Ri0d8BMbZdjBK22IzNTz6BItNW4wbn05vMUv90AXNjlfq5VsBO+0yNVr a0Og== X-Gm-Message-State: AFqh2kpg4GUVWNEaVOf0qihsxCU3J4wZVx+gdQ6UNGHyVkKFRZSW9QOy Mh5BoAvgUi5F2s2Hmn4v8q8UgpthqSKW1ZRRtWc= X-Google-Smtp-Source: AMrXdXuZZRgJzFtnPdMLWSOHzaIMZqdw119+dYyiegh2J8R6bD7NxAkIU3LBEqDwVKXrTaUwOutqe52D2y6Wuzo7lOE= X-Received: by 2002:a05:6402:1843:b0:46b:1d60:f60a with SMTP id v3-20020a056402184300b0046b1d60f60amr6810212edy.193.1673148836232; Sat, 07 Jan 2023 19:33:56 -0800 (PST) MIME-Version: 1.0 References: <20230102115241.25733-1-dbarboza@ventanamicro.com> <20230102115241.25733-11-dbarboza@ventanamicro.com> In-Reply-To: <20230102115241.25733-11-dbarboza@ventanamicro.com> From: Bin Meng Date: Sun, 8 Jan 2023 11:33:46 +0800 Message-ID: Subject: Re: [PATCH v5 10/11] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng , Palmer Dabbelt Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=bmeng.cn@gmail.com; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 03:34:01 -0000 On Mon, Jan 2, 2023 at 7:55 PM Daniel Henrique Barboza wrote: > > The microchip_icicle_kit, sifive_u, spike and virt boards are now doing > the same steps when '-kernel' is used: > > - execute load_kernel() > - load init_rd() > - write kernel_cmdline > > Let's fold everything inside riscv_load_kernel() to avoid code > repetition. To not change the behavior of boards that aren't calling > riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and typo: should be riscv_load_initrd() > allow these boards to opt out from initrd loading. > > Cc: Palmer Dabbelt > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/boot.c | 22 +++++++++++++++++++--- > hw/riscv/microchip_pfsoc.c | 12 ++---------- > hw/riscv/opentitan.c | 2 +- > hw/riscv/sifive_e.c | 3 ++- > hw/riscv/sifive_u.c | 12 ++---------- > hw/riscv/spike.c | 11 +---------- > hw/riscv/virt.c | 12 ++---------- > include/hw/riscv/boot.h | 1 + > 8 files changed, 30 insertions(+), 45 deletions(-) > Otherwise, Reviewed-by: Bin Meng From MAILER-DAEMON Sat Jan 07 22:52:25 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pEMjR-0004La-Hq for mharc-qemu-riscv@gnu.org; Sat, 07 Jan 2023 22:52:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEMjQ-0004LH-1z; Sat, 07 Jan 2023 22:52:24 -0500 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEMjN-0008Lc-Kn; Sat, 07 Jan 2023 22:52:23 -0500 Received: by mail-ej1-x62e.google.com with SMTP id hw16so370330ejc.10; Sat, 07 Jan 2023 19:52:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=I5sNx7TX9ACxlUPDc7jdGO70mReEt4uLX6fgAA91hvo=; b=WAjYiIAgEsaR6ngiji5aTm2R+ImB6tOiclrRhCx2ZaKZutkfgDqPFgY5s/iM8+3RYs sJweG9FK5dx9J55rmGGIKIJyFC7KnKqw04INnq77oUkYpZwwy8YKtWb8ODaq9DygNsdB T1QZcm4zdE/NKJDZjcXAcQrMW6qdC1KLKVa1uke/1Sl2p+YgaLNl/azp0/A1w/fouF0n gcDIwidAUTheyfEtv79GbVdBe8zYXYvBTYZC5KtmFLsIYab8wxCoAKsJQn5S8RJli+U3 jlwu+Y0KGVz90cYOhGOtn4GPTpgw9w1xAnBbqcYidzeiEGB9bGL6hYLcrKFD0RffrBc0 /UtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=I5sNx7TX9ACxlUPDc7jdGO70mReEt4uLX6fgAA91hvo=; b=JkYncS+bnfZf+wD1+ohHDgQSPgDCl/HT+boBLZzvINbWGzHL55fWYiLSLPxwT/2KtT FjQQqTSSjfNAUZHYQdvrJ8en2PXBcemGQK4X4O/U6N9D8il3Amts7FswaIhesFLC9U9L aNjEfldvG8F7ewDj5ezLLRWXAR9rkxMOmcNYdVbJQFVpH1hmGFlxoZW6CQ+3CBNBKDfB oi/LzXnADtKRn3JzUZSTx1u5g+gW5+HJ6haax1oWeIVFm2PYKIDWYl5VrZ/4Zfvis+xM qsitCRKpx4rFiZjdfSjZWRyvZ9GGJN+p7zNLHmldShKpmCgZWEAwUI6y2LPjJ1eOijUr tgKA== X-Gm-Message-State: AFqh2koMumB/NxTODtoqG0cDhz1tTlun24IfluhyQkwDT+CwUlt+rV0b f2EMemUdmtVegJ2dLKyN9K12f1qhbTuN6sfoSq0= X-Google-Smtp-Source: AMrXdXtJbMJ1ZvY6xP5s+/qq59gTpJD7SW3yOPrRjOmb41XDe+EkwYXtj6Mm7PMOY9PCw1v5OtBD/qNQfKxsBtXVlDw= X-Received: by 2002:a17:907:7782:b0:7c0:e380:3d44 with SMTP id ky2-20020a170907778200b007c0e3803d44mr5195971ejc.498.1673149939578; Sat, 07 Jan 2023 19:52:19 -0800 (PST) MIME-Version: 1.0 References: <20221229172734.119600-1-abdulras@google.com> In-Reply-To: <20221229172734.119600-1-abdulras@google.com> From: Bin Meng Date: Sun, 8 Jan 2023 11:52:08 +0800 Message-ID: Subject: Re: [PATCH] riscv: do not set the rounding mode via `gen_set_rm` To: Saleem Abdulrasool Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, frank.chang@sifive.com, Saleem Abdulrasool Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 03:52:24 -0000 On Fri, Dec 30, 2022 at 2:20 AM Saleem Abdulrasool wrote: > > From: Saleem Abdulrasool > > Setting the rounding mode via the `gen_set_rm` call would alter the > state of the disassembler, resetting the `TransOp` in the assembler > context. When we subsequently set the rounding mode to the desired > value, we would trigger an assertion in `decode_save_opc`. Instead > we can set the rounding mode via the `gen_helper_set_rounding_mode` > which will still trigger the exception in the case of an invalid RM > without altering the CPU disassembler state. > > Signed-off-by: Saleem Abdulrasool > --- > target/riscv/insn_trans/trans_rvv.c.inc | 69 +++++++++++++------------ > 1 file changed, 36 insertions(+), 33 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index 4dea4413ae..73f6fab1c5 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -2679,8 +2679,10 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, > int rm) > { > if (checkfn(s, a)) { > + // the helper will raise an exception if the rounding mode is invalid nits: use /* */ > if (rm != RISCV_FRM_DYN) { > - gen_set_rm(s, RISCV_FRM_DYN); > + gen_helper_set_rounding_mode(cpu_env, > + tcg_constant_i32(RISCV_FRM_DYN)); > } > > uint32_t data = 0; > @@ -3001,38 +3003,39 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) > require_scale_zve64f(s); > } > > -#define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \ > -static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ > -{ \ > - if (CHECK(s, a)) { \ > - if (FRM != RISCV_FRM_DYN) { \ > - gen_set_rm(s, RISCV_FRM_DYN); \ > - } \ > - \ > - uint32_t data = 0; \ > - static gen_helper_gvec_3_ptr * const fns[2] = { \ > - gen_helper_##HELPER##_h, \ > - gen_helper_##HELPER##_w, \ > - }; \ > - TCGLabel *over = gen_new_label(); \ > - gen_set_rm(s, FRM); \ > - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ > - tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ > - \ > - data = FIELD_DP32(data, VDATA, VM, a->vm); \ > - data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ > - data = FIELD_DP32(data, VDATA, VTA, s->vta); \ > - data = FIELD_DP32(data, VDATA, VMA, s->vma); \ > - tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ > - vreg_ofs(s, a->rs2), cpu_env, \ > - s->cfg_ptr->vlen / 8, \ > - s->cfg_ptr->vlen / 8, data, \ > - fns[s->sew - 1]); \ > - mark_vs_dirty(s); \ > - gen_set_label(over); \ > - return true; \ > - } \ > - return false; \ > +#define GEN_OPFV_NARROW_TRANS(NAME, CHECK, HELPER, FRM) \ > +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ > +{ \ > + if (CHECK(s, a)) { \ > + if (FRM != RISCV_FRM_DYN) { \ > + gen_helper_set_rounding_mode(cpu_env, \ > + tcg_constant_i32(RISCV_FRM_DYN)); \ > + } \ > + \ > + uint32_t data = 0; \ > + static gen_helper_gvec_3_ptr * const fns[2] = { \ > + gen_helper_##HELPER##_h, \ > + gen_helper_##HELPER##_w, \ > + }; \ > + TCGLabel *over = gen_new_label(); \ > + gen_set_rm(s, FRM); \ > + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ > + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ > + \ > + data = FIELD_DP32(data, VDATA, VM, a->vm); \ > + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ > + data = FIELD_DP32(data, VDATA, VTA, s->vta); \ > + data = FIELD_DP32(data, VDATA, VMA, s->vma); \ > + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ > + vreg_ofs(s, a->rs2), cpu_env, \ > + s->cfg_ptr->vlen / 8, \ > + s->cfg_ptr->vlen / 8, data, \ > + fns[s->sew - 1]); \ > + mark_vs_dirty(s); \ > + gen_set_label(over); \ > + return true; \ > + } \ > + return false; \ > } > > GEN_OPFV_NARROW_TRANS(vfncvt_f_xu_w, opfxv_narrow_check, vfncvt_f_xu_w, > -- Is it possible to create a test case (tests/tcg/riscv64) for this? Regards, Bin From MAILER-DAEMON Sun Jan 08 00:36:06 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pEOLl-000606-E9 for mharc-qemu-riscv@gnu.org; Sun, 08 Jan 2023 00:36:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEOLi-0005z6-AR; Sun, 08 Jan 2023 00:36:02 -0500 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEOLf-0003cw-Nf; Sun, 08 Jan 2023 00:36:00 -0500 Received: by mail-ej1-x631.google.com with SMTP id tz12so12513569ejc.9; Sat, 07 Jan 2023 21:35:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=3xZ6SKNWfaZZc73rws7zd+R9khWnHie2ztD0YJo19aM=; b=PbydBjvaPNjDouLoJY++EIqxe5K5hVeiwi58ozDvoLyMoaARAg/v8x+YVCGipGs7m+ jvfGlP0E8VgVGl+EWnkDmHELtvGeDhh0i5TDIY+snrGlsk54ITxhE34VLneVwysPut1I YFc8dsHL3Pdm/nxNh+VK82eHbWDyKz59OzbCWG9353yiuzeVy3St2LyTlKghAztoDEoY X4iSdg082JQc/nOjvXF027SFZie09cIaBDKjIVxJBeG1v3HKlKlXSY62WNwCu2Q9xlDY cdibVwEZ3KvTDvBC/ydKbraiwXU+PCcxwPWbR5o4ZjfBStvMwePveoKjQms95LurxqU3 pL0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3xZ6SKNWfaZZc73rws7zd+R9khWnHie2ztD0YJo19aM=; b=WD9cJ+xAH/keTGFW3tJaMmAVix4T3DniH3HCr9ZJo2Vn6FaNQKYCdUZ3NNqqV8X3x6 0GPSBVaFmD8e37MaTQf5CHRrycymIvLfBk8/CG8q2j60J620ue1RgkGZ7KeI3us/Cp/4 htuQaxqmpIDF66CkE9cDeoxcCiJapaNPxcGwSTu5zk3rO6D5tGeOEGz7zyn8KjOQcMdY 03h9pppI8Ar0hBfCeGmp8XIRlo8ADNUs12axlaHb1r8YFVbM+6cdTPzhpW64yq+PZvnM 9lCs8TbBwTzm8m/xXzs7SaWzKjfeWhw6Stpbij2a1/U0/Wrq/QWyR/ijaqnogr5yDoaj cTIw== X-Gm-Message-State: AFqh2kqwn5Y/OZlrw06vbS35U5VFTcUcadr+DnTwL11/1hNBiXKG+xS5 FWazS/tVWHRQvUx8Qc4e4y7Vc2M5YidBiVAZf1s= X-Google-Smtp-Source: AMrXdXuN59YN8PLpBjvyhZGCySTz+QTPqhYQQM2eprKf2vxjz8/EkpWcEWGZCLRdCNDtSKi2jli9yUFwnXs5OKERMKQ= X-Received: by 2002:a17:907:6d29:b0:84d:ed8:b9df with SMTP id sa41-20020a1709076d2900b0084d0ed8b9dfmr1154874ejc.26.1673156157041; Sat, 07 Jan 2023 21:35:57 -0800 (PST) MIME-Version: 1.0 References: <20230104220449.41337-1-philmd@linaro.org> <20230104220449.41337-11-philmd@linaro.org> In-Reply-To: <20230104220449.41337-11-philmd@linaro.org> From: Bin Meng Date: Sun, 8 Jan 2023 13:35:46 +0800 Message-ID: Subject: Re: [PATCH 10/20] hw/arm: Open-code pflash_cfi01_register() To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: qemu-devel@nongnu.org, Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , Peter Maydell , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 05:36:03 -0000 On Thu, Jan 5, 2023 at 6:43 AM Philippe Mathieu-Daud=C3=A9 wrote: > > pflash_cfi01_register() hides an implicit sysbus mapping of > MMIO region #0. This is not practical in a heterogeneous world > where multiple cores use different address spaces. In order to > remove to remove pflash_cfi01_register() from the pflash API, duplicated "to remove" > open-code it as a qdev creation call followed by an explicit > sysbus mapping. > > Signed-off-by: Philippe Mathieu-Daud=C3=A9 > --- > hw/arm/collie.c | 15 +++++++++------ > hw/arm/gumstix.c | 19 +++++++++++++------ > hw/arm/mainstone.c | 13 ++++++++----- > hw/arm/omap_sx1.c | 22 ++++++++++++++-------- > hw/arm/versatilepb.c | 13 ++++++++----- > hw/arm/z2.c | 10 +++++++--- > 6 files changed, 59 insertions(+), 33 deletions(-) > Otherwise, Reviewed-by: Bin Meng From MAILER-DAEMON Sun Jan 08 01:49:55 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pEPVD-0001sN-OE for mharc-qemu-riscv@gnu.org; Sun, 08 Jan 2023 01:49:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEPVC-0001ro-I1 for qemu-riscv@nongnu.org; Sun, 08 Jan 2023 01:49:54 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEPVA-0003Jb-9t for qemu-riscv@nongnu.org; Sun, 08 Jan 2023 01:49:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1673160590; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=qNGDwUtYWMQMmQOpmqEBoEHP4xA1cItNiHsnSACei78=; b=e67Ej8yG10IBfqjdPDxAyYZcNaGrgbyUBn1+wQOcwfFXKEYHh65u6nsVMpDzpsqJ07RRQH 1N2b4gbvhtYvCfLT8DmbeEwIdtIKoJOj/XUq+8vOGP+G4NOtxacvbzGtKeVXGb2ryGvTmS YSfWEuZ3+1UbBmw27JV6l5cS+sPfsuc= Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-634-v5uXAmgGPra0pfv8uHMgNA-1; Sun, 08 Jan 2023 01:49:48 -0500 X-MC-Unique: v5uXAmgGPra0pfv8uHMgNA-1 Received: by mail-wr1-f72.google.com with SMTP id l18-20020adfa392000000b002bbd5c680a3so201631wrb.14 for ; Sat, 07 Jan 2023 22:49:48 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=qNGDwUtYWMQMmQOpmqEBoEHP4xA1cItNiHsnSACei78=; b=Fd8msvUqn9YgeEltDmd0a3v0ym3+mmUXrCU2tHm8uGHqDC6xGuDwjm/R3SDKWlePz+ Qt/CKH781+q5qfOx3ohLWRS8LLunHQPKyZtQz/9tdlhBsx6t1kVVHHDaVbhTDma+oO5L 9iYOczINmn4OJHoOlJr77HOBJjZFDosdfnrwoSaIaNmDct2eEKpj5KPbM3BzXuwHojCd JPN4vYmNzbuJQ3O5b41WeXDei5NIi+AnPYCggQVbvp4UxtzAatmUeCiR8ftOQzhkBBsa pcVKhuYwG7kzgjjtThLSfQgF2PmL5BYvVXTVktUFB1/Jrs+RTxst11fW7KW90QGNcuEE Ew/Q== X-Gm-Message-State: AFqh2kpul+VsxsXx6v0UTfU0zhoftuoTjIEsprrJYKcUzgcQZkT9qDap T+ivYiKOGmCOqo6wUmIBVOA7LXbgZW3USR+N+yliLBh/Typ4tRp+lzBEB3T+sof2sZSnj/s5mJT uKLTJDq2HDDIacDg= X-Received: by 2002:a05:600c:4e4f:b0:3cf:9d32:db67 with SMTP id e15-20020a05600c4e4f00b003cf9d32db67mr42761804wmq.3.1673160587265; Sat, 07 Jan 2023 22:49:47 -0800 (PST) X-Google-Smtp-Source: AMrXdXuIUYnVUO1jrkS42MSlDmqtbYjJf7wC+ahppzvv26T0eiHn/CICQD+ZHV6RArpTllYupDf8lA== X-Received: by 2002:a05:600c:4e4f:b0:3cf:9d32:db67 with SMTP id e15-20020a05600c4e4f00b003cf9d32db67mr42761774wmq.3.1673160587001; Sat, 07 Jan 2023 22:49:47 -0800 (PST) Received: from redhat.com ([2.52.141.223]) by smtp.gmail.com with ESMTPSA id o9-20020a05600c510900b003c6f8d30e40sm13207546wms.31.2023.01.07.22.49.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Jan 2023 22:49:46 -0800 (PST) Date: Sun, 8 Jan 2023 01:49:41 -0500 From: "Michael S. Tsirkin" To: Markus Armbruster Cc: qemu-devel@nongnu.org, imammedo@redhat.com, ani@anisinha.ca, peter.maydell@linaro.org, laurent@vivier.eu, edgar.iglesias@gmail.com, Alistair.Francis@wdc.com, bin.meng@windriver.com, palmer@dabbelt.com, marcel.apfelbaum@gmail.com, yangxiaojuan@loongson.cn, gaosong@loongson.cn, richard.henderson@linaro.org, deller@gmx.de, jasowang@redhat.com, vikram.garhwal@amd.com, francisco.iglesias@amd.com, clg@kaod.org, kraxel@redhat.com, marcandre.lureau@redhat.com, riku.voipio@iki.fi, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, crwulff@gmail.com, marex@denx.de Subject: Re: [PATCH v2 0/4] Clean up includes Message-ID: <20230108014842-mutt-send-email-mst@kernel.org> References: <20221222120813.727830-1-armbru@redhat.com> MIME-Version: 1.0 In-Reply-To: <20221222120813.727830-1-armbru@redhat.com> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 06:49:54 -0000 On Thu, Dec 22, 2022 at 01:08:09PM +0100, Markus Armbruster wrote: > Back in 2016, we discussed[1] rules for headers, and these were > generally liked: > > 1. Have a carefully curated header that's included everywhere first. We > got that already thanks to Peter: osdep.h. > > 2. Headers should normally include everything they need beyond osdep.h. > If exceptions are needed for some reason, they must be documented in > the header. If all that's needed from a header is typedefs, put > those into qemu/typedefs.h instead of including the header. > > 3. Cyclic inclusion is forbidden. > > This series fixes a number of rule violations. I had to drop this for now due to failures on bsd in particular. See Peter's answer to my pull. Markus when you merge this feel free to use: Reviewed-by: Michael S. Tsirkin > It is based on > > [PATCH v2 0/4] hw/ppc: Clean up includes > [PATCH v2 0/7] include/hw/pci include/hw/cxl: Clean up includes > [PATCH v2 0/3] block: Clean up includes > [PATCH v3 0/5] coroutine: Clean up includes > > With all of these applied, just three inclusion loops remain reachable > from include/: > > target/microblaze/cpu.h target/microblaze/mmu.h > > target/nios2/cpu.h target/nios2/mmu.h > > target/riscv/cpu.h target/riscv/pmp.h > > Breaking them would be nice, but I'm out of steam. > > v2: > * Rebased > * PATCH 3: v1 posted separately > * PATCH 4: New > > [1] Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org> > https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html > > Based-on: <20221222104628.659681-1-armbru@redhat.com> > > Markus Armbruster (4): > include/hw/virtio: Break inclusion loop > include: Include headers where needed > include: Don't include qemu/osdep.h > docs/devel: Rules on #include in headers > > docs/devel/style.rst | 7 +++++++ > bsd-user/qemu.h | 1 - > crypto/block-luks-priv.h | 1 - > include/exec/plugin-gen.h | 1 + > include/hw/acpi/erst.h | 3 +++ > include/hw/char/cmsdk-apb-uart.h | 1 + > include/hw/char/goldfish_tty.h | 1 + > include/hw/char/xilinx_uartlite.h | 1 + > include/hw/cris/etraxfs.h | 1 + > include/hw/cxl/cxl_host.h | 1 - > include/hw/display/macfb.h | 3 ++- > include/hw/dma/sifive_pdma.h | 2 ++ > include/hw/i386/ioapic_internal.h | 1 + > include/hw/i386/sgx-epc.h | 1 + > include/hw/input/pl050.h | 1 - > include/hw/intc/goldfish_pic.h | 2 ++ > include/hw/intc/loongarch_pch_msi.h | 2 ++ > include/hw/intc/loongarch_pch_pic.h | 2 ++ > include/hw/intc/nios2_vic.h | 2 ++ > include/hw/misc/mchp_pfsoc_dmc.h | 2 ++ > include/hw/misc/mchp_pfsoc_ioscb.h | 2 ++ > include/hw/misc/mchp_pfsoc_sysreg.h | 2 ++ > include/hw/misc/pvpanic.h | 1 + > include/hw/misc/sifive_e_prci.h | 3 ++- > include/hw/misc/sifive_u_otp.h | 3 ++- > include/hw/misc/sifive_u_prci.h | 3 ++- > include/hw/misc/virt_ctrl.h | 2 ++ > include/hw/misc/xlnx-versal-pmc-iou-slcr.h | 1 + > include/hw/net/lasi_82596.h | 2 +- > include/hw/net/xlnx-zynqmp-can.h | 1 + > include/hw/ppc/pnv_psi.h | 2 +- > include/hw/riscv/boot_opensbi.h | 2 ++ > include/hw/riscv/microchip_pfsoc.h | 3 +++ > include/hw/riscv/numa.h | 1 + > include/hw/riscv/sifive_u.h | 2 ++ > include/hw/riscv/spike.h | 2 +- > include/hw/riscv/virt.h | 2 +- > include/hw/ssi/sifive_spi.h | 3 +++ > include/hw/timer/sse-timer.h | 1 + > include/hw/tricore/triboard.h | 1 - > include/hw/usb/hcd-dwc3.h | 1 + > include/hw/usb/hcd-musb.h | 2 ++ > include/hw/usb/xlnx-usb-subsystem.h | 2 ++ > include/hw/usb/xlnx-versal-usb2-ctrl-regs.h | 3 +++ > include/hw/virtio/virtio-mmio.h | 2 +- > include/hw/virtio/virtio.h | 1 - > include/qemu/plugin-memory.h | 3 +++ > include/qemu/userfaultfd.h | 1 - > include/sysemu/dirtyrate.h | 2 ++ > include/sysemu/dump.h | 1 + > include/user/syscall-trace.h | 1 + > net/vmnet_int.h | 1 - > qga/cutils.h | 1 - > target/hexagon/hex_arch_types.h | 1 - > target/hexagon/mmvec/macros.h | 1 - > target/riscv/pmu.h | 1 - > hw/virtio/virtio-qmp.c | 1 + > hw/virtio/virtio.c | 1 + > qga/cutils.c | 3 ++- > 59 files changed, 82 insertions(+), 22 deletions(-) > > -- > 2.38.1 From MAILER-DAEMON Sun Jan 08 01:51:17 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pEPWX-0002b1-KL for mharc-qemu-riscv@gnu.org; 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Tsirkin" To: Markus Armbruster Cc: qemu-devel@nongnu.org, imammedo@redhat.com, ani@anisinha.ca, peter.maydell@linaro.org, laurent@vivier.eu, edgar.iglesias@gmail.com, Alistair.Francis@wdc.com, bin.meng@windriver.com, palmer@dabbelt.com, marcel.apfelbaum@gmail.com, yangxiaojuan@loongson.cn, gaosong@loongson.cn, richard.henderson@linaro.org, deller@gmx.de, jasowang@redhat.com, vikram.garhwal@amd.com, francisco.iglesias@amd.com, clg@kaod.org, kraxel@redhat.com, marcandre.lureau@redhat.com, riku.voipio@iki.fi, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, crwulff@gmail.com, marex@denx.de, Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Bin Meng , Taylor Simpson Subject: Re: [PATCH v2 3/4] include: Don't include qemu/osdep.h Message-ID: <20230108015023-mutt-send-email-mst@kernel.org> References: <20221222120813.727830-1-armbru@redhat.com> <20221222120813.727830-4-armbru@redhat.com> MIME-Version: 1.0 In-Reply-To: <20221222120813.727830-4-armbru@redhat.com> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 08 Jan 2023 06:51:16 -0000 On Thu, Dec 22, 2022 at 01:08:12PM +0100, Markus Armbruster wrote: > docs/devel/style.rst mandates: > > The "qemu/osdep.h" header contains preprocessor macros that affect > the behavior of core system headers like . It must be > the first include so that core system headers included by external > libraries get the preprocessor macros that QEMU depends on. > > Do not include "qemu/osdep.h" from header files since the .c file > will have already included it. > > A few violations have crept in. Fix them. > > Signed-off-by: Markus Armbruster > Reviewed-by: Philippe Mathieu-Daudé > Reviewed-by: Bin Meng > Reviewed-by: Taylor Simpson > Reviewed-by: Alistair Francis Dropped this one due to CI failures. > --- > bsd-user/qemu.h | 1 - > crypto/block-luks-priv.h | 1 - > include/hw/cxl/cxl_host.h | 1 - > include/hw/input/pl050.h | 1 - > include/hw/tricore/triboard.h | 1 - > include/qemu/userfaultfd.h | 1 - > net/vmnet_int.h | 1 - > qga/cutils.h | 1 - > target/hexagon/hex_arch_types.h | 1 - > target/hexagon/mmvec/macros.h | 1 - > target/riscv/pmu.h | 1 - > qga/cutils.c | 3 ++- > 12 files changed, 2 insertions(+), 12 deletions(-) > > diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h > index be6105385e..0ceecfb6df 100644 > --- a/bsd-user/qemu.h > +++ b/bsd-user/qemu.h > @@ -17,7 +17,6 @@ > #ifndef QEMU_H > #define QEMU_H > > -#include "qemu/osdep.h" > #include "cpu.h" > #include "qemu/units.h" > #include "exec/cpu_ldst.h" > diff --git a/crypto/block-luks-priv.h b/crypto/block-luks-priv.h > index dc2dd14e52..8fc967afcb 100644 > --- a/crypto/block-luks-priv.h > +++ b/crypto/block-luks-priv.h > @@ -18,7 +18,6 @@ > * > */ > > -#include "qemu/osdep.h" > #include "qapi/error.h" > #include "qemu/bswap.h" > > diff --git a/include/hw/cxl/cxl_host.h b/include/hw/cxl/cxl_host.h > index a1b662ce40..c9bc9c7c50 100644 > --- a/include/hw/cxl/cxl_host.h > +++ b/include/hw/cxl/cxl_host.h > @@ -7,7 +7,6 @@ > * COPYING file in the top-level directory. > */ > > -#include "qemu/osdep.h" > #include "hw/cxl/cxl.h" > #include "hw/boards.h" > > diff --git a/include/hw/input/pl050.h b/include/hw/input/pl050.h > index 89ec4fafc9..4cb8985f31 100644 > --- a/include/hw/input/pl050.h > +++ b/include/hw/input/pl050.h > @@ -10,7 +10,6 @@ > #ifndef HW_PL050_H > #define HW_PL050_H > > -#include "qemu/osdep.h" > #include "hw/sysbus.h" > #include "migration/vmstate.h" > #include "hw/input/ps2.h" > diff --git a/include/hw/tricore/triboard.h b/include/hw/tricore/triboard.h > index 094c8bd563..4fdd2d7d97 100644 > --- a/include/hw/tricore/triboard.h > +++ b/include/hw/tricore/triboard.h > @@ -18,7 +18,6 @@ > * License along with this library; if not, see . > */ > > -#include "qemu/osdep.h" > #include "qapi/error.h" > #include "hw/boards.h" > #include "sysemu/sysemu.h" > diff --git a/include/qemu/userfaultfd.h b/include/qemu/userfaultfd.h > index 6b74f92792..55c95998e8 100644 > --- a/include/qemu/userfaultfd.h > +++ b/include/qemu/userfaultfd.h > @@ -13,7 +13,6 @@ > #ifndef USERFAULTFD_H > #define USERFAULTFD_H > > -#include "qemu/osdep.h" > #include "exec/hwaddr.h" > #include > > diff --git a/net/vmnet_int.h b/net/vmnet_int.h > index adf6e8c20d..d0b90594f2 100644 > --- a/net/vmnet_int.h > +++ b/net/vmnet_int.h > @@ -10,7 +10,6 @@ > #ifndef VMNET_INT_H > #define VMNET_INT_H > > -#include "qemu/osdep.h" > #include "vmnet_int.h" > #include "clients.h" > > diff --git a/qga/cutils.h b/qga/cutils.h > index f0f30a7d28..2bfaf554a8 100644 > --- a/qga/cutils.h > +++ b/qga/cutils.h > @@ -1,7 +1,6 @@ > #ifndef CUTILS_H_ > #define CUTILS_H_ > > -#include "qemu/osdep.h" > > int qga_open_cloexec(const char *name, int flags, mode_t mode); > > diff --git a/target/hexagon/hex_arch_types.h b/target/hexagon/hex_arch_types.h > index 885f68f760..52a7f2b2f3 100644 > --- a/target/hexagon/hex_arch_types.h > +++ b/target/hexagon/hex_arch_types.h > @@ -18,7 +18,6 @@ > #ifndef HEXAGON_HEX_ARCH_TYPES_H > #define HEXAGON_HEX_ARCH_TYPES_H > > -#include "qemu/osdep.h" > #include "mmvec/mmvec.h" > #include "qemu/int128.h" > > diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h > index 8c864e8c68..1201d778d0 100644 > --- a/target/hexagon/mmvec/macros.h > +++ b/target/hexagon/mmvec/macros.h > @@ -18,7 +18,6 @@ > #ifndef HEXAGON_MMVEC_MACROS_H > #define HEXAGON_MMVEC_MACROS_H > > -#include "qemu/osdep.h" > #include "qemu/host-utils.h" > #include "arch.h" > #include "mmvec/system_ext_mmvec.h" > diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h > index 3004ce37b6..0c819ca983 100644 > --- a/target/riscv/pmu.h > +++ b/target/riscv/pmu.h > @@ -16,7 +16,6 @@ > * this program. If not, see . > */ > > -#include "qemu/osdep.h" > #include "qemu/log.h" > #include "cpu.h" > #include "qemu/main-loop.h" > diff --git a/qga/cutils.c b/qga/cutils.c > index b8e142ef64..b21bcf3683 100644 > --- a/qga/cutils.c > +++ b/qga/cutils.c > @@ -2,8 +2,9 @@ > * This work is licensed under the terms of the GNU GPL, version 2 or later. > * See the COPYING file in the top-level directory. > */ > -#include "cutils.h" > > +#include "qemu/osdep.h" > +#include "cutils.h" > #include "qapi/error.h" > > /** > -- > 2.38.1 From MAILER-DAEMON Mon Jan 09 05:40:01 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pEpZR-0000vB-GU for mharc-qemu-riscv@gnu.org; Mon, 09 Jan 2023 05:40:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEpZP-0000rX-J2 for qemu-riscv@nongnu.org; Mon, 09 Jan 2023 05:39:59 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEpZM-0006F3-Ro for qemu-riscv@nongnu.org; Mon, 09 Jan 2023 05:39:59 -0500 Received: by mail-wm1-x335.google.com with SMTP id ja17so5921612wmb.3 for ; Mon, 09 Jan 2023 02:39:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=xTy+zRGaEwMAcEbHvrvejMsiUb0iYAe4ynWYjVfKoxI=; b=Z1268/tM6Aj/IyFSOml1jlpxYo5Tmm9/LFWbpXJoBCxMsdpuCsa2S+rB60JDUJd8zN 57RArsniLkLotHCCihCrjErybNDEHwnS/CjbP7xKWI7mj2XO2FWlH2EZiKR2VKfTzO2n wQ1w09lNMuwU/wuqr6PHCCdvWaEz+eJKSItvQ0tEYYuHzLZb4DZ77Dphp+DtV4QRM/iE 2xGDTlcx5+Lno0BMonPSAz0rUC2gAzj3Clyuvf+JKrgDk5di/jX39cFZo6e0kvojbLVx JDO07FXFk28qWTeFvO0MC4GfuMuJXAz7JqzALlm7Uom2C9lNEWOAVr/kc5T8WuO9GxpZ Gpew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=xTy+zRGaEwMAcEbHvrvejMsiUb0iYAe4ynWYjVfKoxI=; b=Zvh0rC9IGSchmugauFWBDdzXNHPH3RM5kA/jPFUwicDBZb7n2rJQqDtF+DHuD/Z5fD KGYjLc64EfKTiKL2YtNaYPEhrxn9UcVJYzqIk8Fk5UZyZymMmU0fn/o/nJ129AT2QW1W qfzojx6ITxv4kVfwErRLWMJ/5v8wShkardjC+cUGmOUVDyFn5NzL1pNYvrrvI8y0qFIY WxKVz3fp9n/nND6h5ujg5HIFrXibLiaTUfT3SJVHWPYmejGzH89+uvYb2mQC1yiH15L5 BRxYEqROxQaBrXowrFSWsJWaeelnpX7DqGKY9FqIgh8IIoq5OBeRF1c+fqMyYoO4orRG poJQ== X-Gm-Message-State: AFqh2kqzpjhZus7zQ6m6dXxTFhzyhkIrGBpm3ul2zfZChBZYKTEKxXyi iVeS+aoBjZiFgdI34vYFjZN6rw== X-Google-Smtp-Source: AMrXdXthBUXATOPlkec5oXveGh6z9ogH8gGRCTiMoMnVLKfg4FxlxrzuSxfHzu5FnCWXDA3dtjRI4Q== X-Received: by 2002:a05:600c:4fce:b0:3d9:ee01:60a4 with SMTP id o14-20020a05600c4fce00b003d9ee0160a4mr3050376wmq.1.1673260794779; Mon, 09 Jan 2023 02:39:54 -0800 (PST) Received: from [192.168.30.216] ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id o5-20020a05600c510500b003b4ff30e566sm24693383wms.3.2023.01.09.02.39.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Jan 2023 02:39:54 -0800 (PST) Message-ID: <9ce88e6c-005a-68a3-0962-361981604536@linaro.org> Date: Mon, 9 Jan 2023 11:39:51 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH 00/20] hw: Remove implicit sysbus_mmio_map() from pflash APIs Content-Language: en-US To: Peter Maydell Cc: qemu-devel@nongnu.org, Song Gao , Antony Pavlov , Jan Kiszka , Marcel Apfelbaum , Hanna Reitz , Bernhard Beschow , BALATON Zoltan , Alistair Francis , Paolo Bonzini , qemu-ppc@nongnu.org, Mark Burton , Richard Henderson , Magnus Damm , "Michael S. Tsirkin" , Bin Meng , Max Filippov , Aurelien Jarno , Eduardo Habkost , Palmer Dabbelt , Radoslaw Biernacki , Jiaxun Yang , "Edgar E. Iglesias" , Xiaojuan Yang , qemu-block@nongnu.org, qemu-riscv@nongnu.org, Yoshinori Sato , Alistair Francis , qemu-arm@nongnu.org, Leif Lindholm , Kevin Wolf References: <20230104220449.41337-1-philmd@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Jan 2023 10:39:59 -0000 On 6/1/23 18:51, Peter Maydell wrote: > On Wed, 4 Jan 2023 at 22:04, Philippe Mathieu-Daudé wrote: >> >> Paving the road toward heterogeneous QEMU, the limitations of >> having a single machine sysbus become more apparent. >> >> The sysbus_mmio_map() API forces the caller to map a sysbus >> device to an address on the system bus (system bus here is >> the root MemoryRegion returned by get_system_memory() ). >> >> This is not practical when each core has its own address >> space and group of cores have access to a part of the >> peripherals. >> >> Experimenting with the PFLASH devices. Here the fix is >> quite easy, we split the pflash_cfi_register() -- which >> does the implicit sysbus mapping -- into an explicit qdev >> pflash_cfi_create() followed by the sysbus_mmio_map() call. > > pflash_cfi_register() is a legacy convenience function. If > you don't like the sysbus_mmio_map() it does then you can > create, configure, realize and map the device directly. > This is what hw/arm/virt.c does, for instance (it wants to > map the flash devices into either secure or non secure RAM). Good point, thanks! From MAILER-DAEMON Mon Jan 09 07:01:40 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pEqqS-0005Zu-1I for mharc-qemu-riscv@gnu.org; Mon, 09 Jan 2023 07:01:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEqqR-0005Zg-0X for qemu-riscv@nongnu.org; Mon, 09 Jan 2023 07:01:39 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEqqP-0001nT-3h for qemu-riscv@nongnu.org; Mon, 09 Jan 2023 07:01:38 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1673265696; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=TclbkyhSX21Sa2KCTCzGt6PcChwfW7SrUYi93nNWHac=; b=VFX3oE1SVhK9Ensqi85YmgFlEZURWub+aJkCH/Dd6J1w3AczINGbYEfRgnZO8BrAwVSl0O 9gZLf+WdqHhr5K86ycgwprAE99xi9YzMST4WvVghh0h3b5L+KFFpX/A6gp5PWMnwysD6iR Chs6sc2kT6pg9PRpG8YOz1leSg/XjcA= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-379-qs0PPn3tPlS0juzuVCqIkg-1; Mon, 09 Jan 2023 07:01:32 -0500 X-MC-Unique: qs0PPn3tPlS0juzuVCqIkg-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 1E6411869B72; Mon, 9 Jan 2023 12:01:30 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.78]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 1E7CE492B01; Mon, 9 Jan 2023 12:01:29 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 79D7021E5DCF; Mon, 9 Jan 2023 13:01:27 +0100 (CET) From: Markus Armbruster To: Bernhard Beschow Cc: qemu-devel@nongnu.org, mst@redhat.com, imammedo@redhat.com, ani@anisinha.ca, peter.maydell@linaro.org, laurent@vivier.eu, edgar.iglesias@gmail.com, Alistair.Francis@wdc.com, bin.meng@windriver.com, palmer@dabbelt.com, marcel.apfelbaum@gmail.com, yangxiaojuan@loongson.cn, gaosong@loongson.cn, richard.henderson@linaro.org, deller@gmx.de, jasowang@redhat.com, vikram.garhwal@amd.com, francisco.iglesias@amd.com, clg@kaod.org, kraxel@redhat.com, marcandre.lureau@redhat.com, riku.voipio@iki.fi, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, crwulff@gmail.com, marex@denx.de Subject: Re: [PATCH v2 4/4] docs/devel: Rules on #include in headers References: <20221222120813.727830-1-armbru@redhat.com> <20221222120813.727830-5-armbru@redhat.com> <3400786A-51BD-43D6-A6E4-4EE0A91D1C4E@gmail.com> Date: Mon, 09 Jan 2023 13:01:27 +0100 In-Reply-To: <3400786A-51BD-43D6-A6E4-4EE0A91D1C4E@gmail.com> (Bernhard Beschow's message of "Fri, 23 Dec 2022 10:47:39 +0000") Message-ID: <87ilhfq5m0.fsf@pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Scanned-By: MIMEDefang 3.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Jan 2023 12:01:39 -0000 Bernhard Beschow writes: > Am 22. Dezember 2022 12:08:13 UTC schrieb Markus Armbruster : >>Rules for headers were proposed a long time ago, and generally liked: >> >> Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org> >> https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html >> >>Wortk them into docs/devel/style.rst. >> >>Suggested-by: Bernhard Beschow >>Signed-off-by: Markus Armbruster >>--- >> docs/devel/style.rst | 7 +++++++ >> 1 file changed, 7 insertions(+) >> >>diff --git a/docs/devel/style.rst b/docs/devel/style.rst >>index 7ddd42b6c2..68aa776930 100644 >>--- a/docs/devel/style.rst >>+++ b/docs/devel/style.rst >>@@ -293,6 +293,13 @@ that QEMU depends on. >> Do not include "qemu/osdep.h" from header files since the .c file will have >> already included it. >> >>+Headers should normally include everything they need beyond osdep.h. >>+If exceptions are needed for some reason, they must be documented in >>+the header. If all that's needed from a header is typedefs, consider >>+putting those into qemu/typedefs.h instead of including the header. >>+ >>+Cyclic inclusion is forbidden. >>+ > > Nice! > > I wonder if these should be bullet points like in your mail from 2016. I found them crystal clear since they looked like a todo list for review. I tried to blend my change in with the existing text. > Feel free to respin. Either way: > > Reviewed-by: Bernhard Beschow Thanks! From MAILER-DAEMON Mon Jan 09 07:13:28 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pEr1s-0002E2-Ic for mharc-qemu-riscv@gnu.org; Mon, 09 Jan 2023 07:13:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEr1r-00029A-1A for qemu-riscv@nongnu.org; Mon, 09 Jan 2023 07:13:27 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEr1o-0007sA-0g for qemu-riscv@nongnu.org; Mon, 09 Jan 2023 07:13:26 -0500 Received: by mail-wr1-x42b.google.com with SMTP id z5so6882163wrt.6 for ; Mon, 09 Jan 2023 04:13:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:cc:references:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=oOa558W65nN+mwNWf4ehs5ixKO9EILkwd73Dl1/KY5o=; b=PuQuI74czYjUtr2rm0hjfOH1AslxKCn6g1PF6QqtoswM1Sk6U2qcMQ5B/4pTULuZeg oDWjOvVp/oUVD4wST9ssqo09Q/KRtsYWCtLIeQ5y4RD5jsok+vnMHmQXBp7GjaFa9aDc 6JJXy6V9M/8H01dXogYeEaj+tXrBqmEM3pH5BInqskRGLPU2331GjkKAr7tDUZpsGOma NDfXpHPa+4g4Nv2fhsklrcV7hPfSlZe5Kw9x4kxAL3Rf/Q05pnQCxGdEqUqws6RZeuWq QTHaj/CobfOXIMCiV5absvugbdGvXmc7dLpv0xZBD/K04LoYSP5roTZjaZdfWu7VrP6f 7gaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:cc:references:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=oOa558W65nN+mwNWf4ehs5ixKO9EILkwd73Dl1/KY5o=; b=WL+ZIQ9z0gGS8+QumTJ+TZCFbCWIURosYXSLi796ZdFbfaxLyP12NDMEd/bav653mG pKqYJgBMyTueIVtxRCC5KXq+iN5D0xUYrZ2gq1TsDqBDikEANwJgRxbhoyeC+nYnzx8G 8c92fvhn+XKbhqfRDyjWJGAf7EPkJYeX/a7uj4GEDfvgUQy8H6us1a6UeY39c8Vbxfx7 8T4rPvEkom3GPuAxbe9m9iYrt10qfW9JPvsJagr6gkSm6mhNUg6rWrxn359MWoiuxqOc AyrXMC4IBbC3CtXqPcExPKpRsnaGStXDwd2Ql4bh5W8ziTqATXEVmEcbLAh41ySA6iig Roow== X-Gm-Message-State: AFqh2kpoIOCxzawVgoNZgksgfA6Mb12MypzAEvOlnOR8JsQIbcZiCijo 8SRvX3/tNPJbqArdKKCGgOu5K1FMHq4y4TK+ X-Google-Smtp-Source: AMrXdXsHgQ52Ck2tp7xpe9Yo1kEeKssHFEVhiWNTk6eI1v+ApwgdTpbiT4ZQis3l97GX98/KQfVztQ== X-Received: by 2002:a05:6000:1f1b:b0:2b8:27df:d43f with SMTP id bv27-20020a0560001f1b00b002b827dfd43fmr12843832wrb.24.1673266402512; Mon, 09 Jan 2023 04:13:22 -0800 (PST) Received: from [192.168.30.216] ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id k18-20020adfb352000000b00241fab5a296sm8637861wrd.40.2023.01.09.04.13.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Jan 2023 04:13:21 -0800 (PST) Message-ID: <0e0f31fd-4d10-7bfe-af6d-3bee3cee1073@linaro.org> Date: Mon, 9 Jan 2023 13:13:20 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v2 00/21] hw: Remove implicit sysbus_mmio_map() from pflash APIs Content-Language: en-US To: qemu-devel@nongnu.org References: <20230109120833.3330-1-philmd@linaro.org> Cc: qemu-ppc@nongnu.org, qemu-arm , "open list:SiFive Machines" , Xiaojuan Yang , "Edgar E. Iglesias" , Yoshinori Sato , Magnus Damm , Max Filippov , Song Gao From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230109120833.3330-1-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Jan 2023 12:13:27 -0000 On 9/1/23 13:08, Philippe Mathieu-Daudé wrote: > Since v1: > - Do not introduce pflash_cfi_create(), directly > open-code pflash_cfi_register() before removing it (Peter) > - Added R-b tags Sigh, my sendemail.cccmd command didn't work, so Cc'ing manually the cover. > Paving the road toward heterogeneous QEMU, the limitations of > having a single machine sysbus become more apparent. > > The sysbus_mmio_map() API forces the caller to map a sysbus > device to an address on the system bus (system bus here is > the root MemoryRegion returned by get_system_memory() ). > > This is not practical when each core has its own address > space and group of cores have access to a part of the > peripherals. > > Experimenting with the PFLASH devices. Here the fix is > quite easy: open-code the pflash_cfi_register() functions. > > Since we were touching the PFLASH API, we restricted the > PFlashCFI0X structures to their models. The API now deals > with a generic qdev pointer (DeviceState*). > > Please review, > > Phil. > > Based-on: <20230109115316.2235-1-philmd@linaro.org> > "hw/arm: Cleanups before pflash refactor" > Based-on: <20230109120154.2868-1-philmd@linaro.org> > "hw/misc: Cleanups around PFLASH use" > > Philippe Mathieu-Daudé (21): > hw/block: Rename TYPE_PFLASH_CFI02 'width' property as 'device-width' > hw/block: Pass DeviceState to pflash_cfi01_get_blk() > hw/block: Use pflash_cfi01_get_blk() in pflash_cfi01_legacy_drive() > hw/block: Pass DeviceState to pflash_cfi01_get_memory() > hw/arm: Use generic DeviceState instead of PFlashCFI01 > hw/loongarch: Use generic DeviceState instead of PFlashCFI01 > hw/riscv: Use generic DeviceState instead of PFlashCFI01 > hw/i386: Use generic DeviceState instead of PFlashCFI01 > hw/xtensa: Use generic DeviceState instead of PFlashCFI01 > hw/sh4: Open-code pflash_cfi02_register() > hw/arm/digic: Open-code pflash_cfi02_register() > hw/arm/musicpal: Open-code pflash_cfi02_register() > hw/arm/xilinx_zynq: Open-code pflash_cfi02_register() > hw/block: Remove unused pflash_cfi02_register() > hw/block: Make PFlashCFI02 QOM declaration internal > hw/arm: Open-code pflash_cfi01_register() > hw/microblaze: Open-code pflash_cfi01_register() > hw/mips: Open-code pflash_cfi01_register() > hw/ppc: Open-code pflash_cfi01_register() > hw/block: Remove unused pflash_cfi01_register() > hw/block: Make PFlashCFI01 QOM declaration internal From MAILER-DAEMON Mon Jan 09 10:27:24 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pEu3Y-0000BO-2J for mharc-qemu-riscv@gnu.org; Mon, 09 Jan 2023 10:27:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEu3W-00007s-0i; Mon, 09 Jan 2023 10:27:22 -0500 Received: from bg4.exmail.qq.com ([43.154.221.58]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEu3Q-0004mb-9V; Mon, 09 Jan 2023 10:27:18 -0500 X-QQ-mid: bizesmtp63t1673278017tgq0rfh0 Received: from ubuntu.. ( [111.196.135.79]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 09 Jan 2023 23:26:55 +0800 (CST) X-QQ-SSF: 01200000002000C0C000B00A0000000 X-QQ-FEAT: aBJFcW+uBGY6e7Ss6CavoxlfO09rPEQZXsKF/PrBVtVz3BBTPBOTUL6Kp35xw alb4/KkOXSa7kOSMtFZUP1mS+h4ONfvNkgMtzfvJi2LrG0NSkHrCv6fgxbY6owRK59qnDzq V2RygLIOrtHzksACKWd/wDZsD2U+Xz9InnEu163CbvoM7Yage2QsqVWlcit3uGBwrvSvUP3 RuLQGJpF5r4o0NpkoXOgDS/7Puj85fqG++3stZeA2mVR4fmilDowyAbrKxS2mgVTW1OHQcW P7jaJwyI761BjVyQEIhsg7gIdx63FUu8RsMEcEX6REQD7RbveJZA9p1ylr9Qg91RdRjxP5J KZ/uQA8DBvJI8Pk7Es= X-QQ-GoodBg: 0 From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH] target/riscv: Use TARGET_FMT_lx for env->mhartid Date: Mon, 9 Jan 2023 23:26:55 +0800 Message-Id: <20230109152655.340114-1-bmeng@tinylab.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:tinylab.org:qybglogicsvr:qybglogicsvr3 Received-SPF: pass client-ip=43.154.221.58; envelope-from=bmeng@tinylab.org; helo=bg4.exmail.qq.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Jan 2023 15:27:22 -0000 env->mhartid is currently casted to long before printed, which drops the high 32-bit for rv64 on 32-bit host. Use TARGET_FMT_lx instead. Signed-off-by: Bin Meng --- target/riscv/cpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cc75ca7667..a5ed6d3f63 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -660,9 +660,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) (env->priv_ver < isa_edata_arr[i].min_version)) { isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); #ifndef CONFIG_USER_ONLY - warn_report("disabling %s extension for hart 0x%lx because " - "privilege spec version does not match", - isa_edata_arr[i].name, (unsigned long)env->mhartid); + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx + " because privilege spec version does not match", + isa_edata_arr[i].name, env->mhartid); #else warn_report("disabling %s extension because " "privilege spec version does not match", -- 2.34.1 From MAILER-DAEMON Mon Jan 09 10:47:45 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pEuNF-0000M8-AQ for mharc-qemu-riscv@gnu.org; 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Mon, 09 Jan 2023 07:47:33 -0800 (PST) Message-ID: <6e3de50d-38d9-b5ba-dac4-91352be8b96b@linaro.org> Date: Mon, 9 Jan 2023 16:47:31 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH] target/riscv: Use TARGET_FMT_lx for env->mhartid Content-Language: en-US To: Bin Meng , Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <20230109152655.340114-1-bmeng@tinylab.org> Cc: Thomas Huth , =?UTF-8?Q?Alex_Benn=c3=a9e?= From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230109152655.340114-1-bmeng@tinylab.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Jan 2023 15:47:44 -0000 On 9/1/23 16:26, Bin Meng wrote: > env->mhartid is currently casted to long before printed, which drops > the high 32-bit for rv64 on 32-bit host. Use TARGET_FMT_lx instead. Oh, a 32-bit host user! > Signed-off-by: Bin Meng > --- > > target/riscv/cpu.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index cc75ca7667..a5ed6d3f63 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -660,9 +660,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > (env->priv_ver < isa_edata_arr[i].min_version)) { > isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); > #ifndef CONFIG_USER_ONLY > - warn_report("disabling %s extension for hart 0x%lx because " > - "privilege spec version does not match", > - isa_edata_arr[i].name, (unsigned long)env->mhartid); > + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx > + " because privilege spec version does not match", > + isa_edata_arr[i].name, env->mhartid); Could we cast it to vaddr instead? I'm trying to remove target_[u]long from hw/ and restrict it to the target/ directory. Per "exec/cpu-common.h": /** * vaddr: * Type wide enough to contain any #target_ulong virtual address. */ typedef uint64_t vaddr; Alternatively, since this value has to be accessed out of target/, can we change its type to vaddr in CPURISCVState? Thanks, Phil. From MAILER-DAEMON Mon Jan 09 10:53:58 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pEuTG-0002sx-Fq for mharc-qemu-riscv@gnu.org; Mon, 09 Jan 2023 10:53:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEuTE-0002sS-18; Mon, 09 Jan 2023 10:53:56 -0500 Received: from mail-ed1-x530.google.com ([2a00:1450:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEuTC-0003WX-Cb; Mon, 09 Jan 2023 10:53:55 -0500 Received: by mail-ed1-x530.google.com with SMTP id z11so13198433ede.1; Mon, 09 Jan 2023 07:53:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=q4yqZifAL0IpQxx9YA1ZIQEJ7BSgFoZHHDy0bwIS/Mw=; b=JyCy0sh7WPSpIoNTVqRV9EgOwKyD4fgJ6VBO5R6Wtpgf8dG9yXPWMXbjUCGqrHzr/W M0m26pnhYHZzN+E3nt5CtG5IsEp4M5ivTV33clSab41JXzVHcxyKJPelqLLOXS7Fny2W CNix+VHZTRFZQTshX1kMBlgxhHSYYQ2jzdz0NK8GqaXXNg/QM4KNOCcxU5u1xv/U6Rbc 17kxZoH+9pirJoYAIi05KgaCbSkU8eUb3I3QfqfRRoiENyxZCFiobIynaHbV1Bw805jb Vt8BDNV6NAuFUhrm8HQUvwtvEVj0sB9R0atVoXW/HpR4gV1BXDQVSd714BxX1i8DXA5w +ruw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=q4yqZifAL0IpQxx9YA1ZIQEJ7BSgFoZHHDy0bwIS/Mw=; b=rMSmaKwhNRsrtgy3XaZXchpVTcsSfWfJRV9ptt7sD5D/UlcGIG0CSMzDxuB6SjqYJq 0bOU1AQwDsTPQadnLs3MVsJzeNEzx4ogBB+lJQ6Fkrz9PhflApmuWzB6iAy/tP3SApFn fb78otqRsXGpD65s3PzZXpYfHzfXMCye8W1sys9Z4Bk5nFiWsl53iyd5cariXwMp1SYg W2+2oI2rqZUGCRbWEFd2J+iqUg7o6ODhczx0N8VxZLvrcXxpKwgWqb3E6n/3gzEBBKR0 flOxQwmWL8fsZj0wXIql07EyBjwZNjui/VZuS7NYcyi8CCSi7XLcDaQn6a4gjedvRzSs RINg== X-Gm-Message-State: AFqh2kqDW1sHHW791+YUm4uDrbysR1ZUR9MNrbWoyoHGoBk1r4vXEuMZ sRXSpQ97etSO4QlNOGueQs+sPYedxPFFGltjNQc= X-Google-Smtp-Source: AMrXdXtmsOGkFoTKTw+R8LGRLUSlLHOsX6E7RrJlergXCHh35JjaQFCXFAaWKTxt1K/9bgqRKcuVQluYZvXVjl+CQbA= X-Received: by 2002:a05:6402:2895:b0:499:c172:c6d with SMTP id eg21-20020a056402289500b00499c1720c6dmr72609edb.193.1673279632201; Mon, 09 Jan 2023 07:53:52 -0800 (PST) MIME-Version: 1.0 References: <20230109152655.340114-1-bmeng@tinylab.org> <6e3de50d-38d9-b5ba-dac4-91352be8b96b@linaro.org> In-Reply-To: <6e3de50d-38d9-b5ba-dac4-91352be8b96b@linaro.org> From: Bin Meng Date: Mon, 9 Jan 2023 23:53:41 +0800 Message-ID: Subject: Re: [PATCH] target/riscv: Use TARGET_FMT_lx for env->mhartid To: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Cc: Bin Meng , Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Thomas Huth , =?UTF-8?B?QWxleCBCZW5uw6ll?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=bmeng.cn@gmail.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Jan 2023 15:53:56 -0000 On Mon, Jan 9, 2023 at 11:48 PM Philippe Mathieu-Daud=C3=A9 wrote: > > On 9/1/23 16:26, Bin Meng wrote: > > env->mhartid is currently casted to long before printed, which drops > > the high 32-bit for rv64 on 32-bit host. Use TARGET_FMT_lx instead. > > Oh, a 32-bit host user! > > > Signed-off-by: Bin Meng > > --- > > > > target/riscv/cpu.c | 6 +++--- > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index cc75ca7667..a5ed6d3f63 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -660,9 +660,9 @@ static void riscv_cpu_realize(DeviceState *dev, Err= or **errp) > > (env->priv_ver < isa_edata_arr[i].min_version)) { > > isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); > > #ifndef CONFIG_USER_ONLY > > - warn_report("disabling %s extension for hart 0x%lx because= " > > - "privilege spec version does not match", > > - isa_edata_arr[i].name, (unsigned long)env->mha= rtid); > > + warn_report("disabling %s extension for hart 0x" TARGET_FM= T_lx > > + " because privilege spec version does not matc= h", > > + isa_edata_arr[i].name, env->mhartid); > > Could we cast it to vaddr instead? I'm trying to remove target_[u]long > from hw/ and restrict it to the target/ directory. Per "exec/cpu-common.h= ": > > /** > * vaddr: > * Type wide enough to contain any #target_ulong virtual address. > */ > typedef uint64_t vaddr; > > Alternatively, since this value has to be accessed out of target/, > can we change its type to vaddr in CPURISCVState? > Technically it does not represent a virtual address but a target dependent register that can be 32-bit or 64-bit. Change env->mhartid to vaddr looks weird to me. Regards, Bin From MAILER-DAEMON Mon Jan 09 11:04:15 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pEudD-0007Sp-AT for mharc-qemu-riscv@gnu.org; Mon, 09 Jan 2023 11:04:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pEudB-0007SI-Tu for qemu-riscv@nongnu.org; Mon, 09 Jan 2023 11:04:14 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pEudA-0007OK-82 for qemu-riscv@nongnu.org; Mon, 09 Jan 2023 11:04:13 -0500 Received: by mail-pj1-x1034.google.com with SMTP id b9-20020a17090a7ac900b00226ef160dcaso8341399pjl.2 for ; Mon, 09 Jan 2023 08:04:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=hDSGGa2mIec3Z/Eyh62lHcxtXQEkdf79o5GxRHENBpg=; b=NK7ovHYk83SGT5W8AxUehZpsJBxiWqIYf7o00fwX8TL/105XEXLWFcNmK9zvV672Wf U9EgqxQPAabMNAw2iOqM27DOUuXtchuhyx56H3Iq6BJ04PN+enUrHnG4Q3dlGE/R0cdw mP4He7oqSuRJd7JbwNTpTpoAr3Mp6FU6J8SD0n+AkWYhWxzUnnqvzPyAGpuNyipWWrpu 55yOGPaNveN1Uineys3qL1Gu88lLFdbMVpGTYxNeA2SheOFPWRE0azO6qJwbC5zuZ5uO hMqo+pAreKM644i56UUmDSL69KiU3BjJiT3LzqOJTSpaRZ8pM7DLYdETkWuWto9E6X1+ YKhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=hDSGGa2mIec3Z/Eyh62lHcxtXQEkdf79o5GxRHENBpg=; b=7oU2v0DXN1e+TJWm8a8o1YeE5HuLTBTzd35nHG2UTuj2nJ6Wuef1mCVXzz2kB1j6lb o7dWPtAPDuVpUE7y9MUVTfD20dVdBWZDppsPVZiqZAx+VGNIa0ooTTmL/dRn5bQ1YVMh BudLh10mTvz97xKag6ztPPduTHvhqP96ksTCNb8wbR4oJlt2pEAPXGkzSonZq3XZy75D YB9uf8bWyaSYEEf51xVtRX7PH9/zd84gVgOXw6ZFbONgsgJBTUtNS/34i/Bn7NHyzDzA mW+FVCGET+I2sdA62esQkK7G4HE+ujefZlylO6g5EbmfVwwgUEij82/BQuLdUR7gCGVU sVSA== X-Gm-Message-State: AFqh2krKhQMvwsPRuAK6FdO+upcT11Ry4zwsocErix3YTOk3ZQ6rNWCF acJugfEE8qBv13KjrJfGWxtMfw== X-Google-Smtp-Source: AMrXdXt7BZfuJ0YeM8omzk6LQmFFl4tdlJYcllBNIitnocEwwps+zwwpnWRKg3lOLP66s4NstgMKzQ== X-Received: by 2002:a17:902:9895:b0:191:282:5d72 with SMTP id s21-20020a170902989500b0019102825d72mr79790370plp.51.1673280250004; Mon, 09 Jan 2023 08:04:10 -0800 (PST) Received: from ?IPV6:2602:47:d48c:8101:a909:891c:953d:a6b0? ([2602:47:d48c:8101:a909:891c:953d:a6b0]) by smtp.gmail.com with ESMTPSA id t2-20020a1709027fc200b00192f9991e51sm6184362plb.251.2023.01.09.08.04.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 09 Jan 2023 08:04:09 -0800 (PST) Message-ID: <8d60f5b9-9fa9-2c21-d72e-609bfbaecf39@linaro.org> Date: Mon, 9 Jan 2023 08:04:07 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH] target/riscv: Use TARGET_FMT_lx for env->mhartid Content-Language: en-US To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Bin Meng , Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Thomas Huth , =?UTF-8?Q?Alex_Benn=c3=a9e?= References: <20230109152655.340114-1-bmeng@tinylab.org> <6e3de50d-38d9-b5ba-dac4-91352be8b96b@linaro.org> From: Richard Henderson In-Reply-To: <6e3de50d-38d9-b5ba-dac4-91352be8b96b@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Jan 2023 16:04:14 -0000 On 1/9/23 07:47, Philippe Mathieu-Daudé wrote: > On 9/1/23 16:26, Bin Meng wrote: >> env->mhartid is currently casted to long before printed, which drops >> the high 32-bit for rv64 on 32-bit host. Use TARGET_FMT_lx instead. > > Oh, a 32-bit host user! > >> Signed-off-by: Bin Meng >> --- >> >>   target/riscv/cpu.c | 6 +++--- >>   1 file changed, 3 insertions(+), 3 deletions(-) >> >> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> index cc75ca7667..a5ed6d3f63 100644 >> --- a/target/riscv/cpu.c >> +++ b/target/riscv/cpu.c >> @@ -660,9 +660,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) >>               (env->priv_ver < isa_edata_arr[i].min_version)) { >>               isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); >>   #ifndef CONFIG_USER_ONLY >> -            warn_report("disabling %s extension for hart 0x%lx because " >> -                        "privilege spec version does not match", >> -                        isa_edata_arr[i].name, (unsigned long)env->mhartid); >> +            warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx >> +                        " because privilege spec version does not match", >> +                        isa_edata_arr[i].name, env->mhartid); > > Could we cast it to vaddr instead? I'm trying to remove target_[u]long > from hw/ and restrict it to the target/ directory. Per "exec/cpu-common.h": This isn't in hw/, it's in target/. And no, it's a target-width register. r~ From MAILER-DAEMON Mon Jan 09 17:54:42 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pF12P-000515-Vg for mharc-qemu-riscv@gnu.org; Mon, 09 Jan 2023 17:54:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pF12N-0004wP-P5; Mon, 09 Jan 2023 17:54:39 -0500 Received: from mail-vk1-xa2f.google.com ([2607:f8b0:4864:20::a2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pF12L-0007jP-0s; Mon, 09 Jan 2023 17:54:38 -0500 Received: by mail-vk1-xa2f.google.com with SMTP id l185so1568483vke.2; Mon, 09 Jan 2023 14:54:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=wIml/86VIh1Yv5cQrS4eyVEugrgWsNH8gQXS0Z8IbwI=; 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Mon, 09 Jan 2023 14:54:35 -0800 (PST) MIME-Version: 1.0 References: <20221228062028.29415-1-liweiwei@iscas.ac.cn> In-Reply-To: <20221228062028.29415-1-liweiwei@iscas.ac.cn> From: Alistair Francis Date: Tue, 10 Jan 2023 08:54:09 +1000 Message-ID: Subject: Re: [PATCH v9 0/9] support subsets of code size reduction extension To: Weiwei Li Cc: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wangjunqiang@iscas.ac.cn, lazyparser@gmail.com Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a2f; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Jan 2023 22:54:40 -0000 On Wed, Dec 28, 2022 at 4:23 PM Weiwei Li wrote: > > This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version instru= ctions. > > Specification: > https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specifica= tion > > The port is available here: > https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v9 > > To test Zc* implementation, specify cpu argument with 'x-zca=3Dtrue,x-zcb= =3Dtrue,x-zcf=3Dtrue,f=3Dtrue" and "x-zcd=3Dtrue,d=3Dtrue" (or "x-zcmp=3Dtr= ue,x-zcmt=3Dtrue" with c or d=3Dfalse) to enable Zca/Zcb/Zcf and Zcd(or Zcm= p,Zcmt) extensions support. > > > This implementation can pass the basic zc tests from https://github.com/y= ulong-plct/zc-test > > v9: > * rebase on riscv-to-apply.next > > v8: > * improve disas support in Patch 9 > > v7: > * Fix description for Zca > > v6=EF=BC=9A > * fix base address for jump table in Patch 7 > * rebase on riscv-to-apply.next > > v5: > * fix exception unwind problem for cpu_ld*_code in helper of cm_jalt > > v4: > * improve Zcmp suggested by Richard > * fix stateen related check for Zcmt > > v3: > * update the solution for Zcf to the way of Zcd > * update Zcb to reuse gen_load/store > * use trans function instead of helper for push/pop > > v2: > * add check for relationship between Zca/Zcf/Zcd with C/F/D based on rela= ted discussion in review of Zc* spec > * separate c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/= zcmt > > Weiwei Li (9): > target/riscv: add cfg properties for Zc* extension > target/riscv: add support for Zca extension > target/riscv: add support for Zcf extension > target/riscv: add support for Zcd extension > target/riscv: add support for Zcb extension > target/riscv: add support for Zcmp extension > target/riscv: add support for Zcmt extension > target/riscv: expose properties for Zc* extension > disas/riscv.c: add disasm support for Zc* Thanks! Applied to riscv-to-apply.next Alistair > > disas/riscv.c | 228 +++++++++++++++- > target/riscv/cpu.c | 56 ++++ > target/riscv/cpu.h | 10 + > target/riscv/cpu_bits.h | 7 + > target/riscv/csr.c | 38 ++- > target/riscv/helper.h | 3 + > target/riscv/insn16.decode | 63 ++++- > target/riscv/insn_trans/trans_rvd.c.inc | 18 ++ > target/riscv/insn_trans/trans_rvf.c.inc | 18 ++ > target/riscv/insn_trans/trans_rvi.c.inc | 4 +- > target/riscv/insn_trans/trans_rvzce.c.inc | 313 ++++++++++++++++++++++ > target/riscv/machine.c | 19 ++ > target/riscv/meson.build | 3 +- > target/riscv/translate.c | 15 +- > target/riscv/zce_helper.c | 55 ++++ > 15 files changed, 834 insertions(+), 16 deletions(-) > create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc > create mode 100644 target/riscv/zce_helper.c > > -- > 2.25.1 > > From MAILER-DAEMON Mon Jan 09 17:56:04 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pF13k-0007Nm-Mk for mharc-qemu-riscv@gnu.org; Mon, 09 Jan 2023 17:56:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pF13S-0007GP-67; Mon, 09 Jan 2023 17:55:48 -0500 Received: from mail-vs1-xe29.google.com ([2607:f8b0:4864:20::e29]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pF13Q-0008AA-C3; Mon, 09 Jan 2023 17:55:45 -0500 Received: by mail-vs1-xe29.google.com with SMTP id a64so10449529vsc.2; Mon, 09 Jan 2023 14:55:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=uSd4nickcnF2PN5PBY4LlFHIMczV9y5pOQwPfKCt6bw=; b=R1FPlbuRYJCfqxuiWVakIP9SSLpA/THTOdIZQM6Qit+Kf+OovMleNk5llHZAvpAnEa hRtzZ60bbw3DQ+PhQ14WSUhAv/Zou6wb0d+m8iU5YWzM+YJAXc+2993Kf6ip92OfG0Ni UxFWA7qWBxJaPGWJIhEYsYu3YOZ21mjqIKjkX4GYb91IWd4XO9cBDciPCMnuuSLjfC24 ekgoap+PYkcN0CDlhCG5PFVSIKo3L9eGajoK8BgVeOG7uh2ovnXeKkTLKqQm8M23OYVM wXZD0tyPE08JVtv4UYT0JjIrVqPGOJjqWTGk5YfdZ9iyvpmQKjMjjDQekBJV78caNVLS hKtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=uSd4nickcnF2PN5PBY4LlFHIMczV9y5pOQwPfKCt6bw=; b=nVT0j6otVid495ExuUkwqxJfG8g6ycqcWjy6opMlxh9vvSbtgzDJhUklF3mnoIaCjO GUKy5lgMYa96tisX6g+IcsyJdbwFd6Em0TCgtbVZHme0js/f1k8oqbdQk5MiV0P/xkJu xccTEOJ4rJezzzBF9UlfQ+kfvWJ4w69iwSRiBCL442sJMy8Df7wjyMMhXmD7VW9iqRe7 XxjIIXZLlPYIk3n8X8rnulDf5bXH1rallFVDkclySmGBpEdFC6sJ6nYlalzqWlPFB2JN 8mHW5lL6fJFABWEXrEFzHxnHcj0pmooD/KpgXUVGoxx+8EYhhRiGhniJ+yYsaOxKsfC3 bUvA== X-Gm-Message-State: AFqh2koCFhSbBSXLqizwS3NFs8dzajpXu16Yn4tTATmQ7Plgx+8/aHcy UvUyxNphDyTzZQ6AMIlT7UeRns+s6KmlxpbyEx8= X-Google-Smtp-Source: AMrXdXvhNocXySNj0fy9H8TsyCr0WI+Phrbpwwg2h3qsQ8gdIzfoKPFNjOpDrwJmVX/b4Jk4752XZCKCBRBAnIq3WpY= X-Received: by 2002:a05:6102:f8c:b0:3c9:8cc2:dd04 with SMTP id e12-20020a0561020f8c00b003c98cc2dd04mr7211260vsv.73.1673304938058; Mon, 09 Jan 2023 14:55:38 -0800 (PST) MIME-Version: 1.0 References: <20221229091828.1945072-1-bmeng@tinylab.org> <20221229091828.1945072-13-bmeng@tinylab.org> In-Reply-To: <20221229091828.1945072-13-bmeng@tinylab.org> From: Alistair Francis Date: Tue, 10 Jan 2023 08:55:11 +1000 Message-ID: Subject: Re: [PATCH v2 12/12] hw/riscv: spike: Decouple create_fdt() dependency to ELF loading To: Bin Meng Cc: Alistair Francis , qemu-devel@nongnu.org, Daniel Henrique Barboza , Bin Meng , =?UTF-8?B?TWFyYy1BbmRyw6kgTHVyZWF1?= , Palmer Dabbelt , Paolo Bonzini , qemu-riscv@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e29; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe29.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Jan 2023 22:56:02 -0000 On Thu, Dec 29, 2022 at 8:33 PM Bin Meng wrote: > > At present create_fdt() calls htif_uses_elf_symbols() to determine > whether to insert a property for the HTIF. This unfortunately > creates a hidden dependency to riscv_load_{firmware,kernel} that > create_fdt() must be called after the ELF {firmware,kernel} image > has been loaded. > > Decouple such dependency be adding a new parameter to create_fdt(), > whether custom HTIF base address is used. The flag will be set if > non ELF {firmware,kernel} image is given by user. > > Signed-off-by: Bin Meng Thanks! Applied to riscv-to-apply.next Alistair > > --- > > Changes in v2: > - initialize firmware_end_addr to memmap[SPIKE_DRAM].base > - rework the htif_custom_base detection logic > > include/hw/char/riscv_htif.h | 5 +-- > hw/char/riscv_htif.c | 17 +++++----- > hw/riscv/spike.c | 61 ++++++++++++++++++++++++++++++------ > 3 files changed, 59 insertions(+), 24 deletions(-) > > diff --git a/include/hw/char/riscv_htif.h b/include/hw/char/riscv_htif.h > index 9e8ebbe017..5958c5b986 100644 > --- a/include/hw/char/riscv_htif.h > +++ b/include/hw/char/riscv_htif.h > @@ -44,11 +44,8 @@ typedef struct HTIFState { > void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value, > uint64_t st_size); > > -/* Check if HTIF uses ELF symbols */ > -bool htif_uses_elf_symbols(void); > - > /* legacy pre qom */ > HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr, > - uint64_t nonelf_base); > + uint64_t nonelf_base, bool custom_base); > > #endif > diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c > index 1477fc0090..098de50e35 100644 > --- a/hw/char/riscv_htif.c > +++ b/hw/char/riscv_htif.c > @@ -52,20 +52,17 @@ > #define PK_SYS_WRITE 64 > > static uint64_t fromhost_addr, tohost_addr; > -static int address_symbol_set; > > void htif_symbol_callback(const char *st_name, int st_info, uint64_t st_value, > uint64_t st_size) > { > if (strcmp("fromhost", st_name) == 0) { > - address_symbol_set |= 1; > fromhost_addr = st_value; > if (st_size != 8) { > error_report("HTIF fromhost must be 8 bytes"); > exit(1); > } > } else if (strcmp("tohost", st_name) == 0) { > - address_symbol_set |= 2; > tohost_addr = st_value; > if (st_size != 8) { > error_report("HTIF tohost must be 8 bytes"); > @@ -275,19 +272,19 @@ static const MemoryRegionOps htif_mm_ops = { > .write = htif_mm_write, > }; > > -bool htif_uses_elf_symbols(void) > -{ > - return (address_symbol_set == 3) ? true : false; > -} > - > HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr, > - uint64_t nonelf_base) > + uint64_t nonelf_base, bool custom_base) > { > uint64_t base, size, tohost_offset, fromhost_offset; > > - if (!htif_uses_elf_symbols()) { > + if (custom_base) { > fromhost_addr = nonelf_base; > tohost_addr = nonelf_base + 8; > + } else { > + if (!fromhost_addr || !tohost_addr) { > + error_report("Invalid HTIF fromhost or tohost address"); > + exit(1); > + } > } > > base = MIN(tohost_addr, fromhost_addr); > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index 810a18f283..dd5f912e3d 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -50,7 +50,8 @@ static const MemMapEntry spike_memmap[] = { > }; > > static void create_fdt(SpikeState *s, const MemMapEntry *memmap, > - uint64_t mem_size, const char *cmdline, bool is_32_bit) > + uint64_t mem_size, const char *cmdline, > + bool is_32_bit, bool htif_custom_base) > { > void *fdt; > uint64_t addr, size; > @@ -78,7 +79,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, > > qemu_fdt_add_subnode(fdt, "/htif"); > qemu_fdt_setprop_string(fdt, "/htif", "compatible", "ucb,htif0"); > - if (!htif_uses_elf_symbols()) { > + if (htif_custom_base) { > qemu_fdt_setprop_cells(fdt, "/htif", "reg", > 0x0, memmap[SPIKE_HTIF].base, 0x0, memmap[SPIKE_HTIF].size); > } > @@ -184,18 +185,33 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, > } > } > > +static bool spike_test_elf_image(char *filename) > +{ > + Error *err = NULL; > + > + load_elf_hdr(filename, NULL, NULL, &err); > + if (err) { > + error_free(err); > + return false; > + } else { > + return true; > + } > +} > + > static void spike_board_init(MachineState *machine) > { > const MemMapEntry *memmap = spike_memmap; > SpikeState *s = SPIKE_MACHINE(machine); > MemoryRegion *system_memory = get_system_memory(); > MemoryRegion *mask_rom = g_new(MemoryRegion, 1); > - target_ulong firmware_end_addr, kernel_start_addr; > - const char *firmware_name; > + target_ulong firmware_end_addr = memmap[SPIKE_DRAM].base; > + target_ulong kernel_start_addr; > + char *firmware_name; > uint32_t fdt_load_addr; > uint64_t kernel_entry; > char *soc_name; > int i, base_hartid, hart_count; > + bool htif_custom_base = false; > > /* Check socket count limit */ > if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) { > @@ -257,10 +273,34 @@ static void spike_board_init(MachineState *machine) > memory_region_add_subregion(system_memory, memmap[SPIKE_MROM].base, > mask_rom); > > - firmware_name = riscv_default_firmware_name(&s->soc[0]); > - firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, > - memmap[SPIKE_DRAM].base, > - htif_symbol_callback); > + /* Find firmware */ > + firmware_name = riscv_find_firmware(machine->firmware, > + riscv_default_firmware_name(&s->soc[0])); > + > + /* > + * Test the given firmware or kernel file to see if it is an ELF image. > + * If it is an ELF, we assume it contains the symbols required for > + * the HTIF console, otherwise we fall back to use the custom base > + * passed from device tree for the HTIF console. > + */ > + if (!firmware_name && !machine->kernel_filename) { > + htif_custom_base = true; > + } else { > + if (firmware_name) { > + htif_custom_base = !spike_test_elf_image(firmware_name); > + } > + if (!htif_custom_base && machine->kernel_filename) { > + htif_custom_base = !spike_test_elf_image(machine->kernel_filename); > + } > + } > + > + /* Load firmware */ > + if (firmware_name) { > + firmware_end_addr = riscv_load_firmware(firmware_name, > + memmap[SPIKE_DRAM].base, > + htif_symbol_callback); > + g_free(firmware_name); > + } > > /* Load kernel */ > if (machine->kernel_filename) { > @@ -280,7 +320,7 @@ static void spike_board_init(MachineState *machine) > > /* Create device tree */ > create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, > - riscv_is_32bit(&s->soc[0])); > + riscv_is_32bit(&s->soc[0]), htif_custom_base); > > /* Load initrd */ > if (machine->kernel_filename && machine->initrd_filename) { > @@ -308,7 +348,8 @@ static void spike_board_init(MachineState *machine) > fdt_load_addr); > > /* initialize HTIF using symbols found in load_kernel */ > - htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base); > + htif_mm_init(system_memory, serial_hd(0), memmap[SPIKE_HTIF].base, > + htif_custom_base); > } > > static void spike_machine_instance_init(Object *obj) > -- > 2.34.1 > > From MAILER-DAEMON Mon Jan 09 18:05:06 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pF1CU-0005yI-4h for mharc-qemu-riscv@gnu.org; Mon, 09 Jan 2023 18:05:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pF1CH-0005pV-SW; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::a30; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa30.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Jan 2023 23:04:55 -0000 On Fri, Dec 30, 2022 at 12:26 PM ~elta wrote: > > From: Dongxue Zhang > > Should be cpu->cfg.elen in range [8, 64]. > > Signed-off-by: Dongxue Zhang > Reviewed-by: LIU Zhiwei > Message-ID: > Reviewed-by: Frank Chang > Message-ID: Reviewed-by: Alistair Francis Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6fe176e483..5dc51f7912 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -872,7 +872,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > "Vector extension ELEN must be power of 2"); > return; > } > - if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { > + if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { > error_setg(errp, > "Vector extension implementation only supports ELEN " > "in the range [8, 64]"); > -- > 2.34.5 From MAILER-DAEMON Tue Jan 10 02:18:06 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pF8ta-0006sI-7b for mharc-qemu-riscv@gnu.org; Tue, 10 Jan 2023 02:18:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pF8tY-0006q0-0f; Tue, 10 Jan 2023 02:18:04 -0500 Received: from wout5-smtp.messagingengine.com ([64.147.123.21]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pF8tW-0003MF-ER; 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Tue, 10 Jan 2023 02:17:57 -0500 (EST) From: Klaus Jensen To: Peter Maydell , qemu-devel@nongnu.org Cc: Keith Busch , qemu-block@nongnu.org, Klaus Jensen , Klaus Jensen , qemu-stable@nongnu.org, qemu-riscv@nongnu.org, Guenter Roeck Subject: [PULL 4/4] hw/nvme: fix missing cq eventidx update Date: Tue, 10 Jan 2023 08:17:43 +0100 Message-Id: <20230110071743.63507-5-its@irrelevant.dk> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230110071743.63507-1-its@irrelevant.dk> References: <20230110071743.63507-1-its@irrelevant.dk> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1414; i=k.jensen@samsung.com; h=from:subject; bh=ZXD346KYWBQ1ppNzRS48H9du8tV5U4eKh3aFsjFnjSA=; b=owJ4nAFtAZL+kA0DAAoBTeGvMW1PDekByyZiAGO9EReoCgLaoNslR0/8Se/AFY4fl03KSFATsS2D lji6oaQEz4kBMwQAAQoAHRYhBFIoM6p14tzmokdmwE3hrzFtTw3pBQJjvREXAAoJEE3hrzFtTw3pNS 0H/jLgaSBTm97lD63+sIoKrXMJAssZ4FI9YP7QkOYjerL5xyn1uyw5izNd5aGHq6F+CoupCf36ScFY htWTK03TM6Dw8ZpSMH2vHMxoYcXTJP5PFD2Ku6uLEpjHRoA1ksUxv0o4q9nOh2plBT4CV0MFx8jtao cFpSRcUgrueB3S6ZIc9XjhExjVbQoMtaKCiCf7RrUYpY2I4a+jgbrGk6s7Y8okTifAGqQI7cF51D6a UH4HrkIojdVk/RhHmV9f7HbxcjKcfD5Ui9n9sNkSbhUQGu45HsOJAmHR2JJzkoB7qbzYE5QMjG2FJq rYqeES6glieAlBrwEH46Ra4oNgKum2zM+1wabU X-Developer-Key: i=k.jensen@samsung.com; a=openpgp; fpr=DDCA4D9C9EF931CC3468427263D56FC5E55DA838 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=64.147.123.21; envelope-from=its@irrelevant.dk; helo=wout5-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 07:18:04 -0000 From: Klaus Jensen Prior to reading the shadow doorbell cq head, we have to update the eventidx. Otherwise, we risk that the driver will skip an mmio doorbell write. This happens on riscv64, as reported by Guenter. Adding the missing update to the cq eventidx fixes the issue. Fixes: 3f7fe8de3d49 ("hw/nvme: Implement shadow doorbell buffer support") Cc: qemu-stable@nongnu.org Cc: qemu-riscv@nongnu.org Reported-by: Guenter Roeck Reviewed-by: Keith Busch Signed-off-by: Klaus Jensen --- hw/nvme/ctrl.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 28e02ec7baa6..226480033771 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -1334,6 +1334,15 @@ static inline void nvme_blk_write(BlockBackend *blk, int64_t offset, } } +static void nvme_update_cq_eventidx(const NvmeCQueue *cq) +{ + uint32_t v = cpu_to_le32(cq->head); + + trace_pci_nvme_update_cq_eventidx(cq->cqid, cq->head); + + pci_dma_write(PCI_DEVICE(cq->ctrl), cq->ei_addr, &v, sizeof(v)); +} + static void nvme_update_cq_head(NvmeCQueue *cq) { uint32_t v; @@ -1358,6 +1367,7 @@ static void nvme_post_cqes(void *opaque) hwaddr addr; if (n->dbbuf_enabled) { + nvme_update_cq_eventidx(cq); nvme_update_cq_head(cq); } -- 2.39.0 From MAILER-DAEMON Tue Jan 10 06:43:39 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFD2Z-0004t5-BH for mharc-qemu-riscv@gnu.org; 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Tue, 10 Jan 2023 03:43:33 -0800 (PST) Message-ID: <1adba771-6632-4f68-d72f-4389f9ce7012@ventanamicro.com> Date: Tue, 10 Jan 2023 08:43:29 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH v5 10/11] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() To: Bin Meng Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng , Palmer Dabbelt References: <20230102115241.25733-1-dbarboza@ventanamicro.com> <20230102115241.25733-11-dbarboza@ventanamicro.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 11:43:38 -0000 On 1/8/23 00:33, Bin Meng wrote: > On Mon, Jan 2, 2023 at 7:55 PM Daniel Henrique Barboza > wrote: >> The microchip_icicle_kit, sifive_u, spike and virt boards are now doing >> the same steps when '-kernel' is used: >> >> - execute load_kernel() >> - load init_rd() >> - write kernel_cmdline >> >> Let's fold everything inside riscv_load_kernel() to avoid code >> repetition. To not change the behavior of boards that aren't calling >> riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and > typo: should be riscv_load_initrd() > >> allow these boards to opt out from initrd loading. >> >> Cc: Palmer Dabbelt >> Signed-off-by: Daniel Henrique Barboza >> --- >> hw/riscv/boot.c | 22 +++++++++++++++++++--- >> hw/riscv/microchip_pfsoc.c | 12 ++---------- >> hw/riscv/opentitan.c | 2 +- >> hw/riscv/sifive_e.c | 3 ++- >> hw/riscv/sifive_u.c | 12 ++---------- >> hw/riscv/spike.c | 11 +---------- >> hw/riscv/virt.c | 12 ++---------- >> include/hw/riscv/boot.h | 1 + >> 8 files changed, 30 insertions(+), 45 deletions(-) >> > Otherwise, > Reviewed-by: Bin Meng Thanks! Alistair, let me know if you want me to send another version with the commit message typo fixed. I might as well take the change to rebase it with riscv-to-apply.next. Daniel From MAILER-DAEMON Tue Jan 10 15:14:26 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFL0r-0003RB-Sq for mharc-qemu-riscv@gnu.org; Tue, 10 Jan 2023 15:14:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFL0m-0003Kk-6x for qemu-riscv@nongnu.org; Tue, 10 Jan 2023 15:14:21 -0500 Received: from mail-oi1-x230.google.com ([2607:f8b0:4864:20::230]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFL0k-0000pn-9E for qemu-riscv@nongnu.org; Tue, 10 Jan 2023 15:14:19 -0500 Received: by mail-oi1-x230.google.com with SMTP id r132so509607oif.10 for ; Tue, 10 Jan 2023 12:14:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W3FF41oQMn8zqiEm/hd7dm9Rda9j4Id6q5Oa/vMVqWY=; b=OBA5gO5E1wZY68VhKDrQ4kYaYuRWh9iF/gE1P1erQJ01dCQfUIX+JXK6eiF3KvMl2Q iGKXVYZLip1t5RvqjNJ7NxwrGUPA8gS/nlcJ1PiuoL6oLiAARBliErwjauyLu6SRdh3h Vdc1UbucqQOfW12vELO3xcENI0Rvsd4kNbzMXl6vKGJS3cMKWA0xD2OdeIVc4Z759jmC 8wdhmAT5Cs9Isf0LizYKfoLDNIq1As91CCQBDXtjxnjga7dAy0qVe5aSeuztKejhA/wG 6J4Pr0x2ujXKQXnnzBAY1KJN5Il4/pnyt7qKiKuinJ97VFF4YqbRLIXIlTW7jgCG5sfr RlVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W3FF41oQMn8zqiEm/hd7dm9Rda9j4Id6q5Oa/vMVqWY=; b=kfPpJ3hHkXOFHsUXNdLDbHbeBwn94lj5HmjeHkVgR1pvByeWHo6fB7oPaXBV0RjJOe IUW3FITAy2HfQvf/+ja+JupD7qaIv7zWY+sj3laU17jAU6ckRInXmWFs4y+mIF4Cosbu rC/9kiFcd97Gts02Ph9EndyskmSzlysP+x0kyyPjK3uOhGXAGYAH8unWBL2ZEueXgruF jzmtwEVxfZKUQQe9ZWko67Ky8Qq6n7cOaORfYH7YjdiN2iT2fy+VBKJDjb7GV+pYthwL 9d/4ViZamdGHxTlLUf/oBFBb4RfpVIblhN4zlE+ugEFfLQWPMdp7vZ67cQYJbF3yAdaj bung== X-Gm-Message-State: AFqh2kp+q9vDiEqopnBOKEKyWLLoHwFzgMYbw11b3zFehJ6Bj7KYL3Ce dNmPsvGsbApvipMRNCqi0vat/riFJuk1+2ZWfFI= X-Google-Smtp-Source: AMrXdXuh65erJv2FgYlPE7mBVJ7maNxnTaGqo41o+Jr32CeWBdvSAT00420XU4ItGrlW2i/jrh89Vw== X-Received: by 2002:a05:6808:144c:b0:363:acf6:7843 with SMTP id x12-20020a056808144c00b00363acf67843mr27381799oiv.27.1673381654144; Tue, 10 Jan 2023 12:14:14 -0800 (PST) Received: from grind.. ([152.250.93.24]) by smtp.gmail.com with ESMTPSA id l21-20020a9d7a95000000b0067c87f23476sm6453978otn.57.2023.01.10.12.14.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 12:14:13 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, richard.henderson@linaro.org, Daniel Henrique Barboza Subject: [PATCH 1/2] target/riscv/cpu: set cpu->cfg in register_cpu_props() Date: Tue, 10 Jan 2023 17:14:04 -0300 Message-Id: <20230110201405.247785-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230110201405.247785-1-dbarboza@ventanamicro.com> References: <20230110201405.247785-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 20:14:21 -0000 There is an informal contract between the cpu_init() functions and riscv_cpu_realize(): if cpu->env.misa_ext is zero, assume that the default settings were loaded via register_cpu_props() and do validations to set env.misa_ext. If it's not zero, skip this whole process and assume that the board somehow did everything. At this moment, all SiFive CPUs are setting a non-zero misa_ext during their cpu_init() and skipping a good chunk of riscv_cpu_realize(). This causes problems when the code being skipped in riscv_cpu_realize() contains fixes or assumptions that affects all CPUs, meaning that SiFive CPUs are missing out. To allow this code to not be skipped anymore, all the cpu->cfg.ext_* attributes needs to be set during cpu_init() time. At this moment this is being done in register_cpu_props(). The SiFive oards are setting their own extensions during cpu_init() though, meaning that they don't want all the defaults from register_cpu_props(). Let's move the contract between *_cpu_init() and riscv_cpu_realize() to register_cpu_props(). Inside this function we'll check if cpu->env.misa_ext was set and, if that's the case, set all relevant cpu->cfg.ext_* attributes, and only that. Leave the 'misa_ext' = 0 case as is today, i.e. loading all the defaults from riscv_cpu_extensions[]. register_cpu_props() can then be called by all the cpu_init() functions, including the SiFive ones. This will make all CPUs behave more in line with that riscv_cpu_realize() expects. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 40 ++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 4 ++++ 2 files changed, 44 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ee3659cc7e..b8c1edb7c2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -262,6 +262,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); } @@ -271,6 +272,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; } @@ -305,6 +307,7 @@ static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); } @@ -314,6 +317,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; } @@ -324,6 +328,7 @@ static void rv32_ibex_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.mmu = false; cpu->cfg.epmp = true; @@ -335,6 +340,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; } @@ -1139,10 +1145,44 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_END_OF_LIST(), }; +/* + * Register CPU props based on env.misa_ext. If a non-zero + * value was set, register only the required cpu->cfg.ext_* + * properties and leave. env.misa_ext = 0 means that we want + * all the default properties to be registered. + */ static void register_cpu_props(DeviceState *dev) { + RISCVCPU *cpu = RISCV_CPU(OBJECT(dev)); + uint32_t misa_ext = cpu->env.misa_ext; Property *prop; + /* + * If misa_ext is not zero, set cfg properties now to + * allow them to be read during riscv_cpu_realize() + * later on. + */ + if (cpu->env.misa_ext != 0) { + cpu->cfg.ext_i = misa_ext & RVI; + cpu->cfg.ext_e = misa_ext & RVE; + cpu->cfg.ext_m = misa_ext & RVM; + cpu->cfg.ext_a = misa_ext & RVA; + cpu->cfg.ext_f = misa_ext & RVF; + cpu->cfg.ext_d = misa_ext & RVD; + cpu->cfg.ext_v = misa_ext & RVV; + cpu->cfg.ext_c = misa_ext & RVC; + cpu->cfg.ext_s = misa_ext & RVS; + cpu->cfg.ext_u = misa_ext & RVU; + cpu->cfg.ext_h = misa_ext & RVH; + cpu->cfg.ext_j = misa_ext & RVJ; + + /* + * We don't want to set the default riscv_cpu_extensions + * in this case. + */ + return; + } + for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0158932dc5..798bd081de 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -63,6 +63,10 @@ #define RV(x) ((target_ulong)1 << (x - 'A')) +/* + * Consider updating register_cpu_props() when adding + * new MISA bits here. + */ #define RVI RV('I') #define RVE RV('E') /* E and I are mutually exclusive */ #define RVM RV('M') -- 2.39.0 From MAILER-DAEMON Tue Jan 10 15:14:26 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFL0s-0003RG-1O for mharc-qemu-riscv@gnu.org; Tue, 10 Jan 2023 15:14:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFL0m-0003Ko-Br for qemu-riscv@nongnu.org; Tue, 10 Jan 2023 15:14:20 -0500 Received: from mail-oi1-x244.google.com ([2607:f8b0:4864:20::244]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFL0k-0000pO-8O for qemu-riscv@nongnu.org; Tue, 10 Jan 2023 15:14:19 -0500 Received: by mail-oi1-x244.google.com with SMTP id n8so11103730oih.0 for ; Tue, 10 Jan 2023 12:14:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=gGGv7nNdgIZNrOUX9rzYbYN2AmE+oL6fKFxAH29OxDU=; b=Rc+0BFt3lvQDMKzXc4Sgj20kuc7k1ImZXQnDD9gxFSEKcDUpEW5mXrIygy638zJvMG nU4bH5YYSMxaG4zdO4o1J4wklvREiA7YwB54v5t3MJ4m1VEiFi7AOvj0G3nAVWAWSjdI LrNAh0IarWDC0rt+/Oh5h/pfdPSNfQrq9JLCPCjbWpQgDhsr8kPghpL8gc+x+ukbJLln bd1uJi+QoKEDw08yBIeNtg3WrmuYprGWo6wkqNXEBSdnAPSDZfG1Nt+gWf3iQLlg6Dnp 2omCXkVsSo7dkAvWduCxjpuV0kJajscdUIFOe40uWBEe0xcUHJ3+11UG4iCJvcE1oI/M fo/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=gGGv7nNdgIZNrOUX9rzYbYN2AmE+oL6fKFxAH29OxDU=; b=nIvNf1vnft/4CMwTNCjAMQSY+LpF9i2R2hdDx+tcRz/RJDD6XiHTGSCF+qgsLqxmUo MmU7YNWfh1QyT0h71yl9DdwPqZN/rvm53/qp2yOvLIi04kEDNsUC3P8UL5AhB4RtuiQ1 qrPZzTVTiB+6WY+/5/K3sq3EBjEUQoRFfObsSoS5iAEb66D3d0OOI9AXLvnp7DZWnYCN 4uzsK2SmUSxPrULHlGvT1KkCU7cTaumaCptrkpam0o/dT+KjCJiO/VoflLuSlqyt4zlT F/5kNumKyTSu31tyJVzMklvRGEntvcKEd6FCbfD65Oae7s25hiaQj2eQGucq2Ex6kkps PSOw== X-Gm-Message-State: AFqh2kpV6ya08p9w/WWVx12JxVUZw791U7BYDXYMOVGy6ocujwk2uXM4 BrvP5kRRUb6zgvuTsrlV9ZE0Pw== X-Google-Smtp-Source: AMrXdXsWFPZ54cE583B7Tu/m+tOIEeZ66LotvPMRC69a+CMIJeCicrphYxkgodDU6O8eUBRijVOLWQ== X-Received: by 2002:aca:1111:0:b0:364:5c52:9923 with SMTP id 17-20020aca1111000000b003645c529923mr1481850oir.30.1673381651597; Tue, 10 Jan 2023 12:14:11 -0800 (PST) Received: from grind.. ([152.250.93.24]) by smtp.gmail.com with ESMTPSA id l21-20020a9d7a95000000b0067c87f23476sm6453978otn.57.2023.01.10.12.14.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 12:14:11 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, richard.henderson@linaro.org, Daniel Henrique Barboza Subject: [PATCH 0/2] target/riscv/cpu: fix sifive_u 32/64bits boot in riscv-to-apply.next Date: Tue, 10 Jan 2023 17:14:03 -0300 Message-Id: <20230110201405.247785-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::244; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x244.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 20:14:21 -0000 Hi, I found this bug when testing my avocado changes in riscv-to-apply.next. The sifive_u board, both 32 and 64 bits, stopped booting OpenSBI. The guest hangs indefinitely. Git bisect points that this patch broke things: 8c3f35d25e7e98655c609b6c1e9f103b9240f8f8 is the first bad commit commit 8c3f35d25e7e98655c609b6c1e9f103b9240f8f8 Author: Weiwei Li Date: Wed Dec 28 14:20:21 2022 +0800 target/riscv: add support for Zca extension Modify the check for C extension to Zca (C implies Zca) (https://github.com/alistair23/qemu/commit/8c3f35d25e7e98655c609b6c1e9f103b9240f8f8) But this patch per se isn't doing anything wrong. The root of the problem is that this patch makes assumptions based on the previous patch: commit a2b409aa6cadc1ed9715e1ab916ddd3dade0ba85 Author: Weiwei Li Date: Wed Dec 28 14:20:20 2022 +0800 target/riscv: add cfg properties for Zc* extension (https://github.com/alistair23/qemu/commit/a2b409aa6cadc1ed9715e1ab916ddd3dade0ba85) Which added a lot of logic and assumptions that are being skipped by all the SiFive boards because, during riscv_cpu_realize(), we have this code: /* If only MISA_EXT is unset for misa, then set it from properties */ if (env->misa_ext == 0) { uint32_t ext = 0; (...) } In short, we have a lot of code that are being skipped by all SiFive CPUs because these CPUs are setting a non-zero value in set_misa() in their respective cpu_init() functions. It's possible to just hack in and fix the SiFive problem in isolate, but I believe we can do better and allow all riscv_cpu_realize() to be executed for all CPUs, regardless of what they've done during their cpu_init(). Daniel Henrique Barboza (2): target/riscv/cpu: set cpu->cfg in register_cpu_props() target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() target/riscv/cpu.c | 525 +++++++++++++++++++++++++-------------------- target/riscv/cpu.h | 4 + 2 files changed, 292 insertions(+), 237 deletions(-) -- 2.39.0 From MAILER-DAEMON Tue Jan 10 15:14:32 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFL0y-0003Sx-GD for mharc-qemu-riscv@gnu.org; Tue, 10 Jan 2023 15:14:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFL0o-0003OD-5G for qemu-riscv@nongnu.org; Tue, 10 Jan 2023 15:14:23 -0500 Received: from mail-ot1-x32c.google.com ([2607:f8b0:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFL0k-0000q5-8b for qemu-riscv@nongnu.org; Tue, 10 Jan 2023 15:14:21 -0500 Received: by mail-ot1-x32c.google.com with SMTP id k7-20020a056830168700b0067832816190so7663419otr.1 for ; Tue, 10 Jan 2023 12:14:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EUfZtab7ItHi76p6G7etytF2gLMXOVfh6cZM4zDyA+o=; b=EVAqj53DJCHmN+azr7GDjAh+IWeksVHmwJR+hgUdEf88ikQVV6CW9ssQzjW40XKqgf xCsB0KdsG5d4xUVfg3MO0LYEXbj05xLSMzrHpm2131ioCAonsUNcbabJCE1EnG6kz115 cUgKErY0ypktYIE8glq93/Yaih+f9HhMYsghA0ge94+IErrZA+8BpejYI9LoMzjU1nUf bTsn+ADr16TYPeQxrOg7umAJYtSLEhuFId+fJl8fyJdH7Vq1KfiQvQ4y09Xd4BHMxJU0 zDEf8oTh+cSd0qwvvF+F/+KzBcIhtDu6wBEvoL2O/yG3t3hpqyFy7ig+8RVZsNyNcIK5 /1dw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EUfZtab7ItHi76p6G7etytF2gLMXOVfh6cZM4zDyA+o=; b=Xdk0DGWknUa0WE2FfPwgFv26GHJ3CyVSLe8gYeuVVWOlgwVEfrZoOZvC8afr91eaj0 PzdvgU0fTVpdZ0MK/diEIxWkK4pNq5VM4pXXPZz6MuzLl+TNYZzjJSeGRCTcAe8keVrJ fjhZ1qpK2yKRVRBKxQBOX22LFFxashELXBUCjv1OXrKSmJPXQhwT7ol4rS04hK4HoJyS bLgV4w7mzbhsoTughqvGXt956G17OX4yIbBBTJvFVI6WCwj+PKno14nKH9v/dNoGx54x TBC5rbDLSEpvF8a+qeOYzYwlzhUsAQvZhP4i4HsJ/u855NZwml1MxgnbitP0bfYUQTuw zQjw== X-Gm-Message-State: AFqh2kq07H201A/DdgfnCrF4PSpUTNfy/xb9qMDrdldUpah5opi2g3fy vM0pdyrLLnYZg/RzDPRFyxDR+A== X-Google-Smtp-Source: AMrXdXvWFnFYRTcT8IvBX+R578K2qTe9KKbtdGKXgtbtP7X78kW4Vd1aGjqik8S3omTeAKmCGolvZw== X-Received: by 2002:a9d:4685:0:b0:66e:c096:126c with SMTP id z5-20020a9d4685000000b0066ec096126cmr36461010ote.29.1673381656770; Tue, 10 Jan 2023 12:14:16 -0800 (PST) Received: from grind.. ([152.250.93.24]) by smtp.gmail.com with ESMTPSA id l21-20020a9d7a95000000b0067c87f23476sm6453978otn.57.2023.01.10.12.14.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 12:14:16 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, richard.henderson@linaro.org, Daniel Henrique Barboza Subject: [PATCH 2/2] target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() Date: Tue, 10 Jan 2023 17:14:05 -0300 Message-Id: <20230110201405.247785-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230110201405.247785-1-dbarboza@ventanamicro.com> References: <20230110201405.247785-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 20:14:25 -0000 All RISCV CPUs are setting cpu->cfg during their cpu_init() functions, meaning that there's no reason to skip all the misa validation and setup if misa_ext was set beforehand - especially since we're setting an updated value in set_misa() in the end. Put this code chunk into a new riscv_cpu_validate_set_extensions() helper and always execute it regardless of what the board set in env->misa_ext. This will put more responsibility in how each board is going to init their attributes and extensions if they're not using the defaults. It'll also allow realize() to do its job looking only at the extensions enabled per se, not corner cases that some CPUs might have, and we won't have to change multiple code paths to fix or change how extensions work. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 485 +++++++++++++++++++++++---------------------- 1 file changed, 248 insertions(+), 237 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b8c1edb7c2..33ed59a1b6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -631,6 +631,250 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) } } +/* + * Check consistency between chosen extensions while setting + * cpu->cfg accordingly, doing a set_misa() in the end. + */ +static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env = &cpu->env; + uint32_t ext = 0; + + /* Do some ISA extension error checking */ + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && + cpu->cfg.ext_a && cpu->cfg.ext_f && + cpu->cfg.ext_d && + cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { + warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); + cpu->cfg.ext_i = true; + cpu->cfg.ext_m = true; + cpu->cfg.ext_a = true; + cpu->cfg.ext_f = true; + cpu->cfg.ext_d = true; + cpu->cfg.ext_icsr = true; + cpu->cfg.ext_ifencei = true; + } + + if (cpu->cfg.ext_i && cpu->cfg.ext_e) { + error_setg(errp, + "I and E extensions are incompatible"); + return; + } + + if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { + error_setg(errp, + "Either I or E extension must be set"); + return; + } + + if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { + error_setg(errp, + "Setting S extension without U extension is illegal"); + return; + } + + if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { + error_setg(errp, + "H depends on an I base integer ISA with 32 x registers"); + return; + } + + if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { + error_setg(errp, "H extension implicitly requires S-mode"); + return; + } + + if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { + error_setg(errp, "F extension requires Zicsr"); + return; + } + + if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { + error_setg(errp, "Zawrs extension requires A extension"); + return; + } + + if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { + error_setg(errp, "Zfh/Zfhmin extensions require F extension"); + return; + } + + if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { + error_setg(errp, "D extension requires F extension"); + return; + } + + if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { + error_setg(errp, "V extension requires D extension"); + return; + } + + if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { + error_setg(errp, "Zve32f/Zve64f extensions require F extension"); + return; + } + + /* Set the ISA extensions, checks should have happened above */ + if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || + cpu->cfg.ext_zhinxmin) { + cpu->cfg.ext_zfinx = true; + } + + if (cpu->cfg.ext_zfinx) { + if (!cpu->cfg.ext_icsr) { + error_setg(errp, "Zfinx extension requires Zicsr"); + return; + } + if (cpu->cfg.ext_f) { + error_setg(errp, + "Zfinx cannot be supported together with F extension"); + return; + } + } + + if (cpu->cfg.ext_c) { + cpu->cfg.ext_zca = true; + if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) { + cpu->cfg.ext_zcf = true; + } + if (cpu->cfg.ext_d) { + cpu->cfg.ext_zcd = true; + } + } + + if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { + error_setg(errp, "Zcf extension is only relevant to RV32"); + return; + } + + if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) { + error_setg(errp, "Zcf extension requires F extension"); + return; + } + + if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) { + error_setg(errp, "Zcd extension requires D extension"); + return; + } + + if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || + cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { + error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " + "extension"); + return; + } + + if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { + error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " + "Zcd extension"); + return; + } + + if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { + error_setg(errp, "Zcmt extension requires Zicsr extension"); + return; + } + + if (cpu->cfg.ext_zk) { + cpu->cfg.ext_zkn = true; + cpu->cfg.ext_zkr = true; + cpu->cfg.ext_zkt = true; + } + + if (cpu->cfg.ext_zkn) { + cpu->cfg.ext_zbkb = true; + cpu->cfg.ext_zbkc = true; + cpu->cfg.ext_zbkx = true; + cpu->cfg.ext_zkne = true; + cpu->cfg.ext_zknd = true; + cpu->cfg.ext_zknh = true; + } + + if (cpu->cfg.ext_zks) { + cpu->cfg.ext_zbkb = true; + cpu->cfg.ext_zbkc = true; + cpu->cfg.ext_zbkx = true; + cpu->cfg.ext_zksed = true; + cpu->cfg.ext_zksh = true; + } + + if (cpu->cfg.ext_i) { + ext |= RVI; + } + if (cpu->cfg.ext_e) { + ext |= RVE; + } + if (cpu->cfg.ext_m) { + ext |= RVM; + } + if (cpu->cfg.ext_a) { + ext |= RVA; + } + if (cpu->cfg.ext_f) { + ext |= RVF; + } + if (cpu->cfg.ext_d) { + ext |= RVD; + } + if (cpu->cfg.ext_c) { + ext |= RVC; + } + if (cpu->cfg.ext_s) { + ext |= RVS; + } + if (cpu->cfg.ext_u) { + ext |= RVU; + } + if (cpu->cfg.ext_h) { + ext |= RVH; + } + if (cpu->cfg.ext_v) { + int vext_version = VEXT_VERSION_1_00_0; + ext |= RVV; + if (!is_power_of_2(cpu->cfg.vlen)) { + error_setg(errp, + "Vector extension VLEN must be power of 2"); + return; + } + if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { + error_setg(errp, + "Vector extension implementation only supports VLEN " + "in the range [128, %d]", RV_VLEN_MAX); + return; + } + if (!is_power_of_2(cpu->cfg.elen)) { + error_setg(errp, + "Vector extension ELEN must be power of 2"); + return; + } + if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { + error_setg(errp, + "Vector extension implementation only supports ELEN " + "in the range [8, 64]"); + return; + } + if (cpu->cfg.vext_spec) { + if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { + vext_version = VEXT_VERSION_1_00_0; + } else { + error_setg(errp, + "Unsupported vector spec version '%s'", + cpu->cfg.vext_spec); + return; + } + } else { + qemu_log("vector version is not specified, " + "use the default value v1.0\n"); + } + set_vext_version(env, vext_version); + } + if (cpu->cfg.ext_j) { + ext |= RVJ; + } + + set_misa(env, env->misa_mxl, ext); +} + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -726,243 +970,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } assert(env->misa_mxl_max == env->misa_mxl); - /* If only MISA_EXT is unset for misa, then set it from properties */ - if (env->misa_ext == 0) { - uint32_t ext = 0; - - /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && - cpu->cfg.ext_a && cpu->cfg.ext_f && - cpu->cfg.ext_d && - cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { - warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_i = true; - cpu->cfg.ext_m = true; - cpu->cfg.ext_a = true; - cpu->cfg.ext_f = true; - cpu->cfg.ext_d = true; - cpu->cfg.ext_icsr = true; - cpu->cfg.ext_ifencei = true; - } - - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { - error_setg(errp, - "I and E extensions are incompatible"); - return; - } - - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { - error_setg(errp, - "Either I or E extension must be set"); - return; - } - - if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { - error_setg(errp, - "Setting S extension without U extension is illegal"); - return; - } - - if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { - error_setg(errp, - "H depends on an I base integer ISA with 32 x registers"); - return; - } - - if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { - error_setg(errp, "H extension implicitly requires S-mode"); - return; - } - - if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { - error_setg(errp, "F extension requires Zicsr"); - return; - } - - if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { - error_setg(errp, "Zawrs extension requires A extension"); - return; - } - - if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { - error_setg(errp, "Zfh/Zfhmin extensions require F extension"); - return; - } - - if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { - error_setg(errp, "D extension requires F extension"); - return; - } - - if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { - error_setg(errp, "V extension requires D extension"); - return; - } - - if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { - error_setg(errp, "Zve32f/Zve64f extensions require F extension"); - return; - } - - /* Set the ISA extensions, checks should have happened above */ - if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || - cpu->cfg.ext_zhinxmin) { - cpu->cfg.ext_zfinx = true; - } - - if (cpu->cfg.ext_zfinx) { - if (!cpu->cfg.ext_icsr) { - error_setg(errp, "Zfinx extension requires Zicsr"); - return; - } - if (cpu->cfg.ext_f) { - error_setg(errp, - "Zfinx cannot be supported together with F extension"); - return; - } - } - - if (cpu->cfg.ext_c) { - cpu->cfg.ext_zca = true; - if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) { - cpu->cfg.ext_zcf = true; - } - if (cpu->cfg.ext_d) { - cpu->cfg.ext_zcd = true; - } - } - - if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { - error_setg(errp, "Zcf extension is only relevant to RV32"); - return; - } - - if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) { - error_setg(errp, "Zcf extension requires F extension"); - return; - } - - if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) { - error_setg(errp, "Zcd extension requires D extension"); - return; - } - - if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || - cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { - error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " - "extension"); - return; - } - - if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { - error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " - "Zcd extension"); - return; - } - - if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { - error_setg(errp, "Zcmt extension requires Zicsr extension"); - return; - } - - if (cpu->cfg.ext_zk) { - cpu->cfg.ext_zkn = true; - cpu->cfg.ext_zkr = true; - cpu->cfg.ext_zkt = true; - } - - if (cpu->cfg.ext_zkn) { - cpu->cfg.ext_zbkb = true; - cpu->cfg.ext_zbkc = true; - cpu->cfg.ext_zbkx = true; - cpu->cfg.ext_zkne = true; - cpu->cfg.ext_zknd = true; - cpu->cfg.ext_zknh = true; - } - - if (cpu->cfg.ext_zks) { - cpu->cfg.ext_zbkb = true; - cpu->cfg.ext_zbkc = true; - cpu->cfg.ext_zbkx = true; - cpu->cfg.ext_zksed = true; - cpu->cfg.ext_zksh = true; - } - - if (cpu->cfg.ext_i) { - ext |= RVI; - } - if (cpu->cfg.ext_e) { - ext |= RVE; - } - if (cpu->cfg.ext_m) { - ext |= RVM; - } - if (cpu->cfg.ext_a) { - ext |= RVA; - } - if (cpu->cfg.ext_f) { - ext |= RVF; - } - if (cpu->cfg.ext_d) { - ext |= RVD; - } - if (cpu->cfg.ext_c) { - ext |= RVC; - } - if (cpu->cfg.ext_s) { - ext |= RVS; - } - if (cpu->cfg.ext_u) { - ext |= RVU; - } - if (cpu->cfg.ext_h) { - ext |= RVH; - } - if (cpu->cfg.ext_v) { - int vext_version = VEXT_VERSION_1_00_0; - ext |= RVV; - if (!is_power_of_2(cpu->cfg.vlen)) { - error_setg(errp, - "Vector extension VLEN must be power of 2"); - return; - } - if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { - error_setg(errp, - "Vector extension implementation only supports VLEN " - "in the range [128, %d]", RV_VLEN_MAX); - return; - } - if (!is_power_of_2(cpu->cfg.elen)) { - error_setg(errp, - "Vector extension ELEN must be power of 2"); - return; - } - if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { - error_setg(errp, - "Vector extension implementation only supports ELEN " - "in the range [8, 64]"); - return; - } - if (cpu->cfg.vext_spec) { - if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { - vext_version = VEXT_VERSION_1_00_0; - } else { - error_setg(errp, - "Unsupported vector spec version '%s'", - cpu->cfg.vext_spec); - return; - } - } else { - qemu_log("vector version is not specified, " - "use the default value v1.0\n"); - } - set_vext_version(env, vext_version); - } - if (cpu->cfg.ext_j) { - ext |= RVJ; - } - - set_misa(env, env->misa_mxl, ext); + riscv_cpu_validate_set_extensions(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; } #ifndef CONFIG_USER_ONLY -- 2.39.0 From MAILER-DAEMON Tue Jan 10 15:20:49 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFL73-0006YK-RY for mharc-qemu-riscv@gnu.org; Tue, 10 Jan 2023 15:20:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFL71-0006WF-Lx for qemu-riscv@nongnu.org; Tue, 10 Jan 2023 15:20:47 -0500 Received: from mail-oa1-x44.google.com ([2001:4860:4864:20::44]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFL6z-0002IQ-R2 for qemu-riscv@nongnu.org; Tue, 10 Jan 2023 15:20:47 -0500 Received: by mail-oa1-x44.google.com with SMTP id 586e51a60fabf-1442977d77dso13353442fac.6 for ; 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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH v5 10/11] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() From: Daniel Henrique Barboza To: Bin Meng Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng , Palmer Dabbelt References: <20230102115241.25733-1-dbarboza@ventanamicro.com> <20230102115241.25733-11-dbarboza@ventanamicro.com> <1adba771-6632-4f68-d72f-4389f9ce7012@ventanamicro.com> Content-Language: en-US In-Reply-To: <1adba771-6632-4f68-d72f-4389f9ce7012@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::44; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x44.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 20:20:47 -0000 On 1/10/23 08:43, Daniel Henrique Barboza wrote: > > > On 1/8/23 00:33, Bin Meng wrote: >> On Mon, Jan 2, 2023 at 7:55 PM Daniel Henrique Barboza >> wrote: >>> The microchip_icicle_kit, sifive_u, spike and virt boards are now doing >>> the same steps when '-kernel' is used: >>> >>> - execute load_kernel() >>> - load init_rd() >>> - write kernel_cmdline >>> >>> Let's fold everything inside riscv_load_kernel() to avoid code >>> repetition. To not change the behavior of boards that aren't calling >>> riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and >> typo: should be riscv_load_initrd() >> >>> allow these boards to opt out from initrd loading. >>> >>> Cc: Palmer Dabbelt >>> Signed-off-by: Daniel Henrique Barboza >>> --- >>>   hw/riscv/boot.c            | 22 +++++++++++++++++++--- >>>   hw/riscv/microchip_pfsoc.c | 12 ++---------- >>>   hw/riscv/opentitan.c       |  2 +- >>>   hw/riscv/sifive_e.c        |  3 ++- >>>   hw/riscv/sifive_u.c        | 12 ++---------- >>>   hw/riscv/spike.c           | 11 +---------- >>>   hw/riscv/virt.c            | 12 ++---------- >>>   include/hw/riscv/boot.h    |  1 + >>>   8 files changed, 30 insertions(+), 45 deletions(-) >>> >> Otherwise, >> Reviewed-by: Bin Meng > > Thanks! > > Alistair, let me know if you want me to send another version with the commit > message typo fixed. I might as well take the change to rebase it with > riscv-to-apply.next. While rebasing these patches on top of riscv-to-apply.next, the avocado tests I've introduced here started to fail both sifive_u tests: tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv32_sifive_u: INTERRUPTED: Test interrupted by SIGTERM\nRunner error occurred: ... (5.07 s)  (09/18) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv64_sifive_u: INTERRUPTED: Test interrupted by SIGTERM\nRunner error occurred: ... (5.05 s) I proposed a fix here: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02035.html I can re-send this series after we get that problem figure out. Otherwise we're going to add 2 avocado tests that are failing right from the start hehe. Thanks, Daniel > > > Daniel > From MAILER-DAEMON Tue Jan 10 16:29:59 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFMBz-0007iQ-8e for mharc-qemu-riscv@gnu.org; Tue, 10 Jan 2023 16:29:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFMBx-0007hR-Pe for qemu-riscv@nongnu.org; Tue, 10 Jan 2023 16:29:57 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFMBs-0006fb-HX for qemu-riscv@nongnu.org; Tue, 10 Jan 2023 16:29:57 -0500 Received: by mail-wr1-x434.google.com with SMTP id r2so13151553wrv.7 for ; Tue, 10 Jan 2023 13:29:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=W6wbWAaLwPWIlIyedxb4xDOOJaJOFE6u3k4WgWE5z1Q=; b=NJZgrJVezNBUk1duCF+KjTkxDbZ0B2oYgQK83ujjYQRz+WNzlUbXFUmU9NDDTsM19M goUMPU68xScavEmrKhM2zb28Z0Uwxk8Ks3kUNckShLpzHgDUlR5ymQe1OZjxxTFSGJfy 0mIRfytO1Hzan3AA8Tb7BY3X2jb4Bn5qRPiuxYu8Q2WvtI4lbPS4ceMTfBPmj03uewwZ DDGHmMz6s2PJdA2G8U1VcDFgyfp5CE0R5WzFgg1GOpY1yXdYtJPJVAryA7QY3qB9bevb mGS1tIJTmqUB7pSkXaebkhgeUEgr/3nV7vBsCwGWP/6JsZVQNg8uLSUdjUPpO9cHHeoC RSng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=W6wbWAaLwPWIlIyedxb4xDOOJaJOFE6u3k4WgWE5z1Q=; b=Rej/LZqo/JQNj+IZTxcxRxaOHsdAqXto6bz115b4amNx5DgOJsJFDmwXPQLRp70HWZ chM6ob7wCqGPDSVwwCJadYwCyOrvtOrt3KcOwU/As4VsT/B3q1mMzfTSfuSnZdOateYh Lh+oG3mC0jBu6iPFtdRqVeFGSojfYzaCF80G+VIdhgKQejJmmx85lGoaJF0sS/Sde+LG 5+hRfhmW1yehR4GPlx92vbQdBCb7r0M7EiuKT0Td1hSal8owaeykFEIVayDPDwdHthCh hZ+/2jdak9a2Vp80FCZnUkRgIl4XMmCk99TdWftf3zANYsbsUGb9i2XWSmd5J+hDeXmt U4Eg== X-Gm-Message-State: AFqh2kpKXzeW/z4g2JYgbzEQoeTcgWci2lNIMwG7Kp/uRGX0u3s6+gOy wQXSkwnhE4jFpTgrPOk6NK02Fw== X-Google-Smtp-Source: AMrXdXsUkev5VAsuQo1OfOr+0irzTxLF6bwT0XZWW8EQ21bjlIyp+8HkVhItOJf6wPYBdCkZvWs46A== X-Received: by 2002:a5d:664e:0:b0:2bc:7ec3:8a8 with SMTP id f14-20020a5d664e000000b002bc7ec308a8mr5077500wrw.44.1673386190595; Tue, 10 Jan 2023 13:29:50 -0800 (PST) Received: from localhost.localdomain ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id m7-20020adffe47000000b002b880b6ef19sm12096616wrs.66.2023.01.10.13.29.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Jan 2023 13:29:50 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Peter Maydell , qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= , ale@rev.ng, qemu-riscv@nongnu.org, xen-devel@lists.xenproject.org, Thomas Huth , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH] bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx Date: Tue, 10 Jan 2023 22:29:47 +0100 Message-Id: <20230110212947.34557-1-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 21:29:58 -0000 The 'hwaddr' type is defined in "exec/hwaddr.h" as: hwaddr is the type of a physical address (its size can be different from 'target_ulong'). All definitions use the 'HWADDR_' prefix, except TARGET_FMT_plx: $ fgrep define include/exec/hwaddr.h #define HWADDR_H #define HWADDR_BITS 64 #define HWADDR_MAX UINT64_MAX #define TARGET_FMT_plx "%016" PRIx64 ^^^^^^ #define HWADDR_PRId PRId64 #define HWADDR_PRIi PRIi64 #define HWADDR_PRIo PRIo64 #define HWADDR_PRIu PRIu64 #define HWADDR_PRIx PRIx64 #define HWADDR_PRIX PRIX64 Since hwaddr's size can be *different* from target_ulong, it is very confusing to read one of its format using the 'TARGET_FMT_' prefix, normally used for the target_long / target_ulong types: $ fgrep TARGET_FMT_ include/exec/cpu-defs.h #define TARGET_FMT_lx "%08x" #define TARGET_FMT_ld "%d" #define TARGET_FMT_lu "%u" #define TARGET_FMT_lx "%016" PRIx64 #define TARGET_FMT_ld "%" PRId64 #define TARGET_FMT_lu "%" PRIu64 Apparently this format was missed during commit a8170e5e97 ("Rename target_phys_addr_t to hwaddr"), so complete it by doing a bulk-rename with: $ sed -i -e s/TARGET_FMT_plx/HWADDR_FMT_plx/g $(git grep -l TARGET_FMT_plx) Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/cputlb.c | 2 +- hw/arm/strongarm.c | 24 ++++++++++++------------ hw/block/pflash_cfi01.c | 2 +- hw/char/digic-uart.c | 4 ++-- hw/char/etraxfs_ser.c | 4 ++-- hw/core/loader.c | 8 ++++---- hw/core/sysbus.c | 4 ++-- hw/display/cirrus_vga.c | 4 ++-- hw/display/g364fb.c | 4 ++-- hw/display/vga.c | 8 ++++---- hw/dma/etraxfs_dma.c | 14 +++++++------- hw/dma/pl330.c | 14 +++++++------- hw/dma/xilinx_axidma.c | 4 ++-- hw/dma/xlnx_csu_dma.c | 4 ++-- hw/i2c/mpc_i2c.c | 4 ++-- hw/i386/multiboot.c | 8 ++++---- hw/i386/xen/xen-hvm.c | 8 ++++---- hw/i386/xen/xen-mapcache.c | 16 ++++++++-------- hw/i386/xen/xen_platform.c | 4 ++-- hw/intc/arm_gicv3_dist.c | 8 ++++---- hw/intc/arm_gicv3_its.c | 14 +++++++------- hw/intc/arm_gicv3_redist.c | 8 ++++---- hw/intc/exynos4210_combiner.c | 10 +++++----- hw/misc/auxbus.c | 2 +- hw/misc/ivshmem.c | 6 +++--- hw/misc/macio/mac_dbdma.c | 4 ++-- hw/misc/mst_fpga.c | 4 ++-- hw/net/allwinner-sun8i-emac.c | 4 ++-- hw/net/allwinner_emac.c | 4 ++-- hw/net/fsl_etsec/etsec.c | 4 ++-- hw/net/fsl_etsec/rings.c | 4 ++-- hw/net/pcnet.c | 4 ++-- hw/net/rocker/rocker.c | 26 +++++++++++++------------- hw/net/rocker/rocker_desc.c | 2 +- hw/net/xilinx_axienet.c | 4 ++-- hw/net/xilinx_ethlite.c | 6 +++--- hw/pci-bridge/pci_expander_bridge.c | 2 +- hw/pci-host/bonito.c | 14 +++++++------- hw/pci-host/ppce500.c | 4 ++-- hw/pci/pci_host.c | 4 ++-- hw/ppc/ppc4xx_sdram.c | 2 +- hw/rtc/exynos4210_rtc.c | 4 ++-- hw/sh4/sh7750.c | 4 ++-- hw/ssi/xilinx_spi.c | 4 ++-- hw/ssi/xilinx_spips.c | 8 ++++---- hw/timer/digic-timer.c | 4 ++-- hw/timer/etraxfs_timer.c | 2 +- hw/timer/exynos4210_mct.c | 2 +- hw/timer/exynos4210_pwm.c | 4 ++-- hw/virtio/virtio-mmio.c | 4 ++-- hw/xen/xen_pt.c | 4 ++-- include/exec/hwaddr.h | 2 +- monitor/misc.c | 2 +- softmmu/memory.c | 18 +++++++++--------- softmmu/memory_mapping.c | 4 ++-- softmmu/physmem.c | 10 +++++----- target/i386/monitor.c | 6 +++--- target/loongarch/tlb_helper.c | 2 +- target/microblaze/op_helper.c | 2 +- target/mips/tcg/sysemu/tlb_helper.c | 2 +- target/ppc/mmu-hash32.c | 14 +++++++------- target/ppc/mmu-hash64.c | 12 ++++++------ target/ppc/mmu_common.c | 26 +++++++++++++------------- target/ppc/mmu_helper.c | 4 ++-- target/riscv/cpu_helper.c | 10 +++++----- target/riscv/monitor.c | 2 +- target/sparc/ldst_helper.c | 6 +++--- target/sparc/mmu_helper.c | 10 +++++----- target/tricore/helper.c | 2 +- 69 files changed, 227 insertions(+), 227 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 4948729917..4e040a1cb9 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1142,7 +1142,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, &xlat, &sz, full->attrs, &prot); assert(sz >= TARGET_PAGE_SIZE); - tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx + tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" HWADDR_FMT_plx " prot=%x idx=%d\n", vaddr, full->phys_addr, prot, mmu_idx); diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index 39b8f01ac4..cc73145053 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -151,7 +151,7 @@ static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset, case ICPR: return s->pending; default: - printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n", + printf("%s: Bad register offset 0x" HWADDR_FMT_plx "\n", __func__, offset); return 0; } @@ -173,7 +173,7 @@ static void strongarm_pic_mem_write(void *opaque, hwaddr offset, s->int_idle = (value & 1) ? 0 : ~0; break; default: - printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n", + printf("%s: Bad register offset 0x" HWADDR_FMT_plx "\n", __func__, offset); break; } @@ -333,7 +333,7 @@ static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr, ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / (1000 * ((s->rttr & 0xffff) + 1)); default: - printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); + printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr); return 0; } } @@ -375,7 +375,7 @@ static void strongarm_rtc_write(void *opaque, hwaddr addr, break; default: - printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); + printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr); } } @@ -581,7 +581,7 @@ static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset, return s->status; default: - printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); + printf("%s: Bad offset 0x" HWADDR_FMT_plx "\n", __func__, offset); } return 0; @@ -626,7 +626,7 @@ static void strongarm_gpio_write(void *opaque, hwaddr offset, break; default: - printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); + printf("%s: Bad offset 0x" HWADDR_FMT_plx "\n", __func__, offset); } } @@ -782,7 +782,7 @@ static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset, return s->ppfr | ~0x7f001; default: - printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); + printf("%s: Bad offset 0x" HWADDR_FMT_plx "\n", __func__, offset); } return 0; @@ -817,7 +817,7 @@ static void strongarm_ppc_write(void *opaque, hwaddr offset, break; default: - printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); + printf("%s: Bad offset 0x" HWADDR_FMT_plx "\n", __func__, offset); } } @@ -1164,7 +1164,7 @@ static uint64_t strongarm_uart_read(void *opaque, hwaddr addr, return s->utsr1; default: - printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); + printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr); return 0; } } @@ -1221,7 +1221,7 @@ static void strongarm_uart_write(void *opaque, hwaddr addr, break; default: - printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); + printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr); } } @@ -1443,7 +1443,7 @@ static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr, strongarm_ssp_fifo_update(s); return retval; default: - printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); + printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr); break; } return 0; @@ -1509,7 +1509,7 @@ static void strongarm_ssp_write(void *opaque, hwaddr addr, break; default: - printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); + printf("%s: Bad register 0x" HWADDR_FMT_plx "\n", __func__, addr); break; } } diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 0cbc2fb4cb..36d68c70f6 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -645,7 +645,7 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset, error_flash: qemu_log_mask(LOG_UNIMP, "%s: Unimplemented flash cmd sequence " - "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)" + "(offset " HWADDR_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)" "\n", __func__, offset, pfl->wcycle, pfl->cmd, value); mode_read_array: diff --git a/hw/char/digic-uart.c b/hw/char/digic-uart.c index 00e5df5517..51d4e7db52 100644 --- a/hw/char/digic-uart.c +++ b/hw/char/digic-uart.c @@ -63,7 +63,7 @@ static uint64_t digic_uart_read(void *opaque, hwaddr addr, default: qemu_log_mask(LOG_UNIMP, "digic-uart: read access to unknown register 0x" - TARGET_FMT_plx "\n", addr << 2); + HWADDR_FMT_plx "\n", addr << 2); } return ret; @@ -101,7 +101,7 @@ static void digic_uart_write(void *opaque, hwaddr addr, uint64_t value, default: qemu_log_mask(LOG_UNIMP, "digic-uart: write access to unknown register 0x" - TARGET_FMT_plx "\n", addr << 2); + HWADDR_FMT_plx "\n", addr << 2); } } diff --git a/hw/char/etraxfs_ser.c b/hw/char/etraxfs_ser.c index e8c3017724..8d6422dae4 100644 --- a/hw/char/etraxfs_ser.c +++ b/hw/char/etraxfs_ser.c @@ -113,7 +113,7 @@ ser_read(void *opaque, hwaddr addr, unsigned int size) break; default: r = s->regs[addr]; - D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, r)); + D(qemu_log("%s " HWADDR_FMT_plx "=%x\n", __func__, addr, r)); break; } return r; @@ -127,7 +127,7 @@ ser_write(void *opaque, hwaddr addr, uint32_t value = val64; unsigned char ch = val64; - D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, value)); + D(qemu_log("%s " HWADDR_FMT_plx "=%x\n", __func__, addr, value)); addr >>= 2; switch (addr) { diff --git a/hw/core/loader.c b/hw/core/loader.c index 0548830733..a18fb26469 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -1054,7 +1054,7 @@ ssize_t rom_add_file(const char *file, const char *fw_dir, rom->mr = mr; snprintf(devpath, sizeof(devpath), "/rom@%s", file); } else { - snprintf(devpath, sizeof(devpath), "/rom@" TARGET_FMT_plx, addr); + snprintf(devpath, sizeof(devpath), "/rom@" HWADDR_FMT_plx, addr); } } @@ -1238,10 +1238,10 @@ static void rom_print_one_overlap_error(Rom *last_rom, Rom *rom) "\nThe following two regions overlap (in the %s address space):\n", rom_as_name(rom)); error_printf( - " %s (addresses 0x" TARGET_FMT_plx " - 0x" TARGET_FMT_plx ")\n", + " %s (addresses 0x" HWADDR_FMT_plx " - 0x" HWADDR_FMT_plx ")\n", last_rom->name, last_rom->addr, last_rom->addr + last_rom->romsize); error_printf( - " %s (addresses 0x" TARGET_FMT_plx " - 0x" TARGET_FMT_plx ")\n", + " %s (addresses 0x" HWADDR_FMT_plx " - 0x" HWADDR_FMT_plx ")\n", rom->name, rom->addr, rom->addr + rom->romsize); } @@ -1595,7 +1595,7 @@ HumanReadableText *qmp_x_query_roms(Error **errp) rom->romsize, rom->name); } else if (!rom->fw_file) { - g_string_append_printf(buf, "addr=" TARGET_FMT_plx + g_string_append_printf(buf, "addr=" HWADDR_FMT_plx " size=0x%06zx mem=%s name=\"%s\"\n", rom->addr, rom->romsize, rom->isrom ? "rom" : "ram", diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c index 05c1da3d31..35f902b582 100644 --- a/hw/core/sysbus.c +++ b/hw/core/sysbus.c @@ -269,7 +269,7 @@ static void sysbus_dev_print(Monitor *mon, DeviceState *dev, int indent) for (i = 0; i < s->num_mmio; i++) { size = memory_region_size(s->mmio[i].memory); - monitor_printf(mon, "%*smmio " TARGET_FMT_plx "/" TARGET_FMT_plx "\n", + monitor_printf(mon, "%*smmio " HWADDR_FMT_plx "/" HWADDR_FMT_plx "\n", indent, "", s->mmio[i].addr, size); } } @@ -289,7 +289,7 @@ static char *sysbus_get_fw_dev_path(DeviceState *dev) } } if (s->num_mmio) { - return g_strdup_printf("%s@" TARGET_FMT_plx, qdev_fw_name(dev), + return g_strdup_printf("%s@" HWADDR_FMT_plx, qdev_fw_name(dev), s->mmio[0].addr); } if (s->num_pio) { diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c index 55c32e3e40..b80f98b6c4 100644 --- a/hw/display/cirrus_vga.c +++ b/hw/display/cirrus_vga.c @@ -2041,7 +2041,7 @@ static uint64_t cirrus_vga_mem_read(void *opaque, } else { val = 0xff; qemu_log_mask(LOG_GUEST_ERROR, - "cirrus: mem_readb 0x" TARGET_FMT_plx "\n", addr); + "cirrus: mem_readb 0x" HWADDR_FMT_plx "\n", addr); } return val; } @@ -2105,7 +2105,7 @@ static void cirrus_vga_mem_write(void *opaque, } } else { qemu_log_mask(LOG_GUEST_ERROR, - "cirrus: mem_writeb 0x" TARGET_FMT_plx " " + "cirrus: mem_writeb 0x" HWADDR_FMT_plx " " "value 0x%02" PRIx64 "\n", addr, mem_value); } } diff --git a/hw/display/g364fb.c b/hw/display/g364fb.c index caca86d773..2903cab82d 100644 --- a/hw/display/g364fb.c +++ b/hw/display/g364fb.c @@ -320,7 +320,7 @@ static uint64_t g364fb_ctrl_read(void *opaque, break; default: { - error_report("g364: invalid read at [" TARGET_FMT_plx "]", + error_report("g364: invalid read at [" HWADDR_FMT_plx "]", addr); val = 0; break; @@ -424,7 +424,7 @@ static void g364fb_ctrl_write(void *opaque, break; default: error_report("g364: invalid write of 0x%" PRIx64 - " at [" TARGET_FMT_plx "]", val, addr); + " at [" HWADDR_FMT_plx "]", val, addr); break; } } diff --git a/hw/display/vga.c b/hw/display/vga.c index 0cb26a791b..7a5fdff649 100644 --- a/hw/display/vga.c +++ b/hw/display/vga.c @@ -875,7 +875,7 @@ void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val) uint32_t write_mask, bit_mask, set_mask; #ifdef DEBUG_VGA_MEM - printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val); + printf("vga: [0x" HWADDR_FMT_plx "] = 0x%02x\n", addr, val); #endif /* convert to VGA memory offset */ memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3; @@ -909,7 +909,7 @@ void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val) assert(addr < s->vram_size); s->vram_ptr[addr] = val; #ifdef DEBUG_VGA_MEM - printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr); + printf("vga: chain4: [0x" HWADDR_FMT_plx "]\n", addr); #endif s->plane_updated |= mask; /* only used to detect font change */ memory_region_set_dirty(&s->vram, addr, 1); @@ -925,7 +925,7 @@ void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val) } s->vram_ptr[addr] = val; #ifdef DEBUG_VGA_MEM - printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr); + printf("vga: odd/even: [0x" HWADDR_FMT_plx "]\n", addr); #endif s->plane_updated |= mask; /* only used to detect font change */ memory_region_set_dirty(&s->vram, addr, 1); @@ -1003,7 +1003,7 @@ void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val) (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) | (val & write_mask); #ifdef DEBUG_VGA_MEM - printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n", + printf("vga: latch: [0x" HWADDR_FMT_plx "] mask=0x%08x val=0x%08x\n", addr * 4, write_mask, val); #endif memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t)); diff --git a/hw/dma/etraxfs_dma.c b/hw/dma/etraxfs_dma.c index c4334e87bf..8951864ed7 100644 --- a/hw/dma/etraxfs_dma.c +++ b/hw/dma/etraxfs_dma.c @@ -272,7 +272,7 @@ static void channel_load_d(struct fs_dma_ctrl *ctrl, int c) hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA); /* Load and decode. FIXME: handle endianness. */ - D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); + D(printf("%s ch=%d addr=" HWADDR_FMT_plx "\n", __func__, c, addr)); cpu_physical_memory_read(addr, &ctrl->channels[c].current_d, sizeof(ctrl->channels[c].current_d)); @@ -285,7 +285,7 @@ static void channel_store_c(struct fs_dma_ctrl *ctrl, int c) hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN); /* Encode and store. FIXME: handle endianness. */ - D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); + D(printf("%s ch=%d addr=" HWADDR_FMT_plx "\n", __func__, c, addr)); D(dump_d(c, &ctrl->channels[c].current_d)); cpu_physical_memory_write(addr, &ctrl->channels[c].current_c, sizeof(ctrl->channels[c].current_c)); @@ -296,7 +296,7 @@ static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA); /* Encode and store. FIXME: handle endianness. */ - D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); + D(printf("%s ch=%d addr=" HWADDR_FMT_plx "\n", __func__, c, addr)); cpu_physical_memory_write(addr, &ctrl->channels[c].current_d, sizeof(ctrl->channels[c].current_d)); } @@ -574,7 +574,7 @@ static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c) static uint32_t dma_rinvalid (void *opaque, hwaddr addr) { - hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr); + hw_error("Unsupported short raccess. reg=" HWADDR_FMT_plx "\n", addr); return 0; } @@ -603,7 +603,7 @@ dma_read(void *opaque, hwaddr addr, unsigned int size) default: r = ctrl->channels[c].regs[addr]; - D(printf ("%s c=%d addr=" TARGET_FMT_plx "\n", + D(printf ("%s c=%d addr=" HWADDR_FMT_plx "\n", __func__, c, addr)); break; } @@ -613,7 +613,7 @@ dma_read(void *opaque, hwaddr addr, unsigned int size) static void dma_winvalid (void *opaque, hwaddr addr, uint32_t value) { - hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr); + hw_error("Unsupported short waccess. reg=" HWADDR_FMT_plx "\n", addr); } static void @@ -686,7 +686,7 @@ dma_write(void *opaque, hwaddr addr, break; default: - D(printf ("%s c=%d " TARGET_FMT_plx "\n", + D(printf ("%s c=%d " HWADDR_FMT_plx "\n", __func__, c, addr)); break; } diff --git a/hw/dma/pl330.c b/hw/dma/pl330.c index e5d521c329..e7e67dd8b6 100644 --- a/hw/dma/pl330.c +++ b/hw/dma/pl330.c @@ -1373,7 +1373,7 @@ static void pl330_iomem_write(void *opaque, hwaddr offset, pl330_exec(s); } else { qemu_log_mask(LOG_GUEST_ERROR, "pl330: write of illegal value %u " - "for offset " TARGET_FMT_plx "\n", (unsigned)value, + "for offset " HWADDR_FMT_plx "\n", (unsigned)value, offset); } break; @@ -1384,7 +1384,7 @@ static void pl330_iomem_write(void *opaque, hwaddr offset, s->dbg[1] = value; break; default: - qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad write offset " TARGET_FMT_plx + qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad write offset " HWADDR_FMT_plx "\n", offset); break; } @@ -1409,7 +1409,7 @@ static inline uint32_t pl330_iomem_read_imp(void *opaque, chan_id = offset >> 5; if (chan_id >= s->num_chnls) { qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " - TARGET_FMT_plx "\n", offset); + HWADDR_FMT_plx "\n", offset); return 0; } switch (offset & 0x1f) { @@ -1425,7 +1425,7 @@ static inline uint32_t pl330_iomem_read_imp(void *opaque, return s->chan[chan_id].lc[1]; default: qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " - TARGET_FMT_plx "\n", offset); + HWADDR_FMT_plx "\n", offset); return 0; } } @@ -1434,7 +1434,7 @@ static inline uint32_t pl330_iomem_read_imp(void *opaque, chan_id = offset >> 3; if (chan_id >= s->num_chnls) { qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " - TARGET_FMT_plx "\n", offset); + HWADDR_FMT_plx "\n", offset); return 0; } switch ((offset >> 2) & 1) { @@ -1456,7 +1456,7 @@ static inline uint32_t pl330_iomem_read_imp(void *opaque, chan_id = offset >> 2; if (chan_id >= s->num_chnls) { qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " - TARGET_FMT_plx "\n", offset); + HWADDR_FMT_plx "\n", offset); return 0; } return s->chan[chan_id].fault_type; @@ -1495,7 +1495,7 @@ static inline uint32_t pl330_iomem_read_imp(void *opaque, return s->debug_status; default: qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " - TARGET_FMT_plx "\n", offset); + HWADDR_FMT_plx "\n", offset); } return 0; } diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index cbb8f0f169..6030c76435 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -456,7 +456,7 @@ static uint64_t axidma_read(void *opaque, hwaddr addr, break; default: r = s->regs[addr]; - D(qemu_log("%s ch=%d addr=" TARGET_FMT_plx " v=%x\n", + D(qemu_log("%s ch=%d addr=" HWADDR_FMT_plx " v=%x\n", __func__, sid, addr * 4, r)); break; } @@ -509,7 +509,7 @@ static void axidma_write(void *opaque, hwaddr addr, } break; default: - D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx " v=%x\n", + D(qemu_log("%s: ch=%d addr=" HWADDR_FMT_plx " v=%x\n", __func__, sid, addr * 4, (unsigned)value)); s->regs[addr] = value; break; diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c index 1ce52ea5a2..88002698a1 100644 --- a/hw/dma/xlnx_csu_dma.c +++ b/hw/dma/xlnx_csu_dma.c @@ -211,7 +211,7 @@ static uint32_t xlnx_csu_dma_read(XlnxCSUDMA *s, uint8_t *buf, uint32_t len) if (result == MEMTX_OK) { xlnx_csu_dma_data_process(s, buf, len); } else { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address " TARGET_FMT_plx + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address " HWADDR_FMT_plx " for mem read", __func__, addr); s->regs[R_INT_STATUS] |= R_INT_STATUS_AXI_BRESP_ERR_MASK; xlnx_csu_dma_update_irq(s); @@ -241,7 +241,7 @@ static uint32_t xlnx_csu_dma_write(XlnxCSUDMA *s, uint8_t *buf, uint32_t len) } if (result != MEMTX_OK) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address " TARGET_FMT_plx + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address " HWADDR_FMT_plx " for mem write", __func__, addr); s->regs[R_INT_STATUS] |= R_INT_STATUS_AXI_BRESP_ERR_MASK; xlnx_csu_dma_update_irq(s); diff --git a/hw/i2c/mpc_i2c.c b/hw/i2c/mpc_i2c.c index 845392505f..219c548402 100644 --- a/hw/i2c/mpc_i2c.c +++ b/hw/i2c/mpc_i2c.c @@ -224,7 +224,7 @@ static uint64_t mpc_i2c_read(void *opaque, hwaddr addr, unsigned size) break; } - DPRINTF("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, + DPRINTF("%s: addr " HWADDR_FMT_plx " %02" PRIx32 "\n", __func__, addr, value); return (uint64_t)value; } @@ -234,7 +234,7 @@ static void mpc_i2c_write(void *opaque, hwaddr addr, { MPCI2CState *s = opaque; - DPRINTF("%s: addr " TARGET_FMT_plx " val %08" PRIx64 "\n", __func__, + DPRINTF("%s: addr " HWADDR_FMT_plx " val %08" PRIx64 "\n", __func__, addr, value); switch (addr) { case MPC_I2C_ADR: diff --git a/hw/i386/multiboot.c b/hw/i386/multiboot.c index 963e29362e..3332712ab3 100644 --- a/hw/i386/multiboot.c +++ b/hw/i386/multiboot.c @@ -137,7 +137,7 @@ static void mb_add_mod(MultibootState *s, stl_p(p + MB_MOD_END, end); stl_p(p + MB_MOD_CMDLINE, cmdline_phys); - mb_debug("mod%02d: "TARGET_FMT_plx" - "TARGET_FMT_plx, + mb_debug("mod%02d: "HWADDR_FMT_plx" - "HWADDR_FMT_plx, s->mb_mods_count, start, end); s->mb_mods_count++; @@ -353,7 +353,7 @@ int load_multiboot(X86MachineState *x86ms, mb_add_mod(&mbs, mbs.mb_buf_phys + offs, mbs.mb_buf_phys + offs + mb_mod_length, c); - mb_debug("mod_start: %p\nmod_end: %p\n cmdline: "TARGET_FMT_plx, + mb_debug("mod_start: %p\nmod_end: %p\n cmdline: "HWADDR_FMT_plx, (char *)mbs.mb_buf + offs, (char *)mbs.mb_buf + offs + mb_mod_length, c); g_free(one_file); @@ -382,8 +382,8 @@ int load_multiboot(X86MachineState *x86ms, stl_p(bootinfo + MBI_MMAP_ADDR, ADDR_E820_MAP); mb_debug("multiboot: entry_addr = %#x", mh_entry_addr); - mb_debug(" mb_buf_phys = "TARGET_FMT_plx, mbs.mb_buf_phys); - mb_debug(" mod_start = "TARGET_FMT_plx, + mb_debug(" mb_buf_phys = "HWADDR_FMT_plx, mbs.mb_buf_phys); + mb_debug(" mod_start = "HWADDR_FMT_plx, mbs.mb_buf_phys + mbs.offset_mods); mb_debug(" mb_mods_count = %d", mbs.mb_mods_count); diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c index e4293d6d66..b9a6f7f538 100644 --- a/hw/i386/xen/xen-hvm.c +++ b/hw/i386/xen/xen-hvm.c @@ -516,13 +516,13 @@ static void xen_set_memory(struct MemoryListener *listener, if (xen_set_mem_type(xen_domid, mem_type, start_addr >> TARGET_PAGE_BITS, size >> TARGET_PAGE_BITS)) { - DPRINTF("xen_set_mem_type error, addr: "TARGET_FMT_plx"\n", + DPRINTF("xen_set_mem_type error, addr: "HWADDR_FMT_plx"\n", start_addr); } } } else { if (xen_remove_from_physmap(state, start_addr, size) < 0) { - DPRINTF("physmapping does not exist at "TARGET_FMT_plx"\n", start_addr); + DPRINTF("physmapping does not exist at "HWADDR_FMT_plx"\n", start_addr); } } } @@ -642,8 +642,8 @@ static void xen_sync_dirty_bitmap(XenIOState *state, #endif if (errno == ENODATA) { memory_region_set_dirty(framebuffer, 0, size); - DPRINTF("xen: track_dirty_vram failed (0x" TARGET_FMT_plx - ", 0x" TARGET_FMT_plx "): %s\n", + DPRINTF("xen: track_dirty_vram failed (0x" HWADDR_FMT_plx + ", 0x" HWADDR_FMT_plx "): %s\n", start_addr, start_addr + size, strerror(errno)); } return; diff --git a/hw/i386/xen/xen-mapcache.c b/hw/i386/xen/xen-mapcache.c index a2f93096e7..1d0879d234 100644 --- a/hw/i386/xen/xen-mapcache.c +++ b/hw/i386/xen/xen-mapcache.c @@ -357,7 +357,7 @@ tryagain: entry->lock++; if (entry->lock == 0) { fprintf(stderr, - "mapcache entry lock overflow: "TARGET_FMT_plx" -> %p\n", + "mapcache entry lock overflow: "HWADDR_FMT_plx" -> %p\n", entry->paddr_index, entry->vaddr_base); abort(); } @@ -404,7 +404,7 @@ ram_addr_t xen_ram_addr_from_mapcache(void *ptr) if (!found) { fprintf(stderr, "%s, could not find %p\n", __func__, ptr); QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) { - DPRINTF(" "TARGET_FMT_plx" -> %p is present\n", reventry->paddr_index, + DPRINTF(" "HWADDR_FMT_plx" -> %p is present\n", reventry->paddr_index, reventry->vaddr_req); } abort(); @@ -445,7 +445,7 @@ static void xen_invalidate_map_cache_entry_unlocked(uint8_t *buffer) if (!found) { DPRINTF("%s, could not find %p\n", __func__, buffer); QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) { - DPRINTF(" "TARGET_FMT_plx" -> %p is present\n", reventry->paddr_index, reventry->vaddr_req); + DPRINTF(" "HWADDR_FMT_plx" -> %p is present\n", reventry->paddr_index, reventry->vaddr_req); } return; } @@ -503,7 +503,7 @@ void xen_invalidate_map_cache(void) continue; } fprintf(stderr, "Locked DMA mapping while invalidating mapcache!" - " "TARGET_FMT_plx" -> %p is present\n", + " "HWADDR_FMT_plx" -> %p is present\n", reventry->paddr_index, reventry->vaddr_req); } @@ -562,7 +562,7 @@ static uint8_t *xen_replace_cache_entry_unlocked(hwaddr old_phys_addr, entry = entry->next; } if (!entry) { - DPRINTF("Trying to update an entry for "TARGET_FMT_plx \ + DPRINTF("Trying to update an entry for "HWADDR_FMT_plx \ "that is not in the mapcache!\n", old_phys_addr); return NULL; } @@ -570,15 +570,15 @@ static uint8_t *xen_replace_cache_entry_unlocked(hwaddr old_phys_addr, address_index = new_phys_addr >> MCACHE_BUCKET_SHIFT; address_offset = new_phys_addr & (MCACHE_BUCKET_SIZE - 1); - fprintf(stderr, "Replacing a dummy mapcache entry for "TARGET_FMT_plx \ - " with "TARGET_FMT_plx"\n", old_phys_addr, new_phys_addr); + fprintf(stderr, "Replacing a dummy mapcache entry for "HWADDR_FMT_plx \ + " with "HWADDR_FMT_plx"\n", old_phys_addr, new_phys_addr); xen_remap_bucket(entry, entry->vaddr_base, cache_size, address_index, false); if (!test_bits(address_offset >> XC_PAGE_SHIFT, test_bit_size >> XC_PAGE_SHIFT, entry->valid_mapping)) { - DPRINTF("Unable to update a mapcache entry for "TARGET_FMT_plx"!\n", + DPRINTF("Unable to update a mapcache entry for "HWADDR_FMT_plx"!\n", old_phys_addr); return NULL; } diff --git a/hw/i386/xen/xen_platform.c b/hw/i386/xen/xen_platform.c index 7db0d94ec2..66e6de31a6 100644 --- a/hw/i386/xen/xen_platform.c +++ b/hw/i386/xen/xen_platform.c @@ -445,7 +445,7 @@ static uint64_t platform_mmio_read(void *opaque, hwaddr addr, unsigned size) { DPRINTF("Warning: attempted read from physical address " - "0x" TARGET_FMT_plx " in xen platform mmio space\n", addr); + "0x" HWADDR_FMT_plx " in xen platform mmio space\n", addr); return 0; } @@ -454,7 +454,7 @@ static void platform_mmio_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { DPRINTF("Warning: attempted write of 0x%"PRIx64" to physical " - "address 0x" TARGET_FMT_plx " in xen platform mmio space\n", + "address 0x" HWADDR_FMT_plx " in xen platform mmio space\n", val, addr); } diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index d599fefcbc..35e850685c 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -564,7 +564,7 @@ static bool gicd_readl(GICv3State *s, hwaddr offset, /* WO registers, return unknown value */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest read from WO register at offset " - TARGET_FMT_plx "\n", __func__, offset); + HWADDR_FMT_plx "\n", __func__, offset); *data = 0; return true; default: @@ -773,7 +773,7 @@ static bool gicd_writel(GICv3State *s, hwaddr offset, /* RO registers, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - TARGET_FMT_plx "\n", __func__, offset); + HWADDR_FMT_plx "\n", __func__, offset); return true; default: return false; @@ -838,7 +838,7 @@ MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data, if (!r) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid guest read at offset " TARGET_FMT_plx + "%s: invalid guest read at offset " HWADDR_FMT_plx " size %u\n", __func__, offset, size); trace_gicv3_dist_badread(offset, size, attrs.secure); /* The spec requires that reserved registers are RAZ/WI; @@ -879,7 +879,7 @@ MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data, if (!r) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid guest write at offset " TARGET_FMT_plx + "%s: invalid guest write at offset " HWADDR_FMT_plx " size %u\n", __func__, offset, size); trace_gicv3_dist_badwrite(offset, data, size, attrs.secure); /* The spec requires that reserved registers are RAZ/WI; diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 57c79da5c5..43dfd7a35c 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -1633,7 +1633,7 @@ static bool its_writel(GICv3ITSState *s, hwaddr offset, /* RO register, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - TARGET_FMT_plx "\n", __func__, offset); + HWADDR_FMT_plx "\n", __func__, offset); } break; case GITS_CREADR + 4: @@ -1643,7 +1643,7 @@ static bool its_writel(GICv3ITSState *s, hwaddr offset, /* RO register, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - TARGET_FMT_plx "\n", __func__, offset); + HWADDR_FMT_plx "\n", __func__, offset); } break; case GITS_BASER ... GITS_BASER + 0x3f: @@ -1675,7 +1675,7 @@ static bool its_writel(GICv3ITSState *s, hwaddr offset, /* RO registers, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - TARGET_FMT_plx "\n", __func__, offset); + HWADDR_FMT_plx "\n", __func__, offset); break; default: result = false; @@ -1785,14 +1785,14 @@ static bool its_writell(GICv3ITSState *s, hwaddr offset, /* RO register, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - TARGET_FMT_plx "\n", __func__, offset); + HWADDR_FMT_plx "\n", __func__, offset); } break; case GITS_TYPER: /* RO registers, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - TARGET_FMT_plx "\n", __func__, offset); + HWADDR_FMT_plx "\n", __func__, offset); break; default: result = false; @@ -1851,7 +1851,7 @@ static MemTxResult gicv3_its_read(void *opaque, hwaddr offset, uint64_t *data, if (!result) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid guest read at offset " TARGET_FMT_plx + "%s: invalid guest read at offset " HWADDR_FMT_plx " size %u\n", __func__, offset, size); trace_gicv3_its_badread(offset, size); /* @@ -1887,7 +1887,7 @@ static MemTxResult gicv3_its_write(void *opaque, hwaddr offset, uint64_t data, if (!result) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid guest write at offset " TARGET_FMT_plx + "%s: invalid guest write at offset " HWADDR_FMT_plx " size %u\n", __func__, offset, size); trace_gicv3_its_badwrite(offset, data, size); /* diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index c92ceecc16..297f7f0263 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -601,7 +601,7 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset, /* RO registers, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - TARGET_FMT_plx "\n", __func__, offset); + HWADDR_FMT_plx "\n", __func__, offset); return MEMTX_OK; /* * VLPI frame registers. We don't need a version check for @@ -668,7 +668,7 @@ static MemTxResult gicr_writell(GICv3CPUState *cs, hwaddr offset, /* RO register, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - TARGET_FMT_plx "\n", __func__, offset); + HWADDR_FMT_plx "\n", __func__, offset); return MEMTX_OK; /* * VLPI frame registers. We don't need a version check for @@ -727,7 +727,7 @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data, if (r != MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid guest read at offset " TARGET_FMT_plx + "%s: invalid guest read at offset " HWADDR_FMT_plx " size %u\n", __func__, offset, size); trace_gicv3_redist_badread(gicv3_redist_affid(cs), offset, size, attrs.secure); @@ -786,7 +786,7 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data, if (r != MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid guest write at offset " TARGET_FMT_plx + "%s: invalid guest write at offset " HWADDR_FMT_plx " size %u\n", __func__, offset, size); trace_gicv3_redist_badwrite(gicv3_redist_affid(cs), offset, data, size, attrs.secure); diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c index a289510bdb..4ba448fdb1 100644 --- a/hw/intc/exynos4210_combiner.c +++ b/hw/intc/exynos4210_combiner.c @@ -120,7 +120,7 @@ exynos4210_combiner_read(void *opaque, hwaddr offset, unsigned size) default: if (offset >> 2 >= IIC_REGSET_SIZE) { hw_error("exynos4210.combiner: overflow of reg_set by 0x" - TARGET_FMT_plx "offset\n", offset); + HWADDR_FMT_plx "offset\n", offset); } val = s->reg_set[offset >> 2]; } @@ -184,19 +184,19 @@ static void exynos4210_combiner_write(void *opaque, hwaddr offset, if (req_quad_base_n >= IIC_NGRP) { hw_error("exynos4210.combiner: unallowed write access at offset 0x" - TARGET_FMT_plx "\n", offset); + HWADDR_FMT_plx "\n", offset); return; } if (reg_n > 1) { hw_error("exynos4210.combiner: unallowed write access at offset 0x" - TARGET_FMT_plx "\n", offset); + HWADDR_FMT_plx "\n", offset); return; } if (offset >> 2 >= IIC_REGSET_SIZE) { hw_error("exynos4210.combiner: overflow of reg_set by 0x" - TARGET_FMT_plx "offset\n", offset); + HWADDR_FMT_plx "offset\n", offset); } s->reg_set[offset >> 2] = val; @@ -246,7 +246,7 @@ static void exynos4210_combiner_write(void *opaque, hwaddr offset, break; default: hw_error("exynos4210.combiner: unallowed write access at offset 0x" - TARGET_FMT_plx "\n", offset); + HWADDR_FMT_plx "\n", offset); break; } } diff --git a/hw/misc/auxbus.c b/hw/misc/auxbus.c index 8a8012f5f0..28d50d9d09 100644 --- a/hw/misc/auxbus.c +++ b/hw/misc/auxbus.c @@ -299,7 +299,7 @@ static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent) s = AUX_SLAVE(dev); - monitor_printf(mon, "%*smemory " TARGET_FMT_plx "/" TARGET_FMT_plx "\n", + monitor_printf(mon, "%*smemory " HWADDR_FMT_plx "/" HWADDR_FMT_plx "\n", indent, "", object_property_get_uint(OBJECT(s->mmio), "addr", NULL), memory_region_size(s->mmio)); diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c index 8270db53cd..d66d912172 100644 --- a/hw/misc/ivshmem.c +++ b/hw/misc/ivshmem.c @@ -179,7 +179,7 @@ static void ivshmem_io_write(void *opaque, hwaddr addr, addr &= 0xfc; - IVSHMEM_DPRINTF("writing to addr " TARGET_FMT_plx "\n", addr); + IVSHMEM_DPRINTF("writing to addr " HWADDR_FMT_plx "\n", addr); switch (addr) { case INTRMASK: @@ -207,7 +207,7 @@ static void ivshmem_io_write(void *opaque, hwaddr addr, } break; default: - IVSHMEM_DPRINTF("Unhandled write " TARGET_FMT_plx "\n", addr); + IVSHMEM_DPRINTF("Unhandled write " HWADDR_FMT_plx "\n", addr); } } @@ -233,7 +233,7 @@ static uint64_t ivshmem_io_read(void *opaque, hwaddr addr, break; default: - IVSHMEM_DPRINTF("why are we reading " TARGET_FMT_plx "\n", addr); + IVSHMEM_DPRINTF("why are we reading " HWADDR_FMT_plx "\n", addr); ret = 0; } diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c index efcc02609f..43bb1f56ba 100644 --- a/hw/misc/macio/mac_dbdma.c +++ b/hw/misc/macio/mac_dbdma.c @@ -704,7 +704,7 @@ static void dbdma_write(void *opaque, hwaddr addr, DBDMA_channel *ch = &s->channels[channel]; int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2; - DBDMA_DPRINTFCH(ch, "writel 0x" TARGET_FMT_plx " <= 0x%08"PRIx64"\n", + DBDMA_DPRINTFCH(ch, "writel 0x" HWADDR_FMT_plx " <= 0x%08"PRIx64"\n", addr, value); DBDMA_DPRINTFCH(ch, "channel 0x%x reg 0x%x\n", (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg); @@ -786,7 +786,7 @@ static uint64_t dbdma_read(void *opaque, hwaddr addr, break; } - DBDMA_DPRINTFCH(ch, "readl 0x" TARGET_FMT_plx " => 0x%08x\n", addr, value); + DBDMA_DPRINTFCH(ch, "readl 0x" HWADDR_FMT_plx " => 0x%08x\n", addr, value); DBDMA_DPRINTFCH(ch, "channel 0x%x reg 0x%x\n", (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg); diff --git a/hw/misc/mst_fpga.c b/hw/misc/mst_fpga.c index 2aaadfa966..7692825867 100644 --- a/hw/misc/mst_fpga.c +++ b/hw/misc/mst_fpga.c @@ -131,7 +131,7 @@ mst_fpga_readb(void *opaque, hwaddr addr, unsigned size) return s->pcmcia1; default: printf("Mainstone - mst_fpga_readb: Bad register offset " - "0x" TARGET_FMT_plx "\n", addr); + "0x" HWADDR_FMT_plx "\n", addr); } return 0; } @@ -185,7 +185,7 @@ mst_fpga_writeb(void *opaque, hwaddr addr, uint64_t value, break; default: printf("Mainstone - mst_fpga_writeb: Bad register offset " - "0x" TARGET_FMT_plx "\n", addr); + "0x" HWADDR_FMT_plx "\n", addr); } } diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c index ecc0245fe8..b861d8ff35 100644 --- a/hw/net/allwinner-sun8i-emac.c +++ b/hw/net/allwinner-sun8i-emac.c @@ -663,7 +663,7 @@ static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset, break; default: qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to unknown " - "EMAC register 0x" TARGET_FMT_plx "\n", + "EMAC register 0x" HWADDR_FMT_plx "\n", offset); } @@ -760,7 +760,7 @@ static void allwinner_sun8i_emac_write(void *opaque, hwaddr offset, break; default: qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to unknown " - "EMAC register 0x" TARGET_FMT_plx "\n", + "EMAC register 0x" HWADDR_FMT_plx "\n", offset); } } diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c index ddddf35c45..372e5b66da 100644 --- a/hw/net/allwinner_emac.c +++ b/hw/net/allwinner_emac.c @@ -304,7 +304,7 @@ static uint64_t aw_emac_read(void *opaque, hwaddr offset, unsigned size) default: qemu_log_mask(LOG_UNIMP, "allwinner_emac: read access to unknown register 0x" - TARGET_FMT_plx "\n", offset); + HWADDR_FMT_plx "\n", offset); ret = 0; } @@ -407,7 +407,7 @@ static void aw_emac_write(void *opaque, hwaddr offset, uint64_t value, default: qemu_log_mask(LOG_UNIMP, "allwinner_emac: write access to unknown register 0x" - TARGET_FMT_plx "\n", offset); + HWADDR_FMT_plx "\n", offset); } } diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c index b75d8e3dce..c753bfb3a8 100644 --- a/hw/net/fsl_etsec/etsec.c +++ b/hw/net/fsl_etsec/etsec.c @@ -99,7 +99,7 @@ static uint64_t etsec_read(void *opaque, hwaddr addr, unsigned size) break; } - DPRINTF("Read 0x%08x @ 0x" TARGET_FMT_plx + DPRINTF("Read 0x%08x @ 0x" HWADDR_FMT_plx " : %s (%s)\n", ret, addr, reg->name, reg->desc); @@ -276,7 +276,7 @@ static void etsec_write(void *opaque, } } - DPRINTF("Write 0x%08x @ 0x" TARGET_FMT_plx + DPRINTF("Write 0x%08x @ 0x" HWADDR_FMT_plx " val:0x%08x->0x%08x : %s (%s)\n", (unsigned int)value, addr, before, reg->value, reg->name, reg->desc); diff --git a/hw/net/fsl_etsec/rings.c b/hw/net/fsl_etsec/rings.c index a32589e33b..788463f1b6 100644 --- a/hw/net/fsl_etsec/rings.c +++ b/hw/net/fsl_etsec/rings.c @@ -109,7 +109,7 @@ static void read_buffer_descriptor(eTSEC *etsec, { assert(bd != NULL); - RING_DEBUG("READ Buffer Descriptor @ 0x" TARGET_FMT_plx"\n", addr); + RING_DEBUG("READ Buffer Descriptor @ 0x" HWADDR_FMT_plx"\n", addr); cpu_physical_memory_read(addr, bd, sizeof(eTSEC_rxtx_bd)); @@ -141,7 +141,7 @@ static void write_buffer_descriptor(eTSEC *etsec, stl_be_p(&bd->bufptr, bd->bufptr); } - RING_DEBUG("Write Buffer Descriptor @ 0x" TARGET_FMT_plx"\n", addr); + RING_DEBUG("Write Buffer Descriptor @ 0x" HWADDR_FMT_plx"\n", addr); cpu_physical_memory_write(addr, bd, sizeof(eTSEC_rxtx_bd)); diff --git a/hw/net/pcnet.c b/hw/net/pcnet.c index e63e524913..d456094575 100644 --- a/hw/net/pcnet.c +++ b/hw/net/pcnet.c @@ -908,11 +908,11 @@ static void pcnet_rdte_poll(PCNetState *s) s->csr[37] = nnrd >> 16; #ifdef PCNET_DEBUG if (bad) { - printf("pcnet: BAD RMD RECORDS AFTER 0x" TARGET_FMT_plx "\n", + printf("pcnet: BAD RMD RECORDS AFTER 0x" HWADDR_FMT_plx "\n", crda); } } else { - printf("pcnet: BAD RMD RDA=0x" TARGET_FMT_plx "\n", crda); + printf("pcnet: BAD RMD RDA=0x" HWADDR_FMT_plx "\n", crda); #endif } } diff --git a/hw/net/rocker/rocker.c b/hw/net/rocker/rocker.c index cf54ddf49d..7ea8eb6ba5 100644 --- a/hw/net/rocker/rocker.c +++ b/hw/net/rocker/rocker.c @@ -815,7 +815,7 @@ static void rocker_io_writel(void *opaque, hwaddr addr, uint32_t val) } break; default: - DPRINTF("not implemented dma reg write(l) addr=0x" TARGET_FMT_plx + DPRINTF("not implemented dma reg write(l) addr=0x" HWADDR_FMT_plx " val=0x%08x (ring %d, addr=0x%02x)\n", addr, val, index, offset); break; @@ -857,7 +857,7 @@ static void rocker_io_writel(void *opaque, hwaddr addr, uint32_t val) r->lower32 = 0; break; default: - DPRINTF("not implemented write(l) addr=0x" TARGET_FMT_plx + DPRINTF("not implemented write(l) addr=0x" HWADDR_FMT_plx " val=0x%08x\n", addr, val); break; } @@ -876,8 +876,8 @@ static void rocker_io_writeq(void *opaque, hwaddr addr, uint64_t val) desc_ring_set_base_addr(r->rings[index], val); break; default: - DPRINTF("not implemented dma reg write(q) addr=0x" TARGET_FMT_plx - " val=0x" TARGET_FMT_plx " (ring %d, offset=0x%02x)\n", + DPRINTF("not implemented dma reg write(q) addr=0x" HWADDR_FMT_plx + " val=0x" HWADDR_FMT_plx " (ring %d, offset=0x%02x)\n", addr, val, index, offset); break; } @@ -895,8 +895,8 @@ static void rocker_io_writeq(void *opaque, hwaddr addr, uint64_t val) rocker_port_phys_enable_write(r, val); break; default: - DPRINTF("not implemented write(q) addr=0x" TARGET_FMT_plx - " val=0x" TARGET_FMT_plx "\n", addr, val); + DPRINTF("not implemented write(q) addr=0x" HWADDR_FMT_plx + " val=0x" HWADDR_FMT_plx "\n", addr, val); break; } } @@ -987,8 +987,8 @@ static const char *rocker_reg_name(void *opaque, hwaddr addr) static void rocker_mmio_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - DPRINTF("Write %s addr " TARGET_FMT_plx - ", size %u, val " TARGET_FMT_plx "\n", + DPRINTF("Write %s addr " HWADDR_FMT_plx + ", size %u, val " HWADDR_FMT_plx "\n", rocker_reg_name(opaque, addr), addr, size, val); switch (size) { @@ -1060,7 +1060,7 @@ static uint32_t rocker_io_readl(void *opaque, hwaddr addr) ret = desc_ring_get_credits(r->rings[index]); break; default: - DPRINTF("not implemented dma reg read(l) addr=0x" TARGET_FMT_plx + DPRINTF("not implemented dma reg read(l) addr=0x" HWADDR_FMT_plx " (ring %d, addr=0x%02x)\n", addr, index, offset); ret = 0; break; @@ -1115,7 +1115,7 @@ static uint32_t rocker_io_readl(void *opaque, hwaddr addr) ret = (uint32_t)(r->switch_id >> 32); break; default: - DPRINTF("not implemented read(l) addr=0x" TARGET_FMT_plx "\n", addr); + DPRINTF("not implemented read(l) addr=0x" HWADDR_FMT_plx "\n", addr); ret = 0; break; } @@ -1136,7 +1136,7 @@ static uint64_t rocker_io_readq(void *opaque, hwaddr addr) ret = desc_ring_get_base_addr(r->rings[index]); break; default: - DPRINTF("not implemented dma reg read(q) addr=0x" TARGET_FMT_plx + DPRINTF("not implemented dma reg read(q) addr=0x" HWADDR_FMT_plx " (ring %d, addr=0x%02x)\n", addr, index, offset); ret = 0; break; @@ -1165,7 +1165,7 @@ static uint64_t rocker_io_readq(void *opaque, hwaddr addr) ret = r->switch_id; break; default: - DPRINTF("not implemented read(q) addr=0x" TARGET_FMT_plx "\n", addr); + DPRINTF("not implemented read(q) addr=0x" HWADDR_FMT_plx "\n", addr); ret = 0; break; } @@ -1174,7 +1174,7 @@ static uint64_t rocker_io_readq(void *opaque, hwaddr addr) static uint64_t rocker_mmio_read(void *opaque, hwaddr addr, unsigned size) { - DPRINTF("Read %s addr " TARGET_FMT_plx ", size %u\n", + DPRINTF("Read %s addr " HWADDR_FMT_plx ", size %u\n", rocker_reg_name(opaque, addr), addr, size); switch (size) { diff --git a/hw/net/rocker/rocker_desc.c b/hw/net/rocker/rocker_desc.c index f3068c9250..675383db36 100644 --- a/hw/net/rocker/rocker_desc.c +++ b/hw/net/rocker/rocker_desc.c @@ -104,7 +104,7 @@ static bool desc_ring_empty(DescRing *ring) bool desc_ring_set_base_addr(DescRing *ring, uint64_t base_addr) { if (base_addr & 0x7) { - DPRINTF("ERROR: ring[%d] desc base addr (0x" TARGET_FMT_plx + DPRINTF("ERROR: ring[%d] desc base addr (0x" HWADDR_FMT_plx ") not 8-byte aligned\n", ring->index, base_addr); return false; } diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index 990ff3a1c2..7e00965323 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -524,7 +524,7 @@ static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) if (addr < ARRAY_SIZE(s->regs)) { r = s->regs[addr]; } - DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", + DENET(qemu_log("%s addr=" HWADDR_FMT_plx " v=%x\n", __func__, addr * 4, r)); break; } @@ -630,7 +630,7 @@ static void enet_write(void *opaque, hwaddr addr, break; default: - DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", + DENET(qemu_log("%s addr=" HWADDR_FMT_plx " v=%x\n", __func__, addr * 4, (unsigned)value)); if (addr < ARRAY_SIZE(s->regs)) { s->regs[addr] = value; diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 6e09f7e422..99c22819ea 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -99,7 +99,7 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) case R_RX_CTRL1: case R_RX_CTRL0: r = s->regs[addr]; - D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr * 4, r)); + D(qemu_log("%s " HWADDR_FMT_plx "=%x\n", __func__, addr * 4, r)); break; default: @@ -125,7 +125,7 @@ eth_write(void *opaque, hwaddr addr, if (addr == R_TX_CTRL1) base = 0x800 / 4; - D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n", + D(qemu_log("%s addr=" HWADDR_FMT_plx " val=%x\n", __func__, addr * 4, value)); if ((value & (CTRL_P | CTRL_S)) == CTRL_S) { qemu_send_packet(qemu_get_queue(s->nic), @@ -155,7 +155,7 @@ eth_write(void *opaque, hwaddr addr, case R_TX_LEN0: case R_TX_LEN1: case R_TX_GIE0: - D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n", + D(qemu_log("%s addr=" HWADDR_FMT_plx " val=%x\n", __func__, addr * 4, value)); s->regs[addr] = value; break; diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c index 870d9bab11..e752a21292 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -155,7 +155,7 @@ static char *pxb_host_ofw_unit_address(const SysBusDevice *dev) main_host_sbd = SYS_BUS_DEVICE(main_host); if (main_host_sbd->num_mmio > 0) { - return g_strdup_printf(TARGET_FMT_plx ",%x", + return g_strdup_printf(HWADDR_FMT_plx ",%x", main_host_sbd->mmio[0].addr, position + 1); } if (main_host_sbd->num_pio > 0) { diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c index f04f3ad668..e55e4d2950 100644 --- a/hw/pci-host/bonito.c +++ b/hw/pci-host/bonito.c @@ -254,7 +254,7 @@ static void bonito_writel(void *opaque, hwaddr addr, saddr = addr >> 2; - DPRINTF("bonito_writel "TARGET_FMT_plx" val %lx saddr %x\n", + DPRINTF("bonito_writel "HWADDR_FMT_plx" val %lx saddr %x\n", addr, val, saddr); switch (saddr) { case BONITO_BONPONCFG: @@ -317,7 +317,7 @@ static uint64_t bonito_readl(void *opaque, hwaddr addr, saddr = addr >> 2; - DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr); + DPRINTF("bonito_readl "HWADDR_FMT_plx"\n", addr); switch (saddr) { case BONITO_INTISR: return s->regs[saddr]; @@ -342,7 +342,7 @@ static void bonito_pciconf_writel(void *opaque, hwaddr addr, PCIBonitoState *s = opaque; PCIDevice *d = PCI_DEVICE(s); - DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %lx\n", addr, val); + DPRINTF("bonito_pciconf_writel "HWADDR_FMT_plx" val %lx\n", addr, val); d->config_write(d, addr, val, 4); } @@ -353,7 +353,7 @@ static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr, PCIBonitoState *s = opaque; PCIDevice *d = PCI_DEVICE(s); - DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr); + DPRINTF("bonito_pciconf_readl "HWADDR_FMT_plx"\n", addr); return d->config_read(d, addr, 4); } @@ -469,7 +469,7 @@ static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr) regno = (cfgaddr & BONITO_PCICONF_REG_MASK_HW) >> BONITO_PCICONF_REG_OFFSET; if (idsel == 0) { - error_report("error in bonito pci config address 0x" TARGET_FMT_plx + error_report("error in bonito pci config address 0x" HWADDR_FMT_plx ",pcimap_cfg=0x%x", addr, s->regs[BONITO_PCIMAP_CFG]); exit(1); } @@ -489,7 +489,7 @@ static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val, uint32_t pciaddr; uint16_t status; - DPRINTF("bonito_spciconf_write "TARGET_FMT_plx" size %d val %lx\n", + DPRINTF("bonito_spciconf_write "HWADDR_FMT_plx" size %d val %lx\n", addr, size, val); pciaddr = bonito_sbridge_pciaddr(s, addr); @@ -519,7 +519,7 @@ static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size) uint32_t pciaddr; uint16_t status; - DPRINTF("bonito_spciconf_read "TARGET_FMT_plx" size %d\n", addr, size); + DPRINTF("bonito_spciconf_read "HWADDR_FMT_plx" size %d\n", addr, size); pciaddr = bonito_sbridge_pciaddr(s, addr); diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c index 568849e930..38814247f2 100644 --- a/hw/pci-host/ppce500.c +++ b/hw/pci-host/ppce500.c @@ -189,7 +189,7 @@ static uint64_t pci_reg_read4(void *opaque, hwaddr addr, break; } - pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__, + pci_debug("%s: win:%lx(addr:" HWADDR_FMT_plx ") -> value:%x\n", __func__, win, addr, value); return value; } @@ -268,7 +268,7 @@ static void pci_reg_write4(void *opaque, hwaddr addr, win = addr & 0xfe0; - pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n", + pci_debug("%s: value:%x -> win:%lx(addr:" HWADDR_FMT_plx ")\n", __func__, (unsigned)value, win, addr); switch (win) { diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c index eaf217ff55..7f9f75239c 100644 --- a/hw/pci/pci_host.c +++ b/hw/pci/pci_host.c @@ -143,7 +143,7 @@ static void pci_host_config_write(void *opaque, hwaddr addr, { PCIHostState *s = opaque; - PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx64"\n", + PCI_DPRINTF("%s addr " HWADDR_FMT_plx " len %d val %"PRIx64"\n", __func__, addr, len, val); if (addr != 0 || len != 4) { return; @@ -157,7 +157,7 @@ static uint64_t pci_host_config_read(void *opaque, hwaddr addr, PCIHostState *s = opaque; uint32_t val = s->config_reg; - PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx32"\n", + PCI_DPRINTF("%s addr " HWADDR_FMT_plx " len %d val %"PRIx32"\n", __func__, addr, len, val); return val; } diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c index a24c80b1d2..4501fb28a5 100644 --- a/hw/ppc/ppc4xx_sdram.c +++ b/hw/ppc/ppc4xx_sdram.c @@ -500,7 +500,7 @@ static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size) bcr = 0x8000; break; default: - error_report("invalid RAM size " TARGET_FMT_plx, ram_size); + error_report("invalid RAM size " HWADDR_FMT_plx, ram_size); return 0; } bcr |= ram_base >> 2 & 0xffe00000; diff --git a/hw/rtc/exynos4210_rtc.c b/hw/rtc/exynos4210_rtc.c index d1620c7a2a..2b8a38a296 100644 --- a/hw/rtc/exynos4210_rtc.c +++ b/hw/rtc/exynos4210_rtc.c @@ -374,7 +374,7 @@ static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset, default: qemu_log_mask(LOG_GUEST_ERROR, - "exynos4210.rtc: bad read offset " TARGET_FMT_plx, + "exynos4210.rtc: bad read offset " HWADDR_FMT_plx, offset); break; } @@ -508,7 +508,7 @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset, default: qemu_log_mask(LOG_GUEST_ERROR, - "exynos4210.rtc: bad write offset " TARGET_FMT_plx, + "exynos4210.rtc: bad write offset " HWADDR_FMT_plx, offset); break; diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index c77792d150..ebe0fd96d9 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -207,13 +207,13 @@ static void portb_changed(SH7750State *s, uint16_t prev) static void error_access(const char *kind, hwaddr addr) { - fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n", + fprintf(stderr, "%s to %s (0x" HWADDR_FMT_plx ") not supported\n", kind, regname(addr), addr); } static void ignore_access(const char *kind, hwaddr addr) { - fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n", + fprintf(stderr, "%s to %s (0x" HWADDR_FMT_plx ") ignored\n", kind, regname(addr), addr); } diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c index b2819a7ff0..552927622f 100644 --- a/hw/ssi/xilinx_spi.c +++ b/hw/ssi/xilinx_spi.c @@ -232,7 +232,7 @@ spi_read(void *opaque, hwaddr addr, unsigned int size) break; } - DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, r); + DB_PRINT("addr=" HWADDR_FMT_plx " = %x\n", addr * 4, r); xlx_spi_update_irq(s); return r; } @@ -244,7 +244,7 @@ spi_write(void *opaque, hwaddr addr, XilinxSPI *s = opaque; uint32_t value = val64; - DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, value); + DB_PRINT("addr=" HWADDR_FMT_plx " = %x\n", addr, value); addr >>= 2; switch (addr) { case R_SRR: diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 1e9dba2039..97009d3a5d 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -887,7 +887,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, case R_INTR_STATUS: ret = s->regs[addr] & IXR_ALL; s->regs[addr] = 0; - DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); + DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr * 4, ret); xilinx_spips_update_ixr(s); return ret; case R_INTR_MASK: @@ -916,12 +916,12 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) { ret <<= 8 * shortfall; } - DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); + DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr * 4, ret); xilinx_spips_check_flush(s); xilinx_spips_update_ixr(s); return ret; } - DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, + DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr * 4, s->regs[addr] & mask); return s->regs[addr] & mask; @@ -971,7 +971,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, XilinxSPIPS *s = opaque; bool try_flush = true; - DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); + DB_PRINT_L(0, "addr=" HWADDR_FMT_plx " = %x\n", addr, (unsigned)value); addr >>= 2; switch (addr) { case R_CONFIG: diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c index d5186f4454..973eab4386 100644 --- a/hw/timer/digic-timer.c +++ b/hw/timer/digic-timer.c @@ -76,7 +76,7 @@ static uint64_t digic_timer_read(void *opaque, hwaddr offset, unsigned size) default: qemu_log_mask(LOG_UNIMP, "digic-timer: read access to unknown register 0x" - TARGET_FMT_plx "\n", offset); + HWADDR_FMT_plx "\n", offset); } return ret; @@ -116,7 +116,7 @@ static void digic_timer_write(void *opaque, hwaddr offset, default: qemu_log_mask(LOG_UNIMP, "digic-timer: read access to unknown register 0x" - TARGET_FMT_plx "\n", offset); + HWADDR_FMT_plx "\n", offset); } } diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c index ecc2831baf..0205b49912 100644 --- a/hw/timer/etraxfs_timer.c +++ b/hw/timer/etraxfs_timer.c @@ -324,7 +324,7 @@ timer_write(void *opaque, hwaddr addr, t->rw_ack_intr = 0; break; default: - printf ("%s " TARGET_FMT_plx " %x\n", + printf ("%s " HWADDR_FMT_plx " %x\n", __func__, addr, value); break; } diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c index e175a9f5b9..c17b247da3 100644 --- a/hw/timer/exynos4210_mct.c +++ b/hw/timer/exynos4210_mct.c @@ -1445,7 +1445,7 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, case L0_ICNTO: case L1_ICNTO: case L0_FRCNTO: case L1_FRCNTO: qemu_log_mask(LOG_GUEST_ERROR, - "exynos4210.mct: write to RO register " TARGET_FMT_plx, + "exynos4210.mct: write to RO register " HWADDR_FMT_plx, offset); break; diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c index 02924a9e5b..3528d0f33a 100644 --- a/hw/timer/exynos4210_pwm.c +++ b/hw/timer/exynos4210_pwm.c @@ -257,7 +257,7 @@ static uint64_t exynos4210_pwm_read(void *opaque, hwaddr offset, default: qemu_log_mask(LOG_GUEST_ERROR, - "exynos4210.pwm: bad read offset " TARGET_FMT_plx, + "exynos4210.pwm: bad read offset " HWADDR_FMT_plx, offset); break; } @@ -352,7 +352,7 @@ static void exynos4210_pwm_write(void *opaque, hwaddr offset, default: qemu_log_mask(LOG_GUEST_ERROR, - "exynos4210.pwm: bad write offset " TARGET_FMT_plx, + "exynos4210.pwm: bad write offset " HWADDR_FMT_plx, offset); break; diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c index 103260ec15..23ba625eb6 100644 --- a/hw/virtio/virtio-mmio.c +++ b/hw/virtio/virtio-mmio.c @@ -829,10 +829,10 @@ static char *virtio_mmio_bus_get_dev_path(DeviceState *dev) assert(section.mr); if (proxy_path) { - path = g_strdup_printf("%s/virtio-mmio@" TARGET_FMT_plx, proxy_path, + path = g_strdup_printf("%s/virtio-mmio@" HWADDR_FMT_plx, proxy_path, section.offset_within_address_space); } else { - path = g_strdup_printf("virtio-mmio@" TARGET_FMT_plx, + path = g_strdup_printf("virtio-mmio@" HWADDR_FMT_plx, section.offset_within_address_space); } memory_region_unref(section.mr); diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c index 0ec7e52183..8db0532632 100644 --- a/hw/xen/xen_pt.c +++ b/hw/xen/xen_pt.c @@ -434,7 +434,7 @@ static uint64_t xen_pt_bar_read(void *o, hwaddr addr, PCIDevice *d = o; /* if this function is called, that probably means that there is a * misconfiguration of the IOMMU. */ - XEN_PT_ERR(d, "Should not read BAR through QEMU. @0x"TARGET_FMT_plx"\n", + XEN_PT_ERR(d, "Should not read BAR through QEMU. @0x"HWADDR_FMT_plx"\n", addr); return 0; } @@ -443,7 +443,7 @@ static void xen_pt_bar_write(void *o, hwaddr addr, uint64_t val, { PCIDevice *d = o; /* Same comment as xen_pt_bar_read function */ - XEN_PT_ERR(d, "Should not write BAR through QEMU. @0x"TARGET_FMT_plx"\n", + XEN_PT_ERR(d, "Should not write BAR through QEMU. @0x"HWADDR_FMT_plx"\n", addr); } diff --git a/include/exec/hwaddr.h b/include/exec/hwaddr.h index 8f16d179a8..50fbb2d96c 100644 --- a/include/exec/hwaddr.h +++ b/include/exec/hwaddr.h @@ -10,7 +10,7 @@ typedef uint64_t hwaddr; #define HWADDR_MAX UINT64_MAX -#define TARGET_FMT_plx "%016" PRIx64 +#define HWADDR_FMT_plx "%016" PRIx64 #define HWADDR_PRId PRId64 #define HWADDR_PRIi PRIi64 #define HWADDR_PRIo PRIo64 diff --git a/monitor/misc.c b/monitor/misc.c index bf3f1c67ca..fa0a42c261 100644 --- a/monitor/misc.c +++ b/monitor/misc.c @@ -566,7 +566,7 @@ static void memory_dump(Monitor *mon, int count, int format, int wsize, while (len > 0) { if (is_physical) { - monitor_printf(mon, TARGET_FMT_plx ":", addr); + monitor_printf(mon, HWADDR_FMT_plx ":", addr); } else { monitor_printf(mon, TARGET_FMT_lx ":", (target_ulong)addr); } diff --git a/softmmu/memory.c b/softmmu/memory.c index e05332d07f..9d64efca26 100644 --- a/softmmu/memory.c +++ b/softmmu/memory.c @@ -1281,7 +1281,7 @@ static uint64_t unassigned_mem_read(void *opaque, hwaddr addr, unsigned size) { #ifdef DEBUG_UNASSIGNED - printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); + printf("Unassigned mem read " HWADDR_FMT_plx "\n", addr); #endif return 0; } @@ -1290,7 +1290,7 @@ static void unassigned_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { #ifdef DEBUG_UNASSIGNED - printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val); + printf("Unassigned mem write " HWADDR_FMT_plx " = 0x%"PRIx64"\n", addr, val); #endif } @@ -3220,9 +3220,9 @@ static void mtree_print_mr(const MemoryRegion *mr, unsigned int level, for (i = 0; i < level; i++) { qemu_printf(MTREE_INDENT); } - qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx - " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx - "-" TARGET_FMT_plx "%s", + qemu_printf(HWADDR_FMT_plx "-" HWADDR_FMT_plx + " (prio %d, %s%s): alias %s @%s " HWADDR_FMT_plx + "-" HWADDR_FMT_plx "%s", cur_start, cur_end, mr->priority, mr->nonvolatile ? "nv-" : "", @@ -3242,7 +3242,7 @@ static void mtree_print_mr(const MemoryRegion *mr, unsigned int level, for (i = 0; i < level; i++) { qemu_printf(MTREE_INDENT); } - qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx + qemu_printf(HWADDR_FMT_plx "-" HWADDR_FMT_plx " (prio %d, %s%s): %s%s", cur_start, cur_end, mr->priority, @@ -3329,8 +3329,8 @@ static void mtree_print_flatview(gpointer key, gpointer value, while (n--) { mr = range->mr; if (range->offset_in_region) { - qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx - " (prio %d, %s%s): %s @" TARGET_FMT_plx, + qemu_printf(MTREE_INDENT HWADDR_FMT_plx "-" HWADDR_FMT_plx + " (prio %d, %s%s): %s @" HWADDR_FMT_plx, int128_get64(range->addr.start), int128_get64(range->addr.start) + MR_SIZE(range->addr.size), @@ -3340,7 +3340,7 @@ static void mtree_print_flatview(gpointer key, gpointer value, memory_region_name(mr), range->offset_in_region); } else { - qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx + qemu_printf(MTREE_INDENT HWADDR_FMT_plx "-" HWADDR_FMT_plx " (prio %d, %s%s): %s", int128_get64(range->addr.start), int128_get64(range->addr.start) diff --git a/softmmu/memory_mapping.c b/softmmu/memory_mapping.c index f6f0a829fd..d7f1d096e0 100644 --- a/softmmu/memory_mapping.c +++ b/softmmu/memory_mapping.c @@ -241,8 +241,8 @@ static void guest_phys_block_add_section(GuestPhysListener *g, } #ifdef DEBUG_GUEST_PHYS_REGION_ADD - fprintf(stderr, "%s: target_start=" TARGET_FMT_plx " target_end=" - TARGET_FMT_plx ": %s (count: %u)\n", __func__, target_start, + fprintf(stderr, "%s: target_start=" HWADDR_FMT_plx " target_end=" + HWADDR_FMT_plx ": %s (count: %u)\n", __func__, target_start, target_end, predecessor ? "joined" : "added", g->list->num); #endif } diff --git a/softmmu/physmem.c b/softmmu/physmem.c index edec095c7a..bf585e45a8 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -2475,7 +2475,7 @@ static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data, MemTxResult res; #if defined(DEBUG_SUBPAGE) - printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__, + printf("%s: subpage %p len %u addr " HWADDR_FMT_plx "\n", __func__, subpage, len, addr); #endif res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len); @@ -2493,7 +2493,7 @@ static MemTxResult subpage_write(void *opaque, hwaddr addr, uint8_t buf[8]; #if defined(DEBUG_SUBPAGE) - printf("%s: subpage %p len %u addr " TARGET_FMT_plx + printf("%s: subpage %p len %u addr " HWADDR_FMT_plx " value %"PRIx64"\n", __func__, subpage, len, addr, value); #endif @@ -2507,7 +2507,7 @@ static bool subpage_accepts(void *opaque, hwaddr addr, { subpage_t *subpage = opaque; #if defined(DEBUG_SUBPAGE) - printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n", + printf("%s: subpage %p %c len %u addr " HWADDR_FMT_plx "\n", __func__, subpage, is_write ? 'w' : 'r', len, addr); #endif @@ -2558,7 +2558,7 @@ static subpage_t *subpage_init(FlatView *fv, hwaddr base) NULL, TARGET_PAGE_SIZE); mmio->iomem.subpage = true; #if defined(DEBUG_SUBPAGE) - printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__, + printf("%s: %p base " HWADDR_FMT_plx " len %08x\n", __func__, mmio, base, TARGET_PAGE_SIZE); #endif @@ -3703,7 +3703,7 @@ void mtree_print_dispatch(AddressSpaceDispatch *d, MemoryRegion *root) const char *names[] = { " [unassigned]", " [not dirty]", " [ROM]", " [watch]" }; - qemu_printf(" #%d @" TARGET_FMT_plx ".." TARGET_FMT_plx + qemu_printf(" #%d @" HWADDR_FMT_plx ".." HWADDR_FMT_plx " %s%s%s%s%s", i, s->offset_within_address_space, diff --git a/target/i386/monitor.c b/target/i386/monitor.c index 8e4b4d600c..ad5b7b8bb5 100644 --- a/target/i386/monitor.c +++ b/target/i386/monitor.c @@ -57,7 +57,7 @@ static void print_pte(Monitor *mon, CPUArchState *env, hwaddr addr, { addr = addr_canonical(env, addr); - monitor_printf(mon, TARGET_FMT_plx ": " TARGET_FMT_plx + monitor_printf(mon, HWADDR_FMT_plx ": " HWADDR_FMT_plx " %c%c%c%c%c%c%c%c%c\n", addr, pte & mask, @@ -258,8 +258,8 @@ static void mem_print(Monitor *mon, CPUArchState *env, prot1 = *plast_prot; if (prot != prot1) { if (*pstart != -1) { - monitor_printf(mon, TARGET_FMT_plx "-" TARGET_FMT_plx " " - TARGET_FMT_plx " %c%c%c\n", + monitor_printf(mon, HWADDR_FMT_plx "-" HWADDR_FMT_plx " " + HWADDR_FMT_plx " %c%c%c\n", addr_canonical(env, *pstart), addr_canonical(env, end), addr_canonical(env, end - *pstart), diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c index c6d1de50fe..cce1db1e0a 100644 --- a/target/loongarch/tlb_helper.c +++ b/target/loongarch/tlb_helper.c @@ -655,7 +655,7 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size, physical & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); qemu_log_mask(CPU_LOG_MMU, - "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx + "%s address=%" VADDR_PRIx " physical " HWADDR_FMT_plx " prot %d\n", __func__, address, physical, prot); return true; } else { diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 5b745d0928..f6378030b7 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -403,7 +403,7 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, CPUMBState *env = &cpu->env; qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx - " physaddr 0x" TARGET_FMT_plx " size %d access type %s\n", + " physaddr 0x" HWADDR_FMT_plx " size %d access type %s\n", addr, physaddr, size, access_type == MMU_INST_FETCH ? "INST_FETCH" : (access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE")); diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index 9d16859c0a..e5e1e9dd3f 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -924,7 +924,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, switch (ret) { case TLBRET_MATCH: qemu_log_mask(CPU_LOG_MMU, - "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx + "%s address=%" VADDR_PRIx " physical " HWADDR_FMT_plx " prot %d\n", __func__, address, physical, prot); break; default: diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index cc091c3e62..3976416840 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -346,24 +346,24 @@ static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu, ptem = (vsid << 7) | (pgidx >> 10); /* Page address translation */ - qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx - " htab_mask " TARGET_FMT_plx - " hash " TARGET_FMT_plx "\n", + qemu_log_mask(CPU_LOG_MMU, "htab_base " HWADDR_FMT_plx + " htab_mask " HWADDR_FMT_plx + " hash " HWADDR_FMT_plx "\n", ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), hash); /* Primary PTEG lookup */ - qemu_log_mask(CPU_LOG_MMU, "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, "0 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx " vsid=%" PRIx32 " ptem=%" PRIx32 - " hash=" TARGET_FMT_plx "\n", + " hash=" HWADDR_FMT_plx "\n", ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), vsid, ptem, hash); pteg_off = get_pteg_offset32(cpu, hash); pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 0, ptem, pte); if (pte_offset == -1) { /* Secondary PTEG lookup */ - qemu_log_mask(CPU_LOG_MMU, "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, "1 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx " vsid=%" PRIx32 " api=%" PRIx32 - " hash=" TARGET_FMT_plx "\n", ppc_hash32_hpt_base(cpu), + " hash=" HWADDR_FMT_plx "\n", ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), vsid, ptem, ~hash); pteg_off = get_pteg_offset32(cpu, ~hash); pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 1, ptem, pte); diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index b9b31fd276..900f906990 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -697,15 +697,15 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu, /* Page address translation */ qemu_log_mask(CPU_LOG_MMU, - "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx - " hash " TARGET_FMT_plx "\n", + "htab_base " HWADDR_FMT_plx " htab_mask " HWADDR_FMT_plx + " hash " HWADDR_FMT_plx "\n", ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), hash); /* Primary PTEG lookup */ qemu_log_mask(CPU_LOG_MMU, - "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx + "0 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx - " hash=" TARGET_FMT_plx "\n", + " hash=" HWADDR_FMT_plx "\n", ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), vsid, ptem, hash); ptex = ppc_hash64_pteg_search(cpu, hash, sps, ptem, pte, pshift); @@ -714,9 +714,9 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu, /* Secondary PTEG lookup */ ptem |= HPTE64_V_SECONDARY; qemu_log_mask(CPU_LOG_MMU, - "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx + "1 htab=" HWADDR_FMT_plx "/" HWADDR_FMT_plx " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx - " hash=" TARGET_FMT_plx "\n", ppc_hash64_hpt_base(cpu), + " hash=" HWADDR_FMT_plx "\n", ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), vsid, ptem, ~hash); ptex = ppc_hash64_pteg_search(cpu, ~hash, sps, ptem, pte, pshift); diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 8901f4d134..7235a4befe 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -252,7 +252,7 @@ static int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx, } if (best != -1) { done: - qemu_log_mask(CPU_LOG_MMU, "found TLB at addr " TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, "found TLB at addr " HWADDR_FMT_plx " prot=%01x ret=%d\n", ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); /* Update page flags */ @@ -328,7 +328,7 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, ctx->prot = prot; ret = check_prot(ctx->prot, access_type); if (ret == 0) { - qemu_log_mask(CPU_LOG_MMU, "BAT %d match: r " TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, "BAT %d match: r " HWADDR_FMT_plx " prot=%c%c\n", i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', ctx->prot & PAGE_WRITE ? 'W' : '-'); @@ -403,9 +403,9 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, /* Check if instruction fetch is allowed, if needed */ if (type != ACCESS_CODE || ctx->nx == 0) { /* Page address translation */ - qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx - " htab_mask " TARGET_FMT_plx - " hash " TARGET_FMT_plx "\n", + qemu_log_mask(CPU_LOG_MMU, "htab_base " HWADDR_FMT_plx + " htab_mask " HWADDR_FMT_plx + " hash " HWADDR_FMT_plx "\n", ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), hash); ctx->hash[0] = hash; ctx->hash[1] = ~hash; @@ -420,7 +420,7 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, hwaddr curaddr; uint32_t a0, a1, a2, a3; - qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx + qemu_log("Page table: " HWADDR_FMT_plx " len " HWADDR_FMT_plx "\n", ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu) + 0x80); for (curaddr = ppc_hash32_hpt_base(cpu); @@ -432,7 +432,7 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, a2 = ldl_phys(cs->as, curaddr + 8); a3 = ldl_phys(cs->as, curaddr + 12); if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) { - qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n", + qemu_log(HWADDR_FMT_plx ": %08x %08x %08x %08x\n", curaddr, a0, a1, a2, a3); } } @@ -578,14 +578,14 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, if (ret >= 0) { ctx->raddr = raddr; qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx - " => " TARGET_FMT_plx + " => " HWADDR_FMT_plx " %d %d\n", __func__, address, ctx->raddr, ctx->prot, ret); return 0; } } qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx - " => " TARGET_FMT_plx + " => " HWADDR_FMT_plx " %d %d\n", __func__, address, raddr, ctx->prot, ret); return ret; @@ -666,11 +666,11 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, if (ret >= 0) { ctx->raddr = raddr; qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx - " => " TARGET_FMT_plx " %d %d\n", __func__, + " => " HWADDR_FMT_plx " %d %d\n", __func__, address, ctx->raddr, ctx->prot, ret); } else { qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx - " => " TARGET_FMT_plx " %d %d\n", __func__, + " => " HWADDR_FMT_plx " %d %d\n", __func__, address, raddr, ctx->prot, ret); } @@ -894,11 +894,11 @@ found_tlb: if (ret >= 0) { ctx->raddr = raddr; qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx - " => " TARGET_FMT_plx " %d %d\n", __func__, address, + " => " HWADDR_FMT_plx " %d %d\n", __func__, address, ctx->raddr, ctx->prot, ret); } else { qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx - " => " TARGET_FMT_plx " %d %d\n", __func__, address, + " => " HWADDR_FMT_plx " %d %d\n", __func__, address, raddr, ctx->prot, ret); } diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 2a91f3f46a..64e30435f5 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -826,7 +826,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, tlb->prot &= ~PAGE_VALID; } tlb->PID = env->spr[SPR_40x_PID]; /* PID */ - qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " HWADDR_FMT_plx " EPN " TARGET_FMT_lx " size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__, (int)entry, tlb->RPN, tlb->EPN, tlb->size, @@ -864,7 +864,7 @@ void helper_4xx_tlbwe_lo(CPUPPCState *env, target_ulong entry, if (val & PPC4XX_TLBLO_WR) { tlb->prot |= PAGE_WRITE; } - qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " HWADDR_FMT_plx " EPN " TARGET_FMT_lx " size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__, (int)entry, tlb->RPN, tlb->EPN, tlb->size, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8ea3442b4a..9a28816521 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1272,7 +1272,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " - TARGET_FMT_plx " prot %d\n", + HWADDR_FMT_plx " prot %d\n", __func__, address, ret, pa, prot); if (ret == TRANSLATE_SUCCESS) { @@ -1285,7 +1285,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " - TARGET_FMT_plx " prot %d\n", + HWADDR_FMT_plx " prot %d\n", __func__, im_address, ret, pa, prot2); prot &= prot2; @@ -1295,7 +1295,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, size, access_type, mode); qemu_log_mask(CPU_LOG_MMU, - "%s PMP address=" TARGET_FMT_plx " ret %d prot" + "%s PMP address=" HWADDR_FMT_plx " ret %d prot" " %d tlb_size " TARGET_FMT_lu "\n", __func__, pa, ret, prot_pmp, tlb_size); @@ -1320,7 +1320,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "%s address=%" VADDR_PRIx " ret %d physical " - TARGET_FMT_plx " prot %d\n", + HWADDR_FMT_plx " prot %d\n", __func__, address, ret, pa, prot); if (ret == TRANSLATE_SUCCESS) { @@ -1328,7 +1328,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, size, access_type, mode); qemu_log_mask(CPU_LOG_MMU, - "%s PMP address=" TARGET_FMT_plx " ret %d prot" + "%s PMP address=" HWADDR_FMT_plx " ret %d prot" " %d tlb_size " TARGET_FMT_lu "\n", __func__, pa, ret, prot_pmp, tlb_size); diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index 17e63fab00..236f93b9f5 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -64,7 +64,7 @@ static void print_pte(Monitor *mon, int va_bits, target_ulong vaddr, return; } - monitor_printf(mon, TARGET_FMT_lx " " TARGET_FMT_plx " " TARGET_FMT_lx + monitor_printf(mon, TARGET_FMT_lx " " HWADDR_FMT_plx " " TARGET_FMT_lx " %c%c%c%c%c%c%c\n", addr_canonical(va_bits, vaddr), paddr, size, diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index ec4fae78c3..a53580d9e4 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -430,12 +430,12 @@ static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, #ifdef DEBUG_UNASSIGNED if (is_asi) { - printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx + printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx " asi 0x%02x from " TARGET_FMT_lx "\n", is_exec ? "exec" : is_write ? "write" : "read", size, size == 1 ? "" : "s", addr, is_asi, env->pc); } else { - printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx + printf("Unassigned mem %s access of %d byte%s to " HWADDR_FMT_plx " from " TARGET_FMT_lx "\n", is_exec ? "exec" : is_write ? "write" : "read", size, size == 1 ? "" : "s", addr, env->pc); @@ -490,7 +490,7 @@ static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, CPUSPARCState *env = &cpu->env; #ifdef DEBUG_UNASSIGNED - printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx + printf("Unassigned mem access to " HWADDR_FMT_plx " from " TARGET_FMT_lx "\n", addr, env->pc); #endif diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 919448a494..158ec2ae8f 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -230,7 +230,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (likely(error_code == 0)) { qemu_log_mask(CPU_LOG_MMU, "Translate at %" VADDR_PRIx " -> " - TARGET_FMT_plx ", vaddr " TARGET_FMT_lx "\n", + HWADDR_FMT_plx ", vaddr " TARGET_FMT_lx "\n", address, paddr, vaddr); tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); return true; @@ -356,27 +356,27 @@ void dump_mmu(CPUSPARCState *env) hwaddr pa; uint32_t pde; - qemu_printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n", + qemu_printf("Root ptr: " HWADDR_FMT_plx ", ctx: %d\n", (hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]); for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { pde = mmu_probe(env, va, 2); if (pde) { pa = cpu_get_phys_page_debug(cs, va); - qemu_printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx + qemu_printf("VA: " TARGET_FMT_lx ", PA: " HWADDR_FMT_plx " PDE: " TARGET_FMT_lx "\n", va, pa, pde); for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { pde = mmu_probe(env, va1, 1); if (pde) { pa = cpu_get_phys_page_debug(cs, va1); qemu_printf(" VA: " TARGET_FMT_lx ", PA: " - TARGET_FMT_plx " PDE: " TARGET_FMT_lx "\n", + HWADDR_FMT_plx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde); for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { pde = mmu_probe(env, va2, 0); if (pde) { pa = cpu_get_phys_page_debug(cs, va2); qemu_printf(" VA: " TARGET_FMT_lx ", PA: " - TARGET_FMT_plx " PTE: " + HWADDR_FMT_plx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde); } diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 1db32808e8..114685cce4 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -79,7 +79,7 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, address, rw, mmu_idx); qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical " - TARGET_FMT_plx " prot %d\n", + HWADDR_FMT_plx " prot %d\n", __func__, (target_ulong)address, ret, physical, prot); if (ret == TLBRET_MATCH) { -- 2.38.1 From MAILER-DAEMON Tue Jan 10 17:04:23 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFMjH-0003FC-2G for mharc-qemu-riscv@gnu.org; Tue, 10 Jan 2023 17:04:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFMjE-00034P-2f; Tue, 10 Jan 2023 17:04:20 -0500 Received: from zero.eik.bme.hu ([152.66.115.2]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFMjB-0004bL-UP; Tue, 10 Jan 2023 17:04:19 -0500 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id 3ACFA745712; Tue, 10 Jan 2023 23:01:53 +0100 (CET) Received: by zero.eik.bme.hu (Postfix, from userid 432) id F3B30745706; Tue, 10 Jan 2023 23:01:52 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by zero.eik.bme.hu (Postfix) with ESMTP id F05E37456E3; Tue, 10 Jan 2023 23:01:52 +0100 (CET) Date: Tue, 10 Jan 2023 23:01:52 +0100 (CET) From: BALATON Zoltan To: =?ISO-8859-15?Q?Philippe_Mathieu-Daud=E9?= cc: qemu-devel@nongnu.org, Peter Maydell , qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , =?ISO-8859-15?Q?Alex_Benn=E9e?= , ale@rev.ng, qemu-riscv@nongnu.org, xen-devel@lists.xenproject.org, Thomas Huth Subject: Re: [PATCH] bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx In-Reply-To: <20230110212947.34557-1-philmd@linaro.org> Message-ID: References: <20230110212947.34557-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="3866299591-1251169997-1673388112=:35553" X-Spam-Probability: 9% Received-SPF: pass client-ip=152.66.115.2; envelope-from=balaton@eik.bme.hu; helo=zero.eik.bme.hu X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 22:04:21 -0000 This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. --3866299591-1251169997-1673388112=:35553 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8BIT On Tue, 10 Jan 2023, Philippe Mathieu-Daudé wrote: > The 'hwaddr' type is defined in "exec/hwaddr.h" as: > > hwaddr is the type of a physical address > (its size can be different from 'target_ulong'). > > All definitions use the 'HWADDR_' prefix, except TARGET_FMT_plx: > > $ fgrep define include/exec/hwaddr.h > #define HWADDR_H > #define HWADDR_BITS 64 > #define HWADDR_MAX UINT64_MAX > #define TARGET_FMT_plx "%016" PRIx64 > ^^^^^^ > #define HWADDR_PRId PRId64 > #define HWADDR_PRIi PRIi64 > #define HWADDR_PRIo PRIo64 > #define HWADDR_PRIu PRIu64 > #define HWADDR_PRIx PRIx64 Why are there both TARGET_FMT_plx and HWADDR_PRIx? Why not just use HWADDR_PRIx instead? Regards, BALATON Zoltan --3866299591-1251169997-1673388112=:35553-- From MAILER-DAEMON Tue Jan 10 17:27:28 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFN5c-0004w0-IS for mharc-qemu-riscv@gnu.org; Tue, 10 Jan 2023 17:27:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFN5a-0004vP-Gr for qemu-riscv@nongnu.org; Tue, 10 Jan 2023 17:27:26 -0500 Received: from mail-oi1-x242.google.com ([2607:f8b0:4864:20::242]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFN5X-0000CN-8f for qemu-riscv@nongnu.org; Tue, 10 Jan 2023 17:27:26 -0500 Received: by mail-oi1-x242.google.com with SMTP id h185so11349383oif.5 for ; Tue, 10 Jan 2023 14:27:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=IpoeC3L4roef9zj3oNJSECsxwrRb8L77/kWW9Ca4OjE=; b=M3bRd1KXmm1YAUUllfmPJS91n25kMXC0NzesyNd4hB4Uq5/95W1NObH5bRz5iHBQQN FvcId6jogwG4DMgPq1LAFqr2PdpyAx9hHLt7NL1LTgma0nSB1/EDGg1EwPGHi8m7ihCY Gdq/mnIvFDplKqDQUJCvNIP5+05E4UeoIgOExjENpacBaOwuzeXc+wUAGp70um14hyQB Tk8MF4F8jnqai+idLFE0Y8/dZCWIf7JIrGBhKmJ2OCQQndaH85yls1SCWA/MdSY+QTHT l3pKG2rDW5J59hnBhnRyJuhmJSmaJPPoWIp7Aoi9e9fvBfkQtSsPABA56IE0VTuEVAT5 pqXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=IpoeC3L4roef9zj3oNJSECsxwrRb8L77/kWW9Ca4OjE=; b=cHFdV2PAjic3GDomktY91sUut8OE4zyPS5c5uyXyrvCIr4wV1ThjIs4IsAmphJlZPe 1lr48OR35eF7RZnOr2bEiiptx4fHMEaDDn+Tpzw4pjrgYGIqP+QlQ05DdjMaqUciU2jQ u45+v5PgO3J4skIL1h5Jf10mw2esrjtfPi0mRKXGaruaFXrVJarUuCcnC9Qp266RKsJL PhSJJ448qBuXqauwLAaEjXAjWIIw9+PgZn5p7aXXW3CyjsFV4vsBp8yjQ7FUA02N6vrB KJM07o259ttRGFai+YDySevHlO1JoCnYn12WvLB+jULaKeqIpDJJDn//9IIZH7IjXKng S8HQ== X-Gm-Message-State: AFqh2krntDUrYfQDLbrIm7jxak0yeGVB1ry+kB4g7Iq5A8GbzA2hQSh7 4jETsgrOVXsBIQ6XN01E+oy1Qg== X-Google-Smtp-Source: AMrXdXulFaF1xAqbNuVt6XDKi3TPC5Ums6arIcqg6x2+83NkwYTQ1ABQ8zajgXQmCYb8JYFYDTtfQA== X-Received: by 2002:a54:400b:0:b0:364:5ec5:bc with SMTP id x11-20020a54400b000000b003645ec500bcmr1565594oie.59.1673389641593; Tue, 10 Jan 2023 14:27:21 -0800 (PST) Received: from [192.168.68.107] ([152.250.93.24]) by smtp.gmail.com with ESMTPSA id g19-20020a544f93000000b00363ef79e2a1sm5876316oiy.31.2023.01.10.14.27.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Jan 2023 14:27:21 -0800 (PST) Message-ID: <2613669e-f535-e91d-14b8-5968094877eb@ventanamicro.com> Date: Tue, 10 Jan 2023 19:27:18 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH 0/2] target/riscv/cpu: fix sifive_u 32/64bits boot in riscv-to-apply.next To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, richard.henderson@linaro.org References: <20230110201405.247785-1-dbarboza@ventanamicro.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20230110201405.247785-1-dbarboza@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::242; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x242.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 22:27:26 -0000 Hi, I mentioned that the bug were found in riscv-to-apply.next but forgot to mentioned that the patches were also based on top of it as well: https://github.com/alistair23/qemu/tree/riscv-to-apply.next Thanks, Daniel On 1/10/23 17:14, Daniel Henrique Barboza wrote: > Hi, > > I found this bug when testing my avocado changes in riscv-to-apply.next. > The sifive_u board, both 32 and 64 bits, stopped booting OpenSBI. The > guest hangs indefinitely. > > Git bisect points that this patch broke things: > > 8c3f35d25e7e98655c609b6c1e9f103b9240f8f8 is the first bad commit > commit 8c3f35d25e7e98655c609b6c1e9f103b9240f8f8 > Author: Weiwei Li > Date: Wed Dec 28 14:20:21 2022 +0800 > > target/riscv: add support for Zca extension > > Modify the check for C extension to Zca (C implies Zca) > (https://github.com/alistair23/qemu/commit/8c3f35d25e7e98655c609b6c1e9f103b9240f8f8) > > > But this patch per se isn't doing anything wrong. The root of the > problem is that this patch makes assumptions based on the previous > patch: > > commit a2b409aa6cadc1ed9715e1ab916ddd3dade0ba85 > Author: Weiwei Li > Date: Wed Dec 28 14:20:20 2022 +0800 > > target/riscv: add cfg properties for Zc* extension > (https://github.com/alistair23/qemu/commit/a2b409aa6cadc1ed9715e1ab916ddd3dade0ba85) > > Which added a lot of logic and assumptions that are being skipped by all > the SiFive boards because, during riscv_cpu_realize(), we have this > code: > > /* If only MISA_EXT is unset for misa, then set it from properties */ > if (env->misa_ext == 0) { > uint32_t ext = 0; > (...) > } > > In short, we have a lot of code that are being skipped by all SiFive > CPUs because these CPUs are setting a non-zero value in set_misa() in > their respective cpu_init() functions. > > It's possible to just hack in and fix the SiFive problem in isolate, but > I believe we can do better and allow all riscv_cpu_realize() to be executed > for all CPUs, regardless of what they've done during their cpu_init(). > > > Daniel Henrique Barboza (2): > target/riscv/cpu: set cpu->cfg in register_cpu_props() > target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() > > target/riscv/cpu.c | 525 +++++++++++++++++++++++++-------------------- > target/riscv/cpu.h | 4 + > 2 files changed, 292 insertions(+), 237 deletions(-) > From MAILER-DAEMON Tue Jan 10 17:29:26 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFN7W-00067i-FA for mharc-qemu-riscv@gnu.org; Tue, 10 Jan 2023 17:29:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFN7R-00067B-Kb; Tue, 10 Jan 2023 17:29:25 -0500 Received: from mail-vs1-xe33.google.com ([2607:f8b0:4864:20::e33]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFN7P-0000LU-Or; Tue, 10 Jan 2023 17:29:21 -0500 Received: by mail-vs1-xe33.google.com with SMTP id k6so4954375vsk.1; Tue, 10 Jan 2023 14:29:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=AMTa7aBqaL3uQUzX7PE4u+15twaGBTQEG00lBfyFRxQ=; b=OKYbKGKoJOjCQHDFJ7AeSHK4c4ZBUTxlokCLZthcJxKho7tdkArc5Kg0FPJuYC6KCR BkfQlxsMy+I0LqEsbvZDO/28Z8v36MQTHqz6u3V6RyFt01CqcRQhCnPO1Z1zk1d9gGEU uN3x8PIm7YX1J1K7spGQAhgisgxBtUsoZsNWx1qQTELwDERdmgODQ1b6T+p3BRSxxFx0 Rae7PLBC6Qw/0Xj0Ou9Y/BJbyw2gd/8MwzPgtuvHqBXuElF5dO9gorW8iEcIxVrZqEsl 9Cn26S4pCCzsu7vrPiBVvvulzAZnbNl10Htdr74v8n7gnGnrIwkg4rB48oOi2YVO8d9w AQEw== X-Google-DKIM-Signature: v=1; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e33; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe33.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 22:29:25 -0000 On Mon, Jan 2, 2023 at 9:53 PM Daniel Henrique Barboza wrote: > > This test is used to do a quick sanity check to ensure that we're able > to run the existing QEMU FW image. > > 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and > 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | > RISCV32_BIOS_BIN firmware with minimal options. > > The riscv32 'spike' machine isn't bootable at this moment, requiring an > OpenSBI fix [1] and QEMU side changes [2]. We could just leave at that > or add a 'skip' test to remind us about it. To work as a reminder that > we have a riscv32 'spike' test that should be enabled as soon as OpenSBI > QEMU rom receives the fix, we're adding a 'skip' test: > > (06/18) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv32_spike: > SKIP: requires OpenSBI fix to work > > [1] https://patchwork.ozlabs.org/project/opensbi/patch/20221226033603.186= 0569-1-bmeng@tinylab.org/ > [2] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=3D334159 > > Cc: Cleber Rosa > Cc: Philippe Mathieu-Daud=C3=A9 > Reviewed-by: Bin Meng > Tested-by: Bin Meng > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Signed-off-by: Daniel Henrique Barboza Acked-by: Alistair Francis Alistair > --- > tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ > 1 file changed, 65 insertions(+) > create mode 100644 tests/avocado/riscv_opensbi.py > > diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi= .py > new file mode 100644 > index 0000000000..e02f0d404a > --- /dev/null > +++ b/tests/avocado/riscv_opensbi.py > @@ -0,0 +1,65 @@ > +# OpenSBI boot test for RISC-V machines > +# > +# Copyright (c) 2022, Ventana Micro > +# > +# This work is licensed under the terms of the GNU GPL, version 2 or > +# later. See the COPYING file in the top-level directory. > + > +from avocado_qemu import QemuSystemTest > +from avocado import skip > +from avocado_qemu import wait_for_console_pattern > + > +class RiscvOpenSBI(QemuSystemTest): > + """ > + :avocado: tags=3Daccel:tcg > + """ > + timeout =3D 5 > + > + def boot_opensbi(self): > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + @skip("requires OpenSBI fix to work") > + def test_riscv32_spike(self): > + """ > + :avocado: tags=3Darch:riscv32 > + :avocado: tags=3Dmachine:spike > + """ > + self.boot_opensbi() > + > + def test_riscv64_spike(self): > + """ > + :avocado: tags=3Darch:riscv64 > + :avocado: tags=3Dmachine:spike > + """ > + self.boot_opensbi() > + > + def test_riscv32_sifive_u(self): > + """ > + :avocado: tags=3Darch:riscv32 > + :avocado: tags=3Dmachine:sifive_u > + """ > + self.boot_opensbi() > + > + def test_riscv64_sifive_u(self): > + """ > + :avocado: tags=3Darch:riscv64 > + :avocado: tags=3Dmachine:sifive_u > + """ > + self.boot_opensbi() > + > + def test_riscv32_virt(self): > + """ > + :avocado: tags=3Darch:riscv32 > + :avocado: tags=3Dmachine:virt > + """ > + self.boot_opensbi() > + > + def test_riscv64_virt(self): > + """ > + :avocado: tags=3Darch:riscv64 > + :avocado: tags=3Dmachine:virt > + """ > + self.boot_opensbi() > -- > 2.39.0 > > From MAILER-DAEMON Tue Jan 10 17:30:30 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFN8X-0006p6-Sa for mharc-qemu-riscv@gnu.org; Tue, 10 Jan 2023 17:30:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFN8U-0006ok-Qz; Tue, 10 Jan 2023 17:30:26 -0500 Received: from mail-vs1-xe2c.google.com ([2607:f8b0:4864:20::e2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFN8T-0000i2-5G; Tue, 10 Jan 2023 17:30:26 -0500 Received: by mail-vs1-xe2c.google.com with SMTP id s127so13869492vsb.5; Tue, 10 Jan 2023 14:30:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=KYkPNorHCkymo59gv9B+edmPjN+mghN54XIdHSXJc4U=; b=V9gumePgsTVkFUjvBD4RGheuEhtzTLoPYKgVMpSRyvSclNl/1u+MyaVCr5RvJFvguc YwzCnLJr6d0xeO07h8OFoy80xSeMVa8jyw0r0RqrN/PRXcerUGmYW/+vj2Q6pNFeH7Rq EKCzK7p6AT5jW7HCp0Jz5ynqx6Go9gw9/DhHpsD0/UQoO1F0xOwm5oJCPGQ3wMOV7e/2 ywv2w8FrMTjR6koOqXajl6OjAcIpQ3LrH+PK8tAH0dqYTPWUumTpKnfiy5t7zjteGDdG PKRkmRsq+nEo+HX9iQRIXXncwkVq4fCOAofW3KuPvH4zkFZQPw9+dbyrRCRYMcmxJ4ob hJNw== X-Google-DKIM-Signature: v=1; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e2c; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 22:30:27 -0000 On Mon, Jan 2, 2023 at 9:54 PM Daniel Henrique Barboza wrote: > > riscv_load_firmware(), riscv_load_initrd() and riscv_load_kernel() works > under the assumption that a 'filename' parameter is always not NULL. > > This is currently the case since all callers of these functions are > checking for NULL before calling them. Add an g_assert() to make sure > that a NULL value in these cases are to be considered a bug. > > Suggested-by: Alex Benn=C3=A9e > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/boot.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 98b80af51b..31aa3385a0 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -153,6 +153,8 @@ target_ulong riscv_load_firmware(const char *firmware= _filename, > uint64_t firmware_entry, firmware_end; > ssize_t firmware_size; > > + g_assert(firmware_filename !=3D NULL); > + > if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL, > &firmware_entry, NULL, &firmware_end, NULL, > 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { > @@ -177,6 +179,8 @@ target_ulong riscv_load_kernel(const char *kernel_fil= ename, > { > uint64_t kernel_load_base, kernel_entry; > > + g_assert(kernel_filename !=3D NULL); > + > /* > * NB: Use low address not ELF entry point to ensure that the fw_dyn= amic > * behaviour when loading an ELF matches the fw_payload, fw_jump and= BBL > @@ -209,6 +213,8 @@ hwaddr riscv_load_initrd(const char *filename, uint64= _t mem_size, > { > ssize_t size; > > + g_assert(filename !=3D NULL); > + > /* > * We want to put the initrd far enough into RAM that when the > * kernel is uncompressed it will not clobber the initrd. However > -- > 2.39.0 > > From MAILER-DAEMON Tue Jan 10 17:36:42 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFNEX-0008MN-Nd for mharc-qemu-riscv@gnu.org; Tue, 10 Jan 2023 17:36:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFNEW-0008Lw-LU; Tue, 10 Jan 2023 17:36:40 -0500 Received: from mail-ua1-x929.google.com ([2607:f8b0:4864:20::929]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFNEA-0001fw-TN; Tue, 10 Jan 2023 17:36:30 -0500 Received: by mail-ua1-x929.google.com with SMTP id f5so658581ual.12; Tue, 10 Jan 2023 14:36:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=5o1iM8WV6kYSSryloRh/fSYsaulQuQaXW+NBbzBSQGE=; b=MNKZ7Jl13uZCnBg6hE5UvfHWs4K8hMXb3R74dbflfelQrG1Xw5TgMD8iP345nmSG/u GAk4PKx1QdISuURWJi5Nip7a8ozvgJqfuGWxPsX2oKqKUpEDT0HeNNXm2Y0ihz0QsHNl 3E5teLY2S6/OZzSC0ArD+SPP+sWU5UkGvz8wJBzqJkY+GO5o2F5kiPNfDk8l2BRqe/kT zsQp1XdRDPePL1uUfIR+Js0fp54TwQ8KQAzuOKFt9/UUYtRISQ57BwjLsmGKJedrBKcD IxJC47/gBe/DVY31NHgwoH7x9Aq9f0WTaem570Q3vzIb8OKwzyS7Yw4Ony7EPmdQsz62 NYyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5o1iM8WV6kYSSryloRh/fSYsaulQuQaXW+NBbzBSQGE=; b=Jgh+a50MIXFOiKzIe75dAl7un7tQA1icTdjVy00rl0onZ4YAuxbkczwBUcprC+2hXm /26F9mSuHPjeefxu3zjBqyYLPVwfQCT6XP47AHz7r4vXozOX3AZLUAZqemtzXMtrj6we Ur1f/u4PtxjpRHCAbyDMBswJMdWEOFW1KhUchtLXCfckZRZOIWAOHcPLu9pZKspzBfUz 5AMoB+tCV01LYRIAihv0k0keB8I0AYJ8lAPtjypnAxaR67ucclc3k75wIc0HU0Ey3nKs GFZ4p9dan9+UZpCP+o6AWxy4jPNfPeQsRFrprORtBdfJMSDzgtl7C/C1rfHbV2ijq6pG Rh5Q== X-Gm-Message-State: AFqh2kpdUINz5eMxUQ7CjlAy9z+7XOqLIkEqTeHMl/Mvna9AayvNJCVT qZnwtD+Tc2YS1oh7y6kCRtSr/5HSwbQy9ke/APM= X-Google-Smtp-Source: AMrXdXv0vXkzN8xEU8N/XbLKeySxo2qc+jc0WlPj/Rluah/4nCzaPT+/23zMMxGVE+lyrllJa0x0WrUCKfM+CDcgh4c= X-Received: by 2002:a9f:3191:0:b0:419:1fa3:9618 with SMTP id v17-20020a9f3191000000b004191fa39618mr8644202uad.11.1673390177273; Tue, 10 Jan 2023 14:36:17 -0800 (PST) MIME-Version: 1.0 References: <20230102115241.25733-1-dbarboza@ventanamicro.com> <20230102115241.25733-7-dbarboza@ventanamicro.com> In-Reply-To: <20230102115241.25733-7-dbarboza@ventanamicro.com> From: Alistair Francis Date: Wed, 11 Jan 2023 08:35:51 +1000 Message-ID: Subject: Re: [PATCH v5 06/11] hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng , Palmer Dabbelt , Bin Meng , =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::929; envelope-from=alistair23@gmail.com; helo=mail-ua1-x929.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 22:36:41 -0000 On Mon, Jan 2, 2023 at 9:54 PM Daniel Henrique Barboza wrote: > > riscv_load_initrd() returns the initrd end addr while also writing a > 'start' var to mark the addr start. These informations are being used > just to write the initrd FDT node. Every existing caller of > riscv_load_initrd() is writing the FDT in the same manner. > > We can simplify things by writing the FDT inside riscv_load_initrd(), > sparing callers from having to manage start/end addrs to write the FDT > themselves. > > An 'if (fdt)' check is already inserted at the end of the function > because we'll end up using it later on with other boards that doesn=C2=B4= t > have a FDT. > > Cc: Palmer Dabbelt > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Bin Meng > Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/boot.c | 18 ++++++++++++------ > hw/riscv/microchip_pfsoc.c | 10 ++-------- > hw/riscv/sifive_u.c | 10 ++-------- > hw/riscv/spike.c | 10 ++-------- > hw/riscv/virt.c | 10 ++-------- > include/hw/riscv/boot.h | 4 ++-- > 6 files changed, 22 insertions(+), 40 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 31aa3385a0..6b948d1c9e 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -208,9 +208,10 @@ target_ulong riscv_load_kernel(const char *kernel_fi= lename, > exit(1); > } > > -hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, > - uint64_t kernel_entry, hwaddr *start) > +void riscv_load_initrd(const char *filename, uint64_t mem_size, > + uint64_t kernel_entry, void *fdt) > { > + hwaddr start, end; > ssize_t size; > > g_assert(filename !=3D NULL); > @@ -226,18 +227,23 @@ hwaddr riscv_load_initrd(const char *filename, uint= 64_t mem_size, > * halfway into RAM, and for boards with 256MB of RAM or more we put > * the initrd at 128MB. > */ > - *start =3D kernel_entry + MIN(mem_size / 2, 128 * MiB); > + start =3D kernel_entry + MIN(mem_size / 2, 128 * MiB); > > - size =3D load_ramdisk(filename, *start, mem_size - *start); > + size =3D load_ramdisk(filename, start, mem_size - start); > if (size =3D=3D -1) { > - size =3D load_image_targphys(filename, *start, mem_size - *start= ); > + size =3D load_image_targphys(filename, start, mem_size - start); > if (size =3D=3D -1) { > error_report("could not load ramdisk '%s'", filename); > exit(1); > } > } > > - return *start + size; > + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ > + if (fdt) { > + end =3D start + size; > + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", star= t); > + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); > + } > } > > uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index b10321b564..593a799549 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -633,14 +633,8 @@ static void microchip_icicle_kit_machine_init(Machin= eState *machine) > kernel_start_addr, NULL); > > if (machine->initrd_filename) { > - hwaddr start; > - hwaddr end =3D riscv_load_initrd(machine->initrd_filename, > - machine->ram_size, kernel_ent= ry, > - &start); > - qemu_fdt_setprop_cell(machine->fdt, "/chosen", > - "linux,initrd-start", start); > - qemu_fdt_setprop_cell(machine->fdt, "/chosen", > - "linux,initrd-end", end); > + riscv_load_initrd(machine->initrd_filename, machine->ram_siz= e, > + kernel_entry, machine->fdt); > } > > if (machine->kernel_cmdline && *machine->kernel_cmdline) { > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index ddceb750ea..37f5087172 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -608,14 +608,8 @@ static void sifive_u_machine_init(MachineState *mach= ine) > kernel_start_addr, NULL); > > if (machine->initrd_filename) { > - hwaddr start; > - hwaddr end =3D riscv_load_initrd(machine->initrd_filename, > - machine->ram_size, kernel_ent= ry, > - &start); > - qemu_fdt_setprop_cell(machine->fdt, "/chosen", > - "linux,initrd-start", start); > - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd= -end", > - end); > + riscv_load_initrd(machine->initrd_filename, machine->ram_siz= e, > + kernel_entry, machine->fdt); > } > } else { > /* > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index 004dfb2d5b..5668fe0694 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -316,14 +316,8 @@ static void spike_board_init(MachineState *machine) > htif_symbol_callback); > > if (machine->initrd_filename) { > - hwaddr start; > - hwaddr end =3D riscv_load_initrd(machine->initrd_filename, > - machine->ram_size, kernel_ent= ry, > - &start); > - qemu_fdt_setprop_cell(machine->fdt, "/chosen", > - "linux,initrd-start", start); > - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd= -end", > - end); > + riscv_load_initrd(machine->initrd_filename, machine->ram_siz= e, > + kernel_entry, machine->fdt); > } > } else { > /* > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 408f7a2256..5967b136b4 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -1291,14 +1291,8 @@ static void virt_machine_done(Notifier *notifier, = void *data) > kernel_start_addr, NULL); > > if (machine->initrd_filename) { > - hwaddr start; > - hwaddr end =3D riscv_load_initrd(machine->initrd_filename, > - machine->ram_size, kernel_ent= ry, > - &start); > - qemu_fdt_setprop_cell(machine->fdt, "/chosen", > - "linux,initrd-start", start); > - qemu_fdt_setprop_cell(machine->fdt, "/chosen", "linux,initrd= -end", > - end); > + riscv_load_initrd(machine->initrd_filename, machine->ram_siz= e, > + kernel_entry, machine->fdt); > } > } else { > /* > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h > index b273ab22f7..e37e1d1238 100644 > --- a/include/hw/riscv/boot.h > +++ b/include/hw/riscv/boot.h > @@ -46,8 +46,8 @@ target_ulong riscv_load_firmware(const char *firmware_f= ilename, > target_ulong riscv_load_kernel(const char *kernel_filename, > target_ulong firmware_end_addr, > symbol_fn_t sym_cb); > -hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, > - uint64_t kernel_entry, hwaddr *start); > +void riscv_load_initrd(const char *filename, uint64_t mem_size, > + uint64_t kernel_entry, void *fdt); > uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt= ); > void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayStat= e *harts, > hwaddr saddr, > -- > 2.39.0 > > From MAILER-DAEMON Tue Jan 10 17:38:13 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFNFz-00011D-Kd for mharc-qemu-riscv@gnu.org; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e32; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe32.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 22:38:10 -0000 On Mon, Jan 2, 2023 at 9:55 PM Daniel Henrique Barboza wrote: > > The sifive_u, spike and virt machines are writing the 'bootargs' FDT > node during their respective create_fdt(). > > Given that bootargs is written only when '-append' is used, and this > option is only allowed with the '-kernel' option, which in turn is > already being check before executing riscv_load_kernel(), write > 'bootargs' in the same code path as riscv_load_kernel(). > > Cc: Palmer Dabbelt > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Bin Meng > Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/sifive_u.c | 11 +++++------ > hw/riscv/spike.c | 9 +++++---- > hw/riscv/virt.c | 11 +++++------ > 3 files changed, 15 insertions(+), 16 deletions(-) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 37f5087172..3e6df87b5b 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -117,7 +117,6 @@ static void create_fdt(SiFiveUState *s, const MemMapE= ntry *memmap, > error_report("load_device_tree() failed"); > exit(1); > } > - goto update_bootargs; > } else { > fdt =3D ms->fdt =3D create_device_tree(&fdt_size); > if (!fdt) { > @@ -510,11 +509,6 @@ static void create_fdt(SiFiveUState *s, const MemMap= Entry *memmap, > qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); > > g_free(nodename); > - > -update_bootargs: > - if (cmdline && *cmdline) { > - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); > - } > } > > static void sifive_u_machine_reset(void *opaque, int n, int level) > @@ -611,6 +605,11 @@ static void sifive_u_machine_init(MachineState *mach= ine) > riscv_load_initrd(machine->initrd_filename, machine->ram_siz= e, > kernel_entry, machine->fdt); > } > + > + if (machine->kernel_cmdline && *machine->kernel_cmdline) { > + qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", > + machine->kernel_cmdline); > + } > } else { > /* > * If dynamic firmware is used, it doesn't know where is the next= mode > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index 5668fe0694..60e2912be5 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -179,10 +179,6 @@ static void create_fdt(SpikeState *s, const MemMapEn= try *memmap, > > qemu_fdt_add_subnode(fdt, "/chosen"); > qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); > - > - if (cmdline && *cmdline) { > - qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); > - } > } > > static bool spike_test_elf_image(char *filename) > @@ -319,6 +315,11 @@ static void spike_board_init(MachineState *machine) > riscv_load_initrd(machine->initrd_filename, machine->ram_siz= e, > kernel_entry, machine->fdt); > } > + > + if (machine->kernel_cmdline && *machine->kernel_cmdline) { > + qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", > + machine->kernel_cmdline); > + } > } else { > /* > * If dynamic firmware is used, it doesn't know where is the next= mode > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 5967b136b4..6c946b6def 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -1012,7 +1012,6 @@ static void create_fdt(RISCVVirtState *s, const Mem= MapEntry *memmap, > error_report("load_device_tree() failed"); > exit(1); > } > - goto update_bootargs; > } else { > mc->fdt =3D create_device_tree(&s->fdt_size); > if (!mc->fdt) { > @@ -1050,11 +1049,6 @@ static void create_fdt(RISCVVirtState *s, const Me= mMapEntry *memmap, > create_fdt_fw_cfg(s, memmap); > create_fdt_pmu(s); > > -update_bootargs: > - if (cmdline && *cmdline) { > - qemu_fdt_setprop_string(mc->fdt, "/chosen", "bootargs", cmdline)= ; > - } > - > /* Pass seed to RNG */ > qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); > qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rn= g_seed)); > @@ -1294,6 +1288,11 @@ static void virt_machine_done(Notifier *notifier, = void *data) > riscv_load_initrd(machine->initrd_filename, machine->ram_siz= e, > kernel_entry, machine->fdt); > } > + > + if (machine->kernel_cmdline && *machine->kernel_cmdline) { > + qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", > + machine->kernel_cmdline); > + } > } else { > /* > * If dynamic firmware is used, it doesn't know where is the next= mode > -- > 2.39.0 > > From MAILER-DAEMON Tue Jan 10 17:39:47 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFNHX-0001oJ-85 for mharc-qemu-riscv@gnu.org; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::92f; envelope-from=alistair23@gmail.com; helo=mail-ua1-x92f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 22:39:46 -0000 On Mon, Jan 2, 2023 at 9:55 PM Daniel Henrique Barboza wrote: > > 'filename', 'mem_size' and 'fdt' from riscv_load_initrd() can all be > retrieved by the MachineState object for all callers. > > Cc: Palmer Dabbelt > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/boot.c | 6 ++++-- > hw/riscv/microchip_pfsoc.c | 3 +-- > hw/riscv/sifive_u.c | 3 +-- > hw/riscv/spike.c | 3 +-- > hw/riscv/virt.c | 3 +-- > include/hw/riscv/boot.h | 3 +-- > 6 files changed, 9 insertions(+), 12 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 6b948d1c9e..d3e780c3b6 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -208,9 +208,11 @@ target_ulong riscv_load_kernel(const char *kernel_fi= lename, > exit(1); > } > > -void riscv_load_initrd(const char *filename, uint64_t mem_size, > - uint64_t kernel_entry, void *fdt) > +void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) > { > + const char *filename =3D machine->initrd_filename; > + uint64_t mem_size =3D machine->ram_size; > + void *fdt =3D machine->fdt; > hwaddr start, end; > ssize_t size; > > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index 593a799549..1e9b0a420e 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -633,8 +633,7 @@ static void microchip_icicle_kit_machine_init(Machine= State *machine) > kernel_start_addr, NULL); > > if (machine->initrd_filename) { > - riscv_load_initrd(machine->initrd_filename, machine->ram_siz= e, > - kernel_entry, machine->fdt); > + riscv_load_initrd(machine, kernel_entry); > } > > if (machine->kernel_cmdline && *machine->kernel_cmdline) { > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 3e6df87b5b..c40885ed5c 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -602,8 +602,7 @@ static void sifive_u_machine_init(MachineState *machi= ne) > kernel_start_addr, NULL); > > if (machine->initrd_filename) { > - riscv_load_initrd(machine->initrd_filename, machine->ram_siz= e, > - kernel_entry, machine->fdt); > + riscv_load_initrd(machine, kernel_entry); > } > > if (machine->kernel_cmdline && *machine->kernel_cmdline) { > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index 60e2912be5..99dec74fe8 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -312,8 +312,7 @@ static void spike_board_init(MachineState *machine) > htif_symbol_callback); > > if (machine->initrd_filename) { > - riscv_load_initrd(machine->initrd_filename, machine->ram_siz= e, > - kernel_entry, machine->fdt); > + riscv_load_initrd(machine, kernel_entry); > } > > if (machine->kernel_cmdline && *machine->kernel_cmdline) { > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 6c946b6def..02f1369843 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -1285,8 +1285,7 @@ static void virt_machine_done(Notifier *notifier, v= oid *data) > kernel_start_addr, NULL); > > if (machine->initrd_filename) { > - riscv_load_initrd(machine->initrd_filename, machine->ram_siz= e, > - kernel_entry, machine->fdt); > + riscv_load_initrd(machine, kernel_entry); > } > > if (machine->kernel_cmdline && *machine->kernel_cmdline) { > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h > index e37e1d1238..cfd72ecabf 100644 > --- a/include/hw/riscv/boot.h > +++ b/include/hw/riscv/boot.h > @@ -46,8 +46,7 @@ target_ulong riscv_load_firmware(const char *firmware_f= ilename, > target_ulong riscv_load_kernel(const char *kernel_filename, > target_ulong firmware_end_addr, > symbol_fn_t sym_cb); > -void riscv_load_initrd(const char *filename, uint64_t mem_size, > - uint64_t kernel_entry, void *fdt); > +void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); > uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt= ); > void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayStat= e *harts, > hwaddr saddr, > -- > 2.39.0 > > From MAILER-DAEMON Tue Jan 10 17:41:10 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFNIs-0002ia-Q6 for mharc-qemu-riscv@gnu.org; Tue, 10 Jan 2023 17:41:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFNIr-0002iF-Lm; Tue, 10 Jan 2023 17:41:09 -0500 Received: from mail-vs1-xe2f.google.com ([2607:f8b0:4864:20::e2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFNIp-0002Q0-UY; Tue, 10 Jan 2023 17:41:09 -0500 Received: by mail-vs1-xe2f.google.com with SMTP id s127so13894028vsb.5; Tue, 10 Jan 2023 14:41:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=q0HIt8dF1tonwj/2/j2rsHglq6LnlMrliqx16mdGNiE=; b=lrmOFD2zyOwxt4+nsz+ph/NhK9MmitMlcwn5p+A/6F24p+GEwwA4rrapUT+/RzWE5z gz9y24LcyRHh13gBCIQFE5YV3vaM3lLwHmlWw4i2x9XDuMEKaJqvPpp0cV5Vhr9lbs1o IwZv/IMDKOcYJgJ/KpkPFrz6bMY5S4R5IhqJTlIMedQPxQBH5yOiT3n6BJmAbLr55Ig9 Xn0pIE+4kzXGF9gjus+b2T4xRPzrFGlEv9Qo71AzSavjrE28/YWBni0lcSvtT3EWlvEp dH7PnMpstD6XbU3lZssrht/GCb01CBd2pVmEiK9PQM04EIGprsbMh1OMwlv8Z+F3tonn CIzg== X-Google-DKIM-Signature: v=1; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e2f; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 22:41:10 -0000 On Mon, Jan 2, 2023 at 9:55 PM Daniel Henrique Barboza wrote: > > All callers are using kernel_filename as machine->kernel_filename. > > This will also simplify the changes in riscv_load_kernel() that we're > going to do next. > > Cc: Palmer Dabbelt > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/boot.c | 3 ++- > hw/riscv/microchip_pfsoc.c | 3 +-- > hw/riscv/opentitan.c | 3 +-- > hw/riscv/sifive_e.c | 3 +-- > hw/riscv/sifive_u.c | 3 +-- > hw/riscv/spike.c | 3 +-- > hw/riscv/virt.c | 3 +-- > include/hw/riscv/boot.h | 2 +- > 8 files changed, 9 insertions(+), 14 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index d3e780c3b6..2594276223 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -173,10 +173,11 @@ target_ulong riscv_load_firmware(const char *firmwa= re_filename, > exit(1); > } > > -target_ulong riscv_load_kernel(const char *kernel_filename, > +target_ulong riscv_load_kernel(MachineState *machine, > target_ulong kernel_start_addr, > symbol_fn_t sym_cb) > { > + const char *kernel_filename =3D machine->kernel_filename; > uint64_t kernel_load_base, kernel_entry; > > g_assert(kernel_filename !=3D NULL); > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index 1e9b0a420e..82ae5e7023 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -629,8 +629,7 @@ static void microchip_icicle_kit_machine_init(Machine= State *machine) > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpu= s, > firmware_end_ad= dr); > > - kernel_entry =3D riscv_load_kernel(machine->kernel_filename, > - kernel_start_addr, NULL); > + kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, N= ULL); > > if (machine->initrd_filename) { > riscv_load_initrd(machine, kernel_entry); > diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c > index 85ffdac5be..64d5d435b9 100644 > --- a/hw/riscv/opentitan.c > +++ b/hw/riscv/opentitan.c > @@ -101,8 +101,7 @@ static void opentitan_board_init(MachineState *machin= e) > } > > if (machine->kernel_filename) { > - riscv_load_kernel(machine->kernel_filename, > - memmap[IBEX_DEV_RAM].base, NULL); > + riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); > } > } > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > index d65d2fd869..3e3f4b0088 100644 > --- a/hw/riscv/sifive_e.c > +++ b/hw/riscv/sifive_e.c > @@ -114,8 +114,7 @@ static void sifive_e_machine_init(MachineState *machi= ne) > memmap[SIFIVE_E_DEV_MROM].base, &address_space= _memory); > > if (machine->kernel_filename) { > - riscv_load_kernel(machine->kernel_filename, > - memmap[SIFIVE_E_DEV_DTIM].base, NULL); > + riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL)= ; > } > } > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index c40885ed5c..bac394c959 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -598,8 +598,7 @@ static void sifive_u_machine_init(MachineState *machi= ne) > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpu= s, > firmware_end_ad= dr); > > - kernel_entry =3D riscv_load_kernel(machine->kernel_filename, > - kernel_start_addr, NULL); > + kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, N= ULL); > > if (machine->initrd_filename) { > riscv_load_initrd(machine, kernel_entry); > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index 99dec74fe8..bff9475686 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -307,8 +307,7 @@ static void spike_board_init(MachineState *machine) > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], > firmware_end_ad= dr); > > - kernel_entry =3D riscv_load_kernel(machine->kernel_filename, > - kernel_start_addr, > + kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, > htif_symbol_callback); > > if (machine->initrd_filename) { > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 02f1369843..c8e35f861e 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -1281,8 +1281,7 @@ static void virt_machine_done(Notifier *notifier, v= oid *data) > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], > firmware_end_ad= dr); > > - kernel_entry =3D riscv_load_kernel(machine->kernel_filename, > - kernel_start_addr, NULL); > + kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, N= ULL); > > if (machine->initrd_filename) { > riscv_load_initrd(machine, kernel_entry); > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h > index cfd72ecabf..f94653a09b 100644 > --- a/include/hw/riscv/boot.h > +++ b/include/hw/riscv/boot.h > @@ -43,7 +43,7 @@ char *riscv_find_firmware(const char *firmware_filename= , > target_ulong riscv_load_firmware(const char *firmware_filename, > hwaddr firmware_load_addr, > symbol_fn_t sym_cb); > -target_ulong riscv_load_kernel(const char *kernel_filename, > +target_ulong riscv_load_kernel(MachineState *machine, > target_ulong firmware_end_addr, > symbol_fn_t sym_cb); > void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); > -- > 2.39.0 > > From MAILER-DAEMON Tue Jan 10 17:41:46 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFNJS-0002vU-14 for mharc-qemu-riscv@gnu.org; Tue, 10 Jan 2023 17:41:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFNJR-0002vE-5K; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a2d; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 22:41:45 -0000 On Mon, Jan 2, 2023 at 9:57 PM Daniel Henrique Barboza wrote: > > The only remaining caller is riscv_load_kernel_and_initrd() which > belongs to the same file. > > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/boot.c | 80 ++++++++++++++++++++--------------------- > include/hw/riscv/boot.h | 1 - > 2 files changed, 40 insertions(+), 41 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 4888d5c1e0..e868fb6ade 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -173,6 +173,46 @@ target_ulong riscv_load_firmware(const char *firmwar= e_filename, > exit(1); > } > > +static void riscv_load_initrd(MachineState *machine, uint64_t kernel_ent= ry) > +{ > + const char *filename =3D machine->initrd_filename; > + uint64_t mem_size =3D machine->ram_size; > + void *fdt =3D machine->fdt; > + hwaddr start, end; > + ssize_t size; > + > + g_assert(filename !=3D NULL); > + > + /* > + * We want to put the initrd far enough into RAM that when the > + * kernel is uncompressed it will not clobber the initrd. However > + * on boards without much RAM we must ensure that we still leave > + * enough room for a decent sized initrd, and on boards with large > + * amounts of RAM we must avoid the initrd being so far up in RAM > + * that it is outside lowmem and inaccessible to the kernel. > + * So for boards with less than 256MB of RAM we put the initrd > + * halfway into RAM, and for boards with 256MB of RAM or more we put > + * the initrd at 128MB. > + */ > + start =3D kernel_entry + MIN(mem_size / 2, 128 * MiB); > + > + size =3D load_ramdisk(filename, start, mem_size - start); > + if (size =3D=3D -1) { > + size =3D load_image_targphys(filename, start, mem_size - start); > + if (size =3D=3D -1) { > + error_report("could not load ramdisk '%s'", filename); > + exit(1); > + } > + } > + > + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ > + if (fdt) { > + end =3D start + size; > + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", star= t); > + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); > + } > +} > + > target_ulong riscv_load_kernel(MachineState *machine, > target_ulong kernel_start_addr, > bool load_initrd, > @@ -225,46 +265,6 @@ out: > return kernel_entry; > } > > -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) > -{ > - const char *filename =3D machine->initrd_filename; > - uint64_t mem_size =3D machine->ram_size; > - void *fdt =3D machine->fdt; > - hwaddr start, end; > - ssize_t size; > - > - g_assert(filename !=3D NULL); > - > - /* > - * We want to put the initrd far enough into RAM that when the > - * kernel is uncompressed it will not clobber the initrd. However > - * on boards without much RAM we must ensure that we still leave > - * enough room for a decent sized initrd, and on boards with large > - * amounts of RAM we must avoid the initrd being so far up in RAM > - * that it is outside lowmem and inaccessible to the kernel. > - * So for boards with less than 256MB of RAM we put the initrd > - * halfway into RAM, and for boards with 256MB of RAM or more we put > - * the initrd at 128MB. > - */ > - start =3D kernel_entry + MIN(mem_size / 2, 128 * MiB); > - > - size =3D load_ramdisk(filename, start, mem_size - start); > - if (size =3D=3D -1) { > - size =3D load_image_targphys(filename, start, mem_size - start); > - if (size =3D=3D -1) { > - error_report("could not load ramdisk '%s'", filename); > - exit(1); > - } > - } > - > - /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ > - if (fdt) { > - end =3D start + size; > - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", star= t); > - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); > - } > -} > - > uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) > { > uint64_t temp, fdt_addr; > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h > index c3de897371..cbd131bad7 100644 > --- a/include/hw/riscv/boot.h > +++ b/include/hw/riscv/boot.h > @@ -47,7 +47,6 @@ target_ulong riscv_load_kernel(MachineState *machine, > target_ulong firmware_end_addr, > bool load_initrd, > symbol_fn_t sym_cb); > -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); > uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt= ); > void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayStat= e *harts, > hwaddr saddr, > -- > 2.39.0 > > From MAILER-DAEMON Tue Jan 10 17:43:21 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFNKz-0004Td-QU for mharc-qemu-riscv@gnu.org; Tue, 10 Jan 2023 17:43:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFNKy-0004Sg-8H; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e2d; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 22:43:20 -0000 On Mon, Jan 2, 2023 at 9:55 PM Daniel Henrique Barboza wrote: > > The microchip_icicle_kit, sifive_u, spike and virt boards are now doing > the same steps when '-kernel' is used: > > - execute load_kernel() > - load init_rd() > - write kernel_cmdline > > Let's fold everything inside riscv_load_kernel() to avoid code > repetition. To not change the behavior of boards that aren't calling > riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and > allow these boards to opt out from initrd loading. > > Cc: Palmer Dabbelt > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/boot.c | 22 +++++++++++++++++++--- > hw/riscv/microchip_pfsoc.c | 12 ++---------- > hw/riscv/opentitan.c | 2 +- > hw/riscv/sifive_e.c | 3 ++- > hw/riscv/sifive_u.c | 12 ++---------- > hw/riscv/spike.c | 11 +---------- > hw/riscv/virt.c | 12 ++---------- > include/hw/riscv/boot.h | 1 + > 8 files changed, 30 insertions(+), 45 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 2594276223..4888d5c1e0 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -175,10 +175,12 @@ target_ulong riscv_load_firmware(const char *firmware_filename, > > target_ulong riscv_load_kernel(MachineState *machine, > target_ulong kernel_start_addr, > + bool load_initrd, > symbol_fn_t sym_cb) > { > const char *kernel_filename = machine->kernel_filename; > uint64_t kernel_load_base, kernel_entry; > + void *fdt = machine->fdt; > > g_assert(kernel_filename != NULL); > > @@ -192,21 +194,35 @@ target_ulong riscv_load_kernel(MachineState *machine, > if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, > NULL, &kernel_load_base, NULL, NULL, 0, > EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { > - return kernel_load_base; > + kernel_entry = kernel_load_base; > + goto out; > } > > if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, > NULL, NULL, NULL) > 0) { > - return kernel_entry; > + goto out; > } > > if (load_image_targphys_as(kernel_filename, kernel_start_addr, > current_machine->ram_size, NULL) > 0) { > - return kernel_start_addr; > + kernel_entry = kernel_start_addr; > + goto out; > } > > error_report("could not load kernel '%s'", kernel_filename); > exit(1); > + > +out: > + if (load_initrd && machine->initrd_filename) { > + riscv_load_initrd(machine, kernel_entry); > + } > + > + if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { > + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", > + machine->kernel_cmdline); > + } > + > + return kernel_entry; > } > > void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index 82ae5e7023..c45023a2b1 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -629,16 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) > kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, > firmware_end_addr); > > - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); > - > - if (machine->initrd_filename) { > - riscv_load_initrd(machine, kernel_entry); > - } > - > - if (machine->kernel_cmdline && *machine->kernel_cmdline) { > - qemu_fdt_setprop_string(machine->fdt, "/chosen", > - "bootargs", machine->kernel_cmdline); > - } > + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, > + true, NULL); > > /* Compute the fdt load address in dram */ > fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, > diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c > index 64d5d435b9..f6fd9725a5 100644 > --- a/hw/riscv/opentitan.c > +++ b/hw/riscv/opentitan.c > @@ -101,7 +101,7 @@ static void opentitan_board_init(MachineState *machine) > } > > if (machine->kernel_filename) { > - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); > + riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, false, NULL); > } > } > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > index 3e3f4b0088..6835d1c807 100644 > --- a/hw/riscv/sifive_e.c > +++ b/hw/riscv/sifive_e.c > @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machine) > memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); > > if (machine->kernel_filename) { > - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL); > + riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, > + false, NULL); > } > } > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index bac394c959..9a75d4aa62 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -598,16 +598,8 @@ static void sifive_u_machine_init(MachineState *machine) > kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, > firmware_end_addr); > > - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); > - > - if (machine->initrd_filename) { > - riscv_load_initrd(machine, kernel_entry); > - } > - > - if (machine->kernel_cmdline && *machine->kernel_cmdline) { > - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", > - machine->kernel_cmdline); > - } > + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, > + true, NULL); > } else { > /* > * If dynamic firmware is used, it doesn't know where is the next mode > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index bff9475686..c517885e6e 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -308,16 +308,7 @@ static void spike_board_init(MachineState *machine) > firmware_end_addr); > > kernel_entry = riscv_load_kernel(machine, kernel_start_addr, > - htif_symbol_callback); > - > - if (machine->initrd_filename) { > - riscv_load_initrd(machine, kernel_entry); > - } > - > - if (machine->kernel_cmdline && *machine->kernel_cmdline) { > - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", > - machine->kernel_cmdline); > - } > + true, htif_symbol_callback); > } else { > /* > * If dynamic firmware is used, it doesn't know where is the next mode > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index c8e35f861e..a931ed05ab 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -1281,16 +1281,8 @@ static void virt_machine_done(Notifier *notifier, void *data) > kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], > firmware_end_addr); > > - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); > - > - if (machine->initrd_filename) { > - riscv_load_initrd(machine, kernel_entry); > - } > - > - if (machine->kernel_cmdline && *machine->kernel_cmdline) { > - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", > - machine->kernel_cmdline); > - } > + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, > + true, NULL); > } else { > /* > * If dynamic firmware is used, it doesn't know where is the next mode > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h > index f94653a09b..c3de897371 100644 > --- a/include/hw/riscv/boot.h > +++ b/include/hw/riscv/boot.h > @@ -45,6 +45,7 @@ target_ulong riscv_load_firmware(const char *firmware_filename, > symbol_fn_t sym_cb); > target_ulong riscv_load_kernel(MachineState *machine, > target_ulong firmware_end_addr, > + bool load_initrd, > symbol_fn_t sym_cb); > void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); > uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); > -- > 2.39.0 > > From MAILER-DAEMON Tue Jan 10 17:46:03 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFNNa-0006Mr-WD for mharc-qemu-riscv@gnu.org; Tue, 10 Jan 2023 17:46:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFNNO-0006KD-Of; Tue, 10 Jan 2023 17:45:54 -0500 Received: from mail-ua1-x92b.google.com ([2607:f8b0:4864:20::92b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFNNM-0003EL-Pb; Tue, 10 Jan 2023 17:45:50 -0500 Received: by mail-ua1-x92b.google.com with SMTP id z3so3221575uao.9; Tue, 10 Jan 2023 14:45:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=2S4szICChH5NVreMnM7NLvAxGh2KYylkEgv2UlEf/OE=; b=qsXUulaArwG0MK2Yvs5p9dKUJhHk8Yv0k2wJ31vv3forM/vsuKnX0YY8KIncdPUgWI eHoVu09g0fHGJnOL3V3frM2Y1pSyPbaQA8/bUd//24gZdrojVOEVn4NWL4opCDqJ80DH Y1GJmilupWzQp7FfNAqpfqY/uae1i0tXWviMwLBvdy11pVQNt+xv0IroGlSBJrfcjsUV hRURPsFV/q2t9pVpFa+0HeeQnl7MLSDtqjFZyaOdlPHqpGVpI9OoIEk+Chu+iEyR71CY U/1gH9jtCyoIi1mIP6OmXOwcPjm2ylDyLDyLGmc/sLBF8Ekkq7af8uhjWxjOJBPu6gmO h9XA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=2S4szICChH5NVreMnM7NLvAxGh2KYylkEgv2UlEf/OE=; b=0PHxT0pBa1UPc557O0cbZpHh8zD8suePzr+hcwipJtOVmFVbNchgZZ2N0Clxr9+sDO DviVXiqowLafB93w93OP/pQoi5+If0Z6rVMLSvb+WvHr8oTu7FZ1fBsuckW0QeLHH0d4 1hGlOrLTLoh89IbFmxVx4FI99dvxlNcA5iTkp6GLZlJzmomWo1Mcadb1X2KOHTz5WDrR zgN8QQWYkOB1YoZAoI163DlkmjgDxsLCxWEUcv74h2AJvil6I3xCNNeMyqCflx/7BPWU wevQWciRnZ4E3BamzQE26riYpZMzzniqu0u8+JxZZxYjbPNif8AzFfH4Vy7ldcgT0siK MbNQ== X-Gm-Message-State: AFqh2kqfbRQV+ad/AMPKxPDQqUtYpEvkZzTmfxc+o8W4NhqTaahF+WyA PvBBP8kRKJ1tqgmSdUDE2C+VzggMrxCLANCSucFBXPg8osesOg== X-Google-Smtp-Source: AMrXdXsJmjsHhxBZxbibQ0t8O9NSrIan/vKWNp2HOnmtmAJ7vzJIpO8g1VkA05UM+qenPNPpoq7W3zSQKHgP8knOv4Q= X-Received: by 2002:a9f:3191:0:b0:419:1fa3:9618 with SMTP id v17-20020a9f3191000000b004191fa39618mr8647370uad.11.1673390747277; Tue, 10 Jan 2023 14:45:47 -0800 (PST) MIME-Version: 1.0 References: <20230102115241.25733-1-dbarboza@ventanamicro.com> <20230102115241.25733-11-dbarboza@ventanamicro.com> <1adba771-6632-4f68-d72f-4389f9ce7012@ventanamicro.com> <842056c4-4f77-0db7-fa89-e3973b81bd23@ventanamicro.com> In-Reply-To: <842056c4-4f77-0db7-fa89-e3973b81bd23@ventanamicro.com> From: Alistair Francis Date: Wed, 11 Jan 2023 08:45:21 +1000 Message-ID: Subject: Re: [PATCH v5 10/11] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() To: Daniel Henrique Barboza Cc: Bin Meng , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng , Palmer Dabbelt Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::92b; envelope-from=alistair23@gmail.com; helo=mail-ua1-x92b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 22:46:00 -0000 On Wed, Jan 11, 2023 at 6:21 AM Daniel Henrique Barboza wrote: > > > > On 1/10/23 08:43, Daniel Henrique Barboza wrote: > > > > > > On 1/8/23 00:33, Bin Meng wrote: > >> On Mon, Jan 2, 2023 at 7:55 PM Daniel Henrique Barboza > >> wrote: > >>> The microchip_icicle_kit, sifive_u, spike and virt boards are now doing > >>> the same steps when '-kernel' is used: > >>> > >>> - execute load_kernel() > >>> - load init_rd() > >>> - write kernel_cmdline > >>> > >>> Let's fold everything inside riscv_load_kernel() to avoid code > >>> repetition. To not change the behavior of boards that aren't calling > >>> riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and > >> typo: should be riscv_load_initrd() > >> > >>> allow these boards to opt out from initrd loading. > >>> > >>> Cc: Palmer Dabbelt > >>> Signed-off-by: Daniel Henrique Barboza > >>> --- > >>> hw/riscv/boot.c | 22 +++++++++++++++++++--- > >>> hw/riscv/microchip_pfsoc.c | 12 ++---------- > >>> hw/riscv/opentitan.c | 2 +- > >>> hw/riscv/sifive_e.c | 3 ++- > >>> hw/riscv/sifive_u.c | 12 ++---------- > >>> hw/riscv/spike.c | 11 +---------- > >>> hw/riscv/virt.c | 12 ++---------- > >>> include/hw/riscv/boot.h | 1 + > >>> 8 files changed, 30 insertions(+), 45 deletions(-) > >>> > >> Otherwise, > >> Reviewed-by: Bin Meng > > > > Thanks! > > > > Alistair, let me know if you want me to send another version with the commit > > message typo fixed. I might as well take the change to rebase it with > > riscv-to-apply.next. > > While rebasing these patches on top of riscv-to-apply.next, the avocado tests > I've introduced here started to fail both sifive_u tests: > > tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv32_sifive_u: INTERRUPTED: > Test interrupted by SIGTERM\nRunner error occurred: ... (5.07 s) > (09/18) tests/avocado/riscv_opensbi.py:RiscvOpenSBI.test_riscv64_sifive_u: INTERRUPTED: > Test interrupted by SIGTERM\nRunner error occurred: ... (5.05 s) > > > I proposed a fix here: > > https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02035.html Thanks! I generally push riscv-to-apply.next before running tests, so it's possible to break. I'm seeing similar failures. Generally when I see failures from a series I just drop the series, but if you have a fix that's even better :) Alistair > > I can re-send this series after we get that problem figure out. Otherwise we're > going to add 2 avocado tests that are failing right from the start hehe. > > Thanks, > > Daniel > > > > > > > > Daniel > > > > From MAILER-DAEMON Tue Jan 10 17:53:35 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFNUp-0001N5-QN for mharc-qemu-riscv@gnu.org; Tue, 10 Jan 2023 17:53:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFNUl-0001JA-5k; Tue, 10 Jan 2023 17:53:27 -0500 Received: from mail-ua1-x934.google.com ([2607:f8b0:4864:20::934]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFNUj-00048R-7Y; Tue, 10 Jan 2023 17:53:26 -0500 Received: by mail-ua1-x934.google.com with SMTP id t8so3234292uaj.5; Tue, 10 Jan 2023 14:53:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=xjiLLvsz1+8AN0N78SvCPD3CHYf8zVgFXh0dH4ebgvg=; b=e4UyVrcdaR56i0TIB1EY8tAnuGiQkkk5TcL2I4TmYmf2TmmGLrjBqT/6nXm/ug9fDd IkkITOK+2Dil8brYnWhdbT4BsCNgdL0gG6pZ5HRsHqEUlOd9Yxd0Bhmc5+5AGaIrEDmy 8s6Odw2ZQmWANJ8BkmDdEocmJSiguMinTchxn1mSXBTCmVeHuyN8OJwkYpnzt3yLBLZH RbaR3UIsxF4/xc5YiTAw+RcYHfLyKbkfEwkx1e42DLgipbWsEl/jI3dd1y3G2PptYhQq 4n0R+SCKSnjTRjNcsGwU0L2BbtctX2Fych0eIfdH7kk9+x3Fvr27u3ALB/+/FrUMKgYo g/Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=xjiLLvsz1+8AN0N78SvCPD3CHYf8zVgFXh0dH4ebgvg=; b=AJtU/0YG4sSlKFNYbqXuEuPGsM6susIKJ/iH3YLEs2t57I3W2nx0KTwHJd7IlDI+aF vAMPKpq4Hr7EEtMeVWlfP4038VAH1XWmLS0QALkIadhnCCCopxCnGGpAJ7QTaRa32nGT bCNVN7pUhi1D095ngr3CzJCS5Jg3RzOT4URqaEbh/1FLa+QizUhGwiv8KD9uFrRnCTUe /kx920km9A4wcsmW9jfvwSgO4VanC2oC6/OUkSUe93hsrijV0wbp6WMs+1fF0NjgWpxB 874Wkr4D/Vw7kNXOgryh3d0WSFZAUvvjWgcdEeVBP97v/TOS1qtZB1N+aOXGeBxSl/qP 93lA== X-Gm-Message-State: AFqh2kopilOajcuwXarMwcCwMZlrbk+RH9LXkTHJ1UpHslmAXofetByj 9bgwfl3bFPIhI029Z5C7HjNnXDWjgF+6cLGvZPaEMsjR1wg= X-Google-Smtp-Source: AMrXdXsmpzLZirQI53I+pgirgTHZv3RzKJmD9F8IUIrRKPxaAp5N9NKl2LYX3ZRNQw38hdmZrPuk5/jChQahNV/X+vo= X-Received: by 2002:ab0:6182:0:b0:419:2865:3ae7 with SMTP id h2-20020ab06182000000b0041928653ae7mr8095914uan.70.1673391203706; Tue, 10 Jan 2023 14:53:23 -0800 (PST) MIME-Version: 1.0 References: <20230110201405.247785-1-dbarboza@ventanamicro.com> <20230110201405.247785-2-dbarboza@ventanamicro.com> In-Reply-To: <20230110201405.247785-2-dbarboza@ventanamicro.com> From: Alistair Francis Date: Wed, 11 Jan 2023 08:52:57 +1000 Message-ID: Subject: Re: [PATCH 1/2] target/riscv/cpu: set cpu->cfg in register_cpu_props() To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, richard.henderson@linaro.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::934; envelope-from=alistair23@gmail.com; helo=mail-ua1-x934.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 22:53:29 -0000 On Wed, Jan 11, 2023 at 6:17 AM Daniel Henrique Barboza wrote: > > There is an informal contract between the cpu_init() functions and > riscv_cpu_realize(): if cpu->env.misa_ext is zero, assume that the > default settings were loaded via register_cpu_props() and do validations > to set env.misa_ext. If it's not zero, skip this whole process and > assume that the board somehow did everything. > > At this moment, all SiFive CPUs are setting a non-zero misa_ext during > their cpu_init() and skipping a good chunk of riscv_cpu_realize(). > This causes problems when the code being skipped in riscv_cpu_realize() > contains fixes or assumptions that affects all CPUs, meaning that SiFive > CPUs are missing out. > > To allow this code to not be skipped anymore, all the cpu->cfg.ext_* attributes > needs to be set during cpu_init() time. At this moment this is being done in > register_cpu_props(). The SiFive oards are setting their own extensions during > cpu_init() though, meaning that they don't want all the defaults from > register_cpu_props(). > > Let's move the contract between *_cpu_init() and riscv_cpu_realize() to > register_cpu_props(). Inside this function we'll check if cpu->env.misa_ext > was set and, if that's the case, set all relevant cpu->cfg.ext_* > attributes, and only that. Leave the 'misa_ext' = 0 case as is today, > i.e. loading all the defaults from riscv_cpu_extensions[]. > > register_cpu_props() can then be called by all the cpu_init() functions, > including the SiFive ones. This will make all CPUs behave more in line > with that riscv_cpu_realize() expects. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 40 ++++++++++++++++++++++++++++++++++++++++ > target/riscv/cpu.h | 4 ++++ > 2 files changed, 44 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index ee3659cc7e..b8c1edb7c2 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -262,6 +262,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > + register_cpu_props(DEVICE(obj)); > set_priv_version(env, PRIV_VERSION_1_10_0); > } > > @@ -271,6 +272,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) > RISCVCPU *cpu = RISCV_CPU(obj); > > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); > + register_cpu_props(DEVICE(obj)); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > } > @@ -305,6 +307,7 @@ static void rv32_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > + register_cpu_props(DEVICE(obj)); > set_priv_version(env, PRIV_VERSION_1_10_0); > } > > @@ -314,6 +317,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) > RISCVCPU *cpu = RISCV_CPU(obj); > > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); > + register_cpu_props(DEVICE(obj)); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > } > @@ -324,6 +328,7 @@ static void rv32_ibex_cpu_init(Object *obj) > RISCVCPU *cpu = RISCV_CPU(obj); > > set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); > + register_cpu_props(DEVICE(obj)); > set_priv_version(env, PRIV_VERSION_1_11_0); > cpu->cfg.mmu = false; > cpu->cfg.epmp = true; > @@ -335,6 +340,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > RISCVCPU *cpu = RISCV_CPU(obj); > > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); > + register_cpu_props(DEVICE(obj)); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > } > @@ -1139,10 +1145,44 @@ static Property riscv_cpu_extensions[] = { > DEFINE_PROP_END_OF_LIST(), > }; > > +/* > + * Register CPU props based on env.misa_ext. If a non-zero > + * value was set, register only the required cpu->cfg.ext_* > + * properties and leave. env.misa_ext = 0 means that we want > + * all the default properties to be registered. > + */ > static void register_cpu_props(DeviceState *dev) > { > + RISCVCPU *cpu = RISCV_CPU(OBJECT(dev)); > + uint32_t misa_ext = cpu->env.misa_ext; > Property *prop; > > + /* > + * If misa_ext is not zero, set cfg properties now to > + * allow them to be read during riscv_cpu_realize() > + * later on. > + */ > + if (cpu->env.misa_ext != 0) { > + cpu->cfg.ext_i = misa_ext & RVI; > + cpu->cfg.ext_e = misa_ext & RVE; > + cpu->cfg.ext_m = misa_ext & RVM; > + cpu->cfg.ext_a = misa_ext & RVA; > + cpu->cfg.ext_f = misa_ext & RVF; > + cpu->cfg.ext_d = misa_ext & RVD; > + cpu->cfg.ext_v = misa_ext & RVV; > + cpu->cfg.ext_c = misa_ext & RVC; > + cpu->cfg.ext_s = misa_ext & RVS; > + cpu->cfg.ext_u = misa_ext & RVU; > + cpu->cfg.ext_h = misa_ext & RVH; > + cpu->cfg.ext_j = misa_ext & RVJ; > + > + /* > + * We don't want to set the default riscv_cpu_extensions > + * in this case. > + */ > + return; > + } > + > for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > qdev_property_add_static(dev, prop); > } > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 0158932dc5..798bd081de 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -63,6 +63,10 @@ > > #define RV(x) ((target_ulong)1 << (x - 'A')) > > +/* > + * Consider updating register_cpu_props() when adding > + * new MISA bits here. > + */ > #define RVI RV('I') > #define RVE RV('E') /* E and I are mutually exclusive */ > #define RVM RV('M') > -- > 2.39.0 > > From MAILER-DAEMON Tue Jan 10 17:53:51 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFNV9-0001Ta-OU for mharc-qemu-riscv@gnu.org; Tue, 10 Jan 2023 17:53:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 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Jan 2023 14:53:46 -0800 (PST) MIME-Version: 1.0 References: <20230110201405.247785-1-dbarboza@ventanamicro.com> <20230110201405.247785-3-dbarboza@ventanamicro.com> In-Reply-To: <20230110201405.247785-3-dbarboza@ventanamicro.com> From: Alistair Francis Date: Wed, 11 Jan 2023 08:53:20 +1000 Message-ID: Subject: Re: [PATCH 2/2] target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, richard.henderson@linaro.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e2e; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 22:53:50 -0000 On Wed, Jan 11, 2023 at 6:17 AM Daniel Henrique Barboza wrote: > > All RISCV CPUs are setting cpu->cfg during their cpu_init() functions, > meaning that there's no reason to skip all the misa validation and setup > if misa_ext was set beforehand - especially since we're setting an > updated value in set_misa() in the end. > > Put this code chunk into a new riscv_cpu_validate_set_extensions() > helper and always execute it regardless of what the board set in > env->misa_ext. > > This will put more responsibility in how each board is going to init > their attributes and extensions if they're not using the defaults. > It'll also allow realize() to do its job looking only at the extensions > enabled per se, not corner cases that some CPUs might have, and we won't > have to change multiple code paths to fix or change how extensions work. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 485 +++++++++++++++++++++++---------------------- > 1 file changed, 248 insertions(+), 237 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index b8c1edb7c2..33ed59a1b6 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -631,6 +631,250 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > } > } > > +/* > + * Check consistency between chosen extensions while setting > + * cpu->cfg accordingly, doing a set_misa() in the end. > + */ > +static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) > +{ > + CPURISCVState *env = &cpu->env; > + uint32_t ext = 0; > + > + /* Do some ISA extension error checking */ > + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && > + cpu->cfg.ext_a && cpu->cfg.ext_f && > + cpu->cfg.ext_d && > + cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { > + warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); > + cpu->cfg.ext_i = true; > + cpu->cfg.ext_m = true; > + cpu->cfg.ext_a = true; > + cpu->cfg.ext_f = true; > + cpu->cfg.ext_d = true; > + cpu->cfg.ext_icsr = true; > + cpu->cfg.ext_ifencei = true; > + } > + > + if (cpu->cfg.ext_i && cpu->cfg.ext_e) { > + error_setg(errp, > + "I and E extensions are incompatible"); > + return; > + } > + > + if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { > + error_setg(errp, > + "Either I or E extension must be set"); > + return; > + } > + > + if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { > + error_setg(errp, > + "Setting S extension without U extension is illegal"); > + return; > + } > + > + if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { > + error_setg(errp, > + "H depends on an I base integer ISA with 32 x registers"); > + return; > + } > + > + if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { > + error_setg(errp, "H extension implicitly requires S-mode"); > + return; > + } > + > + if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { > + error_setg(errp, "F extension requires Zicsr"); > + return; > + } > + > + if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { > + error_setg(errp, "Zawrs extension requires A extension"); > + return; > + } > + > + if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { > + error_setg(errp, "Zfh/Zfhmin extensions require F extension"); > + return; > + } > + > + if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { > + error_setg(errp, "D extension requires F extension"); > + return; > + } > + > + if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { > + error_setg(errp, "V extension requires D extension"); > + return; > + } > + > + if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { > + error_setg(errp, "Zve32f/Zve64f extensions require F extension"); > + return; > + } > + > + /* Set the ISA extensions, checks should have happened above */ > + if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || > + cpu->cfg.ext_zhinxmin) { > + cpu->cfg.ext_zfinx = true; > + } > + > + if (cpu->cfg.ext_zfinx) { > + if (!cpu->cfg.ext_icsr) { > + error_setg(errp, "Zfinx extension requires Zicsr"); > + return; > + } > + if (cpu->cfg.ext_f) { > + error_setg(errp, > + "Zfinx cannot be supported together with F extension"); > + return; > + } > + } > + > + if (cpu->cfg.ext_c) { > + cpu->cfg.ext_zca = true; > + if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) { > + cpu->cfg.ext_zcf = true; > + } > + if (cpu->cfg.ext_d) { > + cpu->cfg.ext_zcd = true; > + } > + } > + > + if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { > + error_setg(errp, "Zcf extension is only relevant to RV32"); > + return; > + } > + > + if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) { > + error_setg(errp, "Zcf extension requires F extension"); > + return; > + } > + > + if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) { > + error_setg(errp, "Zcd extension requires D extension"); > + return; > + } > + > + if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || > + cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { > + error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " > + "extension"); > + return; > + } > + > + if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { > + error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " > + "Zcd extension"); > + return; > + } > + > + if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { > + error_setg(errp, "Zcmt extension requires Zicsr extension"); > + return; > + } > + > + if (cpu->cfg.ext_zk) { > + cpu->cfg.ext_zkn = true; > + cpu->cfg.ext_zkr = true; > + cpu->cfg.ext_zkt = true; > + } > + > + if (cpu->cfg.ext_zkn) { > + cpu->cfg.ext_zbkb = true; > + cpu->cfg.ext_zbkc = true; > + cpu->cfg.ext_zbkx = true; > + cpu->cfg.ext_zkne = true; > + cpu->cfg.ext_zknd = true; > + cpu->cfg.ext_zknh = true; > + } > + > + if (cpu->cfg.ext_zks) { > + cpu->cfg.ext_zbkb = true; > + cpu->cfg.ext_zbkc = true; > + cpu->cfg.ext_zbkx = true; > + cpu->cfg.ext_zksed = true; > + cpu->cfg.ext_zksh = true; > + } > + > + if (cpu->cfg.ext_i) { > + ext |= RVI; > + } > + if (cpu->cfg.ext_e) { > + ext |= RVE; > + } > + if (cpu->cfg.ext_m) { > + ext |= RVM; > + } > + if (cpu->cfg.ext_a) { > + ext |= RVA; > + } > + if (cpu->cfg.ext_f) { > + ext |= RVF; > + } > + if (cpu->cfg.ext_d) { > + ext |= RVD; > + } > + if (cpu->cfg.ext_c) { > + ext |= RVC; > + } > + if (cpu->cfg.ext_s) { > + ext |= RVS; > + } > + if (cpu->cfg.ext_u) { > + ext |= RVU; > + } > + if (cpu->cfg.ext_h) { > + ext |= RVH; > + } > + if (cpu->cfg.ext_v) { > + int vext_version = VEXT_VERSION_1_00_0; > + ext |= RVV; > + if (!is_power_of_2(cpu->cfg.vlen)) { > + error_setg(errp, > + "Vector extension VLEN must be power of 2"); > + return; > + } > + if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { > + error_setg(errp, > + "Vector extension implementation only supports VLEN " > + "in the range [128, %d]", RV_VLEN_MAX); > + return; > + } > + if (!is_power_of_2(cpu->cfg.elen)) { > + error_setg(errp, > + "Vector extension ELEN must be power of 2"); > + return; > + } > + if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { > + error_setg(errp, > + "Vector extension implementation only supports ELEN " > + "in the range [8, 64]"); > + return; > + } > + if (cpu->cfg.vext_spec) { > + if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { > + vext_version = VEXT_VERSION_1_00_0; > + } else { > + error_setg(errp, > + "Unsupported vector spec version '%s'", > + cpu->cfg.vext_spec); > + return; > + } > + } else { > + qemu_log("vector version is not specified, " > + "use the default value v1.0\n"); > + } > + set_vext_version(env, vext_version); > + } > + if (cpu->cfg.ext_j) { > + ext |= RVJ; > + } > + > + set_misa(env, env->misa_mxl, ext); > +} > + > static void riscv_cpu_realize(DeviceState *dev, Error **errp) > { > CPUState *cs = CPU(dev); > @@ -726,243 +970,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > assert(env->misa_mxl_max == env->misa_mxl); > > - /* If only MISA_EXT is unset for misa, then set it from properties */ > - if (env->misa_ext == 0) { > - uint32_t ext = 0; > - > - /* Do some ISA extension error checking */ > - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && > - cpu->cfg.ext_a && cpu->cfg.ext_f && > - cpu->cfg.ext_d && > - cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { > - warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); > - cpu->cfg.ext_i = true; > - cpu->cfg.ext_m = true; > - cpu->cfg.ext_a = true; > - cpu->cfg.ext_f = true; > - cpu->cfg.ext_d = true; > - cpu->cfg.ext_icsr = true; > - cpu->cfg.ext_ifencei = true; > - } > - > - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { > - error_setg(errp, > - "I and E extensions are incompatible"); > - return; > - } > - > - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { > - error_setg(errp, > - "Either I or E extension must be set"); > - return; > - } > - > - if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { > - error_setg(errp, > - "Setting S extension without U extension is illegal"); > - return; > - } > - > - if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { > - error_setg(errp, > - "H depends on an I base integer ISA with 32 x registers"); > - return; > - } > - > - if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { > - error_setg(errp, "H extension implicitly requires S-mode"); > - return; > - } > - > - if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { > - error_setg(errp, "F extension requires Zicsr"); > - return; > - } > - > - if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { > - error_setg(errp, "Zawrs extension requires A extension"); > - return; > - } > - > - if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { > - error_setg(errp, "Zfh/Zfhmin extensions require F extension"); > - return; > - } > - > - if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { > - error_setg(errp, "D extension requires F extension"); > - return; > - } > - > - if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { > - error_setg(errp, "V extension requires D extension"); > - return; > - } > - > - if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { > - error_setg(errp, "Zve32f/Zve64f extensions require F extension"); > - return; > - } > - > - /* Set the ISA extensions, checks should have happened above */ > - if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || > - cpu->cfg.ext_zhinxmin) { > - cpu->cfg.ext_zfinx = true; > - } > - > - if (cpu->cfg.ext_zfinx) { > - if (!cpu->cfg.ext_icsr) { > - error_setg(errp, "Zfinx extension requires Zicsr"); > - return; > - } > - if (cpu->cfg.ext_f) { > - error_setg(errp, > - "Zfinx cannot be supported together with F extension"); > - return; > - } > - } > - > - if (cpu->cfg.ext_c) { > - cpu->cfg.ext_zca = true; > - if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) { > - cpu->cfg.ext_zcf = true; > - } > - if (cpu->cfg.ext_d) { > - cpu->cfg.ext_zcd = true; > - } > - } > - > - if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { > - error_setg(errp, "Zcf extension is only relevant to RV32"); > - return; > - } > - > - if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) { > - error_setg(errp, "Zcf extension requires F extension"); > - return; > - } > - > - if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) { > - error_setg(errp, "Zcd extension requires D extension"); > - return; > - } > - > - if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || > - cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { > - error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " > - "extension"); > - return; > - } > - > - if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { > - error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " > - "Zcd extension"); > - return; > - } > - > - if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { > - error_setg(errp, "Zcmt extension requires Zicsr extension"); > - return; > - } > - > - if (cpu->cfg.ext_zk) { > - cpu->cfg.ext_zkn = true; > - cpu->cfg.ext_zkr = true; > - cpu->cfg.ext_zkt = true; > - } > - > - if (cpu->cfg.ext_zkn) { > - cpu->cfg.ext_zbkb = true; > - cpu->cfg.ext_zbkc = true; > - cpu->cfg.ext_zbkx = true; > - cpu->cfg.ext_zkne = true; > - cpu->cfg.ext_zknd = true; > - cpu->cfg.ext_zknh = true; > - } > - > - if (cpu->cfg.ext_zks) { > - cpu->cfg.ext_zbkb = true; > - cpu->cfg.ext_zbkc = true; > - cpu->cfg.ext_zbkx = true; > - cpu->cfg.ext_zksed = true; > - cpu->cfg.ext_zksh = true; > - } > - > - if (cpu->cfg.ext_i) { > - ext |= RVI; > - } > - if (cpu->cfg.ext_e) { > - ext |= RVE; > - } > - if (cpu->cfg.ext_m) { > - ext |= RVM; > - } > - if (cpu->cfg.ext_a) { > - ext |= RVA; > - } > - if (cpu->cfg.ext_f) { > - ext |= RVF; > - } > - if (cpu->cfg.ext_d) { > - ext |= RVD; > - } > - if (cpu->cfg.ext_c) { > - ext |= RVC; > - } > - if (cpu->cfg.ext_s) { > - ext |= RVS; > - } > - if (cpu->cfg.ext_u) { > - ext |= RVU; > - } > - if (cpu->cfg.ext_h) { > - ext |= RVH; > - } > - if (cpu->cfg.ext_v) { > - int vext_version = VEXT_VERSION_1_00_0; > - ext |= RVV; > - if (!is_power_of_2(cpu->cfg.vlen)) { > - error_setg(errp, > - "Vector extension VLEN must be power of 2"); > - return; > - } > - if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { > - error_setg(errp, > - "Vector extension implementation only supports VLEN " > - "in the range [128, %d]", RV_VLEN_MAX); > - return; > - } > - if (!is_power_of_2(cpu->cfg.elen)) { > - error_setg(errp, > - "Vector extension ELEN must be power of 2"); > - return; > - } > - if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { > - error_setg(errp, > - "Vector extension implementation only supports ELEN " > - "in the range [8, 64]"); > - return; > - } > - if (cpu->cfg.vext_spec) { > - if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { > - vext_version = VEXT_VERSION_1_00_0; > - } else { > - error_setg(errp, > - "Unsupported vector spec version '%s'", > - cpu->cfg.vext_spec); > - return; > - } > - } else { > - qemu_log("vector version is not specified, " > - "use the default value v1.0\n"); > - } > - set_vext_version(env, vext_version); > - } > - if (cpu->cfg.ext_j) { > - ext |= RVJ; > - } > - > - set_misa(env, env->misa_mxl, ext); > + riscv_cpu_validate_set_extensions(cpu, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > } > > #ifndef CONFIG_USER_ONLY > -- > 2.39.0 > > From MAILER-DAEMON Tue Jan 10 18:12:18 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFNn0-0008Ch-GG for mharc-qemu-riscv@gnu.org; Tue, 10 Jan 2023 18:12:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFNmx-0008AT-AH; Tue, 10 Jan 2023 18:12:15 -0500 Received: from mail.ilande.co.uk ([2001:41c9:1:41f::167]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFNmv-0006wE-9A; Tue, 10 Jan 2023 18:12:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; 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AYBcXXKnF0KxATW5lDGfbbqBSRHbvEMYh7JH6HCcNxcrQhl049figJ4radkyGy8HxY0ZGjQFmpend al+1HzAqZZAHXWX/ur+CaxaW90RL8dML3/i2D4nT0=; Received: from [2a00:23c4:8baa:d400:877:cbd2:6fe8:34fc] by mail.ilande.co.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1pFNmW-000959-ML; Tue, 10 Jan 2023 23:11:49 +0000 Message-ID: <73231653-7149-6376-633c-c4f61e576c5b@ilande.co.uk> Date: Tue, 10 Jan 2023 23:12:08 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net References: <20230108023719.2466341-1-richard.henderson@linaro.org> From: Mark Cave-Ayland In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-SA-Exim-Connect-IP: 2a00:23c4:8baa:d400:877:cbd2:6fe8:34fc X-SA-Exim-Mail-From: mark.cave-ayland@ilande.co.uk Subject: Re: [PATCH v4 00/36] tcg: Support for Int128 with helpers X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.ilande.co.uk) Received-SPF: pass client-ip=2001:41c9:1:41f::167; envelope-from=mark.cave-ayland@ilande.co.uk; helo=mail.ilande.co.uk X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 23:12:16 -0000 On 08/01/2023 02:36, Richard Henderson wrote: > Changes for v4: > * About half of the v3 series has been merged, > * AArch64 host requires even argument register. > * target/{arm,ppc,s390x,i386} uses included here. > > Patches requiring review: > 01-tcg-Define-TCG_TYPE_I128-and-related-helper-macro.patch > 02-tcg-Handle-dh_typecode_i128-with-TCG_CALL_-RET-AR.patch > 03-tcg-Allocate-objects-contiguously-in-temp_allocat.patch > 05-tcg-Add-TCG_CALL_-RET-ARG-_BY_REF.patch > 07-tcg-Add-TCG_CALL_RET_BY_VEC.patch > 08-include-qemu-int128-Use-Int128-structure-for-TCI.patch > 09-tcg-i386-Add-TCG_TARGET_CALL_-RET-ARG-_I128.patch > 10-tcg-tci-Fix-big-endian-return-register-ordering.patch > 11-tcg-tci-Add-TCG_TARGET_CALL_-RET-ARG-_I128.patch > 13-tcg-Add-temp-allocation-for-TCGv_i128.patch > 14-tcg-Add-basic-data-movement-for-TCGv_i128.patch > 15-tcg-Add-guest-load-store-primitives-for-TCGv_i128.patch > 16-tcg-Add-tcg_gen_-non-atomic_cmpxchg_i128.patch > 17-tcg-Split-out-tcg_gen_nonatomic_cmpxchg_i-32-64.patch > 24-target-s390x-Use-a-single-return-for-helper_divs3.patch > 31-target-s390x-Use-Int128-for-passing-float128.patch > 32-target-s390x-Use-tcg_gen_atomic_cmpxchg_i128-for-.patch > 33-target-s390x-Implement-CC_OP_NZ-in-gen_op_calc_cc.patch > 34-target-i386-Split-out-gen_cmpxchg8b-gen_cmpxchg16.patch > 35-target-i386-Inline-cmpxchg8b.patch > 36-target-i386-Inline-cmpxchg16b.patch > > > r~ > > > Ilya Leoshkevich (2): > tests/tcg/s390x: Add div.c > tests/tcg/s390x: Add clst.c > > Richard Henderson (34): > tcg: Define TCG_TYPE_I128 and related helper macros > tcg: Handle dh_typecode_i128 with TCG_CALL_{RET,ARG}_NORMAL > tcg: Allocate objects contiguously in temp_allocate_frame > tcg: Introduce tcg_out_addi_ptr > tcg: Add TCG_CALL_{RET,ARG}_BY_REF > tcg: Introduce tcg_target_call_oarg_reg > tcg: Add TCG_CALL_RET_BY_VEC > include/qemu/int128: Use Int128 structure for TCI > tcg/i386: Add TCG_TARGET_CALL_{RET,ARG}_I128 > tcg/tci: Fix big-endian return register ordering > tcg/tci: Add TCG_TARGET_CALL_{RET,ARG}_I128 > tcg: Add TCG_TARGET_CALL_{RET,ARG}_I128 > tcg: Add temp allocation for TCGv_i128 > tcg: Add basic data movement for TCGv_i128 > tcg: Add guest load/store primitives for TCGv_i128 > tcg: Add tcg_gen_{non}atomic_cmpxchg_i128 > tcg: Split out tcg_gen_nonatomic_cmpxchg_i{32,64} > target/arm: Use tcg_gen_atomic_cmpxchg_i128 for STXP > target/arm: Use tcg_gen_atomic_cmpxchg_i128 for CASP > target/ppc: Use tcg_gen_atomic_cmpxchg_i128 for STQCX > tests/tcg/s390x: Add long-double.c > target/s390x: Use a single return for helper_divs32/u32 > target/s390x: Use a single return for helper_divs64/u64 > target/s390x: Use Int128 for return from CLST > target/s390x: Use Int128 for return from CKSM > target/s390x: Use Int128 for return from TRE > target/s390x: Copy wout_x1 to wout_x1_P > target/s390x: Use Int128 for returning float128 > target/s390x: Use Int128 for passing float128 > target/s390x: Use tcg_gen_atomic_cmpxchg_i128 for CDSG > target/s390x: Implement CC_OP_NZ in gen_op_calc_cc > target/i386: Split out gen_cmpxchg8b, gen_cmpxchg16b > target/i386: Inline cmpxchg8b > target/i386: Inline cmpxchg16b > > accel/tcg/tcg-runtime.h | 11 + > include/exec/cpu_ldst.h | 10 + > include/exec/helper-head.h | 7 + > include/qemu/atomic128.h | 29 ++- > include/qemu/int128.h | 25 +- > include/tcg/tcg-op.h | 15 ++ > include/tcg/tcg.h | 49 +++- > target/arm/helper-a64.h | 8 - > target/i386/helper.h | 6 - > target/ppc/helper.h | 2 - > target/s390x/helper.h | 54 ++--- > tcg/aarch64/tcg-target.h | 2 + > tcg/arm/tcg-target.h | 2 + > tcg/i386/tcg-target.h | 10 + > tcg/loongarch64/tcg-target.h | 2 + > tcg/mips/tcg-target.h | 2 + > tcg/riscv/tcg-target.h | 3 + > tcg/s390x/tcg-target.h | 2 + > tcg/sparc64/tcg-target.h | 2 + > tcg/tcg-internal.h | 17 ++ > tcg/tci/tcg-target.h | 3 + > target/s390x/tcg/insn-data.h.inc | 60 ++--- > accel/tcg/cputlb.c | 112 +++++++++ > accel/tcg/user-exec.c | 66 ++++++ > target/arm/helper-a64.c | 147 ------------ > target/arm/translate-a64.c | 121 +++++----- > target/i386/tcg/mem_helper.c | 126 ---------- > target/i386/tcg/translate.c | 126 ++++++++-- > target/ppc/mem_helper.c | 44 ---- > target/ppc/translate.c | 102 ++++---- > target/s390x/tcg/fpu_helper.c | 103 ++++---- > target/s390x/tcg/int_helper.c | 64 ++--- > target/s390x/tcg/mem_helper.c | 77 +----- > target/s390x/tcg/translate.c | 217 +++++++++++------ > tcg/tcg-op.c | 393 ++++++++++++++++++++++++++----- > tcg/tcg.c | 303 +++++++++++++++++++++--- > tcg/tci.c | 65 ++--- > tests/tcg/s390x/clst.c | 82 +++++++ > tests/tcg/s390x/div.c | 75 ++++++ > tests/tcg/s390x/long-double.c | 24 ++ > util/int128.c | 42 ++++ > accel/tcg/atomic_common.c.inc | 45 ++++ > tcg/aarch64/tcg-target.c.inc | 17 +- > tcg/arm/tcg-target.c.inc | 30 ++- > tcg/i386/tcg-target.c.inc | 52 +++- > tcg/loongarch64/tcg-target.c.inc | 17 +- > tcg/mips/tcg-target.c.inc | 17 +- > tcg/ppc/tcg-target.c.inc | 20 +- > tcg/riscv/tcg-target.c.inc | 17 +- > tcg/s390x/tcg-target.c.inc | 16 +- > tcg/sparc64/tcg-target.c.inc | 19 +- > tcg/tci/tcg-target.c.inc | 27 ++- > tests/tcg/s390x/Makefile.target | 3 + > 53 files changed, 1936 insertions(+), 954 deletions(-) > create mode 100644 tests/tcg/s390x/clst.c > create mode 100644 tests/tcg/s390x/div.c > create mode 100644 tests/tcg/s390x/long-double.c Now that the TCG documentation is more visible, would it be possible to add a patch to update the relevant parts of docs/devel/tcg-ops.rst to reflect the new Int128 support? ATB, Mark. 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charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 10 Jan 2023 23:27:20 -0000 Richard Henderson writes: > Begin staging in support for TCGv_i128 with Int128. > Define the type enumerator, the typedef, and the > helper-head.h macros. > > This cannot yet be used, because you can't allocate > temporaries of this new type. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro From MAILER-DAEMON Wed Jan 11 00:01:11 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFTEd-00018a-8K for mharc-qemu-riscv@gnu.org; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a33; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa33.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 05:01:10 -0000 On Wed, Dec 28, 2022 at 4:23 PM Weiwei Li wrote: > > This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version instru= ctions. > > Specification: > https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specifica= tion > > The port is available here: > https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v9 > > To test Zc* implementation, specify cpu argument with 'x-zca=3Dtrue,x-zcb= =3Dtrue,x-zcf=3Dtrue,f=3Dtrue" and "x-zcd=3Dtrue,d=3Dtrue" (or "x-zcmp=3Dtr= ue,x-zcmt=3Dtrue" with c or d=3Dfalse) to enable Zca/Zcb/Zcf and Zcd(or Zcm= p,Zcmt) extensions support. > > > This implementation can pass the basic zc tests from https://github.com/y= ulong-plct/zc-test > > v9: > * rebase on riscv-to-apply.next > > v8: > * improve disas support in Patch 9 > > v7: > * Fix description for Zca > > v6=EF=BC=9A > * fix base address for jump table in Patch 7 > * rebase on riscv-to-apply.next > > v5: > * fix exception unwind problem for cpu_ld*_code in helper of cm_jalt > > v4: > * improve Zcmp suggested by Richard > * fix stateen related check for Zcmt > > v3: > * update the solution for Zcf to the way of Zcd > * update Zcb to reuse gen_load/store > * use trans function instead of helper for push/pop > > v2: > * add check for relationship between Zca/Zcf/Zcd with C/F/D based on rela= ted discussion in review of Zc* spec > * separate c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/= zcmt > > Weiwei Li (9): > target/riscv: add cfg properties for Zc* extension > target/riscv: add support for Zca extension > target/riscv: add support for Zcf extension > target/riscv: add support for Zcd extension > target/riscv: add support for Zcb extension > target/riscv: add support for Zcmp extension > target/riscv: add support for Zcmt extension > target/riscv: expose properties for Zc* extension > disas/riscv.c: add disasm support for Zc* This series broke a range of boards that use specific CPUs. I have dropped it from my tree. Daniel has sent a series that should fix it though (https://www.mail-archive.com/qemu-devel@nongnu.org/msg930952.html). I have applied his fixes. Can you rebase this series on https://github.com/alistair23/qemu/tree/riscv-to-apply.next, test to ensure the SiFive boards continue to work and then re-send the series? Alistair > > disas/riscv.c | 228 +++++++++++++++- > target/riscv/cpu.c | 56 ++++ > target/riscv/cpu.h | 10 + > target/riscv/cpu_bits.h | 7 + > target/riscv/csr.c | 38 ++- > target/riscv/helper.h | 3 + > target/riscv/insn16.decode | 63 ++++- > target/riscv/insn_trans/trans_rvd.c.inc | 18 ++ > target/riscv/insn_trans/trans_rvf.c.inc | 18 ++ > target/riscv/insn_trans/trans_rvi.c.inc | 4 +- > target/riscv/insn_trans/trans_rvzce.c.inc | 313 ++++++++++++++++++++++ > target/riscv/machine.c | 19 ++ > target/riscv/meson.build | 3 +- > target/riscv/translate.c | 15 +- > target/riscv/zce_helper.c | 55 ++++ > 15 files changed, 834 insertions(+), 16 deletions(-) > create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc > create mode 100644 target/riscv/zce_helper.c > > -- > 2.25.1 > > From MAILER-DAEMON Wed Jan 11 00:02:23 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFTFm-0001Y2-Tb for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 00:02:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFTFk-0001U6-VC; Wed, 11 Jan 2023 00:02:20 -0500 Received: from mail-vs1-xe34.google.com ([2607:f8b0:4864:20::e34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFTFj-0004TA-83; Wed, 11 Jan 2023 00:02:20 -0500 Received: by mail-vs1-xe34.google.com with SMTP id 3so14564716vsq.7; Tue, 10 Jan 2023 21:02:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=JaKX4u37aTWkO2V9iJYFOqpb4Hx9pLyzHtLcnzVOI/4=; b=Cm9pEwd0wbm/ZkH+u11+GLx+i5Mx6VZoMplRCi24JxwQsJi3QNPJyp60OEcCxSNvTS j+u/Lzu9QyRcIhNuYVtJ/xjMvZExF1tA99xCn9iVrSIDbjQFt4f+rrFmcgw+dsIqzc/Y K+M5zdvrAxbHa8RkYslrfmiLtBSrv4MXXk4YMYPTv1F4PQVpkXJPU4BIlVtG7KfOetq3 ioEyt/S91Ctizfr+emHk4TosBmQaDG8FlDosdcJwGgn1HYfP5eKGIMIfrfL21cQgulHA oG+QcsR6M/5WllPwGdX2pU3WwOzkhwnETK05De7uVFNtrlS3S+bKFZmN/XYqMyGZf1q4 scjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=JaKX4u37aTWkO2V9iJYFOqpb4Hx9pLyzHtLcnzVOI/4=; b=0CeUDJtruUpb19Ek1PO3k3YmFycYcCLeT4mCFqnASiFvnJuxL7c6r17jMby6tsHmv2 TSQhEehbwyaeasLjB+NlDnIgjDY+OBHe4QJWMQ2g68u+D3u41nHiOPrwtF9ncSUtHSXg Ej7Qbevw9wr5qzlIyMHPFUtr1RkYU/Gx22QgxQHmrhZgO88viTyR4IkJihP6vNhBvaOV QkIF7I4FP4ssy2mdNKDhb4o0ejXdxOrqRgNNTv2mqJkrussNt6TYZLLkk3UVnDk9/qV0 ixxdRW+Owgwmavw0YQQXNSYybCGHeP+YyvrWV8YQ59E1y2KM0zDsvC3Cb1GbKQy3aBXK yhWw== X-Gm-Message-State: AFqh2kptTCIhwyGuvk53cXaDitQSHCTJlcNznZ+eBcodr4t+5x9h7ihh oQMC5xABT9jABIVQeCNulxw4V2qLEnG2Md9P+KY= X-Google-Smtp-Source: AMrXdXtQO6s4AGq0C6dqhTq73sgbXCMCFZtcv1rwpveQGiSPVlV/Nvhsr+4tcmjZ284sf9CeSiTrOTCTa5oZEHY0w8k= X-Received: by 2002:a05:6102:510e:b0:3b1:2b83:1861 with SMTP id bm14-20020a056102510e00b003b12b831861mr9412409vsb.10.1673413337946; Tue, 10 Jan 2023 21:02:17 -0800 (PST) MIME-Version: 1.0 References: <20230110201405.247785-1-dbarboza@ventanamicro.com> In-Reply-To: <20230110201405.247785-1-dbarboza@ventanamicro.com> From: Alistair Francis Date: Wed, 11 Jan 2023 15:01:51 +1000 Message-ID: Subject: Re: [PATCH 0/2] target/riscv/cpu: fix sifive_u 32/64bits boot in riscv-to-apply.next To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, richard.henderson@linaro.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e34; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe34.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 05:02:21 -0000 On Wed, Jan 11, 2023 at 6:17 AM Daniel Henrique Barboza wrote: > > Hi, > > I found this bug when testing my avocado changes in riscv-to-apply.next. > The sifive_u board, both 32 and 64 bits, stopped booting OpenSBI. The > guest hangs indefinitely. > > Git bisect points that this patch broke things: > > 8c3f35d25e7e98655c609b6c1e9f103b9240f8f8 is the first bad commit > commit 8c3f35d25e7e98655c609b6c1e9f103b9240f8f8 > Author: Weiwei Li > Date: Wed Dec 28 14:20:21 2022 +0800 > > target/riscv: add support for Zca extension > > Modify the check for C extension to Zca (C implies Zca) > (https://github.com/alistair23/qemu/commit/8c3f35d25e7e98655c609b6c1e9f103b9240f8f8) > > > But this patch per se isn't doing anything wrong. The root of the > problem is that this patch makes assumptions based on the previous > patch: > > commit a2b409aa6cadc1ed9715e1ab916ddd3dade0ba85 > Author: Weiwei Li > Date: Wed Dec 28 14:20:20 2022 +0800 > > target/riscv: add cfg properties for Zc* extension > (https://github.com/alistair23/qemu/commit/a2b409aa6cadc1ed9715e1ab916ddd3dade0ba85) > > Which added a lot of logic and assumptions that are being skipped by all > the SiFive boards because, during riscv_cpu_realize(), we have this > code: > > /* If only MISA_EXT is unset for misa, then set it from properties */ > if (env->misa_ext == 0) { > uint32_t ext = 0; > (...) > } > > In short, we have a lot of code that are being skipped by all SiFive > CPUs because these CPUs are setting a non-zero value in set_misa() in > their respective cpu_init() functions. > > It's possible to just hack in and fix the SiFive problem in isolate, but > I believe we can do better and allow all riscv_cpu_realize() to be executed > for all CPUs, regardless of what they've done during their cpu_init(). > > > Daniel Henrique Barboza (2): > target/riscv/cpu: set cpu->cfg in register_cpu_props() > target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() Thanks for the patches I have rebased these onto the latest master and dropped the other series. That way when the other series is applied we don't break bisectability. Alistair > > target/riscv/cpu.c | 525 +++++++++++++++++++++++++-------------------- > target/riscv/cpu.h | 4 + > 2 files changed, 292 insertions(+), 237 deletions(-) > > -- > 2.39.0 > > From MAILER-DAEMON Wed Jan 11 00:09:06 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFTMH-00032x-R3 for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 00:09:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFTMF-00032d-Nz; Wed, 11 Jan 2023 00:09:03 -0500 Received: from mail-vs1-xe31.google.com ([2607:f8b0:4864:20::e31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFTMC-0005Nr-RV; Wed, 11 Jan 2023 00:09:03 -0500 Received: by mail-vs1-xe31.google.com with SMTP id i188so14560288vsi.8; Tue, 10 Jan 2023 21:09:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; 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Tue, 10 Jan 2023 21:08:59 -0800 (PST) MIME-Version: 1.0 References: <20230102115241.25733-1-dbarboza@ventanamicro.com> In-Reply-To: <20230102115241.25733-1-dbarboza@ventanamicro.com> From: Alistair Francis Date: Wed, 11 Jan 2023 15:08:33 +1000 Message-ID: Subject: Re: [PATCH v5 00/11] riscv: OpenSBI boot test and cleanups To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e31; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe31.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 05:09:04 -0000 On Mon, Jan 2, 2023 at 9:54 PM Daniel Henrique Barboza wrote: > > Hi, > > This new version is still rebased on top of [1]: > > "[PATCH v2 00/12] hw/riscv: Improve Spike HTIF emulation fidelity" > > from Bin Meng. > > The change from v4 is on patch 9 where we added an extra flag in > riscv_load_kernel() to allow for boards that don't load initrd > (e.g. opentitan and sifive_e) to opt out from loading it altogether. > > * Patch without reviews: 9 > > Changes from v4: > - patch 9: > - added a 'load_init' flag in riscv_load_kernel() to control whether > the function should execute riscv_load_initrd() or not > v4 link: https://lists.gnu.org/archive/html/qemu-devel/2022-12/msg04652.html > > Changes from v3: > - patch 1: > - fixed more instances of 'opensbi' and 'Opensbi' to 'OpenSBI' > - changed tests order > - patch 4 (new): > - added a g_assert(filename) guard in riscv_load_initrd() and > riscv_load_kernel() > v3 link: https://mail.gnu.org/archive/html/qemu-devel/2022-12/msg04491.html > > Changes from v2: > - patch 1: > - reduced code repetition with a boot_opensbi() helper > - renamed 'opensbi' to 'OpenSBI' in the file header > - patch 9: > - renamed riscv_load_kernel() to riscv_load_kernel_and_initrd() > v2 link: https://mail.gnu.org/archive/html/qemu-devel/2022-12/msg04466.html > > > Changes from v1: > - patches were rebased with [1] > - patches 13-15: removed > * will be re-sent in a follow-up series > - patches 4-5: removed since they're picked by Bin in [1] > - patch 1: > - added a 'skip' riscv32 spike test > v1 link: https://mail.gnu.org/archive/html/qemu-devel/2022-12/msg03860.html > > > Based-on: <20221227064812.1903326-1-bmeng@tinylab.org> > > Cc: Alistair Francis > Cc: Bin Meng > > [1] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334352 > > Daniel Henrique Barboza (11): > tests/avocado: add RISC-V OpenSBI boot test > hw/riscv/spike: use 'fdt' from MachineState > hw/riscv/sifive_u: use 'fdt' from MachineState > hw/riscv/boot.c: exit early if filename is NULL in load functions > hw/riscv/spike.c: load initrd right after riscv_load_kernel() > hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() > hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() > hw/riscv/boot.c: use MachineState in riscv_load_initrd() > hw/riscv/boot.c: use MachineState in riscv_load_kernel() > hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() > hw/riscv/boot.c: make riscv_load_initrd() static Thanks! Applied to riscv-to-apply.next Alistair > > hw/riscv/boot.c | 91 +++++++++++++++++++++++----------- > hw/riscv/microchip_pfsoc.c | 20 +------- > hw/riscv/opentitan.c | 3 +- > hw/riscv/sifive_e.c | 4 +- > hw/riscv/sifive_u.c | 32 +++--------- > hw/riscv/spike.c | 37 ++++---------- > hw/riscv/virt.c | 21 +------- > include/hw/riscv/boot.h | 5 +- > include/hw/riscv/sifive_u.h | 3 -- > include/hw/riscv/spike.h | 2 - > tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++ > 11 files changed, 150 insertions(+), 133 deletions(-) > create mode 100644 tests/avocado/riscv_opensbi.py > > -- > 2.39.0 > > From MAILER-DAEMON Wed Jan 11 00:39:23 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFTpb-0007co-Ob for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 00:39:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFTpa-0007cJ-6o for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 00:39:22 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFTpY-00026a-O7 for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 00:39:21 -0500 Received: by mail-pj1-x1029.google.com with SMTP id h7-20020a17090aa88700b00225f3e4c992so18876182pjq.1 for ; Tue, 10 Jan 2023 21:39:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=1mILLToEQSFznoisqcOMWl3SJWfi8lRpBkCgUozEfIs=; b=sy2MKt7M0vIYExT2CmpnYfeq51Sks47HoUIweLLxVmIxqhg5Mi9QZ9Hw16ho1ZkQde uHA176M88tEEN9DdhldCN1meg8fkuuhw5mqFRrcVzcwk+StH13zHCT7xGMsNRKeUe0ac J6WxDAYy7dX6WEb3PALa9WMXHmctrMEdwiWlWmzNs+KBO2LwbUn8WXPYjRblpT4GwiY8 MVnlEr6VAnI9Tg1kM+1x7f23Hj2JpZOH0pMrJGThj2xRrBUnkoxN51rT7E+u7CGsOYmo ROqmrRgbOub92OiE1pRTmvzFkrhfxAbcpb7cir/Zl8pBTziviyhTHXhz7tsUf5kib9G2 A+/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=1mILLToEQSFznoisqcOMWl3SJWfi8lRpBkCgUozEfIs=; b=mPiFwedgxORLMaeU1+JZ4OxUX2yO6aOtGwDbmT/JzlQoY/tp+jUAl2KkDBER9Isiws osiNJGryemhz/2XrGnrl8R7RCouCROBQHjqxwQs6OvAcWZZRu9G+oJhyPErh861yQxOc W5HeqAqZuCRkM0TjIhg6k4iLik0XMiW9nS/548V8W1WMnDZ217USptVK5/l7BE68KUKJ 1uTrMTMCR7/yS71ID9TIdSJ2MobtNc5hpK2K0+kSY8sBhri0nsni2hRfj5UwEm49fiDt 4rSc2vwDFUsUtgLTMnz3KujfakJwfS/o/KsJxpUCQo9QXZNJPRN3ZdDkSSfgG5RT0DGS 6aPA== X-Gm-Message-State: AFqh2kphNEz0QjMMvMqMwO+iOSfCs2jBwgWKNObfncPbREF7zTThn2EH VFlAYa1RJfMsfj46fBweSu3Gag== X-Google-Smtp-Source: AMrXdXtbriMkJCCnSao5aFgrcC9mn+lvbGzgy0MRyDHtTGIZVN47k0epXGw+oH6iv6qNpzv2YoFV5Q== X-Received: by 2002:a17:902:9b86:b0:194:4b48:f7f1 with SMTP id y6-20020a1709029b8600b001944b48f7f1mr1109091plp.17.1673415559073; Tue, 10 Jan 2023 21:39:19 -0800 (PST) Received: from [192.168.0.115] (63-157-97-90.dia.static.qwest.net. [63.157.97.90]) by smtp.gmail.com with ESMTPSA id v7-20020a1709028d8700b00192902287d1sm8986860plo.288.2023.01.10.21.39.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Jan 2023 21:39:18 -0800 (PST) Message-ID: Date: Tue, 10 Jan 2023 21:39:16 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH 1/2] target/riscv/cpu: set cpu->cfg in register_cpu_props() Content-Language: en-US To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com References: <20230110201405.247785-1-dbarboza@ventanamicro.com> <20230110201405.247785-2-dbarboza@ventanamicro.com> From: Richard Henderson In-Reply-To: <20230110201405.247785-2-dbarboza@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 05:39:22 -0000 On 1/10/23 12:14, Daniel Henrique Barboza wrote: > +/* > + * Register CPU props based on env.misa_ext. If a non-zero > + * value was set, register only the required cpu->cfg.ext_* > + * properties and leave. env.misa_ext = 0 means that we want > + * all the default properties to be registered. > + */ > static void register_cpu_props(DeviceState *dev) Suggest invoking this as .instance_post_init hook on TYPE_RISCV_CPU. Then you don't need to manually call it on every cpu class. r~ From MAILER-DAEMON Wed Jan 11 00:55:27 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFU58-0003nB-5o for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 00:55:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFU52-0003mO-4w; Wed, 11 Jan 2023 00:55:21 -0500 Received: from mail-ej1-x633.google.com ([2a00:1450:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFU50-0004q8-Eq; Wed, 11 Jan 2023 00:55:19 -0500 Received: by mail-ej1-x633.google.com with SMTP id ss4so26936524ejb.11; Tue, 10 Jan 2023 21:55:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=oTsQvlLXDij0T2arwwsxKvmrZt8+Xx79D23KJCCsFJ4=; b=gdPIrXX5XeSfFuTuKbD7fWc7vfI3tVvDnblrJ25ktXPDJCy7zC9MzGpxyDm3ofgfM0 RQnCFUWSczY3bOk+XyLky+yYmpK8stGnngs95cuR+AKxQl8WP2CYLG+wuOJ/qtmEZaNH inKqeNuG5qIQBJZcWMZoE6xe6qmzdrljXj5y9rBFi5+sipv6PNdHSN4+c30Op5fSIngj 134/07Y4B0mlgbLaChKQ0v9D0rS19+9UCcsPIncOR4P49rvHEBYs/79Bg0ez4Ed/IWNS PMHh2SPHeL4UTiSv3iG90BuiDr4O4sNTdefFMUJ4no07ItGTFhh/B9zadA0QTJOVRdVD ZVLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=oTsQvlLXDij0T2arwwsxKvmrZt8+Xx79D23KJCCsFJ4=; b=Uf9ZiwpHoxnwZMpsIVmC3OgbiLL1GifVfEXv3sJ4ARIZsEQH+vlv+3yaAgWuDfRmWQ IWFT/cM5WPvUfuXugfMfZUqQ4YKEkkQOmx3EndbPnLqD2D/X3Wy5pl5vKcWmASQFVSM1 BKQ2AItoT/gthBtowngj1yEsf3Bk//an/Q9rArG31Pw6XmZ2tbyqw1tdUnBlSJrL7zN0 3vXZaZ+jVtM9ww7qprDjYLTj8RMa4m6ad7Wmi7nf1WYZZ3P7O3zcUijawAA267xIlB4a TceSZinjI7Itnadd53woYH2+Isc+eTT/weZqwpLrdz7BBsw+yww+jpXWQUgtNtfVIptk tSNg== X-Gm-Message-State: AFqh2koDnv12SbM91iH9MNbF7H6WwYZoIAqMHaz4UREP2BYoBbva6r7n mxASMM17u5GZy9n+2nvtgJxAeTSiwQNuTdpX4jY= X-Google-Smtp-Source: AMrXdXstIgNzdQgI3/6hSZDBoyiJuQjlPg2Gg27UxT0LU9XRTyHWW6+xLQCfmjbnGC32tqDzo/9KK4G23EVRroTNvB0= X-Received: by 2002:a17:906:5798:b0:7c0:dcb3:718b with SMTP id k24-20020a170906579800b007c0dcb3718bmr4319696ejq.711.1673416516021; Tue, 10 Jan 2023 21:55:16 -0800 (PST) MIME-Version: 1.0 References: <20230110201405.247785-1-dbarboza@ventanamicro.com> <20230110201405.247785-2-dbarboza@ventanamicro.com> In-Reply-To: <20230110201405.247785-2-dbarboza@ventanamicro.com> From: Bin Meng Date: Wed, 11 Jan 2023 13:55:04 +0800 Message-ID: Subject: Re: [PATCH 1/2] target/riscv/cpu: set cpu->cfg in register_cpu_props() To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, richard.henderson@linaro.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 05:55:22 -0000 On Wed, Jan 11, 2023 at 4:17 AM Daniel Henrique Barboza wrote: > > There is an informal contract between the cpu_init() functions and > riscv_cpu_realize(): if cpu->env.misa_ext is zero, assume that the > default settings were loaded via register_cpu_props() and do validations > to set env.misa_ext. If it's not zero, skip this whole process and > assume that the board somehow did everything. > > At this moment, all SiFive CPUs are setting a non-zero misa_ext during > their cpu_init() and skipping a good chunk of riscv_cpu_realize(). > This causes problems when the code being skipped in riscv_cpu_realize() > contains fixes or assumptions that affects all CPUs, meaning that SiFive > CPUs are missing out. > > To allow this code to not be skipped anymore, all the cpu->cfg.ext_* attributes > needs to be set during cpu_init() time. At this moment this is being done in > register_cpu_props(). The SiFive oards are setting their own extensions during The SiFive boards > cpu_init() though, meaning that they don't want all the defaults from > register_cpu_props(). > > Let's move the contract between *_cpu_init() and riscv_cpu_realize() to > register_cpu_props(). Inside this function we'll check if cpu->env.misa_ext > was set and, if that's the case, set all relevant cpu->cfg.ext_* > attributes, and only that. Leave the 'misa_ext' = 0 case as is today, > i.e. loading all the defaults from riscv_cpu_extensions[]. > > register_cpu_props() can then be called by all the cpu_init() functions, > including the SiFive ones. This will make all CPUs behave more in line > with that riscv_cpu_realize() expects. with what > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu.c | 40 ++++++++++++++++++++++++++++++++++++++++ > target/riscv/cpu.h | 4 ++++ > 2 files changed, 44 insertions(+) > Regards, Bin From MAILER-DAEMON Wed Jan 11 00:56:26 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFU66-00047Z-Hr for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 00:56:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFU65-000477-CV; Wed, 11 Jan 2023 00:56:25 -0500 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFU62-00056u-6K; Wed, 11 Jan 2023 00:56:25 -0500 Received: by mail-ed1-x534.google.com with SMTP id s5so20802085edc.12; Tue, 10 Jan 2023 21:56:21 -0800 (PST) DKIM-Signature: v=1; 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Tue, 10 Jan 2023 21:56:20 -0800 (PST) MIME-Version: 1.0 References: <20230110201405.247785-1-dbarboza@ventanamicro.com> <20230110201405.247785-3-dbarboza@ventanamicro.com> In-Reply-To: <20230110201405.247785-3-dbarboza@ventanamicro.com> From: Bin Meng Date: Wed, 11 Jan 2023 13:56:08 +0800 Message-ID: Subject: Re: [PATCH 2/2] target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, richard.henderson@linaro.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=bmeng.cn@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 05:56:25 -0000 On Wed, Jan 11, 2023 at 4:17 AM Daniel Henrique Barboza wrote: > > All RISCV CPUs are setting cpu->cfg during their cpu_init() functions, > meaning that there's no reason to skip all the misa validation and setup > if misa_ext was set beforehand - especially since we're setting an > updated value in set_misa() in the end. > > Put this code chunk into a new riscv_cpu_validate_set_extensions() > helper and always execute it regardless of what the board set in > env->misa_ext. > > This will put more responsibility in how each board is going to init > their attributes and extensions if they're not using the defaults. > It'll also allow realize() to do its job looking only at the extensions > enabled per se, not corner cases that some CPUs might have, and we won't > have to change multiple code paths to fix or change how extensions work. > > Signed-off-by: Daniel Henrique Barboza > --- > target/riscv/cpu.c | 485 +++++++++++++++++++++++---------------------- > 1 file changed, 248 insertions(+), 237 deletions(-) > Reviewed-by: Bin Meng From MAILER-DAEMON Wed Jan 11 02:10:34 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFVFp-0000VT-IZ for mharc-qemu-riscv@gnu.org; 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Tue, 10 Jan 2023 23:10:16 -0800 (PST) Message-ID: <92cd2724-6a14-deb1-923c-dad28de5e8c6@linaro.org> Date: Wed, 11 Jan 2023 08:10:14 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH] bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx Content-Language: en-US To: BALATON Zoltan Cc: qemu-devel@nongnu.org, Peter Maydell , qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , =?UTF-8?Q?Alex_Benn=c3=a9e?= , ale@rev.ng, qemu-riscv@nongnu.org, xen-devel@lists.xenproject.org, Thomas Huth References: <20230110212947.34557-1-philmd@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 07:10:30 -0000 On 10/1/23 23:01, BALATON Zoltan wrote: > On Tue, 10 Jan 2023, Philippe Mathieu-Daudé wrote: >> The 'hwaddr' type is defined in "exec/hwaddr.h" as: >> >>    hwaddr is the type of a physical address >>   (its size can be different from 'target_ulong'). >> >> All definitions use the 'HWADDR_' prefix, except TARGET_FMT_plx: >> >> $ fgrep define include/exec/hwaddr.h >> #define HWADDR_H >> #define HWADDR_BITS 64 >> #define HWADDR_MAX UINT64_MAX >> #define TARGET_FMT_plx "%016" PRIx64 >>         ^^^^^^ >> #define HWADDR_PRId PRId64 >> #define HWADDR_PRIi PRIi64 >> #define HWADDR_PRIo PRIo64 >> #define HWADDR_PRIu PRIu64 >> #define HWADDR_PRIx PRIx64 > > Why are there both TARGET_FMT_plx and HWADDR_PRIx? Why not just use > HWADDR_PRIx instead? Too lazy to specify the 0-digit alignment format I presume? From MAILER-DAEMON Wed Jan 11 02:20:37 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFVPW-0007pA-Uw for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 02:20:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFVPC-0007A9-Qa; Wed, 11 Jan 2023 02:20:26 -0500 Received: from smtp25.cstnet.cn ([159.226.251.25] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFVP8-0001ZN-2A; Wed, 11 Jan 2023 02:20:14 -0500 Received: from [192.168.3.184] (unknown [61.165.33.198]) by APP-05 (Coremail) with SMTP id zQCowABXX+8YY75jzmApDA--.161S2; Wed, 11 Jan 2023 15:19:54 +0800 (CST) Message-ID: <046ab74f-30f6-8dcb-d0e8-ba634a909d8d@iscas.ac.cn> Date: Wed, 11 Jan 2023 15:19:52 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v9 0/9] support subsets of code size reduction extension To: Alistair Francis , Weiwei Li Cc: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wangjunqiang@iscas.ac.cn, lazyparser@gmail.com References: <20221228062028.29415-1-liweiwei@iscas.ac.cn> Content-Language: en-US From: weiwei In-Reply-To: Content-Type: text/plain; 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envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 07:20:30 -0000 On 2023/1/11 13:00, Alistair Francis wrote: > On Wed, Dec 28, 2022 at 4:23 PM Weiwei Li wrote: >> This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version instructions. >> >> Specification: >> https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification >> >> The port is available here: >> https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v9 >> >> To test Zc* implementation, specify cpu argument with 'x-zca=true,x-zcb=true,x-zcf=true,f=true" and "x-zcd=true,d=true" (or "x-zcmp=true,x-zcmt=true" with c or d=false) to enable Zca/Zcb/Zcf and Zcd(or Zcmp,Zcmt) extensions support. >> >> >> This implementation can pass the basic zc tests from https://github.com/yulong-plct/zc-test >> >> v9: >> * rebase on riscv-to-apply.next >> >> v8: >> * improve disas support in Patch 9 >> >> v7: >> * Fix description for Zca >> >> v6: >> * fix base address for jump table in Patch 7 >> * rebase on riscv-to-apply.next >> >> v5: >> * fix exception unwind problem for cpu_ld*_code in helper of cm_jalt >> >> v4: >> * improve Zcmp suggested by Richard >> * fix stateen related check for Zcmt >> >> v3: >> * update the solution for Zcf to the way of Zcd >> * update Zcb to reuse gen_load/store >> * use trans function instead of helper for push/pop >> >> v2: >> * add check for relationship between Zca/Zcf/Zcd with C/F/D based on related discussion in review of Zc* spec >> * separate c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/zcmt >> >> Weiwei Li (9): >> target/riscv: add cfg properties for Zc* extension >> target/riscv: add support for Zca extension >> target/riscv: add support for Zcf extension >> target/riscv: add support for Zcd extension >> target/riscv: add support for Zcb extension >> target/riscv: add support for Zcmp extension >> target/riscv: add support for Zcmt extension >> target/riscv: expose properties for Zc* extension >> disas/riscv.c: add disasm support for Zc* > This series broke a range of boards that use specific CPUs. I have > dropped it from my tree. > > Daniel has sent a series that should fix it though > (https://www.mail-archive.com/qemu-devel@nongnu.org/msg930952.html). I > have applied his fixes. Can you rebase this series on > https://github.com/alistair23/qemu/tree/riscv-to-apply.next, test to > ensure the SiFive boards continue to work and then re-send the series? > > Alistair This seems "C implies Zca" is not applied on specific CPUs and it'll be fixed if Zc* related check is moved to riscv_cpu_validate_set_extensions just as  Daniel's series. I'll rebase on it and test the CPUs in next version. Regards, Weiwei Li >> disas/riscv.c | 228 +++++++++++++++- >> target/riscv/cpu.c | 56 ++++ >> target/riscv/cpu.h | 10 + >> target/riscv/cpu_bits.h | 7 + >> target/riscv/csr.c | 38 ++- >> target/riscv/helper.h | 3 + >> target/riscv/insn16.decode | 63 ++++- >> target/riscv/insn_trans/trans_rvd.c.inc | 18 ++ >> target/riscv/insn_trans/trans_rvf.c.inc | 18 ++ >> target/riscv/insn_trans/trans_rvi.c.inc | 4 +- >> target/riscv/insn_trans/trans_rvzce.c.inc | 313 ++++++++++++++++++++++ >> target/riscv/machine.c | 19 ++ >> target/riscv/meson.build | 3 +- >> target/riscv/translate.c | 15 +- >> target/riscv/zce_helper.c | 55 ++++ >> 15 files changed, 834 insertions(+), 16 deletions(-) >> create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc >> create mode 100644 target/riscv/zce_helper.c >> >> -- >> 2.25.1 >> >> From MAILER-DAEMON Wed Jan 11 02:52:50 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFVuk-0004Jh-DY for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 02:52:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFVuW-0004FV-81; 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Wed, 11 Jan 2023 02:52:29 -0500 (EST) From: Klaus Jensen To: qemu-devel@nongnu.org, Peter Maydell Cc: Klaus Jensen , qemu-block@nongnu.org, Keith Busch , Klaus Jensen , qemu-stable@nongnu.org, qemu-riscv@nongnu.org, Guenter Roeck Subject: [PULL 4/6] hw/nvme: fix missing cq eventidx update Date: Wed, 11 Jan 2023 08:52:11 +0100 Message-Id: <20230111075213.70404-5-its@irrelevant.dk> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111075213.70404-1-its@irrelevant.dk> References: <20230111075213.70404-1-its@irrelevant.dk> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1414; i=k.jensen@samsung.com; h=from:subject; bh=ZXD346KYWBQ1ppNzRS48H9du8tV5U4eKh3aFsjFnjSA=; b=owJ4nAFtAZL+kA0DAAoBTeGvMW1PDekByyZiAGO+aq2oCgLaoNslR0/8Se/AFY4fl03KSFATsS2D lji6oaQEz4kBMwQAAQoAHRYhBFIoM6p14tzmokdmwE3hrzFtTw3pBQJjvmqtAAoJEE3hrzFtTw3pqX EIAIKyRJ2R3FFs91sLd4P03smHrDPltF9fp0PJW88rONRogEO70L2nHH/C8JdrPIZ8Ck7hz9bX+d0D HsV2oJy/FNvVt6KtjurkhRXuo+0lNhuMMZnPBicnEn+fsN4VbNJEfgIObQguer5GEVzQTA6xSCmUeo IEsSvLz5n6h4MpY+Ln3ik8EIa+FInQaaQQAowVTC4vnPQZgSjoEksGtpEmPltJlGX60f46wm1iJ+yH /2+elydbcb+Q+UgnukaSlkIs5ILzT97FNHIxMauOKb5yNmjHRBK26V2ybc2FL/p3ZWREKgY8MuPf18 a+DcYrWNOKoiSYBVe6dYY7DQz4+qHfZ/AXiaf7 X-Developer-Key: i=k.jensen@samsung.com; a=openpgp; fpr=DDCA4D9C9EF931CC3468427263D56FC5E55DA838 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=64.147.123.19; envelope-from=its@irrelevant.dk; helo=wout3-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 07:52:46 -0000 From: Klaus Jensen Prior to reading the shadow doorbell cq head, we have to update the eventidx. Otherwise, we risk that the driver will skip an mmio doorbell write. This happens on riscv64, as reported by Guenter. Adding the missing update to the cq eventidx fixes the issue. Fixes: 3f7fe8de3d49 ("hw/nvme: Implement shadow doorbell buffer support") Cc: qemu-stable@nongnu.org Cc: qemu-riscv@nongnu.org Reported-by: Guenter Roeck Reviewed-by: Keith Busch Signed-off-by: Klaus Jensen --- hw/nvme/ctrl.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 28e02ec7baa6..226480033771 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -1334,6 +1334,15 @@ static inline void nvme_blk_write(BlockBackend *blk, int64_t offset, } } +static void nvme_update_cq_eventidx(const NvmeCQueue *cq) +{ + uint32_t v = cpu_to_le32(cq->head); + + trace_pci_nvme_update_cq_eventidx(cq->cqid, cq->head); + + pci_dma_write(PCI_DEVICE(cq->ctrl), cq->ei_addr, &v, sizeof(v)); +} + static void nvme_update_cq_head(NvmeCQueue *cq) { uint32_t v; @@ -1358,6 +1367,7 @@ static void nvme_post_cqes(void *opaque) hwaddr addr; if (n->dbbuf_enabled) { + nvme_update_cq_eventidx(cq); nvme_update_cq_head(cq); } -- 2.39.0 From MAILER-DAEMON Wed Jan 11 03:00:01 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFW1h-0008Cd-1R for mharc-qemu-riscv@gnu.org; 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Treat this just like we currently break > down 64-bit quantities for a 32-bit host. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro From MAILER-DAEMON Wed Jan 11 03:39:26 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFWdq-0004el-9K for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 03:39:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFWde-0004Yc-HS for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 03:39:15 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFWdc-0005Nw-VB for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 03:39:14 -0500 Received: by mail-wm1-x334.google.com with SMTP id p3-20020a05600c1d8300b003d9ee5f125bso7292789wms.4 for ; Wed, 11 Jan 2023 00:39:12 -0800 (PST) DKIM-Signature: v=1; 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Wed, 11 Jan 2023 00:39:11 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id o11-20020a05600c4fcb00b003c6f3f6675bsm23898568wmq.26.2023.01.11.00.39.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 11 Jan 2023 00:39:10 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 0/4] bulk: Replace TARGET_FMT_plx by HWADDR_PRIx Date: Wed, 11 Jan 2023 09:39:05 +0100 Message-Id: <20230111083909.42624-1-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 08:39:20 -0000 Since v1: - Fix checkpatch style violations - Use HWADDR_PRIx instead of HWADDR_FMT_plx (Zoltan) Supersedes: <20230110212947.34557-1-philmd@linaro.org> "bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx" Philippe Mathieu-Daudé (4): hw: Remove hardcoded tabs (code style) bulk: Coding style fixes bulk: Replace TARGET_FMT_plx -> HWADDR_PRIx bulk: Prefix '0x' to hex values displayed with HWADDR_PRIx format accel/tcg/cputlb.c | 2 +- hw/arm/strongarm.c | 24 ++-- hw/block/pflash_cfi01.c | 5 +- hw/char/digic-uart.c | 8 +- hw/char/etraxfs_ser.c | 4 +- hw/core/loader.c | 8 +- hw/core/sysbus.c | 5 +- hw/display/cirrus_vga.c | 4 +- hw/display/g364fb.c | 4 +- hw/display/vga.c | 8 +- hw/dma/etraxfs_dma.c | 196 ++++++++++++++-------------- hw/dma/pl330.c | 26 ++-- hw/dma/xilinx_axidma.c | 4 +- hw/dma/xlnx_csu_dma.c | 4 +- hw/i2c/mpc_i2c.c | 4 +- hw/i386/multiboot.c | 9 +- hw/i386/xen/xen-hvm.c | 9 +- hw/i386/xen/xen-mapcache.c | 21 +-- hw/i386/xen/xen_platform.c | 4 +- hw/intc/arm_gicv3_dist.c | 8 +- hw/intc/arm_gicv3_its.c | 14 +- hw/intc/arm_gicv3_redist.c | 8 +- hw/intc/exynos4210_combiner.c | 20 +-- hw/misc/auxbus.c | 3 +- hw/misc/ivshmem.c | 6 +- hw/misc/macio/mac_dbdma.c | 4 +- hw/misc/mst_fpga.c | 162 ++++++++++++----------- hw/net/allwinner-sun8i-emac.c | 4 +- hw/net/allwinner_emac.c | 8 +- hw/net/fsl_etsec/etsec.c | 4 +- hw/net/fsl_etsec/rings.c | 4 +- hw/net/pcnet.c | 4 +- hw/net/rocker/rocker.c | 26 ++-- hw/net/rocker/rocker_desc.c | 2 +- hw/net/xilinx_axienet.c | 4 +- hw/net/xilinx_ethlite.c | 6 +- hw/pci-bridge/pci_expander_bridge.c | 2 +- hw/pci-host/bonito.c | 14 +- hw/pci-host/ppce500.c | 4 +- hw/pci/pci_host.c | 4 +- hw/ppc/ppc4xx_sdram.c | 2 +- hw/rtc/exynos4210_rtc.c | 4 +- hw/sh4/sh7750.c | 4 +- hw/ssi/xilinx_spi.c | 4 +- hw/ssi/xilinx_spips.c | 8 +- hw/timer/digic-timer.c | 8 +- hw/timer/etraxfs_timer.c | 3 +- hw/timer/exynos4210_mct.c | 2 +- hw/timer/exynos4210_pwm.c | 4 +- hw/virtio/virtio-mmio.c | 4 +- hw/xen/xen_pt.c | 4 +- include/exec/hwaddr.h | 1 - monitor/misc.c | 2 +- softmmu/memory.c | 19 +-- softmmu/memory_mapping.c | 4 +- softmmu/physmem.c | 10 +- target/i386/monitor.c | 6 +- target/loongarch/tlb_helper.c | 2 +- target/microblaze/op_helper.c | 2 +- target/mips/tcg/sysemu/tlb_helper.c | 2 +- target/ppc/mmu-hash32.c | 20 +-- target/ppc/mmu-hash64.c | 12 +- target/ppc/mmu_common.c | 30 +++-- target/ppc/mmu_helper.c | 4 +- target/riscv/cpu_helper.c | 10 +- target/riscv/monitor.c | 2 +- target/sparc/ldst_helper.c | 6 +- target/sparc/mmu_helper.c | 13 +- target/tricore/helper.c | 2 +- 69 files changed, 430 insertions(+), 424 deletions(-) -- 2.38.1 From MAILER-DAEMON Wed Jan 11 03:39:27 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFWdr-0004gM-C6 for mharc-qemu-riscv@gnu.org; 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Wed, 11 Jan 2023 00:39:20 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 2/4] bulk: Coding style fixes Date: Wed, 11 Jan 2023 09:39:07 +0100 Message-Id: <20230111083909.42624-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230111083909.42624-1-philmd@linaro.org> References: <20230111083909.42624-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 08:39:26 -0000 Fix the following checkpatch.pl violation on lines using the TARGET_FMT_plx definition to avoid: WARNING: line over 80 characters Signed-off-by: Philippe Mathieu-Daudé --- hw/block/pflash_cfi01.c | 5 +++-- hw/char/digic-uart.c | 8 ++++---- hw/core/sysbus.c | 3 ++- hw/dma/pl330.c | 16 +++++++++------- hw/i386/multiboot.c | 3 ++- hw/i386/xen/xen-hvm.c | 3 ++- hw/i386/xen/xen-mapcache.c | 13 ++++++++----- hw/intc/exynos4210_combiner.c | 20 ++++++++++---------- hw/misc/auxbus.c | 3 ++- hw/net/allwinner_emac.c | 8 ++++---- hw/timer/digic-timer.c | 8 ++++---- hw/timer/etraxfs_timer.c | 3 +-- softmmu/memory.c | 3 ++- target/ppc/mmu-hash32.c | 10 ++++++---- target/ppc/mmu_common.c | 8 +++++--- target/sparc/mmu_helper.c | 5 +++-- 16 files changed, 67 insertions(+), 52 deletions(-) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 0cbc2fb4cb..951419b2ed 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -645,8 +645,9 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset, error_flash: qemu_log_mask(LOG_UNIMP, "%s: Unimplemented flash cmd sequence " - "(offset " TARGET_FMT_plx ", wcycle 0x%x cmd 0x%x value 0x%x)" - "\n", __func__, offset, pfl->wcycle, pfl->cmd, value); + "(offset " TARGET_FMT_plx + ", wcycle 0x%x cmd 0x%x value 0x%x)\n", + __func__, offset, pfl->wcycle, pfl->cmd, value); mode_read_array: trace_pflash_mode_read_array(pfl->name); diff --git a/hw/char/digic-uart.c b/hw/char/digic-uart.c index 00e5df5517..3bbc43193b 100644 --- a/hw/char/digic-uart.c +++ b/hw/char/digic-uart.c @@ -62,8 +62,8 @@ static uint64_t digic_uart_read(void *opaque, hwaddr addr, default: qemu_log_mask(LOG_UNIMP, - "digic-uart: read access to unknown register 0x" - TARGET_FMT_plx "\n", addr << 2); + "digic-uart: read access to unknown register" + " 0x" TARGET_FMT_plx "\n", addr << 2); } return ret; @@ -100,8 +100,8 @@ static void digic_uart_write(void *opaque, hwaddr addr, uint64_t value, default: qemu_log_mask(LOG_UNIMP, - "digic-uart: write access to unknown register 0x" - TARGET_FMT_plx "\n", addr << 2); + "digic-uart: write access to unknown register" + " 0x" TARGET_FMT_plx "\n", addr << 2); } } diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c index 05c1da3d31..e8b31683e7 100644 --- a/hw/core/sysbus.c +++ b/hw/core/sysbus.c @@ -269,7 +269,8 @@ static void sysbus_dev_print(Monitor *mon, DeviceState *dev, int indent) for (i = 0; i < s->num_mmio; i++) { size = memory_region_size(s->mmio[i].memory); - monitor_printf(mon, "%*smmio " TARGET_FMT_plx "/" TARGET_FMT_plx "\n", + monitor_printf(mon, + "%*smmio " TARGET_FMT_plx "/" TARGET_FMT_plx "\n", indent, "", s->mmio[i].addr, size); } } diff --git a/hw/dma/pl330.c b/hw/dma/pl330.c index e5d521c329..60ce65c2a7 100644 --- a/hw/dma/pl330.c +++ b/hw/dma/pl330.c @@ -1337,8 +1337,8 @@ static void pl330_debug_exec(PL330State *s) } if (ch->stall) { trace_pl330_debug_exec_stall(); - qemu_log_mask(LOG_UNIMP, "pl330: stall of debug instruction not " - "implemented\n"); + qemu_log_mask(LOG_UNIMP, + "pl330: stall of debug instruction not implemented\n"); } s->debug_status = 0; } @@ -1372,9 +1372,10 @@ static void pl330_iomem_write(void *opaque, hwaddr offset, pl330_debug_exec(s); pl330_exec(s); } else { - qemu_log_mask(LOG_GUEST_ERROR, "pl330: write of illegal value %u " - "for offset " TARGET_FMT_plx "\n", (unsigned)value, - offset); + qemu_log_mask(LOG_GUEST_ERROR, + "pl330: write of illegal value %u" + " for offset " TARGET_FMT_plx "\n", + (unsigned)value, offset); } break; case PL330_REG_DBGINST0: @@ -1384,8 +1385,9 @@ static void pl330_iomem_write(void *opaque, hwaddr offset, s->dbg[1] = value; break; default: - qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad write offset " TARGET_FMT_plx - "\n", offset); + qemu_log_mask(LOG_GUEST_ERROR, + "pl330: bad write offset " TARGET_FMT_plx "\n", + offset); break; } } diff --git a/hw/i386/multiboot.c b/hw/i386/multiboot.c index 963e29362e..ec747245c2 100644 --- a/hw/i386/multiboot.c +++ b/hw/i386/multiboot.c @@ -353,7 +353,8 @@ int load_multiboot(X86MachineState *x86ms, mb_add_mod(&mbs, mbs.mb_buf_phys + offs, mbs.mb_buf_phys + offs + mb_mod_length, c); - mb_debug("mod_start: %p\nmod_end: %p\n cmdline: "TARGET_FMT_plx, + mb_debug("mod_start: %p\nmod_end: %p\n" + " cmdline: "TARGET_FMT_plx, (char *)mbs.mb_buf + offs, (char *)mbs.mb_buf + offs + mb_mod_length, c); g_free(one_file); diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c index e4293d6d66..67d250ab54 100644 --- a/hw/i386/xen/xen-hvm.c +++ b/hw/i386/xen/xen-hvm.c @@ -522,7 +522,8 @@ static void xen_set_memory(struct MemoryListener *listener, } } else { if (xen_remove_from_physmap(state, start_addr, size) < 0) { - DPRINTF("physmapping does not exist at "TARGET_FMT_plx"\n", start_addr); + DPRINTF("physmapping does not exist at "TARGET_FMT_plx"\n", + start_addr); } } } diff --git a/hw/i386/xen/xen-mapcache.c b/hw/i386/xen/xen-mapcache.c index a2f93096e7..491320e24a 100644 --- a/hw/i386/xen/xen-mapcache.c +++ b/hw/i386/xen/xen-mapcache.c @@ -357,7 +357,8 @@ tryagain: entry->lock++; if (entry->lock == 0) { fprintf(stderr, - "mapcache entry lock overflow: "TARGET_FMT_plx" -> %p\n", + "mapcache entry lock overflow: " + TARGET_FMT_plx" -> %p\n", entry->paddr_index, entry->vaddr_base); abort(); } @@ -404,8 +405,8 @@ ram_addr_t xen_ram_addr_from_mapcache(void *ptr) if (!found) { fprintf(stderr, "%s, could not find %p\n", __func__, ptr); QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) { - DPRINTF(" "TARGET_FMT_plx" -> %p is present\n", reventry->paddr_index, - reventry->vaddr_req); + DPRINTF(" "TARGET_FMT_plx" -> %p is present\n", + reventry->paddr_index, reventry->vaddr_req); } abort(); return 0; @@ -445,7 +446,8 @@ static void xen_invalidate_map_cache_entry_unlocked(uint8_t *buffer) if (!found) { DPRINTF("%s, could not find %p\n", __func__, buffer); QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) { - DPRINTF(" "TARGET_FMT_plx" -> %p is present\n", reventry->paddr_index, reventry->vaddr_req); + DPRINTF(" "TARGET_FMT_plx" -> %p is present\n", + reventry->paddr_index, reventry->vaddr_req); } return; } @@ -578,7 +580,8 @@ static uint8_t *xen_replace_cache_entry_unlocked(hwaddr old_phys_addr, if (!test_bits(address_offset >> XC_PAGE_SHIFT, test_bit_size >> XC_PAGE_SHIFT, entry->valid_mapping)) { - DPRINTF("Unable to update a mapcache entry for "TARGET_FMT_plx"!\n", + DPRINTF("Unable to update a mapcache entry for " + TARGET_FMT_plx "!\n", old_phys_addr); return NULL; } diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c index a289510bdb..44810bb63a 100644 --- a/hw/intc/exynos4210_combiner.c +++ b/hw/intc/exynos4210_combiner.c @@ -119,8 +119,8 @@ exynos4210_combiner_read(void *opaque, hwaddr offset, unsigned size) break; default: if (offset >> 2 >= IIC_REGSET_SIZE) { - hw_error("exynos4210.combiner: overflow of reg_set by 0x" - TARGET_FMT_plx "offset\n", offset); + hw_error("exynos4210.combiner: overflow of reg_set by" + " 0x" TARGET_FMT_plx "offset\n", offset); } val = s->reg_set[offset >> 2]; } @@ -183,20 +183,20 @@ static void exynos4210_combiner_write(void *opaque, hwaddr offset, reg_n = (offset - (req_quad_base_n << 4)) >> 2; if (req_quad_base_n >= IIC_NGRP) { - hw_error("exynos4210.combiner: unallowed write access at offset 0x" - TARGET_FMT_plx "\n", offset); + hw_error("exynos4210.combiner: unallowed write access at offset" + " 0x" TARGET_FMT_plx "\n", offset); return; } if (reg_n > 1) { - hw_error("exynos4210.combiner: unallowed write access at offset 0x" - TARGET_FMT_plx "\n", offset); + hw_error("exynos4210.combiner: unallowed write access at offset" + " 0x" TARGET_FMT_plx "\n", offset); return; } if (offset >> 2 >= IIC_REGSET_SIZE) { - hw_error("exynos4210.combiner: overflow of reg_set by 0x" - TARGET_FMT_plx "offset\n", offset); + hw_error("exynos4210.combiner: overflow of reg_set by" + " 0x" TARGET_FMT_plx "offset\n", offset); } s->reg_set[offset >> 2] = val; @@ -245,8 +245,8 @@ static void exynos4210_combiner_write(void *opaque, hwaddr offset, exynos4210_combiner_update(s, grp_quad_base_n + 3); break; default: - hw_error("exynos4210.combiner: unallowed write access at offset 0x" - TARGET_FMT_plx "\n", offset); + hw_error("exynos4210.combiner: unallowed write access at offset" + " 0x" TARGET_FMT_plx "\n", offset); break; } } diff --git a/hw/misc/auxbus.c b/hw/misc/auxbus.c index 8a8012f5f0..a2a0f88836 100644 --- a/hw/misc/auxbus.c +++ b/hw/misc/auxbus.c @@ -299,7 +299,8 @@ static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent) s = AUX_SLAVE(dev); - monitor_printf(mon, "%*smemory " TARGET_FMT_plx "/" TARGET_FMT_plx "\n", + monitor_printf(mon, + "%*smemory " TARGET_FMT_plx "/" TARGET_FMT_plx "\n", indent, "", object_property_get_uint(OBJECT(s->mmio), "addr", NULL), memory_region_size(s->mmio)); diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c index ddddf35c45..53412c23e4 100644 --- a/hw/net/allwinner_emac.c +++ b/hw/net/allwinner_emac.c @@ -303,8 +303,8 @@ static uint64_t aw_emac_read(void *opaque, hwaddr offset, unsigned size) extract32(s->phy_target, PHY_REG_SHIFT, 8)); default: qemu_log_mask(LOG_UNIMP, - "allwinner_emac: read access to unknown register 0x" - TARGET_FMT_plx "\n", offset); + "allwinner_emac: read access to unknown register" + " 0x" TARGET_FMT_plx "\n", offset); ret = 0; } @@ -406,8 +406,8 @@ static void aw_emac_write(void *opaque, hwaddr offset, uint64_t value, break; default: qemu_log_mask(LOG_UNIMP, - "allwinner_emac: write access to unknown register 0x" - TARGET_FMT_plx "\n", offset); + "allwinner_emac: write access to unknown register" + " 0x" TARGET_FMT_plx "\n", offset); } } diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c index d5186f4454..d324b5e698 100644 --- a/hw/timer/digic-timer.c +++ b/hw/timer/digic-timer.c @@ -75,8 +75,8 @@ static uint64_t digic_timer_read(void *opaque, hwaddr offset, unsigned size) break; default: qemu_log_mask(LOG_UNIMP, - "digic-timer: read access to unknown register 0x" - TARGET_FMT_plx "\n", offset); + "digic-timer: read access to unknown register" + " 0x" TARGET_FMT_plx "\n", offset); } return ret; @@ -115,8 +115,8 @@ static void digic_timer_write(void *opaque, hwaddr offset, default: qemu_log_mask(LOG_UNIMP, - "digic-timer: read access to unknown register 0x" - TARGET_FMT_plx "\n", offset); + "digic-timer: read access to unknown register" + " 0x" TARGET_FMT_plx "\n", offset); } } diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c index ecc2831baf..993df3557d 100644 --- a/hw/timer/etraxfs_timer.c +++ b/hw/timer/etraxfs_timer.c @@ -324,8 +324,7 @@ timer_write(void *opaque, hwaddr addr, t->rw_ack_intr = 0; break; default: - printf ("%s " TARGET_FMT_plx " %x\n", - __func__, addr, value); + printf("%s " TARGET_FMT_plx " %x\n", __func__, addr, value); break; } } diff --git a/softmmu/memory.c b/softmmu/memory.c index e05332d07f..e8c1f73312 100644 --- a/softmmu/memory.c +++ b/softmmu/memory.c @@ -1290,7 +1290,8 @@ static void unassigned_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { #ifdef DEBUG_UNASSIGNED - printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", addr, val); + printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", + addr, val); #endif } diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index cc091c3e62..ad353a86bc 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -361,10 +361,12 @@ static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu, pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 0, ptem, pte); if (pte_offset == -1) { /* Secondary PTEG lookup */ - qemu_log_mask(CPU_LOG_MMU, "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx - " vsid=%" PRIx32 " api=%" PRIx32 - " hash=" TARGET_FMT_plx "\n", ppc_hash32_hpt_base(cpu), - ppc_hash32_hpt_mask(cpu), vsid, ptem, ~hash); + qemu_log_mask(CPU_LOG_MMU, + "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx + " vsid=%" PRIx32 " api=%" PRIx32 + " hash=" TARGET_FMT_plx "\n", + ppc_hash32_hpt_base(cpu), + ppc_hash32_hpt_mask(cpu), vsid, ptem, ~hash); pteg_off = get_pteg_offset32(cpu, ~hash); pte_offset = ppc_hash32_pteg_search(cpu, pteg_off, 1, ptem, pte); } diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 8901f4d134..94cbb8b6a0 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -328,7 +328,8 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, ctx->prot = prot; ret = check_prot(ctx->prot, access_type); if (ret == 0) { - qemu_log_mask(CPU_LOG_MMU, "BAT %d match: r " TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, + "BAT %d match: r " TARGET_FMT_plx " prot=%c%c\n", i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', ctx->prot & PAGE_WRITE ? 'W' : '-'); @@ -420,8 +421,9 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, hwaddr curaddr; uint32_t a0, a1, a2, a3; - qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx - "\n", ppc_hash32_hpt_base(cpu), + qemu_log("Page table: " TARGET_FMT_plx + " len " TARGET_FMT_plx "\n", + ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu) + 0x80); for (curaddr = ppc_hash32_hpt_base(cpu); curaddr < (ppc_hash32_hpt_base(cpu) diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 919448a494..e3bdb6c3b8 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -368,8 +368,9 @@ void dump_mmu(CPUSPARCState *env) pde = mmu_probe(env, va1, 1); if (pde) { pa = cpu_get_phys_page_debug(cs, va1); - qemu_printf(" VA: " TARGET_FMT_lx ", PA: " - TARGET_FMT_plx " PDE: " TARGET_FMT_lx "\n", + qemu_printf(" VA: " TARGET_FMT_lx + ", PA: " TARGET_FMT_plx + " PDE: " TARGET_FMT_lx "\n", va1, pa, pde); for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { pde = mmu_probe(env, va2, 0); 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Wed, 11 Jan 2023 00:39:16 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id f28-20020a05600c491c00b003d9bd56e9c1sm16525824wmp.11.2023.01.11.00.39.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 11 Jan 2023 00:39:15 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v2 1/4] hw: Remove hardcoded tabs (code style) Date: Wed, 11 Jan 2023 09:39:06 +0100 Message-Id: <20230111083909.42624-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230111083909.42624-1-philmd@linaro.org> References: <20230111083909.42624-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 08:39:25 -0000 We are going to modify this code, fix its style first to avoid the following checkpatch.pl violations: ERROR: code indent should never use tabs ERROR: space prohibited between function name and open parenthesis '(' Signed-off-by: Philippe Mathieu-Daudé --- hw/dma/etraxfs_dma.c | 196 +++++++++++++++++++++---------------------- hw/misc/mst_fpga.c | 162 ++++++++++++++++++----------------- 2 files changed, 175 insertions(+), 183 deletions(-) diff --git a/hw/dma/etraxfs_dma.c b/hw/dma/etraxfs_dma.c index c4334e87bf..88d303ba4a 100644 --- a/hw/dma/etraxfs_dma.c +++ b/hw/dma/etraxfs_dma.c @@ -269,34 +269,34 @@ static void channel_load_c(struct fs_dma_ctrl *ctrl, int c) static void channel_load_d(struct fs_dma_ctrl *ctrl, int c) { - hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA); + hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA); - /* Load and decode. FIXME: handle endianness. */ - D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); + /* Load and decode. FIXME: handle endianness. */ + D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); cpu_physical_memory_read(addr, &ctrl->channels[c].current_d, sizeof(ctrl->channels[c].current_d)); - D(dump_d(c, &ctrl->channels[c].current_d)); - ctrl->channels[c].regs[RW_DATA] = addr; + D(dump_d(c, &ctrl->channels[c].current_d)); + ctrl->channels[c].regs[RW_DATA] = addr; } static void channel_store_c(struct fs_dma_ctrl *ctrl, int c) { - hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN); + hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN); - /* Encode and store. FIXME: handle endianness. */ - D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); - D(dump_d(c, &ctrl->channels[c].current_d)); + /* Encode and store. FIXME: handle endianness. */ + D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); + D(dump_d(c, &ctrl->channels[c].current_d)); cpu_physical_memory_write(addr, &ctrl->channels[c].current_c, sizeof(ctrl->channels[c].current_c)); } static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) { - hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA); + hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA); - /* Encode and store. FIXME: handle endianness. */ - D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); + /* Encode and store. FIXME: handle endianness. */ + D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); cpu_physical_memory_write(addr, &ctrl->channels[c].current_d, sizeof(ctrl->channels[c].current_d)); } @@ -574,46 +574,43 @@ static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c) static uint32_t dma_rinvalid (void *opaque, hwaddr addr) { - hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr); - return 0; + hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr); + return 0; } -static uint64_t -dma_read(void *opaque, hwaddr addr, unsigned int size) +static uint64_t dma_read(void *opaque, hwaddr addr, unsigned int size) { - struct fs_dma_ctrl *ctrl = opaque; - int c; - uint32_t r = 0; + struct fs_dma_ctrl *ctrl = opaque; + int c; + uint32_t r = 0; - if (size != 4) { - dma_rinvalid(opaque, addr); - } + if (size != 4) { + dma_rinvalid(opaque, addr); + } - /* Make addr relative to this channel and bounded to nr regs. */ - c = fs_channel(addr); - addr &= 0xff; - addr >>= 2; - switch (addr) - { - case RW_STAT: - r = ctrl->channels[c].state & 7; - r |= ctrl->channels[c].eol << 5; - r |= ctrl->channels[c].stream_cmd_src << 8; - break; + /* Make addr relative to this channel and bounded to nr regs. */ + c = fs_channel(addr); + addr &= 0xff; + addr >>= 2; + switch (addr) { + case RW_STAT: + r = ctrl->channels[c].state & 7; + r |= ctrl->channels[c].eol << 5; + r |= ctrl->channels[c].stream_cmd_src << 8; + break; - default: - r = ctrl->channels[c].regs[addr]; - D(printf ("%s c=%d addr=" TARGET_FMT_plx "\n", - __func__, c, addr)); - break; - } - return r; + default: + r = ctrl->channels[c].regs[addr]; + D(printf("%s c=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); + break; + } + return r; } static void dma_winvalid (void *opaque, hwaddr addr, uint32_t value) { - hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr); + hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr); } static void @@ -625,71 +622,68 @@ dma_update_state(struct fs_dma_ctrl *ctrl, int c) ctrl->channels[c].state = RST; } -static void -dma_write(void *opaque, hwaddr addr, - uint64_t val64, unsigned int size) +static void dma_write(void *opaque, hwaddr addr, uint64_t val64, + unsigned int size) { - struct fs_dma_ctrl *ctrl = opaque; - uint32_t value = val64; - int c; + struct fs_dma_ctrl *ctrl = opaque; + uint32_t value = val64; + int c; - if (size != 4) { - dma_winvalid(opaque, addr, value); - } + if (size != 4) { + dma_winvalid(opaque, addr, value); + } - /* Make addr relative to this channel and bounded to nr regs. */ - c = fs_channel(addr); - addr &= 0xff; - addr >>= 2; - switch (addr) - { - case RW_DATA: - ctrl->channels[c].regs[addr] = value; - break; + /* Make addr relative to this channel and bounded to nr regs. */ + c = fs_channel(addr); + addr &= 0xff; + addr >>= 2; + switch (addr) { + case RW_DATA: + ctrl->channels[c].regs[addr] = value; + break; - case RW_CFG: - ctrl->channels[c].regs[addr] = value; - dma_update_state(ctrl, c); - break; - case RW_CMD: - /* continue. */ - if (value & ~1) - printf("Invalid store to ch=%d RW_CMD %x\n", - c, value); - ctrl->channels[c].regs[addr] = value; - channel_continue(ctrl, c); - break; - - case RW_SAVED_DATA: - case RW_SAVED_DATA_BUF: - case RW_GROUP: - case RW_GROUP_DOWN: - ctrl->channels[c].regs[addr] = value; - break; - - case RW_ACK_INTR: - case RW_INTR_MASK: - ctrl->channels[c].regs[addr] = value; - channel_update_irq(ctrl, c); - if (addr == RW_ACK_INTR) - ctrl->channels[c].regs[RW_ACK_INTR] = 0; - break; - - case RW_STREAM_CMD: - if (value & ~1023) - printf("Invalid store to ch=%d " - "RW_STREAMCMD %x\n", - c, value); - ctrl->channels[c].regs[addr] = value; - D(printf("stream_cmd ch=%d\n", c)); - channel_stream_cmd(ctrl, c, value); - break; - - default: - D(printf ("%s c=%d " TARGET_FMT_plx "\n", - __func__, c, addr)); - break; + case RW_CFG: + ctrl->channels[c].regs[addr] = value; + dma_update_state(ctrl, c); + break; + case RW_CMD: + /* continue. */ + if (value & ~1) { + printf("Invalid store to ch=%d RW_CMD %x\n", c, value); } + ctrl->channels[c].regs[addr] = value; + channel_continue(ctrl, c); + break; + + case RW_SAVED_DATA: + case RW_SAVED_DATA_BUF: + case RW_GROUP: + case RW_GROUP_DOWN: + ctrl->channels[c].regs[addr] = value; + break; + + case RW_ACK_INTR: + case RW_INTR_MASK: + ctrl->channels[c].regs[addr] = value; + channel_update_irq(ctrl, c); + if (addr == RW_ACK_INTR) { + ctrl->channels[c].regs[RW_ACK_INTR] = 0; + } + break; + + case RW_STREAM_CMD: + if (value & ~1023) { + printf("Invalid store to ch=%d RW_STREAMCMD %x\n", c, value); + } + ctrl->channels[c].regs[addr] = value; + D(printf("stream_cmd ch=%d\n", c)); + channel_stream_cmd(ctrl, c, value); + break; + + default: + D(printf("%s c=%d " TARGET_FMT_plx "\n", __func__, c, addr)); + break; + } } static const MemoryRegionOps dma_ops = { diff --git a/hw/misc/mst_fpga.c b/hw/misc/mst_fpga.c index 2aaadfa966..87c09217a6 100644 --- a/hw/misc/mst_fpga.c +++ b/hw/misc/mst_fpga.c @@ -99,94 +99,92 @@ mst_fpga_set_irq(void *opaque, int irq, int level) } -static uint64_t -mst_fpga_readb(void *opaque, hwaddr addr, unsigned size) +static uint64_t mst_fpga_readb(void *opaque, hwaddr addr, unsigned size) { - mst_irq_state *s = (mst_irq_state *) opaque; + mst_irq_state *s = (mst_irq_state *) opaque; - switch (addr) { - case MST_LEDDAT1: - return s->leddat1; - case MST_LEDDAT2: - return s->leddat2; - case MST_LEDCTRL: - return s->ledctrl; - case MST_GPSWR: - return s->gpswr; - case MST_MSCWR1: - return s->mscwr1; - case MST_MSCWR2: - return s->mscwr2; - case MST_MSCWR3: - return s->mscwr3; - case MST_MSCRD: - return s->mscrd; - case MST_INTMSKENA: - return s->intmskena; - case MST_INTSETCLR: - return s->intsetclr; - case MST_PCMCIA0: - return s->pcmcia0; - case MST_PCMCIA1: - return s->pcmcia1; - default: - printf("Mainstone - mst_fpga_readb: Bad register offset " - "0x" TARGET_FMT_plx "\n", addr); - } - return 0; + switch (addr) { + case MST_LEDDAT1: + return s->leddat1; + case MST_LEDDAT2: + return s->leddat2; + case MST_LEDCTRL: + return s->ledctrl; + case MST_GPSWR: + return s->gpswr; + case MST_MSCWR1: + return s->mscwr1; + case MST_MSCWR2: + return s->mscwr2; + case MST_MSCWR3: + return s->mscwr3; + case MST_MSCRD: + return s->mscrd; + case MST_INTMSKENA: + return s->intmskena; + case MST_INTSETCLR: + return s->intsetclr; + case MST_PCMCIA0: + return s->pcmcia0; + case MST_PCMCIA1: + return s->pcmcia1; + default: + printf("Mainstone - mst_fpga_readb: Bad register offset " + "0x" TARGET_FMT_plx "\n", addr); + } + return 0; } -static void -mst_fpga_writeb(void *opaque, hwaddr addr, uint64_t value, - unsigned size) +static void mst_fpga_writeb(void *opaque, hwaddr addr, uint64_t value, + unsigned size) { - mst_irq_state *s = (mst_irq_state *) opaque; - value &= 0xffffffff; + mst_irq_state *s = (mst_irq_state *) opaque; + value &= 0xffffffff; - switch (addr) { - case MST_LEDDAT1: - s->leddat1 = value; - break; - case MST_LEDDAT2: - s->leddat2 = value; - break; - case MST_LEDCTRL: - s->ledctrl = value; - break; - case MST_GPSWR: - s->gpswr = value; - break; - case MST_MSCWR1: - s->mscwr1 = value; - break; - case MST_MSCWR2: - s->mscwr2 = value; - break; - case MST_MSCWR3: - s->mscwr3 = value; - break; - case MST_MSCRD: - s->mscrd = value; - break; - case MST_INTMSKENA: /* Mask interrupt */ - s->intmskena = (value & 0xFEEFF); - qemu_set_irq(s->parent, s->intsetclr & s->intmskena); - break; - case MST_INTSETCLR: /* clear or set interrupt */ - s->intsetclr = (value & 0xFEEFF); - qemu_set_irq(s->parent, s->intsetclr & s->intmskena); - break; - /* For PCMCIAx allow the to change only power and reset */ - case MST_PCMCIA0: - s->pcmcia0 = (value & 0x1f) | (s->pcmcia0 & ~0x1f); - break; - case MST_PCMCIA1: - s->pcmcia1 = (value & 0x1f) | (s->pcmcia1 & ~0x1f); - break; - default: - printf("Mainstone - mst_fpga_writeb: Bad register offset " - "0x" TARGET_FMT_plx "\n", addr); - } + switch (addr) { + case MST_LEDDAT1: + s->leddat1 = value; + break; + case MST_LEDDAT2: + s->leddat2 = value; + break; + case MST_LEDCTRL: + s->ledctrl = value; + break; + case MST_GPSWR: + s->gpswr = value; + break; + case MST_MSCWR1: + s->mscwr1 = value; + break; + case MST_MSCWR2: + s->mscwr2 = value; + break; + case MST_MSCWR3: + s->mscwr3 = value; + break; + case MST_MSCRD: + s->mscrd = value; + break; + case MST_INTMSKENA: /* Mask interrupt */ + s->intmskena = (value & 0xFEEFF); + qemu_set_irq(s->parent, s->intsetclr & s->intmskena); + break; + case MST_INTSETCLR: /* clear or set interrupt */ + s->intsetclr = (value & 0xFEEFF); + qemu_set_irq(s->parent, s->intsetclr & s->intmskena); + break; + /* For PCMCIAx allow the to change only power and reset */ + case MST_PCMCIA0: + s->pcmcia0 = (value & 0x1f) | (s->pcmcia0 & ~0x1f); + break; + case MST_PCMCIA1: + s->pcmcia1 = (value & 0x1f) | (s->pcmcia1 & ~0x1f); + break; + default: + printf("Mainstone - mst_fpga_writeb: Bad register offset " + "0x" TARGET_FMT_plx "\n", addr); + } } static const MemoryRegionOps mst_fpga_ops = { -- 2.38.1 From MAILER-DAEMON Wed Jan 11 03:39:34 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFWdy-0004lm-1E for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 03:39:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFWdv-0004lD-Ig for qemu-riscv@nongnu.org; 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Wed, 11 Jan 2023 00:39:25 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , BALATON Zoltan Subject: [PATCH v2 3/4] bulk: Replace TARGET_FMT_plx -> HWADDR_PRIx Date: Wed, 11 Jan 2023 09:39:08 +0100 Message-Id: <20230111083909.42624-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230111083909.42624-1-philmd@linaro.org> References: <20230111083909.42624-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 08:39:32 -0000 The 'hwaddr' type is defined in "exec/hwaddr.h" as: hwaddr is the type of a physical address (its size can be different from 'target_ulong'). All definitions use the 'HWADDR_' prefix, except TARGET_FMT_plx: $ fgrep define include/exec/hwaddr.h #define HWADDR_H #define HWADDR_BITS 64 #define HWADDR_MAX UINT64_MAX #define TARGET_FMT_plx "%016" PRIx64 ^^^^^^ #define HWADDR_PRId PRId64 #define HWADDR_PRIi PRIi64 #define HWADDR_PRIo PRIo64 #define HWADDR_PRIu PRIu64 #define HWADDR_PRIx PRIx64 #define HWADDR_PRIX PRIX64 Since hwaddr's size can be *different* from target_ulong, it is very confusing to read one of its format using the 'TARGET_FMT_' prefix, normally used for the target_long / target_ulong types: $ fgrep TARGET_FMT_ include/exec/cpu-defs.h #define TARGET_FMT_lx "%08x" #define TARGET_FMT_ld "%d" #define TARGET_FMT_lu "%u" #define TARGET_FMT_lx "%016" PRIx64 #define TARGET_FMT_ld "%" PRId64 #define TARGET_FMT_lu "%" PRIu64 Apparently this format was missed during commit a8170e5e97 ("Rename target_phys_addr_t to hwaddr"), so complete it by doing a bulk-replacement to '"%016" HWADDR_PRIx' using: $ sed -i -E \ -e 's/" ?TARGET_FMT_plx ?"/%016" HWADDR_PRIx "/g' \ -e 's/" ?TARGET_FMT_plx/%016" HWADDR_PRIx/g' \ -e 's/TARGET_FMT_plx ?"/"%016" HWADDR_PRIx "/g' \ $(git grep -l TARGET_FMT_plx) and removing the definition from "exec/hwaddr.h". Suggested-by: BALATON Zoltan Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/cputlb.c | 2 +- hw/arm/strongarm.c | 24 ++++++++++++------------ hw/block/pflash_cfi01.c | 2 +- hw/char/digic-uart.c | 4 ++-- hw/char/etraxfs_ser.c | 4 ++-- hw/core/loader.c | 8 ++++---- hw/core/sysbus.c | 4 ++-- hw/display/cirrus_vga.c | 4 ++-- hw/display/g364fb.c | 4 ++-- hw/display/vga.c | 8 ++++---- hw/dma/etraxfs_dma.c | 14 +++++++------- hw/dma/pl330.c | 14 +++++++------- hw/dma/xilinx_axidma.c | 4 ++-- hw/dma/xlnx_csu_dma.c | 4 ++-- hw/i2c/mpc_i2c.c | 4 ++-- hw/i386/multiboot.c | 8 ++++---- hw/i386/xen/xen-hvm.c | 8 ++++---- hw/i386/xen/xen-mapcache.c | 16 ++++++++-------- hw/i386/xen/xen_platform.c | 4 ++-- hw/intc/arm_gicv3_dist.c | 8 ++++---- hw/intc/arm_gicv3_its.c | 14 +++++++------- hw/intc/arm_gicv3_redist.c | 8 ++++---- hw/intc/exynos4210_combiner.c | 10 +++++----- hw/misc/auxbus.c | 2 +- hw/misc/ivshmem.c | 6 +++--- hw/misc/macio/mac_dbdma.c | 4 ++-- hw/misc/mst_fpga.c | 4 ++-- hw/net/allwinner-sun8i-emac.c | 4 ++-- hw/net/allwinner_emac.c | 4 ++-- hw/net/fsl_etsec/etsec.c | 4 ++-- hw/net/fsl_etsec/rings.c | 4 ++-- hw/net/pcnet.c | 4 ++-- hw/net/rocker/rocker.c | 26 +++++++++++++------------- hw/net/rocker/rocker_desc.c | 2 +- hw/net/xilinx_axienet.c | 4 ++-- hw/net/xilinx_ethlite.c | 6 +++--- hw/pci-bridge/pci_expander_bridge.c | 2 +- hw/pci-host/bonito.c | 14 +++++++------- hw/pci-host/ppce500.c | 4 ++-- hw/pci/pci_host.c | 4 ++-- hw/ppc/ppc4xx_sdram.c | 2 +- hw/rtc/exynos4210_rtc.c | 4 ++-- hw/sh4/sh7750.c | 4 ++-- hw/ssi/xilinx_spi.c | 4 ++-- hw/ssi/xilinx_spips.c | 8 ++++---- hw/timer/digic-timer.c | 4 ++-- hw/timer/etraxfs_timer.c | 2 +- hw/timer/exynos4210_mct.c | 2 +- hw/timer/exynos4210_pwm.c | 4 ++-- hw/virtio/virtio-mmio.c | 4 ++-- hw/xen/xen_pt.c | 4 ++-- include/exec/hwaddr.h | 1 - monitor/misc.c | 2 +- softmmu/memory.c | 18 +++++++++--------- softmmu/memory_mapping.c | 4 ++-- softmmu/physmem.c | 10 +++++----- target/i386/monitor.c | 6 +++--- target/loongarch/tlb_helper.c | 2 +- target/microblaze/op_helper.c | 2 +- target/mips/tcg/sysemu/tlb_helper.c | 2 +- target/ppc/mmu-hash32.c | 14 +++++++------- target/ppc/mmu-hash64.c | 12 ++++++------ target/ppc/mmu_common.c | 28 ++++++++++++++-------------- target/ppc/mmu_helper.c | 4 ++-- target/riscv/cpu_helper.c | 10 +++++----- target/riscv/monitor.c | 2 +- target/sparc/ldst_helper.c | 6 +++--- target/sparc/mmu_helper.c | 10 +++++----- target/tricore/helper.c | 2 +- 69 files changed, 227 insertions(+), 228 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 4948729917..d85d926490 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1142,7 +1142,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, &xlat, &sz, full->attrs, &prot); assert(sz >= TARGET_PAGE_SIZE); - tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx + tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x%016" HWADDR_PRIx " prot=%x idx=%d\n", vaddr, full->phys_addr, prot, mmu_idx); diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index 39b8f01ac4..1dbc7651d7 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -151,7 +151,7 @@ static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset, case ICPR: return s->pending; default: - printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n", + printf("%s: Bad register offset 0x%016" HWADDR_PRIx "\n", __func__, offset); return 0; } @@ -173,7 +173,7 @@ static void strongarm_pic_mem_write(void *opaque, hwaddr offset, s->int_idle = (value & 1) ? 0 : ~0; break; default: - printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n", + printf("%s: Bad register offset 0x%016" HWADDR_PRIx "\n", __func__, offset); break; } @@ -333,7 +333,7 @@ static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr, ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) / (1000 * ((s->rttr & 0xffff) + 1)); default: - printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); + printf("%s: Bad register 0x%016" HWADDR_PRIx "\n", __func__, addr); return 0; } } @@ -375,7 +375,7 @@ static void strongarm_rtc_write(void *opaque, hwaddr addr, break; default: - printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); + printf("%s: Bad register 0x%016" HWADDR_PRIx "\n", __func__, addr); } } @@ -581,7 +581,7 @@ static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset, return s->status; default: - printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); + printf("%s: Bad offset 0x%016" HWADDR_PRIx "\n", __func__, offset); } return 0; @@ -626,7 +626,7 @@ static void strongarm_gpio_write(void *opaque, hwaddr offset, break; default: - printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); + printf("%s: Bad offset 0x%016" HWADDR_PRIx "\n", __func__, offset); } } @@ -782,7 +782,7 @@ static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset, return s->ppfr | ~0x7f001; default: - printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); + printf("%s: Bad offset 0x%016" HWADDR_PRIx "\n", __func__, offset); } return 0; @@ -817,7 +817,7 @@ static void strongarm_ppc_write(void *opaque, hwaddr offset, break; default: - printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); + printf("%s: Bad offset 0x%016" HWADDR_PRIx "\n", __func__, offset); } } @@ -1164,7 +1164,7 @@ static uint64_t strongarm_uart_read(void *opaque, hwaddr addr, return s->utsr1; default: - printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); + printf("%s: Bad register 0x%016" HWADDR_PRIx "\n", __func__, addr); return 0; } } @@ -1221,7 +1221,7 @@ static void strongarm_uart_write(void *opaque, hwaddr addr, break; default: - printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); + printf("%s: Bad register 0x%016" HWADDR_PRIx "\n", __func__, addr); } } @@ -1443,7 +1443,7 @@ static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr, strongarm_ssp_fifo_update(s); return retval; default: - printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); + printf("%s: Bad register 0x%016" HWADDR_PRIx "\n", __func__, addr); break; } return 0; @@ -1509,7 +1509,7 @@ static void strongarm_ssp_write(void *opaque, hwaddr addr, break; default: - printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr); + printf("%s: Bad register 0x%016" HWADDR_PRIx "\n", __func__, addr); break; } } diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 951419b2ed..20624e3176 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -645,7 +645,7 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset, error_flash: qemu_log_mask(LOG_UNIMP, "%s: Unimplemented flash cmd sequence " - "(offset " TARGET_FMT_plx + "(offset %016" HWADDR_PRIx ", wcycle 0x%x cmd 0x%x value 0x%x)\n", __func__, offset, pfl->wcycle, pfl->cmd, value); diff --git a/hw/char/digic-uart.c b/hw/char/digic-uart.c index 3bbc43193b..4e45e9e7cc 100644 --- a/hw/char/digic-uart.c +++ b/hw/char/digic-uart.c @@ -63,7 +63,7 @@ static uint64_t digic_uart_read(void *opaque, hwaddr addr, default: qemu_log_mask(LOG_UNIMP, "digic-uart: read access to unknown register" - " 0x" TARGET_FMT_plx "\n", addr << 2); + " 0x%016" HWADDR_PRIx "\n", addr << 2); } return ret; @@ -101,7 +101,7 @@ static void digic_uart_write(void *opaque, hwaddr addr, uint64_t value, default: qemu_log_mask(LOG_UNIMP, "digic-uart: write access to unknown register" - " 0x" TARGET_FMT_plx "\n", addr << 2); + " 0x%016" HWADDR_PRIx "\n", addr << 2); } } diff --git a/hw/char/etraxfs_ser.c b/hw/char/etraxfs_ser.c index e8c3017724..d79a5b1bf1 100644 --- a/hw/char/etraxfs_ser.c +++ b/hw/char/etraxfs_ser.c @@ -113,7 +113,7 @@ ser_read(void *opaque, hwaddr addr, unsigned int size) break; default: r = s->regs[addr]; - D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, r)); + D(qemu_log("%s %016" HWADDR_PRIx "=%x\n", __func__, addr, r)); break; } return r; @@ -127,7 +127,7 @@ ser_write(void *opaque, hwaddr addr, uint32_t value = val64; unsigned char ch = val64; - D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr, value)); + D(qemu_log("%s %016" HWADDR_PRIx "=%x\n", __func__, addr, value)); addr >>= 2; switch (addr) { diff --git a/hw/core/loader.c b/hw/core/loader.c index 0548830733..e9cc5a60e8 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -1054,7 +1054,7 @@ ssize_t rom_add_file(const char *file, const char *fw_dir, rom->mr = mr; snprintf(devpath, sizeof(devpath), "/rom@%s", file); } else { - snprintf(devpath, sizeof(devpath), "/rom@" TARGET_FMT_plx, addr); + snprintf(devpath, sizeof(devpath), "/rom@%016" HWADDR_PRIx, addr); } } @@ -1238,10 +1238,10 @@ static void rom_print_one_overlap_error(Rom *last_rom, Rom *rom) "\nThe following two regions overlap (in the %s address space):\n", rom_as_name(rom)); error_printf( - " %s (addresses 0x" TARGET_FMT_plx " - 0x" TARGET_FMT_plx ")\n", + " %s (addresses 0x%016" HWADDR_PRIx " - 0x%016" HWADDR_PRIx ")\n", last_rom->name, last_rom->addr, last_rom->addr + last_rom->romsize); error_printf( - " %s (addresses 0x" TARGET_FMT_plx " - 0x" TARGET_FMT_plx ")\n", + " %s (addresses 0x%016" HWADDR_PRIx " - 0x%016" HWADDR_PRIx ")\n", rom->name, rom->addr, rom->addr + rom->romsize); } @@ -1595,7 +1595,7 @@ HumanReadableText *qmp_x_query_roms(Error **errp) rom->romsize, rom->name); } else if (!rom->fw_file) { - g_string_append_printf(buf, "addr=" TARGET_FMT_plx + g_string_append_printf(buf, "addr=%016" HWADDR_PRIx " size=0x%06zx mem=%s name=\"%s\"\n", rom->addr, rom->romsize, rom->isrom ? "rom" : "ram", diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c index e8b31683e7..5c0099c5eb 100644 --- a/hw/core/sysbus.c +++ b/hw/core/sysbus.c @@ -270,7 +270,7 @@ static void sysbus_dev_print(Monitor *mon, DeviceState *dev, int indent) for (i = 0; i < s->num_mmio; i++) { size = memory_region_size(s->mmio[i].memory); monitor_printf(mon, - "%*smmio " TARGET_FMT_plx "/" TARGET_FMT_plx "\n", + "%*smmio %016" HWADDR_PRIx "/%016" HWADDR_PRIx "\n", indent, "", s->mmio[i].addr, size); } } @@ -290,7 +290,7 @@ static char *sysbus_get_fw_dev_path(DeviceState *dev) } } if (s->num_mmio) { - return g_strdup_printf("%s@" TARGET_FMT_plx, qdev_fw_name(dev), + return g_strdup_printf("%s@%016" HWADDR_PRIx, qdev_fw_name(dev), s->mmio[0].addr); } if (s->num_pio) { diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c index 55c32e3e40..adc4bd7f9a 100644 --- a/hw/display/cirrus_vga.c +++ b/hw/display/cirrus_vga.c @@ -2041,7 +2041,7 @@ static uint64_t cirrus_vga_mem_read(void *opaque, } else { val = 0xff; qemu_log_mask(LOG_GUEST_ERROR, - "cirrus: mem_readb 0x" TARGET_FMT_plx "\n", addr); + "cirrus: mem_readb 0x%016" HWADDR_PRIx "\n", addr); } return val; } @@ -2105,7 +2105,7 @@ static void cirrus_vga_mem_write(void *opaque, } } else { qemu_log_mask(LOG_GUEST_ERROR, - "cirrus: mem_writeb 0x" TARGET_FMT_plx " " + "cirrus: mem_writeb 0x%016" HWADDR_PRIx " " "value 0x%02" PRIx64 "\n", addr, mem_value); } } diff --git a/hw/display/g364fb.c b/hw/display/g364fb.c index caca86d773..7a3065d696 100644 --- a/hw/display/g364fb.c +++ b/hw/display/g364fb.c @@ -320,7 +320,7 @@ static uint64_t g364fb_ctrl_read(void *opaque, break; default: { - error_report("g364: invalid read at [" TARGET_FMT_plx "]", + error_report("g364: invalid read at [%016" HWADDR_PRIx "]", addr); val = 0; break; @@ -424,7 +424,7 @@ static void g364fb_ctrl_write(void *opaque, break; default: error_report("g364: invalid write of 0x%" PRIx64 - " at [" TARGET_FMT_plx "]", val, addr); + " at [%016" HWADDR_PRIx "]", val, addr); break; } } diff --git a/hw/display/vga.c b/hw/display/vga.c index 0cb26a791b..cf9bfb2293 100644 --- a/hw/display/vga.c +++ b/hw/display/vga.c @@ -875,7 +875,7 @@ void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val) uint32_t write_mask, bit_mask, set_mask; #ifdef DEBUG_VGA_MEM - printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val); + printf("vga: [0x%016" HWADDR_PRIx "] = 0x%02x\n", addr, val); #endif /* convert to VGA memory offset */ memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3; @@ -909,7 +909,7 @@ void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val) assert(addr < s->vram_size); s->vram_ptr[addr] = val; #ifdef DEBUG_VGA_MEM - printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr); + printf("vga: chain4: [0x%016" HWADDR_PRIx "]\n", addr); #endif s->plane_updated |= mask; /* only used to detect font change */ memory_region_set_dirty(&s->vram, addr, 1); @@ -925,7 +925,7 @@ void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val) } s->vram_ptr[addr] = val; #ifdef DEBUG_VGA_MEM - printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr); + printf("vga: odd/even: [0x%016" HWADDR_PRIx "]\n", addr); #endif s->plane_updated |= mask; /* only used to detect font change */ memory_region_set_dirty(&s->vram, addr, 1); @@ -1003,7 +1003,7 @@ void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val) (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) | (val & write_mask); #ifdef DEBUG_VGA_MEM - printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n", + printf("vga: latch: [0x%016" HWADDR_PRIx "] mask=0x%08x val=0x%08x\n", addr * 4, write_mask, val); #endif memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t)); diff --git a/hw/dma/etraxfs_dma.c b/hw/dma/etraxfs_dma.c index 88d303ba4a..f69da09143 100644 --- a/hw/dma/etraxfs_dma.c +++ b/hw/dma/etraxfs_dma.c @@ -272,7 +272,7 @@ static void channel_load_d(struct fs_dma_ctrl *ctrl, int c) hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA); /* Load and decode. FIXME: handle endianness. */ - D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); + D(printf("%s ch=%d addr=%016" HWADDR_PRIx "\n", __func__, c, addr)); cpu_physical_memory_read(addr, &ctrl->channels[c].current_d, sizeof(ctrl->channels[c].current_d)); @@ -285,7 +285,7 @@ static void channel_store_c(struct fs_dma_ctrl *ctrl, int c) hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN); /* Encode and store. FIXME: handle endianness. */ - D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); + D(printf("%s ch=%d addr=%016" HWADDR_PRIx "\n", __func__, c, addr)); D(dump_d(c, &ctrl->channels[c].current_d)); cpu_physical_memory_write(addr, &ctrl->channels[c].current_c, sizeof(ctrl->channels[c].current_c)); @@ -296,7 +296,7 @@ static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA); /* Encode and store. FIXME: handle endianness. */ - D(printf("%s ch=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); + D(printf("%s ch=%d addr=%016" HWADDR_PRIx "\n", __func__, c, addr)); cpu_physical_memory_write(addr, &ctrl->channels[c].current_d, sizeof(ctrl->channels[c].current_d)); } @@ -574,7 +574,7 @@ static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c) static uint32_t dma_rinvalid (void *opaque, hwaddr addr) { - hw_error("Unsupported short raccess. reg=" TARGET_FMT_plx "\n", addr); + hw_error("Unsupported short raccess. reg=%016" HWADDR_PRIx "\n", addr); return 0; } @@ -601,7 +601,7 @@ static uint64_t dma_read(void *opaque, hwaddr addr, unsigned int size) default: r = ctrl->channels[c].regs[addr]; - D(printf("%s c=%d addr=" TARGET_FMT_plx "\n", __func__, c, addr)); + D(printf("%s c=%d addr=%016" HWADDR_PRIx "\n", __func__, c, addr)); break; } return r; @@ -610,7 +610,7 @@ static uint64_t dma_read(void *opaque, hwaddr addr, unsigned int size) static void dma_winvalid (void *opaque, hwaddr addr, uint32_t value) { - hw_error("Unsupported short waccess. reg=" TARGET_FMT_plx "\n", addr); + hw_error("Unsupported short waccess. reg=%016" HWADDR_PRIx "\n", addr); } static void @@ -681,7 +681,7 @@ static void dma_write(void *opaque, hwaddr addr, uint64_t val64, break; default: - D(printf("%s c=%d " TARGET_FMT_plx "\n", __func__, c, addr)); + D(printf("%s c=%d %016" HWADDR_PRIx "\n", __func__, c, addr)); break; } } diff --git a/hw/dma/pl330.c b/hw/dma/pl330.c index 60ce65c2a7..ba72343c20 100644 --- a/hw/dma/pl330.c +++ b/hw/dma/pl330.c @@ -1374,7 +1374,7 @@ static void pl330_iomem_write(void *opaque, hwaddr offset, } else { qemu_log_mask(LOG_GUEST_ERROR, "pl330: write of illegal value %u" - " for offset " TARGET_FMT_plx "\n", + " for offset %016" HWADDR_PRIx "\n", (unsigned)value, offset); } break; @@ -1386,7 +1386,7 @@ static void pl330_iomem_write(void *opaque, hwaddr offset, break; default: qemu_log_mask(LOG_GUEST_ERROR, - "pl330: bad write offset " TARGET_FMT_plx "\n", + "pl330: bad write offset %016" HWADDR_PRIx "\n", offset); break; } @@ -1411,7 +1411,7 @@ static inline uint32_t pl330_iomem_read_imp(void *opaque, chan_id = offset >> 5; if (chan_id >= s->num_chnls) { qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " - TARGET_FMT_plx "\n", offset); + "%016" HWADDR_PRIx "\n", offset); return 0; } switch (offset & 0x1f) { @@ -1427,7 +1427,7 @@ static inline uint32_t pl330_iomem_read_imp(void *opaque, return s->chan[chan_id].lc[1]; default: qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " - TARGET_FMT_plx "\n", offset); + "%016" HWADDR_PRIx "\n", offset); return 0; } } @@ -1436,7 +1436,7 @@ static inline uint32_t pl330_iomem_read_imp(void *opaque, chan_id = offset >> 3; if (chan_id >= s->num_chnls) { qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " - TARGET_FMT_plx "\n", offset); + "%016" HWADDR_PRIx "\n", offset); return 0; } switch ((offset >> 2) & 1) { @@ -1458,7 +1458,7 @@ static inline uint32_t pl330_iomem_read_imp(void *opaque, chan_id = offset >> 2; if (chan_id >= s->num_chnls) { qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " - TARGET_FMT_plx "\n", offset); + "%016" HWADDR_PRIx "\n", offset); return 0; } return s->chan[chan_id].fault_type; @@ -1497,7 +1497,7 @@ static inline uint32_t pl330_iomem_read_imp(void *opaque, return s->debug_status; default: qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " - TARGET_FMT_plx "\n", offset); + "%016" HWADDR_PRIx "\n", offset); } return 0; } diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index cbb8f0f169..74ff5ba842 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -456,7 +456,7 @@ static uint64_t axidma_read(void *opaque, hwaddr addr, break; default: r = s->regs[addr]; - D(qemu_log("%s ch=%d addr=" TARGET_FMT_plx " v=%x\n", + D(qemu_log("%s ch=%d addr=%016" HWADDR_PRIx " v=%x\n", __func__, sid, addr * 4, r)); break; } @@ -509,7 +509,7 @@ static void axidma_write(void *opaque, hwaddr addr, } break; default: - D(qemu_log("%s: ch=%d addr=" TARGET_FMT_plx " v=%x\n", + D(qemu_log("%s: ch=%d addr=%016" HWADDR_PRIx " v=%x\n", __func__, sid, addr * 4, (unsigned)value)); s->regs[addr] = value; break; diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c index 1ce52ea5a2..e2ef8139fc 100644 --- a/hw/dma/xlnx_csu_dma.c +++ b/hw/dma/xlnx_csu_dma.c @@ -211,7 +211,7 @@ static uint32_t xlnx_csu_dma_read(XlnxCSUDMA *s, uint8_t *buf, uint32_t len) if (result == MEMTX_OK) { xlnx_csu_dma_data_process(s, buf, len); } else { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address " TARGET_FMT_plx + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address %016" HWADDR_PRIx " for mem read", __func__, addr); s->regs[R_INT_STATUS] |= R_INT_STATUS_AXI_BRESP_ERR_MASK; xlnx_csu_dma_update_irq(s); @@ -241,7 +241,7 @@ static uint32_t xlnx_csu_dma_write(XlnxCSUDMA *s, uint8_t *buf, uint32_t len) } if (result != MEMTX_OK) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address " TARGET_FMT_plx + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address %016" HWADDR_PRIx " for mem write", __func__, addr); s->regs[R_INT_STATUS] |= R_INT_STATUS_AXI_BRESP_ERR_MASK; xlnx_csu_dma_update_irq(s); diff --git a/hw/i2c/mpc_i2c.c b/hw/i2c/mpc_i2c.c index 845392505f..3e4e185083 100644 --- a/hw/i2c/mpc_i2c.c +++ b/hw/i2c/mpc_i2c.c @@ -224,7 +224,7 @@ static uint64_t mpc_i2c_read(void *opaque, hwaddr addr, unsigned size) break; } - DPRINTF("%s: addr " TARGET_FMT_plx " %02" PRIx32 "\n", __func__, + DPRINTF("%s: addr %016" HWADDR_PRIx " %02" PRIx32 "\n", __func__, addr, value); return (uint64_t)value; } @@ -234,7 +234,7 @@ static void mpc_i2c_write(void *opaque, hwaddr addr, { MPCI2CState *s = opaque; - DPRINTF("%s: addr " TARGET_FMT_plx " val %08" PRIx64 "\n", __func__, + DPRINTF("%s: addr %016" HWADDR_PRIx " val %08" PRIx64 "\n", __func__, addr, value); switch (addr) { case MPC_I2C_ADR: diff --git a/hw/i386/multiboot.c b/hw/i386/multiboot.c index ec747245c2..31b9abb81b 100644 --- a/hw/i386/multiboot.c +++ b/hw/i386/multiboot.c @@ -137,7 +137,7 @@ static void mb_add_mod(MultibootState *s, stl_p(p + MB_MOD_END, end); stl_p(p + MB_MOD_CMDLINE, cmdline_phys); - mb_debug("mod%02d: "TARGET_FMT_plx" - "TARGET_FMT_plx, + mb_debug("mod%02d: %016" HWADDR_PRIx " - %016" HWADDR_PRIx, s->mb_mods_count, start, end); s->mb_mods_count++; @@ -354,7 +354,7 @@ int load_multiboot(X86MachineState *x86ms, mbs.mb_buf_phys + offs + mb_mod_length, c); mb_debug("mod_start: %p\nmod_end: %p\n" - " cmdline: "TARGET_FMT_plx, + " cmdline: %016" HWADDR_PRIx, (char *)mbs.mb_buf + offs, (char *)mbs.mb_buf + offs + mb_mod_length, c); g_free(one_file); @@ -383,8 +383,8 @@ int load_multiboot(X86MachineState *x86ms, stl_p(bootinfo + MBI_MMAP_ADDR, ADDR_E820_MAP); mb_debug("multiboot: entry_addr = %#x", mh_entry_addr); - mb_debug(" mb_buf_phys = "TARGET_FMT_plx, mbs.mb_buf_phys); - mb_debug(" mod_start = "TARGET_FMT_plx, + mb_debug(" mb_buf_phys = %016" HWADDR_PRIx, mbs.mb_buf_phys); + mb_debug(" mod_start = %016" HWADDR_PRIx, mbs.mb_buf_phys + mbs.offset_mods); mb_debug(" mb_mods_count = %d", mbs.mb_mods_count); diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c index 67d250ab54..08c44fcd35 100644 --- a/hw/i386/xen/xen-hvm.c +++ b/hw/i386/xen/xen-hvm.c @@ -516,13 +516,13 @@ static void xen_set_memory(struct MemoryListener *listener, if (xen_set_mem_type(xen_domid, mem_type, start_addr >> TARGET_PAGE_BITS, size >> TARGET_PAGE_BITS)) { - DPRINTF("xen_set_mem_type error, addr: "TARGET_FMT_plx"\n", + DPRINTF("xen_set_mem_type error, addr: %016" HWADDR_PRIx "\n", start_addr); } } } else { if (xen_remove_from_physmap(state, start_addr, size) < 0) { - DPRINTF("physmapping does not exist at "TARGET_FMT_plx"\n", + DPRINTF("physmapping does not exist at %016" HWADDR_PRIx "\n", start_addr); } } @@ -643,8 +643,8 @@ static void xen_sync_dirty_bitmap(XenIOState *state, #endif if (errno == ENODATA) { memory_region_set_dirty(framebuffer, 0, size); - DPRINTF("xen: track_dirty_vram failed (0x" TARGET_FMT_plx - ", 0x" TARGET_FMT_plx "): %s\n", + DPRINTF("xen: track_dirty_vram failed (0x%016" HWADDR_PRIx + ", 0x%016" HWADDR_PRIx "): %s\n", start_addr, start_addr + size, strerror(errno)); } return; diff --git a/hw/i386/xen/xen-mapcache.c b/hw/i386/xen/xen-mapcache.c index 491320e24a..abac16a66a 100644 --- a/hw/i386/xen/xen-mapcache.c +++ b/hw/i386/xen/xen-mapcache.c @@ -358,7 +358,7 @@ tryagain: if (entry->lock == 0) { fprintf(stderr, "mapcache entry lock overflow: " - TARGET_FMT_plx" -> %p\n", + "%016" HWADDR_PRIx " -> %p\n", entry->paddr_index, entry->vaddr_base); abort(); } @@ -405,7 +405,7 @@ ram_addr_t xen_ram_addr_from_mapcache(void *ptr) if (!found) { fprintf(stderr, "%s, could not find %p\n", __func__, ptr); QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) { - DPRINTF(" "TARGET_FMT_plx" -> %p is present\n", + DPRINTF(" %016" HWADDR_PRIx " -> %p is present\n", reventry->paddr_index, reventry->vaddr_req); } abort(); @@ -446,7 +446,7 @@ static void xen_invalidate_map_cache_entry_unlocked(uint8_t *buffer) if (!found) { DPRINTF("%s, could not find %p\n", __func__, buffer); QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) { - DPRINTF(" "TARGET_FMT_plx" -> %p is present\n", + DPRINTF(" %016" HWADDR_PRIx " -> %p is present\n", reventry->paddr_index, reventry->vaddr_req); } return; @@ -505,7 +505,7 @@ void xen_invalidate_map_cache(void) continue; } fprintf(stderr, "Locked DMA mapping while invalidating mapcache!" - " "TARGET_FMT_plx" -> %p is present\n", + " %016" HWADDR_PRIx " -> %p is present\n", reventry->paddr_index, reventry->vaddr_req); } @@ -564,7 +564,7 @@ static uint8_t *xen_replace_cache_entry_unlocked(hwaddr old_phys_addr, entry = entry->next; } if (!entry) { - DPRINTF("Trying to update an entry for "TARGET_FMT_plx \ + DPRINTF("Trying to update an entry for %016" HWADDR_PRIx \ "that is not in the mapcache!\n", old_phys_addr); return NULL; } @@ -572,8 +572,8 @@ static uint8_t *xen_replace_cache_entry_unlocked(hwaddr old_phys_addr, address_index = new_phys_addr >> MCACHE_BUCKET_SHIFT; address_offset = new_phys_addr & (MCACHE_BUCKET_SIZE - 1); - fprintf(stderr, "Replacing a dummy mapcache entry for "TARGET_FMT_plx \ - " with "TARGET_FMT_plx"\n", old_phys_addr, new_phys_addr); + fprintf(stderr, "Replacing a dummy mapcache entry for %016" HWADDR_PRIx \ + " with %016" HWADDR_PRIx "\n", old_phys_addr, new_phys_addr); xen_remap_bucket(entry, entry->vaddr_base, cache_size, address_index, false); @@ -581,7 +581,7 @@ static uint8_t *xen_replace_cache_entry_unlocked(hwaddr old_phys_addr, test_bit_size >> XC_PAGE_SHIFT, entry->valid_mapping)) { DPRINTF("Unable to update a mapcache entry for " - TARGET_FMT_plx "!\n", + "%016" HWADDR_PRIx "!\n", old_phys_addr); return NULL; } diff --git a/hw/i386/xen/xen_platform.c b/hw/i386/xen/xen_platform.c index 7db0d94ec2..392b6d29d5 100644 --- a/hw/i386/xen/xen_platform.c +++ b/hw/i386/xen/xen_platform.c @@ -445,7 +445,7 @@ static uint64_t platform_mmio_read(void *opaque, hwaddr addr, unsigned size) { DPRINTF("Warning: attempted read from physical address " - "0x" TARGET_FMT_plx " in xen platform mmio space\n", addr); + "0x%016" HWADDR_PRIx " in xen platform mmio space\n", addr); return 0; } @@ -454,7 +454,7 @@ static void platform_mmio_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { DPRINTF("Warning: attempted write of 0x%"PRIx64" to physical " - "address 0x" TARGET_FMT_plx " in xen platform mmio space\n", + "address 0x%016" HWADDR_PRIx " in xen platform mmio space\n", val, addr); } diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index d599fefcbc..d827f08bcf 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -564,7 +564,7 @@ static bool gicd_readl(GICv3State *s, hwaddr offset, /* WO registers, return unknown value */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest read from WO register at offset " - TARGET_FMT_plx "\n", __func__, offset); + "%016" HWADDR_PRIx "\n", __func__, offset); *data = 0; return true; default: @@ -773,7 +773,7 @@ static bool gicd_writel(GICv3State *s, hwaddr offset, /* RO registers, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - TARGET_FMT_plx "\n", __func__, offset); + "%016" HWADDR_PRIx "\n", __func__, offset); return true; default: return false; @@ -838,7 +838,7 @@ MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data, if (!r) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid guest read at offset " TARGET_FMT_plx + "%s: invalid guest read at offset %016" HWADDR_PRIx " size %u\n", __func__, offset, size); trace_gicv3_dist_badread(offset, size, attrs.secure); /* The spec requires that reserved registers are RAZ/WI; @@ -879,7 +879,7 @@ MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data, if (!r) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid guest write at offset " TARGET_FMT_plx + "%s: invalid guest write at offset %016" HWADDR_PRIx " size %u\n", __func__, offset, size); trace_gicv3_dist_badwrite(offset, data, size, attrs.secure); /* The spec requires that reserved registers are RAZ/WI; diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 57c79da5c5..ec398b5eb1 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -1633,7 +1633,7 @@ static bool its_writel(GICv3ITSState *s, hwaddr offset, /* RO register, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - TARGET_FMT_plx "\n", __func__, offset); + "%016" HWADDR_PRIx "\n", __func__, offset); } break; case GITS_CREADR + 4: @@ -1643,7 +1643,7 @@ static bool its_writel(GICv3ITSState *s, hwaddr offset, /* RO register, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - TARGET_FMT_plx "\n", __func__, offset); + "%016" HWADDR_PRIx "\n", __func__, offset); } break; case GITS_BASER ... GITS_BASER + 0x3f: @@ -1675,7 +1675,7 @@ static bool its_writel(GICv3ITSState *s, hwaddr offset, /* RO registers, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - TARGET_FMT_plx "\n", __func__, offset); + "%016" HWADDR_PRIx "\n", __func__, offset); break; default: result = false; @@ -1785,14 +1785,14 @@ static bool its_writell(GICv3ITSState *s, hwaddr offset, /* RO register, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - TARGET_FMT_plx "\n", __func__, offset); + "%016" HWADDR_PRIx "\n", __func__, offset); } break; case GITS_TYPER: /* RO registers, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - TARGET_FMT_plx "\n", __func__, offset); + "%016" HWADDR_PRIx "\n", __func__, offset); break; default: result = false; @@ -1851,7 +1851,7 @@ static MemTxResult gicv3_its_read(void *opaque, hwaddr offset, uint64_t *data, if (!result) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid guest read at offset " TARGET_FMT_plx + "%s: invalid guest read at offset %016" HWADDR_PRIx " size %u\n", __func__, offset, size); trace_gicv3_its_badread(offset, size); /* @@ -1887,7 +1887,7 @@ static MemTxResult gicv3_its_write(void *opaque, hwaddr offset, uint64_t data, if (!result) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid guest write at offset " TARGET_FMT_plx + "%s: invalid guest write at offset %016" HWADDR_PRIx " size %u\n", __func__, offset, size); trace_gicv3_its_badwrite(offset, data, size); /* diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index c92ceecc16..b59171735c 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -601,7 +601,7 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset, /* RO registers, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - TARGET_FMT_plx "\n", __func__, offset); + "%016" HWADDR_PRIx "\n", __func__, offset); return MEMTX_OK; /* * VLPI frame registers. We don't need a version check for @@ -668,7 +668,7 @@ static MemTxResult gicr_writell(GICv3CPUState *cs, hwaddr offset, /* RO register, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - TARGET_FMT_plx "\n", __func__, offset); + "%016" HWADDR_PRIx "\n", __func__, offset); return MEMTX_OK; /* * VLPI frame registers. We don't need a version check for @@ -727,7 +727,7 @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data, if (r != MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid guest read at offset " TARGET_FMT_plx + "%s: invalid guest read at offset %016" HWADDR_PRIx " size %u\n", __func__, offset, size); trace_gicv3_redist_badread(gicv3_redist_affid(cs), offset, size, attrs.secure); @@ -786,7 +786,7 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data, if (r != MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid guest write at offset " TARGET_FMT_plx + "%s: invalid guest write at offset %016" HWADDR_PRIx " size %u\n", __func__, offset, size); trace_gicv3_redist_badwrite(gicv3_redist_affid(cs), offset, data, size, attrs.secure); diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c index 44810bb63a..e9493eeaa5 100644 --- a/hw/intc/exynos4210_combiner.c +++ b/hw/intc/exynos4210_combiner.c @@ -120,7 +120,7 @@ exynos4210_combiner_read(void *opaque, hwaddr offset, unsigned size) default: if (offset >> 2 >= IIC_REGSET_SIZE) { hw_error("exynos4210.combiner: overflow of reg_set by" - " 0x" TARGET_FMT_plx "offset\n", offset); + " 0x%016" HWADDR_PRIx "offset\n", offset); } val = s->reg_set[offset >> 2]; } @@ -184,19 +184,19 @@ static void exynos4210_combiner_write(void *opaque, hwaddr offset, if (req_quad_base_n >= IIC_NGRP) { hw_error("exynos4210.combiner: unallowed write access at offset" - " 0x" TARGET_FMT_plx "\n", offset); + " 0x%016" HWADDR_PRIx "\n", offset); return; } if (reg_n > 1) { hw_error("exynos4210.combiner: unallowed write access at offset" - " 0x" TARGET_FMT_plx "\n", offset); + " 0x%016" HWADDR_PRIx "\n", offset); return; } if (offset >> 2 >= IIC_REGSET_SIZE) { hw_error("exynos4210.combiner: overflow of reg_set by" - " 0x" TARGET_FMT_plx "offset\n", offset); + " 0x%016" HWADDR_PRIx "offset\n", offset); } s->reg_set[offset >> 2] = val; @@ -246,7 +246,7 @@ static void exynos4210_combiner_write(void *opaque, hwaddr offset, break; default: hw_error("exynos4210.combiner: unallowed write access at offset" - " 0x" TARGET_FMT_plx "\n", offset); + " 0x%016" HWADDR_PRIx "\n", offset); break; } } diff --git a/hw/misc/auxbus.c b/hw/misc/auxbus.c index a2a0f88836..014a30f5a1 100644 --- a/hw/misc/auxbus.c +++ b/hw/misc/auxbus.c @@ -300,7 +300,7 @@ static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent) s = AUX_SLAVE(dev); monitor_printf(mon, - "%*smemory " TARGET_FMT_plx "/" TARGET_FMT_plx "\n", + "%*smemory %016" HWADDR_PRIx "/%016" HWADDR_PRIx "\n", indent, "", object_property_get_uint(OBJECT(s->mmio), "addr", NULL), memory_region_size(s->mmio)); diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c index 8270db53cd..ee41b90018 100644 --- a/hw/misc/ivshmem.c +++ b/hw/misc/ivshmem.c @@ -179,7 +179,7 @@ static void ivshmem_io_write(void *opaque, hwaddr addr, addr &= 0xfc; - IVSHMEM_DPRINTF("writing to addr " TARGET_FMT_plx "\n", addr); + IVSHMEM_DPRINTF("writing to addr %016" HWADDR_PRIx "\n", addr); switch (addr) { case INTRMASK: @@ -207,7 +207,7 @@ static void ivshmem_io_write(void *opaque, hwaddr addr, } break; default: - IVSHMEM_DPRINTF("Unhandled write " TARGET_FMT_plx "\n", addr); + IVSHMEM_DPRINTF("Unhandled write %016" HWADDR_PRIx "\n", addr); } } @@ -233,7 +233,7 @@ static uint64_t ivshmem_io_read(void *opaque, hwaddr addr, break; default: - IVSHMEM_DPRINTF("why are we reading " TARGET_FMT_plx "\n", addr); + IVSHMEM_DPRINTF("why are we reading %016" HWADDR_PRIx "\n", addr); ret = 0; } diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdma.c index efcc02609f..82322ed736 100644 --- a/hw/misc/macio/mac_dbdma.c +++ b/hw/misc/macio/mac_dbdma.c @@ -704,7 +704,7 @@ static void dbdma_write(void *opaque, hwaddr addr, DBDMA_channel *ch = &s->channels[channel]; int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2; - DBDMA_DPRINTFCH(ch, "writel 0x" TARGET_FMT_plx " <= 0x%08"PRIx64"\n", + DBDMA_DPRINTFCH(ch, "writel 0x%016" HWADDR_PRIx " <= 0x%08"PRIx64"\n", addr, value); DBDMA_DPRINTFCH(ch, "channel 0x%x reg 0x%x\n", (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg); @@ -786,7 +786,7 @@ static uint64_t dbdma_read(void *opaque, hwaddr addr, break; } - DBDMA_DPRINTFCH(ch, "readl 0x" TARGET_FMT_plx " => 0x%08x\n", addr, value); + DBDMA_DPRINTFCH(ch, "readl 0x%016" HWADDR_PRIx " => 0x%08x\n", addr, value); DBDMA_DPRINTFCH(ch, "channel 0x%x reg 0x%x\n", (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg); diff --git a/hw/misc/mst_fpga.c b/hw/misc/mst_fpga.c index 87c09217a6..2d57bc86bd 100644 --- a/hw/misc/mst_fpga.c +++ b/hw/misc/mst_fpga.c @@ -130,7 +130,7 @@ static uint64_t mst_fpga_readb(void *opaque, hwaddr addr, unsigned size) return s->pcmcia1; default: printf("Mainstone - mst_fpga_readb: Bad register offset " - "0x" TARGET_FMT_plx "\n", addr); + "0x%016" HWADDR_PRIx "\n", addr); } return 0; } @@ -183,7 +183,7 @@ static void mst_fpga_writeb(void *opaque, hwaddr addr, uint64_t value, break; default: printf("Mainstone - mst_fpga_writeb: Bad register offset " - "0x" TARGET_FMT_plx "\n", addr); + "0x%016" HWADDR_PRIx "\n", addr); } } diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c index ecc0245fe8..b903bf87db 100644 --- a/hw/net/allwinner-sun8i-emac.c +++ b/hw/net/allwinner-sun8i-emac.c @@ -663,7 +663,7 @@ static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset, break; default: qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to unknown " - "EMAC register 0x" TARGET_FMT_plx "\n", + "EMAC register 0x%016" HWADDR_PRIx "\n", offset); } @@ -760,7 +760,7 @@ static void allwinner_sun8i_emac_write(void *opaque, hwaddr offset, break; default: qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to unknown " - "EMAC register 0x" TARGET_FMT_plx "\n", + "EMAC register 0x%016" HWADDR_PRIx "\n", offset); } } diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c index 53412c23e4..6bfb9286fe 100644 --- a/hw/net/allwinner_emac.c +++ b/hw/net/allwinner_emac.c @@ -304,7 +304,7 @@ static uint64_t aw_emac_read(void *opaque, hwaddr offset, unsigned size) default: qemu_log_mask(LOG_UNIMP, "allwinner_emac: read access to unknown register" - " 0x" TARGET_FMT_plx "\n", offset); + " 0x%016" HWADDR_PRIx "\n", offset); ret = 0; } @@ -407,7 +407,7 @@ static void aw_emac_write(void *opaque, hwaddr offset, uint64_t value, default: qemu_log_mask(LOG_UNIMP, "allwinner_emac: write access to unknown register" - " 0x" TARGET_FMT_plx "\n", offset); + " 0x%016" HWADDR_PRIx "\n", offset); } } diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c index b75d8e3dce..4c020e9105 100644 --- a/hw/net/fsl_etsec/etsec.c +++ b/hw/net/fsl_etsec/etsec.c @@ -99,7 +99,7 @@ static uint64_t etsec_read(void *opaque, hwaddr addr, unsigned size) break; } - DPRINTF("Read 0x%08x @ 0x" TARGET_FMT_plx + DPRINTF("Read 0x%08x @ 0x%016" HWADDR_PRIx " : %s (%s)\n", ret, addr, reg->name, reg->desc); @@ -276,7 +276,7 @@ static void etsec_write(void *opaque, } } - DPRINTF("Write 0x%08x @ 0x" TARGET_FMT_plx + DPRINTF("Write 0x%08x @ 0x%016" HWADDR_PRIx " val:0x%08x->0x%08x : %s (%s)\n", (unsigned int)value, addr, before, reg->value, reg->name, reg->desc); diff --git a/hw/net/fsl_etsec/rings.c b/hw/net/fsl_etsec/rings.c index a32589e33b..9ff1f894e6 100644 --- a/hw/net/fsl_etsec/rings.c +++ b/hw/net/fsl_etsec/rings.c @@ -109,7 +109,7 @@ static void read_buffer_descriptor(eTSEC *etsec, { assert(bd != NULL); - RING_DEBUG("READ Buffer Descriptor @ 0x" TARGET_FMT_plx"\n", addr); + RING_DEBUG("READ Buffer Descriptor @ 0x%016" HWADDR_PRIx "\n", addr); cpu_physical_memory_read(addr, bd, sizeof(eTSEC_rxtx_bd)); @@ -141,7 +141,7 @@ static void write_buffer_descriptor(eTSEC *etsec, stl_be_p(&bd->bufptr, bd->bufptr); } - RING_DEBUG("Write Buffer Descriptor @ 0x" TARGET_FMT_plx"\n", addr); + RING_DEBUG("Write Buffer Descriptor @ 0x%016" HWADDR_PRIx "\n", addr); cpu_physical_memory_write(addr, bd, sizeof(eTSEC_rxtx_bd)); diff --git a/hw/net/pcnet.c b/hw/net/pcnet.c index e63e524913..ac6514c17a 100644 --- a/hw/net/pcnet.c +++ b/hw/net/pcnet.c @@ -908,11 +908,11 @@ static void pcnet_rdte_poll(PCNetState *s) s->csr[37] = nnrd >> 16; #ifdef PCNET_DEBUG if (bad) { - printf("pcnet: BAD RMD RECORDS AFTER 0x" TARGET_FMT_plx "\n", + printf("pcnet: BAD RMD RECORDS AFTER 0x%016" HWADDR_PRIx "\n", crda); } } else { - printf("pcnet: BAD RMD RDA=0x" TARGET_FMT_plx "\n", crda); + printf("pcnet: BAD RMD RDA=0x%016" HWADDR_PRIx "\n", crda); #endif } } diff --git a/hw/net/rocker/rocker.c b/hw/net/rocker/rocker.c index cf54ddf49d..0d41dd52a2 100644 --- a/hw/net/rocker/rocker.c +++ b/hw/net/rocker/rocker.c @@ -815,7 +815,7 @@ static void rocker_io_writel(void *opaque, hwaddr addr, uint32_t val) } break; default: - DPRINTF("not implemented dma reg write(l) addr=0x" TARGET_FMT_plx + DPRINTF("not implemented dma reg write(l) addr=0x%016" HWADDR_PRIx " val=0x%08x (ring %d, addr=0x%02x)\n", addr, val, index, offset); break; @@ -857,7 +857,7 @@ static void rocker_io_writel(void *opaque, hwaddr addr, uint32_t val) r->lower32 = 0; break; default: - DPRINTF("not implemented write(l) addr=0x" TARGET_FMT_plx + DPRINTF("not implemented write(l) addr=0x%016" HWADDR_PRIx " val=0x%08x\n", addr, val); break; } @@ -876,8 +876,8 @@ static void rocker_io_writeq(void *opaque, hwaddr addr, uint64_t val) desc_ring_set_base_addr(r->rings[index], val); break; default: - DPRINTF("not implemented dma reg write(q) addr=0x" TARGET_FMT_plx - " val=0x" TARGET_FMT_plx " (ring %d, offset=0x%02x)\n", + DPRINTF("not implemented dma reg write(q) addr=0x%016" HWADDR_PRIx + " val=0x%016" HWADDR_PRIx " (ring %d, offset=0x%02x)\n", addr, val, index, offset); break; } @@ -895,8 +895,8 @@ static void rocker_io_writeq(void *opaque, hwaddr addr, uint64_t val) rocker_port_phys_enable_write(r, val); break; default: - DPRINTF("not implemented write(q) addr=0x" TARGET_FMT_plx - " val=0x" TARGET_FMT_plx "\n", addr, val); + DPRINTF("not implemented write(q) addr=0x%016" HWADDR_PRIx + " val=0x%016" HWADDR_PRIx "\n", addr, val); break; } } @@ -987,8 +987,8 @@ static const char *rocker_reg_name(void *opaque, hwaddr addr) static void rocker_mmio_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - DPRINTF("Write %s addr " TARGET_FMT_plx - ", size %u, val " TARGET_FMT_plx "\n", + DPRINTF("Write %s addr %016" HWADDR_PRIx + ", size %u, val %016" HWADDR_PRIx "\n", rocker_reg_name(opaque, addr), addr, size, val); switch (size) { @@ -1060,7 +1060,7 @@ static uint32_t rocker_io_readl(void *opaque, hwaddr addr) ret = desc_ring_get_credits(r->rings[index]); break; default: - DPRINTF("not implemented dma reg read(l) addr=0x" TARGET_FMT_plx + DPRINTF("not implemented dma reg read(l) addr=0x%016" HWADDR_PRIx " (ring %d, addr=0x%02x)\n", addr, index, offset); ret = 0; break; @@ -1115,7 +1115,7 @@ static uint32_t rocker_io_readl(void *opaque, hwaddr addr) ret = (uint32_t)(r->switch_id >> 32); break; default: - DPRINTF("not implemented read(l) addr=0x" TARGET_FMT_plx "\n", addr); + DPRINTF("not implemented read(l) addr=0x%016" HWADDR_PRIx "\n", addr); ret = 0; break; } @@ -1136,7 +1136,7 @@ static uint64_t rocker_io_readq(void *opaque, hwaddr addr) ret = desc_ring_get_base_addr(r->rings[index]); break; default: - DPRINTF("not implemented dma reg read(q) addr=0x" TARGET_FMT_plx + DPRINTF("not implemented dma reg read(q) addr=0x%016" HWADDR_PRIx " (ring %d, addr=0x%02x)\n", addr, index, offset); ret = 0; break; @@ -1165,7 +1165,7 @@ static uint64_t rocker_io_readq(void *opaque, hwaddr addr) ret = r->switch_id; break; default: - DPRINTF("not implemented read(q) addr=0x" TARGET_FMT_plx "\n", addr); + DPRINTF("not implemented read(q) addr=0x%016" HWADDR_PRIx "\n", addr); ret = 0; break; } @@ -1174,7 +1174,7 @@ static uint64_t rocker_io_readq(void *opaque, hwaddr addr) static uint64_t rocker_mmio_read(void *opaque, hwaddr addr, unsigned size) { - DPRINTF("Read %s addr " TARGET_FMT_plx ", size %u\n", + DPRINTF("Read %s addr %016" HWADDR_PRIx ", size %u\n", rocker_reg_name(opaque, addr), addr, size); switch (size) { diff --git a/hw/net/rocker/rocker_desc.c b/hw/net/rocker/rocker_desc.c index f3068c9250..dfdfbafde7 100644 --- a/hw/net/rocker/rocker_desc.c +++ b/hw/net/rocker/rocker_desc.c @@ -104,7 +104,7 @@ static bool desc_ring_empty(DescRing *ring) bool desc_ring_set_base_addr(DescRing *ring, uint64_t base_addr) { if (base_addr & 0x7) { - DPRINTF("ERROR: ring[%d] desc base addr (0x" TARGET_FMT_plx + DPRINTF("ERROR: ring[%d] desc base addr (0x%016" HWADDR_PRIx ") not 8-byte aligned\n", ring->index, base_addr); return false; } diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index 990ff3a1c2..814b71a93c 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -524,7 +524,7 @@ static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) if (addr < ARRAY_SIZE(s->regs)) { r = s->regs[addr]; } - DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", + DENET(qemu_log("%s addr=%016" HWADDR_PRIx " v=%x\n", __func__, addr * 4, r)); break; } @@ -630,7 +630,7 @@ static void enet_write(void *opaque, hwaddr addr, break; default: - DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n", + DENET(qemu_log("%s addr=%016" HWADDR_PRIx " v=%x\n", __func__, addr * 4, (unsigned)value)); if (addr < ARRAY_SIZE(s->regs)) { s->regs[addr] = value; diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 6e09f7e422..150248e543 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -99,7 +99,7 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) case R_RX_CTRL1: case R_RX_CTRL0: r = s->regs[addr]; - D(qemu_log("%s " TARGET_FMT_plx "=%x\n", __func__, addr * 4, r)); + D(qemu_log("%s %016" HWADDR_PRIx "=%x\n", __func__, addr * 4, r)); break; default: @@ -125,7 +125,7 @@ eth_write(void *opaque, hwaddr addr, if (addr == R_TX_CTRL1) base = 0x800 / 4; - D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n", + D(qemu_log("%s addr=%016" HWADDR_PRIx " val=%x\n", __func__, addr * 4, value)); if ((value & (CTRL_P | CTRL_S)) == CTRL_S) { qemu_send_packet(qemu_get_queue(s->nic), @@ -155,7 +155,7 @@ eth_write(void *opaque, hwaddr addr, case R_TX_LEN0: case R_TX_LEN1: case R_TX_GIE0: - D(qemu_log("%s addr=" TARGET_FMT_plx " val=%x\n", + D(qemu_log("%s addr=%016" HWADDR_PRIx " val=%x\n", __func__, addr * 4, value)); s->regs[addr] = value; break; diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c index 870d9bab11..16b427d3c1 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -155,7 +155,7 @@ static char *pxb_host_ofw_unit_address(const SysBusDevice *dev) main_host_sbd = SYS_BUS_DEVICE(main_host); if (main_host_sbd->num_mmio > 0) { - return g_strdup_printf(TARGET_FMT_plx ",%x", + return g_strdup_printf("%016" HWADDR_PRIx ",%x", main_host_sbd->mmio[0].addr, position + 1); } if (main_host_sbd->num_pio > 0) { diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c index f04f3ad668..2d54435f74 100644 --- a/hw/pci-host/bonito.c +++ b/hw/pci-host/bonito.c @@ -254,7 +254,7 @@ static void bonito_writel(void *opaque, hwaddr addr, saddr = addr >> 2; - DPRINTF("bonito_writel "TARGET_FMT_plx" val %lx saddr %x\n", + DPRINTF("bonito_writel %016" HWADDR_PRIx " val %lx saddr %x\n", addr, val, saddr); switch (saddr) { case BONITO_BONPONCFG: @@ -317,7 +317,7 @@ static uint64_t bonito_readl(void *opaque, hwaddr addr, saddr = addr >> 2; - DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr); + DPRINTF("bonito_readl %016" HWADDR_PRIx "\n", addr); switch (saddr) { case BONITO_INTISR: return s->regs[saddr]; @@ -342,7 +342,7 @@ static void bonito_pciconf_writel(void *opaque, hwaddr addr, PCIBonitoState *s = opaque; PCIDevice *d = PCI_DEVICE(s); - DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %lx\n", addr, val); + DPRINTF("bonito_pciconf_writel %016" HWADDR_PRIx " val %lx\n", addr, val); d->config_write(d, addr, val, 4); } @@ -353,7 +353,7 @@ static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr, PCIBonitoState *s = opaque; PCIDevice *d = PCI_DEVICE(s); - DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr); + DPRINTF("bonito_pciconf_readl %016" HWADDR_PRIx "\n", addr); return d->config_read(d, addr, 4); } @@ -469,7 +469,7 @@ static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr) regno = (cfgaddr & BONITO_PCICONF_REG_MASK_HW) >> BONITO_PCICONF_REG_OFFSET; if (idsel == 0) { - error_report("error in bonito pci config address 0x" TARGET_FMT_plx + error_report("error in bonito pci config address 0x%016" HWADDR_PRIx ",pcimap_cfg=0x%x", addr, s->regs[BONITO_PCIMAP_CFG]); exit(1); } @@ -489,7 +489,7 @@ static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val, uint32_t pciaddr; uint16_t status; - DPRINTF("bonito_spciconf_write "TARGET_FMT_plx" size %d val %lx\n", + DPRINTF("bonito_spciconf_write %016" HWADDR_PRIx " size %d val %lx\n", addr, size, val); pciaddr = bonito_sbridge_pciaddr(s, addr); @@ -519,7 +519,7 @@ static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size) uint32_t pciaddr; uint16_t status; - DPRINTF("bonito_spciconf_read "TARGET_FMT_plx" size %d\n", addr, size); + DPRINTF("bonito_spciconf_read %016" HWADDR_PRIx " size %d\n", addr, size); pciaddr = bonito_sbridge_pciaddr(s, addr); diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c index 568849e930..b522da730c 100644 --- a/hw/pci-host/ppce500.c +++ b/hw/pci-host/ppce500.c @@ -189,7 +189,7 @@ static uint64_t pci_reg_read4(void *opaque, hwaddr addr, break; } - pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__, + pci_debug("%s: win:%lx(addr:%016" HWADDR_PRIx ") -> value:%x\n", __func__, win, addr, value); return value; } @@ -268,7 +268,7 @@ static void pci_reg_write4(void *opaque, hwaddr addr, win = addr & 0xfe0; - pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n", + pci_debug("%s: value:%x -> win:%lx(addr:%016" HWADDR_PRIx ")\n", __func__, (unsigned)value, win, addr); switch (win) { diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c index eaf217ff55..efb1a9d901 100644 --- a/hw/pci/pci_host.c +++ b/hw/pci/pci_host.c @@ -143,7 +143,7 @@ static void pci_host_config_write(void *opaque, hwaddr addr, { PCIHostState *s = opaque; - PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx64"\n", + PCI_DPRINTF("%s addr %016" HWADDR_PRIx " len %d val %"PRIx64"\n", __func__, addr, len, val); if (addr != 0 || len != 4) { return; @@ -157,7 +157,7 @@ static uint64_t pci_host_config_read(void *opaque, hwaddr addr, PCIHostState *s = opaque; uint32_t val = s->config_reg; - PCI_DPRINTF("%s addr " TARGET_FMT_plx " len %d val %"PRIx32"\n", + PCI_DPRINTF("%s addr %016" HWADDR_PRIx " len %d val %"PRIx32"\n", __func__, addr, len, val); return val; } diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c index a24c80b1d2..b306683cfb 100644 --- a/hw/ppc/ppc4xx_sdram.c +++ b/hw/ppc/ppc4xx_sdram.c @@ -500,7 +500,7 @@ static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size) bcr = 0x8000; break; default: - error_report("invalid RAM size " TARGET_FMT_plx, ram_size); + error_report("invalid RAM size %016" HWADDR_PRIx, ram_size); return 0; } bcr |= ram_base >> 2 & 0xffe00000; diff --git a/hw/rtc/exynos4210_rtc.c b/hw/rtc/exynos4210_rtc.c index d1620c7a2a..1ec3b20501 100644 --- a/hw/rtc/exynos4210_rtc.c +++ b/hw/rtc/exynos4210_rtc.c @@ -374,7 +374,7 @@ static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset, default: qemu_log_mask(LOG_GUEST_ERROR, - "exynos4210.rtc: bad read offset " TARGET_FMT_plx, + "exynos4210.rtc: bad read offset %016" HWADDR_PRIx, offset); break; } @@ -508,7 +508,7 @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset, default: qemu_log_mask(LOG_GUEST_ERROR, - "exynos4210.rtc: bad write offset " TARGET_FMT_plx, + "exynos4210.rtc: bad write offset %016" HWADDR_PRIx, offset); break; diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index c77792d150..9d1f0a2f28 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -207,13 +207,13 @@ static void portb_changed(SH7750State *s, uint16_t prev) static void error_access(const char *kind, hwaddr addr) { - fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n", + fprintf(stderr, "%s to %s (0x%016" HWADDR_PRIx ") not supported\n", kind, regname(addr), addr); } static void ignore_access(const char *kind, hwaddr addr) { - fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n", + fprintf(stderr, "%s to %s (0x%016" HWADDR_PRIx ") ignored\n", kind, regname(addr), addr); } diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c index b2819a7ff0..be4a40f0ca 100644 --- a/hw/ssi/xilinx_spi.c +++ b/hw/ssi/xilinx_spi.c @@ -232,7 +232,7 @@ spi_read(void *opaque, hwaddr addr, unsigned int size) break; } - DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, r); + DB_PRINT("addr=%016" HWADDR_PRIx " = %x\n", addr * 4, r); xlx_spi_update_irq(s); return r; } @@ -244,7 +244,7 @@ spi_write(void *opaque, hwaddr addr, XilinxSPI *s = opaque; uint32_t value = val64; - DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, value); + DB_PRINT("addr=%016" HWADDR_PRIx " = %x\n", addr, value); addr >>= 2; switch (addr) { case R_SRR: diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 1e9dba2039..8b7e715c74 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -887,7 +887,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, case R_INTR_STATUS: ret = s->regs[addr] & IXR_ALL; s->regs[addr] = 0; - DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); + DB_PRINT_L(0, "addr=%016" HWADDR_PRIx " = %x\n", addr * 4, ret); xilinx_spips_update_ixr(s); return ret; case R_INTR_MASK: @@ -916,12 +916,12 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) { ret <<= 8 * shortfall; } - DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); + DB_PRINT_L(0, "addr=%016" HWADDR_PRIx " = %x\n", addr * 4, ret); xilinx_spips_check_flush(s); xilinx_spips_update_ixr(s); return ret; } - DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, + DB_PRINT_L(0, "addr=%016" HWADDR_PRIx " = %x\n", addr * 4, s->regs[addr] & mask); return s->regs[addr] & mask; @@ -971,7 +971,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, XilinxSPIPS *s = opaque; bool try_flush = true; - DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value); + DB_PRINT_L(0, "addr=%016" HWADDR_PRIx " = %x\n", addr, (unsigned)value); addr >>= 2; switch (addr) { case R_CONFIG: diff --git a/hw/timer/digic-timer.c b/hw/timer/digic-timer.c index d324b5e698..66a721b2f0 100644 --- a/hw/timer/digic-timer.c +++ b/hw/timer/digic-timer.c @@ -76,7 +76,7 @@ static uint64_t digic_timer_read(void *opaque, hwaddr offset, unsigned size) default: qemu_log_mask(LOG_UNIMP, "digic-timer: read access to unknown register" - " 0x" TARGET_FMT_plx "\n", offset); + " 0x%016" HWADDR_PRIx "\n", offset); } return ret; @@ -116,7 +116,7 @@ static void digic_timer_write(void *opaque, hwaddr offset, default: qemu_log_mask(LOG_UNIMP, "digic-timer: read access to unknown register" - " 0x" TARGET_FMT_plx "\n", offset); + " 0x%016" HWADDR_PRIx "\n", offset); } } diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c index 993df3557d..782a370159 100644 --- a/hw/timer/etraxfs_timer.c +++ b/hw/timer/etraxfs_timer.c @@ -324,7 +324,7 @@ timer_write(void *opaque, hwaddr addr, t->rw_ack_intr = 0; break; default: - printf("%s " TARGET_FMT_plx " %x\n", __func__, addr, value); + printf("%s %016" HWADDR_PRIx " %x\n", __func__, addr, value); break; } } diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c index e175a9f5b9..5f5d53c009 100644 --- a/hw/timer/exynos4210_mct.c +++ b/hw/timer/exynos4210_mct.c @@ -1445,7 +1445,7 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, case L0_ICNTO: case L1_ICNTO: case L0_FRCNTO: case L1_FRCNTO: qemu_log_mask(LOG_GUEST_ERROR, - "exynos4210.mct: write to RO register " TARGET_FMT_plx, + "exynos4210.mct: write to RO register %016" HWADDR_PRIx, offset); break; diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c index 02924a9e5b..a4ac44e150 100644 --- a/hw/timer/exynos4210_pwm.c +++ b/hw/timer/exynos4210_pwm.c @@ -257,7 +257,7 @@ static uint64_t exynos4210_pwm_read(void *opaque, hwaddr offset, default: qemu_log_mask(LOG_GUEST_ERROR, - "exynos4210.pwm: bad read offset " TARGET_FMT_plx, + "exynos4210.pwm: bad read offset %016" HWADDR_PRIx, offset); break; } @@ -352,7 +352,7 @@ static void exynos4210_pwm_write(void *opaque, hwaddr offset, default: qemu_log_mask(LOG_GUEST_ERROR, - "exynos4210.pwm: bad write offset " TARGET_FMT_plx, + "exynos4210.pwm: bad write offset %016" HWADDR_PRIx, offset); break; diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c index 103260ec15..c90f620802 100644 --- a/hw/virtio/virtio-mmio.c +++ b/hw/virtio/virtio-mmio.c @@ -829,10 +829,10 @@ static char *virtio_mmio_bus_get_dev_path(DeviceState *dev) assert(section.mr); if (proxy_path) { - path = g_strdup_printf("%s/virtio-mmio@" TARGET_FMT_plx, proxy_path, + path = g_strdup_printf("%s/virtio-mmio@%016" HWADDR_PRIx, proxy_path, section.offset_within_address_space); } else { - path = g_strdup_printf("virtio-mmio@" TARGET_FMT_plx, + path = g_strdup_printf("virtio-mmio@%016" HWADDR_PRIx, section.offset_within_address_space); } memory_region_unref(section.mr); diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c index 0ec7e52183..1f0c8c7050 100644 --- a/hw/xen/xen_pt.c +++ b/hw/xen/xen_pt.c @@ -434,7 +434,7 @@ static uint64_t xen_pt_bar_read(void *o, hwaddr addr, PCIDevice *d = o; /* if this function is called, that probably means that there is a * misconfiguration of the IOMMU. */ - XEN_PT_ERR(d, "Should not read BAR through QEMU. @0x"TARGET_FMT_plx"\n", + XEN_PT_ERR(d, "Should not read BAR through QEMU. @0x%016" HWADDR_PRIx "\n", addr); return 0; } @@ -443,7 +443,7 @@ static void xen_pt_bar_write(void *o, hwaddr addr, uint64_t val, { PCIDevice *d = o; /* Same comment as xen_pt_bar_read function */ - XEN_PT_ERR(d, "Should not write BAR through QEMU. @0x"TARGET_FMT_plx"\n", + XEN_PT_ERR(d, "Should not write BAR through QEMU. @0x%016" HWADDR_PRIx "\n", addr); } diff --git a/include/exec/hwaddr.h b/include/exec/hwaddr.h index 8f16d179a8..30c748cec6 100644 --- a/include/exec/hwaddr.h +++ b/include/exec/hwaddr.h @@ -10,7 +10,6 @@ typedef uint64_t hwaddr; #define HWADDR_MAX UINT64_MAX -#define TARGET_FMT_plx "%016" PRIx64 #define HWADDR_PRId PRId64 #define HWADDR_PRIi PRIi64 #define HWADDR_PRIo PRIo64 diff --git a/monitor/misc.c b/monitor/misc.c index bf3f1c67ca..9861ec2905 100644 --- a/monitor/misc.c +++ b/monitor/misc.c @@ -566,7 +566,7 @@ static void memory_dump(Monitor *mon, int count, int format, int wsize, while (len > 0) { if (is_physical) { - monitor_printf(mon, TARGET_FMT_plx ":", addr); + monitor_printf(mon, "%016" HWADDR_PRIx ":", addr); } else { monitor_printf(mon, TARGET_FMT_lx ":", (target_ulong)addr); } diff --git a/softmmu/memory.c b/softmmu/memory.c index e8c1f73312..14850d4d3c 100644 --- a/softmmu/memory.c +++ b/softmmu/memory.c @@ -1281,7 +1281,7 @@ static uint64_t unassigned_mem_read(void *opaque, hwaddr addr, unsigned size) { #ifdef DEBUG_UNASSIGNED - printf("Unassigned mem read " TARGET_FMT_plx "\n", addr); + printf("Unassigned mem read %016" HWADDR_PRIx "\n", addr); #endif return 0; } @@ -1290,7 +1290,7 @@ static void unassigned_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { #ifdef DEBUG_UNASSIGNED - printf("Unassigned mem write " TARGET_FMT_plx " = 0x%"PRIx64"\n", + printf("Unassigned mem write %016" HWADDR_PRIx " = 0x%"PRIx64"\n", addr, val); #endif } @@ -3221,9 +3221,9 @@ static void mtree_print_mr(const MemoryRegion *mr, unsigned int level, for (i = 0; i < level; i++) { qemu_printf(MTREE_INDENT); } - qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx - " (prio %d, %s%s): alias %s @%s " TARGET_FMT_plx - "-" TARGET_FMT_plx "%s", + qemu_printf("%016" HWADDR_PRIx "-%016" HWADDR_PRIx + " (prio %d, %s%s): alias %s @%s %016" HWADDR_PRIx + "-%016" HWADDR_PRIx "%s", cur_start, cur_end, mr->priority, mr->nonvolatile ? "nv-" : "", @@ -3243,7 +3243,7 @@ static void mtree_print_mr(const MemoryRegion *mr, unsigned int level, for (i = 0; i < level; i++) { qemu_printf(MTREE_INDENT); } - qemu_printf(TARGET_FMT_plx "-" TARGET_FMT_plx + qemu_printf("%016" HWADDR_PRIx "-%016" HWADDR_PRIx " (prio %d, %s%s): %s%s", cur_start, cur_end, mr->priority, @@ -3330,8 +3330,8 @@ static void mtree_print_flatview(gpointer key, gpointer value, while (n--) { mr = range->mr; if (range->offset_in_region) { - qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx - " (prio %d, %s%s): %s @" TARGET_FMT_plx, + qemu_printf(MTREE_INDENT "%016" HWADDR_PRIx "-%016" HWADDR_PRIx + " (prio %d, %s%s): %s @%016" HWADDR_PRIx, int128_get64(range->addr.start), int128_get64(range->addr.start) + MR_SIZE(range->addr.size), @@ -3341,7 +3341,7 @@ static void mtree_print_flatview(gpointer key, gpointer value, memory_region_name(mr), range->offset_in_region); } else { - qemu_printf(MTREE_INDENT TARGET_FMT_plx "-" TARGET_FMT_plx + qemu_printf(MTREE_INDENT "%016" HWADDR_PRIx "-%016" HWADDR_PRIx " (prio %d, %s%s): %s", int128_get64(range->addr.start), int128_get64(range->addr.start) diff --git a/softmmu/memory_mapping.c b/softmmu/memory_mapping.c index f6f0a829fd..c82c896a68 100644 --- a/softmmu/memory_mapping.c +++ b/softmmu/memory_mapping.c @@ -241,8 +241,8 @@ static void guest_phys_block_add_section(GuestPhysListener *g, } #ifdef DEBUG_GUEST_PHYS_REGION_ADD - fprintf(stderr, "%s: target_start=" TARGET_FMT_plx " target_end=" - TARGET_FMT_plx ": %s (count: %u)\n", __func__, target_start, + fprintf(stderr, "%s: target_start=%016" HWADDR_PRIx " target_end=" + "%016" HWADDR_PRIx ": %s (count: %u)\n", __func__, target_start, target_end, predecessor ? "joined" : "added", g->list->num); #endif } diff --git a/softmmu/physmem.c b/softmmu/physmem.c index edec095c7a..f8e094dfef 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -2475,7 +2475,7 @@ static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data, MemTxResult res; #if defined(DEBUG_SUBPAGE) - printf("%s: subpage %p len %u addr " TARGET_FMT_plx "\n", __func__, + printf("%s: subpage %p len %u addr %016" HWADDR_PRIx "\n", __func__, subpage, len, addr); #endif res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len); @@ -2493,7 +2493,7 @@ static MemTxResult subpage_write(void *opaque, hwaddr addr, uint8_t buf[8]; #if defined(DEBUG_SUBPAGE) - printf("%s: subpage %p len %u addr " TARGET_FMT_plx + printf("%s: subpage %p len %u addr %016" HWADDR_PRIx " value %"PRIx64"\n", __func__, subpage, len, addr, value); #endif @@ -2507,7 +2507,7 @@ static bool subpage_accepts(void *opaque, hwaddr addr, { subpage_t *subpage = opaque; #if defined(DEBUG_SUBPAGE) - printf("%s: subpage %p %c len %u addr " TARGET_FMT_plx "\n", + printf("%s: subpage %p %c len %u addr %016" HWADDR_PRIx "\n", __func__, subpage, is_write ? 'w' : 'r', len, addr); #endif @@ -2558,7 +2558,7 @@ static subpage_t *subpage_init(FlatView *fv, hwaddr base) NULL, TARGET_PAGE_SIZE); mmio->iomem.subpage = true; #if defined(DEBUG_SUBPAGE) - printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__, + printf("%s: %p base %016" HWADDR_PRIx " len %08x\n", __func__, mmio, base, TARGET_PAGE_SIZE); #endif @@ -3703,7 +3703,7 @@ void mtree_print_dispatch(AddressSpaceDispatch *d, MemoryRegion *root) const char *names[] = { " [unassigned]", " [not dirty]", " [ROM]", " [watch]" }; - qemu_printf(" #%d @" TARGET_FMT_plx ".." TARGET_FMT_plx + qemu_printf(" #%d @%016" HWADDR_PRIx "..%016" HWADDR_PRIx " %s%s%s%s%s", i, s->offset_within_address_space, diff --git a/target/i386/monitor.c b/target/i386/monitor.c index 8e4b4d600c..59b7a814ea 100644 --- a/target/i386/monitor.c +++ b/target/i386/monitor.c @@ -57,7 +57,7 @@ static void print_pte(Monitor *mon, CPUArchState *env, hwaddr addr, { addr = addr_canonical(env, addr); - monitor_printf(mon, TARGET_FMT_plx ": " TARGET_FMT_plx + monitor_printf(mon, "%016" HWADDR_PRIx ": %016" HWADDR_PRIx " %c%c%c%c%c%c%c%c%c\n", addr, pte & mask, @@ -258,8 +258,8 @@ static void mem_print(Monitor *mon, CPUArchState *env, prot1 = *plast_prot; if (prot != prot1) { if (*pstart != -1) { - monitor_printf(mon, TARGET_FMT_plx "-" TARGET_FMT_plx " " - TARGET_FMT_plx " %c%c%c\n", + monitor_printf(mon, "%016" HWADDR_PRIx "-%016" HWADDR_PRIx " " + "%016" HWADDR_PRIx " %c%c%c\n", addr_canonical(env, *pstart), addr_canonical(env, end), addr_canonical(env, end - *pstart), diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c index c6d1de50fe..e143936ebd 100644 --- a/target/loongarch/tlb_helper.c +++ b/target/loongarch/tlb_helper.c @@ -655,7 +655,7 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size, physical & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); qemu_log_mask(CPU_LOG_MMU, - "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx + "%s address=%" VADDR_PRIx " physical %016" HWADDR_PRIx " prot %d\n", __func__, address, physical, prot); return true; } else { diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 5b745d0928..50d3a202dc 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -403,7 +403,7 @@ void mb_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr, CPUMBState *env = &cpu->env; qemu_log_mask(CPU_LOG_INT, "Transaction failed: vaddr 0x%" VADDR_PRIx - " physaddr 0x" TARGET_FMT_plx " size %d access type %s\n", + " physaddr 0x%016" HWADDR_PRIx " size %d access type %s\n", addr, physaddr, size, access_type == MMU_INST_FETCH ? "INST_FETCH" : (access_type == MMU_DATA_LOAD ? "DATA_LOAD" : "DATA_STORE")); diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index 9d16859c0a..1f572be2b3 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -924,7 +924,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, switch (ret) { case TLBRET_MATCH: qemu_log_mask(CPU_LOG_MMU, - "%s address=%" VADDR_PRIx " physical " TARGET_FMT_plx + "%s address=%" VADDR_PRIx " physical %016" HWADDR_PRIx " prot %d\n", __func__, address, physical, prot); break; default: diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index ad353a86bc..0641b93963 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -346,15 +346,15 @@ static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu, ptem = (vsid << 7) | (pgidx >> 10); /* Page address translation */ - qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx - " htab_mask " TARGET_FMT_plx - " hash " TARGET_FMT_plx "\n", + qemu_log_mask(CPU_LOG_MMU, "htab_base %016" HWADDR_PRIx + " htab_mask %016" HWADDR_PRIx + " hash %016" HWADDR_PRIx "\n", ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), hash); /* Primary PTEG lookup */ - qemu_log_mask(CPU_LOG_MMU, "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, "0 htab=%016" HWADDR_PRIx "/%016" HWADDR_PRIx " vsid=%" PRIx32 " ptem=%" PRIx32 - " hash=" TARGET_FMT_plx "\n", + " hash=%016" HWADDR_PRIx "\n", ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), vsid, ptem, hash); pteg_off = get_pteg_offset32(cpu, hash); @@ -362,9 +362,9 @@ static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu, if (pte_offset == -1) { /* Secondary PTEG lookup */ qemu_log_mask(CPU_LOG_MMU, - "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx + "1 htab=%016" HWADDR_PRIx "/%016" HWADDR_PRIx " vsid=%" PRIx32 " api=%" PRIx32 - " hash=" TARGET_FMT_plx "\n", + " hash=%016" HWADDR_PRIx "\n", ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), vsid, ptem, ~hash); pteg_off = get_pteg_offset32(cpu, ~hash); diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index b9b31fd276..3e4b006d4a 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -697,15 +697,15 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu, /* Page address translation */ qemu_log_mask(CPU_LOG_MMU, - "htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx - " hash " TARGET_FMT_plx "\n", + "htab_base %016" HWADDR_PRIx " htab_mask %016" HWADDR_PRIx + " hash %016" HWADDR_PRIx "\n", ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), hash); /* Primary PTEG lookup */ qemu_log_mask(CPU_LOG_MMU, - "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx + "0 htab=%016" HWADDR_PRIx "/%016" HWADDR_PRIx " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx - " hash=" TARGET_FMT_plx "\n", + " hash=%016" HWADDR_PRIx "\n", ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), vsid, ptem, hash); ptex = ppc_hash64_pteg_search(cpu, hash, sps, ptem, pte, pshift); @@ -714,9 +714,9 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu, /* Secondary PTEG lookup */ ptem |= HPTE64_V_SECONDARY; qemu_log_mask(CPU_LOG_MMU, - "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx + "1 htab=%016" HWADDR_PRIx "/%016" HWADDR_PRIx " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx - " hash=" TARGET_FMT_plx "\n", ppc_hash64_hpt_base(cpu), + " hash=%016" HWADDR_PRIx "\n", ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), vsid, ptem, ~hash); ptex = ppc_hash64_pteg_search(cpu, ~hash, sps, ptem, pte, pshift); diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 94cbb8b6a0..e9d469adeb 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -252,7 +252,7 @@ static int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx, } if (best != -1) { done: - qemu_log_mask(CPU_LOG_MMU, "found TLB at addr " TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, "found TLB at addr %016" HWADDR_PRIx " prot=%01x ret=%d\n", ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); /* Update page flags */ @@ -329,7 +329,7 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, ret = check_prot(ctx->prot, access_type); if (ret == 0) { qemu_log_mask(CPU_LOG_MMU, - "BAT %d match: r " TARGET_FMT_plx + "BAT %d match: r %016" HWADDR_PRIx " prot=%c%c\n", i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', ctx->prot & PAGE_WRITE ? 'W' : '-'); @@ -404,9 +404,9 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, /* Check if instruction fetch is allowed, if needed */ if (type != ACCESS_CODE || ctx->nx == 0) { /* Page address translation */ - qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx - " htab_mask " TARGET_FMT_plx - " hash " TARGET_FMT_plx "\n", + qemu_log_mask(CPU_LOG_MMU, "htab_base %016" HWADDR_PRIx + " htab_mask %016" HWADDR_PRIx + " hash %016" HWADDR_PRIx "\n", ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), hash); ctx->hash[0] = hash; ctx->hash[1] = ~hash; @@ -421,8 +421,8 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, hwaddr curaddr; uint32_t a0, a1, a2, a3; - qemu_log("Page table: " TARGET_FMT_plx - " len " TARGET_FMT_plx "\n", + qemu_log("Page table: %016" HWADDR_PRIx + " len %016" HWADDR_PRIx "\n", ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu) + 0x80); for (curaddr = ppc_hash32_hpt_base(cpu); @@ -434,7 +434,7 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, a2 = ldl_phys(cs->as, curaddr + 8); a3 = ldl_phys(cs->as, curaddr + 12); if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) { - qemu_log(TARGET_FMT_plx ": %08x %08x %08x %08x\n", + qemu_log("%016" HWADDR_PRIx ": %08x %08x %08x %08x\n", curaddr, a0, a1, a2, a3); } } @@ -580,14 +580,14 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, if (ret >= 0) { ctx->raddr = raddr; qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx - " => " TARGET_FMT_plx + " => %016" HWADDR_PRIx " %d %d\n", __func__, address, ctx->raddr, ctx->prot, ret); return 0; } } qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx - " => " TARGET_FMT_plx + " => %016" HWADDR_PRIx " %d %d\n", __func__, address, raddr, ctx->prot, ret); return ret; @@ -668,11 +668,11 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, if (ret >= 0) { ctx->raddr = raddr; qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx - " => " TARGET_FMT_plx " %d %d\n", __func__, + " => %016" HWADDR_PRIx " %d %d\n", __func__, address, ctx->raddr, ctx->prot, ret); } else { qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx - " => " TARGET_FMT_plx " %d %d\n", __func__, + " => %016" HWADDR_PRIx " %d %d\n", __func__, address, raddr, ctx->prot, ret); } @@ -896,11 +896,11 @@ found_tlb: if (ret >= 0) { ctx->raddr = raddr; qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx - " => " TARGET_FMT_plx " %d %d\n", __func__, address, + " => %016" HWADDR_PRIx " %d %d\n", __func__, address, ctx->raddr, ctx->prot, ret); } else { qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx - " => " TARGET_FMT_plx " %d %d\n", __func__, address, + " => %016" HWADDR_PRIx " %d %d\n", __func__, address, raddr, ctx->prot, ret); } diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 2a91f3f46a..3b1230d270 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -826,7 +826,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, tlb->prot &= ~PAGE_VALID; } tlb->PID = env->spr[SPR_40x_PID]; /* PID */ - qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN %016" HWADDR_PRIx " EPN " TARGET_FMT_lx " size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__, (int)entry, tlb->RPN, tlb->EPN, tlb->size, @@ -864,7 +864,7 @@ void helper_4xx_tlbwe_lo(CPUPPCState *env, target_ulong entry, if (val & PPC4XX_TLBLO_WR) { tlb->prot |= PAGE_WRITE; } - qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN " TARGET_FMT_plx + qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN %016" HWADDR_PRIx " EPN " TARGET_FMT_lx " size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__, (int)entry, tlb->RPN, tlb->EPN, tlb->size, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8ea3442b4a..5c45e92b9f 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1272,7 +1272,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " - TARGET_FMT_plx " prot %d\n", + "%016" HWADDR_PRIx " prot %d\n", __func__, address, ret, pa, prot); if (ret == TRANSLATE_SUCCESS) { @@ -1285,7 +1285,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " - TARGET_FMT_plx " prot %d\n", + "%016" HWADDR_PRIx " prot %d\n", __func__, im_address, ret, pa, prot2); prot &= prot2; @@ -1295,7 +1295,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, size, access_type, mode); qemu_log_mask(CPU_LOG_MMU, - "%s PMP address=" TARGET_FMT_plx " ret %d prot" + "%s PMP address=%016" HWADDR_PRIx " ret %d prot" " %d tlb_size " TARGET_FMT_lu "\n", __func__, pa, ret, prot_pmp, tlb_size); @@ -1320,7 +1320,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "%s address=%" VADDR_PRIx " ret %d physical " - TARGET_FMT_plx " prot %d\n", + "%016" HWADDR_PRIx " prot %d\n", __func__, address, ret, pa, prot); if (ret == TRANSLATE_SUCCESS) { @@ -1328,7 +1328,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, size, access_type, mode); qemu_log_mask(CPU_LOG_MMU, - "%s PMP address=" TARGET_FMT_plx " ret %d prot" + "%s PMP address=%016" HWADDR_PRIx " ret %d prot" " %d tlb_size " TARGET_FMT_lu "\n", __func__, pa, ret, prot_pmp, tlb_size); diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index 17e63fab00..81125886fe 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -64,7 +64,7 @@ static void print_pte(Monitor *mon, int va_bits, target_ulong vaddr, return; } - monitor_printf(mon, TARGET_FMT_lx " " TARGET_FMT_plx " " TARGET_FMT_lx + monitor_printf(mon, TARGET_FMT_lx " %016" HWADDR_PRIx " " TARGET_FMT_lx " %c%c%c%c%c%c%c\n", addr_canonical(va_bits, vaddr), paddr, size, diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index ec4fae78c3..91bfb4490e 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -430,12 +430,12 @@ static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, #ifdef DEBUG_UNASSIGNED if (is_asi) { - printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx + printf("Unassigned mem %s access of %d byte%s to %016" HWADDR_PRIx " asi 0x%02x from " TARGET_FMT_lx "\n", is_exec ? "exec" : is_write ? "write" : "read", size, size == 1 ? "" : "s", addr, is_asi, env->pc); } else { - printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx + printf("Unassigned mem %s access of %d byte%s to %016" HWADDR_PRIx " from " TARGET_FMT_lx "\n", is_exec ? "exec" : is_write ? "write" : "read", size, size == 1 ? "" : "s", addr, env->pc); @@ -490,7 +490,7 @@ static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, CPUSPARCState *env = &cpu->env; #ifdef DEBUG_UNASSIGNED - printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx + printf("Unassigned mem access to %016" HWADDR_PRIx " from " TARGET_FMT_lx "\n", addr, env->pc); #endif diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index e3bdb6c3b8..3ded8ff30e 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -230,7 +230,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (likely(error_code == 0)) { qemu_log_mask(CPU_LOG_MMU, "Translate at %" VADDR_PRIx " -> " - TARGET_FMT_plx ", vaddr " TARGET_FMT_lx "\n", + "%016" HWADDR_PRIx ", vaddr " TARGET_FMT_lx "\n", address, paddr, vaddr); tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); return true; @@ -356,20 +356,20 @@ void dump_mmu(CPUSPARCState *env) hwaddr pa; uint32_t pde; - qemu_printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n", + qemu_printf("Root ptr: %016" HWADDR_PRIx ", ctx: %d\n", (hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]); for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { pde = mmu_probe(env, va, 2); if (pde) { pa = cpu_get_phys_page_debug(cs, va); - qemu_printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx + qemu_printf("VA: " TARGET_FMT_lx ", PA: %016" HWADDR_PRIx " PDE: " TARGET_FMT_lx "\n", va, pa, pde); for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { pde = mmu_probe(env, va1, 1); if (pde) { pa = cpu_get_phys_page_debug(cs, va1); qemu_printf(" VA: " TARGET_FMT_lx - ", PA: " TARGET_FMT_plx + ", PA: %016" HWADDR_PRIx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde); for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { @@ -377,7 +377,7 @@ void dump_mmu(CPUSPARCState *env) if (pde) { pa = cpu_get_phys_page_debug(cs, va2); qemu_printf(" VA: " TARGET_FMT_lx ", PA: " - TARGET_FMT_plx " PTE: " + "%016" HWADDR_PRIx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde); } diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 1db32808e8..55a1d780cf 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -79,7 +79,7 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, address, rw, mmu_idx); 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Wed, 11 Jan 2023 00:39:31 -0800 (PST) Received: from localhost.localdomain ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id p21-20020a7bcc95000000b003c65c9a36dfsm17082738wma.48.2023.01.11.00.39.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 11 Jan 2023 00:39:31 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH v2 4/4] bulk: Prefix '0x' to hex values displayed with HWADDR_PRIx format Date: Wed, 11 Jan 2023 09:39:09 +0100 Message-Id: <20230111083909.42624-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230111083909.42624-1-philmd@linaro.org> References: <20230111083909.42624-1-philmd@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 08:39:37 -0000 Automatic change running: $ sed -i -E \ 's/([^0][^x])%016" HWADDR_PRIx/\10x%016" HWADDR_PRIx/g' \ $(git grep -l -F '%016" HWADDR_PRIx') Signed-off-by: Philippe Mathieu-Daudé --- RFC: Maybe some non-0x prefix are justified in some cases, i.e. 'info mtree' output, or generically in monitor output? (see the few monitor_printf calls). --- hw/block/pflash_cfi01.c | 2 +- hw/char/etraxfs_ser.c | 4 ++-- hw/core/loader.c | 4 ++-- hw/core/sysbus.c | 4 ++-- hw/display/g364fb.c | 4 ++-- hw/dma/etraxfs_dma.c | 14 +++++++------- hw/dma/pl330.c | 14 +++++++------- hw/dma/xilinx_axidma.c | 4 ++-- hw/dma/xlnx_csu_dma.c | 4 ++-- hw/i2c/mpc_i2c.c | 4 ++-- hw/i386/multiboot.c | 8 ++++---- hw/i386/xen/xen-hvm.c | 4 ++-- hw/i386/xen/xen-mapcache.c | 16 ++++++++-------- hw/intc/arm_gicv3_dist.c | 8 ++++---- hw/intc/arm_gicv3_its.c | 14 +++++++------- hw/intc/arm_gicv3_redist.c | 8 ++++---- hw/misc/auxbus.c | 2 +- hw/misc/ivshmem.c | 6 +++--- hw/net/rocker/rocker.c | 6 +++--- hw/net/xilinx_axienet.c | 4 ++-- hw/net/xilinx_ethlite.c | 6 +++--- hw/pci-bridge/pci_expander_bridge.c | 2 +- hw/pci-host/bonito.c | 12 ++++++------ hw/pci-host/ppce500.c | 4 ++-- hw/pci/pci_host.c | 4 ++-- hw/ppc/ppc4xx_sdram.c | 2 +- hw/rtc/exynos4210_rtc.c | 4 ++-- hw/ssi/xilinx_spi.c | 4 ++-- hw/ssi/xilinx_spips.c | 8 ++++---- hw/timer/etraxfs_timer.c | 2 +- hw/timer/exynos4210_mct.c | 2 +- hw/timer/exynos4210_pwm.c | 4 ++-- hw/virtio/virtio-mmio.c | 4 ++-- monitor/misc.c | 2 +- softmmu/memory.c | 18 +++++++++--------- softmmu/memory_mapping.c | 4 ++-- softmmu/physmem.c | 10 +++++----- target/i386/monitor.c | 6 +++--- target/loongarch/tlb_helper.c | 2 +- target/mips/tcg/sysemu/tlb_helper.c | 2 +- target/ppc/mmu-hash32.c | 14 +++++++------- target/ppc/mmu-hash64.c | 12 ++++++------ target/ppc/mmu_common.c | 28 ++++++++++++++-------------- target/ppc/mmu_helper.c | 4 ++-- target/riscv/cpu_helper.c | 10 +++++----- target/riscv/monitor.c | 2 +- target/sparc/ldst_helper.c | 6 +++--- target/sparc/mmu_helper.c | 10 +++++----- target/tricore/helper.c | 2 +- 49 files changed, 162 insertions(+), 162 deletions(-) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 20624e3176..ee63c9fa5b 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -645,7 +645,7 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset, error_flash: qemu_log_mask(LOG_UNIMP, "%s: Unimplemented flash cmd sequence " - "(offset %016" HWADDR_PRIx + "(offset 0x%016" HWADDR_PRIx ", wcycle 0x%x cmd 0x%x value 0x%x)\n", __func__, offset, pfl->wcycle, pfl->cmd, value); diff --git a/hw/char/etraxfs_ser.c b/hw/char/etraxfs_ser.c index d79a5b1bf1..407c56c826 100644 --- a/hw/char/etraxfs_ser.c +++ b/hw/char/etraxfs_ser.c @@ -113,7 +113,7 @@ ser_read(void *opaque, hwaddr addr, unsigned int size) break; default: r = s->regs[addr]; - D(qemu_log("%s %016" HWADDR_PRIx "=%x\n", __func__, addr, r)); + D(qemu_log("%s 0x%016" HWADDR_PRIx "=%x\n", __func__, addr, r)); break; } return r; @@ -127,7 +127,7 @@ ser_write(void *opaque, hwaddr addr, uint32_t value = val64; unsigned char ch = val64; - D(qemu_log("%s %016" HWADDR_PRIx "=%x\n", __func__, addr, value)); + D(qemu_log("%s 0x%016" HWADDR_PRIx "=%x\n", __func__, addr, value)); addr >>= 2; switch (addr) { diff --git a/hw/core/loader.c b/hw/core/loader.c index e9cc5a60e8..98eada1e6f 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -1054,7 +1054,7 @@ ssize_t rom_add_file(const char *file, const char *fw_dir, rom->mr = mr; snprintf(devpath, sizeof(devpath), "/rom@%s", file); } else { - snprintf(devpath, sizeof(devpath), "/rom@%016" HWADDR_PRIx, addr); + snprintf(devpath, sizeof(devpath), "/rom@0x%016" HWADDR_PRIx, addr); } } @@ -1595,7 +1595,7 @@ HumanReadableText *qmp_x_query_roms(Error **errp) rom->romsize, rom->name); } else if (!rom->fw_file) { - g_string_append_printf(buf, "addr=%016" HWADDR_PRIx + g_string_append_printf(buf, "addr=0x%016" HWADDR_PRIx " size=0x%06zx mem=%s name=\"%s\"\n", rom->addr, rom->romsize, rom->isrom ? "rom" : "ram", diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c index 5c0099c5eb..a698db3590 100644 --- a/hw/core/sysbus.c +++ b/hw/core/sysbus.c @@ -270,7 +270,7 @@ static void sysbus_dev_print(Monitor *mon, DeviceState *dev, int indent) for (i = 0; i < s->num_mmio; i++) { size = memory_region_size(s->mmio[i].memory); monitor_printf(mon, - "%*smmio %016" HWADDR_PRIx "/%016" HWADDR_PRIx "\n", + "%*smmio 0x%016" HWADDR_PRIx "/0x%016" HWADDR_PRIx "\n", indent, "", s->mmio[i].addr, size); } } @@ -290,7 +290,7 @@ static char *sysbus_get_fw_dev_path(DeviceState *dev) } } if (s->num_mmio) { - return g_strdup_printf("%s@%016" HWADDR_PRIx, qdev_fw_name(dev), + return g_strdup_printf("%s@0x%016" HWADDR_PRIx, qdev_fw_name(dev), s->mmio[0].addr); } if (s->num_pio) { diff --git a/hw/display/g364fb.c b/hw/display/g364fb.c index 7a3065d696..f9f76bb962 100644 --- a/hw/display/g364fb.c +++ b/hw/display/g364fb.c @@ -320,7 +320,7 @@ static uint64_t g364fb_ctrl_read(void *opaque, break; default: { - error_report("g364: invalid read at [%016" HWADDR_PRIx "]", + error_report("g364: invalid read at [0x%016" HWADDR_PRIx "]", addr); val = 0; break; @@ -424,7 +424,7 @@ static void g364fb_ctrl_write(void *opaque, break; default: error_report("g364: invalid write of 0x%" PRIx64 - " at [%016" HWADDR_PRIx "]", val, addr); + " at [0x%016" HWADDR_PRIx "]", val, addr); break; } } diff --git a/hw/dma/etraxfs_dma.c b/hw/dma/etraxfs_dma.c index f69da09143..935bb16dcd 100644 --- a/hw/dma/etraxfs_dma.c +++ b/hw/dma/etraxfs_dma.c @@ -272,7 +272,7 @@ static void channel_load_d(struct fs_dma_ctrl *ctrl, int c) hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA); /* Load and decode. FIXME: handle endianness. */ - D(printf("%s ch=%d addr=%016" HWADDR_PRIx "\n", __func__, c, addr)); + D(printf("%s ch=%d addr=0x%016" HWADDR_PRIx "\n", __func__, c, addr)); cpu_physical_memory_read(addr, &ctrl->channels[c].current_d, sizeof(ctrl->channels[c].current_d)); @@ -285,7 +285,7 @@ static void channel_store_c(struct fs_dma_ctrl *ctrl, int c) hwaddr addr = channel_reg(ctrl, c, RW_GROUP_DOWN); /* Encode and store. FIXME: handle endianness. */ - D(printf("%s ch=%d addr=%016" HWADDR_PRIx "\n", __func__, c, addr)); + D(printf("%s ch=%d addr=0x%016" HWADDR_PRIx "\n", __func__, c, addr)); D(dump_d(c, &ctrl->channels[c].current_d)); cpu_physical_memory_write(addr, &ctrl->channels[c].current_c, sizeof(ctrl->channels[c].current_c)); @@ -296,7 +296,7 @@ static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) hwaddr addr = channel_reg(ctrl, c, RW_SAVED_DATA); /* Encode and store. FIXME: handle endianness. */ - D(printf("%s ch=%d addr=%016" HWADDR_PRIx "\n", __func__, c, addr)); + D(printf("%s ch=%d addr=0x%016" HWADDR_PRIx "\n", __func__, c, addr)); cpu_physical_memory_write(addr, &ctrl->channels[c].current_d, sizeof(ctrl->channels[c].current_d)); } @@ -574,7 +574,7 @@ static inline int channel_in_run(struct fs_dma_ctrl *ctrl, int c) static uint32_t dma_rinvalid (void *opaque, hwaddr addr) { - hw_error("Unsupported short raccess. reg=%016" HWADDR_PRIx "\n", addr); + hw_error("Unsupported short raccess. reg=0x%016" HWADDR_PRIx "\n", addr); return 0; } @@ -601,7 +601,7 @@ static uint64_t dma_read(void *opaque, hwaddr addr, unsigned int size) default: r = ctrl->channels[c].regs[addr]; - D(printf("%s c=%d addr=%016" HWADDR_PRIx "\n", __func__, c, addr)); + D(printf("%s c=%d addr=0x%016" HWADDR_PRIx "\n", __func__, c, addr)); break; } return r; @@ -610,7 +610,7 @@ static uint64_t dma_read(void *opaque, hwaddr addr, unsigned int size) static void dma_winvalid (void *opaque, hwaddr addr, uint32_t value) { - hw_error("Unsupported short waccess. reg=%016" HWADDR_PRIx "\n", addr); + hw_error("Unsupported short waccess. reg=0x%016" HWADDR_PRIx "\n", addr); } static void @@ -681,7 +681,7 @@ static void dma_write(void *opaque, hwaddr addr, uint64_t val64, break; default: - D(printf("%s c=%d %016" HWADDR_PRIx "\n", __func__, c, addr)); + D(printf("%s c=%d 0x%016" HWADDR_PRIx "\n", __func__, c, addr)); break; } } diff --git a/hw/dma/pl330.c b/hw/dma/pl330.c index ba72343c20..90ff54ea34 100644 --- a/hw/dma/pl330.c +++ b/hw/dma/pl330.c @@ -1374,7 +1374,7 @@ static void pl330_iomem_write(void *opaque, hwaddr offset, } else { qemu_log_mask(LOG_GUEST_ERROR, "pl330: write of illegal value %u" - " for offset %016" HWADDR_PRIx "\n", + " for offset 0x%016" HWADDR_PRIx "\n", (unsigned)value, offset); } break; @@ -1386,7 +1386,7 @@ static void pl330_iomem_write(void *opaque, hwaddr offset, break; default: qemu_log_mask(LOG_GUEST_ERROR, - "pl330: bad write offset %016" HWADDR_PRIx "\n", + "pl330: bad write offset 0x%016" HWADDR_PRIx "\n", offset); break; } @@ -1411,7 +1411,7 @@ static inline uint32_t pl330_iomem_read_imp(void *opaque, chan_id = offset >> 5; if (chan_id >= s->num_chnls) { qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " - "%016" HWADDR_PRIx "\n", offset); + "0x%016" HWADDR_PRIx "\n", offset); return 0; } switch (offset & 0x1f) { @@ -1427,7 +1427,7 @@ static inline uint32_t pl330_iomem_read_imp(void *opaque, return s->chan[chan_id].lc[1]; default: qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " - "%016" HWADDR_PRIx "\n", offset); + "0x%016" HWADDR_PRIx "\n", offset); return 0; } } @@ -1436,7 +1436,7 @@ static inline uint32_t pl330_iomem_read_imp(void *opaque, chan_id = offset >> 3; if (chan_id >= s->num_chnls) { qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " - "%016" HWADDR_PRIx "\n", offset); + "0x%016" HWADDR_PRIx "\n", offset); return 0; } switch ((offset >> 2) & 1) { @@ -1458,7 +1458,7 @@ static inline uint32_t pl330_iomem_read_imp(void *opaque, chan_id = offset >> 2; if (chan_id >= s->num_chnls) { qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " - "%016" HWADDR_PRIx "\n", offset); + "0x%016" HWADDR_PRIx "\n", offset); return 0; } return s->chan[chan_id].fault_type; @@ -1497,7 +1497,7 @@ static inline uint32_t pl330_iomem_read_imp(void *opaque, return s->debug_status; default: qemu_log_mask(LOG_GUEST_ERROR, "pl330: bad read offset " - "%016" HWADDR_PRIx "\n", offset); + "0x%016" HWADDR_PRIx "\n", offset); } return 0; } diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index 74ff5ba842..b9081d1fa9 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -456,7 +456,7 @@ static uint64_t axidma_read(void *opaque, hwaddr addr, break; default: r = s->regs[addr]; - D(qemu_log("%s ch=%d addr=%016" HWADDR_PRIx " v=%x\n", + D(qemu_log("%s ch=%d addr=0x%016" HWADDR_PRIx " v=%x\n", __func__, sid, addr * 4, r)); break; } @@ -509,7 +509,7 @@ static void axidma_write(void *opaque, hwaddr addr, } break; default: - D(qemu_log("%s: ch=%d addr=%016" HWADDR_PRIx " v=%x\n", + D(qemu_log("%s: ch=%d addr=0x%016" HWADDR_PRIx " v=%x\n", __func__, sid, addr * 4, (unsigned)value)); s->regs[addr] = value; break; diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c index e2ef8139fc..c590a1f678 100644 --- a/hw/dma/xlnx_csu_dma.c +++ b/hw/dma/xlnx_csu_dma.c @@ -211,7 +211,7 @@ static uint32_t xlnx_csu_dma_read(XlnxCSUDMA *s, uint8_t *buf, uint32_t len) if (result == MEMTX_OK) { xlnx_csu_dma_data_process(s, buf, len); } else { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address %016" HWADDR_PRIx + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%016" HWADDR_PRIx " for mem read", __func__, addr); s->regs[R_INT_STATUS] |= R_INT_STATUS_AXI_BRESP_ERR_MASK; xlnx_csu_dma_update_irq(s); @@ -241,7 +241,7 @@ static uint32_t xlnx_csu_dma_write(XlnxCSUDMA *s, uint8_t *buf, uint32_t len) } if (result != MEMTX_OK) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address %016" HWADDR_PRIx + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address 0x%016" HWADDR_PRIx " for mem write", __func__, addr); s->regs[R_INT_STATUS] |= R_INT_STATUS_AXI_BRESP_ERR_MASK; xlnx_csu_dma_update_irq(s); diff --git a/hw/i2c/mpc_i2c.c b/hw/i2c/mpc_i2c.c index 3e4e185083..4f90b606b5 100644 --- a/hw/i2c/mpc_i2c.c +++ b/hw/i2c/mpc_i2c.c @@ -224,7 +224,7 @@ static uint64_t mpc_i2c_read(void *opaque, hwaddr addr, unsigned size) break; } - DPRINTF("%s: addr %016" HWADDR_PRIx " %02" PRIx32 "\n", __func__, + DPRINTF("%s: addr 0x%016" HWADDR_PRIx " %02" PRIx32 "\n", __func__, addr, value); return (uint64_t)value; } @@ -234,7 +234,7 @@ static void mpc_i2c_write(void *opaque, hwaddr addr, { MPCI2CState *s = opaque; - DPRINTF("%s: addr %016" HWADDR_PRIx " val %08" PRIx64 "\n", __func__, + DPRINTF("%s: addr 0x%016" HWADDR_PRIx " val %08" PRIx64 "\n", __func__, addr, value); switch (addr) { case MPC_I2C_ADR: diff --git a/hw/i386/multiboot.c b/hw/i386/multiboot.c index 31b9abb81b..4ff2179aa4 100644 --- a/hw/i386/multiboot.c +++ b/hw/i386/multiboot.c @@ -137,7 +137,7 @@ static void mb_add_mod(MultibootState *s, stl_p(p + MB_MOD_END, end); stl_p(p + MB_MOD_CMDLINE, cmdline_phys); - mb_debug("mod%02d: %016" HWADDR_PRIx " - %016" HWADDR_PRIx, + mb_debug("mod%02d: 0x%016" HWADDR_PRIx " - 0x%016" HWADDR_PRIx, s->mb_mods_count, start, end); s->mb_mods_count++; @@ -354,7 +354,7 @@ int load_multiboot(X86MachineState *x86ms, mbs.mb_buf_phys + offs + mb_mod_length, c); mb_debug("mod_start: %p\nmod_end: %p\n" - " cmdline: %016" HWADDR_PRIx, + " cmdline: 0x%016" HWADDR_PRIx, (char *)mbs.mb_buf + offs, (char *)mbs.mb_buf + offs + mb_mod_length, c); g_free(one_file); @@ -383,8 +383,8 @@ int load_multiboot(X86MachineState *x86ms, stl_p(bootinfo + MBI_MMAP_ADDR, ADDR_E820_MAP); mb_debug("multiboot: entry_addr = %#x", mh_entry_addr); - mb_debug(" mb_buf_phys = %016" HWADDR_PRIx, mbs.mb_buf_phys); - mb_debug(" mod_start = %016" HWADDR_PRIx, + mb_debug(" mb_buf_phys = 0x%016" HWADDR_PRIx, mbs.mb_buf_phys); + mb_debug(" mod_start = 0x%016" HWADDR_PRIx, mbs.mb_buf_phys + mbs.offset_mods); mb_debug(" mb_mods_count = %d", mbs.mb_mods_count); diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c index 08c44fcd35..e5dc348a9b 100644 --- a/hw/i386/xen/xen-hvm.c +++ b/hw/i386/xen/xen-hvm.c @@ -516,13 +516,13 @@ static void xen_set_memory(struct MemoryListener *listener, if (xen_set_mem_type(xen_domid, mem_type, start_addr >> TARGET_PAGE_BITS, size >> TARGET_PAGE_BITS)) { - DPRINTF("xen_set_mem_type error, addr: %016" HWADDR_PRIx "\n", + DPRINTF("xen_set_mem_type error, addr: 0x%016" HWADDR_PRIx "\n", start_addr); } } } else { if (xen_remove_from_physmap(state, start_addr, size) < 0) { - DPRINTF("physmapping does not exist at %016" HWADDR_PRIx "\n", + DPRINTF("physmapping does not exist at 0x%016" HWADDR_PRIx "\n", start_addr); } } diff --git a/hw/i386/xen/xen-mapcache.c b/hw/i386/xen/xen-mapcache.c index abac16a66a..e8576ad0a6 100644 --- a/hw/i386/xen/xen-mapcache.c +++ b/hw/i386/xen/xen-mapcache.c @@ -358,7 +358,7 @@ tryagain: if (entry->lock == 0) { fprintf(stderr, "mapcache entry lock overflow: " - "%016" HWADDR_PRIx " -> %p\n", + "0x%016" HWADDR_PRIx " -> %p\n", entry->paddr_index, entry->vaddr_base); abort(); } @@ -405,7 +405,7 @@ ram_addr_t xen_ram_addr_from_mapcache(void *ptr) if (!found) { fprintf(stderr, "%s, could not find %p\n", __func__, ptr); QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) { - DPRINTF(" %016" HWADDR_PRIx " -> %p is present\n", + DPRINTF(" 0x%016" HWADDR_PRIx " -> %p is present\n", reventry->paddr_index, reventry->vaddr_req); } abort(); @@ -446,7 +446,7 @@ static void xen_invalidate_map_cache_entry_unlocked(uint8_t *buffer) if (!found) { DPRINTF("%s, could not find %p\n", __func__, buffer); QTAILQ_FOREACH(reventry, &mapcache->locked_entries, next) { - DPRINTF(" %016" HWADDR_PRIx " -> %p is present\n", + DPRINTF(" 0x%016" HWADDR_PRIx " -> %p is present\n", reventry->paddr_index, reventry->vaddr_req); } return; @@ -505,7 +505,7 @@ void xen_invalidate_map_cache(void) continue; } fprintf(stderr, "Locked DMA mapping while invalidating mapcache!" - " %016" HWADDR_PRIx " -> %p is present\n", + " 0x%016" HWADDR_PRIx " -> %p is present\n", reventry->paddr_index, reventry->vaddr_req); } @@ -564,7 +564,7 @@ static uint8_t *xen_replace_cache_entry_unlocked(hwaddr old_phys_addr, entry = entry->next; } if (!entry) { - DPRINTF("Trying to update an entry for %016" HWADDR_PRIx \ + DPRINTF("Trying to update an entry for 0x%016" HWADDR_PRIx \ "that is not in the mapcache!\n", old_phys_addr); return NULL; } @@ -572,8 +572,8 @@ static uint8_t *xen_replace_cache_entry_unlocked(hwaddr old_phys_addr, address_index = new_phys_addr >> MCACHE_BUCKET_SHIFT; address_offset = new_phys_addr & (MCACHE_BUCKET_SIZE - 1); - fprintf(stderr, "Replacing a dummy mapcache entry for %016" HWADDR_PRIx \ - " with %016" HWADDR_PRIx "\n", old_phys_addr, new_phys_addr); + fprintf(stderr, "Replacing a dummy mapcache entry for 0x%016" HWADDR_PRIx \ + " with 0x%016" HWADDR_PRIx "\n", old_phys_addr, new_phys_addr); xen_remap_bucket(entry, entry->vaddr_base, cache_size, address_index, false); @@ -581,7 +581,7 @@ static uint8_t *xen_replace_cache_entry_unlocked(hwaddr old_phys_addr, test_bit_size >> XC_PAGE_SHIFT, entry->valid_mapping)) { DPRINTF("Unable to update a mapcache entry for " - "%016" HWADDR_PRIx "!\n", + "0x%016" HWADDR_PRIx "!\n", old_phys_addr); return NULL; } diff --git a/hw/intc/arm_gicv3_dist.c b/hw/intc/arm_gicv3_dist.c index d827f08bcf..9e43e35120 100644 --- a/hw/intc/arm_gicv3_dist.c +++ b/hw/intc/arm_gicv3_dist.c @@ -564,7 +564,7 @@ static bool gicd_readl(GICv3State *s, hwaddr offset, /* WO registers, return unknown value */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest read from WO register at offset " - "%016" HWADDR_PRIx "\n", __func__, offset); + "0x%016" HWADDR_PRIx "\n", __func__, offset); *data = 0; return true; default: @@ -773,7 +773,7 @@ static bool gicd_writel(GICv3State *s, hwaddr offset, /* RO registers, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - "%016" HWADDR_PRIx "\n", __func__, offset); + "0x%016" HWADDR_PRIx "\n", __func__, offset); return true; default: return false; @@ -838,7 +838,7 @@ MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data, if (!r) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid guest read at offset %016" HWADDR_PRIx + "%s: invalid guest read at offset 0x%016" HWADDR_PRIx " size %u\n", __func__, offset, size); trace_gicv3_dist_badread(offset, size, attrs.secure); /* The spec requires that reserved registers are RAZ/WI; @@ -879,7 +879,7 @@ MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data, if (!r) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid guest write at offset %016" HWADDR_PRIx + "%s: invalid guest write at offset 0x%016" HWADDR_PRIx " size %u\n", __func__, offset, size); trace_gicv3_dist_badwrite(offset, data, size, attrs.secure); /* The spec requires that reserved registers are RAZ/WI; diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index ec398b5eb1..0a7f3a318e 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -1633,7 +1633,7 @@ static bool its_writel(GICv3ITSState *s, hwaddr offset, /* RO register, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - "%016" HWADDR_PRIx "\n", __func__, offset); + "0x%016" HWADDR_PRIx "\n", __func__, offset); } break; case GITS_CREADR + 4: @@ -1643,7 +1643,7 @@ static bool its_writel(GICv3ITSState *s, hwaddr offset, /* RO register, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - "%016" HWADDR_PRIx "\n", __func__, offset); + "0x%016" HWADDR_PRIx "\n", __func__, offset); } break; case GITS_BASER ... GITS_BASER + 0x3f: @@ -1675,7 +1675,7 @@ static bool its_writel(GICv3ITSState *s, hwaddr offset, /* RO registers, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - "%016" HWADDR_PRIx "\n", __func__, offset); + "0x%016" HWADDR_PRIx "\n", __func__, offset); break; default: result = false; @@ -1785,14 +1785,14 @@ static bool its_writell(GICv3ITSState *s, hwaddr offset, /* RO register, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - "%016" HWADDR_PRIx "\n", __func__, offset); + "0x%016" HWADDR_PRIx "\n", __func__, offset); } break; case GITS_TYPER: /* RO registers, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - "%016" HWADDR_PRIx "\n", __func__, offset); + "0x%016" HWADDR_PRIx "\n", __func__, offset); break; default: result = false; @@ -1851,7 +1851,7 @@ static MemTxResult gicv3_its_read(void *opaque, hwaddr offset, uint64_t *data, if (!result) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid guest read at offset %016" HWADDR_PRIx + "%s: invalid guest read at offset 0x%016" HWADDR_PRIx " size %u\n", __func__, offset, size); trace_gicv3_its_badread(offset, size); /* @@ -1887,7 +1887,7 @@ static MemTxResult gicv3_its_write(void *opaque, hwaddr offset, uint64_t data, if (!result) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid guest write at offset %016" HWADDR_PRIx + "%s: invalid guest write at offset 0x%016" HWADDR_PRIx " size %u\n", __func__, offset, size); trace_gicv3_its_badwrite(offset, data, size); /* diff --git a/hw/intc/arm_gicv3_redist.c b/hw/intc/arm_gicv3_redist.c index b59171735c..d889472db1 100644 --- a/hw/intc/arm_gicv3_redist.c +++ b/hw/intc/arm_gicv3_redist.c @@ -601,7 +601,7 @@ static MemTxResult gicr_writel(GICv3CPUState *cs, hwaddr offset, /* RO registers, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - "%016" HWADDR_PRIx "\n", __func__, offset); + "0x%016" HWADDR_PRIx "\n", __func__, offset); return MEMTX_OK; /* * VLPI frame registers. We don't need a version check for @@ -668,7 +668,7 @@ static MemTxResult gicr_writell(GICv3CPUState *cs, hwaddr offset, /* RO register, ignore the write */ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid guest write to RO register at offset " - "%016" HWADDR_PRIx "\n", __func__, offset); + "0x%016" HWADDR_PRIx "\n", __func__, offset); return MEMTX_OK; /* * VLPI frame registers. We don't need a version check for @@ -727,7 +727,7 @@ MemTxResult gicv3_redist_read(void *opaque, hwaddr offset, uint64_t *data, if (r != MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid guest read at offset %016" HWADDR_PRIx + "%s: invalid guest read at offset 0x%016" HWADDR_PRIx " size %u\n", __func__, offset, size); trace_gicv3_redist_badread(gicv3_redist_affid(cs), offset, size, attrs.secure); @@ -786,7 +786,7 @@ MemTxResult gicv3_redist_write(void *opaque, hwaddr offset, uint64_t data, if (r != MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid guest write at offset %016" HWADDR_PRIx + "%s: invalid guest write at offset 0x%016" HWADDR_PRIx " size %u\n", __func__, offset, size); trace_gicv3_redist_badwrite(gicv3_redist_affid(cs), offset, data, size, attrs.secure); diff --git a/hw/misc/auxbus.c b/hw/misc/auxbus.c index 014a30f5a1..f075593666 100644 --- a/hw/misc/auxbus.c +++ b/hw/misc/auxbus.c @@ -300,7 +300,7 @@ static void aux_slave_dev_print(Monitor *mon, DeviceState *dev, int indent) s = AUX_SLAVE(dev); monitor_printf(mon, - "%*smemory %016" HWADDR_PRIx "/%016" HWADDR_PRIx "\n", + "%*smemory 0x%016" HWADDR_PRIx "/0x%016" HWADDR_PRIx "\n", indent, "", object_property_get_uint(OBJECT(s->mmio), "addr", NULL), memory_region_size(s->mmio)); diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c index ee41b90018..2ea2fca362 100644 --- a/hw/misc/ivshmem.c +++ b/hw/misc/ivshmem.c @@ -179,7 +179,7 @@ static void ivshmem_io_write(void *opaque, hwaddr addr, addr &= 0xfc; - IVSHMEM_DPRINTF("writing to addr %016" HWADDR_PRIx "\n", addr); + IVSHMEM_DPRINTF("writing to addr 0x%016" HWADDR_PRIx "\n", addr); switch (addr) { case INTRMASK: @@ -207,7 +207,7 @@ static void ivshmem_io_write(void *opaque, hwaddr addr, } break; default: - IVSHMEM_DPRINTF("Unhandled write %016" HWADDR_PRIx "\n", addr); + IVSHMEM_DPRINTF("Unhandled write 0x%016" HWADDR_PRIx "\n", addr); } } @@ -233,7 +233,7 @@ static uint64_t ivshmem_io_read(void *opaque, hwaddr addr, break; default: - IVSHMEM_DPRINTF("why are we reading %016" HWADDR_PRIx "\n", addr); + IVSHMEM_DPRINTF("why are we reading 0x%016" HWADDR_PRIx "\n", addr); ret = 0; } diff --git a/hw/net/rocker/rocker.c b/hw/net/rocker/rocker.c index 0d41dd52a2..f88b74bb8a 100644 --- a/hw/net/rocker/rocker.c +++ b/hw/net/rocker/rocker.c @@ -987,8 +987,8 @@ static const char *rocker_reg_name(void *opaque, hwaddr addr) static void rocker_mmio_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - DPRINTF("Write %s addr %016" HWADDR_PRIx - ", size %u, val %016" HWADDR_PRIx "\n", + DPRINTF("Write %s addr 0x%016" HWADDR_PRIx + ", size %u, val 0x%016" HWADDR_PRIx "\n", rocker_reg_name(opaque, addr), addr, size, val); switch (size) { @@ -1174,7 +1174,7 @@ static uint64_t rocker_io_readq(void *opaque, hwaddr addr) static uint64_t rocker_mmio_read(void *opaque, hwaddr addr, unsigned size) { - DPRINTF("Read %s addr %016" HWADDR_PRIx ", size %u\n", + DPRINTF("Read %s addr 0x%016" HWADDR_PRIx ", size %u\n", rocker_reg_name(opaque, addr), addr, size); switch (size) { diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index 814b71a93c..54b37b9e67 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -524,7 +524,7 @@ static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size) if (addr < ARRAY_SIZE(s->regs)) { r = s->regs[addr]; } - DENET(qemu_log("%s addr=%016" HWADDR_PRIx " v=%x\n", + DENET(qemu_log("%s addr=0x%016" HWADDR_PRIx " v=%x\n", __func__, addr * 4, r)); break; } @@ -630,7 +630,7 @@ static void enet_write(void *opaque, hwaddr addr, break; default: - DENET(qemu_log("%s addr=%016" HWADDR_PRIx " v=%x\n", + DENET(qemu_log("%s addr=0x%016" HWADDR_PRIx " v=%x\n", __func__, addr * 4, (unsigned)value)); if (addr < ARRAY_SIZE(s->regs)) { s->regs[addr] = value; diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 150248e543..7347e36ed8 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -99,7 +99,7 @@ eth_read(void *opaque, hwaddr addr, unsigned int size) case R_RX_CTRL1: case R_RX_CTRL0: r = s->regs[addr]; - D(qemu_log("%s %016" HWADDR_PRIx "=%x\n", __func__, addr * 4, r)); + D(qemu_log("%s 0x%016" HWADDR_PRIx "=%x\n", __func__, addr * 4, r)); break; default: @@ -125,7 +125,7 @@ eth_write(void *opaque, hwaddr addr, if (addr == R_TX_CTRL1) base = 0x800 / 4; - D(qemu_log("%s addr=%016" HWADDR_PRIx " val=%x\n", + D(qemu_log("%s addr=0x%016" HWADDR_PRIx " val=%x\n", __func__, addr * 4, value)); if ((value & (CTRL_P | CTRL_S)) == CTRL_S) { qemu_send_packet(qemu_get_queue(s->nic), @@ -155,7 +155,7 @@ eth_write(void *opaque, hwaddr addr, case R_TX_LEN0: case R_TX_LEN1: case R_TX_GIE0: - D(qemu_log("%s addr=%016" HWADDR_PRIx " val=%x\n", + D(qemu_log("%s addr=0x%016" HWADDR_PRIx " val=%x\n", __func__, addr * 4, value)); s->regs[addr] = value; break; diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c index 16b427d3c1..9b535d4843 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -155,7 +155,7 @@ static char *pxb_host_ofw_unit_address(const SysBusDevice *dev) main_host_sbd = SYS_BUS_DEVICE(main_host); if (main_host_sbd->num_mmio > 0) { - return g_strdup_printf("%016" HWADDR_PRIx ",%x", + return g_strdup_printf("0x%016" HWADDR_PRIx ",%x", main_host_sbd->mmio[0].addr, position + 1); } if (main_host_sbd->num_pio > 0) { diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c index 2d54435f74..42312cde8f 100644 --- a/hw/pci-host/bonito.c +++ b/hw/pci-host/bonito.c @@ -254,7 +254,7 @@ static void bonito_writel(void *opaque, hwaddr addr, saddr = addr >> 2; - DPRINTF("bonito_writel %016" HWADDR_PRIx " val %lx saddr %x\n", + DPRINTF("bonito_writel 0x%016" HWADDR_PRIx " val %lx saddr %x\n", addr, val, saddr); switch (saddr) { case BONITO_BONPONCFG: @@ -317,7 +317,7 @@ static uint64_t bonito_readl(void *opaque, hwaddr addr, saddr = addr >> 2; - DPRINTF("bonito_readl %016" HWADDR_PRIx "\n", addr); + DPRINTF("bonito_readl 0x%016" HWADDR_PRIx "\n", addr); switch (saddr) { case BONITO_INTISR: return s->regs[saddr]; @@ -342,7 +342,7 @@ static void bonito_pciconf_writel(void *opaque, hwaddr addr, PCIBonitoState *s = opaque; PCIDevice *d = PCI_DEVICE(s); - DPRINTF("bonito_pciconf_writel %016" HWADDR_PRIx " val %lx\n", addr, val); + DPRINTF("bonito_pciconf_writel 0x%016" HWADDR_PRIx " val %lx\n", addr, val); d->config_write(d, addr, val, 4); } @@ -353,7 +353,7 @@ static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr, PCIBonitoState *s = opaque; PCIDevice *d = PCI_DEVICE(s); - DPRINTF("bonito_pciconf_readl %016" HWADDR_PRIx "\n", addr); + DPRINTF("bonito_pciconf_readl 0x%016" HWADDR_PRIx "\n", addr); return d->config_read(d, addr, 4); } @@ -489,7 +489,7 @@ static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val, uint32_t pciaddr; uint16_t status; - DPRINTF("bonito_spciconf_write %016" HWADDR_PRIx " size %d val %lx\n", + DPRINTF("bonito_spciconf_write 0x%016" HWADDR_PRIx " size %d val %lx\n", addr, size, val); pciaddr = bonito_sbridge_pciaddr(s, addr); @@ -519,7 +519,7 @@ static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size) uint32_t pciaddr; uint16_t status; - DPRINTF("bonito_spciconf_read %016" HWADDR_PRIx " size %d\n", addr, size); + DPRINTF("bonito_spciconf_read 0x%016" HWADDR_PRIx " size %d\n", addr, size); pciaddr = bonito_sbridge_pciaddr(s, addr); diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c index b522da730c..e68e72d76b 100644 --- a/hw/pci-host/ppce500.c +++ b/hw/pci-host/ppce500.c @@ -189,7 +189,7 @@ static uint64_t pci_reg_read4(void *opaque, hwaddr addr, break; } - pci_debug("%s: win:%lx(addr:%016" HWADDR_PRIx ") -> value:%x\n", __func__, + pci_debug("%s: win:%lx(addr:0x%016" HWADDR_PRIx ") -> value:%x\n", __func__, win, addr, value); return value; } @@ -268,7 +268,7 @@ static void pci_reg_write4(void *opaque, hwaddr addr, win = addr & 0xfe0; - pci_debug("%s: value:%x -> win:%lx(addr:%016" HWADDR_PRIx ")\n", + pci_debug("%s: value:%x -> win:%lx(addr:0x%016" HWADDR_PRIx ")\n", __func__, (unsigned)value, win, addr); switch (win) { diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c index efb1a9d901..870cb0f935 100644 --- a/hw/pci/pci_host.c +++ b/hw/pci/pci_host.c @@ -143,7 +143,7 @@ static void pci_host_config_write(void *opaque, hwaddr addr, { PCIHostState *s = opaque; - PCI_DPRINTF("%s addr %016" HWADDR_PRIx " len %d val %"PRIx64"\n", + PCI_DPRINTF("%s addr 0x%016" HWADDR_PRIx " len %d val %"PRIx64"\n", __func__, addr, len, val); if (addr != 0 || len != 4) { return; @@ -157,7 +157,7 @@ static uint64_t pci_host_config_read(void *opaque, hwaddr addr, PCIHostState *s = opaque; uint32_t val = s->config_reg; - PCI_DPRINTF("%s addr %016" HWADDR_PRIx " len %d val %"PRIx32"\n", + PCI_DPRINTF("%s addr 0x%016" HWADDR_PRIx " len %d val %"PRIx32"\n", __func__, addr, len, val); return val; } diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c index b306683cfb..a42d72cddd 100644 --- a/hw/ppc/ppc4xx_sdram.c +++ b/hw/ppc/ppc4xx_sdram.c @@ -500,7 +500,7 @@ static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size) bcr = 0x8000; break; default: - error_report("invalid RAM size %016" HWADDR_PRIx, ram_size); + error_report("invalid RAM size 0x%016" HWADDR_PRIx, ram_size); return 0; } bcr |= ram_base >> 2 & 0xffe00000; diff --git a/hw/rtc/exynos4210_rtc.c b/hw/rtc/exynos4210_rtc.c index 1ec3b20501..c25beba5ba 100644 --- a/hw/rtc/exynos4210_rtc.c +++ b/hw/rtc/exynos4210_rtc.c @@ -374,7 +374,7 @@ static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset, default: qemu_log_mask(LOG_GUEST_ERROR, - "exynos4210.rtc: bad read offset %016" HWADDR_PRIx, + "exynos4210.rtc: bad read offset 0x%016" HWADDR_PRIx, offset); break; } @@ -508,7 +508,7 @@ static void exynos4210_rtc_write(void *opaque, hwaddr offset, default: qemu_log_mask(LOG_GUEST_ERROR, - "exynos4210.rtc: bad write offset %016" HWADDR_PRIx, + "exynos4210.rtc: bad write offset 0x%016" HWADDR_PRIx, offset); break; diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c index be4a40f0ca..b5db70daad 100644 --- a/hw/ssi/xilinx_spi.c +++ b/hw/ssi/xilinx_spi.c @@ -232,7 +232,7 @@ spi_read(void *opaque, hwaddr addr, unsigned int size) break; } - DB_PRINT("addr=%016" HWADDR_PRIx " = %x\n", addr * 4, r); + DB_PRINT("addr=0x%016" HWADDR_PRIx " = %x\n", addr * 4, r); xlx_spi_update_irq(s); return r; } @@ -244,7 +244,7 @@ spi_write(void *opaque, hwaddr addr, XilinxSPI *s = opaque; uint32_t value = val64; - DB_PRINT("addr=%016" HWADDR_PRIx " = %x\n", addr, value); + DB_PRINT("addr=0x%016" HWADDR_PRIx " = %x\n", addr, value); addr >>= 2; switch (addr) { case R_SRR: diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 8b7e715c74..4fa7d25eb0 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -887,7 +887,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, case R_INTR_STATUS: ret = s->regs[addr] & IXR_ALL; s->regs[addr] = 0; - DB_PRINT_L(0, "addr=%016" HWADDR_PRIx " = %x\n", addr * 4, ret); + DB_PRINT_L(0, "addr=0x%016" HWADDR_PRIx " = %x\n", addr * 4, ret); xilinx_spips_update_ixr(s); return ret; case R_INTR_MASK: @@ -916,12 +916,12 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, if (!(s->regs[R_CONFIG] & R_CONFIG_ENDIAN)) { ret <<= 8 * shortfall; } - DB_PRINT_L(0, "addr=%016" HWADDR_PRIx " = %x\n", addr * 4, ret); + DB_PRINT_L(0, "addr=0x%016" HWADDR_PRIx " = %x\n", addr * 4, ret); xilinx_spips_check_flush(s); xilinx_spips_update_ixr(s); return ret; } - DB_PRINT_L(0, "addr=%016" HWADDR_PRIx " = %x\n", addr * 4, + DB_PRINT_L(0, "addr=0x%016" HWADDR_PRIx " = %x\n", addr * 4, s->regs[addr] & mask); return s->regs[addr] & mask; @@ -971,7 +971,7 @@ static void xilinx_spips_write(void *opaque, hwaddr addr, XilinxSPIPS *s = opaque; bool try_flush = true; - DB_PRINT_L(0, "addr=%016" HWADDR_PRIx " = %x\n", addr, (unsigned)value); + DB_PRINT_L(0, "addr=0x%016" HWADDR_PRIx " = %x\n", addr, (unsigned)value); addr >>= 2; switch (addr) { case R_CONFIG: diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c index 782a370159..324e2d1a0c 100644 --- a/hw/timer/etraxfs_timer.c +++ b/hw/timer/etraxfs_timer.c @@ -324,7 +324,7 @@ timer_write(void *opaque, hwaddr addr, t->rw_ack_intr = 0; break; default: - printf("%s %016" HWADDR_PRIx " %x\n", __func__, addr, value); + printf("%s 0x%016" HWADDR_PRIx " %x\n", __func__, addr, value); break; } } diff --git a/hw/timer/exynos4210_mct.c b/hw/timer/exynos4210_mct.c index 5f5d53c009..4a86c89310 100644 --- a/hw/timer/exynos4210_mct.c +++ b/hw/timer/exynos4210_mct.c @@ -1445,7 +1445,7 @@ static void exynos4210_mct_write(void *opaque, hwaddr offset, case L0_ICNTO: case L1_ICNTO: case L0_FRCNTO: case L1_FRCNTO: qemu_log_mask(LOG_GUEST_ERROR, - "exynos4210.mct: write to RO register %016" HWADDR_PRIx, + "exynos4210.mct: write to RO register 0x%016" HWADDR_PRIx, offset); break; diff --git a/hw/timer/exynos4210_pwm.c b/hw/timer/exynos4210_pwm.c index a4ac44e150..cfdf93949d 100644 --- a/hw/timer/exynos4210_pwm.c +++ b/hw/timer/exynos4210_pwm.c @@ -257,7 +257,7 @@ static uint64_t exynos4210_pwm_read(void *opaque, hwaddr offset, default: qemu_log_mask(LOG_GUEST_ERROR, - "exynos4210.pwm: bad read offset %016" HWADDR_PRIx, + "exynos4210.pwm: bad read offset 0x%016" HWADDR_PRIx, offset); break; } @@ -352,7 +352,7 @@ static void exynos4210_pwm_write(void *opaque, hwaddr offset, default: qemu_log_mask(LOG_GUEST_ERROR, - "exynos4210.pwm: bad write offset %016" HWADDR_PRIx, + "exynos4210.pwm: bad write offset 0x%016" HWADDR_PRIx, offset); break; diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c index c90f620802..9040ce5bef 100644 --- a/hw/virtio/virtio-mmio.c +++ b/hw/virtio/virtio-mmio.c @@ -829,10 +829,10 @@ static char *virtio_mmio_bus_get_dev_path(DeviceState *dev) assert(section.mr); if (proxy_path) { - path = g_strdup_printf("%s/virtio-mmio@%016" HWADDR_PRIx, proxy_path, + path = g_strdup_printf("%s/virtio-mmio@0x%016" HWADDR_PRIx, proxy_path, section.offset_within_address_space); } else { - path = g_strdup_printf("virtio-mmio@%016" HWADDR_PRIx, + path = g_strdup_printf("virtio-mmio@0x%016" HWADDR_PRIx, section.offset_within_address_space); } memory_region_unref(section.mr); diff --git a/monitor/misc.c b/monitor/misc.c index 9861ec2905..96370900db 100644 --- a/monitor/misc.c +++ b/monitor/misc.c @@ -566,7 +566,7 @@ static void memory_dump(Monitor *mon, int count, int format, int wsize, while (len > 0) { if (is_physical) { - monitor_printf(mon, "%016" HWADDR_PRIx ":", addr); + monitor_printf(mon, "0x%016" HWADDR_PRIx ":", addr); } else { monitor_printf(mon, TARGET_FMT_lx ":", (target_ulong)addr); } diff --git a/softmmu/memory.c b/softmmu/memory.c index 14850d4d3c..3c91e98df8 100644 --- a/softmmu/memory.c +++ b/softmmu/memory.c @@ -1281,7 +1281,7 @@ static uint64_t unassigned_mem_read(void *opaque, hwaddr addr, unsigned size) { #ifdef DEBUG_UNASSIGNED - printf("Unassigned mem read %016" HWADDR_PRIx "\n", addr); + printf("Unassigned mem read 0x%016" HWADDR_PRIx "\n", addr); #endif return 0; } @@ -1290,7 +1290,7 @@ static void unassigned_mem_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { #ifdef DEBUG_UNASSIGNED - printf("Unassigned mem write %016" HWADDR_PRIx " = 0x%"PRIx64"\n", + printf("Unassigned mem write 0x%016" HWADDR_PRIx " = 0x%"PRIx64"\n", addr, val); #endif } @@ -3221,9 +3221,9 @@ static void mtree_print_mr(const MemoryRegion *mr, unsigned int level, for (i = 0; i < level; i++) { qemu_printf(MTREE_INDENT); } - qemu_printf("%016" HWADDR_PRIx "-%016" HWADDR_PRIx - " (prio %d, %s%s): alias %s @%s %016" HWADDR_PRIx - "-%016" HWADDR_PRIx "%s", + qemu_printf("0x%016" HWADDR_PRIx "-0x%016" HWADDR_PRIx + " (prio %d, %s%s): alias %s @%s 0x%016" HWADDR_PRIx + "-0x%016" HWADDR_PRIx "%s", cur_start, cur_end, mr->priority, mr->nonvolatile ? "nv-" : "", @@ -3243,7 +3243,7 @@ static void mtree_print_mr(const MemoryRegion *mr, unsigned int level, for (i = 0; i < level; i++) { qemu_printf(MTREE_INDENT); } - qemu_printf("%016" HWADDR_PRIx "-%016" HWADDR_PRIx + qemu_printf("0x%016" HWADDR_PRIx "-0x%016" HWADDR_PRIx " (prio %d, %s%s): %s%s", cur_start, cur_end, mr->priority, @@ -3330,8 +3330,8 @@ static void mtree_print_flatview(gpointer key, gpointer value, while (n--) { mr = range->mr; if (range->offset_in_region) { - qemu_printf(MTREE_INDENT "%016" HWADDR_PRIx "-%016" HWADDR_PRIx - " (prio %d, %s%s): %s @%016" HWADDR_PRIx, + qemu_printf(MTREE_INDENT "0x%016" HWADDR_PRIx "-0x%016" HWADDR_PRIx + " (prio %d, %s%s): %s @0x%016" HWADDR_PRIx, int128_get64(range->addr.start), int128_get64(range->addr.start) + MR_SIZE(range->addr.size), @@ -3341,7 +3341,7 @@ static void mtree_print_flatview(gpointer key, gpointer value, memory_region_name(mr), range->offset_in_region); } else { - qemu_printf(MTREE_INDENT "%016" HWADDR_PRIx "-%016" HWADDR_PRIx + qemu_printf(MTREE_INDENT "0x%016" HWADDR_PRIx "-0x%016" HWADDR_PRIx " (prio %d, %s%s): %s", int128_get64(range->addr.start), int128_get64(range->addr.start) diff --git a/softmmu/memory_mapping.c b/softmmu/memory_mapping.c index c82c896a68..413b013c47 100644 --- a/softmmu/memory_mapping.c +++ b/softmmu/memory_mapping.c @@ -241,8 +241,8 @@ static void guest_phys_block_add_section(GuestPhysListener *g, } #ifdef DEBUG_GUEST_PHYS_REGION_ADD - fprintf(stderr, "%s: target_start=%016" HWADDR_PRIx " target_end=" - "%016" HWADDR_PRIx ": %s (count: %u)\n", __func__, target_start, + fprintf(stderr, "%s: target_start=0x%016" HWADDR_PRIx " target_end=" + "0x%016" HWADDR_PRIx ": %s (count: %u)\n", __func__, target_start, target_end, predecessor ? "joined" : "added", g->list->num); #endif } diff --git a/softmmu/physmem.c b/softmmu/physmem.c index f8e094dfef..b85b0037be 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -2475,7 +2475,7 @@ static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data, MemTxResult res; #if defined(DEBUG_SUBPAGE) - printf("%s: subpage %p len %u addr %016" HWADDR_PRIx "\n", __func__, + printf("%s: subpage %p len %u addr 0x%016" HWADDR_PRIx "\n", __func__, subpage, len, addr); #endif res = flatview_read(subpage->fv, addr + subpage->base, attrs, buf, len); @@ -2493,7 +2493,7 @@ static MemTxResult subpage_write(void *opaque, hwaddr addr, uint8_t buf[8]; #if defined(DEBUG_SUBPAGE) - printf("%s: subpage %p len %u addr %016" HWADDR_PRIx + printf("%s: subpage %p len %u addr 0x%016" HWADDR_PRIx " value %"PRIx64"\n", __func__, subpage, len, addr, value); #endif @@ -2507,7 +2507,7 @@ static bool subpage_accepts(void *opaque, hwaddr addr, { subpage_t *subpage = opaque; #if defined(DEBUG_SUBPAGE) - printf("%s: subpage %p %c len %u addr %016" HWADDR_PRIx "\n", + printf("%s: subpage %p %c len %u addr 0x%016" HWADDR_PRIx "\n", __func__, subpage, is_write ? 'w' : 'r', len, addr); #endif @@ -2558,7 +2558,7 @@ static subpage_t *subpage_init(FlatView *fv, hwaddr base) NULL, TARGET_PAGE_SIZE); mmio->iomem.subpage = true; #if defined(DEBUG_SUBPAGE) - printf("%s: %p base %016" HWADDR_PRIx " len %08x\n", __func__, + printf("%s: %p base 0x%016" HWADDR_PRIx " len %08x\n", __func__, mmio, base, TARGET_PAGE_SIZE); #endif @@ -3703,7 +3703,7 @@ void mtree_print_dispatch(AddressSpaceDispatch *d, MemoryRegion *root) const char *names[] = { " [unassigned]", " [not dirty]", " [ROM]", " [watch]" }; - qemu_printf(" #%d @%016" HWADDR_PRIx "..%016" HWADDR_PRIx + qemu_printf(" #%d @0x%016" HWADDR_PRIx "..0x%016" HWADDR_PRIx " %s%s%s%s%s", i, s->offset_within_address_space, diff --git a/target/i386/monitor.c b/target/i386/monitor.c index 59b7a814ea..d8e7af89f8 100644 --- a/target/i386/monitor.c +++ b/target/i386/monitor.c @@ -57,7 +57,7 @@ static void print_pte(Monitor *mon, CPUArchState *env, hwaddr addr, { addr = addr_canonical(env, addr); - monitor_printf(mon, "%016" HWADDR_PRIx ": %016" HWADDR_PRIx + monitor_printf(mon, "0x%016" HWADDR_PRIx ": 0x%016" HWADDR_PRIx " %c%c%c%c%c%c%c%c%c\n", addr, pte & mask, @@ -258,8 +258,8 @@ static void mem_print(Monitor *mon, CPUArchState *env, prot1 = *plast_prot; if (prot != prot1) { if (*pstart != -1) { - monitor_printf(mon, "%016" HWADDR_PRIx "-%016" HWADDR_PRIx " " - "%016" HWADDR_PRIx " %c%c%c\n", + monitor_printf(mon, "0x%016" HWADDR_PRIx "-0x%016" HWADDR_PRIx " " + "0x%016" HWADDR_PRIx " %c%c%c\n", addr_canonical(env, *pstart), addr_canonical(env, end), addr_canonical(env, end - *pstart), diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c index e143936ebd..9ccc2fa667 100644 --- a/target/loongarch/tlb_helper.c +++ b/target/loongarch/tlb_helper.c @@ -655,7 +655,7 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size, physical & TARGET_PAGE_MASK, prot, mmu_idx, TARGET_PAGE_SIZE); qemu_log_mask(CPU_LOG_MMU, - "%s address=%" VADDR_PRIx " physical %016" HWADDR_PRIx + "%s address=%" VADDR_PRIx " physical 0x%016" HWADDR_PRIx " prot %d\n", __func__, address, physical, prot); return true; } else { diff --git a/target/mips/tcg/sysemu/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index 1f572be2b3..5cbf73940a 100644 --- a/target/mips/tcg/sysemu/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -924,7 +924,7 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, switch (ret) { case TLBRET_MATCH: qemu_log_mask(CPU_LOG_MMU, - "%s address=%" VADDR_PRIx " physical %016" HWADDR_PRIx + "%s address=%" VADDR_PRIx " physical 0x%016" HWADDR_PRIx " prot %d\n", __func__, address, physical, prot); break; default: diff --git a/target/ppc/mmu-hash32.c b/target/ppc/mmu-hash32.c index 0641b93963..09166b8e03 100644 --- a/target/ppc/mmu-hash32.c +++ b/target/ppc/mmu-hash32.c @@ -346,15 +346,15 @@ static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu, ptem = (vsid << 7) | (pgidx >> 10); /* Page address translation */ - qemu_log_mask(CPU_LOG_MMU, "htab_base %016" HWADDR_PRIx - " htab_mask %016" HWADDR_PRIx - " hash %016" HWADDR_PRIx "\n", + qemu_log_mask(CPU_LOG_MMU, "htab_base 0x%016" HWADDR_PRIx + " htab_mask 0x%016" HWADDR_PRIx + " hash 0x%016" HWADDR_PRIx "\n", ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), hash); /* Primary PTEG lookup */ - qemu_log_mask(CPU_LOG_MMU, "0 htab=%016" HWADDR_PRIx "/%016" HWADDR_PRIx + qemu_log_mask(CPU_LOG_MMU, "0 htab=0x%016" HWADDR_PRIx "/0x%016" HWADDR_PRIx " vsid=%" PRIx32 " ptem=%" PRIx32 - " hash=%016" HWADDR_PRIx "\n", + " hash=0x%016" HWADDR_PRIx "\n", ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), vsid, ptem, hash); pteg_off = get_pteg_offset32(cpu, hash); @@ -362,9 +362,9 @@ static hwaddr ppc_hash32_htab_lookup(PowerPCCPU *cpu, if (pte_offset == -1) { /* Secondary PTEG lookup */ qemu_log_mask(CPU_LOG_MMU, - "1 htab=%016" HWADDR_PRIx "/%016" HWADDR_PRIx + "1 htab=0x%016" HWADDR_PRIx "/0x%016" HWADDR_PRIx " vsid=%" PRIx32 " api=%" PRIx32 - " hash=%016" HWADDR_PRIx "\n", + " hash=0x%016" HWADDR_PRIx "\n", ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), vsid, ptem, ~hash); pteg_off = get_pteg_offset32(cpu, ~hash); diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 3e4b006d4a..8d3394890b 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -697,15 +697,15 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu, /* Page address translation */ qemu_log_mask(CPU_LOG_MMU, - "htab_base %016" HWADDR_PRIx " htab_mask %016" HWADDR_PRIx - " hash %016" HWADDR_PRIx "\n", + "htab_base 0x%016" HWADDR_PRIx " htab_mask 0x%016" HWADDR_PRIx + " hash 0x%016" HWADDR_PRIx "\n", ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), hash); /* Primary PTEG lookup */ qemu_log_mask(CPU_LOG_MMU, - "0 htab=%016" HWADDR_PRIx "/%016" HWADDR_PRIx + "0 htab=0x%016" HWADDR_PRIx "/0x%016" HWADDR_PRIx " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx - " hash=%016" HWADDR_PRIx "\n", + " hash=0x%016" HWADDR_PRIx "\n", ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), vsid, ptem, hash); ptex = ppc_hash64_pteg_search(cpu, hash, sps, ptem, pte, pshift); @@ -714,9 +714,9 @@ static hwaddr ppc_hash64_htab_lookup(PowerPCCPU *cpu, /* Secondary PTEG lookup */ ptem |= HPTE64_V_SECONDARY; qemu_log_mask(CPU_LOG_MMU, - "1 htab=%016" HWADDR_PRIx "/%016" HWADDR_PRIx + "1 htab=0x%016" HWADDR_PRIx "/0x%016" HWADDR_PRIx " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx - " hash=%016" HWADDR_PRIx "\n", ppc_hash64_hpt_base(cpu), + " hash=0x%016" HWADDR_PRIx "\n", ppc_hash64_hpt_base(cpu), ppc_hash64_hpt_mask(cpu), vsid, ptem, ~hash); ptex = ppc_hash64_pteg_search(cpu, ~hash, sps, ptem, pte, pshift); diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index e9d469adeb..bbde3ec41f 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -252,7 +252,7 @@ static int ppc6xx_tlb_check(CPUPPCState *env, mmu_ctx_t *ctx, } if (best != -1) { done: - qemu_log_mask(CPU_LOG_MMU, "found TLB at addr %016" HWADDR_PRIx + qemu_log_mask(CPU_LOG_MMU, "found TLB at addr 0x%016" HWADDR_PRIx " prot=%01x ret=%d\n", ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret); /* Update page flags */ @@ -329,7 +329,7 @@ static int get_bat_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, ret = check_prot(ctx->prot, access_type); if (ret == 0) { qemu_log_mask(CPU_LOG_MMU, - "BAT %d match: r %016" HWADDR_PRIx + "BAT %d match: r 0x%016" HWADDR_PRIx " prot=%c%c\n", i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-', ctx->prot & PAGE_WRITE ? 'W' : '-'); @@ -404,9 +404,9 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, /* Check if instruction fetch is allowed, if needed */ if (type != ACCESS_CODE || ctx->nx == 0) { /* Page address translation */ - qemu_log_mask(CPU_LOG_MMU, "htab_base %016" HWADDR_PRIx - " htab_mask %016" HWADDR_PRIx - " hash %016" HWADDR_PRIx "\n", + qemu_log_mask(CPU_LOG_MMU, "htab_base 0x%016" HWADDR_PRIx + " htab_mask 0x%016" HWADDR_PRIx + " hash 0x%016" HWADDR_PRIx "\n", ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu), hash); ctx->hash[0] = hash; ctx->hash[1] = ~hash; @@ -421,8 +421,8 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, hwaddr curaddr; uint32_t a0, a1, a2, a3; - qemu_log("Page table: %016" HWADDR_PRIx - " len %016" HWADDR_PRIx "\n", + qemu_log("Page table: 0x%016" HWADDR_PRIx + " len 0x%016" HWADDR_PRIx "\n", ppc_hash32_hpt_base(cpu), ppc_hash32_hpt_mask(cpu) + 0x80); for (curaddr = ppc_hash32_hpt_base(cpu); @@ -434,7 +434,7 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, a2 = ldl_phys(cs->as, curaddr + 8); a3 = ldl_phys(cs->as, curaddr + 12); if (a0 != 0 || a1 != 0 || a2 != 0 || a3 != 0) { - qemu_log("%016" HWADDR_PRIx ": %08x %08x %08x %08x\n", + qemu_log("0x%016" HWADDR_PRIx ": %08x %08x %08x %08x\n", curaddr, a0, a1, a2, a3); } } @@ -580,14 +580,14 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, if (ret >= 0) { ctx->raddr = raddr; qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx - " => %016" HWADDR_PRIx + " => 0x%016" HWADDR_PRIx " %d %d\n", __func__, address, ctx->raddr, ctx->prot, ret); return 0; } } qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx - " => %016" HWADDR_PRIx + " => 0x%016" HWADDR_PRIx " %d %d\n", __func__, address, raddr, ctx->prot, ret); return ret; @@ -668,11 +668,11 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, if (ret >= 0) { ctx->raddr = raddr; qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx - " => %016" HWADDR_PRIx " %d %d\n", __func__, + " => 0x%016" HWADDR_PRIx " %d %d\n", __func__, address, ctx->raddr, ctx->prot, ret); } else { qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx - " => %016" HWADDR_PRIx " %d %d\n", __func__, + " => 0x%016" HWADDR_PRIx " %d %d\n", __func__, address, raddr, ctx->prot, ret); } @@ -896,11 +896,11 @@ found_tlb: if (ret >= 0) { ctx->raddr = raddr; qemu_log_mask(CPU_LOG_MMU, "%s: access granted " TARGET_FMT_lx - " => %016" HWADDR_PRIx " %d %d\n", __func__, address, + " => 0x%016" HWADDR_PRIx " %d %d\n", __func__, address, ctx->raddr, ctx->prot, ret); } else { qemu_log_mask(CPU_LOG_MMU, "%s: access refused " TARGET_FMT_lx - " => %016" HWADDR_PRIx " %d %d\n", __func__, address, + " => 0x%016" HWADDR_PRIx " %d %d\n", __func__, address, raddr, ctx->prot, ret); } diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index 3b1230d270..ab1a4eb7e6 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -826,7 +826,7 @@ void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, tlb->prot &= ~PAGE_VALID; } tlb->PID = env->spr[SPR_40x_PID]; /* PID */ - qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN %016" HWADDR_PRIx + qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN 0x%016" HWADDR_PRIx " EPN " TARGET_FMT_lx " size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__, (int)entry, tlb->RPN, tlb->EPN, tlb->size, @@ -864,7 +864,7 @@ void helper_4xx_tlbwe_lo(CPUPPCState *env, target_ulong entry, if (val & PPC4XX_TLBLO_WR) { tlb->prot |= PAGE_WRITE; } - qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN %016" HWADDR_PRIx + qemu_log_mask(CPU_LOG_MMU, "%s: set up TLB %d RPN 0x%016" HWADDR_PRIx " EPN " TARGET_FMT_lx " size " TARGET_FMT_lx " prot %c%c%c%c PID %d\n", __func__, (int)entry, tlb->RPN, tlb->EPN, tlb->size, diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 5c45e92b9f..51033e2ee8 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1272,7 +1272,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "%s 1st-stage address=%" VADDR_PRIx " ret %d physical " - "%016" HWADDR_PRIx " prot %d\n", + "0x%016" HWADDR_PRIx " prot %d\n", __func__, address, ret, pa, prot); if (ret == TRANSLATE_SUCCESS) { @@ -1285,7 +1285,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "%s 2nd-stage address=%" VADDR_PRIx " ret %d physical " - "%016" HWADDR_PRIx " prot %d\n", + "0x%016" HWADDR_PRIx " prot %d\n", __func__, im_address, ret, pa, prot2); prot &= prot2; @@ -1295,7 +1295,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, size, access_type, mode); qemu_log_mask(CPU_LOG_MMU, - "%s PMP address=%016" HWADDR_PRIx " ret %d prot" + "%s PMP address=0x%016" HWADDR_PRIx " ret %d prot" " %d tlb_size " TARGET_FMT_lu "\n", __func__, pa, ret, prot_pmp, tlb_size); @@ -1320,7 +1320,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, qemu_log_mask(CPU_LOG_MMU, "%s address=%" VADDR_PRIx " ret %d physical " - "%016" HWADDR_PRIx " prot %d\n", + "0x%016" HWADDR_PRIx " prot %d\n", __func__, address, ret, pa, prot); if (ret == TRANSLATE_SUCCESS) { @@ -1328,7 +1328,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, size, access_type, mode); qemu_log_mask(CPU_LOG_MMU, - "%s PMP address=%016" HWADDR_PRIx " ret %d prot" + "%s PMP address=0x%016" HWADDR_PRIx " ret %d prot" " %d tlb_size " TARGET_FMT_lu "\n", __func__, pa, ret, prot_pmp, tlb_size); diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c index 81125886fe..60b5b1027f 100644 --- a/target/riscv/monitor.c +++ b/target/riscv/monitor.c @@ -64,7 +64,7 @@ static void print_pte(Monitor *mon, int va_bits, target_ulong vaddr, return; } - monitor_printf(mon, TARGET_FMT_lx " %016" HWADDR_PRIx " " TARGET_FMT_lx + monitor_printf(mon, TARGET_FMT_lx " 0x%016" HWADDR_PRIx " " TARGET_FMT_lx " %c%c%c%c%c%c%c\n", addr_canonical(va_bits, vaddr), paddr, size, diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 91bfb4490e..3c772a0677 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -430,12 +430,12 @@ static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, #ifdef DEBUG_UNASSIGNED if (is_asi) { - printf("Unassigned mem %s access of %d byte%s to %016" HWADDR_PRIx + printf("Unassigned mem %s access of %d byte%s to 0x%016" HWADDR_PRIx " asi 0x%02x from " TARGET_FMT_lx "\n", is_exec ? "exec" : is_write ? "write" : "read", size, size == 1 ? "" : "s", addr, is_asi, env->pc); } else { - printf("Unassigned mem %s access of %d byte%s to %016" HWADDR_PRIx + printf("Unassigned mem %s access of %d byte%s to 0x%016" HWADDR_PRIx " from " TARGET_FMT_lx "\n", is_exec ? "exec" : is_write ? "write" : "read", size, size == 1 ? "" : "s", addr, env->pc); @@ -490,7 +490,7 @@ static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, CPUSPARCState *env = &cpu->env; #ifdef DEBUG_UNASSIGNED - printf("Unassigned mem access to %016" HWADDR_PRIx " from " TARGET_FMT_lx + printf("Unassigned mem access to 0x%016" HWADDR_PRIx " from " TARGET_FMT_lx "\n", addr, env->pc); #endif diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 3ded8ff30e..4f79a09d8b 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -230,7 +230,7 @@ bool sparc_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (likely(error_code == 0)) { qemu_log_mask(CPU_LOG_MMU, "Translate at %" VADDR_PRIx " -> " - "%016" HWADDR_PRIx ", vaddr " TARGET_FMT_lx "\n", + "0x%016" HWADDR_PRIx ", vaddr " TARGET_FMT_lx "\n", address, paddr, vaddr); tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); return true; @@ -356,20 +356,20 @@ void dump_mmu(CPUSPARCState *env) hwaddr pa; uint32_t pde; - qemu_printf("Root ptr: %016" HWADDR_PRIx ", ctx: %d\n", + qemu_printf("Root ptr: 0x%016" HWADDR_PRIx ", ctx: %d\n", (hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]); for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { pde = mmu_probe(env, va, 2); if (pde) { pa = cpu_get_phys_page_debug(cs, va); - qemu_printf("VA: " TARGET_FMT_lx ", PA: %016" HWADDR_PRIx + qemu_printf("VA: " TARGET_FMT_lx ", PA: 0x%016" HWADDR_PRIx " PDE: " TARGET_FMT_lx "\n", va, pa, pde); for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { pde = mmu_probe(env, va1, 1); if (pde) { pa = cpu_get_phys_page_debug(cs, va1); qemu_printf(" VA: " TARGET_FMT_lx - ", PA: %016" HWADDR_PRIx + ", PA: 0x%016" HWADDR_PRIx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde); for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { @@ -377,7 +377,7 @@ void dump_mmu(CPUSPARCState *env) if (pde) { pa = cpu_get_phys_page_debug(cs, va2); qemu_printf(" VA: " TARGET_FMT_lx ", PA: " - "%016" HWADDR_PRIx " PTE: " + "0x%016" HWADDR_PRIx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde); } diff --git a/target/tricore/helper.c b/target/tricore/helper.c index 55a1d780cf..9c96c14ddb 100644 --- a/target/tricore/helper.c +++ b/target/tricore/helper.c @@ -79,7 +79,7 @@ bool tricore_cpu_tlb_fill(CPUState *cs, vaddr address, int size, address, rw, mmu_idx); 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Wed, 11 Jan 2023 02:00:37 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id o7-20020a5d62c7000000b002bbeda3809csm7777857wrv.11.2023.01.11.02.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 02:00:36 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 4ABEC1FFB7; Wed, 11 Jan 2023 10:00:36 +0000 (GMT) References: <20230108023719.2466341-1-richard.henderson@linaro.org> <20230108023719.2466341-4-richard.henderson@linaro.org> User-agent: mu4e 1.9.12; emacs 29.0.60 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, qemu-devel@nongnu.org Subject: Re: [PATCH v4 03/36] tcg: Allocate objects contiguously in temp_allocate_frame Date: Wed, 11 Jan 2023 09:59:52 +0000 In-reply-to: <20230108023719.2466341-4-richard.henderson@linaro.org> Message-ID: <87zgapl7az.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 10:00:45 -0000 Richard Henderson writes: > When allocating a temp to the stack frame, consider the > base type and allocate all parts at once. > > Signed-off-by: Richard Henderson > --- > tcg/tcg.c | 30 ++++++++++++++++++++++-------- > 1 file changed, 22 insertions(+), 8 deletions(-) > > diff --git a/tcg/tcg.c b/tcg/tcg.c > index 99e6e4e1a8..7e69e2c9fd 100644 > --- a/tcg/tcg.c > +++ b/tcg/tcg.c > @@ -3242,11 +3242,12 @@ static bool liveness_pass_2(TCGContext *s) >=20=20 > static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) > { > - int size =3D tcg_type_size(ts->type); > - int align; > intptr_t off; > + int size, align; >=20=20 > - switch (ts->type) { > + /* When allocating an object, look at the full type. */ > + size =3D tcg_type_size(ts->base_type); > + switch (ts->base_type) { > case TCG_TYPE_I32: > align =3D 4; > break; > @@ -3277,13 +3278,26 @@ static void temp_allocate_frame(TCGContext *s, TC= GTemp *ts) > tcg_raise_tb_overflow(s); > } > s->current_frame_offset =3D off + size; > - > - ts->mem_offset =3D off; > #if defined(__sparc__) > - ts->mem_offset +=3D TCG_TARGET_STACK_BIAS; > + off +=3D TCG_TARGET_STACK_BIAS; > #endif > - ts->mem_base =3D s->frame_temp; > - ts->mem_allocated =3D 1; > + > + /* If the object was subdivided, assign memory to all the parts. */ > + if (ts->base_type !=3D ts->type) { > + int part_size =3D tcg_type_size(ts->type); > + int part_count =3D size / part_size; > + > + ts -=3D ts->temp_subindex; Whats going on here? Are we jumping to a previous temp? What guarentees there is something at ts - ts->temp_subindex? > + for (int i =3D 0; i < part_count; ++i) { > + ts[i].mem_offset =3D off + i * part_size; > + ts[i].mem_base =3D s->frame_temp; > + ts[i].mem_allocated =3D 1; > + } > + } else { > + ts->mem_offset =3D off; > + ts->mem_base =3D s->frame_temp; > + ts->mem_allocated =3D 1; > + } > } >=20=20 > /* Assign @reg to @ts, and update reg_to_temp[]. */ --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro From MAILER-DAEMON Wed Jan 11 05:39:54 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFYWQ-0003kb-KT for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 05:39:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFYWP-0003ja-5J; Wed, 11 Jan 2023 05:39:53 -0500 Received: from smtp80.cstnet.cn ([159.226.251.80] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFYWM-0007k5-8M; Wed, 11 Jan 2023 05:39:52 -0500 Received: from localhost.localdomain (unknown [61.165.33.198]) by APP-01 (Coremail) with SMTP id qwCowABHTTXskb5jCcUADA--.29173S2; Wed, 11 Jan 2023 18:39:41 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v10 0/9] support subsets of virtual memory extension Date: Wed, 11 Jan 2023 18:39:27 +0800 Message-Id: <20230111103936.129269-1-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CM-TRANSID: qwCowABHTTXskb5jCcUADA--.29173S2 X-Coremail-Antispam: 1UD129KBjvJXoWxZr1kZFyfCF1fXw17ur1UGFg_yoW5Xr1fpr WrC3yakrZ8tFWxJw4ft3WUJw15AFs5Wr45Awn7Jw1kJay3ArW3Jrs7K3W3G3WxJF1rWrnF 93WUCw13u3yUJFJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkS14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oV Cq3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE14v_Gw1l 42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJV WUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAK I48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r 4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY 6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfUonmRUUUUU X-Originating-IP: [61.165.33.198] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.80; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 10:39:53 -0000 This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version instructions. Specification: https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v9 To test Zc* implementation, specify cpu argument with 'x-zca=true,x-zcb=true,x-zcf=true,f=true" and "x-zcd=true,d=true" (or "x-zcmp=true,x-zcmt=true" with c or d=false) to enable Zca/Zcb/Zcf and Zcd(or Zcmp,Zcmt) extensions support. This implementation can pass the basic zc tests from https://github.com/yulong-plct/zc-test v10: * rebase on Daniel's series(riscv-to-apply.next) and adjust riscv-tests to test on sifive related CPUs v9: * rebase on riscv-to-apply.next v8: * improve disas support in Patch 9 v7: * Fix description for Zca v6: * fix base address for jump table in Patch 7 * rebase on riscv-to-apply.next v5: * fix exception unwind problem for cpu_ld*_code in helper of cm_jalt v4: * improve Zcmp suggested by Richard * fix stateen related check for Zcmt v3: * update the solution for Zcf to the way of Zcd * update Zcb to reuse gen_load/store * use trans function instead of helper for push/pop v2: * add check for relationship between Zca/Zcf/Zcd with C/F/D based on related discussion in review of Zc* spec * separate c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/zcmt Weiwei Li (9): target/riscv: add cfg properties for Zc* extension target/riscv: add support for Zca extension target/riscv: add support for Zcf extension target/riscv: add support for Zcd extension target/riscv: add support for Zcb extension target/riscv: add support for Zcmp extension target/riscv: add support for Zcmt extension target/riscv: expose properties for Zc* extension disas/riscv.c: add disasm support for Zc* disas/riscv.c | 228 +++++++++++++++- target/riscv/cpu.c | 56 ++++ target/riscv/cpu.h | 10 + target/riscv/cpu_bits.h | 7 + target/riscv/csr.c | 38 ++- target/riscv/helper.h | 3 + target/riscv/insn16.decode | 63 ++++- target/riscv/insn_trans/trans_rvd.c.inc | 18 ++ target/riscv/insn_trans/trans_rvf.c.inc | 18 ++ target/riscv/insn_trans/trans_rvi.c.inc | 4 +- target/riscv/insn_trans/trans_rvzce.c.inc | 313 ++++++++++++++++++++++ target/riscv/machine.c | 19 ++ target/riscv/meson.build | 3 +- target/riscv/translate.c | 15 +- target/riscv/zce_helper.c | 55 ++++ 15 files changed, 834 insertions(+), 16 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc create mode 100644 target/riscv/zce_helper.c -- 2.25.1 From MAILER-DAEMON Wed Jan 11 05:39:55 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFYWR-0003lb-PM for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 05:39:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFYWP-0003jv-Uy; Wed, 11 Jan 2023 05:39:53 -0500 Received: from smtp80.cstnet.cn ([159.226.251.80] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFYWM-0007k6-8d; Wed, 11 Jan 2023 05:39:53 -0500 Received: from localhost.localdomain (unknown [61.165.33.198]) by APP-01 (Coremail) with SMTP id qwCowABHTTXskb5jCcUADA--.29173S3; Wed, 11 Jan 2023 18:39:41 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v10 1/9] target/riscv: add cfg properties for Zc* extension Date: Wed, 11 Jan 2023 18:39:28 +0800 Message-Id: <20230111103936.129269-2-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230111103936.129269-1-liweiwei@iscas.ac.cn> References: <20230111103936.129269-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: qwCowABHTTXskb5jCcUADA--.29173S3 X-Coremail-Antispam: 1UD129KBjvJXoW7KFy7CF1DurykXF1kZrWrXwb_yoW8KF4xpr 4rG3yYkrWDJr17C3yfXF1UK3Z8Wws2vayIg392q3WxuFW7ArW5Xr1vkw1UWF45tFs5Xa1a 9F17CF98CwsrJa7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBa14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1I6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0DM2AI xVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20x vE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xv r2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkIecxEwVAFwVW8twCF04k20x vY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I 3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIx AIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAI cVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2js IEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUqkskUUUUU= X-Originating-IP: [61.165.33.198] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.80; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 10:39:54 -0000 Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension Add check for these properties Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 43 +++++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 6 ++++++ 2 files changed, 49 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c192d96a94..39ab7e46d3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -726,6 +726,49 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) } } + if (cpu->cfg.ext_c) { + cpu->cfg.ext_zca = true; + if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) { + cpu->cfg.ext_zcf = true; + } + if (cpu->cfg.ext_d) { + cpu->cfg.ext_zcd = true; + } + } + + if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { + error_setg(errp, "Zcf extension is only relevant to RV32"); + return; + } + + if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) { + error_setg(errp, "Zcf extension requires F extension"); + return; + } + + if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) { + error_setg(errp, "Zcd extension requires D extension"); + return; + } + + if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || + cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { + error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " + "extension"); + return; + } + + if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { + error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " + "Zcd extension"); + return; + } + + if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { + error_setg(errp, "Zcmt extension requires Zicsr extension"); + return; + } + if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn = true; cpu->cfg.ext_zkr = true; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bcf0826753..dc2410269d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -434,6 +434,12 @@ struct RISCVCPUConfig { bool ext_zbkc; bool ext_zbkx; bool ext_zbs; + bool ext_zca; + bool ext_zcb; + bool ext_zcd; + bool ext_zcf; + bool ext_zcmp; + bool ext_zcmt; bool ext_zk; bool ext_zkn; bool ext_zknd; -- 2.25.1 From MAILER-DAEMON Wed Jan 11 05:39:56 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFYWR-0003lk-Ug for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 05:39:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFYWQ-0003kS-IZ; Wed, 11 Jan 2023 05:39:54 -0500 Received: from smtp80.cstnet.cn ([159.226.251.80] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFYWM-0007kQ-Ay; Wed, 11 Jan 2023 05:39:54 -0500 Received: from localhost.localdomain (unknown [61.165.33.198]) by APP-01 (Coremail) with SMTP id qwCowABHTTXskb5jCcUADA--.29173S7; Wed, 11 Jan 2023 18:39:43 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v10 5/9] target/riscv: add support for Zcb extension Date: Wed, 11 Jan 2023 18:39:32 +0800 Message-Id: <20230111103936.129269-6-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230111103936.129269-1-liweiwei@iscas.ac.cn> References: <20230111103936.129269-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: qwCowABHTTXskb5jCcUADA--.29173S7 X-Coremail-Antispam: 1UD129KBjvJXoW3Jw1Dtw13Cr18try7tF15XFb_yoW7trWrpF 1xCryUGFyqgFyIyayfKF13XF17Wr4fWrWUK39xAw1kGayYgFWDJF1DKay3Ka1DXr4DWr4j k3WDAayUJ3y0q37anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBl14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr 1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE14v_Gw1l42 xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWU GwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI4 8JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r4U JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcV C2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbPC7UUUUUU== X-Originating-IP: [61.165.33.198] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.80; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 10:39:54 -0000 Add encode and trans* functions support for Zcb instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode | 24 ++++++ target/riscv/insn_trans/trans_rvzce.c.inc | 100 ++++++++++++++++++++++ target/riscv/translate.c | 2 + 3 files changed, 126 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index b62664b6af..47603ec1e0 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -43,6 +43,8 @@ %imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4 %imm_lui 12:s1 2:5 !function=ex_shift_12 +%zcb_b_uimm 5:1 6:1 +%zcb_h_uimm 5:1 !function=ex_shift_1 # Argument sets imported from insn32.decode: &empty !extern @@ -53,6 +55,7 @@ &b imm rs2 rs1 !extern &u imm rd !extern &shift shamt rs1 rd !extern +&r2 rd rs1 !extern # Formats 16: @@ -89,6 +92,13 @@ @c_andi ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3 +@zcb_unary ... ... ... .. ... .. &r2 rs1=%rs1_3 rd=%rs1_3 +@zcb_binary ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 rd=%rs1_3 +@zcb_lb ... . .. ... .. ... .. &i imm=%zcb_b_uimm rs1=%rs1_3 rd=%rs2_3 +@zcb_lh ... . .. ... .. ... .. &i imm=%zcb_h_uimm rs1=%rs1_3 rd=%rs2_3 +@zcb_sb ... . .. ... .. ... .. &s imm=%zcb_b_uimm rs1=%rs1_3 rs2=%rs2_3 +@zcb_sh ... . .. ... .. ... .. &s imm=%zcb_h_uimm rs1=%rs1_3 rs2=%rs2_3 + # *** RV32/64C Standard Extension (Quadrant 0) *** { # Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved. @@ -180,3 +190,17 @@ sw 110 . ..... ..... 10 @c_swsp sd 111 . ..... ..... 10 @c_sdsp c_fsw 111 . ..... ..... 10 @c_swsp } + +# *** RV64 and RV32 Zcb Extension *** +c_zext_b 100 111 ... 11 000 01 @zcb_unary +c_sext_b 100 111 ... 11 001 01 @zcb_unary +c_zext_h 100 111 ... 11 010 01 @zcb_unary +c_sext_h 100 111 ... 11 011 01 @zcb_unary +c_zext_w 100 111 ... 11 100 01 @zcb_unary +c_not 100 111 ... 11 101 01 @zcb_unary +c_mul 100 111 ... 10 ... 01 @zcb_binary +c_lbu 100 000 ... .. ... 00 @zcb_lb +c_lhu 100 001 ... 0. ... 00 @zcb_lh +c_lh 100 001 ... 1. ... 00 @zcb_lh +c_sb 100 010 ... .. ... 00 @zcb_sb +c_sh 100 011 ... 0. ... 00 @zcb_sh diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc new file mode 100644 index 0000000000..de96c4afaf --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -0,0 +1,100 @@ +/* + * RISC-V translation routines for the Zcb Standard Extension. + * + * Copyright (c) 2021-2022 PLCT Lab + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#define REQUIRE_ZCB(ctx) do { \ + if (!ctx->cfg_ptr->ext_zcb) \ + return false; \ +} while (0) + +static bool trans_c_zext_b(DisasContext *ctx, arg_c_zext_b *a) +{ + REQUIRE_ZCB(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8u_tl); +} + +static bool trans_c_zext_h(DisasContext *ctx, arg_c_zext_h *a) +{ + REQUIRE_ZCB(ctx); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl); +} + +static bool trans_c_sext_b(DisasContext *ctx, arg_c_sext_b *a) +{ + REQUIRE_ZCB(ctx); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext8s_tl); +} + +static bool trans_c_sext_h(DisasContext *ctx, arg_c_sext_h *a) +{ + REQUIRE_ZCB(ctx); + REQUIRE_ZBB(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16s_tl); +} + +static bool trans_c_zext_w(DisasContext *ctx, arg_c_zext_w *a) +{ + REQUIRE_64BIT(ctx); + REQUIRE_ZCB(ctx); + REQUIRE_ZBA(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext32u_tl); +} + +static bool trans_c_not(DisasContext *ctx, arg_c_not *a) +{ + REQUIRE_ZCB(ctx); + return gen_unary(ctx, a, EXT_NONE, tcg_gen_not_tl); +} + +static bool trans_c_mul(DisasContext *ctx, arg_c_mul *a) +{ + REQUIRE_ZCB(ctx); + REQUIRE_M_OR_ZMMUL(ctx); + return gen_arith(ctx, a, EXT_NONE, tcg_gen_mul_tl, NULL); +} + +static bool trans_c_lbu(DisasContext *ctx, arg_c_lbu *a) +{ + REQUIRE_ZCB(ctx); + return gen_load(ctx, a, MO_UB); +} + +static bool trans_c_lhu(DisasContext *ctx, arg_c_lhu *a) +{ + REQUIRE_ZCB(ctx); + return gen_load(ctx, a, MO_UW); +} + +static bool trans_c_lh(DisasContext *ctx, arg_c_lh *a) +{ + REQUIRE_ZCB(ctx); + return gen_load(ctx, a, MO_SW); +} + +static bool trans_c_sb(DisasContext *ctx, arg_c_sb *a) +{ + REQUIRE_ZCB(ctx); + return gen_store(ctx, a, MO_UB); +} + +static bool trans_c_sh(DisasContext *ctx, arg_c_sh *a) +{ + REQUIRE_ZCB(ctx); + return gen_store(ctx, a, MO_UW); +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 93ec2b7c55..76d1a9661c 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1069,6 +1069,8 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) /* Include the auto-generated decoder for 16 bit insn */ #include "decode-insn16.c.inc" +#include "insn_trans/trans_rvzce.c.inc" + /* Include decoders for factored-out extensions */ #include "decode-XVentanaCondOps.c.inc" -- 2.25.1 From MAILER-DAEMON Wed Jan 11 05:39:56 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFYWS-0003mF-6O for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 05:39:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFYWQ-0003k0-5X; Wed, 11 Jan 2023 05:39:54 -0500 Received: from smtp80.cstnet.cn ([159.226.251.80] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFYWM-0007k9-8u; Wed, 11 Jan 2023 05:39:53 -0500 Received: from localhost.localdomain (unknown [61.165.33.198]) by APP-01 (Coremail) with SMTP id qwCowABHTTXskb5jCcUADA--.29173S5; Wed, 11 Jan 2023 18:39:42 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v10 3/9] target/riscv: add support for Zcf extension Date: Wed, 11 Jan 2023 18:39:30 +0800 Message-Id: <20230111103936.129269-4-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230111103936.129269-1-liweiwei@iscas.ac.cn> References: <20230111103936.129269-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: qwCowABHTTXskb5jCcUADA--.29173S5 X-Coremail-Antispam: 1UD129KBjvJXoW7uF43Zr43Zry3AFW8trW3GFg_yoW8trWxpr 18C3y7GrWUAryfA3Z3tF45Xr1UJrs2gry8t39Iyw1kGa15GFs8Zw1qqr13tr4UXFyvqr1Y kF18A39xC3yktrDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBa14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JrWl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0DM2AI xVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20x vE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xv r2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkIecxEwVAFwVW8twCF04k20x vY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I 3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIx AIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAI cVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2js IEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUHWlkUUUUU= X-Originating-IP: [61.165.33.198] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.80; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 10:39:54 -0000 Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode | 8 ++++---- target/riscv/insn_trans/trans_rvf.c.inc | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index ccfe59f294..f3ea650325 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -109,11 +109,11 @@ sw 110 ... ... .. ... 00 @cs_w # *** RV32C and RV64C specific Standard Extension (Quadrant 0) *** { ld 011 ... ... .. ... 00 @cl_d - flw 011 ... ... .. ... 00 @cl_w + c_flw 011 ... ... .. ... 00 @cl_w } { sd 111 ... ... .. ... 00 @cs_d - fsw 111 ... ... .. ... 00 @cs_w + c_fsw 111 ... ... .. ... 00 @cs_w } # *** RV32/64C Standard Extension (Quadrant 1) *** @@ -174,9 +174,9 @@ sw 110 . ..... ..... 10 @c_swsp { c64_illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0 ld 011 . ..... ..... 10 @c_ldsp - flw 011 . ..... ..... 10 @c_lwsp + c_flw 011 . ..... ..... 10 @c_lwsp } { sd 111 . ..... ..... 10 @c_sdsp - fsw 111 . ..... ..... 10 @c_swsp + c_fsw 111 . ..... ..... 10 @c_swsp } diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index 965e1f8d11..5df9c148dc 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -30,6 +30,12 @@ } \ } while (0) +#define REQUIRE_ZCF(ctx) do { \ + if (!ctx->cfg_ptr->ext_zcf) { \ + return false; \ + } \ +} while (0) + static bool trans_flw(DisasContext *ctx, arg_flw *a) { TCGv_i64 dest; @@ -61,6 +67,18 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) return true; } +static bool trans_c_flw(DisasContext *ctx, arg_flw *a) +{ + REQUIRE_ZCF(ctx); + return trans_flw(ctx, a); +} + +static bool trans_c_fsw(DisasContext *ctx, arg_fsw *a) +{ + REQUIRE_ZCF(ctx); + return trans_fsw(ctx, a); +} + static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a) { REQUIRE_FPU; -- 2.25.1 From MAILER-DAEMON Wed Jan 11 05:39:59 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFYWU-0003o7-NG for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 05:39:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFYWR-0003lj-Ts; Wed, 11 Jan 2023 05:39:55 -0500 Received: from smtp80.cstnet.cn ([159.226.251.80] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFYWN-0007kq-4U; Wed, 11 Jan 2023 05:39:55 -0500 Received: from localhost.localdomain (unknown [61.165.33.198]) by APP-01 (Coremail) with SMTP id qwCowABHTTXskb5jCcUADA--.29173S11; Wed, 11 Jan 2023 18:39:47 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v10 9/9] disas/riscv.c: add disasm support for Zc* Date: Wed, 11 Jan 2023 18:39:36 +0800 Message-Id: <20230111103936.129269-10-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230111103936.129269-1-liweiwei@iscas.ac.cn> References: <20230111103936.129269-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: qwCowABHTTXskb5jCcUADA--.29173S11 X-Coremail-Antispam: 1UD129KBjvJXoW3AF4DGw47WrWDXFyUuFW7Arb_yoWfZF1fpF 1rG343trWjka4fX3WfAFWUAas8trWUXr4xJaySy3Z3Casru343CF1jq3yavFykG3yrKr47 uFsxWa1jg3Z7JwUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBG14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr 1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE14v_Gw1l42 xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWU GwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI4 8JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r4U JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcV C2z280aVCY1x0267AKxVW8Jr0_Cr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUQFxUUUUUU= X-Originating-IP: [61.165.33.198] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.80; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 10:39:56 -0000 Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd* instructions currently Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis --- disas/riscv.c | 228 +++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 227 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b/disas/riscv.c index d216b9c39b..f75da98540 100644 --- a/disas/riscv.c +++ b/disas/riscv.c @@ -163,6 +163,13 @@ typedef enum { rv_codec_v_i, rv_codec_vsetvli, rv_codec_vsetivli, + rv_codec_zcb_ext, + rv_codec_zcb_mul, + rv_codec_zcb_lb, + rv_codec_zcb_lh, + rv_codec_zcmp_cm_pushpop, + rv_codec_zcmp_cm_mv, + rv_codec_zcmt_jt, } rv_codec; typedef enum { @@ -935,6 +942,26 @@ typedef enum { rv_op_vsetvli = 766, rv_op_vsetivli = 767, rv_op_vsetvl = 768, + rv_op_c_zext_b = 769, + rv_op_c_sext_b = 770, + rv_op_c_zext_h = 771, + rv_op_c_sext_h = 772, + rv_op_c_zext_w = 773, + rv_op_c_not = 774, + rv_op_c_mul = 775, + rv_op_c_lbu = 776, + rv_op_c_lhu = 777, + rv_op_c_lh = 778, + rv_op_c_sb = 779, + rv_op_c_sh = 780, + rv_op_cm_push = 781, + rv_op_cm_pop = 782, + rv_op_cm_popret = 783, + rv_op_cm_popretz = 784, + rv_op_cm_mva01s = 785, + rv_op_cm_mvsa01 = 786, + rv_op_cm_jt = 787, + rv_op_cm_jalt = 788, } rv_op; /* structures */ @@ -958,6 +985,7 @@ typedef struct { uint8_t rnum; uint8_t vm; uint32_t vzimm; + uint8_t rlist; } rv_decode; typedef struct { @@ -1070,6 +1098,10 @@ static const char rv_vreg_name_sym[32][4] = { #define rv_fmt_vd_vm "O\tDm" #define rv_fmt_vsetvli "O\t0,1,v" #define rv_fmt_vsetivli "O\t0,u,v" +#define rv_fmt_rs1_rs2_zce_ldst "O\t2,i(1)" +#define rv_fmt_push_rlist "O\tx,-i" +#define rv_fmt_pop_rlist "O\tx,i" +#define rv_fmt_zcmt_index "O\ti" /* pseudo-instruction constraints */ @@ -2065,7 +2097,27 @@ const rv_opcode_data opcode_data[] = { { "vsext.vf8", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, rv_op_vsext_vf8, rv_op_vsext_vf8, 0 }, { "vsetvli", rv_codec_vsetvli, rv_fmt_vsetvli, NULL, rv_op_vsetvli, rv_op_vsetvli, 0 }, { "vsetivli", rv_codec_vsetivli, rv_fmt_vsetivli, NULL, rv_op_vsetivli, rv_op_vsetivli, 0 }, - { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 } + { "vsetvl", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, rv_op_vsetvl, rv_op_vsetvl, 0 }, + { "c.zext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, + { "c.sext.b", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, + { "c.zext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, + { "c.sext.h", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, + { "c.zext.w", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, + { "c.not", rv_codec_zcb_ext, rv_fmt_rd, NULL, 0 }, + { "c.mul", rv_codec_zcb_mul, rv_fmt_rd_rs2, NULL, 0, 0 }, + { "c.lbu", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, + { "c.lhu", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, + { "c.lh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, + { "c.sb", rv_codec_zcb_lb, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, + { "c.sh", rv_codec_zcb_lh, rv_fmt_rs1_rs2_zce_ldst, NULL, 0, 0, 0 }, + { "cm.push", rv_codec_zcmp_cm_pushpop, rv_fmt_push_rlist, NULL, 0, 0 }, + { "cm.pop", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, + { "cm.popret", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0, 0 }, + { "cm.popretz", rv_codec_zcmp_cm_pushpop, rv_fmt_pop_rlist, NULL, 0, 0 }, + { "cm.mva01s", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, + { "cm.mvsa01", rv_codec_zcmp_cm_mv, rv_fmt_rd_rs2, NULL, 0, 0, 0 }, + { "cm.jt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, + { "cm.jalt", rv_codec_zcmt_jt, rv_fmt_zcmt_index, NULL, 0 }, }; /* CSR names */ @@ -2084,6 +2136,7 @@ static const char *csr_name(int csrno) case 0x000a: return "vxrm"; case 0x000f: return "vcsr"; case 0x0015: return "seed"; + case 0x0017: return "jvt"; case 0x0040: return "uscratch"; case 0x0041: return "uepc"; case 0x0042: return "ucause"; @@ -2306,6 +2359,24 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) op = rv_op_c_ld; } break; + case 4: + switch ((inst >> 10) & 0b111) { + case 0: op = rv_op_c_lbu; break; + case 1: + if (((inst >> 6) & 1) == 0) { + op = rv_op_c_lhu; + } else { + op = rv_op_c_lh; + } + break; + case 2: op = rv_op_c_sb; break; + case 3: + if (((inst >> 6) & 1) == 0) { + op = rv_op_c_sh; + } + break; + } + break; case 5: if (isa == rv128) { op = rv_op_c_sq; @@ -2362,6 +2433,17 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) case 3: op = rv_op_c_and; break; case 4: op = rv_op_c_subw; break; case 5: op = rv_op_c_addw; break; + case 6: op = rv_op_c_mul; break; + case 7: + switch ((inst >> 2) & 0b111) { + case 0: op = rv_op_c_zext_b; break; + case 1: op = rv_op_c_sext_b; break; + case 2: op = rv_op_c_zext_h; break; + case 3: op = rv_op_c_sext_h; break; + case 4: op = rv_op_c_zext_w; break; + case 5: op = rv_op_c_not; break; + } + break; } break; } @@ -2417,6 +2499,46 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa) op = rv_op_c_sqsp; } else { op = rv_op_c_fsdsp; + if (((inst >> 12) & 0b01)) { + switch ((inst >> 8) & 0b01111) { + case 8: + if (((inst >> 4) & 0b01111) >= 4) { + op = rv_op_cm_push; + } + break; + case 10: + if (((inst >> 4) & 0b01111) >= 4) { + op = rv_op_cm_pop; + } + break; + case 12: + if (((inst >> 4) & 0b01111) >= 4) { + op = rv_op_cm_popretz; + } + break; + case 14: + if (((inst >> 4) & 0b01111) >= 4) { + op = rv_op_cm_popret; + } + break; + } + } else { + switch ((inst >> 10) & 0b011) { + case 0: + if (((inst >> 2) & 0xFF) >= 32) { + op = rv_op_cm_jalt; + } else { + op = rv_op_cm_jt; + } + break; + case 3: + switch ((inst >> 5) & 0b011) { + case 1: op = rv_op_cm_mvsa01; break; + case 3: op = rv_op_cm_mva01s; break; + } + break; + } + } } break; case 6: op = rv_op_c_swsp; break; @@ -3661,6 +3783,21 @@ static uint32_t operand_crs2q(rv_inst inst) return (inst << 59) >> 61; } +static uint32_t calculate_xreg(uint32_t sreg) +{ + return sreg < 2 ? sreg + 8 : sreg + 16; +} + +static uint32_t operand_sreg1(rv_inst inst) +{ + return calculate_xreg((inst << 54) >> 61); +} + +static uint32_t operand_sreg2(rv_inst inst) +{ + return calculate_xreg((inst << 59) >> 61); +} + static uint32_t operand_crd(rv_inst inst) { return (inst << 52) >> 59; @@ -3883,6 +4020,46 @@ static uint32_t operand_vm(rv_inst inst) return (inst << 38) >> 63; } +static uint32_t operand_uimm_c_lb(rv_inst inst) +{ + return (((inst << 58) >> 63) << 1) | + ((inst << 57) >> 63); +} + +static uint32_t operand_uimm_c_lh(rv_inst inst) +{ + return (((inst << 58) >> 63) << 1); +} + +static uint32_t operand_zcmp_spimm(rv_inst inst) +{ + return ((inst << 60) >> 62) << 4; +} + +static uint32_t operand_zcmp_rlist(rv_inst inst) +{ + return ((inst << 56) >> 60); +} + +static uint32_t calculate_stack_adj(rv_isa isa, uint32_t rlist, uint32_t spimm) +{ + int xlen_bytes_log2 = isa == rv64 ? 3 : 2; + int regs = rlist == 15 ? 13 : rlist - 3; + uint32_t stack_adj_base = ROUND_UP(regs << xlen_bytes_log2, 16); + return stack_adj_base + spimm; +} + +static uint32_t operand_zcmp_stack_adj(rv_inst inst, rv_isa isa) +{ + return calculate_stack_adj(isa, operand_zcmp_rlist(inst), + operand_zcmp_spimm(inst)); +} + +static uint32_t operand_tbl_index(rv_inst inst) +{ + return ((inst << 54) >> 56); +} + /* decode operands */ static void decode_inst_operands(rv_decode *dec, rv_isa isa) @@ -4199,6 +4376,34 @@ static void decode_inst_operands(rv_decode *dec, rv_isa isa) dec->imm = operand_vimm(inst); dec->vzimm = operand_vzimm10(inst); break; + case rv_codec_zcb_lb: + dec->rs1 = operand_crs1q(inst) + 8; + dec->rs2 = operand_crs2q(inst) + 8; + dec->imm = operand_uimm_c_lb(inst); + break; + case rv_codec_zcb_lh: + dec->rs1 = operand_crs1q(inst) + 8; + dec->rs2 = operand_crs2q(inst) + 8; + dec->imm = operand_uimm_c_lh(inst); + break; + case rv_codec_zcb_ext: + dec->rd = operand_crs1q(inst) + 8; + break; + case rv_codec_zcb_mul: + dec->rd = operand_crs1rdq(inst) + 8; + dec->rs2 = operand_crs2q(inst) + 8; + break; + case rv_codec_zcmp_cm_pushpop: + dec->imm = operand_zcmp_stack_adj(inst, isa); + dec->rlist = operand_zcmp_rlist(inst); + break; + case rv_codec_zcmp_cm_mv: + dec->rd = operand_sreg1(inst); + dec->rs2 = operand_sreg2(inst); + break; + case rv_codec_zcmt_jt: + dec->imm = operand_tbl_index(inst); + break; }; } @@ -4358,6 +4563,9 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec) case ')': append(buf, ")", buflen); break; + case '-': + append(buf, "-", buflen); + break; case 'b': snprintf(tmp, sizeof(tmp), "%d", dec->bs); append(buf, tmp, buflen); @@ -4541,6 +4749,24 @@ static void format_inst(char *buf, size_t buflen, size_t tab, rv_decode *dec) append(buf, vma, buflen); break; } + case 'x': { + switch (dec->rlist) { + case 4: + snprintf(tmp, sizeof(tmp), "{ra}"); + break; + case 5: + snprintf(tmp, sizeof(tmp), "{ra, s0}"); + break; + case 15: + snprintf(tmp, sizeof(tmp), "{ra, s0-s11}"); + break; + default: + snprintf(tmp, sizeof(tmp), "{ra, s0-s%d}", dec->rlist - 5); + break; + } + append(buf, tmp, buflen); + break; + } default: break; } -- 2.25.1 From MAILER-DAEMON Wed Jan 11 05:40:08 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFYWa-0003pk-HT for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 05:40:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFYWQ-0003k4-9A; Wed, 11 Jan 2023 05:39:54 -0500 Received: from smtp80.cstnet.cn ([159.226.251.80] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFYWM-0007k8-9P; Wed, 11 Jan 2023 05:39:54 -0500 Received: from localhost.localdomain (unknown [61.165.33.198]) by APP-01 (Coremail) with SMTP id qwCowABHTTXskb5jCcUADA--.29173S4; Wed, 11 Jan 2023 18:39:42 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li , Wilfred Mallawa Subject: [PATCH v10 2/9] target/riscv: add support for Zca extension Date: Wed, 11 Jan 2023 18:39:29 +0800 Message-Id: <20230111103936.129269-3-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230111103936.129269-1-liweiwei@iscas.ac.cn> References: <20230111103936.129269-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: qwCowABHTTXskb5jCcUADA--.29173S4 X-Coremail-Antispam: 1UD129KBjvJXoW7ZF13tF18Ww1xCrWfXw1UJrb_yoW8KF47pr 4Fk3yUKrZ5Jr93Aa95GF4jqr1UJr4SgrWxJws0vws3JFW3Xr45XF4DKry3KrWUZFs2qr1Y 9FZ0yFy5Za18XaDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPl14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0DM2AI xVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20x vE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xv r2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2IY04 v7MxkIecxEwVAFwVW8twCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC2 0s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI 0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv2 0xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2js IE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZF pf9x0JUczV8UUUUU= X-Originating-IP: [61.165.33.198] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.80; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 10:39:54 -0000 Modify the check for C extension to Zca (C implies Zca) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Reviewed-by: Wilfred Mallawa --- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/translate.c | 8 ++++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 4496f21266..ef7c3002b0 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -56,7 +56,7 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2); gen_set_pc(ctx, cpu_pc); - if (!has_ext(ctx, RVC)) { + if (!ctx->cfg_ptr->ext_zca) { TCGv t0 = tcg_temp_new(); misaligned = gen_new_label(); @@ -178,7 +178,7 @@ static bool gen_branch(DisasContext *ctx, arg_b *a, TCGCond cond) gen_set_label(l); /* branch taken */ - if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + a->imm) & 0x3)) { + if (!ctx->cfg_ptr->ext_zca && ((ctx->base.pc_next + a->imm) & 0x3)) { /* misaligned */ gen_exception_inst_addr_mis(ctx); } else { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index df38db7553..93ec2b7c55 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -557,7 +557,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) /* check misaligned: */ next_pc = ctx->base.pc_next + imm; - if (!has_ext(ctx, RVC)) { + if (!ctx->cfg_ptr->ext_zca) { if ((next_pc & 0x3) != 0) { gen_exception_inst_addr_mis(ctx); return; @@ -1099,7 +1099,11 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) if (insn_len(opcode) == 2) { ctx->opcode = opcode; ctx->pc_succ_insn = ctx->base.pc_next + 2; - if (has_ext(ctx, RVC) && decode_insn16(ctx, opcode)) { + /* + * The Zca extension is added as way to refer to instructions in the C + * extension that do not include the floating-point loads and stores + */ + if (ctx->cfg_ptr->ext_zca && decode_insn16(ctx, opcode)) { return; } } else { -- 2.25.1 From MAILER-DAEMON Wed Jan 11 05:40:21 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFYWh-0003qu-L2 for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 05:40:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFYWR-0003lW-I9; Wed, 11 Jan 2023 05:39:55 -0500 Received: from smtp80.cstnet.cn ([159.226.251.80] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFYWM-0007ka-9N; Wed, 11 Jan 2023 05:39:55 -0500 Received: from localhost.localdomain (unknown [61.165.33.198]) by APP-01 (Coremail) with SMTP id qwCowABHTTXskb5jCcUADA--.29173S8; Wed, 11 Jan 2023 18:39:45 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v10 6/9] target/riscv: add support for Zcmp extension Date: Wed, 11 Jan 2023 18:39:33 +0800 Message-Id: <20230111103936.129269-7-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230111103936.129269-1-liweiwei@iscas.ac.cn> References: <20230111103936.129269-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: qwCowABHTTXskb5jCcUADA--.29173S8 X-Coremail-Antispam: 1UD129KBjvJXoWxuw4DWw1xtw1kAw1UuFWUCFg_yoW3Gr1xpF 1UC347Wr48ZFWSy3y8KFyrCFnIqrn3KrWjv34Skw1vka9xWFWDJr48KrW3tw48WFykZFW5 CFZ8uayjv3y5XrUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBl14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr 1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE14v_Gw1l42 xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWU GwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI4 8JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r4U JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcV C2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbPC7UUUUUU== X-Originating-IP: [61.165.33.198] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.80; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 10:39:55 -0000 Add encode, trans* functions for Zcmp instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode | 18 +++ target/riscv/insn_trans/trans_rvzce.c.inc | 189 +++++++++++++++++++++- target/riscv/translate.c | 5 + 3 files changed, 211 insertions(+), 1 deletion(-) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 47603ec1e0..4654c23052 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -21,6 +21,8 @@ %rs1_3 7:3 !function=ex_rvc_register %rs2_3 2:3 !function=ex_rvc_register %rs2_5 2:5 +%sreg1 7:3 !function=ex_sreg_register +%sreg2 2:3 !function=ex_sreg_register # Immediates: %imm_ci 12:s1 2:5 @@ -45,6 +47,8 @@ %zcb_b_uimm 5:1 6:1 %zcb_h_uimm 5:1 !function=ex_shift_1 +%zcmp_spimm 2:2 !function=ex_shift_4 +%zcmp_rlist 4:4 # Argument sets imported from insn32.decode: &empty !extern @@ -56,7 +60,9 @@ &u imm rd !extern &shift shamt rs1 rd !extern &r2 rd rs1 !extern +&r2_s rs1 rs2 !extern +&zcmp zcmp_rlist zcmp_spimm # Formats 16: @cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd @@ -98,6 +104,8 @@ @zcb_lh ... . .. ... .. ... .. &i imm=%zcb_h_uimm rs1=%rs1_3 rd=%rs2_3 @zcb_sb ... . .. ... .. ... .. &s imm=%zcb_b_uimm rs1=%rs1_3 rs2=%rs2_3 @zcb_sh ... . .. ... .. ... .. &s imm=%zcb_h_uimm rs1=%rs1_3 rs2=%rs2_3 +@zcmp ... ... ........ .. &zcmp %zcmp_rlist %zcmp_spimm +@cm_mv ... ... ... .. ... .. &r2_s rs2=%sreg2 rs1=%sreg1 # *** RV32/64C Standard Extension (Quadrant 0) *** { @@ -177,6 +185,16 @@ slli 000 . ..... ..... 10 @c_shift2 { sq 101 ... ... .. ... 10 @c_sqsp c_fsd 101 ...... ..... 10 @c_sdsp + + # *** RV64 and RV32 Zcmp Extension *** + [ + cm_push 101 11000 .... .. 10 @zcmp + cm_pop 101 11010 .... .. 10 @zcmp + cm_popret 101 11110 .... .. 10 @zcmp + cm_popretz 101 11100 .... .. 10 @zcmp + cm_mva01s 101 011 ... 11 ... 10 @cm_mv + cm_mvsa01 101 011 ... 01 ... 10 @cm_mv + ] } sw 110 . ..... ..... 10 @c_swsp diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc index de96c4afaf..30b53a9509 100644 --- a/target/riscv/insn_trans/trans_rvzce.c.inc +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -1,5 +1,5 @@ /* - * RISC-V translation routines for the Zcb Standard Extension. + * RISC-V translation routines for the Zc[b,mp] Standard Extensions. * * Copyright (c) 2021-2022 PLCT Lab * @@ -21,6 +21,11 @@ return false; \ } while (0) +#define REQUIRE_ZCMP(ctx) do { \ + if (!ctx->cfg_ptr->ext_zcmp) \ + return false; \ +} while (0) + static bool trans_c_zext_b(DisasContext *ctx, arg_c_zext_b *a) { REQUIRE_ZCB(ctx); @@ -98,3 +103,185 @@ static bool trans_c_sh(DisasContext *ctx, arg_c_sh *a) REQUIRE_ZCB(ctx); return gen_store(ctx, a, MO_UW); } + +#define X_S0 8 +#define X_S1 9 +#define X_Sn 16 + +static uint32_t decode_push_pop_list(DisasContext *ctx, target_ulong rlist) +{ + uint32_t reg_bitmap = 0; + + if (ctx->cfg_ptr->ext_e && rlist > 6) { + return 0; + } + + switch (rlist) { + case 15: + reg_bitmap |= 1 << (X_Sn + 11) ; + reg_bitmap |= 1 << (X_Sn + 10) ; + /* FALL THROUGH */ + case 14: + reg_bitmap |= 1 << (X_Sn + 9) ; + /* FALL THROUGH */ + case 13: + reg_bitmap |= 1 << (X_Sn + 8) ; + /* FALL THROUGH */ + case 12: + reg_bitmap |= 1 << (X_Sn + 7) ; + /* FALL THROUGH */ + case 11: + reg_bitmap |= 1 << (X_Sn + 6) ; + /* FALL THROUGH */ + case 10: + reg_bitmap |= 1 << (X_Sn + 5) ; + /* FALL THROUGH */ + case 9: + reg_bitmap |= 1 << (X_Sn + 4) ; + /* FALL THROUGH */ + case 8: + reg_bitmap |= 1 << (X_Sn + 3) ; + /* FALL THROUGH */ + case 7: + reg_bitmap |= 1 << (X_Sn + 2) ; + /* FALL THROUGH */ + case 6: + reg_bitmap |= 1 << X_S1 ; + /* FALL THROUGH */ + case 5: + reg_bitmap |= 1 << X_S0; + /* FALL THROUGH */ + case 4: + reg_bitmap |= 1 << xRA; + break; + default: + break; + } + + return reg_bitmap; +} + +static bool gen_pop(DisasContext *ctx, arg_zcmp *a, bool ret, bool ret_val) +{ + REQUIRE_ZCMP(ctx); + + uint32_t reg_bitmap = decode_push_pop_list(ctx, a->zcmp_rlist); + if (reg_bitmap == 0) { + return false; + } + + MemOp memop = get_ol(ctx) == MXL_RV32 ? MO_TEUL : MO_TEUQ; + int reg_size = memop_size(memop); + target_ulong stack_adj = ROUND_UP(ctpop32(reg_bitmap) * reg_size, 16) + + a->zcmp_spimm; + TCGv sp = dest_gpr(ctx, xSP); + TCGv addr = tcg_temp_new(); + int i; + + tcg_gen_addi_tl(addr, sp, stack_adj - reg_size); + + for (i = X_Sn + 11; i >= 0; i--) { + if (reg_bitmap & (1 << i)) { + TCGv dest = dest_gpr(ctx, i); + tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop); + gen_set_gpr(ctx, i, dest); + tcg_gen_subi_tl(addr, addr, reg_size); + } + } + + tcg_gen_addi_tl(sp, sp, stack_adj); + gen_set_gpr(ctx, xSP, sp); + + if (ret_val) { + gen_set_gpr(ctx, xA0, ctx->zero); + } + + if (ret) { + TCGv ret_addr = get_gpr(ctx, xRA, EXT_NONE); + gen_set_pc(ctx, ret_addr); + tcg_gen_lookup_and_goto_ptr(); + ctx->base.is_jmp = DISAS_NORETURN; + } + + tcg_temp_free(addr); + return true; +} + +static bool trans_cm_push(DisasContext *ctx, arg_cm_push *a) +{ + REQUIRE_ZCMP(ctx); + + uint32_t reg_bitmap = decode_push_pop_list(ctx, a->zcmp_rlist); + if (reg_bitmap == 0) { + return false; + } + + MemOp memop = get_ol(ctx) == MXL_RV32 ? MO_TEUL : MO_TEUQ; + int reg_size = memop_size(memop); + target_ulong stack_adj = ROUND_UP(ctpop32(reg_bitmap) * reg_size, 16) + + a->zcmp_spimm; + TCGv sp = dest_gpr(ctx, xSP); + TCGv addr = tcg_temp_new(); + int i; + + tcg_gen_subi_tl(addr, sp, reg_size); + + for (i = X_Sn + 11; i >= 0; i--) { + if (reg_bitmap & (1 << i)) { + TCGv val = get_gpr(ctx, i, EXT_NONE); + tcg_gen_qemu_st_tl(val, addr, ctx->mem_idx, memop); + tcg_gen_subi_tl(addr, addr, reg_size); + } + } + + tcg_gen_subi_tl(sp, sp, stack_adj); + gen_set_gpr(ctx, xSP, sp); + + tcg_temp_free(addr); + return true; +} + +static bool trans_cm_pop(DisasContext *ctx, arg_cm_pop *a) +{ + return gen_pop(ctx, a, false, false); +} + +static bool trans_cm_popret(DisasContext *ctx, arg_cm_popret *a) +{ + return gen_pop(ctx, a, true, false); +} + +static bool trans_cm_popretz(DisasContext *ctx, arg_cm_popret *a) +{ + return gen_pop(ctx, a, true, true); +} + +static bool trans_cm_mva01s(DisasContext *ctx, arg_cm_mva01s *a) +{ + REQUIRE_ZCMP(ctx); + + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); + + gen_set_gpr(ctx, xA0, src1); + gen_set_gpr(ctx, xA1, src2); + + return true; +} + +static bool trans_cm_mvsa01(DisasContext *ctx, arg_cm_mvsa01 *a) +{ + REQUIRE_ZCMP(ctx); + + if (a->rs1 == a->rs2) { + return false; + } + + TCGv a0 = get_gpr(ctx, xA0, EXT_NONE); + TCGv a1 = get_gpr(ctx, xA1, EXT_NONE); + + gen_set_gpr(ctx, a->rs1, a0); + gen_set_gpr(ctx, a->rs2, a1); + + return true; +} diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 76d1a9661c..1670319c36 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -738,6 +738,11 @@ static int ex_rvc_register(DisasContext *ctx, int reg) return 8 + reg; } +static int ex_sreg_register(DisasContext *ctx, int reg) +{ + return reg < 2 ? reg + 8 : reg + 16; +} + static int ex_rvc_shiftli(DisasContext *ctx, int imm) { /* For RV128 a shamt of 0 means a shift by 64. */ -- 2.25.1 From MAILER-DAEMON Wed Jan 11 05:40:30 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFYWr-0003ri-RG for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 05:40:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFYWS-0003mX-77; Wed, 11 Jan 2023 05:39:56 -0500 Received: from smtp80.cstnet.cn ([159.226.251.80] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFYWN-0007kt-Gb; Wed, 11 Jan 2023 05:39:55 -0500 Received: from localhost.localdomain (unknown [61.165.33.198]) by APP-01 (Coremail) with SMTP id qwCowABHTTXskb5jCcUADA--.29173S9; Wed, 11 Jan 2023 18:39:46 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v10 7/9] target/riscv: add support for Zcmt extension Date: Wed, 11 Jan 2023 18:39:34 +0800 Message-Id: <20230111103936.129269-8-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230111103936.129269-1-liweiwei@iscas.ac.cn> References: <20230111103936.129269-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: qwCowABHTTXskb5jCcUADA--.29173S9 X-Coremail-Antispam: 1UD129KBjvJXoW3KrWDZF17Jry3JFyUKF1rWFg_yoWDuw1kpF 4rC3y7GrW8JrZ7Aa4fKF45tF15Jw4rG3yUCws3Xws5Ja13JFWrJr1DKw13KF4DXFZ5ur4j 93Z0yFy5CrW8ZFJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBl14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr 1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE14v_Gw1l42 xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWU GwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI4 8JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r4U JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcV C2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbPC7UUUUUU== X-Originating-IP: [61.165.33.198] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.80; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 10:39:56 -0000 Add encode, trans* functions and helper functions support for Zcmt instrutions Add support for jvt csr Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 4 ++ target/riscv/cpu_bits.h | 7 +++ target/riscv/csr.c | 38 +++++++++++++++- target/riscv/helper.h | 3 ++ target/riscv/insn16.decode | 7 ++- target/riscv/insn_trans/trans_rvzce.c.inc | 28 +++++++++++- target/riscv/machine.c | 19 ++++++++ target/riscv/meson.build | 3 +- target/riscv/zce_helper.c | 55 +++++++++++++++++++++++ 9 files changed, 159 insertions(+), 5 deletions(-) create mode 100644 target/riscv/zce_helper.c diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index dc2410269d..798bd081de 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -185,6 +185,8 @@ struct CPUArchState { uint32_t features; + target_ulong jvt; + #ifdef CONFIG_USER_ONLY uint32_t elf_flags; #endif @@ -600,6 +602,8 @@ void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, target_ulong new_val, target_ulong write_mask), void *rmw_fn_arg); + +RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); #endif void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8b0d7e20ea..ce347e5575 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -319,6 +319,7 @@ #define SMSTATEEN_MAX_COUNT 4 #define SMSTATEEN0_CS (1ULL << 0) #define SMSTATEEN0_FCSR (1ULL << 1) +#define SMSTATEEN0_JVT (1ULL << 2) #define SMSTATEEN0_HSCONTXT (1ULL << 57) #define SMSTATEEN0_IMSIC (1ULL << 58) #define SMSTATEEN0_AIA (1ULL << 59) @@ -523,6 +524,9 @@ /* Crypto Extension */ #define CSR_SEED 0x015 +/* Zcmt Extension */ +#define CSR_JVT 0x017 + /* mstatus CSR bits */ #define MSTATUS_UIE 0x00000001 #define MSTATUS_SIE 0x00000002 @@ -894,4 +898,7 @@ typedef enum RISCVException { #define MHPMEVENT_IDX_MASK 0xFFFFF #define MHPMEVENT_SSCOF_RESVD 16 +/* JVT CSR bits */ +#define JVT_MODE 0x3F +#define JVT_BASE (~0x3F) #endif diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e6f8250929..a752e8b215 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -42,8 +42,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) /* Predicates */ #if !defined(CONFIG_USER_ONLY) -static RISCVException smstateen_acc_ok(CPURISCVState *env, int index, - uint64_t bit) +RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit) { bool virt = riscv_cpu_virt_enabled(env); CPUState *cs = env_cpu(env); @@ -163,6 +162,24 @@ static RISCVException ctr32(CPURISCVState *env, int csrno) return ctr(env, csrno); } +static RISCVException zcmt(CPURISCVState *env, int csrno) +{ + RISCVCPU *cpu = env_archcpu(env); + + if (!cpu->cfg.ext_zcmt) { + return RISCV_EXCP_ILLEGAL_INST; + } + +#if !defined(CONFIG_USER_ONLY) + RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT); + if (ret != RISCV_EXCP_NONE) { + return ret; + } +#endif + + return RISCV_EXCP_NONE; +} + #if !defined(CONFIG_USER_ONLY) static RISCVException mctr(CPURISCVState *env, int csrno) { @@ -3980,6 +3997,20 @@ RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, return ret; } +static RISCVException read_jvt(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val = env->jvt; + return RISCV_EXCP_NONE; +} + +static RISCVException write_jvt(CPURISCVState *env, int csrno, + target_ulong val) +{ + env->jvt = val; + return RISCV_EXCP_NONE; +} + /* Control and Status Register function table */ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { /* User Floating-Point CSRs */ @@ -4017,6 +4048,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { /* Crypto Extension */ [CSR_SEED] = { "seed", seed, NULL, NULL, rmw_seed }, + /* Zcmt Extension */ + [CSR_JVT] = {"jvt", zcmt, read_jvt, write_jvt}, + #if !defined(CONFIG_USER_ONLY) /* Machine Timers and Counters */ [CSR_MCYCLE] = { "mcycle", any, read_hpmcounter, diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 227c7122ef..d979f0bfc4 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1136,3 +1136,6 @@ DEF_HELPER_FLAGS_1(aes64im, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_3(sm4ed, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) + +/* Zce helper */ +DEF_HELPER_FLAGS_2(cm_jalt, TCG_CALL_NO_WG, tl, env, i32) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index 4654c23052..c359c574ab 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -49,6 +49,7 @@ %zcb_h_uimm 5:1 !function=ex_shift_1 %zcmp_spimm 2:2 !function=ex_shift_4 %zcmp_rlist 4:4 +%zcmt_index 2:8 # Argument sets imported from insn32.decode: &empty !extern @@ -63,6 +64,7 @@ &r2_s rs1 rs2 !extern &zcmp zcmp_rlist zcmp_spimm +&zcmt zcmt_index # Formats 16: @cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd @@ -106,6 +108,7 @@ @zcb_sh ... . .. ... .. ... .. &s imm=%zcb_h_uimm rs1=%rs1_3 rs2=%rs2_3 @zcmp ... ... ........ .. &zcmp %zcmp_rlist %zcmp_spimm @cm_mv ... ... ... .. ... .. &r2_s rs2=%sreg2 rs1=%sreg1 +@zcmt_jt ... ... ........ .. &zcmt %zcmt_index # *** RV32/64C Standard Extension (Quadrant 0) *** { @@ -186,7 +189,7 @@ slli 000 . ..... ..... 10 @c_shift2 sq 101 ... ... .. ... 10 @c_sqsp c_fsd 101 ...... ..... 10 @c_sdsp - # *** RV64 and RV32 Zcmp Extension *** + # *** RV64 and RV32 Zcmp/Zcmt Extension *** [ cm_push 101 11000 .... .. 10 @zcmp cm_pop 101 11010 .... .. 10 @zcmp @@ -194,6 +197,8 @@ slli 000 . ..... ..... 10 @c_shift2 cm_popretz 101 11100 .... .. 10 @zcmp cm_mva01s 101 011 ... 11 ... 10 @cm_mv cm_mvsa01 101 011 ... 01 ... 10 @cm_mv + + cm_jalt 101 000 ........ 10 @zcmt_jt ] } sw 110 . ..... ..... 10 @c_swsp diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc b/target/riscv/insn_trans/trans_rvzce.c.inc index 30b53a9509..957bd23ead 100644 --- a/target/riscv/insn_trans/trans_rvzce.c.inc +++ b/target/riscv/insn_trans/trans_rvzce.c.inc @@ -1,5 +1,5 @@ /* - * RISC-V translation routines for the Zc[b,mp] Standard Extensions. + * RISC-V translation routines for the Zc[b,mp,mt] Standard Extensions. * * Copyright (c) 2021-2022 PLCT Lab * @@ -26,6 +26,11 @@ return false; \ } while (0) +#define REQUIRE_ZCMT(ctx) do { \ + if (!ctx->cfg_ptr->ext_zcmt) \ + return false; \ +} while (0) + static bool trans_c_zext_b(DisasContext *ctx, arg_c_zext_b *a) { REQUIRE_ZCB(ctx); @@ -285,3 +290,24 @@ static bool trans_cm_mvsa01(DisasContext *ctx, arg_cm_mvsa01 *a) return true; } + +static bool trans_cm_jalt(DisasContext *ctx, arg_cm_jalt *a) +{ + REQUIRE_ZCMT(ctx); + + /* + * Update pc to current for the non-unwinding exception + * that might come from cpu_ld*_code() in the helper. + */ + tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next); + gen_helper_cm_jalt(cpu_pc, cpu_env, tcg_constant_i32(a->zcmt_index)); + + /* c.jt vs c.jalt depends on the index. */ + if (a->zcmt_index >= 32) { + gen_set_gpri(ctx, xRA, ctx->pc_succ_insn); + } + + tcg_gen_lookup_and_goto_ptr(); + ctx->base.is_jmp = DISAS_NORETURN; + return true; +} diff --git a/target/riscv/machine.c b/target/riscv/machine.c index c6ce318cce..3e98b8a53e 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -331,6 +331,24 @@ static const VMStateDescription vmstate_pmu_ctr_state = { } }; +static bool jvt_needed(void *opaque) +{ + RISCVCPU *cpu = opaque; + + return cpu->cfg.ext_zcmt; +} + +static const VMStateDescription vmstate_jvt = { + .name = "cpu/jvt", + .version_id = 1, + .minimum_version_id = 1, + .needed = jvt_needed, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(env.jvt, RISCVCPU), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu = { .name = "cpu", .version_id = 6, @@ -398,6 +416,7 @@ const VMStateDescription vmstate_riscv_cpu = { &vmstate_envcfg, &vmstate_debug, &vmstate_smstateen, + &vmstate_jvt, NULL } }; diff --git a/target/riscv/meson.build b/target/riscv/meson.build index ba25164d74..4bf9c9e632 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -18,7 +18,8 @@ riscv_ss.add(files( 'bitmanip_helper.c', 'translate.c', 'm128_helper.c', - 'crypto_helper.c' + 'crypto_helper.c', + 'zce_helper.c' )) riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c')) diff --git a/target/riscv/zce_helper.c b/target/riscv/zce_helper.c new file mode 100644 index 0000000000..b433bda16d --- /dev/null +++ b/target/riscv/zce_helper.c @@ -0,0 +1,55 @@ +/* + * RISC-V Zcmt Extension Helper for QEMU. + * + * Copyright (c) 2021-2022 PLCT Lab + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "exec/cpu_ldst.h" + +target_ulong HELPER(cm_jalt)(CPURISCVState *env, uint32_t index) +{ + +#if !defined(CONFIG_USER_ONLY) + RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT); + if (ret != RISCV_EXCP_NONE) { + riscv_raise_exception(env, ret, 0); + } +#endif + + target_ulong target; + target_ulong val = env->jvt; + int xlen = riscv_cpu_xlen(env); + uint8_t mode = get_field(val, JVT_MODE); + target_ulong base = val & JVT_BASE; + target_ulong t0; + + if (mode != 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, 0); + } + + if (xlen == 32) { + t0 = base + (index << 2); + target = cpu_ldl_code(env, t0); + } else { + t0 = base + (index << 3); + target = cpu_ldq_code(env, t0); + } + + return target & ~0x1; +} -- 2.25.1 From MAILER-DAEMON Wed Jan 11 05:40:32 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFYX0-0003uf-96 for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 05:40:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFYWQ-0003kH-DJ; Wed, 11 Jan 2023 05:39:54 -0500 Received: from smtp80.cstnet.cn ([159.226.251.80] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFYWM-0007kC-AG; Wed, 11 Jan 2023 05:39:54 -0500 Received: from localhost.localdomain (unknown [61.165.33.198]) by APP-01 (Coremail) with SMTP id qwCowABHTTXskb5jCcUADA--.29173S6; Wed, 11 Jan 2023 18:39:43 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v10 4/9] target/riscv: add support for Zcd extension Date: Wed, 11 Jan 2023 18:39:31 +0800 Message-Id: <20230111103936.129269-5-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230111103936.129269-1-liweiwei@iscas.ac.cn> References: <20230111103936.129269-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: qwCowABHTTXskb5jCcUADA--.29173S6 X-Coremail-Antispam: 1UD129KBjvJXoW7Aw1UuFW8GF1kWr4fJrW5KFg_yoW8Kr47pF 18Cw47GFW5GryfZa13tF43JF1UJFs3Gry8t39Iywn5Gay5GF45Zr1UtFy3tr4UXFZ7Zr1Y kF1DA3y3C395trDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBv14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr 1l84ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0D M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7MxkIecxEwVAFwVW8twCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l IxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4 A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUQFxUUUUUU= X-Originating-IP: [61.165.33.198] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.80; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 10:39:54 -0000 Separate c_fld/c_fsd from fld/fsd to add additional check for c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse their encodings Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode | 8 ++++---- target/riscv/insn_trans/trans_rvd.c.inc | 18 ++++++++++++++++++ 2 files changed, 22 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn16.decode b/target/riscv/insn16.decode index f3ea650325..b62664b6af 100644 --- a/target/riscv/insn16.decode +++ b/target/riscv/insn16.decode @@ -97,12 +97,12 @@ } { lq 001 ... ... .. ... 00 @cl_q - fld 001 ... ... .. ... 00 @cl_d + c_fld 001 ... ... .. ... 00 @cl_d } lw 010 ... ... .. ... 00 @cl_w { sq 101 ... ... .. ... 00 @cs_q - fsd 101 ... ... .. ... 00 @cs_d + c_fsd 101 ... ... .. ... 00 @cs_d } sw 110 ... ... .. ... 00 @cs_w @@ -148,7 +148,7 @@ addw 100 1 11 ... 01 ... 01 @cs_2 slli 000 . ..... ..... 10 @c_shift2 { lq 001 ... ... .. ... 10 @c_lqsp - fld 001 . ..... ..... 10 @c_ldsp + c_fld 001 . ..... ..... 10 @c_ldsp } { illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0 @@ -166,7 +166,7 @@ slli 000 . ..... ..... 10 @c_shift2 } { sq 101 ... ... .. ... 10 @c_sqsp - fsd 101 ...... ..... 10 @c_sdsp + c_fsd 101 ...... ..... 10 @c_sdsp } sw 110 . ..... ..... 10 @c_swsp diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc index 6e3159b797..47849ffdfd 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -31,6 +31,12 @@ } \ } while (0) +#define REQUIRE_ZCD(ctx) do { \ + if (!ctx->cfg_ptr->ext_zcd) { \ + return false; \ + } \ +} while (0) + static bool trans_fld(DisasContext *ctx, arg_fld *a) { TCGv addr; @@ -59,6 +65,18 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) return true; } +static bool trans_c_fld(DisasContext *ctx, arg_fld *a) +{ + REQUIRE_ZCD(ctx); + return trans_fld(ctx, a); +} + +static bool trans_c_fsd(DisasContext *ctx, arg_fsd *a) +{ + REQUIRE_ZCD(ctx); + return trans_fsd(ctx, a); +} + static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a) { REQUIRE_FPU; -- 2.25.1 From MAILER-DAEMON Wed Jan 11 05:40:34 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFYX3-0003yA-7O for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 05:40:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFYWV-0003oz-Tn; Wed, 11 Jan 2023 05:40:03 -0500 Received: from smtp80.cstnet.cn ([159.226.251.80] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pFYWT-0007mk-Tc; Wed, 11 Jan 2023 05:39:59 -0500 Received: from localhost.localdomain (unknown [61.165.33.198]) by APP-01 (Coremail) with SMTP id qwCowABHTTXskb5jCcUADA--.29173S10; Wed, 11 Jan 2023 18:39:46 +0800 (CST) From: Weiwei Li To: richard.henderson@linaro.org, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v10 8/9] target/riscv: expose properties for Zc* extension Date: Wed, 11 Jan 2023 18:39:35 +0800 Message-Id: <20230111103936.129269-9-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230111103936.129269-1-liweiwei@iscas.ac.cn> References: <20230111103936.129269-1-liweiwei@iscas.ac.cn> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID: qwCowABHTTXskb5jCcUADA--.29173S10 X-Coremail-Antispam: 1UD129KBjvJXoW7uw1fCFWDtw48XF4UZFWxXrb_yoW8uF47pr y5Ga47Kw15Jr13Gwn3tr1DJ3yrGw4rA3s7K3ySv3Z7XrZ3KrZrX3ZrC39rW3yftF4rZr4S gF13Zr1xCrs5ta7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBl14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr 1UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq 3wAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7 IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4U M4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE14v_Gw1l42 xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWU GwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI4 8JMIIF0xvE2Ix0cI8IcVAFwI0_JFI_Gr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26F4j6r4U JwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Jr0_Gr1lIxAIcV C2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbPC7UUUUUU== X-Originating-IP: [61.165.33.198] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.80; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 10:40:04 -0000 Expose zca,zcb,zcf,zcd,zcmp,zcmt properties Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 39ab7e46d3..6df667805f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -81,6 +81,12 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), + ISA_EXT_DATA_ENTRY(zca, true, PRIV_VERSION_1_12_0, ext_zca), + ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb), + ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf), + ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd), + ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp), + ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt), ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), @@ -1135,6 +1141,13 @@ static Property riscv_cpu_extensions[] = { /* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), + + DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), + DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), + DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false), + DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false), + DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false), + DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), /* ePMP 0.9.3 */ DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), -- 2.25.1 From MAILER-DAEMON Wed Jan 11 06:37:54 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFZQY-0007Xg-No for mharc-qemu-riscv@gnu.org; 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Wed, 11 Jan 2023 03:37:49 -0800 (PST) Message-ID: <466be876-011f-40b3-8d2b-7ddd64fecded@linaro.org> Date: Wed, 11 Jan 2023 12:37:47 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v4 10/36] tcg/tci: Fix big-endian return register ordering Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net References: <20230108023719.2466341-1-richard.henderson@linaro.org> <20230108023719.2466341-11-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230108023719.2466341-11-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 11:37:53 -0000 On 8/1/23 03:36, Richard Henderson wrote: > We expect the backend to require register pairs in > host-endian ordering, thus for big-endian the first > register of a pair contains the high part. > We were forcing R0 to contain the low part for calls. > > Signed-off-by: Richard Henderson > --- > tcg/tci.c | 21 +++++++++++---------- > 1 file changed, 11 insertions(+), 10 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Wed Jan 11 06:41:22 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFZTl-0000B9-IT for mharc-qemu-riscv@gnu.org; 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Wed, 11 Jan 2023 03:41:02 -0800 (PST) Message-ID: <4aa7f3f1-551e-edf3-c1e1-1604fc42d3f4@linaro.org> Date: Wed, 11 Jan 2023 12:41:01 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v4 14/36] tcg: Add basic data movement for TCGv_i128 Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net References: <20230108023719.2466341-1-richard.henderson@linaro.org> <20230108023719.2466341-15-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230108023719.2466341-15-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 11:41:12 -0000 On 8/1/23 03:36, Richard Henderson wrote: > Add code generation functions for data movement between > TCGv_i128 (mov) and to/from TCGv_i64 (concat, extract). > > Signed-off-by: Richard Henderson > --- > include/tcg/tcg-op.h | 4 ++++ > tcg/tcg-internal.h | 13 +++++++++++++ > tcg/tcg-op.c | 20 ++++++++++++++++++++ > 3 files changed, 37 insertions(+) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Wed Jan 11 09:21:51 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFbzD-000820-Is for mharc-qemu-riscv@gnu.org; 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boundary="000000000000db2c1205f1fdb778" Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=stagethalescristal@gmail.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 14:21:44 -0000 --000000000000db2c1205f1fdb778 Content-Type: text/plain; charset="UTF-8" Hello, Sorry in advance if this is not the right way to do it but I'm a student and not very used to this kind of stuff (first mailing list). I'm trying to run qemu for the Microchip PolarFire SoC Icicle kit but I'm facing a few issues and the wiki page about that seems obsolete. I follow almost exactly what the wiki does (except I use a terminal as a tty instead of the socket bc it didn't work) but my HSS won't boot on versions more recent than 2020.10 or 0.99.12. However I can't find any image compatible for versions older than 2020.10 or 0.99.12 (mines hang at "starting kernel ...". Is there any newer version of the tutorial ? Or does anyone have an idea on how to deal with this issue and use qemu for newer versions of the HSS ? Thanks for your help. --000000000000db2c1205f1fdb778 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hello,
Sorry in advance if this is not the = right way to do it but I'm a student and not very used to this kind of = stuff (first mailing list).
I'm trying to run qemu for the Mi= crochip PolarFire SoC Icicle kit but I'm facing a few issues and the wi= ki page about that seems obsolete.
I follow almost exactly what t= he wiki does (except I use a terminal as a tty instead of the socket bc it = didn't work) but my HSS won't boot on versions more recent than 202= 0.10 or 0.99.12.
However I can't find any image compatib= le for versions older than 2020.10 or 0.99.12 (mines hang at "starting= kernel ...".
Is there any newer version of the tutorial ? O= r does anyone have an idea on how to deal with this issue and use qemu for = newer versions of the HSS ?

Thanks for your help.<= br>
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([2607:fb90:8062:d32d:5ad4:bcd:2063:a06]) by smtp.gmail.com with ESMTPSA id m20-20020ac866d4000000b003a6a7a20575sm7661969qtp.73.2023.01.11.07.06.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Jan 2023 07:06:58 -0800 (PST) Message-ID: <7ba0bf63-1b46-7f70-a0ff-6d62cc963d4f@linaro.org> Date: Wed, 11 Jan 2023 07:06:53 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v4 03/36] tcg: Allocate objects contiguously in temp_allocate_frame Content-Language: en-US To: =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, qemu-devel@nongnu.org References: <20230108023719.2466341-1-richard.henderson@linaro.org> <20230108023719.2466341-4-richard.henderson@linaro.org> <87zgapl7az.fsf@linaro.org> From: Richard Henderson In-Reply-To: <87zgapl7az.fsf@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::832; envelope-from=richard.henderson@linaro.org; helo=mail-qt1-x832.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 15:07:23 -0000 On 1/11/23 01:59, Alex Bennée wrote: >> @@ -3277,13 +3278,26 @@ static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) >> tcg_raise_tb_overflow(s); >> } >> s->current_frame_offset = off + size; >> - >> - ts->mem_offset = off; >> #if defined(__sparc__) >> - ts->mem_offset += TCG_TARGET_STACK_BIAS; >> + off += TCG_TARGET_STACK_BIAS; >> #endif >> - ts->mem_base = s->frame_temp; >> - ts->mem_allocated = 1; >> + >> + /* If the object was subdivided, assign memory to all the parts. */ >> + if (ts->base_type != ts->type) { >> + int part_size = tcg_type_size(ts->type); >> + int part_count = size / part_size; >> + >> + ts -= ts->temp_subindex; > > Whats going on here? Are we jumping to a previous temp? What guarentees > there is something at ts - ts->temp_subindex? Yes. Guaranteed by base_type != type. See tcg_temp_new_internal -- it's the raison d'être of temp_subindex. r~ From MAILER-DAEMON Wed Jan 11 10:52:02 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFdOU-00023l-Li for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 10:52:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFdOS-00021j-03 for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 10:52:00 -0500 Received: from mail-oa1-x31.google.com ([2001:4860:4864:20::31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFdOQ-0007qN-GE for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 10:51:59 -0500 Received: by mail-oa1-x31.google.com with SMTP id 586e51a60fabf-1322d768ba7so15950114fac.5 for ; Wed, 11 Jan 2023 07:51:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=WwVMr3DCxLXykOzNi+Px+mDON8RyJnPpnV4piDeP7As=; b=HjsYNdxtu4nvATuGxqJUATWGo9P8uXS63XFkR5e2WT1lNz8eQ+Ki4NLi9xqUSoBFGe tLeqhte/cCcUI8fMkyC7x3Ckk3Q0w0MhhmmviSeD5ryWNkn1Lyrwu4KJlXEI6GtDu6J9 VZuNkeaOZM1yoNtk5Z6kqcv/ZodXuUpSto1QgLWH5U70BwOqmnNuLhl5bVcpAaKhM0w3 /PZoHHmolDyT7DSjTML+8WfWyor6a67RSuxyyrU18Dy3NnV7MA87GENX83LYYod2Zjz7 GY2NpSkHSCtzFA3pKL3zqkhetHGHFxelYDexQ+qC5AiQyEq5ST2EDQstHagN+Et8rkgm MaKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=WwVMr3DCxLXykOzNi+Px+mDON8RyJnPpnV4piDeP7As=; b=zAAaJp8MOdSfQndQMZmw+obOuTkdR3KU/jxBMDYA0LzKcs7GlE+LNt2rjvQ14AWOWd uu/dT5Ol+EwMe1wxYQUiUKB4mLzgBw9gvd3I+JoKSFJ/WyWSGUqFVmV8RGE7ypw1XMH7 esYxwLCkqCXqUfqO9SKUwvVj3VRHOMoYcIQFuAGRwXlH7cTejCSu3MPb2KQExl0sMC4j nOPn0QrAEsSJNTLJZe6GVG8Ogu8MysfEOob4hXNb0Kg8bGWw+rDLdYwfJx8sNUBZD7iJ oSMqBENx6SI2HSOlbJOigptkmfHbtk1xg4l6MnO0QgYreg8YmWV54LAHfTa2htGkpSWR HIyw== X-Gm-Message-State: AFqh2kpVnF5qwIMU1xyM1RDpRWu7MZ9s869GQKLNWPQDP2ssR/G5Aizr p2RiwJXr+ZadxLbPwp8VIHRhug== X-Google-Smtp-Source: AMrXdXuE+eMd1GxgNIo2lxDmKGRFEhh3xAQvlEJjTqGLv49KGUgd/jbOzu6r1pGFhfWmNQuGbaFvng== X-Received: by 2002:a05:6870:5885:b0:14f:b76d:bce4 with SMTP id be5-20020a056870588500b0014fb76dbce4mr30123726oab.24.1673452316489; Wed, 11 Jan 2023 07:51:56 -0800 (PST) Received: from [192.168.68.107] ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id y6-20020a056870418600b00144e18d8525sm7426264oac.25.2023.01.11.07.51.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Jan 2023 07:51:55 -0800 (PST) Message-ID: <46284293-8a49-36f4-c52e-4a976d8b0591@ventanamicro.com> Date: Wed, 11 Jan 2023 12:51:53 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH 1/2] target/riscv/cpu: set cpu->cfg in register_cpu_props() Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com References: <20230110201405.247785-1-dbarboza@ventanamicro.com> <20230110201405.247785-2-dbarboza@ventanamicro.com> From: Daniel Henrique Barboza In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 15:52:00 -0000 On 1/11/23 02:39, Richard Henderson wrote: > On 1/10/23 12:14, Daniel Henrique Barboza wrote: >> +/* >> + * Register CPU props based on env.misa_ext. If a non-zero >> + * value was set, register only the required cpu->cfg.ext_* >> + * properties and leave. env.misa_ext = 0 means that we want >> + * all the default properties to be registered. >> + */ >>   static void register_cpu_props(DeviceState *dev) > > Suggest invoking this as .instance_post_init hook on TYPE_RISCV_CPU. > Then you don't need to manually call it on every cpu class. That would be nice but we have code such as: @@ -317,7 +310,6 @@ static void rv32_sifive_e_cpu_init(Object *obj)      RISCVCPU *cpu = RISCV_CPU(obj);      set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);      register_cpu_props(DEVICE(obj));      set_priv_version(env, PRIV_VERSION_1_10_0);      cpu->cfg.mmu = false; <=========== That are setting cpu->cfg attrs after register_cpu_props(), i.e. "I want the defaults and these specific settings on top of it". I can think of a few ways to add a a post_init hook to reduce this code repetition but I'll need to play around with it a bit first. Thanks, Daniel > > > r~ From MAILER-DAEMON Wed Jan 11 11:41:02 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFe9u-0006qS-3b for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 11:41:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFe9s-0006p7-Sa for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 11:41:00 -0500 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFe9r-0008Ms-0f for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 11:41:00 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E68F161D54; Wed, 11 Jan 2023 16:40:50 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id A7FD6C433F0; Wed, 11 Jan 2023 16:40:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673455250; bh=mJ7/OhXpyeQ5K/mRmb5v6laD26dU5T1KftFHjraeFWE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=GIcmbO7xasBapmKjxzmIEcEOI2gi48V3dukzry4lLZZT9w1Q6oeN4OE12Yvl2MZEm RSXn4XB9PoENVTZjT0XV2oGTYAb68doJeE4w9qkmtFDXIV8uSjR6B3ZvZeDmxnrsMD JExZFWGX3XZ+K/198Q+TY04qogm7S9rlX3nahE4h3G3tnzKLsDE89HSjClaMhJ83Fm 06c8idODsAObYzG45klE39+LQFx88V+ECgu4ctmTAKxAuO0ogO+k0s+Gq2yqC6Y1D8 KZUhI6s9aMPM6e3rH3AgwoL/eooDmy2S8HpYavCrD728F60a+UfY/HSszznpy18NPP lErCpoYP78kcw== Date: Wed, 11 Jan 2023 16:40:47 +0000 From: Conor Dooley To: stage TC Cc: qemu-riscv@nongnu.org Subject: Re: qemu icicle kit es Message-ID: References: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="VBWWAWZsjmo5LLEM" Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2604:1380:4641:c500::1; envelope-from=conor@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 16:41:01 -0000 --VBWWAWZsjmo5LLEM Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Jan 11, 2023 at 03:21:26PM +0100, stage TC wrote: > Hello, > Sorry in advance if this is not the right way to do it but I'm a student > and not very used to this kind of stuff (first mailing list). Don't worry, you are doing fine :) > I'm trying to run qemu for the Microchip PolarFire SoC Icicle kit but I'm > facing a few issues and the wiki page about that seems obsolete. I must admit, it's a long time since I tried to use a v2020.x release of any MPFS software. Last time I did give the steps in the docs a go, with a suitably vintage version of QEMU, things worked as expected. However, using more recent versions of QEMU I ran into some problems with the sd/mmc emulation & never get into U-Boot. > I follow almost exactly what the wiki does (except I use a terminal as a > tty instead of the socket bc it didn't work) but my HSS won't boot on > versions more recent than 2020.10 or 0.99.12. What does "my HSS won't boot" mean? E.g: - Does the MICROCHIP logo banner appear (if it existed back then!)? If it didnt, the version string I think was. - Does the HSS console appear? - Does it fail to launch the next bootloader stage? > However I can't find any image compatible for versions older than 2020.10 > or 0.99.12 (mines hang at "starting kernel ...". By that do you mean you cannot find a pre-built yocto image? I am not sure that there are any that pre-date the one linked in the wiki that are still available, as those on GitHub only go back as far as v2021.02 > Is there any newer version of the tutorial ? Or does anyone have an idea on > how to deal with this issue and use qemu for newer versions of the HSS ? I do my testing with something like: $(QEMU)/qemu-system-riscv64 \ -M microchip-icicle-kit \ -m 2G -smp 5 \ -kernel $(vmlinux_bin) \ -dtb $(devkit).dtb \ -initrd $(initramfs) \ -display none \ -serial null \ -serial stdio This loads a kernel directly rather than using the HSS - for recent versions of the HSS, implementations of some peripherals need to be added, for example, it checks things like the cache configuration during boot, which are not emulated in QEMU. For that reason, I've stuck with doing direct kernel boots. Linux v6.0.18 (and the associated devicetree) is the most recent combination that I have booted unmodified using the master branch of QEMU using this method. More recent (linux) kernels come with a device tree that will require changes in QEMU to support & I have unfortunately not had the time to work on that recently. Sorry that I am really of no help to you. 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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x18-20020a4ac592000000b004a3543fbfbbsm7214974oop.14.2023.01.11.09.09.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 09:09:54 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH 00/10] riscv: create_fdt() related cleanups Date: Wed, 11 Jan 2023 14:09:38 -0300 Message-Id: <20230111170948.316276-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c41; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc41.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 17:09:57 -0000 Hi, This is a follow-up of: "[PATCH v5 00/11] riscv: OpenSBI boot test and cleanups" Patches were based on top of riscv-to-apply.next [1] + the series above. The recent FDT changes made in hw/riscv (all machines are now using the FDT via MachineState::fdt) allowed for most of the cleanups made here. Patches 9 and 10 were based on a suggestion made by Phil a few weeks ago. I decided to go for it. [1] https://github.com/alistair23/qemu/tree/riscv-to-apply.next Daniel Henrique Barboza (10): hw/riscv/spike.c: simplify create_fdt() hw/riscv/virt.c: simplify create_fdt() hw/riscv/sifive_u.c: simplify create_fdt() hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus() hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() hw/riscv: simplify riscv_load_fdt() hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' hw/riscv/boot.c | 4 +- hw/riscv/microchip_pfsoc.c | 4 +- hw/riscv/numa.c | 14 +- hw/riscv/sifive_u.c | 11 +- hw/riscv/spike.c | 25 +- hw/riscv/virt.c | 484 +++++++++++++++++++------------------ include/hw/riscv/boot.h | 2 +- include/hw/riscv/numa.h | 10 +- 8 files changed, 277 insertions(+), 277 deletions(-) -- 2.39.0 From MAILER-DAEMON Wed Jan 11 12:10:01 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFebw-0002Ws-Qs for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 12:10:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFebv-0002SP-GT for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 12:09:59 -0500 Received: from mail-oo1-xc2f.google.com ([2607:f8b0:4864:20::c2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFebt-00068W-S1 for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 12:09:59 -0500 Received: by mail-oo1-xc2f.google.com with SMTP id 187-20020a4a09c4000000b004d8f3cb09f5so4196269ooa.6 for ; Wed, 11 Jan 2023 09:09:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ee4ykpWvS9vCAX6jduEVuqgjn4tTXtGMZ/j/etyizQI=; b=Xciz4c5//fY9jmbrOEF5QX5b82dLRCI5F+p3/ta4URE5gBffRmwupyU0Wq+aWSzXHM 7PZoYri9UJAGP9ozujEbvWMdtBPzEhN8QIHiAlPWGdvq7KL0zuLV07npdIifrok86xKr S9T4Js8yoI2WDfW/raqdgPbg1hp48waIxB1UG1TnPyP7A2yo6AaTRnmCZROdIahnkDgI jNtNpyHg4WRVeUM1+dljIhpAJFnwbMgTnF3nQUUp/rFdeETTZ/84FSjDYACgG8VODPOD AJTYhuaFXD3YNlzc32b3OCAE/xZ7zcpQeycHZZl35pHDEhDt3hMYV9W0Fjij7nbLLxkA 9Agw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ee4ykpWvS9vCAX6jduEVuqgjn4tTXtGMZ/j/etyizQI=; b=u6cwncKVUKU4GjBfNu54VfdtLy/u9Uwju2t7OY1LH3M5Z0oF7UWO3WO75OBmbCPXe7 Xpw4F/uvW1HjCiXZuPVT5PaMbMuM7aJRA8CsUn0kOfR0ceZuh11qUShKEouMeNYwz/HS hDZCG/VAjEkyij0I6n0vdIYoXgW/3z+SI3XOZlbTS2icRQ1ky1z/2v+CYqHtuBLBmlyn OlbCXUrrsW6AS1k+rMO6oKuEnqk3MC1OxhGCap3vJmt+IBltpKA/lBfjWky+VegI2dzK XLQBw7mI0QOlIasgKPEmYj1A2PGp1Nd2RSYCuLfetjQ9IseduiX2AYWtpb5BrdJhuY/F DNIw== X-Gm-Message-State: AFqh2kplTWR82zfyfVVGwsyp1GK5Fh+Y5ONb1XwtHmQWZf58YHiYwoVu +sDQIQ2E5TV+JMplZXi92B0nXA== X-Google-Smtp-Source: AMrXdXuRKJEuzXU5ClXUt6z7xQTvD/jJq/aFi1pBpKC9s2BLFCsvzGgsNpZlmrRt+ERoEtBceyF4xA== X-Received: by 2002:a4a:3712:0:b0:4c9:f4e1:afe0 with SMTP id r18-20020a4a3712000000b004c9f4e1afe0mr16481964oor.1.1673456996582; Wed, 11 Jan 2023 09:09:56 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x18-20020a4ac592000000b004a3543fbfbbsm7214974oop.14.2023.01.11.09.09.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 09:09:56 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH 01/10] hw/riscv/spike.c: simplify create_fdt() Date: Wed, 11 Jan 2023 14:09:39 -0300 Message-Id: <20230111170948.316276-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> References: <20230111170948.316276-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 17:09:59 -0000 'mem_size' and 'cmdline' are unused. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/spike.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index c517885e6e..4a66016d69 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -49,7 +49,6 @@ static const MemMapEntry spike_memmap[] = { }; static void create_fdt(SpikeState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_bit, bool htif_custom_base) { void *fdt; @@ -299,8 +298,7 @@ static void spike_board_init(MachineState *machine) } /* Create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc[0]), htif_custom_base); + create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base); /* Load kernel */ if (machine->kernel_filename) { -- 2.39.0 From MAILER-DAEMON Wed Jan 11 12:10:05 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFec1-0002hN-7P for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 12:10:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFeby-0002bO-P6 for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 12:10:02 -0500 Received: from mail-oo1-xc2c.google.com ([2607:f8b0:4864:20::c2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFebw-00069D-0w for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 12:10:02 -0500 Received: by mail-oo1-xc2c.google.com with SMTP id d16-20020a4a5210000000b004f23d1aea58so426936oob.3 for ; Wed, 11 Jan 2023 09:09:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H4dXSiAnits5ErKwehcEjsLRKL1HaEAOZOXpk41ZAWU=; b=S2SERipg15y4IXl848CDa/ZgPj93Ezd31PiqNY6UifDVOKt8+PtFjIRJ+YFbmvlfMt ilfO0BKD7nA9BayltTgbkk6dzEuSzUX5LhX8pRAD/PwJpXV32u1N2xxQ7K/ceuSLicY5 pW0BDy6n1Mspx2zgytrAGJ3tUlubV/Gf3mc7VXukaD5ESQPF6pLiK/dpdq9/qS7kvZgK NhC4GPbl1YcjnrHWNfFtr0C4o5uyPpj+9usENog+pEGZUkMgUr0fOwxmIxLOdWqusD99 F3Oipcy30cfKR8s+RjrIGzES/UCipiEico6+BgW6VRizC3lgu6Fk8eURLWJD65kYAnXM vQYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H4dXSiAnits5ErKwehcEjsLRKL1HaEAOZOXpk41ZAWU=; b=DtCrg8sVvJn/PIpiIXqxkAtvyECSIORRVlRaH9JitvdiP1nzsZGom+HgN04AxXsh1Y 0xlXMamh8PxOOzG2fIT3Pe1+Z7qxIdxlmNPPp7deb6cE83gNp5wZZp0bIeaag8UWhu2a UJ2fJqZ2mtl0s33b9jMPDrdXqxZR/M+9nkXlD+vEWM15cXDOrX2ceyfvqXEv99aw2sgR eo3OjtrewvDEsYvb2UDncMVDp2tPADP34Pxdq6RVNqX6zgy4N73jW65/1dTW7vVQVDys 3D7n0HgCC3tYCF/o7rRtkQPO3W/QVWYj4lJZzRJAKI2edaCsHcsP9WBqeWAo8pHb4H3d sNvA== X-Gm-Message-State: AFqh2kp2kNJocyu354nIv+xSuJB7idGl9do766Bdc/hqQ2CPx5SXkUFG /YWvPi1yUOV35ye+GfYljtJbqg== X-Google-Smtp-Source: AMrXdXvSNJiFv6PAv/N1Lp1vE3Zk7qxb0XYZV9mpGlEv1cDhWfkN6GxK1apcwCjsKnLiU0y12CIyjA== X-Received: by 2002:a4a:ca93:0:b0:49f:8720:d5b2 with SMTP id x19-20020a4aca93000000b0049f8720d5b2mr30777123ooq.8.1673456998770; Wed, 11 Jan 2023 09:09:58 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x18-20020a4ac592000000b004a3543fbfbbsm7214974oop.14.2023.01.11.09.09.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 09:09:58 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH 02/10] hw/riscv/virt.c: simplify create_fdt() Date: Wed, 11 Jan 2023 14:09:40 -0300 Message-Id: <20230111170948.316276-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> References: <20230111170948.316276-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c2c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 17:10:03 -0000 'mem_size' and 'cmdline' aren't being used. Remove them. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index a931ed05ab..89c99ec1af 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -999,7 +999,7 @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) } static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_bit) + bool is_32_bit) { MachineState *mc = MACHINE(s); uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; @@ -1499,8 +1499,7 @@ static void virt_machine_init(MachineState *machine) virt_flash_map(s, system_memory); /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc[0])); + create_fdt(s, memmap, riscv_is_32bit(&s->soc[0])); s->machine_done.notify = virt_machine_done; qemu_add_machine_init_done_notifier(&s->machine_done); -- 2.39.0 From MAILER-DAEMON Wed Jan 11 12:10:07 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFec2-0002i2-JL for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 12:10:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFec0-0002h9-PS for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 12:10:04 -0500 Received: from mail-oo1-xc36.google.com ([2607:f8b0:4864:20::c36]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFeby-00069z-HE for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 12:10:03 -0500 Received: by mail-oo1-xc36.google.com with SMTP id s10-20020a4aa54a000000b004f240f120b3so380692oom.1 for ; Wed, 11 Jan 2023 09:10:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DPONLIzIEy/3UQV9VjMXIl8RnUsRqK9vSoHXVRNeILc=; b=o4RMcKEM7PDjq66qO5ILPI4+50kxiFwI1Qe7/NK+PYZwMwomH1BdDsFsViq2FyUc7E 59G+XFjDpG5hRBhzORLsWsAD/FCVQ4mXTU6yuy/BoiuljzNNLZSfPrJU6FeWoL+MLdqe edOkc/X+gDqDkGCoOViLmIHU3k4XDVt01N5GawsbHz6sYp4GkiLrx/k28wd3hd90/+lW gGuYrPN4cLBXRfWXnF3zTDH1BiRD3FTrNccU4ucWBUxuu0QLfJvgJpRgpT6qcEaQBtbX Bs6WypDDjtA6P0jxh/3F8hFl2KIRhCOoeK13wcycemwIQewBbdjkQO9JBmACeopw4JLi Vzuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DPONLIzIEy/3UQV9VjMXIl8RnUsRqK9vSoHXVRNeILc=; b=258dPOXBQA/ytUYhOxkU2+9u/LAx1ohbRNTl0TD4fLoZlVQCHlDCDu4/B0l3m7rUwz 8J8lTRuz2Fm9QZ/mP4rMXHLSGa83iDQImkdA1Iw62UyqnBLpfdH/NiWfKujlqSMYPwNQ KWx6PlhL9Xr1MyeYzfrzmTkV2Nn39ziJZKXsvc8tajn/mzuCHAnSTQ38nzxakkm7ib/u KvaX9sVC/1Bijpmd4nVJ4th9Ft7V9ZcZcRNlmhZtKuc4PeYYQ2pT/HEnXnY3IiMMMLmx avTSJdULCRQ75VAjPqddIp+24TKpflVETdfRHF+gIRouUAoV7Sar6E1MK3Muvj9C3TH5 AxAw== X-Gm-Message-State: AFqh2krfx3qxVdRIVRfKuq2NtMJy17fsaH/D1t5IndtHpMSuBPBhJwp2 Sez/8b0RihjGiDSL/UX7AgTPfUz3jL9YvN3273A= X-Google-Smtp-Source: AMrXdXtkfl4QADQqITJKwHm1S6GlYPwmAjvPaTnw/pJumAF+OIalE1qpkaIG700gZO40KIBXte7erw== X-Received: by 2002:a4a:dbd8:0:b0:4a0:bc7f:462c with SMTP id t24-20020a4adbd8000000b004a0bc7f462cmr31480242oou.9.1673457001365; Wed, 11 Jan 2023 09:10:01 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x18-20020a4ac592000000b004a3543fbfbbsm7214974oop.14.2023.01.11.09.09.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 09:10:00 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Palmer Dabbelt Subject: [PATCH 03/10] hw/riscv/sifive_u.c: simplify create_fdt() Date: Wed, 11 Jan 2023 14:09:41 -0300 Message-Id: <20230111170948.316276-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> References: <20230111170948.316276-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 17:10:05 -0000 'cmdline' isn't being used. Remove it. A MachineState pointer is being retrieved via a MACHINE() macro calling qdev_get_machine(). Use MACHINE(s) instead to avoid calling qdev(). 'mem_size' is being set as machine->ram_size by the caller. Retrieve it via ms->ram_size. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza --- hw/riscv/sifive_u.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9a75d4aa62..ccad386920 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -94,9 +94,10 @@ static const MemMapEntry sifive_u_memmap[] = { #define GEM_REVISION 0x10070109 static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, - uint64_t mem_size, const char *cmdline, bool is_32_bit) + bool is_32_bit) { - MachineState *ms = MACHINE(qdev_get_machine()); + MachineState *ms = MACHINE(s); + uint64_t mem_size = ms->ram_size; void *fdt; int cpu, fdt_size; uint32_t *cells; @@ -560,8 +561,7 @@ static void sifive_u_machine_init(MachineState *machine) qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); /* create device tree */ - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, - riscv_is_32bit(&s->soc.u_cpus)); + create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus)); if (s->start_in_flash) { /* -- 2.39.0 From MAILER-DAEMON Wed Jan 11 12:10:15 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFec6-0002jX-D3 for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 12:10:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFec2-0002i9-PC for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 12:10:07 -0500 Received: from mail-oa1-x2c.google.com ([2001:4860:4864:20::2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFec0-0006JK-Hb for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 12:10:05 -0500 Received: by mail-oa1-x2c.google.com with SMTP id 586e51a60fabf-1442977d77dso16194446fac.6 for ; Wed, 11 Jan 2023 09:10:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3Dkt8d3SpLodgKfYwmKReWsLo4BoLEeY7LR0KGeK3q0=; b=NlWShxDXsW+93CsfYq174mztRukMpbkfKqqgKWdMNucAqeovFx8qPOYlEXbDYV7biS ckttsNqmjrE3lwn9u4pZhuT8F70NxqwpjmP2P+9wvwq6aNW1OWYN4VmvmygpqHMZJJJT 8JtUPb57n/msVQ64XlqJ65g15vR8I8z8moGozxOdZP1YcE4CjB1mqmnSGmMdK67m4xRN EhWdweojEgyHysqqeP/SrTJrwSJzET3nch+vdAe0wEusU8Rf9WiMdmjaTYbJW455Lp8J XFgF3mAdGEWkzo1v1MywqV5PtZnQIdIuuQJ4qC5/kPXep5t5RmRU3ZQdibIyw81APsfh Ju/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3Dkt8d3SpLodgKfYwmKReWsLo4BoLEeY7LR0KGeK3q0=; b=gElHAXnjjArlevWVdRn/VsAmn2YGcOZ0oZVhz+eNraqFhFFpibaau6dIQqDQgzPK7I g/ajOuyBm3yuSCMeXsvnS60M2wTeCkmk7yjGRVfihejkkRYJYFcDpa0kP4WhznBZDes6 PTm4yTkNH0dLxqUvCIxMG3CEaq3x+DG9tVV2IyoAAq5CH8pfyU8V4EOXW/SlcpQmdV7l g525bIKMfSQMj7gjXAHUFamGOsFAhS6ImjDuSsMu8FLgA8Blk/yEsjMclFHu1eV7joS+ zwzS2+LEoObebUz6Kvi8lJ+iUNYQxKa3V/1XZ26+NvOa7RwgWBW0W8uMW+eelY/ZAQx5 dqyA== X-Gm-Message-State: AFqh2ko4xLl/Qmoz4h2FX38h6FQ3PUaEwmRiX1V2FQbAei/HKSDmlVQx dubfrevb0jaco4RI1Q32lHgylN5bJVUdrc2Ufz4= X-Google-Smtp-Source: AMrXdXsF08KcX6PHEOHd90nt35sn+52H1ZAiT3xeihfvSH/jQniOvnXYV6kPrBqvH+kwIWaoqr9GgA== X-Received: by 2002:a05:6870:9a14:b0:144:7a85:63ce with SMTP id fo20-20020a0568709a1400b001447a8563cemr42291578oab.54.1673457003354; Wed, 11 Jan 2023 09:10:03 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x18-20020a4ac592000000b004a3543fbfbbsm7214974oop.14.2023.01.11.09.10.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 09:10:02 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH 04/10] hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus() Date: Wed, 11 Jan 2023 14:09:42 -0300 Message-Id: <20230111170948.316276-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> References: <20230111170948.316276-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::2c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 17:10:07 -0000 create_fdt_socket_cpus() writes a different 'mmu-type' value if we're running in 32 or 64 bits. However, the flag is being calculated during virt_machine_init(), and is passed around in create_fdt(), then create_fdt_socket(), and then finally create_fdt_socket_cpus(). None of the intermediate functions are using the flag, which is a bit misleading. Remove 'is_32_bit' flag from create_fdt_socket_cpus() and calculate it using the already available RISCVVirtState pointer. This will also change the signature of create_fdt_socket() and create_fdt(), making it clear that these functions don't do anything special when we're running in 32 bit mode. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 89c99ec1af..99a0a43a73 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -223,12 +223,13 @@ static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, char *clust_name, uint32_t *phandle, - bool is_32_bit, uint32_t *intc_phandles) + uint32_t *intc_phandles) { int cpu; uint32_t cpu_phandle; MachineState *mc = MACHINE(s); char *name, *cpu_name, *core_name, *intc_name; + bool is_32_bit = riscv_is_32bit(&s->soc[0]); for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { cpu_phandle = (*phandle)++; @@ -721,7 +722,7 @@ static void create_fdt_pmu(RISCVVirtState *s) } static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, - bool is_32_bit, uint32_t *phandle, + uint32_t *phandle, uint32_t *irq_mmio_phandle, uint32_t *irq_pcie_phandle, uint32_t *irq_virtio_phandle, @@ -750,7 +751,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, qemu_fdt_add_subnode(mc->fdt, clust_name); create_fdt_socket_cpus(s, socket, clust_name, phandle, - is_32_bit, &intc_phandles[phandle_pos]); + &intc_phandles[phandle_pos]); create_fdt_socket_memory(s, memmap, socket); @@ -998,8 +999,7 @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) g_free(nodename); } -static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, - bool is_32_bit) +static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) { MachineState *mc = MACHINE(s); uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; @@ -1031,9 +1031,9 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); - create_fdt_sockets(s, memmap, is_32_bit, &phandle, - &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, - &msi_pcie_phandle); + create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle, + &irq_pcie_phandle, &irq_virtio_phandle, + &msi_pcie_phandle); create_fdt_virtio(s, memmap, irq_virtio_phandle); @@ -1499,7 +1499,7 @@ static void virt_machine_init(MachineState *machine) virt_flash_map(s, system_memory); /* create device tree */ - create_fdt(s, memmap, riscv_is_32bit(&s->soc[0])); + create_fdt(s, memmap); s->machine_done.notify = virt_machine_done; qemu_add_machine_init_done_notifier(&s->machine_done); -- 2.39.0 From MAILER-DAEMON Wed Jan 11 12:10:27 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFecN-00033M-LW for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 12:10:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFec4-0002j7-Ig for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 12:10:10 -0500 Received: from mail-oo1-xc2f.google.com ([2607:f8b0:4864:20::c2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFec2-0006Mt-IO for qemu-riscv@nongnu.org; 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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x18-20020a4ac592000000b004a3543fbfbbsm7214974oop.14.2023.01.11.09.10.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 09:10:05 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH 05/10] hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() Date: Wed, 11 Jan 2023 14:09:43 -0300 Message-Id: <20230111170948.316276-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> References: <20230111170948.316276-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 17:10:12 -0000 There's no need to use a MachineState pointer and a fdt pointer now that all RISC-V machines are using the FDT from the MachineState. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/numa.c | 6 +++--- hw/riscv/spike.c | 6 +++--- hw/riscv/virt.c | 18 +++++++++--------- include/hw/riscv/numa.h | 6 +++--- 4 files changed, 18 insertions(+), 18 deletions(-) diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c index 7fe92d402f..f4343f5cde 100644 --- a/hw/riscv/numa.c +++ b/hw/riscv/numa.c @@ -156,11 +156,11 @@ uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id) ms->numa_state->nodes[socket_id].node_mem : 0; } -void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt, - const char *node_name, int socket_id) +void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, + int socket_id) { if (numa_enabled(ms)) { - qemu_fdt_setprop_cell(fdt, node_name, "numa-node-id", socket_id); + qemu_fdt_setprop_cell(ms->fdt, node_name, "numa-node-id", socket_id); } } diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 4a66016d69..05d34651cb 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -121,7 +121,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, qemu_fdt_setprop_cell(fdt, cpu_name, "reg", s->soc[socket].hartid_base + cpu); qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); + riscv_socket_fdt_write_id(mc, cpu_name, socket); qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); @@ -154,7 +154,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, qemu_fdt_setprop_cells(fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); + riscv_socket_fdt_write_id(mc, mem_name, socket); g_free(mem_name); clint_addr = memmap[SPIKE_CLINT].base + @@ -167,7 +167,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); + riscv_socket_fdt_write_id(mc, clint_name, socket); g_free(clint_name); g_free(clint_cells); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 99a0a43a73..1d3bd25cb5 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -253,7 +253,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", s->soc[socket].hartid_base + cpu); qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket); + riscv_socket_fdt_write_id(mc, cpu_name, socket); qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); intc_phandles[cpu] = (*phandle)++; @@ -291,7 +291,7 @@ static void create_fdt_socket_memory(RISCVVirtState *s, qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket); + riscv_socket_fdt_write_id(mc, mem_name, socket); g_free(mem_name); } @@ -327,7 +327,7 @@ static void create_fdt_socket_clint(RISCVVirtState *s, 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket); + riscv_socket_fdt_write_id(mc, clint_name, socket); g_free(clint_name); g_free(clint_cells); @@ -372,7 +372,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, aclint_mswi_cells, aclint_cells_size); qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); + riscv_socket_fdt_write_id(mc, name, socket); g_free(name); } @@ -396,7 +396,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, 0x0, RISCV_ACLINT_DEFAULT_MTIME); qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", aclint_mtimer_cells, aclint_cells_size); - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); + riscv_socket_fdt_write_id(mc, name, socket); g_free(name); if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { @@ -412,7 +412,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, aclint_sswi_cells, aclint_cells_size); qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); + riscv_socket_fdt_write_id(mc, name, socket); g_free(name); } @@ -471,7 +471,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s, 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", VIRT_IRQCHIP_NUM_SOURCES - 1); - riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket); + riscv_socket_fdt_write_id(mc, plic_name, socket); qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", plic_phandles[socket]); @@ -663,7 +663,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_s_phandle); qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); + riscv_socket_fdt_write_id(mc, aplic_name, socket); qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); g_free(aplic_name); @@ -691,7 +691,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); + riscv_socket_fdt_write_id(mc, aplic_name, socket); qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); if (!socket) { diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h index 1a9cce3344..634df6673f 100644 --- a/include/hw/riscv/numa.h +++ b/include/hw/riscv/numa.h @@ -90,10 +90,10 @@ bool riscv_socket_check_hartids(const MachineState *ms, int socket_id); * @ms: pointer to machine state * @socket_id: socket index * - * Write NUMA node-id FDT property for given FDT node + * Write NUMA node-id FDT property in MachineState->fdt */ -void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt, - const char *node_name, int socket_id); +void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, + int socket_id); /** * riscv_socket_fdt_write_distance_matrix: -- 2.39.0 From MAILER-DAEMON Wed Jan 11 12:10:28 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFecN-00033Q-Q9 for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 12:10:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFec8-0002jv-0Z for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 12:10:15 -0500 Received: from mail-oo1-xc2b.google.com ([2607:f8b0:4864:20::c2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFec6-0006Nf-8t for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 12:10:11 -0500 Received: by mail-oo1-xc2b.google.com with SMTP id d2-20020a4ab202000000b004ae3035538bso4188849ooo.12 for ; Wed, 11 Jan 2023 09:10:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; 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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x18-20020a4ac592000000b004a3543fbfbbsm7214974oop.14.2023.01.11.09.10.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 09:10:07 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH 06/10] hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() Date: Wed, 11 Jan 2023 14:09:44 -0300 Message-Id: <20230111170948.316276-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> References: <20230111170948.316276-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c2b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 17:10:18 -0000 There's no need to use a MachineState pointer and a fdt pointer now that all RISC-V machines are using the FDT from the MachineState. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/numa.c | 8 ++++---- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 2 +- include/hw/riscv/numa.h | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c index f4343f5cde..4720102561 100644 --- a/hw/riscv/numa.c +++ b/hw/riscv/numa.c @@ -164,7 +164,7 @@ void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, } } -void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt) +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms) { int i, j, idx; uint32_t *dist_matrix, dist_matrix_size; @@ -184,10 +184,10 @@ void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt) } } - qemu_fdt_add_subnode(fdt, "/distance-map"); - qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", + qemu_fdt_add_subnode(ms->fdt, "/distance-map"); + qemu_fdt_setprop_string(ms->fdt, "/distance-map", "compatible", "numa-distance-map-v1"); - qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", + qemu_fdt_setprop(ms->fdt, "/distance-map", "distance-matrix", dist_matrix, dist_matrix_size); g_free(dist_matrix); } diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 05d34651cb..91bf194ec1 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -174,7 +174,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, g_free(clust_name); } - riscv_socket_fdt_write_distance_matrix(mc, fdt); + riscv_socket_fdt_write_distance_matrix(mc); qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 1d3bd25cb5..e374b58f89 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -805,7 +805,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, } } - riscv_socket_fdt_write_distance_matrix(mc, mc->fdt); + riscv_socket_fdt_write_distance_matrix(mc); } static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h index 634df6673f..8f5280211d 100644 --- a/include/hw/riscv/numa.h +++ b/include/hw/riscv/numa.h @@ -100,9 +100,9 @@ void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, * @ms: pointer to machine state * @socket_id: socket index * - * Write NUMA distance matrix in FDT for given machine + * Write NUMA distance matrix in MachineState->fdt */ -void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt); +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms); CpuInstanceProperties riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index); -- 2.39.0 From MAILER-DAEMON Wed Jan 11 12:10:28 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFecO-000346-77 for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 12:10:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFec9-0002kH-E0 for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 12:10:16 -0500 Received: from mail-oa1-x2b.google.com ([2001:4860:4864:20::2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFec6-0006OK-Tv for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 12:10:13 -0500 Received: by mail-oa1-x2b.google.com with SMTP id 586e51a60fabf-1433ef3b61fso16163268fac.10 for ; Wed, 11 Jan 2023 09:10:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; 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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x18-20020a4ac592000000b004a3543fbfbbsm7214974oop.14.2023.01.11.09.10.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 09:10:09 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH 07/10] hw/riscv: simplify riscv_load_fdt() Date: Wed, 11 Jan 2023 14:09:45 -0300 Message-Id: <20230111170948.316276-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> References: <20230111170948.316276-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::2b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 17:10:19 -0000 All callers of riscv_load_fdt() are using machine->ram_size as 'mem_size' and the fdt is always retrievable via machine->fdt. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 4 +++- hw/riscv/microchip_pfsoc.c | 4 ++-- hw/riscv/sifive_u.c | 3 +-- hw/riscv/spike.c | 3 +-- hw/riscv/virt.c | 3 +-- include/hw/riscv/boot.h | 2 +- 6 files changed, 9 insertions(+), 10 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index e868fb6ade..21dea7eac2 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -265,10 +265,12 @@ out: return kernel_entry; } -uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) +uint64_t riscv_load_fdt(MachineState *ms, hwaddr dram_base) { uint64_t temp, fdt_addr; + uint64_t mem_size = ms->ram_size; hwaddr dram_end = dram_base + mem_size; + void *fdt = ms->fdt; int ret, fdtsize = fdt_totalsize(fdt); if (fdtsize <= 0) { diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index c45023a2b1..6bb08f66bd 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -633,8 +633,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) true, NULL); /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_load_fdt(machine, + memmap[MICROCHIP_PFSOC_DRAM_LO].base); /* Load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr, memmap[MICROCHIP_PFSOC_ENVM_DATA].base, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index ccad386920..fc2a8a7af4 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -609,8 +609,7 @@ static void sifive_u_machine_init(MachineState *machine) } /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_load_fdt(machine, memmap[SIFIVE_U_DEV_DRAM].base); if (!riscv_is_32bit(&s->soc.u_cpus)) { start_addr_hi32 = (uint64_t)start_addr >> 32; } diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 91bf194ec1..82093dd2cb 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -316,8 +316,7 @@ static void spike_board_init(MachineState *machine) } /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_load_fdt(machine, memmap[SPIKE_DRAM].base); /* load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e374b58f89..0a0252368e 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1300,8 +1300,7 @@ static void virt_machine_done(Notifier *notifier, void *data) } /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_load_fdt(machine, memmap[VIRT_DRAM].base); /* load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, virt_memmap[VIRT_MROM].base, diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index cbd131bad7..3581bbe447 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -47,7 +47,7 @@ target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, bool load_initrd, symbol_fn_t sym_cb); -uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); +uint64_t riscv_load_fdt(MachineState *ms, hwaddr dram_start); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr, hwaddr rom_base, hwaddr rom_size, -- 2.39.0 From MAILER-DAEMON Wed Jan 11 12:10:28 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFecO-00034K-CA for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 12:10:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFecB-0002kx-W3 for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 12:10:17 -0500 Received: from mail-oo1-xc2f.google.com ([2607:f8b0:4864:20::c2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFec8-0006PS-NT for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 12:10:14 -0500 Received: by mail-oo1-xc2f.google.com with SMTP id d9-20020a4aa589000000b004af737509f4so4188824oom.11 for ; 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Wed, 11 Jan 2023 09:10:11 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x18-20020a4ac592000000b004a3543fbfbbsm7214974oop.14.2023.01.11.09.10.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 09:10:11 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH 08/10] hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() Date: Wed, 11 Jan 2023 14:09:46 -0300 Message-Id: <20230111170948.316276-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> References: <20230111170948.316276-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 17:10:19 -0000 riscv_socket_count() returns either ms->numa_state->num_nodes or 1 depending on NUMA support. In any case the value can be retrieved only once and used in the rest of the function. This will also alleviate the rename we're going to do next by reducing the instances of MachineState 'mc' inside hw/riscv/virt.c. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 0a0252368e..f9bdf2a70b 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -505,13 +505,14 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, int cpu, socket; char *imsic_name; MachineState *mc = MACHINE(s); + int socket_count = riscv_socket_count(mc); uint32_t imsic_max_hart_per_socket, imsic_guest_bits; uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; *msi_m_phandle = (*phandle)++; *msi_s_phandle = (*phandle)++; imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2); - imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4); + imsic_regs = g_new0(uint32_t, socket_count * 4); /* M-level IMSIC node */ for (cpu = 0; cpu < mc->smp.cpus; cpu++) { @@ -519,7 +520,7 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); } imsic_max_hart_per_socket = 0; - for (socket = 0; socket < riscv_socket_count(mc); socket++) { + for (socket = 0; socket < socket_count; socket++) { imsic_addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; @@ -545,14 +546,14 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, - riscv_socket_count(mc) * sizeof(uint32_t) * 4); + socket_count * sizeof(uint32_t) * 4); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); - if (riscv_socket_count(mc) > 1) { + if (socket_count > 1) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", - imsic_num_bits(riscv_socket_count(mc))); + imsic_num_bits(socket_count)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); } @@ -567,7 +568,7 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, } imsic_guest_bits = imsic_num_bits(s->aia_guests + 1); imsic_max_hart_per_socket = 0; - for (socket = 0; socket < riscv_socket_count(mc); socket++) { + for (socket = 0; socket < socket_count; socket++) { imsic_addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * @@ -594,18 +595,18 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, - riscv_socket_count(mc) * sizeof(uint32_t) * 4); + socket_count * sizeof(uint32_t) * 4); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); if (imsic_guest_bits) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits", imsic_guest_bits); } - if (riscv_socket_count(mc) > 1) { + if (socket_count > 1) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", - imsic_num_bits(riscv_socket_count(mc))); + imsic_num_bits(socket_count)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); } @@ -733,6 +734,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, MachineState *mc = MACHINE(s); uint32_t msi_m_phandle = 0, msi_s_phandle = 0; uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; + int socket_count = riscv_socket_count(mc); qemu_fdt_add_subnode(mc->fdt, "/cpus"); qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", @@ -744,7 +746,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, intc_phandles = g_new0(uint32_t, mc->smp.cpus); phandle_pos = mc->smp.cpus; - for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { + for (socket = (socket_count - 1); socket >= 0; socket--) { phandle_pos -= s->soc[socket].num_harts; clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); @@ -775,7 +777,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, } phandle_pos = mc->smp.cpus; - for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { + for (socket = (socket_count - 1); socket >= 0; socket--) { phandle_pos -= s->soc[socket].num_harts; if (s->aia_type == VIRT_AIA_TYPE_NONE) { @@ -790,7 +792,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, g_free(intc_phandles); - for (socket = 0; socket < riscv_socket_count(mc); socket++) { + for (socket = 0; socket < socket_count; socket++) { if (socket == 0) { *irq_mmio_phandle = xplic_phandles[socket]; *irq_virtio_phandle = xplic_phandles[socket]; @@ -1051,7 +1053,8 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) /* Pass seed to RNG */ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); - qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); + qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", + rng_seed, sizeof(rng_seed)); } static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, @@ -1326,9 +1329,10 @@ static void virt_machine_init(MachineState *machine) char *soc_name; DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; int i, base_hartid, hart_count; + int socket_count = riscv_socket_count(machine); /* Check socket count limit */ - if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { + if (VIRT_SOCKETS_MAX < socket_count) { error_report("number of sockets/nodes should be less than %d", VIRT_SOCKETS_MAX); exit(1); @@ -1336,7 +1340,7 @@ static void virt_machine_init(MachineState *machine) /* Initialize sockets */ mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; - for (i = 0; i < riscv_socket_count(machine); i++) { + for (i = 0; i < socket_count; i++) { if (!riscv_socket_check_hartids(machine, i)) { error_report("discontinuous hartids in socket%d", i); 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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x18-20020a4ac592000000b004a3543fbfbbsm7214974oop.14.2023.01.11.09.10.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 09:10:13 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 09/10] hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' Date: Wed, 11 Jan 2023 14:09:47 -0300 Message-Id: <20230111170948.316276-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> References: <20230111170948.316276-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c2b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 17:10:26 -0000 We have a convention in other QEMU boards/archs to name MachineState pointers as either 'machine' or 'ms'. MachineClass pointers are usually called 'mc'. The 'virt' RISC-V machine has a lot of instances where MachineState pointers are named 'mc'. There is nothing wrong with that, but we gain more compatibility with the rest of the QEMU code base, and easier reviews, if we follow QEMU conventions. Rename all 'mc' MachineState pointers to 'ms'. This is a very tedious and mechanical patch that was produced by doing the following: - find/replace all 'MachineState *mc' to 'MachineState *ms'; - find/replace all 'mc->fdt' to 'ms->fdt'; - find/replace all 'mc->smp.cpus' to 'ms->smp.cpus'; - replace any remaining occurrences of 'mc' that the compiler complained about. Suggested-by: Philippe Mathieu-Daudé Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 434 ++++++++++++++++++++++++------------------------ 1 file changed, 217 insertions(+), 217 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f9bdf2a70b..3b73666d2a 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -227,7 +227,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, { int cpu; uint32_t cpu_phandle; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); char *name, *cpu_name, *core_name, *intc_name; bool is_32_bit = riscv_is_32bit(&s->soc[0]); @@ -236,40 +236,40 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); - qemu_fdt_add_subnode(mc->fdt, cpu_name); + qemu_fdt_add_subnode(ms->fdt, cpu_name); if (riscv_feature(&s->soc[socket].harts[cpu].env, RISCV_FEATURE_MMU)) { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", + qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); } else { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", + qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", "riscv,none"); } name = riscv_isa_string(&s->soc[socket].harts[cpu]); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); + qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name); g_free(name); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv"); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay"); - qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", + qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); + qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); + qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", s->soc[socket].hartid_base + cpu); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, cpu_name, socket); - qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); + qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); + riscv_socket_fdt_write_id(ms, cpu_name, socket); + qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); intc_phandles[cpu] = (*phandle)++; intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); - qemu_fdt_add_subnode(mc->fdt, intc_name); - qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", + qemu_fdt_add_subnode(ms->fdt, intc_name); + qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", intc_phandles[cpu]); - qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", + qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", "riscv,cpu-intc"); - qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); + qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); core_name = g_strdup_printf("%s/core%d", clust_name, cpu); - qemu_fdt_add_subnode(mc->fdt, core_name); - qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle); + qemu_fdt_add_subnode(ms->fdt, core_name); + qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); g_free(core_name); g_free(intc_name); @@ -282,16 +282,16 @@ static void create_fdt_socket_memory(RISCVVirtState *s, { char *mem_name; uint64_t addr, size; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); - addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); - size = riscv_socket_mem_size(mc, socket); + addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); + size = riscv_socket_mem_size(ms, socket); mem_name = g_strdup_printf("/memory@%lx", (long)addr); - qemu_fdt_add_subnode(mc->fdt, mem_name); - qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", + qemu_fdt_add_subnode(ms->fdt, mem_name); + qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); - qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, mem_name, socket); + qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); + riscv_socket_fdt_write_id(ms, mem_name, socket); g_free(mem_name); } @@ -303,7 +303,7 @@ static void create_fdt_socket_clint(RISCVVirtState *s, char *clint_name; uint32_t *clint_cells; unsigned long clint_addr; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); static const char * const clint_compat[2] = { "sifive,clint0", "riscv,clint0" }; @@ -319,15 +319,15 @@ static void create_fdt_socket_clint(RISCVVirtState *s, clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); - qemu_fdt_add_subnode(mc->fdt, clint_name); - qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible", + qemu_fdt_add_subnode(ms->fdt, clint_name); + qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", (char **)&clint_compat, ARRAY_SIZE(clint_compat)); - qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); - qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, clint_name, socket); + riscv_socket_fdt_write_id(ms, clint_name, socket); g_free(clint_name); g_free(clint_cells); @@ -344,7 +344,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, uint32_t *aclint_mswi_cells; uint32_t *aclint_sswi_cells; uint32_t *aclint_mtimer_cells; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); @@ -363,16 +363,16 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); name = g_strdup_printf("/soc/mswi@%lx", addr); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-mswi"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", aclint_mswi_cells, aclint_cells_size); - qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, name, socket); + qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); + riscv_socket_fdt_write_id(ms, name, socket); g_free(name); } @@ -386,33 +386,33 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; } name = g_strdup_printf("/soc/mtimer@%lx", addr); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-mtimer"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 0x0, RISCV_ACLINT_DEFAULT_MTIME); - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", aclint_mtimer_cells, aclint_cells_size); - riscv_socket_fdt_write_id(mc, name, socket); + riscv_socket_fdt_write_id(ms, name, socket); g_free(name); if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { addr = memmap[VIRT_ACLINT_SSWI].base + (memmap[VIRT_ACLINT_SSWI].size * socket); name = g_strdup_printf("/soc/sswi@%lx", addr); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-sswi"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", aclint_sswi_cells, aclint_cells_size); - qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, name, socket); + qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); + riscv_socket_fdt_write_id(ms, name, socket); g_free(name); } @@ -430,7 +430,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s, char *plic_name; uint32_t *plic_cells; unsigned long plic_addr; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); static const char * const plic_compat[2] = { "sifive,plic-1.0.0", "riscv,plic0" }; @@ -456,27 +456,27 @@ static void create_fdt_socket_plic(RISCVVirtState *s, plic_phandles[socket] = (*phandle)++; plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); - qemu_fdt_add_subnode(mc->fdt, plic_name); - qemu_fdt_setprop_cell(mc->fdt, plic_name, + qemu_fdt_add_subnode(ms->fdt, plic_name); + qemu_fdt_setprop_cell(ms->fdt, plic_name, "#interrupt-cells", FDT_PLIC_INT_CELLS); - qemu_fdt_setprop_cell(mc->fdt, plic_name, + qemu_fdt_setprop_cell(ms->fdt, plic_name, "#address-cells", FDT_PLIC_ADDR_CELLS); - qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", + qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", (char **)&plic_compat, ARRAY_SIZE(plic_compat)); - qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); - qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", + qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", VIRT_IRQCHIP_NUM_SOURCES - 1); - riscv_socket_fdt_write_id(mc, plic_name, socket); - qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", + riscv_socket_fdt_write_id(ms, plic_name, socket); + qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", plic_phandles[socket]); if (!socket) { - platform_bus_add_all_fdt_nodes(mc->fdt, plic_name, + platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, memmap[VIRT_PLATFORM_BUS].base, memmap[VIRT_PLATFORM_BUS].size, VIRT_PLATFORM_BUS_IRQ); @@ -504,18 +504,18 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, { int cpu, socket; char *imsic_name; - MachineState *mc = MACHINE(s); - int socket_count = riscv_socket_count(mc); + MachineState *ms = MACHINE(s); + int socket_count = riscv_socket_count(ms); uint32_t imsic_max_hart_per_socket, imsic_guest_bits; uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; *msi_m_phandle = (*phandle)++; *msi_s_phandle = (*phandle)++; - imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2); + imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); imsic_regs = g_new0(uint32_t, socket_count * 4); /* M-level IMSIC node */ - for (cpu = 0; cpu < mc->smp.cpus; cpu++) { + for (cpu = 0; cpu < ms->smp.cpus; cpu++) { imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); } @@ -534,35 +534,35 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, } imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)memmap[VIRT_IMSIC_M].base); - qemu_fdt_add_subnode(mc->fdt, imsic_name); - qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", + qemu_fdt_add_subnode(ms->fdt, imsic_name); + qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", FDT_IMSIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", - imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); - qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", + imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); + qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, socket_count * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); if (socket_count > 1) { - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", imsic_num_bits(socket_count)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); } - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle); + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phandle); g_free(imsic_name); /* S-level IMSIC node */ - for (cpu = 0; cpu < mc->smp.cpus; cpu++) { + for (cpu = 0; cpu < ms->smp.cpus; cpu++) { imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); } @@ -583,34 +583,34 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, } imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)memmap[VIRT_IMSIC_S].base); - qemu_fdt_add_subnode(mc->fdt, imsic_name); - qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", + qemu_fdt_add_subnode(ms->fdt, imsic_name); + qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", FDT_IMSIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", - imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); - qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", + imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); + qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, socket_count * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); if (imsic_guest_bits) { - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", imsic_guest_bits); } if (socket_count > 1) { - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", imsic_num_bits(socket_count)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); } - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle); + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_s_phandle); g_free(imsic_name); g_free(imsic_regs); @@ -629,7 +629,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, char *aplic_name; uint32_t *aplic_cells; unsigned long aplic_addr; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); uint32_t aplic_m_phandle, aplic_s_phandle; aplic_m_phandle = (*phandle)++; @@ -644,28 +644,28 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_addr = memmap[VIRT_APLIC_M].base + (memmap[VIRT_APLIC_M].size * socket); aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); - qemu_fdt_add_subnode(mc->fdt, aplic_name); - qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, + qemu_fdt_add_subnode(ms->fdt, aplic_name); + qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#interrupt-cells", FDT_APLIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); if (s->aia_type == VIRT_AIA_TYPE_APLIC) { - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); } else { - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_m_phandle); } - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", VIRT_IRQCHIP_NUM_SOURCES); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", aplic_s_phandle); - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(mc, aplic_name, socket); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); + riscv_socket_fdt_write_id(ms, aplic_name, socket); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phandle); g_free(aplic_name); /* S-level APLIC node */ @@ -676,27 +676,27 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_addr = memmap[VIRT_APLIC_S].base + (memmap[VIRT_APLIC_S].size * socket); aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); - qemu_fdt_add_subnode(mc->fdt, aplic_name); - qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, + qemu_fdt_add_subnode(ms->fdt, aplic_name); + qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#interrupt-cells", FDT_APLIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); if (s->aia_type == VIRT_AIA_TYPE_APLIC) { - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); } else { - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_s_phandle); } - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(mc, aplic_name, socket); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); + riscv_socket_fdt_write_id(ms, aplic_name, socket); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_s_phandle); if (!socket) { - platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name, + platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, memmap[VIRT_PLATFORM_BUS].base, memmap[VIRT_PLATFORM_BUS].size, VIRT_PLATFORM_BUS_IRQ); @@ -711,13 +711,13 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, static void create_fdt_pmu(RISCVVirtState *s) { char *pmu_name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); RISCVCPU hart = s->soc[0].harts[0]; pmu_name = g_strdup_printf("/soc/pmu"); - qemu_fdt_add_subnode(mc->fdt, pmu_name); - qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu"); - riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name); + qemu_fdt_add_subnode(ms->fdt, pmu_name); + qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); + riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name); g_free(pmu_name); } @@ -731,26 +731,26 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, { char *clust_name; int socket, phandle_pos; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); uint32_t msi_m_phandle = 0, msi_s_phandle = 0; uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; - int socket_count = riscv_socket_count(mc); + int socket_count = riscv_socket_count(ms); - qemu_fdt_add_subnode(mc->fdt, "/cpus"); - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", + qemu_fdt_add_subnode(ms->fdt, "/cpus"); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); - qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); + qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); - intc_phandles = g_new0(uint32_t, mc->smp.cpus); + intc_phandles = g_new0(uint32_t, ms->smp.cpus); - phandle_pos = mc->smp.cpus; + phandle_pos = ms->smp.cpus; for (socket = (socket_count - 1); socket >= 0; socket--) { phandle_pos -= s->soc[socket].num_harts; clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); - qemu_fdt_add_subnode(mc->fdt, clust_name); + qemu_fdt_add_subnode(ms->fdt, clust_name); create_fdt_socket_cpus(s, socket, clust_name, phandle, &intc_phandles[phandle_pos]); @@ -776,7 +776,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, *msi_pcie_phandle = msi_s_phandle; } - phandle_pos = mc->smp.cpus; + phandle_pos = ms->smp.cpus; for (socket = (socket_count - 1); socket >= 0; socket--) { phandle_pos -= s->soc[socket].num_harts; @@ -807,7 +807,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, } } - riscv_socket_fdt_write_distance_matrix(mc); + riscv_socket_fdt_write_distance_matrix(ms); } static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, @@ -815,23 +815,23 @@ static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, { int i; char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); for (i = 0; i < VIRTIO_COUNT; i++) { name = g_strdup_printf("/soc/virtio_mmio@%lx", (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 0x0, memmap[VIRT_VIRTIO].size); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_virtio_phandle); if (s->aia_type == VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", VIRTIO_IRQ + i); } else { - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", VIRTIO_IRQ + i, 0x4); } g_free(name); @@ -843,29 +843,29 @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, uint32_t msi_pcie_phandle) { char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); name = g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS); - qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "pci-host-ecam-generic"); - qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci"); - qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0); - qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0, + qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); + qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); + qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); - qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0); + qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { - qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); } - qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0, + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); - qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges", + qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 1, FDT_PCI_RANGE_IOPORT, 2, 0, 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 1, FDT_PCI_RANGE_MMIO, @@ -875,7 +875,7 @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); - create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle); + create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); g_free(name); } @@ -884,39 +884,39 @@ static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, { char *name; uint32_t test_phandle; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); test_phandle = (*phandle)++; name = g_strdup_printf("/soc/test@%lx", (long)memmap[VIRT_TEST].base); - qemu_fdt_add_subnode(mc->fdt, name); + qemu_fdt_add_subnode(ms->fdt, name); { static const char * const compat[3] = { "sifive,test1", "sifive,test0", "syscon" }; - qemu_fdt_setprop_string_array(mc->fdt, name, "compatible", + qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", (char **)&compat, ARRAY_SIZE(compat)); } - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); - qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle); - test_phandle = qemu_fdt_get_phandle(mc->fdt, name); + qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); + test_phandle = qemu_fdt_get_phandle(ms->fdt, name); g_free(name); name = g_strdup_printf("/reboot"); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot"); - qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); - qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); - qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET); + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); + qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); + qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); g_free(name); name = g_strdup_printf("/poweroff"); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff"); - qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); - qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); - qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS); + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); + qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); + qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); g_free(name); } @@ -924,24 +924,24 @@ static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, uint32_t irq_mmio_phandle) { char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_UART0].base, 0x0, memmap[VIRT_UART0].size); - qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); if (s->aia_type == VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); } else { - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4); + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); } - qemu_fdt_add_subnode(mc->fdt, "/chosen"); - qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); + qemu_fdt_add_subnode(ms->fdt, "/chosen"); + qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); g_free(name); } @@ -949,20 +949,20 @@ static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, uint32_t irq_mmio_phandle) { char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "google,goldfish-rtc"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); if (s->aia_type == VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); } else { - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4); + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); } g_free(name); } @@ -970,68 +970,68 @@ static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) { char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; hwaddr flashbase = virt_memmap[VIRT_FLASH].base; name = g_strdup_printf("/flash@%" PRIx64, flashbase); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); - qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); + qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2, flashbase, 2, flashsize, 2, flashbase + flashsize, 2, flashsize); - qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); + qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); g_free(name); } static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) { char *nodename; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); hwaddr base = memmap[VIRT_FW_CFG].base; hwaddr size = memmap[VIRT_FW_CFG].size; nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); - qemu_fdt_add_subnode(mc->fdt, nodename); - qemu_fdt_setprop_string(mc->fdt, nodename, + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "qemu,fw-cfg-mmio"); - qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", + qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); - qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); + qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); g_free(nodename); } static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) { - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; uint8_t rng_seed[32]; - if (mc->dtb) { - mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); - if (!mc->fdt) { + if (ms->dtb) { + ms->fdt = load_device_tree(ms->dtb, &s->fdt_size); + if (!ms->fdt) { error_report("load_device_tree() failed"); exit(1); } } else { - mc->fdt = create_device_tree(&s->fdt_size); - if (!mc->fdt) { + ms->fdt = create_device_tree(&s->fdt_size); + if (!ms->fdt) { error_report("create_device_tree() failed"); exit(1); } } - qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu"); - qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio"); - qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2); - qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2); + qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); + qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); + qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); + qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); - qemu_fdt_add_subnode(mc->fdt, "/soc"); - qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0); - qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus"); - qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); - qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); + qemu_fdt_add_subnode(ms->fdt, "/soc"); + qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); + qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); + qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); + qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, @@ -1053,7 +1053,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) /* Pass seed to RNG */ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); - qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", + qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); } @@ -1106,14 +1106,14 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, return dev; } -static FWCfgState *create_fw_cfg(const MachineState *mc) +static FWCfgState *create_fw_cfg(const MachineState *ms) { hwaddr base = virt_memmap[VIRT_FW_CFG].base; FWCfgState *fw_cfg; fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, &address_space_memory); - fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); + fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); return fw_cfg; } -- 2.39.0 From MAILER-DAEMON Wed Jan 11 12:10:29 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFecO-000359-Sj for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 12:10:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFecI-0002yl-31 for qemu-riscv@nongnu.org; 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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x18-20020a4ac592000000b004a3543fbfbbsm7214974oop.14.2023.01.11.09.10.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Jan 2023 09:10:15 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH 10/10] hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' Date: Wed, 11 Jan 2023 14:09:48 -0300 Message-Id: <20230111170948.316276-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> References: <20230111170948.316276-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 11 Jan 2023 17:10:26 -0000 Follow the QEMU convention of naming MachineState pointers as 'ms' by renaming the instances where we're calling it 'mc'. Suggested-by: Philippe Mathieu-Daudé Signed-off-by: Daniel Henrique Barboza --- hw/riscv/spike.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 82093dd2cb..d753fb1f31 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -56,7 +56,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, uint64_t addr, size; unsigned long clint_addr; int cpu, socket; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); uint32_t *clint_cells; uint32_t cpu_phandle, intc_phandle, phandle = 1; char *name, *mem_name, *clint_name, *clust_name; @@ -65,7 +65,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, "sifive,clint0", "riscv,clint0" }; - fdt = mc->fdt = create_device_tree(&fdt_size); + fdt = ms->fdt = create_device_tree(&fdt_size); if (!fdt) { error_report("create_device_tree() failed"); exit(1); @@ -96,7 +96,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); - for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { + for (socket = (riscv_socket_count(ms) - 1); socket >= 0; socket--) { clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); qemu_fdt_add_subnode(fdt, clust_name); @@ -121,7 +121,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, qemu_fdt_setprop_cell(fdt, cpu_name, "reg", s->soc[socket].hartid_base + cpu); qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, cpu_name, socket); + riscv_socket_fdt_write_id(ms, cpu_name, socket); qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); @@ -147,14 +147,14 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, g_free(cpu_name); } - addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket); - size = riscv_socket_mem_size(mc, socket); + addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(ms, socket); + size = riscv_socket_mem_size(ms, socket); mem_name = g_strdup_printf("/memory@%lx", (long)addr); qemu_fdt_add_subnode(fdt, mem_name); qemu_fdt_setprop_cells(fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, mem_name, socket); + riscv_socket_fdt_write_id(ms, mem_name, socket); g_free(mem_name); clint_addr = memmap[SPIKE_CLINT].base + @@ -167,14 +167,14 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, clint_name, socket); + riscv_socket_fdt_write_id(ms, clint_name, socket); g_free(clint_name); g_free(clint_cells); g_free(clust_name); } - riscv_socket_fdt_write_distance_matrix(mc); + riscv_socket_fdt_write_distance_matrix(ms); qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e36; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe36.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 00:34:31 -0000 On Mon, Jan 2, 2023 at 9:55 PM Daniel Henrique Barboza wrote: > > The microchip_icicle_kit, sifive_u, spike and virt boards are now doing > the same steps when '-kernel' is used: > > - execute load_kernel() > - load init_rd() > - write kernel_cmdline > > Let's fold everything inside riscv_load_kernel() to avoid code > repetition. To not change the behavior of boards that aren't calling > riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and > allow these boards to opt out from initrd loading. > > Cc: Palmer Dabbelt > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/boot.c | 22 +++++++++++++++++++--- > hw/riscv/microchip_pfsoc.c | 12 ++---------- > hw/riscv/opentitan.c | 2 +- > hw/riscv/sifive_e.c | 3 ++- > hw/riscv/sifive_u.c | 12 ++---------- > hw/riscv/spike.c | 11 +---------- > hw/riscv/virt.c | 12 ++---------- > include/hw/riscv/boot.h | 1 + > 8 files changed, 30 insertions(+), 45 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 2594276223..4888d5c1e0 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -175,10 +175,12 @@ target_ulong riscv_load_firmware(const char *firmware_filename, > > target_ulong riscv_load_kernel(MachineState *machine, > target_ulong kernel_start_addr, > + bool load_initrd, > symbol_fn_t sym_cb) > { > const char *kernel_filename = machine->kernel_filename; > uint64_t kernel_load_base, kernel_entry; > + void *fdt = machine->fdt; > > g_assert(kernel_filename != NULL); > > @@ -192,21 +194,35 @@ target_ulong riscv_load_kernel(MachineState *machine, > if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, > NULL, &kernel_load_base, NULL, NULL, 0, > EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { > - return kernel_load_base; > + kernel_entry = kernel_load_base; This breaks 32-bit Xvisor loading. It seems that for the 32-bit guest we get a value of 0xffffffff80000000. Previously the top bits would be lost as we return a target_ulong from this function, but with this change we pass the value 0xffffffff80000000 to riscv_load_initrd() which causes failures. This diff fixes the failure for me diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 4888d5c1e0..f08ed44b97 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -194,7 +194,7 @@ target_ulong riscv_load_kernel(MachineState *machine, if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL, &kernel_load_base, NULL, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { - kernel_entry = kernel_load_base; + kernel_entry = (target_ulong) kernel_load_base; goto out; } but I don't think that's the right fix. We should instead look at the CPU XLEN and drop the high bits if required. I'm going to drop this patch, do you mind looking into a proper fix? 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id ml21-20020a17090b361500b002135de3013fsm9581017pjb.32.2023.01.11.16.36.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Jan 2023 16:36:49 -0800 (PST) Message-ID: <0a5fa04b-5576-3350-a0c6-bfeab2e11cca@linaro.org> Date: Wed, 11 Jan 2023 09:48:09 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v2 1/4] hw: Remove hardcoded tabs (code style) Content-Language: en-US To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org References: <20230111083909.42624-1-philmd@linaro.org> <20230111083909.42624-2-philmd@linaro.org> From: Richard Henderson In-Reply-To: <20230111083909.42624-2-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: 20 X-Spam_score: 2.0 X-Spam_bar: ++ X-Spam_report: (2.0 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_03_06=1.592, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 00:36:54 -0000 On 1/11/23 00:39, Philippe Mathieu-Daudé wrote: > We are going to modify this code, fix its style first to avoid > the following checkpatch.pl violations: > > ERROR: code indent should never use tabs > ERROR: space prohibited between function name and open parenthesis '(' > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/dma/etraxfs_dma.c | 196 +++++++++++++++++++++---------------------- > hw/misc/mst_fpga.c | 162 ++++++++++++++++++----------------- > 2 files changed, 175 insertions(+), 183 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Wed Jan 11 19:36:59 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFlaV-0007iW-HQ for mharc-qemu-riscv@gnu.org; Wed, 11 Jan 2023 19:36:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFlaT-0007am-8r for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 19:36:57 -0500 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFlaQ-0001lz-Uy for qemu-riscv@nongnu.org; Wed, 11 Jan 2023 19:36:56 -0500 Received: by mail-pj1-x102b.google.com with SMTP id z1-20020a17090a66c100b00226f05b9595so3984069pjl.0 for ; Wed, 11 Jan 2023 16:36:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=nwuYdBYbacb9IWlfEKWZ+6Ak12b3r2mxv1nKNS0ptTY=; b=JtvqOCMYzrzn6oTn2ep9CgKQhHe40kl/2mKYyMkXNhZIKwVNrfTGwTCOMzptoDImx0 x0oXQ9Usvhjrs8fqHN3QaQDzGmvGK7ucdfd1F1Y0smxlkolyWebozjshUZWaPOUenkF3 jApaX7doudMH1tvsBsaz0UnujSxwizd9BLnX4bFH9i30VxGMKbmtZBayTj/L9WcLhzED 4SMg/gD58uyZI0ACUPGvP3+uwe6eqJ84Ke4AR7BfTa1foZ0Ep5dlfw8tI/bkqKYsbSNI vcU/hQdorB0fUBtNxyyEhYK3fgKgXgF1r5+wbWBiGfxomwIdDyhBw2Yc3cCZJ5x9xqin gP0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=nwuYdBYbacb9IWlfEKWZ+6Ak12b3r2mxv1nKNS0ptTY=; b=tFsNFoPBRVW5rILuESU/lu05jJA4RsgPXqMW35eyDoua1TS05Ejr8paj3degbIYr1X ZOo4BxXZjxbNYPKd772SfA2vH30EOrfS6ZB58IumLhOXRb1pN8gpAEvAvfSgWBdz14OJ LigoyGufH42e2X4eNz1HfIIHN3sfl9QNum/fWOZOykE4bg91CSn9Gl1JY+ys/W74pG+x p6/T84V+dAHMOoAM5Nix7I1CqFkm91etGlUIBLWdD29+IQj7fAJPbIIWKMAdOWhxOptL /WVLAD4av4sGAyLgcO8a3DVeH5RAmTAytdAzyiW/YVKkNnTOEDiPiIGzmlN8QD3uKR65 Oaqw== X-Gm-Message-State: AFqh2kqhbCwpd1FO900sEmxn7sdP9ZJM5wGCtBOPPrvdsu4xoUe4R6sT jo6iIg4TmaAhCG5V5ofikMov+Q== X-Google-Smtp-Source: AMrXdXvyY+3jSWw9f8vVzeUnmyUPbsbfJJMtVdgPU8mB68cIzDlO6YOL89teKNCCPIvW8eK1jFko8A== X-Received: by 2002:a17:902:a5c1:b0:189:62fd:140e with SMTP id t1-20020a170902a5c100b0018962fd140emr73199788plq.29.1673483813705; Wed, 11 Jan 2023 16:36:53 -0800 (PST) Received: from [192.168.5.146] (rrcs-173-198-77-218.west.biz.rr.com. [173.198.77.218]) by smtp.gmail.com with ESMTPSA id k7-20020a170902760700b00192bf7eaf28sm10716395pll.286.2023.01.11.16.36.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Jan 2023 16:36:53 -0800 (PST) Message-ID: <6da2fab1-4318-f466-bdec-0c4296711bf9@linaro.org> Date: Wed, 11 Jan 2023 09:48:58 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v2 2/4] bulk: Coding style fixes Content-Language: en-US To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org References: <20230111083909.42624-1-philmd@linaro.org> <20230111083909.42624-3-philmd@linaro.org> From: Richard Henderson In-Reply-To: <20230111083909.42624-3-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: 20 X-Spam_score: 2.0 X-Spam_bar: ++ X-Spam_report: (2.0 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_03_06=1.592, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 00:36:57 -0000 On 1/11/23 00:39, Philippe Mathieu-Daudé wrote: > Fix the following checkpatch.pl violation on lines using the > TARGET_FMT_plx definition to avoid: > > WARNING: line over 80 characters > > Signed-off-by: Philippe Mathieu-Daudé > --- > hw/block/pflash_cfi01.c | 5 +++-- > hw/char/digic-uart.c | 8 ++++---- > hw/core/sysbus.c | 3 ++- > hw/dma/pl330.c | 16 +++++++++------- > hw/i386/multiboot.c | 3 ++- > hw/i386/xen/xen-hvm.c | 3 ++- > hw/i386/xen/xen-mapcache.c | 13 ++++++++----- > hw/intc/exynos4210_combiner.c | 20 ++++++++++---------- > hw/misc/auxbus.c | 3 ++- > hw/net/allwinner_emac.c | 8 ++++---- > hw/timer/digic-timer.c | 8 ++++---- > hw/timer/etraxfs_timer.c | 3 +-- > softmmu/memory.c | 3 ++- > target/ppc/mmu-hash32.c | 10 ++++++---- > target/ppc/mmu_common.c | 8 +++++--- > target/sparc/mmu_helper.c | 5 +++-- > 16 files changed, 67 insertions(+), 52 deletions(-) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Wed Jan 11 19:37:02 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFlaY-0007ok-6z for mharc-qemu-riscv@gnu.org; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jd9-20020a170903260900b00186727e5f5csm10743237plb.248.2023.01.11.16.36.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Jan 2023 16:36:56 -0800 (PST) Message-ID: <782e40cf-532b-8148-1512-1b56668977e1@linaro.org> Date: Wed, 11 Jan 2023 09:50:25 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v2 3/4] bulk: Replace TARGET_FMT_plx -> HWADDR_PRIx Content-Language: en-US To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, BALATON Zoltan References: <20230111083909.42624-1-philmd@linaro.org> <20230111083909.42624-4-philmd@linaro.org> From: Richard Henderson In-Reply-To: <20230111083909.42624-4-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, DATE_IN_PAST_03_06=1.592, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 00:37:01 -0000 On 1/11/23 00:39, Philippe Mathieu-Daudé wrote: > The 'hwaddr' type is defined in "exec/hwaddr.h" as: > > hwaddr is the type of a physical address > (its size can be different from 'target_ulong'). > > All definitions use the 'HWADDR_' prefix, except TARGET_FMT_plx: > > $ fgrep define include/exec/hwaddr.h > #define HWADDR_H > #define HWADDR_BITS 64 > #define HWADDR_MAX UINT64_MAX > #define TARGET_FMT_plx "%016" PRIx64 > ^^^^^^ > #define HWADDR_PRId PRId64 > #define HWADDR_PRIi PRIi64 > #define HWADDR_PRIo PRIo64 > #define HWADDR_PRIu PRIu64 > #define HWADDR_PRIx PRIx64 > #define HWADDR_PRIX PRIX64 > > Since hwaddr's size can be*different* from target_ulong, it is > very confusing to read one of its format using the 'TARGET_FMT_' > prefix, normally used for the target_long / target_ulong types: > > $ fgrep TARGET_FMT_ include/exec/cpu-defs.h > #define TARGET_FMT_lx "%08x" > #define TARGET_FMT_ld "%d" > #define TARGET_FMT_lu "%u" > #define TARGET_FMT_lx "%016" PRIx64 > #define TARGET_FMT_ld "%" PRId64 > #define TARGET_FMT_lu "%" PRIu64 > > Apparently this format was missed during commit a8170e5e97 > ("Rename target_phys_addr_t to hwaddr"), so complete it by > doing a bulk-replacement to '"%016" HWADDR_PRIx' using: > > $ sed -i -E \ > -e 's/" ?TARGET_FMT_plx ?"/%016" HWADDR_PRIx "/g' \ > -e 's/" ?TARGET_FMT_plx/%016" HWADDR_PRIx/g' \ > -e 's/TARGET_FMT_plx ?"/"%016" HWADDR_PRIx "/g' \ > $(git grep -l TARGET_FMT_plx) > > and removing the definition from "exec/hwaddr.h". > > Suggested-by: BALATON Zoltan > Signed-off-by: Philippe Mathieu-Daudé > --- Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Thu Jan 12 02:33:59 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFs62-0008Vk-TC for mharc-qemu-riscv@gnu.org; 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Wed, 11 Jan 2023 23:33:50 -0800 (PST) Message-ID: Date: Thu, 12 Jan 2023 08:33:49 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH 07/10] hw/riscv: simplify riscv_load_fdt() Content-Language: en-US To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com References: <20230111170948.316276-1-dbarboza@ventanamicro.com> <20230111170948.316276-8-dbarboza@ventanamicro.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230111170948.316276-8-dbarboza@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 07:33:54 -0000 On 11/1/23 18:09, Daniel Henrique Barboza wrote: > All callers of riscv_load_fdt() are using machine->ram_size as > 'mem_size' and the fdt is always retrievable via machine->fdt. > > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/boot.c | 4 +++- > hw/riscv/microchip_pfsoc.c | 4 ++-- > hw/riscv/sifive_u.c | 3 +-- > hw/riscv/spike.c | 3 +-- > hw/riscv/virt.c | 3 +-- > include/hw/riscv/boot.h | 2 +- > 6 files changed, 9 insertions(+), 10 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index e868fb6ade..21dea7eac2 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -265,10 +265,12 @@ out: > return kernel_entry; > } > > -uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) > +uint64_t riscv_load_fdt(MachineState *ms, hwaddr dram_base) > { > uint64_t temp, fdt_addr; > + uint64_t mem_size = ms->ram_size; > hwaddr dram_end = dram_base + mem_size; What about sparse memory ...? > if (fdtsize <= 0) { > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index c45023a2b1..6bb08f66bd 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -633,8 +633,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) > true, NULL); > > /* Compute the fdt load address in dram */ > - fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, > - machine->ram_size, machine->fdt); > + fdt_load_addr = riscv_load_fdt(machine, > + memmap[MICROCHIP_PFSOC_DRAM_LO].base); ... i.e: hw/riscv/microchip_pfsoc.c: [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 }, hw/riscv/microchip_pfsoc.c: [MICROCHIP_PFSOC_DRAM_HI] = { 0x1000000000, 0x0 }, IIUC FDT is always loaded into a contiguous region, so maybe simply 'dram_base' is a bad name for '[fdt_]load_address'? 'mem_size' is used to calculate 'dram_end'... This function seems buggy. We should pass either start_addr/end_addr or base/size, but the range passed must be contiguous. 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Wed, 11 Jan 2023 23:36:44 -0800 (PST) Received: from [192.168.30.216] ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id l27-20020a05600c2cdb00b003a84375d0d1sm27817202wmc.44.2023.01.11.23.36.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Jan 2023 23:36:43 -0800 (PST) Message-ID: Date: Thu, 12 Jan 2023 08:36:42 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH 00/10] riscv: create_fdt() related cleanups Content-Language: en-US To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com References: <20230111170948.316276-1-dbarboza@ventanamicro.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 07:36:51 -0000 On 11/1/23 18:09, Daniel Henrique Barboza wrote: > Hi, > > This is a follow-up of: > > "[PATCH v5 00/11] riscv: OpenSBI boot test and cleanups" > > Patches were based on top of riscv-to-apply.next [1] + the series above. > > The recent FDT changes made in hw/riscv (all machines are now using the > FDT via MachineState::fdt) allowed for most of the cleanups made here. > > Patches 9 and 10 were based on a suggestion made by Phil a few weeks ago. > I decided to go for it. > > [1] https://github.com/alistair23/qemu/tree/riscv-to-apply.next > > Daniel Henrique Barboza (10): > hw/riscv/spike.c: simplify create_fdt() > hw/riscv/virt.c: simplify create_fdt() > hw/riscv/sifive_u.c: simplify create_fdt() > hw/riscv/virt.c: remove 'is_32_bit' param from > create_fdt_socket_cpus() > hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() > hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() > hw/riscv: simplify riscv_load_fdt() > hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() > hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' > hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' Patch 7 likely needs rework (problem predating your series). Meanwhile for patches 1-6 & 8-10: Reviewed-by: Philippe Mathieu-Daudé Thanks for this cleanup! From MAILER-DAEMON Thu Jan 12 03:30:07 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFsyN-0007RQ-2L for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 03:30:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFsyK-0007Qp-Fn for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 03:30:04 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFsyI-0003vV-14 for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 03:30:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1673512201; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=sVfYgbCVY/WbpS8k7uGQZNd6BIUD4uBueoLXy5mqWVE=; b=h471Qi/HIPdSHurxdQXeqiBabI7XBvGdcF0H4iB1SPplcTrA8oMkplR95eYLKwymqP2NBi tHRIolnYLRyJu5CAWDCyaYcFfUHiLysimeyRTt0aPi1txgPUMuitjHUtcvVKCtTYckr8OA 87twRhrF1Ng/g4S6hn9fbJVo8zAJ4Yw= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-380-6R0NKPu-NdmoCq1Gd1nDjw-1; Thu, 12 Jan 2023 03:29:57 -0500 X-MC-Unique: 6R0NKPu-NdmoCq1Gd1nDjw-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 2E1A3101A521; Thu, 12 Jan 2023 08:29:57 +0000 (UTC) Received: from thuth.com (unknown [10.39.193.2]) by smtp.corp.redhat.com (Postfix) with ESMTP id 3B1711759E; Thu, 12 Jan 2023 08:29:54 +0000 (UTC) From: Thomas Huth To: Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Markus Armbruster , qemu-block@nongnu.org Subject: [PATCH] hw/misc/sifive_u_otp: Remove the deprecated OTP config with '-drive if=none' Date: Thu, 12 Jan 2023 09:29:51 +0100 Message-Id: <20230112082951.874492-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.5 Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 08:30:05 -0000 '-drive if=none' is meant for configuring back-end devices only, so this got marked as deprecated in QEMU 6.2. Users should now only use the new way with '-drive if=pflash' instead. Signed-off-by: Thomas Huth --- docs/about/deprecated.rst | 6 ------ docs/about/removed-features.rst | 7 +++++++ hw/misc/sifive_u_otp.c | 7 ------- 3 files changed, 7 insertions(+), 13 deletions(-) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 68d29642d7..bfe8148490 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -87,12 +87,6 @@ as short-form boolean values, and passed to plugins as ``arg_name=on``. However, short-form booleans are deprecated and full explicit ``arg_name=on`` form is preferred. -``-drive if=none`` for the sifive_u OTP device (since 6.2) -'''''''''''''''''''''''''''''''''''''''''''''''''''''''''' - -Using ``-drive if=none`` to configure the OTP device of the sifive_u -RISC-V machine is deprecated. Use ``-drive if=pflash`` instead. - ``-no-hpet`` (since 8.0) '''''''''''''''''''''''' diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst index c918cabd1a..b1cb15f3d9 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -422,6 +422,13 @@ the value is hexadecimal. That is, '0x20M' should be written either as ``tty`` and ``parport`` used to be aliases for ``serial`` and ``parallel`` respectively. The actual backend names should be used instead. +``-drive if=none`` for the sifive_u OTP device (removed in 8.0) +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +Using ``-drive if=none`` to configure the OTP device of the sifive_u +RISC-V machine is deprecated. Use ``-drive if=pflash`` instead. + + QEMU Machine Protocol (QMP) commands ------------------------------------ diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c index 6d7fdb040a..8965f5c22a 100644 --- a/hw/misc/sifive_u_otp.c +++ b/hw/misc/sifive_u_otp.c @@ -210,13 +210,6 @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); dinfo = drive_get(IF_PFLASH, 0, 0); - if (!dinfo) { - dinfo = drive_get(IF_NONE, 0, 0); - if (dinfo) { - warn_report("using \"-drive if=none\" for the OTP is deprecated, " - "use \"-drive if=pflash\" instead."); - } - } if (dinfo) { int ret; uint64_t perm; -- 2.31.1 From MAILER-DAEMON Thu Jan 12 03:38:08 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFt68-0001lp-La for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 03:38:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFt60-0001kp-Cz for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 03:38:05 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFt5y-0005VK-MD for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 03:38:00 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1673512677; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7embLn2Cl9KxGN9+kbnQOPXT2oZ/iLd9DqhronnvJrU=; b=FNljmB6tyr2LSU2npTR/HJa4TYtjIPyIPn3lc/sVjcQkBRaOCy5PEn2dSyguiOrsoQffnA OLq0bp3V4iZmgcrAhE8Dhnpxq3BvjCwX+hKMQJ/8NwHYQdXIyI74Kbxjc8CJdTsbNWN7+b qsCLkeaew9hiyWXAd2QcumpXwbot+Es= Received: from mail-wm1-f69.google.com (mail-wm1-f69.google.com [209.85.128.69]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-584-AF1BXn-XNuemcjb43VPNWw-1; Thu, 12 Jan 2023 03:37:56 -0500 X-MC-Unique: AF1BXn-XNuemcjb43VPNWw-1 Received: by mail-wm1-f69.google.com with SMTP id bd6-20020a05600c1f0600b003d96f7f2396so12127449wmb.3 for ; Thu, 12 Jan 2023 00:37:56 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:references:cc:to:from :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=7embLn2Cl9KxGN9+kbnQOPXT2oZ/iLd9DqhronnvJrU=; b=oKS7JWHN3NcBGfVPic2ESR308WXfNrEsMB8eRmE9RJdK3n0sRzleWeAn8YEUJatM4b t1XEHEo7Fx0pNzmdMAt1XPyHPuw1T9cPKcWguIOwVO0us3v5TU3bCp71NjZ2s+KVi/ot eZ1ZIedCsG9ipDC5oxEy34ZwP+fybxcCY6QEtEXQKpTOTG3wY6hgK3u/Q6KwbeJTm/wi ZZOP/AeobziXrm/XHxk2TucXZCwPgGVuV5ZXbK9Qlkpmh8UVuC6jjpOa85QAZoollmGx c4uzotMDEl1xk+3WW0VX3c3nOGQv3OW8K0u1vGpF1SHG9es4GV799KdxWWv2ynzsoZC2 bPqg== X-Gm-Message-State: AFqh2kpVSxNoUkZWjXmWMBoMG3oCSilzu7Ce2jHkD2AoquAofH+JuNyb KV7/iKvQFTIdnB2fhrAgN6ztgWKRA6QZhzjBe/BzauioVLAG4c1eN8vk1TJ85SUiueUVJv3R5Cu F53LjdkkIW8oTWzM= X-Received: by 2002:a05:6000:4004:b0:242:bef:80a1 with SMTP id cy4-20020a056000400400b002420bef80a1mr52390552wrb.2.1673512675249; Thu, 12 Jan 2023 00:37:55 -0800 (PST) X-Google-Smtp-Source: AMrXdXtcZj97D5Xhasc+mQYa27iYhW/tBafaSvxYWJl/ENqksENh7ttStFtCU/dvt4BWpkBu8FeHrQ== X-Received: by 2002:a05:6000:4004:b0:242:bef:80a1 with SMTP id cy4-20020a056000400400b002420bef80a1mr52390532wrb.2.1673512674946; Thu, 12 Jan 2023 00:37:54 -0800 (PST) Received: from [192.168.0.2] (ip-109-43-177-128.web.vodafone.de. [109.43.177.128]) by smtp.gmail.com with ESMTPSA id n6-20020adfe786000000b002bdbde1d3absm5558982wrm.78.2023.01.12.00.37.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Jan 2023 00:37:54 -0800 (PST) Message-ID: <1b78cb0a-3d75-cdec-eb3a-bcd7fad04c51@redhat.com> Date: Thu, 12 Jan 2023 09:37:52 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 Subject: Re: [PATCH] hw/misc/sifive_u_otp: Remove the deprecated OTP config with '-drive if=none' From: Thomas Huth To: Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Markus Armbruster , qemu-block@nongnu.org References: <20230112082951.874492-1-thuth@redhat.com> In-Reply-To: <20230112082951.874492-1-thuth@redhat.com> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 08:38:06 -0000 On 12/01/2023 09.29, Thomas Huth wrote: > '-drive if=none' is meant for configuring back-end devices only, so this > got marked as deprecated in QEMU 6.2. Users should now only use the new > way with '-drive if=pflash' instead. > > Signed-off-by: Thomas Huth > --- > docs/about/deprecated.rst | 6 ------ > docs/about/removed-features.rst | 7 +++++++ > hw/misc/sifive_u_otp.c | 7 ------- > 3 files changed, 7 insertions(+), 13 deletions(-) > > diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst > index 68d29642d7..bfe8148490 100644 > --- a/docs/about/deprecated.rst > +++ b/docs/about/deprecated.rst > @@ -87,12 +87,6 @@ as short-form boolean values, and passed to plugins as ``arg_name=on``. > However, short-form booleans are deprecated and full explicit ``arg_name=on`` > form is preferred. > > -``-drive if=none`` for the sifive_u OTP device (since 6.2) > -'''''''''''''''''''''''''''''''''''''''''''''''''''''''''' > - > -Using ``-drive if=none`` to configure the OTP device of the sifive_u > -RISC-V machine is deprecated. Use ``-drive if=pflash`` instead. > - > ``-no-hpet`` (since 8.0) > '''''''''''''''''''''''' > > diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst > index c918cabd1a..b1cb15f3d9 100644 > --- a/docs/about/removed-features.rst > +++ b/docs/about/removed-features.rst > @@ -422,6 +422,13 @@ the value is hexadecimal. That is, '0x20M' should be written either as > ``tty`` and ``parport`` used to be aliases for ``serial`` and ``parallel`` > respectively. The actual backend names should be used instead. > > +``-drive if=none`` for the sifive_u OTP device (removed in 8.0) > +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' > + > +Using ``-drive if=none`` to configure the OTP device of the sifive_u > +RISC-V machine is deprecated. Use ``-drive if=pflash`` instead. -ENOTENOUGHCOFFEEYET I think I should adjust that description a little bit instead of blindly copy-n-pasting it... Sorry. I'll send a v2. Thomas From MAILER-DAEMON Thu Jan 12 03:39:36 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFt7V-0002Uu-II for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 03:39:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFt7T-0002Sj-Cg for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 03:39:32 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFt7R-0005fH-Av for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 03:39:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1673512768; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=dRJfkbWwyIQzTd8U489EfmTPNO/iCMPsE3eVTYqVKdc=; b=X0sO/pgistsAbjHZXHadUDAtbukPSn/TRiTlbLfI/xMJYoApu+8dr0KD/sqB0dheDFf9NH E4ViLDI4WnUDvqgq1hzsN5hbq9UM3ZAz3q6lwXESlZm4V1KC78dHPuDC7F3BkRvKp0l5yo e9JyZ0X4WEOVI641BjRlojQnpWso5sk= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-412-UaBl1OE_MlWgXpFCOUT8KA-1; Thu, 12 Jan 2023 03:39:24 -0500 X-MC-Unique: UaBl1OE_MlWgXpFCOUT8KA-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.rdu2.redhat.com [10.11.54.1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 371AB1C05AB0; Thu, 12 Jan 2023 08:39:24 +0000 (UTC) Received: from thuth.com (unknown [10.39.193.2]) by smtp.corp.redhat.com (Postfix) with ESMTP id BE7A740C2064; Thu, 12 Jan 2023 08:39:22 +0000 (UTC) From: Thomas Huth To: Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Markus Armbruster , qemu-block@nongnu.org Subject: [PATCH v2] hw/misc/sifive_u_otp: Remove the deprecated OTP config with '-drive if=none' Date: Thu, 12 Jan 2023 09:39:21 +0100 Message-Id: <20230112083921.887828-1-thuth@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.1 Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 08:39:32 -0000 '-drive if=none' is meant for configuring back-end devices only, so this got marked as deprecated in QEMU 6.2. Users should now only use the new way with '-drive if=pflash' instead. Signed-off-by: Thomas Huth --- docs/about/deprecated.rst | 6 ------ docs/about/removed-features.rst | 7 +++++++ hw/misc/sifive_u_otp.c | 7 ------- 3 files changed, 7 insertions(+), 13 deletions(-) diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 68d29642d7..bfe8148490 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -87,12 +87,6 @@ as short-form boolean values, and passed to plugins as ``arg_name=on``. However, short-form booleans are deprecated and full explicit ``arg_name=on`` form is preferred. -``-drive if=none`` for the sifive_u OTP device (since 6.2) -'''''''''''''''''''''''''''''''''''''''''''''''''''''''''' - -Using ``-drive if=none`` to configure the OTP device of the sifive_u -RISC-V machine is deprecated. Use ``-drive if=pflash`` instead. - ``-no-hpet`` (since 8.0) '''''''''''''''''''''''' diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst index c918cabd1a..6bd0a2b4e4 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -422,6 +422,13 @@ the value is hexadecimal. That is, '0x20M' should be written either as ``tty`` and ``parport`` used to be aliases for ``serial`` and ``parallel`` respectively. The actual backend names should be used instead. +``-drive if=none`` for the sifive_u OTP device (removed in 8.0) +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +Use ``-drive if=pflash`` to configure the OTP device of the sifive_u +RISC-V machine instead. + + QEMU Machine Protocol (QMP) commands ------------------------------------ diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c index 6d7fdb040a..8965f5c22a 100644 --- a/hw/misc/sifive_u_otp.c +++ b/hw/misc/sifive_u_otp.c @@ -210,13 +210,6 @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp) sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); dinfo = drive_get(IF_PFLASH, 0, 0); - if (!dinfo) { - dinfo = drive_get(IF_NONE, 0, 0); - if (dinfo) { - warn_report("using \"-drive if=none\" for the OTP is deprecated, " - "use \"-drive if=pflash\" instead."); - } - } if (dinfo) { int ret; uint64_t perm; -- 2.31.1 From MAILER-DAEMON Thu Jan 12 04:15:08 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFtfw-0002NF-3A for mharc-qemu-riscv@gnu.org; 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Thu, 12 Jan 2023 01:15:01 -0800 (PST) Message-ID: Date: Thu, 12 Jan 2023 10:15:00 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH] hw/misc/sifive_u_otp: Remove the deprecated OTP config with '-drive if=none' Content-Language: en-US To: Thomas Huth , Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Markus Armbruster , qemu-block@nongnu.org References: <20230112082951.874492-1-thuth@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230112082951.874492-1-thuth@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 09:15:06 -0000 On 12/1/23 09:29, Thomas Huth wrote: > '-drive if=none' is meant for configuring back-end devices only, so this > got marked as deprecated in QEMU 6.2. Users should now only use the new > way with '-drive if=pflash' instead. > > Signed-off-by: Thomas Huth > --- > docs/about/deprecated.rst | 6 ------ > docs/about/removed-features.rst | 7 +++++++ > hw/misc/sifive_u_otp.c | 7 ------- > 3 files changed, 7 insertions(+), 13 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 12 04:15:39 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFtgP-0002Wc-QW for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 04:15:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFtgK-0002UB-9h for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 04:15:36 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFtgH-0003pQ-C7 for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 04:15:30 -0500 Received: by mail-wr1-x432.google.com with SMTP id r2so17411329wrv.7 for ; Thu, 12 Jan 2023 01:15:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=rxJi5BjmJRRSwr/bA/lb0PJCE0xQIspFvkNmfFDA1js=; b=AiBJuGK9OMM8Bcvw42LvZmu8qc6LghP0SFyeACZGkr9A6E8odOdstFomBdaC0c0fsU STjJsaWwPpk2QNtMco6ViVrKj6RBXpg4putOBxKlCWcmGBGk1q3vr37EaHKTuoUf1dBO 8zEta2hz+kfLSEe2v/yatIzswAvKp8q4hIsT71mhwLh5wK9LP+8c9zWfXcdb5dHZkY8D ybQEJAAivUFp8V/ylVCaIo0Jg/4MEjz2Wu2IrblbhZlAAIyjpj0GUbAnaQf/Pqe11ffG i8mFW5XopjjoZyjpwIZQaDWGN1DIWTD9JkncPXao/vkJ+ax/IciGyRTmvW8cc0K4HBPP OcDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=rxJi5BjmJRRSwr/bA/lb0PJCE0xQIspFvkNmfFDA1js=; b=ZtB5CVkIa5FfXF2gl90fJ0kyZSQ2j3pfabSrbpg26PgDnLnb1KiEIzF3gn1FR0r1m/ oivtmyF0GWo+XOepmUpNWR3rt/HWb7j223WBEpQ+7i5j1llZYbiyp/Z8GbryJY9tvN+J SqfwZLCKTwHhSz3L/RmiKtyNgi+oA5rhSwrC8eOOyawnK3im8IR98mmxuTZ3Y1riNdMr CFJxDKUIIDnzGTK5pXtP0rtvI90ubd+WJ5cUeiuR1VHdz79quxQelh/qGstcN2ySI4c1 UfCWzFSQoy6rsllZNRWu+PVNfqwThAndkwYK4yssoLWS2U91w2CTITGq5z7JElLp7jqE ypFA== X-Gm-Message-State: AFqh2krs/iBQBrc63Rn9O3Npygqztf5s39dM/YreyONCvXHURJMFiy/e Po0pKDC7Gsraoo3EricnWW5b/Q== X-Google-Smtp-Source: AMrXdXuD5zigCnElQEHvB7u906utAbK7O6QhsGBIByMg5vrs+bt5ns8flgYiSYSHtoHjfRL2ffWZqA== X-Received: by 2002:adf:f9cb:0:b0:285:d0ba:92e2 with SMTP id w11-20020adff9cb000000b00285d0ba92e2mr37392636wrr.47.1673514927928; Thu, 12 Jan 2023 01:15:27 -0800 (PST) Received: from [192.168.30.216] ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id n13-20020a5d67cd000000b002bdcce37d31sm2274327wrw.99.2023.01.12.01.15.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Jan 2023 01:15:27 -0800 (PST) Message-ID: <077848ec-b5c7-696c-f17b-c1bd3cd8a54c@linaro.org> Date: Thu, 12 Jan 2023 10:15:26 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v2] hw/misc/sifive_u_otp: Remove the deprecated OTP config with '-drive if=none' Content-Language: en-US To: Thomas Huth , Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Markus Armbruster , qemu-block@nongnu.org References: <20230112083921.887828-1-thuth@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230112083921.887828-1-thuth@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 09:15:36 -0000 On 12/1/23 09:39, Thomas Huth wrote: > '-drive if=none' is meant for configuring back-end devices only, so this > got marked as deprecated in QEMU 6.2. Users should now only use the new > way with '-drive if=pflash' instead. > > Signed-off-by: Thomas Huth > --- > docs/about/deprecated.rst | 6 ------ > docs/about/removed-features.rst | 7 +++++++ > hw/misc/sifive_u_otp.c | 7 ------- > 3 files changed, 7 insertions(+), 13 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 12 04:16:13 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFtgz-0002xd-C6 for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 04:16:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFtgx-0002wD-Os for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 04:16:11 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFtgv-0003tN-0D for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 04:16:11 -0500 Received: by mail-wm1-x32a.google.com with SMTP id ay12-20020a05600c1e0c00b003d9ea12bafcso10683245wmb.3 for ; Thu, 12 Jan 2023 01:16:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:references:cc:to:from :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=AetZmlO1b2EWe5EIF7NB9tiCOx7ssrEdvyQMErQTo2I=; b=P76ehxpOcKuJhLaOdLsLviOWBmM13UyHLR1h7kKeiCKF2rP8QGjxzT/L0KUIcCxEM4 XUcTf7QfwoZtgrEZF7O250SYONTTUbsPn+YEXkgYWWjBbTvBz97m80WUC5uXgsSm1QOA vNircbQozqYn9+zth28Jb+c8IpQ8F56Dy0AyL+SZ7ERDEo5LUcu9AzUM3Zf13GT7TKcH UwXw/8u7J0SxB/wGiGqCDKf0IlKlyFU22cDrN2XK33XzHVYCZiB98MkVVuoQc03ZG/PE sy3S3fhBBe1ArybzNXzuwfPPN8OUdORC/tlCBZwVevgh/Y2ZHfmOjaaju7D1asSxxrd3 ioOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:references:cc:to:from :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=AetZmlO1b2EWe5EIF7NB9tiCOx7ssrEdvyQMErQTo2I=; b=7saiZDH0Lb/5bOYZE9GomsntyYWNk1kRoe76CVeRlZD5U9Jup038cKpGaWPR+TZvm0 nCgfZxf5T2GudwfX7BTAt6Ga87EqTdZfbYQvuukp63phWOynIYk2itF4MkLZDvuW0hM8 YPkgsqyKm+UhaKRF0VrUPhiBUBWccGBr22Afr+pJbJYKlkt/lwvwFpq7520L6A++KPZM aJeOQRqKGWkUpJ8cfPsRPG8eIAEZaRwHvgqmd8hg93u4tMTBM2+55Ni8XebQ42fZOwCB OhbCSzCaIoXPLYHy3r5tgfsm6gVT1QcdlhM6D6Q5AlUU3uZQIJhP6P0LmRVUXZ4FWpUK HTLw== X-Gm-Message-State: AFqh2kpqA5XBFBrahIUuDDCgBWWvv+WOK09/GvYBqgy3FI4Bxj3Eu53w lUwO9SjTRTmOrXHbTiQcusnTYw== X-Google-Smtp-Source: AMrXdXs3p9ICvDUHEE0YFxIK2mcgYtMwDCHDH+mB+GPKtCC8o4xmAohD0tjvaHqgco8HiPQDf/HXWw== X-Received: by 2002:a1c:4b03:0:b0:3d9:103d:9081 with SMTP id y3-20020a1c4b03000000b003d9103d9081mr54799184wma.28.1673514967419; Thu, 12 Jan 2023 01:16:07 -0800 (PST) Received: from [192.168.30.216] ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id l14-20020a05600c1d0e00b003da105437besm3208040wms.29.2023.01.12.01.16.06 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Jan 2023 01:16:06 -0800 (PST) Message-ID: <28498e65-43e7-3fa0-6c2f-7f6511891572@linaro.org> Date: Thu, 12 Jan 2023 10:16:05 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH] hw/misc/sifive_u_otp: Remove the deprecated OTP config with '-drive if=none' Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= To: Thomas Huth , Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Markus Armbruster , qemu-block@nongnu.org References: <20230112082951.874492-1-thuth@redhat.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 09:16:12 -0000 On 12/1/23 10:15, Philippe Mathieu-Daudé wrote: > On 12/1/23 09:29, Thomas Huth wrote: >> '-drive if=none' is meant for configuring back-end devices only, so this >> got marked as deprecated in QEMU 6.2. Users should now only use the new >> way with '-drive if=pflash' instead. >> >> Signed-off-by: Thomas Huth >> --- >>   docs/about/deprecated.rst       | 6 ------ >>   docs/about/removed-features.rst | 7 +++++++ >>   hw/misc/sifive_u_otp.c          | 7 ------- >>   3 files changed, 7 insertions(+), 13 deletions(-) > > Reviewed-by: Philippe Mathieu-Daudé -ENOTENOUGHCOFFEEYET I read v2 and meant to reply there :P From MAILER-DAEMON Thu Jan 12 04:45:49 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFu9c-00072o-EA for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 04:45:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFu9Z-00071l-9t; Thu, 12 Jan 2023 04:45:45 -0500 Received: from mail-vs1-xe30.google.com ([2607:f8b0:4864:20::e30]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFu9U-0001q1-AS; Thu, 12 Jan 2023 04:45:42 -0500 Received: by mail-vs1-xe30.google.com with SMTP id q125so6745412vsb.0; Thu, 12 Jan 2023 01:45:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=D493d/lf6395odeXd8Z4oL1EMywgeerAnKb+g0+vV6o=; b=IXTySs+I667/BCAfEagoFk8CIQ3C58N6R7Eps/58s250J1tjBnfLLs84YkBS0VjA+R JDeT0Mx01p44HyGlZ4zL+qYbc27I25D4HlNIE8F6m6qzj7ZCEIdYW5BzKyuhW1P0QwkY 0rD0GyeUUXefRMOqvekBK7wvNMebYI7gz/gIQlLutJIBb9Qrgu1vpFhMRoBBsyu+Z7+g 1OCmdUmiaIyFt045dMbDo+KxlXeVGpr/+u5teJxgfmo68t5h0XT/z/16PSRkwbpprwZN B8kodySe8y/2dlLbpNaEPhKrRkdZ3gi77ktk9QGVK7W6Dj7oezpSEB446MX6IXoBzT7O RqVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=D493d/lf6395odeXd8Z4oL1EMywgeerAnKb+g0+vV6o=; b=BkzaXZhFqwM6AU/LjUFKJuygFa+EzO0Z0HL4ym1w6hoU+Q0svNgJ/HCak7D/ToBpRr MNv9Rm8aZf45/esa0IVQHeUIqBFfiYaDmh1jDpV/yaVsqVhVxE0HTpdlZYrr6wt8agBO 2nHKWYhhUewziRBGPGXrj6vByMmLD59R4+cUlhgFWkCSiAjNLY2H4JsdNcN2mhnt0ct9 k/OR8liKtVT4GlZVbrKeevHGO4iBfwYjaCBmR+qSSbMV9loI56EdR5zSz0gmxI/xebKE Y2oanaSEPUXUMuTfE/9OcQdW/za9KB6EVfZxfSoawI+fdnEc9F62sOlxUCsBHnFb7MkL fIqQ== X-Gm-Message-State: AFqh2krhO7wVp8REoDPeAvwmPBypUbLdauJOfOgza81uXyfUogYnBw7w /kYT1SwocyCsfOAr6yp/gOuplZYE5IiIPnsAiuU= X-Google-Smtp-Source: AMrXdXtp3UeFMDQWnj5sxRdluQeDfh9v9fi5qL7RDm702fYjW+wyZ8s98mhW/cwmLh99hlQrAtiuZD1GlyGUghKKuaQ= X-Received: by 2002:a05:6102:510e:b0:3b1:2b83:1861 with SMTP id bm14-20020a056102510e00b003b12b831861mr10025864vsb.10.1673516738156; Thu, 12 Jan 2023 01:45:38 -0800 (PST) MIME-Version: 1.0 References: <20230112083921.887828-1-thuth@redhat.com> In-Reply-To: <20230112083921.887828-1-thuth@redhat.com> From: Alistair Francis Date: Thu, 12 Jan 2023 19:45:11 +1000 Message-ID: Subject: Re: [PATCH v2] hw/misc/sifive_u_otp: Remove the deprecated OTP config with '-drive if=none' To: Thomas Huth Cc: Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Markus Armbruster , qemu-block@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e30; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe30.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 09:45:46 -0000 On Thu, Jan 12, 2023 at 6:40 PM Thomas Huth wrote: > > '-drive if=none' is meant for configuring back-end devices only, so this > got marked as deprecated in QEMU 6.2. Users should now only use the new > way with '-drive if=pflash' instead. > > Signed-off-by: Thomas Huth Reviewed-by: Alistair Francis Alistair > --- > docs/about/deprecated.rst | 6 ------ > docs/about/removed-features.rst | 7 +++++++ > hw/misc/sifive_u_otp.c | 7 ------- > 3 files changed, 7 insertions(+), 13 deletions(-) > > diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst > index 68d29642d7..bfe8148490 100644 > --- a/docs/about/deprecated.rst > +++ b/docs/about/deprecated.rst > @@ -87,12 +87,6 @@ as short-form boolean values, and passed to plugins as ``arg_name=on``. > However, short-form booleans are deprecated and full explicit ``arg_name=on`` > form is preferred. > > -``-drive if=none`` for the sifive_u OTP device (since 6.2) > -'''''''''''''''''''''''''''''''''''''''''''''''''''''''''' > - > -Using ``-drive if=none`` to configure the OTP device of the sifive_u > -RISC-V machine is deprecated. Use ``-drive if=pflash`` instead. > - > ``-no-hpet`` (since 8.0) > '''''''''''''''''''''''' > > diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst > index c918cabd1a..6bd0a2b4e4 100644 > --- a/docs/about/removed-features.rst > +++ b/docs/about/removed-features.rst > @@ -422,6 +422,13 @@ the value is hexadecimal. That is, '0x20M' should be written either as > ``tty`` and ``parport`` used to be aliases for ``serial`` and ``parallel`` > respectively. The actual backend names should be used instead. > > +``-drive if=none`` for the sifive_u OTP device (removed in 8.0) > +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' > + > +Use ``-drive if=pflash`` to configure the OTP device of the sifive_u > +RISC-V machine instead. > + > + > QEMU Machine Protocol (QMP) commands > ------------------------------------ > > diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c > index 6d7fdb040a..8965f5c22a 100644 > --- a/hw/misc/sifive_u_otp.c > +++ b/hw/misc/sifive_u_otp.c > @@ -210,13 +210,6 @@ static void sifive_u_otp_realize(DeviceState *dev, Error **errp) > sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); > > dinfo = drive_get(IF_PFLASH, 0, 0); > - if (!dinfo) { > - dinfo = drive_get(IF_NONE, 0, 0); > - if (dinfo) { > - warn_report("using \"-drive if=none\" for the OTP is deprecated, " > - "use \"-drive if=pflash\" instead."); > - } > - } > if (dinfo) { > int ret; > uint64_t perm; > -- > 2.31.1 > > From MAILER-DAEMON Thu Jan 12 04:53:02 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFuGc-0001J6-PK for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 04:53:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFuGa-0001I3-3m for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 04:53:00 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFuGY-0003Pl-3V for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 04:52:59 -0500 Received: by mail-wr1-x436.google.com with SMTP id z5so16451581wrt.6 for ; Thu, 12 Jan 2023 01:52:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=FuNcuf2D/AzRh85hRnKbWp4J5xrtPp8u+DqxFsNl8bo=; b=WPSiraDCW0GBL2b5VwsROUjmdYI1x63os+OAq62sNkwgwbYI2pVNk5V8SfvAaV2t3+ SqhjfVfsYT+zQFQwjlaCT8eX9pmvYZ9yP8bvuwkKBr28U8EN/g7hSPLTNoMbu/WigToz bqRu0H13FtkkGhTzI+KR3aoZWpvdXk82INgc0f2XjGAneWQQ+rj0F/Qg9l3ZSVgOBP6/ 5d9OPqeEY3S6ElrOPejCt5/imdsYLbUPewydOzV2ngXvmBHJBCRAITo3JQORpQQu2/2E KfZJqjFijaacT3LiyPMSUtekAHHaWDoVsWgqKzAU9lYznqZPyWsKCfYTzZbsTADAONxF 49kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=FuNcuf2D/AzRh85hRnKbWp4J5xrtPp8u+DqxFsNl8bo=; b=KzVLjcbYOkaISeQQaxw87zks4Y2mOZKaqmjZ1XjfU1V8HaYAolpqZ/HDX8Q0A3xAdp /llPSf/MgXfoXCaZY/N3TGtLUt+Y1+zJspnBD2Mzx3X8IaU3D+QDu5yKcNqGx/dmPBj6 xsIGXT3+XpEMXtQtgT+TwwgzyeMkHv7Qg0YGKaRqNfKgh9t2KiSneEcS8BTmW6GN6JnH 5R+zwHFWmggqvoJ5fJpnTV30u16VI0rLrf/h0t7I1jsV1fD58cdq913HYUYHwhuCYe04 dvUHvkkesnTH5Du7kWTyCNCJ0yNM8vlKVsLciE+I5wLdg51pyIc/JvRCALn8h40GzBm7 aaww== X-Gm-Message-State: AFqh2kqqgq0/o/JroDtOq+ZlLoLFtBfo+2QB641KcQOkBynLQf3+jmj4 ++8tP3yyCSaycSl7ynKI6jTvKCoJ3K/762cTr+k= X-Google-Smtp-Source: AMrXdXtrx0cV26dGx/B8C9w+EUQBiWR5gBXPHj6WOnqH6NvitPcYrPKR3ESxL3hS1ZFQRpkDS+IIR61+NWYqiou2TtM= X-Received: by 2002:a5d:6752:0:b0:2aa:bf1f:cc9 with SMTP id l18-20020a5d6752000000b002aabf1f0cc9mr1118495wrw.82.1673517171536; Thu, 12 Jan 2023 01:52:51 -0800 (PST) MIME-Version: 1.0 References: In-Reply-To: From: stage TC Date: Thu, 12 Jan 2023 10:52:39 +0100 Message-ID: Subject: Re: qemu icicle kit es To: Conor Dooley Cc: qemu-riscv@nongnu.org Content-Type: multipart/alternative; boundary="00000000000088f75005f20e1418" Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=stagethalescristal@gmail.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 09:53:00 -0000 --00000000000088f75005f20e1418 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Le mer. 11 janv. 2023 =C3=A0 17:40, Conor Dooley a =C3= =A9crit : >On Wed, Jan 11, 2023 at 03:21:26PM +0100, stage TC wrote: >> Hello, >> Sorry in advance if this is not the right way to do it but I'm a student >> and not very used to this kind of stuff (first mailing list). >Don't worry, you are doing fine :) >> I'm trying to run qemu for the Microchip PolarFire SoC Icicle kit but I'= m >> facing a few issues and the wiki page about that seems obsolete. >I must admit, it's a long time since I tried to use a v2020.x release of >any MPFS software. Last time I did give the steps in the docs a go, >with a suitably vintage version of QEMU, things worked as expected. >However, using more recent versions of QEMU I ran into some problems >with the sd/mmc emulation & never get into U-Boot. I was using qemu 7.1 and then came back to qemu 5.2 to try using the same version as the wiki, does the version of qemu have an impact ? Should I use a more recent one ? >> I follow almost exactly what the wiki does (except I use a terminal as a >> tty instead of the socket bc it didn't work) but my HSS won't boot on >> versions more recent than 2020.10 or 0.99.12. >What does "my HSS won't boot" mean? E.g: >- Does the MICROCHIP logo banner appear (if it existed back then!)? > If it didnt, the version string I think was. >- Does the HSS console appear? >- Does it fail to launch the next bootloader stage? With the 0.99.12 and the v2021.02 image the MICROCHIP logo banner appears with the HSS console and the next bootloader stage seems to launch correctly (see the logs in the attachment). With the 0.99.15 the MICROCHIP logo banner appears but the HSS console is stuck at "Selecting SD Card ..." With a more recent one nothing appends. >> However I can't find any image compatible for versions older than 2020.1= 0 >> or 0.99.12 (mines hang at "starting kernel ...". >By that do you mean you cannot find a pre-built yocto image? I am not >sure that there are any that pre-date the one linked in the wiki that >are still available, as those on GitHub only go back as far as v2021.02 Yes, that is what I was talking about. The link in the wiki is obsolete and the v2021.2 (the only one left with an sdcard specific version) looks to have been tested on HSS 0.99.15. >> Is there any newer version of the tutorial ? Or does anyone have an idea on >> how to deal with this issue and use qemu for newer versions of the HSS ? >I do my testing with something like: >$(QEMU)/qemu-system-riscv64 \ > -M microchip-icicle-kit \ > -m 2G -smp 5 \ > -kernel $(vmlinux_bin) \ > -dtb $(devkit).dtb \ > -initrd $(initramfs) \ > -display none \ > -serial null \ > -serial stdio >This loads a kernel directly rather than using the HSS - for recent >versions of the HSS, implementations of some peripherals need to be >added, for example, it checks things like the cache configuration >during boot, which are not emulated in QEMU. >For that reason, I've stuck with doing direct kernel boots. Linux >v6.0.18 (and the associated devicetree) is the most recent combination >that I have booted unmodified using the master branch of QEMU using >this method. Thanks, I will try to study and use this method, it may be useful. >More recent (linux) kernels come with a device tree that will require >changes in QEMU to support & I have unfortunately not had the time >to work on that recently. >Sorry that I am really of no help to you. It helps me at least to know that this is not just something easy that I'm not able to do for no reason. Thanks. >Conor. Islem --00000000000088f75005f20e1418 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable

Le mer. 11 janv. 2023 =C3=A0=C2=A017:40, Conor Dooley <conor@kernel.org> a =C3=A9crit=C2=A0:<= br>
>On Wed, Jan 11, 2023 at = 03:21:26PM +0100, stage TC wrote:
>> Hello,
>&g= t; Sorry in advance if this is not the right way to do it but I'm a stu= dent
>> and not very u= sed to this kind of stuff (first mailing list).

>Don'= ;t worry, you are doing fine :)
=
>> I'm trying to = run qemu for the Microchip PolarFire SoC Icicle kit but I'm
>> facing a few issues and the wi= ki page about that seems obsolete.
=C2=A0
>I mus= t admit, it's a long time since I tried to use a v2020.x release of
=
>any MPFS software. Last time I did give the steps in the doc= s a go,
>with a suitably vintage version of QEMU, things w= orked as expected.
>However, using more recent versions of= QEMU I ran into some problems
>with the sd/mmc emulation = & never get into U-Boot.=C2=A0

I was usin= g qemu 7.1 and then came back to qemu 5.2 to try using the same version as = the wiki, does the version of qemu have an impact ?
Should I= use a more recent one ?

>> I follow alm= ost exactly what the wiki does (except I use a terminal as a
= >> tty instead of the socket bc it didn't work) but my HSS won= 9;t boot on
>> versions more recent than 2020.10 or 0.9= 9.12.

>What does "my HSS won't boot&qu= ot; mean? E.g:
>- Does the MICROCHIP logo banner appear (i= f it existed back then!)?
>=C2=A0=C2=A0 If it didnt, the v= ersion string I think was.
>- Does the HSS console appear?=
>- Does it fail to launch the next bootloader stage?

With the 0.99.12 and the v2021.02 image the MICROCHIP = logo banner appears with the HSS console and the next bootloader stage seem= s to launch correctly (see the logs in the attachment).
With the = 0.99.15 the MICROCHIP logo banner appears but the HSS console is stuck at &= quot;Selecting SD Card ..."
With a more recent one nothing a= ppends.

>> However I can't find any = image compatible for versions older than 2020.10
>> or = 0.99.12 (mines hang at "starting kernel ...".

>By that do you mean you cannot find a pre-built yocto image? I am= not
>sure that there are any that pre-date the one linked= in the wiki that
>are still available, as those on GitHub= only go back as far as v2021.02

Yes, that is what= I was talking about. The link in the wiki is obsolete and the v2021.2 (the= only one left with an sdcard specific version) looks to have been tested o= n HSS 0.99.15.

>> Is there any newer ver= sion of the tutorial ? Or does anyone have an idea on
>>= ; how to deal with this issue and use qemu for newer versions of the HSS ?<= /div>

>I do my testing with something like:
=
>$(QEMU)/qemu-system-riscv64 \
>=C2=A0 =C2=A0 =C2= =A0 =C2=A0 -M microchip-icicle-kit \
>=C2=A0 =C2=A0 =C2=A0= =C2=A0 -m 2G -smp 5 \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 -kerne= l $(vmlinux_bin) \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 -dtb $(dev= kit).dtb \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 -initrd $(initramf= s) \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 -display none \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 -serial null \
>=C2= =A0 =C2=A0 =C2=A0 =C2=A0 -serial stdio

>This lo= ads a kernel directly rather than using the HSS - for recent
= >versions of the HSS, implementations of some peripherals need to be
=
>added, for example, it checks things like the cache configur= ation
>during boot, which are not emulated in QEMU.
<= div>
>For that reason, I've stuck with doing direct ke= rnel boots. Linux
>v6.0.18 (and the associated devicetree)= is the most recent combination
>that I have booted unmodi= fied using the master branch of QEMU using
>this method.

Thanks, I will try to study and use this method, it= may be useful.

>More recent (linux) kernel= s come with a device tree that will require
>changes in QE= MU to support & I have unfortunately not had the time
>= ;to work on that recently.
>Sorry that I am really of no help = to you.

It helps me at least to know that this is = not just something easy that I'm not able to do for no reason. Thanks. =

>Conor.

Islem
=

--00000000000088f75005f20e1418-- From MAILER-DAEMON Thu Jan 12 06:04:06 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFvNN-0008LD-1y for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 06:04:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFvNH-0008I0-Hn for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 06:04:00 -0500 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFvN1-0008Jt-1Z for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 06:03:44 -0500 Received: by mail-pf1-x42b.google.com with SMTP id c9so13523825pfj.5 for ; Thu, 12 Jan 2023 03:03:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=YRMIxmrMjxFmZ7KhnuQyQ4LQN+JFHEuz988Y3hBKhAY=; b=AE2aKbGlog+nDLpzx6+73PFOKcFOlk7OrHENBBiyt8FPDfJtjJp9iazQfWNk1uJlM0 QhMv2+Ux9eLUuLYjgMZWUkvqrbE7es6WjuMPIEs60T4Ls+D9q0/MzjqYBaO5D/adYkBZ nLgcDr0VnC6f+kKHzeT+m/f66v9V7jsPZreL9Ref5zsYSVjUQMk+NCI/f3XlF9FD4h0p wOJxBBhwgklj8lzeQO0DR7laeFBaDePYrZfypE63u0O/Ijnim3Qg/vKTEBQfhWb/FDZ3 bh9hcjDTqiCPNZ6NKrduBHZtkSr3wrmKYWvOgX+Ta+5LYTfWRaUENMdezVR8C8dPh7E4 HGZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YRMIxmrMjxFmZ7KhnuQyQ4LQN+JFHEuz988Y3hBKhAY=; b=YtjLPUI8wsGWcOMCMB825gb9lWZ6qHMTkMV9RCGtvlQU/jLsucwrA/ph7aRM0ndc+w MaxZmafNIL6TgPAXPUadc0c43BtOIRpHkoWyshsosxJLnSDzNwv9NRlol8C7E2wevCGW TV7jCTZ3J/GJ7cO9uUc6X61APNv8xkCWX2uDVu1PdqYCIGyYUR9zDeoyJK7gd268XytN W2eW+G+zcKOzpttFUrv80a2wvaFmUDU6MtlAZH7uaHRMNIPOPngnm5VlAjnQdSKhllyk Qi0TMMJKvyYGi+v4nSC11OKnf+XknuMU7FttsVYE2m3ciiw2xgoHFSAEpVzxyc/pjjPJ vjuA== X-Gm-Message-State: AFqh2krbqjwzC+CPFW794uQDUJH4NIja3cbbt3bzHvN16aeBecAubDvk QTOVWU/tIzQbJTqiTclRsiLfOzLmT/MzgA3e+mkBgw== X-Google-Smtp-Source: AMrXdXu5V4bX22nwNZjWYHOvPbmvbmEPrM5ZbLD1wZubhZ6omG79rXH/n1MH1qTGUPIgVjvQP0rVQQGio1U3g6Ik/Ao= X-Received: by 2002:a63:e20b:0:b0:479:18a:8359 with SMTP id q11-20020a63e20b000000b00479018a8359mr4968225pgh.105.1673521421294; Thu, 12 Jan 2023 03:03:41 -0800 (PST) MIME-Version: 1.0 References: <20230110212947.34557-1-philmd@linaro.org> In-Reply-To: From: Peter Maydell Date: Thu, 12 Jan 2023 11:03:29 +0000 Message-ID: Subject: Re: [PATCH] bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx To: BALATON Zoltan Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Richard Henderson , =?UTF-8?B?QWxleCBCZW5uw6ll?= , ale@rev.ng, qemu-riscv@nongnu.org, xen-devel@lists.xenproject.org, Thomas Huth Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 11:04:02 -0000 On Tue, 10 Jan 2023 at 22:04, BALATON Zoltan wrote: > > On Tue, 10 Jan 2023, Philippe Mathieu-Daud=C3=A9 wrote: > > The 'hwaddr' type is defined in "exec/hwaddr.h" as: > > > > hwaddr is the type of a physical address > > (its size can be different from 'target_ulong'). > > > > All definitions use the 'HWADDR_' prefix, except TARGET_FMT_plx: > > > > $ fgrep define include/exec/hwaddr.h > > #define HWADDR_H > > #define HWADDR_BITS 64 > > #define HWADDR_MAX UINT64_MAX > > #define TARGET_FMT_plx "%016" PRIx64 > > ^^^^^^ > > #define HWADDR_PRId PRId64 > > #define HWADDR_PRIi PRIi64 > > #define HWADDR_PRIo PRIo64 > > #define HWADDR_PRIu PRIu64 > > #define HWADDR_PRIx PRIx64 > > Why are there both TARGET_FMT_plx and HWADDR_PRIx? Why not just use > HWADDR_PRIx instead? TARGET_FMT_plx is part of a family of defines for printing target_foo types; the rest are in cpu-defs.h. These all include the '%' character. This is more convenient to use, but it's also out-of-line with the C standard format macros like PRIx64. The HWADDR_* macros take the approach of aligning with how you use the C standard format macros. As usual in QEMU, where there are two different ways of doing things, it's probably because one of them is a lot older than the other and written by a different person. In theory it would be nice to apply some consistency here but it rarely seems worth the effort of the bulk code edit. thanks -- PMM From MAILER-DAEMON Thu Jan 12 06:50:51 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFw6X-0000uA-MC for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 06:50:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFw64-0000q9-Vr for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 06:50:20 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFw62-0000SM-LK for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 06:50:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1673524214; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pm9no63Gh/VwyX03yviNU3MTjFd5bbQ28HgEQPd/cVs=; b=OzfyKrYMat4jmrbWUIqI3A80p6weKkJR/pNuy0spis8Zha25WHeCpERBlTEAa5h0S3d7yM Kr8SP6QjL75dFo9lZT1e2s0iN1aY+rVAFrG/hocTgpT+zKsNbKNUZVsY6kCgFFX9V+RmG8 vnKGVZ60eW074GLPUZBiwraKdSWUdFY= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-265-Q76FFjMAPdytH4irqvepRQ-1; Thu, 12 Jan 2023 06:50:08 -0500 X-MC-Unique: Q76FFjMAPdytH4irqvepRQ-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 194B71C0691B; Thu, 12 Jan 2023 11:50:08 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.78]) by smtp.corp.redhat.com (Postfix) with ESMTPS id E3CC12026D68; Thu, 12 Jan 2023 11:50:06 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id DF8E921E5DF6; Thu, 12 Jan 2023 12:50:05 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, ben.widawsky@intel.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, jasowang@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, philmd@linaro.org, mst@redhat.com, Bin Meng Subject: [PATCH v3 1/1] include: Don't include qemu/osdep.h Date: Thu, 12 Jan 2023 12:50:05 +0100 Message-Id: <20230112115005.1504812-2-armbru@redhat.com> In-Reply-To: <20230112115005.1504812-1-armbru@redhat.com> References: <20230112115005.1504812-1-armbru@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.4 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 11:50:28 -0000 docs/devel/style.rst mandates: The "qemu/osdep.h" header contains preprocessor macros that affect the behavior of core system headers like . It must be the first include so that core system headers included by external libraries get the preprocessor macros that QEMU depends on. Do not include "qemu/osdep.h" from header files since the .c file will have already included it. A few violations have crept in. Fix them. Signed-off-by: Markus Armbruster Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Reviewed-by: Taylor Simpson Reviewed-by: Alistair Francis --- bsd-user/qemu.h | 1 - crypto/block-luks-priv.h | 1 - include/hw/cxl/cxl_host.h | 1 - include/hw/input/pl050.h | 1 - include/hw/tricore/triboard.h | 1 - include/qemu/userfaultfd.h | 1 - net/vmnet_int.h | 1 - qga/cutils.h | 1 - target/hexagon/hex_arch_types.h | 1 - target/hexagon/mmvec/macros.h | 1 - target/riscv/pmu.h | 1 - bsd-user/arm/signal.c | 1 + bsd-user/arm/target_arch_cpu.c | 2 ++ bsd-user/freebsd/os-sys.c | 1 + bsd-user/i386/signal.c | 1 + bsd-user/x86_64/signal.c | 1 + qga/cutils.c | 3 ++- 17 files changed, 8 insertions(+), 12 deletions(-) diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index be6105385e..0ceecfb6df 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -17,7 +17,6 @@ #ifndef QEMU_H #define QEMU_H -#include "qemu/osdep.h" #include "cpu.h" #include "qemu/units.h" #include "exec/cpu_ldst.h" diff --git a/crypto/block-luks-priv.h b/crypto/block-luks-priv.h index 90a20d432b..1066df0307 100644 --- a/crypto/block-luks-priv.h +++ b/crypto/block-luks-priv.h @@ -18,7 +18,6 @@ * */ -#include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/bswap.h" diff --git a/include/hw/cxl/cxl_host.h b/include/hw/cxl/cxl_host.h index a1b662ce40..c9bc9c7c50 100644 --- a/include/hw/cxl/cxl_host.h +++ b/include/hw/cxl/cxl_host.h @@ -7,7 +7,6 @@ * COPYING file in the top-level directory. */ -#include "qemu/osdep.h" #include "hw/cxl/cxl.h" #include "hw/boards.h" diff --git a/include/hw/input/pl050.h b/include/hw/input/pl050.h index 89ec4fafc9..4cb8985f31 100644 --- a/include/hw/input/pl050.h +++ b/include/hw/input/pl050.h @@ -10,7 +10,6 @@ #ifndef HW_PL050_H #define HW_PL050_H -#include "qemu/osdep.h" #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/input/ps2.h" diff --git a/include/hw/tricore/triboard.h b/include/hw/tricore/triboard.h index 094c8bd563..4fdd2d7d97 100644 --- a/include/hw/tricore/triboard.h +++ b/include/hw/tricore/triboard.h @@ -18,7 +18,6 @@ * License along with this library; if not, see . */ -#include "qemu/osdep.h" #include "qapi/error.h" #include "hw/boards.h" #include "sysemu/sysemu.h" diff --git a/include/qemu/userfaultfd.h b/include/qemu/userfaultfd.h index 6b74f92792..55c95998e8 100644 --- a/include/qemu/userfaultfd.h +++ b/include/qemu/userfaultfd.h @@ -13,7 +13,6 @@ #ifndef USERFAULTFD_H #define USERFAULTFD_H -#include "qemu/osdep.h" #include "exec/hwaddr.h" #include diff --git a/net/vmnet_int.h b/net/vmnet_int.h index adf6e8c20d..d0b90594f2 100644 --- a/net/vmnet_int.h +++ b/net/vmnet_int.h @@ -10,7 +10,6 @@ #ifndef VMNET_INT_H #define VMNET_INT_H -#include "qemu/osdep.h" #include "vmnet_int.h" #include "clients.h" diff --git a/qga/cutils.h b/qga/cutils.h index f0f30a7d28..2bfaf554a8 100644 --- a/qga/cutils.h +++ b/qga/cutils.h @@ -1,7 +1,6 @@ #ifndef CUTILS_H_ #define CUTILS_H_ -#include "qemu/osdep.h" int qga_open_cloexec(const char *name, int flags, mode_t mode); diff --git a/target/hexagon/hex_arch_types.h b/target/hexagon/hex_arch_types.h index 885f68f760..52a7f2b2f3 100644 --- a/target/hexagon/hex_arch_types.h +++ b/target/hexagon/hex_arch_types.h @@ -18,7 +18,6 @@ #ifndef HEXAGON_HEX_ARCH_TYPES_H #define HEXAGON_HEX_ARCH_TYPES_H -#include "qemu/osdep.h" #include "mmvec/mmvec.h" #include "qemu/int128.h" diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index 8c864e8c68..1201d778d0 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -18,7 +18,6 @@ #ifndef HEXAGON_MMVEC_MACROS_H #define HEXAGON_MMVEC_MACROS_H -#include "qemu/osdep.h" #include "qemu/host-utils.h" #include "arch.h" #include "mmvec/system_ext_mmvec.h" diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 3004ce37b6..0c819ca983 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -16,7 +16,6 @@ * this program. If not, see . */ -#include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" #include "qemu/main-loop.h" diff --git a/bsd-user/arm/signal.c b/bsd-user/arm/signal.c index 2b1dd745d1..9734407543 100644 --- a/bsd-user/arm/signal.c +++ b/bsd-user/arm/signal.c @@ -17,6 +17,7 @@ * along with this program; if not, see . */ +#include "qemu/osdep.h" #include "qemu.h" /* diff --git a/bsd-user/arm/target_arch_cpu.c b/bsd-user/arm/target_arch_cpu.c index 02bf9149d5..fe38ae2210 100644 --- a/bsd-user/arm/target_arch_cpu.c +++ b/bsd-user/arm/target_arch_cpu.c @@ -16,6 +16,8 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, see . */ + +#include "qemu/osdep.h" #include "target_arch.h" void target_cpu_set_tls(CPUARMState *env, target_ulong newtls) diff --git a/bsd-user/freebsd/os-sys.c b/bsd-user/freebsd/os-sys.c index 309e27b9d6..1676ec10f8 100644 --- a/bsd-user/freebsd/os-sys.c +++ b/bsd-user/freebsd/os-sys.c @@ -17,6 +17,7 @@ * along with this program; if not, see . */ +#include "qemu/osdep.h" #include "qemu.h" #include "target_arch_sysarch.h" diff --git a/bsd-user/i386/signal.c b/bsd-user/i386/signal.c index 5dd975ce56..a3131047b8 100644 --- a/bsd-user/i386/signal.c +++ b/bsd-user/i386/signal.c @@ -17,6 +17,7 @@ * along with this program; if not, see . */ +#include "qemu/osdep.h" #include "qemu.h" /* diff --git a/bsd-user/x86_64/signal.c b/bsd-user/x86_64/signal.c index c3875bc4c6..46cb865180 100644 --- a/bsd-user/x86_64/signal.c +++ b/bsd-user/x86_64/signal.c @@ -16,6 +16,7 @@ * along with this program; if not, see . */ +#include "qemu/osdep.h" #include "qemu.h" /* diff --git a/qga/cutils.c b/qga/cutils.c index b8e142ef64..b21bcf3683 100644 --- a/qga/cutils.c +++ b/qga/cutils.c @@ -2,8 +2,9 @@ * This work is licensed under the terms of the GNU GPL, version 2 or later. * See the COPYING file in the top-level directory. */ -#include "cutils.h" +#include "qemu/osdep.h" +#include "cutils.h" #include "qapi/error.h" /** -- 2.39.0 From MAILER-DAEMON Thu Jan 12 06:51:04 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFw6o-0000ys-7p for mharc-qemu-riscv@gnu.org; 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Thu, 12 Jan 2023 06:50:08 -0500 X-MC-Unique: fUVLaQU1MJS32GSsPi4rMg-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id EF48085CBE2; Thu, 12 Jan 2023 11:50:07 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.78]) by smtp.corp.redhat.com (Postfix) with ESMTPS id E369E1121314; Thu, 12 Jan 2023 11:50:06 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id DD5A621E5DCF; Thu, 12 Jan 2023 12:50:05 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, ben.widawsky@intel.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, jasowang@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, philmd@linaro.org, mst@redhat.com Subject: [PATCH v3 0/1] Clean up includes Date: Thu, 12 Jan 2023 12:50:04 +0100 Message-Id: <20230112115005.1504812-1-armbru@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 11:50:28 -0000 Back in 2016, we discussed[1] rules for headers, and these were generally liked: 1. Have a carefully curated header that's included everywhere first. We got that already thanks to Peter: osdep.h. 2. Headers should normally include everything they need beyond osdep.h. If exceptions are needed for some reason, they must be documented in the header. If all that's needed from a header is typedefs, put those into qemu/typedefs.h instead of including the header. 3. Cyclic inclusion is forbidden. This series fixes a number of rule violations. Together with [PATCH v2 0/4] hw/ppc: Clean up includes [PATCH v2 0/7] include/hw/pci include/hw/cxl: Clean up includes in master as commit 9d94c21363..881e019770 [PATCH v2 0/3] block: Clean up includes [PATCH v3 0/5] coroutine: Clean up includes just three inclusion loops remain reachable from include/: target/microblaze/cpu.h target/microblaze/mmu.h target/nios2/cpu.h target/nios2/mmu.h target/riscv/cpu.h target/riscv/pmp.h Breaking them would be nice, but I'm out of steam. v3: * Rebased, old PATCH 1+2+4 are in master as commit 881e019770..f07ceffdf5 * PATCH 1: Fix bsd-user v2: * Rebased * PATCH 3: v1 posted separately * PATCH 4: New [1] Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org> https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html Markus Armbruster (1): include: Don't include qemu/osdep.h bsd-user/qemu.h | 1 - crypto/block-luks-priv.h | 1 - include/hw/cxl/cxl_host.h | 1 - include/hw/input/pl050.h | 1 - include/hw/tricore/triboard.h | 1 - include/qemu/userfaultfd.h | 1 - net/vmnet_int.h | 1 - qga/cutils.h | 1 - target/hexagon/hex_arch_types.h | 1 - target/hexagon/mmvec/macros.h | 1 - target/riscv/pmu.h | 1 - bsd-user/arm/signal.c | 1 + bsd-user/arm/target_arch_cpu.c | 2 ++ bsd-user/freebsd/os-sys.c | 1 + bsd-user/i386/signal.c | 1 + bsd-user/x86_64/signal.c | 1 + qga/cutils.c | 3 ++- 17 files changed, 8 insertions(+), 12 deletions(-) -- 2.39.0 From MAILER-DAEMON Thu Jan 12 08:24:43 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFxZT-000155-AK for mharc-qemu-riscv@gnu.org; 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Thu, 12 Jan 2023 05:24:36 -0800 (PST) Message-ID: <07be21f4-ba88-1bdf-62c6-09adcf5dfecc@ventanamicro.com> Date: Thu, 12 Jan 2023 10:24:33 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH v5 10/11] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() To: Alistair Francis Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng , Palmer Dabbelt References: <20230102115241.25733-1-dbarboza@ventanamicro.com> <20230102115241.25733-11-dbarboza@ventanamicro.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 13:24:41 -0000 On 1/11/23 21:34, Alistair Francis wrote: > On Mon, Jan 2, 2023 at 9:55 PM Daniel Henrique Barboza > wrote: >> The microchip_icicle_kit, sifive_u, spike and virt boards are now doing >> the same steps when '-kernel' is used: >> >> - execute load_kernel() >> - load init_rd() >> - write kernel_cmdline >> >> Let's fold everything inside riscv_load_kernel() to avoid code >> repetition. To not change the behavior of boards that aren't calling >> riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and >> allow these boards to opt out from initrd loading. >> >> Cc: Palmer Dabbelt >> Signed-off-by: Daniel Henrique Barboza >> --- >> hw/riscv/boot.c | 22 +++++++++++++++++++--- >> hw/riscv/microchip_pfsoc.c | 12 ++---------- >> hw/riscv/opentitan.c | 2 +- >> hw/riscv/sifive_e.c | 3 ++- >> hw/riscv/sifive_u.c | 12 ++---------- >> hw/riscv/spike.c | 11 +---------- >> hw/riscv/virt.c | 12 ++---------- >> include/hw/riscv/boot.h | 1 + >> 8 files changed, 30 insertions(+), 45 deletions(-) >> >> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c >> index 2594276223..4888d5c1e0 100644 >> --- a/hw/riscv/boot.c >> +++ b/hw/riscv/boot.c >> @@ -175,10 +175,12 @@ target_ulong riscv_load_firmware(const char *firmware_filename, >> >> target_ulong riscv_load_kernel(MachineState *machine, >> target_ulong kernel_start_addr, >> + bool load_initrd, >> symbol_fn_t sym_cb) >> { >> const char *kernel_filename = machine->kernel_filename; >> uint64_t kernel_load_base, kernel_entry; >> + void *fdt = machine->fdt; >> >> g_assert(kernel_filename != NULL); >> >> @@ -192,21 +194,35 @@ target_ulong riscv_load_kernel(MachineState *machine, >> if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, >> NULL, &kernel_load_base, NULL, NULL, 0, >> EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { >> - return kernel_load_base; >> + kernel_entry = kernel_load_base; > This breaks 32-bit Xvisor loading. It seems that for the 32-bit guest > we get a value of 0xffffffff80000000. > > Previously the top bits would be lost as we return a target_ulong from > this function, but with this change we pass the value > 0xffffffff80000000 to riscv_load_initrd() which causes failures. > > This diff fixes the failure for me > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 4888d5c1e0..f08ed44b97 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -194,7 +194,7 @@ target_ulong riscv_load_kernel(MachineState *machine, > if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, > NULL, &kernel_load_base, NULL, NULL, 0, > EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { > - kernel_entry = kernel_load_base; > + kernel_entry = (target_ulong) kernel_load_base; > goto out; > } > > > but I don't think that's the right fix. We should instead look at the > CPU XLEN and drop the high bits if required. > > I'm going to drop this patch, do you mind looking into a proper fix? Thanks for looking this up! I 'll fix it and resend patches 10 and 11. Daniel > > Alistair From MAILER-DAEMON Thu Jan 12 08:52:10 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFy00-0003Ux-0Q for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 08:52:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFxzd-0002vZ-VD for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 08:51:52 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFxzV-0003kT-G4 for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 08:51:41 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1673531495; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1kd6neTRgQmgMh6DNG6DwXYTgAy1+iQonnVyEcqozWM=; b=M3QChTRs9IMVNBdFmIKFEcC/xyjX/mF3YLS4twNJZB3F5zdCq2Da+gwMuF3DwY0F4RQ/ne nnbHv/oev5c5PM+hVXuxvbdVgJSt2bwB3kgZfXt60UJ5RAEBqNjzu+r9SRSO/IhOekY2mv KSHNat6B2mnXVj9V5Kkgdl1fn+jmc/Y= Received: from mail-wm1-f69.google.com (mail-wm1-f69.google.com [209.85.128.69]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-647-eTcFwHCVN6qRrC8DQ-_i8g-1; Thu, 12 Jan 2023 08:51:33 -0500 X-MC-Unique: eTcFwHCVN6qRrC8DQ-_i8g-1 Received: by mail-wm1-f69.google.com with SMTP id f20-20020a7bc8d4000000b003d1cda5bd6fso4295591wml.9 for ; Thu, 12 Jan 2023 05:51:32 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=1kd6neTRgQmgMh6DNG6DwXYTgAy1+iQonnVyEcqozWM=; b=inFjHRWSDNoKwXND29M8tUdPPCVZkw+1pOLjHnTSwapB9aB4rgorGo0yZzgiV+lLgs HPPIwjFls8WQVNru0XqrjTgBeIYEg5MfbIfkaRt/iPOpjXAkDKn4hMz30xDuOOd4rEIL xEPFz07H3Z5nU3hfGDBzElffkfE34FbZDTVcIL+f+fVxG3Ext6OnL1RX3tC4Ctpbdt3P YiVTcx4ID8kugcObKT4vLKpXyfSZF6Jns1C6Xu1Cj0BF1Ua4JzRDtAg8G//GJ34S5QLk 7XrI9fgImLEqmxJkP0l1HmeJJ+un2QwbhItb5XXNavYabuQpIDspSoCIyNEDlKCuNPeP qQgg== X-Gm-Message-State: AFqh2krFAmCMRJM5CBCfX8Cn0nTq6QGFB/QNIYKn3TpxH4AELcmDBWAX +01JDAUAVvDpASI2ZT/DgQTQ6pHs0LZezFDkeRE9j90aOxAcN44cM28VONB752ih0M7nczf7au3 Us9n1WtMGH4JC0QE= X-Received: by 2002:a5d:6443:0:b0:2ba:ecb4:5e19 with SMTP id d3-20020a5d6443000000b002baecb45e19mr14872466wrw.11.1673531491944; Thu, 12 Jan 2023 05:51:31 -0800 (PST) X-Google-Smtp-Source: AMrXdXuCDWMX0+MZ6xrmfjPzxy6tksZkIeYbgnZCPZJmOxg8ZdZz+JvkCWpNGGEsq87he7gMEfFuPQ== X-Received: by 2002:a5d:6443:0:b0:2ba:ecb4:5e19 with SMTP id d3-20020a5d6443000000b002baecb45e19mr14872431wrw.11.1673531491584; Thu, 12 Jan 2023 05:51:31 -0800 (PST) Received: from redhat.com ([2.52.157.155]) by smtp.gmail.com with ESMTPSA id z9-20020a7bc7c9000000b003d9ef37ec1bsm17340547wmk.5.2023.01.12.05.51.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jan 2023 05:51:30 -0800 (PST) Date: Thu, 12 Jan 2023 08:51:26 -0500 From: "Michael S. Tsirkin" To: Markus Armbruster Cc: qemu-devel@nongnu.org, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, ben.widawsky@intel.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, jasowang@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, philmd@linaro.org, Bin Meng Subject: Re: [PATCH v3 1/1] include: Don't include qemu/osdep.h Message-ID: <20230112082537-mutt-send-email-mst@kernel.org> References: <20230112115005.1504812-1-armbru@redhat.com> <20230112115005.1504812-2-armbru@redhat.com> MIME-Version: 1.0 In-Reply-To: <20230112115005.1504812-2-armbru@redhat.com> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 13:51:56 -0000 On Thu, Jan 12, 2023 at 12:50:05PM +0100, Markus Armbruster wrote: > docs/devel/style.rst mandates: > > The "qemu/osdep.h" header contains preprocessor macros that affect > the behavior of core system headers like . It must be > the first include so that core system headers included by external > libraries get the preprocessor macros that QEMU depends on. > > Do not include "qemu/osdep.h" from header files since the .c file > will have already included it. > > A few violations have crept in. Fix them. > > Signed-off-by: Markus Armbruster > Reviewed-by: Philippe Mathieu-Daudé > Reviewed-by: Bin Meng > Reviewed-by: Taylor Simpson > Reviewed-by: Alistair Francis With my awesome grep skillz I found one more: $ grep -r --include='*.h' qemu/osdep.h include/block/graph-lock.h:#include "qemu/osdep.h" Looks like all C files must include qemu/osdep.h, no? How about 1- add -include qemu/osdep.h on compile command line drop #include "qemu/osdep.h" from C files 2- drop double include guards, replace with a warning. following patch implements part 2: qemu/osdep: don't include it from headers doing so will lead to trouble eventually - instead of working around such cases make it more likely it will fail. Signed-off-by: Michael S. Tsirkin --- diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 7d059ad526..e4a60f911c 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -24,7 +24,12 @@ * This work is licensed under the terms of the GNU GPL, version 2 or later. * See the COPYING file in the top-level directory. */ -#ifndef QEMU_OSDEP_H +#ifdef QEMU_OSDEP_H +#warning "Never include qemu/osdep.h from a header!" +#endif + +static inline void qemu_osdep_never_include_from_header(void) {} + #define QEMU_OSDEP_H #include "config-host.h" @@ -714,5 +719,3 @@ static inline int platform_does_not_support_system(const char *command) #ifdef __cplusplus } #endif - -#endif From MAILER-DAEMON Thu Jan 12 08:56:52 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFy4Z-0006oN-Rz for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 08:56:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFy4D-0006jQ-On for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 08:56:29 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFy3v-0004YV-DS for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 08:56:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1673531770; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VJ9f+embDPz9PYDeSIaeJDx8u76O2BFiQiTfKwfIaTk=; b=TJqOPnHRShB18mD6a0D4Z+T/V3tGjRIHCmZUM0HRk4YCKjA6b6xEQWlTmuHdSKldu4oAmB X5VgOL4si9ygoMHEoEa282AI67enX2N5Hww4vbDS5l8NXkgJWHSL1lB3lPi37DhcB1TT9+ CVI5LGLKzF7T//dUevaNfYtRI5wu6iQ= Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-619-TnBN5c2BOZWwibzmGKfIgw-1; Thu, 12 Jan 2023 08:56:09 -0500 X-MC-Unique: TnBN5c2BOZWwibzmGKfIgw-1 Received: by mail-wr1-f72.google.com with SMTP id r10-20020adfa14a000000b0025ba73dff40so3495544wrr.12 for ; Thu, 12 Jan 2023 05:56:09 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=VJ9f+embDPz9PYDeSIaeJDx8u76O2BFiQiTfKwfIaTk=; b=D5MN2Pjl2f+MlTZWHQ/ujUDI+U2FDIlSuJPeIrThCpMFOn4Gfy2VUzFoXuC8v8vBhQ UckegaIN2dU2h5s8nt0s+FscswxlHXx2L2q0jJTNxWf4IzXHXQr81gVPSTd1JJAfcF5n gZa2zliKPgA90MybX7LMbB3F5GVxPhLKWoTNA+NaqY/kyTChdLujaVAqHni/LfnJaiLD x6kl83rJFKBwMlRwjyyeIczOdJou1jc8BJ53hxaP8UMEYv+L9yslpxvUUVhz4oKO37q0 EJFstKL4qxQQq0mKI7aC9wZC3wdj0gVRPpcLi38uhI2iZxoJQQhQAjRTNNqAuuGmx3t6 IX2w== X-Gm-Message-State: AFqh2ko7LgPs7qV+gEjYc5hTRqhJfvPyllS+ovMFtrphlbEkiZ21arTb 9hwrbiPhpVjI6SEQC66oRz8/MM9cd6Em/+ZSbX6/YaKltRwqHc203RT7d2MCJqqzPSAkMF6wlfc XQRx6WrIInKScdlM= X-Received: by 2002:a05:600c:358c:b0:3d9:fa37:e457 with SMTP id p12-20020a05600c358c00b003d9fa37e457mr7593933wmq.15.1673531768168; Thu, 12 Jan 2023 05:56:08 -0800 (PST) X-Google-Smtp-Source: AMrXdXtocFfslYukPkoG1dmkAZXVRuJ02lZghNlYjRzexqYJR34IEREBRqOnPYjJHzDz4/JLfFKW2Q== X-Received: by 2002:a05:600c:358c:b0:3d9:fa37:e457 with SMTP id p12-20020a05600c358c00b003d9fa37e457mr7593922wmq.15.1673531767913; Thu, 12 Jan 2023 05:56:07 -0800 (PST) Received: from redhat.com ([2.52.157.155]) by smtp.gmail.com with ESMTPSA id i14-20020a05600c354e00b003d1d5a83b2esm29300208wmq.35.2023.01.12.05.56.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jan 2023 05:56:07 -0800 (PST) Date: Thu, 12 Jan 2023 08:56:03 -0500 From: "Michael S. Tsirkin" To: Markus Armbruster Cc: qemu-devel@nongnu.org, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, ben.widawsky@intel.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, jasowang@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, philmd@linaro.org, Bin Meng Subject: Re: [PATCH v3 1/1] include: Don't include qemu/osdep.h Message-ID: <20230112085520-mutt-send-email-mst@kernel.org> References: <20230112115005.1504812-1-armbru@redhat.com> <20230112115005.1504812-2-armbru@redhat.com> <20230112082537-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 In-Reply-To: <20230112082537-mutt-send-email-mst@kernel.org> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 13:56:38 -0000 On Thu, Jan 12, 2023 at 08:51:32AM -0500, Michael S. Tsirkin wrote: > On Thu, Jan 12, 2023 at 12:50:05PM +0100, Markus Armbruster wrote: > > docs/devel/style.rst mandates: > > > > The "qemu/osdep.h" header contains preprocessor macros that affect > > the behavior of core system headers like . It must be > > the first include so that core system headers included by external > > libraries get the preprocessor macros that QEMU depends on. > > > > Do not include "qemu/osdep.h" from header files since the .c file > > will have already included it. > > > > A few violations have crept in. Fix them. > > > > Signed-off-by: Markus Armbruster > > Reviewed-by: Philippe Mathieu-Daudé > > Reviewed-by: Bin Meng > > Reviewed-by: Taylor Simpson > > Reviewed-by: Alistair Francis > > With my awesome grep skillz I found one more: > $ grep -r --include='*.h' qemu/osdep.h > include/block/graph-lock.h:#include "qemu/osdep.h" Also: $ grep -r --include='*.inc' qemu/osdep.h ui/vnc-enc-zrle.c.inc:#include "qemu/osdep.h" crypto/akcipher-nettle.c.inc:#include "qemu/osdep.h" crypto/akcipher-gcrypt.c.inc:#include "qemu/osdep.h" crypto/rsakey-nettle.c.inc:#include "qemu/osdep.h" crypto/cipher-gnutls.c.inc:#include "qemu/osdep.h" target/xtensa/core-dc233c/xtensa-modules.c.inc:#include "qemu/osdep.h" target/xtensa/core-sample_controller/xtensa-modules.c.inc:#include "qemu/osdep.h" target/xtensa/core-de212/xtensa-modules.c.inc:#include "qemu/osdep.h" target/xtensa/core-dc232b/xtensa-modules.c.inc:#include "qemu/osdep.h" target/xtensa/core-fsf/xtensa-modules.c.inc:#include "qemu/osdep.h" target/cris/translate_v10.c.inc:#include "qemu/osdep.h" > Looks like all C files must include qemu/osdep.h, no? > How about > > 1- add -include qemu/osdep.h on compile command line > drop #include "qemu/osdep.h" from C files > 2- drop double include guards, replace with a warning. > > following patch implements part 2: > > > qemu/osdep: don't include it from headers > > doing so will lead to trouble eventually - instead of > working around such cases make it more likely it will fail. > > Signed-off-by: Michael S. Tsirkin > > --- > > diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h > index 7d059ad526..e4a60f911c 100644 > --- a/include/qemu/osdep.h > +++ b/include/qemu/osdep.h > @@ -24,7 +24,12 @@ > * This work is licensed under the terms of the GNU GPL, version 2 or later. > * See the COPYING file in the top-level directory. > */ > -#ifndef QEMU_OSDEP_H > +#ifdef QEMU_OSDEP_H > +#warning "Never include qemu/osdep.h from a header!" > +#endif > + > +static inline void qemu_osdep_never_include_from_header(void) {} > + > #define QEMU_OSDEP_H > > #include "config-host.h" > @@ -714,5 +719,3 @@ static inline int platform_does_not_support_system(const char *command) > #ifdef __cplusplus > } > #endif > - > -#endif From MAILER-DAEMON Thu Jan 12 08:56:52 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFy4a-0006om-7l for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 08:56:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFy4D-0006jO-Os for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 08:56:29 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFy3p-0004Y5-Kj for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 08:56:10 -0500 Received: by mail-wm1-x32f.google.com with SMTP id m26-20020a05600c3b1a00b003d9811fcaafso15097669wms.5 for ; Thu, 12 Jan 2023 05:56:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=bR4Af2RZyxEDuvk4gSG5bIeoG+aXm1oIHB0AEur0ySg=; b=6qqUOMLt3y65svjlY+lEMDxkWhvRRKLwmHco3610SSn+fatnKAPYnOSPoquyiehYoq w/ZXjkI54UciLbkYGCLzaDj+nV1v+CoOUFi3XsQw+gmN08wsZedaxm0yCrCm85NtqYOa i+AIHd1yymSG7HVbM5SF3OcQAuY75ml8JolU3whQFfiK2N8mgxWP0Ks6w7FGJws1oel1 H2GRTQh5BlTYQujBB9Uv+VpLDNFv0hhjwPyuRr0nWyALJXTeBcX8wBs1s0ctFStejLeG 85pGQ5ps2Oki6EpjNpximojgYanoDkmQ31wZ9CVv0UMO/XWY0h4KruGk8oNCCriz2zaW oQfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=bR4Af2RZyxEDuvk4gSG5bIeoG+aXm1oIHB0AEur0ySg=; b=Px6YknJjFHAH+bBw8OMdndVzqfrVb/1vD/Nl8WaR7ZEYZlIn7PNdCyqg8g9DAGeakS 3q9Whq5aLoa5J82KMPOk8+QrU3Mh1t0r018EFExQr49Y0Jc2jgLBJefdb+1KYCnQxc8H apcjqACSJdCMxX5/TBGNytRMGkz4609QwgA6xgEicng+cc0wdU39mNcEpeFaNiYv0tBR 7/cXhNgdGySIQWnKvPLqT8zQDSrGYDBmdhkhIfcpB8CZHBvSM7pCXkML5Tn8QZOzX3pc iKjNLKPzKX7Qt2kXrrk7WbwfhJEm4+iECRKDDWEhZvfhSXoHBVppKCRf7r2mHN6QeDIv DtQA== X-Gm-Message-State: AFqh2kro5UQTdHKJ/gpeiT7SVS/XXPpAaF4izaztaHgpXTl/GcFlLNkC EUiAnI0Tqi8oxPNAUmOSTa3CUwkPTnR3S3XGZ/TyHw== X-Google-Smtp-Source: AMrXdXvqv1JKgKk3zPLh3mqYCFsu24d6979hj9Ejh8pmRONNakUwuSFH8J7+6Po6nm1JyLpu+VqIvKun1DijbTTsjRs= X-Received: by 2002:a1c:4c02:0:b0:3d9:fbc2:578 with SMTP id z2-20020a1c4c02000000b003d9fbc20578mr397312wmf.155.1673531763350; Thu, 12 Jan 2023 05:56:03 -0800 (PST) MIME-Version: 1.0 References: <20221212102250.3365948-1-alexghiti@rivosinc.com> <20230106163045.jerqbds3mgi3ri4e@orel> In-Reply-To: <20230106163045.jerqbds3mgi3ri4e@orel> From: Alexandre Ghiti Date: Thu, 12 Jan 2023 13:55:52 +0000 Message-ID: Subject: Re: [PATCH v4] riscv: Allow user to set the satp mode To: Andrew Jones Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 13:56:38 -0000 Hey Andrew, Sorry about the response delay, I was traveling. On Fri, Jan 6, 2023 at 4:30 PM Andrew Jones wrote: > > On Mon, Dec 12, 2022 at 11:22:50AM +0100, Alexandre Ghiti wrote: > > RISC-V specifies multiple sizes for addressable memory and Linux probes for > > the machine's support at startup via the satp CSR register (done in > > csr.c:validate_vm). > > > > As per the specification, sv64 must support sv57, which in turn must > > support sv48...etc. So we can restrict machine support by simply setting the > > "highest" supported mode and the bare mode is always supported. > > > > You can set the satp mode using the new properties "mbare", "sv32", > > "sv39", "sv48", "sv57" and "sv64" as follows: > > -cpu rv64,sv57=on # Linux will boot using sv57 scheme > > -cpu rv64,sv39=on # Linux will boot using sv39 scheme > > > > We take the highest level set by the user: > > -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme > > > > We make sure that invalid configurations are rejected: > > -cpu rv64,sv32=on # Can't enable 32-bit satp mode in 64-bit > > -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are > > # enabled > > > > We accept "redundant" configurations: > > -cpu rv64,sv48=on,sv57=off # sv39 must be supported if higher modes are > ^ from this #, it looks like a copy+paste > mistake Yes, something is not right here, thanks. > > > > In addition, we now correctly set the device-tree entry 'mmu-type' using > > those new properties. > > > > Co-Developed-by: Ludovic Henry > > Signed-off-by: Ludovic Henry > > Signed-off-by: Alexandre Ghiti > > --- > > v4: > > - Use custom boolean properties instead of OnOffAuto properties, based > > on ARMVQMap, as suggested by Andrew > > > > v3: > > - Free sv_name as pointed by Bin > > - Replace satp-mode with boolean properties as suggested by Andrew > > - Removed RB from Atish as the patch considerably changed > > > > v2: > > - Use error_setg + return as suggested by Alistair > > - Add RB from Atish > > - Fixed checkpatch issues missed in v1 > > - Replaced Ludovic email address with the rivos one > > > > hw/riscv/virt.c | 20 +++-- > > target/riscv/cpu.c | 217 +++++++++++++++++++++++++++++++++++++++++++-- > > target/riscv/cpu.h | 25 ++++++ > > target/riscv/csr.c | 13 ++- > > 4 files changed, 256 insertions(+), 19 deletions(-) > > > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > > index a5bc7353b4..9bb5ba7366 100644 > > --- a/hw/riscv/virt.c > > +++ b/hw/riscv/virt.c > > @@ -228,7 +228,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > > int cpu; > > uint32_t cpu_phandle; > > MachineState *mc = MACHINE(s); > > - char *name, *cpu_name, *core_name, *intc_name; > > + uint8_t satp_mode_max; > > + char *name, *cpu_name, *core_name, *intc_name, *sv_name; > > > > for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { > > cpu_phandle = (*phandle)++; > > @@ -236,14 +237,15 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > > cpu_name = g_strdup_printf("/cpus/cpu@%d", > > s->soc[socket].hartid_base + cpu); > > qemu_fdt_add_subnode(mc->fdt, cpu_name); > > - if (riscv_feature(&s->soc[socket].harts[cpu].env, > > - RISCV_FEATURE_MMU)) { > > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > > - (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); > > - } else { > > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > > - "riscv,none"); > > - } > > + > > + satp_mode_max = satp_mode_max_from_map( > > + s->soc[socket].harts[cpu].cfg.satp_mode.map, > > + is_32_bit); > > + sv_name = g_strdup_printf("riscv,%s", > > + satp_mode_str(satp_mode_max, is_32_bit)); > > + qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", sv_name); > > + g_free(sv_name); > > + > > name = riscv_isa_string(&s->soc[socket].harts[cpu]); > > qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); > > g_free(name); > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index d14e95c9dc..639231ce2e 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -27,6 +27,7 @@ > > #include "time_helper.h" > > #include "exec/exec-all.h" > > #include "qapi/error.h" > > +#include "qapi/visitor.h" > > #include "qemu/error-report.h" > > #include "hw/qdev-properties.h" > > #include "migration/vmstate.h" > > @@ -199,7 +200,7 @@ static const char * const riscv_intr_names[] = { > > "reserved" > > }; > > > > -static void register_cpu_props(DeviceState *dev); > > +static void register_cpu_props(Object *obj); > > Please do this dev -> obj change in a separate ("no functional change > intended") patch. Ok, I can do that. > > > > > const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) > > { > > @@ -237,7 +238,7 @@ static void riscv_any_cpu_init(Object *obj) > > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > > #endif > > set_priv_version(env, PRIV_VERSION_1_12_0); > > - register_cpu_props(DEVICE(obj)); > > + register_cpu_props(obj); > > } > > > > #if defined(TARGET_RISCV64) > > @@ -246,7 +247,7 @@ static void rv64_base_cpu_init(Object *obj) > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > /* We set this in the realise function */ > > set_misa(env, MXL_RV64, 0); > > - register_cpu_props(DEVICE(obj)); > > + register_cpu_props(obj); > > /* Set latest version of privileged specification */ > > set_priv_version(env, PRIV_VERSION_1_12_0); > > } > > @@ -279,7 +280,7 @@ static void rv128_base_cpu_init(Object *obj) > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > /* We set this in the realise function */ > > set_misa(env, MXL_RV128, 0); > > - register_cpu_props(DEVICE(obj)); > > + register_cpu_props(obj); > > /* Set latest version of privileged specification */ > > set_priv_version(env, PRIV_VERSION_1_12_0); > > } > > @@ -289,7 +290,7 @@ static void rv32_base_cpu_init(Object *obj) > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > /* We set this in the realise function */ > > set_misa(env, MXL_RV32, 0); > > - register_cpu_props(DEVICE(obj)); > > + register_cpu_props(obj); > > /* Set latest version of privileged specification */ > > set_priv_version(env, PRIV_VERSION_1_12_0); > > } > > @@ -342,7 +343,7 @@ static void riscv_host_cpu_init(Object *obj) > > #elif defined(TARGET_RISCV64) > > set_misa(env, MXL_RV64, 0); > > #endif > > - register_cpu_props(DEVICE(obj)); > > + register_cpu_props(obj); > > } > > #endif > > > > @@ -612,6 +613,71 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > > } > > } > > > > +#define OFFSET_SATP_MODE_64 16 > > It's not clear to me why we need this offset. Looking below it seems to be > for helping to distinguish rv64-only modes when sanity checking modes for > rv32, but can't we just do that with valid_vm_1_10_32/64[]? If we don't duplicate the bitmap for rv32 and rv64, it's hard to reject the following input -cpu rv64,sv32=on but using valid_vm_1_10_32/64 could do the trick indeed. > > > + > > +static uint8_t idx_satp_mode_from_str(const char *satp_mode_str) > > nit: I'd drop the 'idx_' prefix. This function does not return the 'real' satp_mode, but the index in the bitmap (which is offsetted for 64-bit), will remove if I can get rid of OFFSET_SATP_MODE_64. > > > +{ > > + if (!strncmp(satp_mode_str, "mbare", 5)) { > > + return VM_1_10_MBARE; > > + } > > Do we need a property for mbare? It should always be present, no? That's an interesting question actually: in this patch version, to only enable mbare mode, one should use "mbare=on". But that's weird actually, I think we should rather explicitly disable the mode n+1, ie: sv39=off # enable mbare only sv48=off # enable sv39 ...etc So you're right, mbare is always there, so I'll remove the property. > > > + > > + if (!strncmp(satp_mode_str, "sv32", 4)) { > > + return VM_1_10_SV32; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv39", 4)) { > > + return VM_1_10_SV39 + OFFSET_SATP_MODE_64; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv48", 4)) { > > + return VM_1_10_SV48 + OFFSET_SATP_MODE_64; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv57", 4)) { > > + return VM_1_10_SV57 + OFFSET_SATP_MODE_64; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv64", 4)) { > > + return VM_1_10_SV64 + OFFSET_SATP_MODE_64; > > + } > > + > > + /* Will never get there */ > > + return -1; > > g_assert_not_reached() Thanks > > > +} > > + > > +uint8_t satp_mode_max_from_map(uint32_t map, bool is_32_bit) > > We shouldn't need is_32_bit. > If we get rid of OFFSET_SATP_MODE_64, I agree. > > +{ > > + return is_32_bit ? > > + (31 - __builtin_clz(map & 0xFFFF)) : (31 - __builtin_clz(map >> 16)); > > __builtin_clz is undefined when its input is zero, so we should either > use the clz32() wrapper or handle zero ourselves. How about > > { > /* > * map is always valid when this is called. It's either zero or > * only valid mode bits are set. > */ > return map ? __builtin_clz(map) : 0; > } > I did not know, thanks > > +} > > + > > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > > This function is not used outside this file, so can be static. It is actually used in hw/riscv/virt.c > Since we pass is_32_bit in here, then I don't think we need > OFFSET_SATP_MODE_64 > > > +{ > > + if (is_32_bit) { > > + switch (satp_mode) { > > + case VM_1_10_SV32: > > + return "sv32"; > > + case VM_1_10_MBARE: > > + return "none"; > > + } > > + } else { > > + switch (satp_mode) { > > + case VM_1_10_SV64: > > + return "sv64"; > > + case VM_1_10_SV57: > > + return "sv57"; > > + case VM_1_10_SV48: > > + return "sv48"; > > + case VM_1_10_SV39: > > + return "sv39"; > > + case VM_1_10_MBARE: > > + return "none"; > > + } > > + } > > + > > + return NULL; > > g_assert_not_reached() Thanks > > > +} > > + > > static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > { > > CPUState *cs = CPU(dev); > > @@ -907,6 +973,30 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > } > > #endif > > > > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > > + > > + /* > > + * If unset by both the user and the cpu, we fallback to sv32 for 32-bit > > + * or sv57 for 64-bit when a MMU is present, and bare otherwise. > > + */ > > + if (cpu->cfg.satp_mode.map == 0) { > > + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > > + if (rv32) { > > + cpu->cfg.satp_mode.map |= (1 << idx_satp_mode_from_str("sv32")); > > + } else { > > + cpu->cfg.satp_mode.map |= (1 << idx_satp_mode_from_str("sv57")); > > + } > > + } else { > > + cpu->cfg.satp_mode.map |= (1 << idx_satp_mode_from_str("mbare")); > > If we can drop the mbare property then it's implied and we don't need to > add it to the map. Agreed > > > + } > > + } > > + > > + riscv_cpu_finalize_features(cpu, &local_err); > > + if (local_err != NULL) { > > + error_propagate(errp, local_err); > > + return; > > + } > > + > > riscv_cpu_register_gdb_regs_for_features(cs); > > > > qemu_init_vcpu(cs); > > @@ -915,6 +1005,115 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > mcc->parent_realize(dev, errp); > > } > > > > +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, > > + void *opaque, Error **errp) > > +{ > > + RISCVSATPMap *satp_map = opaque; > > + uint8_t idx_satp = idx_satp_mode_from_str(name); > > + bool value; > > + > > + value = (satp_map->map & (1 << idx_satp)); > > + > > + visit_type_bool(v, name, &value, errp); > > +} > > + > > +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, > > + void *opaque, Error **errp) > > +{ > > + RISCVSATPMap *satp_map = opaque; > > + uint8_t idx_satp = idx_satp_mode_from_str(name); > > + bool value; > > + > > + if (!visit_type_bool(v, name, &value, errp)) { > > + return; > > + } > > + > > + if (value) { > > + satp_map->map |= 1 << idx_satp; > > + } > > If the user does e.g. sv32=on,sv32=off, which is pointless but valid, > then unless we have an > > else { > satp_map->map &= ~(1 << idx_satp); > } > > we won't properly disable sv32. It's best to use deposit32. Ok thanks, I'll take a look at this function. > > > + > > + satp_map->init |= 1 << idx_satp; > > +} > > + > > +static void riscv_add_satp_mode_properties(Object *obj) > > +{ > > + RISCVCPU *cpu = RISCV_CPU(obj); > > + > > + object_property_add(obj, "mbare", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > +} > > + > > +#define error_append_or_setg(errp, str, ...) ({ \ > > + if (*errp) \ > > + error_append_hint(errp, str"\n", ##__VA_ARGS__);\ > > + else \ > > + error_setg(errp, str, ##__VA_ARGS__); \ > > + }) > > Missing {} on the if/else and the if should be if (errp && *errp), but > I'd rather not have this macro at all. Why not just do error_setg and > return on the first error? I realize the user will only get one error > per try, but why not, at least they won't get confused as to what to > fix each try. Ok, I'll do that then! > > > + > > +void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > > This is only called from one place in the same file, so it can be static. Ok > > > +{ > > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > > + > > + /* Get rid of 32-bit/64-bit incompatibility */ > > + if (rv32) { > > + if (cpu->cfg.satp_mode.map >= (1 << OFFSET_SATP_MODE_64)) > > Missing {} Ok > > > + error_append_or_setg(errp, "cannot enable 64-bit satp modes " > > + "(sv39/sv48/sv57/sv64) if cpu is in 32-bit " > > I'd drop the "(sv39/sv48/sv57/sv64)" rather than introduce another place to > maintain when the list changes. Ok > > > + "mode"); > > + } else { > > + if (cpu->cfg.satp_mode.map & (1 << VM_1_10_SV32)) > > + error_append_or_setg(errp, "cannot enable 32-bit satp mode (sv32) " > > + "if cpu is in 64-bit mode"); > > + } > > + > > + /* > > + * Then make sure the user did not ask for an invalid configuration as per > > + * the specification. > > + */ > > + if (rv32) { > > + if (cpu->cfg.satp_mode.map & (1 << VM_1_10_SV32)) { > > + if (!(cpu->cfg.satp_mode.map & (1 << VM_1_10_MBARE)) && > > + (cpu->cfg.satp_mode.init & (1 << VM_1_10_MBARE))) > > Missing {} Ok > > > + error_append_or_setg(errp, "cannot disable mbare satp mode if " > > + "sv32 is enabled"); > > } else if ((cpu->cfg.satp_mode.map & (1 << VM_1_10_MBARE)) && > !(cpu->cfg.satp_mode.init & (1 << VM_1_10_MBARE))) { > cpu->cfg.satp_mode.map |= (1 << VM_1_10_MBARE); > } I can remove this check as mbare is always present > > > + } > > + } else { > > + uint8_t satp_mode_max; > > + > > + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map, false); > > + > > + for (int i = satp_mode_max - 1; i >= 0; --i) { > > + if (!(cpu->cfg.satp_mode.map & (1 << (i + OFFSET_SATP_MODE_64))) && > > + (cpu->cfg.satp_mode.init & (1 << (i + OFFSET_SATP_MODE_64)))) > > Missing {} Ok > > > + error_append_or_setg(errp, "cannot disable %s satp mode if %s " > > + "is enabled", > > + satp_mode_str(i, false), > > + satp_mode_str(satp_mode_max, false)); > > Same else-if concept needed here. Since I'd think we'd want to populate > the map with all the implicit modes. The point of this function is to make sure the user did not ask for an invalid configuration, right? As for setting the bits of the implicit modes, I'll see if that's needed, I'm not opposed to it, just did not find the utility. > > > + } > > + } > > Additionally I'd think we want to try and work valid_vm_1_10_32/64[] > checks into this function in order to be sure that map is fully populated > with valid bits when we're done. Ok I'll try to come up with something. > > > +} > > + > > +void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > > +{ > > + Error *local_err = NULL; > > + > > + riscv_cpu_satp_mode_finalize(cpu, &local_err); > > + if (local_err != NULL) { > > + error_propagate(errp, local_err); > > + return; > > + } > > +} > > + > > #ifndef CONFIG_USER_ONLY > > static void riscv_cpu_set_irq(void *opaque, int irq, int level) > > { > > @@ -1070,13 +1269,16 @@ static Property riscv_cpu_extensions[] = { > > DEFINE_PROP_END_OF_LIST(), > > }; > > > > -static void register_cpu_props(DeviceState *dev) > > +static void register_cpu_props(Object *obj) > > { > > Property *prop; > > + DeviceState *dev = DEVICE(obj); > > > > for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > > qdev_property_add_static(dev, prop); > > } > > + > > + riscv_add_satp_mode_properties(obj); > > } > > > > static Property riscv_cpu_properties[] = { > > @@ -1094,6 +1296,7 @@ static Property riscv_cpu_properties[] = { > > > > DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), > > DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), > > + > > Stray change Thanks > > > DEFINE_PROP_END_OF_LIST(), > > }; > > > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index 3a9e25053f..1717b33321 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -27,6 +27,7 @@ > > #include "qom/object.h" > > #include "qemu/int128.h" > > #include "cpu_bits.h" > > +#include "qapi/qapi-types-common.h" > > > > #define TCG_GUEST_DEFAULT_MO 0 > > > > @@ -407,6 +408,22 @@ struct RISCVCPUClass { > > DeviceReset parent_reset; > > }; > > > > +/* > > + * map and init are divided into two 16bit bitmaps: the upper one is for rv64 > > + * and the lower one is for rv32, this is because the value for sv32 (ie. 1) > > + * may be reused later for another purpose for rv64 (see the specification which > > + * states that it is "reserved for standard use"). > > I understand this, but I'm not sure why we can't use the same bit1 for > rv32 to mean one thing and for rv64 another. We can have another define > for rv64 that is also 1 and valid_vm_1_10_64[] is the authority. Ok > > > + * > > + * In a 16bit bitmap in map, the most significant set bit is the maximum > > + * satp mode that is supported. > > + * > > + * Both 16bit bitmaps in init are used to make sure the user selected a correct > > + * combination as per the specification. > > + */ > > +typedef struct { > > + uint32_t map, init; > > +} RISCVSATPMap; > > + > > struct RISCVCPUConfig { > > bool ext_i; > > bool ext_e; > > @@ -480,6 +497,8 @@ struct RISCVCPUConfig { > > bool debug; > > > > bool short_isa_string; > > + > > + RISCVSATPMap satp_mode; > > }; > > > > typedef struct RISCVCPUConfig RISCVCPUConfig; > > @@ -789,4 +808,10 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); > > > > void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); > > > > +uint8_t satp_mode_max_from_map(uint32_t map, bool is_32_bit); > > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); > > + > > +void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp); > > satp_mode_str and riscv_cpu_satp_mode_finalize should be static > so they should be dropped from here. Yes riscv_cpu_satp_mode_finalize can be dropped > > > +void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); > > + > > #endif /* RISCV_CPU_H */ > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 5c9a7ee287..5c732653b2 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -1109,10 +1109,17 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, > > > > static int validate_vm(CPURISCVState *env, target_ulong vm) > > { > > - if (riscv_cpu_mxl(env) == MXL_RV32) { > > - return valid_vm_1_10_32[vm & 0xf]; > > + uint8_t satp_mode_max; > > + RISCVCPU *cpu = RISCV_CPU(env_cpu(env)); > > + bool is_32_bit = riscv_cpu_mxl(env) == MXL_RV32; > > + > > + vm &= 0xf; > > + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map, is_32_bit); > > + > > + if (is_32_bit) { > > + return valid_vm_1_10_32[vm] && (vm <= satp_mode_max); > > } else { > > - return valid_vm_1_10_64[vm & 0xf]; > > + return valid_vm_1_10_64[vm] && (vm <= satp_mode_max); > > } > > } > > > > -- > > 2.37.2 > > > > Thanks, > drew Lot to process but I'll be back soon with a v5. Thanks for the thorough review, Alex From MAILER-DAEMON Thu Jan 12 09:47:30 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFyra-0003i9-RJ for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 09:47:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFyrZ-0003hE-5Z for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 09:47:29 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFyrX-0004wG-KZ for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 09:47:28 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1673534846; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=W/fVAbhTSCKn36CoCFZfOgn98LrHMlA4vtdqO0hTv4M=; b=KJE9VJ8GuJ0oBRbntlzt+FoOg/+0AP1Ox9arFX63SuJXKGi8XARZFE1Yb3R1WmKcdm1kea cq1Ildcu42l3cvymGnuSs1pvROJ3DQm58VYxTehmKMwfw8SNJlD02vK2Z2yOwk+gzLhx04 xVsStos6LaTOsZua3BzOmUPwXBbJs78= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-636-hOM0BqJPP6eRye7pR-FeKg-1; Thu, 12 Jan 2023 09:47:21 -0500 X-MC-Unique: hOM0BqJPP6eRye7pR-FeKg-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 0629018E0920; Thu, 12 Jan 2023 14:47:21 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.78]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 6DAC12166B26; Thu, 12 Jan 2023 14:47:20 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 40C2A21E6A36; Thu, 12 Jan 2023 15:47:19 +0100 (CET) From: Markus Armbruster To: "Michael S. Tsirkin" Cc: Markus Armbruster , qemu-devel@nongnu.org, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, ben.widawsky@intel.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, jasowang@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, philmd@linaro.org, Bin Meng Subject: Re: [PATCH v3 1/1] include: Don't include qemu/osdep.h References: <20230112115005.1504812-1-armbru@redhat.com> <20230112115005.1504812-2-armbru@redhat.com> <20230112082537-mutt-send-email-mst@kernel.org> <20230112085520-mutt-send-email-mst@kernel.org> Date: Thu, 12 Jan 2023 15:47:19 +0100 In-Reply-To: <20230112085520-mutt-send-email-mst@kernel.org> (Michael S. Tsirkin's message of "Thu, 12 Jan 2023 08:56:03 -0500") Message-ID: <87zgan4xoo.fsf@pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.1 on 10.11.54.6 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 14:47:29 -0000 "Michael S. Tsirkin" writes: > On Thu, Jan 12, 2023 at 08:51:32AM -0500, Michael S. Tsirkin wrote: >> On Thu, Jan 12, 2023 at 12:50:05PM +0100, Markus Armbruster wrote: >> > docs/devel/style.rst mandates: >> >=20 >> > The "qemu/osdep.h" header contains preprocessor macros that affect >> > the behavior of core system headers like . It must be >> > the first include so that core system headers included by external >> > libraries get the preprocessor macros that QEMU depends on. >> >=20 >> > Do not include "qemu/osdep.h" from header files since the .c file >> > will have already included it. >> >=20 >> > A few violations have crept in. Fix them. >> >=20 >> > Signed-off-by: Markus Armbruster >> > Reviewed-by: Philippe Mathieu-Daud=C3=A9 >> > Reviewed-by: Bin Meng >> > Reviewed-by: Taylor Simpson >> > Reviewed-by: Alistair Francis >>=20 >> With my awesome grep skillz I found one more: >> $ grep -r --include=3D'*.h' qemu/osdep.h >> include/block/graph-lock.h:#include "qemu/osdep.h" Crept in after I prepared my v1. I neglected to re-check. > Also: > $ grep -r --include=3D'*.inc' qemu/osdep.h > ui/vnc-enc-zrle.c.inc:#include "qemu/osdep.h" > crypto/akcipher-nettle.c.inc:#include "qemu/osdep.h" > crypto/akcipher-gcrypt.c.inc:#include "qemu/osdep.h" > crypto/rsakey-nettle.c.inc:#include "qemu/osdep.h" > crypto/cipher-gnutls.c.inc:#include "qemu/osdep.h" > target/xtensa/core-dc233c/xtensa-modules.c.inc:#include "qemu/osdep.h" > target/xtensa/core-sample_controller/xtensa-modules.c.inc:#include "qemu/= osdep.h" > target/xtensa/core-de212/xtensa-modules.c.inc:#include "qemu/osdep.h" > target/xtensa/core-dc232b/xtensa-modules.c.inc:#include "qemu/osdep.h" > target/xtensa/core-fsf/xtensa-modules.c.inc:#include "qemu/osdep.h" > target/cris/translate_v10.c.inc:#include "qemu/osdep.h" Good point. Looks like I successfully supressed all memory of .inc. >> Looks like all C files must include qemu/osdep.h, no? I remember there are a few exceptions, but I don't remember which .c they are. Hmm... see commit 4bd802b209cff612d1a99674a91895b735be8630. >> How about >>=20 >> 1- add -include qemu/osdep.h on compile command line >> drop #include "qemu/osdep.h" from C files Then you need to encode the exceptions in the build system. Which might not be a bad thing. >> 2- drop double include guards, replace with a warning. >>=20 >> following patch implements part 2: >>=20 >>=20 >> qemu/osdep: don't include it from headers >>=20 >> doing so will lead to trouble eventually - instead of >> working around such cases make it more likely it will fail. >>=20 >> Signed-off-by: Michael S. Tsirkin >>=20 >> --- >>=20 >> diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h >> index 7d059ad526..e4a60f911c 100644 >> --- a/include/qemu/osdep.h >> +++ b/include/qemu/osdep.h >> @@ -24,7 +24,12 @@ >> * This work is licensed under the terms of the GNU GPL, version 2 or l= ater. >> * See the COPYING file in the top-level directory. >> */ >> -#ifndef QEMU_OSDEP_H >> +#ifdef QEMU_OSDEP_H >> +#warning "Never include qemu/osdep.h from a header!" >> +#endif >> + >> +static inline void qemu_osdep_never_include_from_header(void) {} >> + Why do you need the function, too? >> #define QEMU_OSDEP_H >>=20=20 >> #include "config-host.h" >> @@ -714,5 +719,3 @@ static inline int platform_does_not_support_system(c= onst char *command) >> #ifdef __cplusplus >> } >> #endif >> - >> -#endif From MAILER-DAEMON Thu Jan 12 09:53:03 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFywx-00075T-PY for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 09:53:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFywv-00073x-MZ for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 09:53:01 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFywu-0005jz-1D for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 09:53:01 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1673535179; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Orpw9Mzjk/P1UNMXU9A1/QjjTSyb08eqlI5WuROrZFA=; b=Hl5ASamqWjSmLC4zWtIb7CnVVhDD14fwVD2WVPkec2S2AzBB2SENWyCpFPVAp7XG+CKFq5 4jO/QfvdM1gCCVsgAu1HbsceScZqDVI2n6pIcNzvUp83L49SL/+MxGbRgkCY9AMIO3JgWF hiRWPr1ZU3kG62urgpZzb27r6XgEED4= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-189-ml0PJfCFNLS_57WecqpE6A-1; Thu, 12 Jan 2023 09:52:54 -0500 X-MC-Unique: ml0PJfCFNLS_57WecqpE6A-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.rdu2.redhat.com [10.11.54.8]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 1856C1C08980; Thu, 12 Jan 2023 14:52:53 +0000 (UTC) Received: from redhat.com (unknown [10.33.36.222]) by smtp.corp.redhat.com (Postfix) with ESMTPS id D1CBBC15BA0; Thu, 12 Jan 2023 14:52:50 +0000 (UTC) Date: Thu, 12 Jan 2023 14:52:48 +0000 From: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= To: "Michael S. Tsirkin" Cc: Markus Armbruster , qemu-devel@nongnu.org, imp@bsdimp.com, kevans@freebsd.org, ben.widawsky@intel.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, jasowang@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, philmd@linaro.org, Bin Meng Subject: Re: [PATCH v3 1/1] include: Don't include qemu/osdep.h Message-ID: Reply-To: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= References: <20230112115005.1504812-1-armbru@redhat.com> <20230112115005.1504812-2-armbru@redhat.com> <20230112082537-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20230112082537-mutt-send-email-mst@kernel.org> User-Agent: Mutt/2.2.9 (2022-11-12) X-Scanned-By: MIMEDefang 3.1 on 10.11.54.8 Received-SPF: pass client-ip=170.10.129.124; envelope-from=berrange@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 14:53:01 -0000 On Thu, Jan 12, 2023 at 08:51:26AM -0500, Michael S. Tsirkin wrote: > On Thu, Jan 12, 2023 at 12:50:05PM +0100, Markus Armbruster wrote: > > docs/devel/style.rst mandates: > > > > The "qemu/osdep.h" header contains preprocessor macros that affect > > the behavior of core system headers like . It must be > > the first include so that core system headers included by external > > libraries get the preprocessor macros that QEMU depends on. > > > > Do not include "qemu/osdep.h" from header files since the .c file > > will have already included it. > > > > A few violations have crept in. Fix them. > > > > Signed-off-by: Markus Armbruster > > Reviewed-by: Philippe Mathieu-Daudé > > Reviewed-by: Bin Meng > > Reviewed-by: Taylor Simpson > > Reviewed-by: Alistair Francis > > With my awesome grep skillz I found one more: > $ grep -r --include='*.h' qemu/osdep.h > include/block/graph-lock.h:#include "qemu/osdep.h" > > Looks like all C files must include qemu/osdep.h, no? Yes, and IMHO that is/was a mistake, as it means our other header files are not self-contained, which prevents developer tools from reporting useful bugs when you're editting. For example, if you have clangd integrated into your editor, it will warn you as you're editting if you've referenced a function / type that doesn't exist in the file, or anything it includes. This is made completely useless for QEMU .h files though, as they're all incomplete, only the .c files have the full headers. With regards, Daniel -- |: https://berrange.com -o- https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o- https://fstop138.berrange.com :| |: https://entangle-photo.org -o- https://www.instagram.com/dberrange :| From MAILER-DAEMON Thu Jan 12 10:59:13 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pFzyy-000565-RI for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 10:59:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pFzyx-00055R-3z for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 10:59:11 -0500 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pFzyv-0001zj-AV for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 10:59:10 -0500 Received: by mail-pj1-x102f.google.com with SMTP id o1-20020a17090a678100b00219cf69e5f0so24045914pjj.2 for ; Thu, 12 Jan 2023 07:59:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=9XsNXvHrKB5fBnHaG9Xw20MMzOK6GmCYiu04FFFlrXM=; b=JCAt5+dEu4bOnmKtN6iZTFsXB5AWmOxrkmDHehhwBx213pZvJvhikFDJCARMTbg/qW 4Xlr31rH/kyTUGqc7daISnLiT2EK7qhb4qIk3JEsHgn/rBuAk1wUGjtCSFPOWsfalwWm Mla4B7Qgs0gMkllOmdLloWzARD7xy1DKV6z2jVXjtFgXB1UF6TOOeRkujI4T7uE4FkG/ G4iFWF8TsaFoBaZeGziCSjYUs2yC1mouyTMHHIDerQlRHaQzXLq6gNDLzIyIZ+IaLAor dzhqftZZVPHgPlwis7E4Rd+9hW9RYwt6EXJ/eh/wZCRi5QXsArFqHCIU8nNwyZvafi/2 ImFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9XsNXvHrKB5fBnHaG9Xw20MMzOK6GmCYiu04FFFlrXM=; b=RybfuCJFcPpU/YYUFfxLOxfrc8AwAIoqP/XW1KYlbV8aw+J6WwpITrAtwW5i04obTP Hni+YCf/HgCO3Tee9pNFGXdqlzdN7WZMXGRFRUcERQXHJcb84yZdw72GQU1+ALwkXOTK CaQY2EFqKtiTTT6yeT05CLnUMSiWq7hj5frLbZ5ZJyKsNZ+apySxsE3px535bB5T7QW7 n7bkOEn7M610yeHDz4/3GTKu7BS8VEuiI0bVbjWBmo3opDyM5rqSHtJcX0MfWHXf32F8 BxfXi7WRSbDGNM9NzCGU3syyEhSHQx35AQEdixWRe24eCZMOPQapgKRtT93S0TssP6XB RGWQ== X-Gm-Message-State: AFqh2kqf4Rw4DuldSlVlgvdafSizG+lAIFoj9VI1OAp+IemBG5mdrf1Y cYdc5QgOpMRnCzXiyNWATh1TTo5F7w1f1w1+Nm6fpA== X-Google-Smtp-Source: AMrXdXtv/z2TJBieQyDVhoLiAmMq4k41KKq4Gc5DT9erQY1R41afYQlcB6cPDRkUbaN+xX73PQUytqFRUY/H7x64058= X-Received: by 2002:a17:90a:77c7:b0:219:e2f1:81ad with SMTP id e7-20020a17090a77c700b00219e2f181admr6296004pjs.19.1673539147791; Thu, 12 Jan 2023 07:59:07 -0800 (PST) MIME-Version: 1.0 References: <20230112115005.1504812-1-armbru@redhat.com> <20230112115005.1504812-2-armbru@redhat.com> <20230112082537-mutt-send-email-mst@kernel.org> In-Reply-To: From: Peter Maydell Date: Thu, 12 Jan 2023 15:58:56 +0000 Message-ID: Subject: Re: [PATCH v3 1/1] include: Don't include qemu/osdep.h To: =?UTF-8?Q?Daniel_P=2E_Berrang=C3=A9?= Cc: "Michael S. Tsirkin" , Markus Armbruster , qemu-devel@nongnu.org, imp@bsdimp.com, kevans@freebsd.org, ben.widawsky@intel.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, jasowang@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, philmd@linaro.org, Bin Meng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=peter.maydell@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 15:59:11 -0000 On Thu, 12 Jan 2023 at 15:14, Daniel P. Berrang=C3=A9 = wrote: > > On Thu, Jan 12, 2023 at 08:51:26AM -0500, Michael S. Tsirkin wrote: > > On Thu, Jan 12, 2023 at 12:50:05PM +0100, Markus Armbruster wrote: > > > docs/devel/style.rst mandates: > > > > > > The "qemu/osdep.h" header contains preprocessor macros that affec= t > > > the behavior of core system headers like . It must be > > > the first include so that core system headers included by externa= l > > > libraries get the preprocessor macros that QEMU depends on. > > > > > > Do not include "qemu/osdep.h" from header files since the .c file > > > will have already included it. > > > > > > A few violations have crept in. Fix them. > > > > > > Signed-off-by: Markus Armbruster > > > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > > > Reviewed-by: Bin Meng > > > Reviewed-by: Taylor Simpson > > > Reviewed-by: Alistair Francis > > > > With my awesome grep skillz I found one more: > > $ grep -r --include=3D'*.h' qemu/osdep.h > > include/block/graph-lock.h:#include "qemu/osdep.h" > > > > Looks like all C files must include qemu/osdep.h, no? > > Yes, and IMHO that is/was a mistake, as it means our other header > files are not self-contained, which prevents developer tools from > reporting useful bugs when you're editting. The underlying requirement is "osdep.h must be included before any system header file". "Always first in every .c file" is an easy way to achieve that, and "never in any .h file" is then not mandatory but falls out from the fact that any such include is pointless and only serves to increase the compilation time (and to increase the chances that you don't notice that you forgot osdep.h in your .c file). If there's a better way to do this (e.g. one which meant that it was a compile error to put osdep includes in the wrong place or to omit them) then that would certainly save us periodically having to do this kind of fixup commit. thanks -- PMM From MAILER-DAEMON Thu Jan 12 11:08:12 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pG07g-0002MA-Jb for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 11:08:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG07d-0002Lp-S1 for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 11:08:10 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG07b-0003iI-W0 for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 11:08:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1673539686; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AFyTiLZgETk24M8fu35FVWHiD18haESTxvCD/MZcpcg=; b=EL97xM5EH0sBa5i6QHCt2iNHE82/welX8v9EzVy5LcbqWxE97dRcPFXQ5enfpl6Lwbu4/4 +nOHTW34Wg7YgXDZDD+i/PtRDer89fTgfgsbclDWrAQA6Zu4XKP8LOnI9AGCcsrCUGcUqM M/3rymZY9W9dyT2PC3ZYWNlDRVOkbV0= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-577-j-u1WPkPPM-8YizwqmsXqw-1; Thu, 12 Jan 2023 11:08:03 -0500 X-MC-Unique: j-u1WPkPPM-8YizwqmsXqw-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 08F281818E48; Thu, 12 Jan 2023 16:08:01 +0000 (UTC) Received: from redhat.com (unknown [10.33.36.222]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 6615C2166B29; Thu, 12 Jan 2023 16:07:58 +0000 (UTC) Date: Thu, 12 Jan 2023 16:07:56 +0000 From: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= To: Peter Maydell Cc: "Michael S. Tsirkin" , Markus Armbruster , qemu-devel@nongnu.org, imp@bsdimp.com, kevans@freebsd.org, ben.widawsky@intel.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, jasowang@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, philmd@linaro.org, Bin Meng Subject: Re: [PATCH v3 1/1] include: Don't include qemu/osdep.h Message-ID: Reply-To: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= References: <20230112115005.1504812-1-armbru@redhat.com> <20230112115005.1504812-2-armbru@redhat.com> <20230112082537-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/2.2.9 (2022-11-12) X-Scanned-By: MIMEDefang 3.1 on 10.11.54.6 Received-SPF: pass client-ip=170.10.129.124; envelope-from=berrange@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 16:08:10 -0000 On Thu, Jan 12, 2023 at 03:58:56PM +0000, Peter Maydell wrote: > On Thu, 12 Jan 2023 at 15:14, Daniel P. Berrangé wrote: > > > > On Thu, Jan 12, 2023 at 08:51:26AM -0500, Michael S. Tsirkin wrote: > > > On Thu, Jan 12, 2023 at 12:50:05PM +0100, Markus Armbruster wrote: > > > > docs/devel/style.rst mandates: > > > > > > > > The "qemu/osdep.h" header contains preprocessor macros that affect > > > > the behavior of core system headers like . It must be > > > > the first include so that core system headers included by external > > > > libraries get the preprocessor macros that QEMU depends on. > > > > > > > > Do not include "qemu/osdep.h" from header files since the .c file > > > > will have already included it. > > > > > > > > A few violations have crept in. Fix them. > > > > > > > > Signed-off-by: Markus Armbruster > > > > Reviewed-by: Philippe Mathieu-Daudé > > > > Reviewed-by: Bin Meng > > > > Reviewed-by: Taylor Simpson > > > > Reviewed-by: Alistair Francis > > > > > > With my awesome grep skillz I found one more: > > > $ grep -r --include='*.h' qemu/osdep.h > > > include/block/graph-lock.h:#include "qemu/osdep.h" > > > > > > Looks like all C files must include qemu/osdep.h, no? > > > > Yes, and IMHO that is/was a mistake, as it means our other header > > files are not self-contained, which prevents developer tools from > > reporting useful bugs when you're editting. > > The underlying requirement is "osdep.h must be included > before any system header file". "Always first in every .c file" > is an easy way to achieve that, and "never in any .h file" is > then not mandatory but falls out from the fact that any > such include is pointless and only serves to increase > the compilation time (and to increase the chances that > you don't notice that you forgot osdep.h in your .c file). > > If there's a better way to do this (e.g. one which meant > that it was a compile error to put osdep includes in the > wrong place or to omit them) then that would certainly > save us periodically having to do this kind of fixup commit. I think the challenge is that osdep.h is too big as it exists today. The stuff the needs to come before system headers is actually little more than config-host.h and a few #defines most of which are specific to windows. If those critical #defines went into config-host.h, then we could have a rule 'config-host.h' must be included in all .c files as the first thing. All the header files could just reference the specific system headers they care about instead of making everything from osdep.h visible in their namespace. Still this would be quite a lot of work to adapt to at this point. With regards, Daniel -- |: https://berrange.com -o- https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o- https://fstop138.berrange.com :| |: https://entangle-photo.org -o- https://www.instagram.com/dberrange :| From MAILER-DAEMON Thu Jan 12 11:20:52 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pG0Jw-0004T2-Aq for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 11:20:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG0Ju-0004Sk-TC for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 11:20:50 -0500 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pG0Jt-0005fh-6f for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 11:20:50 -0500 Received: by mail-pj1-x102f.google.com with SMTP id s13-20020a17090a6e4d00b0022900843652so2562869pjm.1 for ; Thu, 12 Jan 2023 08:20:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=kMrjHmCg1A+wNht30Z+xf3kV0pLt6BvLnr7luCC1WM0=; b=rl2sQHKDLAVSQ8jPaxCedRR3mM3nhOD5ucNhJN5uZgRgOg63IxOAQqzWbIdFg5hW3L cqhXUEUOciKAz/F5ZlUUEtRMcsj6J99q30SmbXbgeLrNT85msn0lcMtp7yYyolzrGOPI tyb3CFFxflmsmGfEJoMOFTyL9Y7oKSclMwkPNPT9Ky5QopaFVcjuCDEbw9ThZIrnimqA 9hKOrdGpxb3tGdaFtLPEAlMCJI5Gd7d9QU0S5Y0O4MqZVkOJeKqoNgIdFGphRlSfWWb9 aHFmJxDWi7Fkf4TA1jSdaaVkw5uunHaIk6Zqffyhe7C9T1fP3Zm4Vp1W7/KXTQt+ZvS1 1MjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kMrjHmCg1A+wNht30Z+xf3kV0pLt6BvLnr7luCC1WM0=; b=GxBLbwfpxWYrnoiS9TEf754YmCpXoj5sqyLo3bw+ZvwQXkeBDhHcIPSGEPRqRxBpXr T9eWJJ2Zat1yYuKt/dxecse5ivarg62ldwkflakqA4qe+C2dkL2pUPu8y49zgrfBH90G eJOmPrbQQ9O3+xFNuS6lwA3A5yuB7G6y/KgAKI3slf3lvRJtcc8XgoVCAkCcfC5Hw+xx mOxNabZEPRjR+Z4TDji60YkUdT5+IjuDxaXxW5mEH/1a0kKS87fHRwI/UATsuG8lRaGJ PMWhyT2y5hLk0I7D0AAosrW6PHx+ojQQQmXFfpketXMYBtx/Y8tvalIqo1HmsjpiaLR5 uUDg== X-Gm-Message-State: AFqh2krpEWZrLoGUAbRVzvNZB4dZtWuPsJoLeBonhd71AkxrcK+RCUXl JJmeSbITD9Ubn52QGoH/Q7z+F1Wcj7oDSMZwcydTpw== X-Google-Smtp-Source: AMrXdXvdlVP/tfer2Id1Kqud5iB98fK3P+6OrG6Vwvl57a3z4O5W5xYze83qh1VandXCSLvFsOfVeLu25FxTm5UMjxo= X-Received: by 2002:a17:902:690a:b0:193:1f3a:4977 with SMTP id j10-20020a170902690a00b001931f3a4977mr1628896plk.168.1673540447533; Thu, 12 Jan 2023 08:20:47 -0800 (PST) MIME-Version: 1.0 References: <20230112115005.1504812-1-armbru@redhat.com> <20230112115005.1504812-2-armbru@redhat.com> <20230112082537-mutt-send-email-mst@kernel.org> In-Reply-To: From: Peter Maydell Date: Thu, 12 Jan 2023 16:20:36 +0000 Message-ID: Subject: Re: [PATCH v3 1/1] include: Don't include qemu/osdep.h To: =?UTF-8?Q?Daniel_P=2E_Berrang=C3=A9?= Cc: "Michael S. Tsirkin" , Markus Armbruster , qemu-devel@nongnu.org, imp@bsdimp.com, kevans@freebsd.org, ben.widawsky@intel.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, jasowang@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, philmd@linaro.org, Bin Meng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=peter.maydell@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 16:20:51 -0000 On Thu, 12 Jan 2023 at 16:08, Daniel P. Berrang=C3=A9 = wrote: > I think the challenge is that osdep.h is too big as it exists > today. The stuff the needs to come before system headers is > actually little more than config-host.h and a few #defines > most of which are specific to windows. If those critical > #defines went into config-host.h, then we could have a rule > 'config-host.h' must be included in all .c files as the first > thing. This doesn't seem much different to the rules we have today, except you've renamed osdep.h to config-host.h... > All the header files could just reference the specific > system headers they care about instead of making everything > from osdep.h visible in their namespace. Still this would be > quite a lot of work to adapt to at this point. It certainly does have more in it than strictly necessary, though we have thinned it out quite a bit from when we first put in the convention. A lot of the functions at the tail end of the file could be moved out into their own headers, for instance -- patches welcome ;-) > All the header files could just reference the specific > system headers they care about instead of making everything > from osdep.h visible in their namespace. There are some complicated things in there, not always limited to Windows. Also where there is some header that needs a platform-specific workaround I prefer that that header is pulled in by osdep.h. This avoids the failure mode of "developer working on Linux directly includes some-system-header.h; works fine on their machine, but doesn't work on oddball-platform where the header needs a workaround". (For instance, handling "sys/mman.h on this system doesn't define MAP_ANONYMOUS", or the backcompat stuff in glib-compat.h.) thanks -- PMM From MAILER-DAEMON Thu Jan 12 11:30:37 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pG0TN-0007jR-IR for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 11:30:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG0TM-0007jA-7x for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 11:30:36 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG0TK-00078v-6f for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 11:30:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1673541033; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6ItsCWe1UDiIbTyHhNfrT6iDzjS+UiQ4kz4DGSVQ3d8=; b=ZCw59cesAm6FsvXpEnRP1SLdFYsfOu75i6IxmbcTP/hXpE4XOW52M+uyiTyoqL879F0KWr 1wr2it7x52tUSubi5Rwcupq9b5t0BX8NEUjbmTQG30dssTfiaox8BdToM2zs/UtVNedARc 4LlK5/A6ByDb8oYEE2ZbhBmfOLc4OuE= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-650-93pzmnrXNkSZdZTIGhgU4A-1; Thu, 12 Jan 2023 11:30:31 -0500 X-MC-Unique: 93pzmnrXNkSZdZTIGhgU4A-1 Received: from smtp.corp.redhat.com (int-mx09.intmail.prod.int.rdu2.redhat.com [10.11.54.9]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 24E5C811E6E; Thu, 12 Jan 2023 16:30:31 +0000 (UTC) Received: from redhat.com (unknown [10.33.36.222]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 48EE6492C14; Thu, 12 Jan 2023 16:30:28 +0000 (UTC) Date: Thu, 12 Jan 2023 16:30:20 +0000 From: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= To: Peter Maydell Cc: "Michael S. Tsirkin" , Markus Armbruster , qemu-devel@nongnu.org, imp@bsdimp.com, kevans@freebsd.org, ben.widawsky@intel.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, jasowang@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, philmd@linaro.org, Bin Meng Subject: Re: [PATCH v3 1/1] include: Don't include qemu/osdep.h Message-ID: Reply-To: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= References: <20230112115005.1504812-1-armbru@redhat.com> <20230112115005.1504812-2-armbru@redhat.com> <20230112082537-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/2.2.9 (2022-11-12) X-Scanned-By: MIMEDefang 3.1 on 10.11.54.9 Received-SPF: pass client-ip=170.10.133.124; envelope-from=berrange@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 16:30:36 -0000 On Thu, Jan 12, 2023 at 04:20:36PM +0000, Peter Maydell wrote: > On Thu, 12 Jan 2023 at 16:08, Daniel P. Berrangé wrote: > > I think the challenge is that osdep.h is too big as it exists > > today. The stuff the needs to come before system headers is > > actually little more than config-host.h and a few #defines > > most of which are specific to windows. If those critical > > #defines went into config-host.h, then we could have a rule > > 'config-host.h' must be included in all .c files as the first > > thing. > > This doesn't seem much different to the rules we have today, > except you've renamed osdep.h to config-host.h... If the QEMU header files all contain #includes for the system headers they rely on, then when tools are validating code in the header, they can stand a better chance of being able to resolve all the types. Though it'll still fail if some of the system header pieces only get exposed as a result of config-host.h macros, but that's relatively few, compared to today where amost nothing resolves if yuo validate the headers files in isolation. > > All the header files could just reference the specific > > system headers they care about instead of making everything > > from osdep.h visible in their namespace. > > There are some complicated things in there, not always > limited to Windows. Also where there is some header > that needs a platform-specific workaround I prefer that > that header is pulled in by osdep.h. This avoids the > failure mode of "developer working on Linux directly > includes some-system-header.h; works fine on their machine, > but doesn't work on oddball-platform where the header > needs a workaround". (For instance, handling "sys/mman.h > on this system doesn't define MAP_ANONYMOUS", or the > backcompat stuff in glib-compat.h.) Yeah, its not entirely straightforward, though our CI will catch that on our most important target platforms. With regards, Daniel -- |: https://berrange.com -o- https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o- https://fstop138.berrange.com :| |: https://entangle-photo.org -o- https://www.instagram.com/dberrange :| From MAILER-DAEMON Thu Jan 12 11:38:37 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pG0b5-0002z2-Ph for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 11:38:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG0b3-0002yl-JQ for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 11:38:33 -0500 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pG0b1-0008HP-JJ for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 11:38:33 -0500 Received: by mail-pf1-x434.google.com with SMTP id x4so10055446pfj.1 for ; Thu, 12 Jan 2023 08:38:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=/EGkQVNtaoQAMvDYuqtGmbHuLfJzMrrI3jFxmiv6ma8=; b=fgTdwLU8V54u7Oc1oIcH+DsG5YZSfXWsm1fbnJDjWJ/g3OoArdXyptgi9Hs0VS5Ht3 N4/kW4NCJ5O6F3aoW2vpkf/hEuTYoHebeC64zvPzU/YY3MK6eUaHhkmafsD91lUEijT8 ok9kpMIt7ZyY5mri2f28yeVE0HKnOB5X0sWUzgFzE7cy40H2hDWyCmcgRez9gpKmqAe2 gogZtJtlKQzhTvpsKlFd3zdufklSO90+m+tV1hi5htJNQ2D6V/O+4bKDk03J/usaS/j5 4knVMfVoTOMNrg0HpPosMXbfZlloblpOymu2nkBbcuj18lAnDZgM3Gd7Ci+cJZNoODZz Ft0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/EGkQVNtaoQAMvDYuqtGmbHuLfJzMrrI3jFxmiv6ma8=; b=hSNRhNeSmdzaN5HrFhKJfbzZk3g4MBSe4oPrQoOh1qD7EmVEYF709MyhAaIY4OONcv uEyQ65l8UgVKbq6qUlerUr6tF+ZJ6lm1PJpGzc4zhhV3mc3nzlkHG1ZA2uGPiDW7RWLW Ju7vx7bW734x+TyCorjVQukPzF1MzeTcQoh7QauOGS0j/Ze/0AwWUePNQ9P4rHqK1k7s X0L1FWsj6tPVe3MX5EpNMeWFSeR04JXG1yNKul6Dh3735Ni5HPA5BBNgu1rfotl4flWH umlwAGXeApU5PoTptCeqCZbLM3q3bLYlSmre8NuA7vrQjwozNRveOc2sdL0CaE5rY8/k DvDA== X-Gm-Message-State: AFqh2kr850r/6/Tm7fFp4hXppfVwwxqvcVspd76UsGcE/mbblsmE2/8L gpVgi6BOdwezFBSbQHpgn1qIN8oo6viokilkB7pNjg== X-Google-Smtp-Source: AMrXdXuuxq2fNigpEKi8gb0ubH8uILQj605ArM46se1dHWc8JKUsHhSBsoBcrlQg44JDJsd1n7eca/SnonAZKVV2naw= X-Received: by 2002:a63:e20b:0:b0:479:18a:8359 with SMTP id q11-20020a63e20b000000b00479018a8359mr5040754pgh.105.1673541509513; Thu, 12 Jan 2023 08:38:29 -0800 (PST) MIME-Version: 1.0 References: <20230112115005.1504812-1-armbru@redhat.com> <20230112115005.1504812-2-armbru@redhat.com> <20230112082537-mutt-send-email-mst@kernel.org> In-Reply-To: From: Peter Maydell Date: Thu, 12 Jan 2023 16:38:18 +0000 Message-ID: Subject: Re: [PATCH v3 1/1] include: Don't include qemu/osdep.h To: =?UTF-8?Q?Daniel_P=2E_Berrang=C3=A9?= Cc: "Michael S. Tsirkin" , Markus Armbruster , qemu-devel@nongnu.org, imp@bsdimp.com, kevans@freebsd.org, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, jasowang@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, philmd@linaro.org, Bin Meng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 16:38:33 -0000 On Thu, 12 Jan 2023 at 16:30, Daniel P. Berrang=C3=A9 = wrote: > > On Thu, Jan 12, 2023 at 04:20:36PM +0000, Peter Maydell wrote: > > On Thu, 12 Jan 2023 at 16:08, Daniel P. Berrang=C3=A9 wrote: > > > I think the challenge is that osdep.h is too big as it exists > > > today. The stuff the needs to come before system headers is > > > actually little more than config-host.h and a few #defines > > > most of which are specific to windows. If those critical > > > #defines went into config-host.h, then we could have a rule > > > 'config-host.h' must be included in all .c files as the first > > > thing. > > > > This doesn't seem much different to the rules we have today, > > except you've renamed osdep.h to config-host.h... > > If the QEMU header files all contain #includes for the > system headers they rely on, then when tools are validating > code in the header, they can stand a better chance of being > able to resolve all the types. Though it'll still fail if > some of the system header pieces only get exposed as a result > of config-host.h macros, but that's relatively few, compared > to today where amost nothing resolves if yuo validate the > headers files in isolation. Yeah, but I don't want QEMU header files to contain lots of includes for system header files, because of... > > There are some complicated things in there, not always > > limited to Windows. Also where there is some header > > that needs a platform-specific workaround I prefer that > > that header is pulled in by osdep.h. This avoids the > > failure mode of "developer working on Linux directly > > includes some-system-header.h; works fine on their machine, > > but doesn't work on oddball-platform where the header > > needs a workaround". (For instance, handling "sys/mman.h > > on this system doesn't define MAP_ANONYMOUS", or the > > backcompat stuff in glib-compat.h.) ...this. So we'd have to have config-host.h include all the system headers we're working around anyway. -- PMM From MAILER-DAEMON Thu Jan 12 12:31:09 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pG1Px-0002KC-OE for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 12:31:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG1Pt-0002GN-SQ; Thu, 12 Jan 2023 12:31:07 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG1Pn-0000uL-UU; Thu, 12 Jan 2023 12:31:01 -0500 Received: from lhrpeml500005.china.huawei.com (unknown [172.18.147.200]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4NtBQv41ZDz6J9h8; Fri, 13 Jan 2023 01:30:47 +0800 (CST) Received: from localhost (10.202.227.76) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 12 Jan 2023 17:30:53 +0000 Date: Thu, 12 Jan 2023 17:30:52 +0000 From: Jonathan Cameron To: Markus Armbruster CC: , , , , , , , , , , , , , , , , Bin Meng Subject: Re: [PATCH v3 1/1] include: Don't include qemu/osdep.h Message-ID: <20230112173052.00006303@Huawei.com> In-Reply-To: <20230112115005.1504812-2-armbru@redhat.com> References: <20230112115005.1504812-1-armbru@redhat.com> <20230112115005.1504812-2-armbru@redhat.com> Organization: Huawei Technologies Research and Development (UK) Ltd. X-Mailer: Claws Mail 4.1.0 (GTK 3.24.33; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset="ISO-8859-1" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.202.227.76] X-ClientProxiedBy: lhrpeml500004.china.huawei.com (7.191.163.9) To lhrpeml500005.china.huawei.com (7.191.163.240) X-CFilter-Loop: Reflected Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 17:31:08 -0000 On Thu, 12 Jan 2023 12:50:05 +0100 Markus Armbruster wrote: > docs/devel/style.rst mandates: >=20 > The "qemu/osdep.h" header contains preprocessor macros that affect > the behavior of core system headers like . It must be > the first include so that core system headers included by external > libraries get the preprocessor macros that QEMU depends on. >=20 > Do not include "qemu/osdep.h" from header files since the .c file > will have already included it. >=20 > A few violations have crept in. Fix them. >=20 > Signed-off-by: Markus Armbruster > Reviewed-by: Philippe Mathieu-Daud=E9 > Reviewed-by: Bin Meng > Reviewed-by: Taylor Simpson > Reviewed-by: Alistair Francis For the CXL one. Acked-by: Jonathan Cameron > --- > bsd-user/qemu.h | 1 - > crypto/block-luks-priv.h | 1 - > include/hw/cxl/cxl_host.h | 1 - > include/hw/input/pl050.h | 1 - > include/hw/tricore/triboard.h | 1 - > include/qemu/userfaultfd.h | 1 - > net/vmnet_int.h | 1 - > qga/cutils.h | 1 - > target/hexagon/hex_arch_types.h | 1 - > target/hexagon/mmvec/macros.h | 1 - > target/riscv/pmu.h | 1 - > bsd-user/arm/signal.c | 1 + > bsd-user/arm/target_arch_cpu.c | 2 ++ > bsd-user/freebsd/os-sys.c | 1 + > bsd-user/i386/signal.c | 1 + > bsd-user/x86_64/signal.c | 1 + > qga/cutils.c | 3 ++- > 17 files changed, 8 insertions(+), 12 deletions(-) >=20 > diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h > index be6105385e..0ceecfb6df 100644 > --- a/bsd-user/qemu.h > +++ b/bsd-user/qemu.h > @@ -17,7 +17,6 @@ > #ifndef QEMU_H > #define QEMU_H > =20 > -#include "qemu/osdep.h" > #include "cpu.h" > #include "qemu/units.h" > #include "exec/cpu_ldst.h" > diff --git a/crypto/block-luks-priv.h b/crypto/block-luks-priv.h > index 90a20d432b..1066df0307 100644 > --- a/crypto/block-luks-priv.h > +++ b/crypto/block-luks-priv.h > @@ -18,7 +18,6 @@ > * > */ > =20 > -#include "qemu/osdep.h" > #include "qapi/error.h" > #include "qemu/bswap.h" > =20 > diff --git a/include/hw/cxl/cxl_host.h b/include/hw/cxl/cxl_host.h > index a1b662ce40..c9bc9c7c50 100644 > --- a/include/hw/cxl/cxl_host.h > +++ b/include/hw/cxl/cxl_host.h > @@ -7,7 +7,6 @@ > * COPYING file in the top-level directory. > */ > =20 > -#include "qemu/osdep.h" > #include "hw/cxl/cxl.h" > #include "hw/boards.h" > =20 > diff --git a/include/hw/input/pl050.h b/include/hw/input/pl050.h > index 89ec4fafc9..4cb8985f31 100644 > --- a/include/hw/input/pl050.h > +++ b/include/hw/input/pl050.h > @@ -10,7 +10,6 @@ > #ifndef HW_PL050_H > #define HW_PL050_H > =20 > -#include "qemu/osdep.h" > #include "hw/sysbus.h" > #include "migration/vmstate.h" > #include "hw/input/ps2.h" > diff --git a/include/hw/tricore/triboard.h b/include/hw/tricore/triboard.h > index 094c8bd563..4fdd2d7d97 100644 > --- a/include/hw/tricore/triboard.h > +++ b/include/hw/tricore/triboard.h > @@ -18,7 +18,6 @@ > * License along with this library; if not, see . > */ > =20 > -#include "qemu/osdep.h" > #include "qapi/error.h" > #include "hw/boards.h" > #include "sysemu/sysemu.h" > diff --git a/include/qemu/userfaultfd.h b/include/qemu/userfaultfd.h > index 6b74f92792..55c95998e8 100644 > --- a/include/qemu/userfaultfd.h > +++ b/include/qemu/userfaultfd.h > @@ -13,7 +13,6 @@ > #ifndef USERFAULTFD_H > #define USERFAULTFD_H > =20 > -#include "qemu/osdep.h" > #include "exec/hwaddr.h" > #include > =20 > diff --git a/net/vmnet_int.h b/net/vmnet_int.h > index adf6e8c20d..d0b90594f2 100644 > --- a/net/vmnet_int.h > +++ b/net/vmnet_int.h > @@ -10,7 +10,6 @@ > #ifndef VMNET_INT_H > #define VMNET_INT_H > =20 > -#include "qemu/osdep.h" > #include "vmnet_int.h" > #include "clients.h" > =20 > diff --git a/qga/cutils.h b/qga/cutils.h > index f0f30a7d28..2bfaf554a8 100644 > --- a/qga/cutils.h > +++ b/qga/cutils.h > @@ -1,7 +1,6 @@ > #ifndef CUTILS_H_ > #define CUTILS_H_ > =20 > -#include "qemu/osdep.h" > =20 > int qga_open_cloexec(const char *name, int flags, mode_t mode); > =20 > diff --git a/target/hexagon/hex_arch_types.h b/target/hexagon/hex_arch_ty= pes.h > index 885f68f760..52a7f2b2f3 100644 > --- a/target/hexagon/hex_arch_types.h > +++ b/target/hexagon/hex_arch_types.h > @@ -18,7 +18,6 @@ > #ifndef HEXAGON_HEX_ARCH_TYPES_H > #define HEXAGON_HEX_ARCH_TYPES_H > =20 > -#include "qemu/osdep.h" > #include "mmvec/mmvec.h" > #include "qemu/int128.h" > =20 > diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h > index 8c864e8c68..1201d778d0 100644 > --- a/target/hexagon/mmvec/macros.h > +++ b/target/hexagon/mmvec/macros.h > @@ -18,7 +18,6 @@ > #ifndef HEXAGON_MMVEC_MACROS_H > #define HEXAGON_MMVEC_MACROS_H > =20 > -#include "qemu/osdep.h" > #include "qemu/host-utils.h" > #include "arch.h" > #include "mmvec/system_ext_mmvec.h" > diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h > index 3004ce37b6..0c819ca983 100644 > --- a/target/riscv/pmu.h > +++ b/target/riscv/pmu.h > @@ -16,7 +16,6 @@ > * this program. If not, see . > */ > =20 > -#include "qemu/osdep.h" > #include "qemu/log.h" > #include "cpu.h" > #include "qemu/main-loop.h" > diff --git a/bsd-user/arm/signal.c b/bsd-user/arm/signal.c > index 2b1dd745d1..9734407543 100644 > --- a/bsd-user/arm/signal.c > +++ b/bsd-user/arm/signal.c > @@ -17,6 +17,7 @@ > * along with this program; if not, see . > */ > =20 > +#include "qemu/osdep.h" > #include "qemu.h" > =20 > /* > diff --git a/bsd-user/arm/target_arch_cpu.c b/bsd-user/arm/target_arch_cp= u.c > index 02bf9149d5..fe38ae2210 100644 > --- a/bsd-user/arm/target_arch_cpu.c > +++ b/bsd-user/arm/target_arch_cpu.c > @@ -16,6 +16,8 @@ > * You should have received a copy of the GNU General Public License > * along with this program; if not, see . > */ > + > +#include "qemu/osdep.h" > #include "target_arch.h" > =20 > void target_cpu_set_tls(CPUARMState *env, target_ulong newtls) > diff --git a/bsd-user/freebsd/os-sys.c b/bsd-user/freebsd/os-sys.c > index 309e27b9d6..1676ec10f8 100644 > --- a/bsd-user/freebsd/os-sys.c > +++ b/bsd-user/freebsd/os-sys.c > @@ -17,6 +17,7 @@ > * along with this program; if not, see . > */ > =20 > +#include "qemu/osdep.h" > #include "qemu.h" > #include "target_arch_sysarch.h" > =20 > diff --git a/bsd-user/i386/signal.c b/bsd-user/i386/signal.c > index 5dd975ce56..a3131047b8 100644 > --- a/bsd-user/i386/signal.c > +++ b/bsd-user/i386/signal.c > @@ -17,6 +17,7 @@ > * along with this program; if not, see . > */ > =20 > +#include "qemu/osdep.h" > #include "qemu.h" > =20 > /* > diff --git a/bsd-user/x86_64/signal.c b/bsd-user/x86_64/signal.c > index c3875bc4c6..46cb865180 100644 > --- a/bsd-user/x86_64/signal.c > +++ b/bsd-user/x86_64/signal.c > @@ -16,6 +16,7 @@ > * along with this program; if not, see . > */ > =20 > +#include "qemu/osdep.h" > #include "qemu.h" > =20 > /* > diff --git a/qga/cutils.c b/qga/cutils.c > index b8e142ef64..b21bcf3683 100644 > --- a/qga/cutils.c > +++ b/qga/cutils.c > @@ -2,8 +2,9 @@ > * This work is licensed under the terms of the GNU GPL, version 2 or la= ter. > * See the COPYING file in the top-level directory. > */ > -#include "cutils.h" > =20 > +#include "qemu/osdep.h" > +#include "cutils.h" > #include "qapi/error.h" > =20 > /** From MAILER-DAEMON Thu Jan 12 12:38:25 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pG1Wz-0006zp-45 for mharc-qemu-riscv@gnu.org; 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Tsirkin" To: Markus Armbruster Cc: qemu-devel@nongnu.org, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, ben.widawsky@intel.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, jasowang@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, philmd@linaro.org, Bin Meng Subject: Re: [PATCH v3 1/1] include: Don't include qemu/osdep.h Message-ID: <20230112123434-mutt-send-email-mst@kernel.org> References: <20230112115005.1504812-1-armbru@redhat.com> <20230112115005.1504812-2-armbru@redhat.com> <20230112082537-mutt-send-email-mst@kernel.org> <20230112085520-mutt-send-email-mst@kernel.org> <87zgan4xoo.fsf@pond.sub.org> MIME-Version: 1.0 In-Reply-To: <87zgan4xoo.fsf@pond.sub.org> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 17:38:19 -0000 On Thu, Jan 12, 2023 at 03:47:19PM +0100, Markus Armbruster wrote: > "Michael S. Tsirkin" writes: > > > On Thu, Jan 12, 2023 at 08:51:32AM -0500, Michael S. Tsirkin wrote: > >> On Thu, Jan 12, 2023 at 12:50:05PM +0100, Markus Armbruster wrote: > >> > docs/devel/style.rst mandates: > >> > > >> > The "qemu/osdep.h" header contains preprocessor macros that affect > >> > the behavior of core system headers like . It must be > >> > the first include so that core system headers included by external > >> > libraries get the preprocessor macros that QEMU depends on. > >> > > >> > Do not include "qemu/osdep.h" from header files since the .c file > >> > will have already included it. > >> > > >> > A few violations have crept in. Fix them. > >> > > >> > Signed-off-by: Markus Armbruster > >> > Reviewed-by: Philippe Mathieu-Daudé > >> > Reviewed-by: Bin Meng > >> > Reviewed-by: Taylor Simpson > >> > Reviewed-by: Alistair Francis > >> > >> With my awesome grep skillz I found one more: > >> $ grep -r --include='*.h' qemu/osdep.h > >> include/block/graph-lock.h:#include "qemu/osdep.h" > > Crept in after I prepared my v1. I neglected to re-check. > > > Also: > > $ grep -r --include='*.inc' qemu/osdep.h > > ui/vnc-enc-zrle.c.inc:#include "qemu/osdep.h" > > crypto/akcipher-nettle.c.inc:#include "qemu/osdep.h" > > crypto/akcipher-gcrypt.c.inc:#include "qemu/osdep.h" > > crypto/rsakey-nettle.c.inc:#include "qemu/osdep.h" > > crypto/cipher-gnutls.c.inc:#include "qemu/osdep.h" > > target/xtensa/core-dc233c/xtensa-modules.c.inc:#include "qemu/osdep.h" > > target/xtensa/core-sample_controller/xtensa-modules.c.inc:#include "qemu/osdep.h" > > target/xtensa/core-de212/xtensa-modules.c.inc:#include "qemu/osdep.h" > > target/xtensa/core-dc232b/xtensa-modules.c.inc:#include "qemu/osdep.h" > > target/xtensa/core-fsf/xtensa-modules.c.inc:#include "qemu/osdep.h" > > target/cris/translate_v10.c.inc:#include "qemu/osdep.h" > > Good point. Looks like I successfully supressed all memory of .inc. > > >> Looks like all C files must include qemu/osdep.h, no? > > I remember there are a few exceptions, but I don't remember which .c > they are. Hmm... see commit 4bd802b209cff612d1a99674a91895b735be8630. > > >> How about > >> > >> 1- add -include qemu/osdep.h on compile command line > >> drop #include "qemu/osdep.h" from C files > > Then you need to encode the exceptions in the build system. Which might > not be a bad thing. > > >> 2- drop double include guards, replace with a warning. > >> > >> following patch implements part 2: > >> > >> > >> qemu/osdep: don't include it from headers > >> > >> doing so will lead to trouble eventually - instead of > >> working around such cases make it more likely it will fail. > >> > >> Signed-off-by: Michael S. Tsirkin > >> > >> --- > >> > >> diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h > >> index 7d059ad526..e4a60f911c 100644 > >> --- a/include/qemu/osdep.h > >> +++ b/include/qemu/osdep.h > >> @@ -24,7 +24,12 @@ > >> * This work is licensed under the terms of the GNU GPL, version 2 or later. > >> * See the COPYING file in the top-level directory. > >> */ > >> -#ifndef QEMU_OSDEP_H > >> +#ifdef QEMU_OSDEP_H > >> +#warning "Never include qemu/osdep.h from a header!" > >> +#endif > >> + > >> +static inline void qemu_osdep_never_include_from_header(void) {} > >> + > > Why do you need the function, too? This seems to give a bit more info if header does get included twice: instead of just a warning on the second include compiler says definition is duplicated and then shows where the first definition was. OTOH first one was almost for sure from the proper first include so maybe we don't care. Let me drop this. > >> #define QEMU_OSDEP_H > >> > >> #include "config-host.h" > >> @@ -714,5 +719,3 @@ static inline int platform_does_not_support_system(const char *command) > >> #ifdef __cplusplus > >> } > >> #endif > >> - > >> -#endif From MAILER-DAEMON Thu Jan 12 12:43:22 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pG1bl-0001XO-Qn for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 12:43:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG1bg-0001T7-AQ for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 12:43:20 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG1be-0002yN-W3 for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 12:43:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1673545394; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VRnRLfWYBmS7QFJ95fJ0/Y/8sdTtZKcRN8b0GCktwzg=; b=dzgoS4UdL/1B/G5owX+M+63j3NojTI6pYBgXAYC79YbGjJRpRNuuo9XaFc8r1bC4BCuCAs pXi0qNuKRKvGUMlNLa+ZK24F+SOnMrPA3eTDk4pBc07npZhkypGW/l00QMJcGr6QWNT2Jc O7MlWsRrnLS683NvteybPERJDKNSmSI= Received: from mail-wr1-f69.google.com (mail-wr1-f69.google.com [209.85.221.69]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-30-tqpvNsoIO4C9aL1E_vrh1g-1; Thu, 12 Jan 2023 12:41:35 -0500 X-MC-Unique: tqpvNsoIO4C9aL1E_vrh1g-1 Received: by mail-wr1-f69.google.com with SMTP id o5-20020adfba05000000b0029064ccbe46so3663743wrg.9 for ; Thu, 12 Jan 2023 09:41:35 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=VRnRLfWYBmS7QFJ95fJ0/Y/8sdTtZKcRN8b0GCktwzg=; b=3qIZbYiLDKl/qZXE3iKUUZX+AN33TFPftKjYvjWY+DBiXTB7P1UuFaGOeONYkOxtMA sjomjVp2hEwxE1T6vU9YVooIkTk1JaXHPVUWFbg4iDpcCl96BAcQCsyqJ/eTJ0pvmQes qmWG4g0fVJ6rvcsm3fSS7sJXDnBw2OfRQ7JQWrHi5k6X0tFTtBkB1nKgoF9a0PspcsnU xsQ420VbC+dToZz9RkQAXbENKUB9znvuq5qnzBz7rUDpE/Gm1XXecJ1PWcycrJ2AP/he EyJL47rrrHUC/0cgSEElQfZ8rai1V9KWSAZQpDDaGOwmrqg+rY/qdr/8su5Q0X9Ike+d oyeQ== X-Gm-Message-State: AFqh2krGVTyoIcBAs9ofdDEQOF9GNx+2cVle2IgdbSHuKhpBp+WP2CEN t7qfG2EdEiTDUZb1KnVIWr+DaQkzE9q+jcFNj4c/+yPsfq9HwaEV3eL+nR55puWpEeES20VXBFq HJJznxEaZRCEKSwY= X-Received: by 2002:a7b:ca4f:0:b0:3c6:edc0:5170 with SMTP id m15-20020a7bca4f000000b003c6edc05170mr55535586wml.25.1673545294728; Thu, 12 Jan 2023 09:41:34 -0800 (PST) X-Google-Smtp-Source: AMrXdXv2Nfl2zhadh45vjFKuA0ruFaFWL/u9Me8rBybNq4JDbL2Atvy21u073sGdrWEYpGLxX/RH+w== X-Received: by 2002:a7b:ca4f:0:b0:3c6:edc0:5170 with SMTP id m15-20020a7bca4f000000b003c6edc05170mr55535567wml.25.1673545294497; Thu, 12 Jan 2023 09:41:34 -0800 (PST) Received: from redhat.com ([2.52.157.155]) by smtp.gmail.com with ESMTPSA id e7-20020a056000120700b00241dd5de644sm17027607wrx.97.2023.01.12.09.41.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jan 2023 09:41:33 -0800 (PST) Date: Thu, 12 Jan 2023 12:41:29 -0500 From: "Michael S. Tsirkin" To: Markus Armbruster Cc: qemu-devel@nongnu.org, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, ben.widawsky@intel.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, jasowang@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, philmd@linaro.org, Bin Meng Subject: Re: [PATCH v3 1/1] include: Don't include qemu/osdep.h Message-ID: <20230112124011-mutt-send-email-mst@kernel.org> References: <20230112115005.1504812-1-armbru@redhat.com> <20230112115005.1504812-2-armbru@redhat.com> MIME-Version: 1.0 In-Reply-To: <20230112115005.1504812-2-armbru@redhat.com> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 17:43:20 -0000 On Thu, Jan 12, 2023 at 12:50:05PM +0100, Markus Armbruster wrote: > docs/devel/style.rst mandates: > > The "qemu/osdep.h" header contains preprocessor macros that affect > the behavior of core system headers like . It must be > the first include so that core system headers included by external > libraries get the preprocessor macros that QEMU depends on. > > Do not include "qemu/osdep.h" from header files since the .c file > will have already included it. > > A few violations have crept in. Fix them. > > Signed-off-by: Markus Armbruster > Reviewed-by: Philippe Mathieu-Daudé > Reviewed-by: Bin Meng > Reviewed-by: Taylor Simpson > Reviewed-by: Alistair Francis here's v2 - can be applied after you fix all instances of this. Feel free to use. ---> qemu/osdep: we don't include it from headers doing so will lead to trouble eventually - instead of silently working around such cases make it more likely it will fail. Signed-off-by: Michael S. Tsirkin -- diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 7d059ad526..3ddeb7fd41 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -24,7 +24,9 @@ * This work is licensed under the terms of the GNU GPL, version 2 or later. * See the COPYING file in the top-level directory. */ -#ifndef QEMU_OSDEP_H +#ifdef QEMU_OSDEP_H +#warning "Never include qemu/osdep.h from a header!" +#else #define QEMU_OSDEP_H #include "config-host.h" From MAILER-DAEMON Thu Jan 12 12:43:41 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pG1c3-0001hc-Tl for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 12:43:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG1by-0001gP-5t for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 12:43:34 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG1bw-00030B-AN for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 12:43:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1673545411; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=q8K/J3ngYbpkfG8Q1Q/IuCkSZ858JPZU0keveTQ6P4I=; b=ZWNtoJPE9AzpaOleiKUWAYISl5PsOx6kodSgZTeS6Mz6KfX6u1rZ10nUJ6nJWTDmM2N8qn 24FDPK2OIBgPd0wS1MMdCDRrG8XAEGPZpZU235Lyo9VXKAFps7SDu/H4MWyvru2os1mik4 M/c5sK44tVgQbcFubqCKU2VdGtyjb1U= Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-657-082AXiShOEu1Jj84SYjwnw-1; Thu, 12 Jan 2023 12:43:30 -0500 X-MC-Unique: 082AXiShOEu1Jj84SYjwnw-1 Received: by mail-wr1-f72.google.com with SMTP id i28-20020adfa51c000000b002ba26dfcd08so3691618wrb.18 for ; Thu, 12 Jan 2023 09:43:29 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=q8K/J3ngYbpkfG8Q1Q/IuCkSZ858JPZU0keveTQ6P4I=; b=wOfmtEqixyPYwD18r0mItNxChbCciQYI5KyAaPERpx/OxG0no86vD+UY0cLboOv/qf n3U2jqQCOKWNktqf5hWef+wZ2QaK2SxgzqkrcuRR6pvKm1EzcGoMW8MvYWkVDYIuvk0z oY+eYhw9umVm2XCouOYuE7QksTdqzzSI57HCPGrQB9TVVvXxxz3xIJaO5MzWbnpVl3bk MnYWhN+f15DkH0+Z9tJXMRCsxSD3/aAAbdQGfvOGC0h/RE8zjQzLZL0jIzMbwJt2WdHR +xMapZ1eHC9Yr/rw0AZfzM6qy6w2wnDrHU6emQZu/DywSWNoxb+VHqY0c0yAGWyJNJk0 aURQ== X-Gm-Message-State: AFqh2kobuCUddo5MeJ6FG3q7DFPhYkGkbTlVnUAJQxwlLL5Bpeyrgkq8 vaTRjmphEoUdnTMtlzln4EDkQfZoIY6T6cVO7KzAFhRoi5aRAZoZUIxKvvh8XDzLY9OEMf1j089 UkbDk263xprswmzw= X-Received: by 2002:a05:600c:1e8c:b0:3da:1d94:bfa5 with SMTP id be12-20020a05600c1e8c00b003da1d94bfa5mr993410wmb.16.1673545409049; Thu, 12 Jan 2023 09:43:29 -0800 (PST) X-Google-Smtp-Source: AMrXdXsR2WwyP5Vkv/KGXTNOZNSES1CqEIG83Ns/gkJOMdMj/28hfefPxK7WGjocouBUczrAVis1Hg== X-Received: by 2002:a05:600c:1e8c:b0:3da:1d94:bfa5 with SMTP id be12-20020a05600c1e8c00b003da1d94bfa5mr993392wmb.16.1673545408803; Thu, 12 Jan 2023 09:43:28 -0800 (PST) Received: from redhat.com ([2.52.157.155]) by smtp.gmail.com with ESMTPSA id m18-20020a05600c4f5200b003c71358a42dsm36439441wmq.18.2023.01.12.09.43.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jan 2023 09:43:28 -0800 (PST) Date: Thu, 12 Jan 2023 12:43:23 -0500 From: "Michael S. Tsirkin" To: Peter Maydell Cc: Daniel =?iso-8859-1?Q?P=2E_Berrang=E9?= , Markus Armbruster , qemu-devel@nongnu.org, imp@bsdimp.com, kevans@freebsd.org, ben.widawsky@intel.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, jasowang@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, philmd@linaro.org, Bin Meng Subject: Re: [PATCH v3 1/1] include: Don't include qemu/osdep.h Message-ID: <20230112124239-mutt-send-email-mst@kernel.org> References: <20230112115005.1504812-1-armbru@redhat.com> <20230112115005.1504812-2-armbru@redhat.com> <20230112082537-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 17:43:35 -0000 On Thu, Jan 12, 2023 at 03:58:56PM +0000, Peter Maydell wrote: > On Thu, 12 Jan 2023 at 15:14, Daniel P. Berrangé wrote: > > > > On Thu, Jan 12, 2023 at 08:51:26AM -0500, Michael S. Tsirkin wrote: > > > On Thu, Jan 12, 2023 at 12:50:05PM +0100, Markus Armbruster wrote: > > > > docs/devel/style.rst mandates: > > > > > > > > The "qemu/osdep.h" header contains preprocessor macros that affect > > > > the behavior of core system headers like . It must be > > > > the first include so that core system headers included by external > > > > libraries get the preprocessor macros that QEMU depends on. > > > > > > > > Do not include "qemu/osdep.h" from header files since the .c file > > > > will have already included it. > > > > > > > > A few violations have crept in. Fix them. > > > > > > > > Signed-off-by: Markus Armbruster > > > > Reviewed-by: Philippe Mathieu-Daudé > > > > Reviewed-by: Bin Meng > > > > Reviewed-by: Taylor Simpson > > > > Reviewed-by: Alistair Francis > > > > > > With my awesome grep skillz I found one more: > > > $ grep -r --include='*.h' qemu/osdep.h > > > include/block/graph-lock.h:#include "qemu/osdep.h" > > > > > > Looks like all C files must include qemu/osdep.h, no? > > > > Yes, and IMHO that is/was a mistake, as it means our other header > > files are not self-contained, which prevents developer tools from > > reporting useful bugs when you're editting. > > The underlying requirement is "osdep.h must be included > before any system header file". "Always first in every .c file" > is an easy way to achieve that, and "never in any .h file" is > then not mandatory but falls out from the fact that any > such include is pointless and only serves to increase > the compilation time (and to increase the chances that > you don't notice that you forgot osdep.h in your .c file). > > If there's a better way to do this (e.g. one which meant > that it was a compile error to put osdep includes in the > wrong place or to omit them) then that would certainly > save us periodically having to do this kind of fixup commit. > > thanks > -- PMM yes I just posted a patch that will catch most (though not all) such cases. if we switch to -include it will catch all of them but there seems to be some resistance to this idea. From MAILER-DAEMON Thu Jan 12 12:45:01 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pG1dH-0002PD-W4 for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 12:44:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG1dC-0002Jk-Fd for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 12:44:51 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG1dA-00037X-C0 for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 12:44:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1673545486; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NtwoKh/3iAKB2XE/31DuEYgAr//oVfLpFtkMDcaEqpE=; b=HzXJ3B3y56sYVbuA0BiG1VKDZbtnp1Pf9urWetbgB7vo+dA+DapgVBdGBUzMbDhnRkL6Mm GZNxQkuwABmttKUoNzw7rdRsJElm2CI5+3PMwKjHeqYcKV5kGYSvguU5MnPabb5uKxQ7jc h452GpdgZPgWJpK2Vg6deRuPtu1Uhcc= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-215-TbksA1BdNsefWnC0nIvYDQ-1; Thu, 12 Jan 2023 12:44:42 -0500 X-MC-Unique: TbksA1BdNsefWnC0nIvYDQ-1 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.rdu2.redhat.com [10.11.54.2]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 924543813F35; Thu, 12 Jan 2023 17:44:40 +0000 (UTC) Received: from redhat.com (unknown [10.33.36.222]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9F13D4085720; Thu, 12 Jan 2023 17:44:34 +0000 (UTC) Date: Thu, 12 Jan 2023 17:44:31 +0000 From: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= To: "Michael S. Tsirkin" Cc: Markus Armbruster , qemu-devel@nongnu.org, imp@bsdimp.com, kevans@freebsd.org, ben.widawsky@intel.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, jasowang@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, philmd@linaro.org, Bin Meng Subject: Re: [PATCH v3 1/1] include: Don't include qemu/osdep.h Message-ID: Reply-To: Daniel =?utf-8?B?UC4gQmVycmFuZ8Op?= References: <20230112115005.1504812-1-armbru@redhat.com> <20230112115005.1504812-2-armbru@redhat.com> <20230112082537-mutt-send-email-mst@kernel.org> <20230112085520-mutt-send-email-mst@kernel.org> <87zgan4xoo.fsf@pond.sub.org> <20230112123434-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20230112123434-mutt-send-email-mst@kernel.org> User-Agent: Mutt/2.2.9 (2022-11-12) X-Scanned-By: MIMEDefang 3.1 on 10.11.54.2 Received-SPF: pass client-ip=170.10.129.124; envelope-from=berrange@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 17:44:51 -0000 On Thu, Jan 12, 2023 at 12:37:46PM -0500, Michael S. Tsirkin wrote: > On Thu, Jan 12, 2023 at 03:47:19PM +0100, Markus Armbruster wrote: > > "Michael S. Tsirkin" writes: > > > > > On Thu, Jan 12, 2023 at 08:51:32AM -0500, Michael S. Tsirkin wrote: > > >> On Thu, Jan 12, 2023 at 12:50:05PM +0100, Markus Armbruster wrote: > > >> > docs/devel/style.rst mandates: > > >> > > > >> > The "qemu/osdep.h" header contains preprocessor macros that affect > > >> > the behavior of core system headers like . It must be > > >> > the first include so that core system headers included by external > > >> > libraries get the preprocessor macros that QEMU depends on. > > >> > > > >> > Do not include "qemu/osdep.h" from header files since the .c file > > >> > will have already included it. > > >> > > > >> > A few violations have crept in. Fix them. > > >> > > > >> > Signed-off-by: Markus Armbruster > > >> > Reviewed-by: Philippe Mathieu-Daudé > > >> > Reviewed-by: Bin Meng > > >> > Reviewed-by: Taylor Simpson > > >> > Reviewed-by: Alistair Francis > > >> > > >> With my awesome grep skillz I found one more: > > >> $ grep -r --include='*.h' qemu/osdep.h > > >> include/block/graph-lock.h:#include "qemu/osdep.h" > > > > Crept in after I prepared my v1. I neglected to re-check. > > > > > Also: > > > $ grep -r --include='*.inc' qemu/osdep.h > > > ui/vnc-enc-zrle.c.inc:#include "qemu/osdep.h" > > > crypto/akcipher-nettle.c.inc:#include "qemu/osdep.h" > > > crypto/akcipher-gcrypt.c.inc:#include "qemu/osdep.h" > > > crypto/rsakey-nettle.c.inc:#include "qemu/osdep.h" > > > crypto/cipher-gnutls.c.inc:#include "qemu/osdep.h" > > > target/xtensa/core-dc233c/xtensa-modules.c.inc:#include "qemu/osdep.h" > > > target/xtensa/core-sample_controller/xtensa-modules.c.inc:#include "qemu/osdep.h" > > > target/xtensa/core-de212/xtensa-modules.c.inc:#include "qemu/osdep.h" > > > target/xtensa/core-dc232b/xtensa-modules.c.inc:#include "qemu/osdep.h" > > > target/xtensa/core-fsf/xtensa-modules.c.inc:#include "qemu/osdep.h" > > > target/cris/translate_v10.c.inc:#include "qemu/osdep.h" > > > > Good point. Looks like I successfully supressed all memory of .inc. > > > > >> Looks like all C files must include qemu/osdep.h, no? > > > > I remember there are a few exceptions, but I don't remember which .c > > they are. Hmm... see commit 4bd802b209cff612d1a99674a91895b735be8630. > > > > >> How about > > >> > > >> 1- add -include qemu/osdep.h on compile command line > > >> drop #include "qemu/osdep.h" from C files > > > > Then you need to encode the exceptions in the build system. Which might > > not be a bad thing. > > > > >> 2- drop double include guards, replace with a warning. > > >> > > >> following patch implements part 2: > > >> > > >> > > >> qemu/osdep: don't include it from headers > > >> > > >> doing so will lead to trouble eventually - instead of > > >> working around such cases make it more likely it will fail. > > >> > > >> Signed-off-by: Michael S. Tsirkin > > >> > > >> --- > > >> > > >> diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h > > >> index 7d059ad526..e4a60f911c 100644 > > >> --- a/include/qemu/osdep.h > > >> +++ b/include/qemu/osdep.h > > >> @@ -24,7 +24,12 @@ > > >> * This work is licensed under the terms of the GNU GPL, version 2 or later. > > >> * See the COPYING file in the top-level directory. > > >> */ > > >> -#ifndef QEMU_OSDEP_H > > >> +#ifdef QEMU_OSDEP_H > > >> +#warning "Never include qemu/osdep.h from a header!" > > >> +#endif > > >> + > > >> +static inline void qemu_osdep_never_include_from_header(void) {} > > >> + > > > > Why do you need the function, too? > > This seems to give a bit more info if header does get included > twice: instead of just a warning on the second include compiler says > definition is duplicated and then shows where the first definition was. > OTOH first one was almost for sure from the proper first include so > maybe we don't care. Let me drop this. FWIW, if we want to simplify our header guards, we could replace the #ifndef FOO_H #define FOO_H .... #endif /* FOO_H */ with merely #pragma once at the top of each header. With regards, Daniel -- |: https://berrange.com -o- https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o- https://fstop138.berrange.com :| |: https://entangle-photo.org -o- https://www.instagram.com/dberrange :| From MAILER-DAEMON Thu Jan 12 12:47:59 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pG1gF-000438-KV for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 12:47:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG1gE-00042j-K6 for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 12:47:58 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG1gC-0003wH-RO for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 12:47:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1673545676; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/q8S/JFjp2otsghtMnNM7eaxXDSxB6fyjCEWaw5dovY=; b=C3jZgAFJEpWUhnMSnloOeag7JTodrNH7CLoYmuDEMylbwBVwWd1Zkq/HUr0VK0+PxlAGUE G3lWgUt1irfNRpj/L5ZE6NUUQYfXlJlthSMhjjzcNNn3QQKun8SB2HxLTy2I1UcyMZeIkb /7JxpjvqLy5F5SjS3znR3m1WHSieBqc= Received: from mail-wr1-f70.google.com (mail-wr1-f70.google.com [209.85.221.70]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-646-_bZlUyOSPc6pDJRG5gMmIg-1; Thu, 12 Jan 2023 12:47:55 -0500 X-MC-Unique: _bZlUyOSPc6pDJRG5gMmIg-1 Received: by mail-wr1-f70.google.com with SMTP id g24-20020adfa498000000b002bbeb5fc4b7so3096359wrb.10 for ; Thu, 12 Jan 2023 09:47:55 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=/q8S/JFjp2otsghtMnNM7eaxXDSxB6fyjCEWaw5dovY=; b=XOS31zziOfIx0yP9/rAElZ1Upb+MWooN7Ei7CzwwDM5TOellGoKfRR3sKZd+FUWmiT GT5IhUmmlhFMSRXQyZZuWOsA1GMGnwdXC4kNMYVtNoUotyArRoGzT/aHris9azUvkSSw e3NT8gHMEh9NQmWNAHYA5qvC9BxK8ZQNJE7VbEUQ2HSRFYkr0Zqj5u4g3sWW/b90BfoG J6tAtb0P5eGd1WXLLRRRkFJ23CyBSQrLeQfTZiOkAEnpAUp3cFthjesO2qXtnaFhSldr RyUFyXmqMRLp6Pirbo5A6cnT5ag+s1g46pxraL1bcsfT5kriE3hJzouYMEYwhngzeNme BMnw== X-Gm-Message-State: AFqh2krAQUpPAH/91tKzZYGPip9eR3JCH3DTl43QwRFvFsigfdert/3m 84AuxZpPYYm/X2PyI67aFYzSFET/CZKl8HBxqxqjLhUs0pbasR745Ob5r4NxIDA/zIZskyfRsIF pqKZd+LaYvO/bzl8= X-Received: by 2002:a05:600c:601b:b0:3d3:56ce:5693 with SMTP id az27-20020a05600c601b00b003d356ce5693mr55157390wmb.17.1673545674172; Thu, 12 Jan 2023 09:47:54 -0800 (PST) X-Google-Smtp-Source: AMrXdXuSDDDpaT5RVO83IPz9PPIzxQXSBtPASceLihuN8y4ssRDLx2e2vRMkj1s0bLtc50mYHXYY8A== X-Received: by 2002:a05:600c:601b:b0:3d3:56ce:5693 with SMTP id az27-20020a05600c601b00b003d356ce5693mr55157383wmb.17.1673545673979; Thu, 12 Jan 2023 09:47:53 -0800 (PST) Received: from redhat.com ([2.52.157.155]) by smtp.gmail.com with ESMTPSA id z18-20020a5d44d2000000b002368f6b56desm20327271wrr.18.2023.01.12.09.47.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jan 2023 09:47:53 -0800 (PST) Date: Thu, 12 Jan 2023 12:47:48 -0500 From: "Michael S. Tsirkin" To: Daniel =?iso-8859-1?Q?P=2E_Berrang=E9?= Cc: Markus Armbruster , qemu-devel@nongnu.org, imp@bsdimp.com, kevans@freebsd.org, ben.widawsky@intel.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, jasowang@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, philmd@linaro.org, Bin Meng Subject: Re: [PATCH v3 1/1] include: Don't include qemu/osdep.h Message-ID: <20230112124707-mutt-send-email-mst@kernel.org> References: <20230112115005.1504812-1-armbru@redhat.com> <20230112115005.1504812-2-armbru@redhat.com> <20230112082537-mutt-send-email-mst@kernel.org> <20230112085520-mutt-send-email-mst@kernel.org> <87zgan4xoo.fsf@pond.sub.org> <20230112123434-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 17:47:58 -0000 On Thu, Jan 12, 2023 at 05:44:31PM +0000, Daniel P. Berrangé wrote: > On Thu, Jan 12, 2023 at 12:37:46PM -0500, Michael S. Tsirkin wrote: > > On Thu, Jan 12, 2023 at 03:47:19PM +0100, Markus Armbruster wrote: > > > "Michael S. Tsirkin" writes: > > > > > > > On Thu, Jan 12, 2023 at 08:51:32AM -0500, Michael S. Tsirkin wrote: > > > >> On Thu, Jan 12, 2023 at 12:50:05PM +0100, Markus Armbruster wrote: > > > >> > docs/devel/style.rst mandates: > > > >> > > > > >> > The "qemu/osdep.h" header contains preprocessor macros that affect > > > >> > the behavior of core system headers like . It must be > > > >> > the first include so that core system headers included by external > > > >> > libraries get the preprocessor macros that QEMU depends on. > > > >> > > > > >> > Do not include "qemu/osdep.h" from header files since the .c file > > > >> > will have already included it. > > > >> > > > > >> > A few violations have crept in. Fix them. > > > >> > > > > >> > Signed-off-by: Markus Armbruster > > > >> > Reviewed-by: Philippe Mathieu-Daudé > > > >> > Reviewed-by: Bin Meng > > > >> > Reviewed-by: Taylor Simpson > > > >> > Reviewed-by: Alistair Francis > > > >> > > > >> With my awesome grep skillz I found one more: > > > >> $ grep -r --include='*.h' qemu/osdep.h > > > >> include/block/graph-lock.h:#include "qemu/osdep.h" > > > > > > Crept in after I prepared my v1. I neglected to re-check. > > > > > > > Also: > > > > $ grep -r --include='*.inc' qemu/osdep.h > > > > ui/vnc-enc-zrle.c.inc:#include "qemu/osdep.h" > > > > crypto/akcipher-nettle.c.inc:#include "qemu/osdep.h" > > > > crypto/akcipher-gcrypt.c.inc:#include "qemu/osdep.h" > > > > crypto/rsakey-nettle.c.inc:#include "qemu/osdep.h" > > > > crypto/cipher-gnutls.c.inc:#include "qemu/osdep.h" > > > > target/xtensa/core-dc233c/xtensa-modules.c.inc:#include "qemu/osdep.h" > > > > target/xtensa/core-sample_controller/xtensa-modules.c.inc:#include "qemu/osdep.h" > > > > target/xtensa/core-de212/xtensa-modules.c.inc:#include "qemu/osdep.h" > > > > target/xtensa/core-dc232b/xtensa-modules.c.inc:#include "qemu/osdep.h" > > > > target/xtensa/core-fsf/xtensa-modules.c.inc:#include "qemu/osdep.h" > > > > target/cris/translate_v10.c.inc:#include "qemu/osdep.h" > > > > > > Good point. Looks like I successfully supressed all memory of .inc. > > > > > > >> Looks like all C files must include qemu/osdep.h, no? > > > > > > I remember there are a few exceptions, but I don't remember which .c > > > they are. Hmm... see commit 4bd802b209cff612d1a99674a91895b735be8630. > > > > > > >> How about > > > >> > > > >> 1- add -include qemu/osdep.h on compile command line > > > >> drop #include "qemu/osdep.h" from C files > > > > > > Then you need to encode the exceptions in the build system. Which might > > > not be a bad thing. > > > > > > >> 2- drop double include guards, replace with a warning. > > > >> > > > >> following patch implements part 2: > > > >> > > > >> > > > >> qemu/osdep: don't include it from headers > > > >> > > > >> doing so will lead to trouble eventually - instead of > > > >> working around such cases make it more likely it will fail. > > > >> > > > >> Signed-off-by: Michael S. Tsirkin > > > >> > > > >> --- > > > >> > > > >> diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h > > > >> index 7d059ad526..e4a60f911c 100644 > > > >> --- a/include/qemu/osdep.h > > > >> +++ b/include/qemu/osdep.h > > > >> @@ -24,7 +24,12 @@ > > > >> * This work is licensed under the terms of the GNU GPL, version 2 or later. > > > >> * See the COPYING file in the top-level directory. > > > >> */ > > > >> -#ifndef QEMU_OSDEP_H > > > >> +#ifdef QEMU_OSDEP_H > > > >> +#warning "Never include qemu/osdep.h from a header!" > > > >> +#endif > > > >> + > > > >> +static inline void qemu_osdep_never_include_from_header(void) {} > > > >> + > > > > > > Why do you need the function, too? > > > > This seems to give a bit more info if header does get included > > twice: instead of just a warning on the second include compiler says > > definition is duplicated and then shows where the first definition was. > > OTOH first one was almost for sure from the proper first include so > > maybe we don't care. Let me drop this. > > FWIW, if we want to simplify our header guards, we could replace the > > #ifndef FOO_H > #define FOO_H > > .... > > #endif /* FOO_H */ > > with merely > > #pragma once > > at the top of each header. > > With regards, > Daniel Will break this trick, won't it? -- MST From MAILER-DAEMON Thu Jan 12 13:03:34 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pG1vK-00066N-KG for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 13:03:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG1vI-000642-A1 for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 13:03:33 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG1vG-0006Dq-Am for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 13:03:32 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E65A4620ED; Thu, 12 Jan 2023 18:03:19 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8399EC433F0; Thu, 12 Jan 2023 18:03:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673546599; bh=qTv8IYJOt8rByIYZ3hMM0xkfeBjOZoM5UrpJJu2JU+E=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=iteD9gQQarvkFOPGPjov6iJZekX0anWu+jb0TbN9NSB7o2hkXOcI/5Syz2w9VSCN1 2YtndLfOTFAyPjnRheMX2WnSc8lNQgW4VFuSWwPzUhysHETnR9F2u28d+x2Z5dWHjr 7OKLS2HGfh1lOd4wKWYnYRk+OfpaLagUUmZzncdIWFTVqfa/kOcAGDk3NxEGnVYstD 9aQRkf7pWTsWqXMeTIk7OA1MS2+bZ6SyLDMz+1aCWr5CQTv43LKZ8WNDrdis+Ttbxw fDGhhY9dVG0Id3qQeVwRztfI1YaJfqD6OdYw/yt3ivzF4BeGV5p7AC8PmnOsnrmCuD qrQ9OTdK65vzA== Date: Thu, 12 Jan 2023 18:03:16 +0000 From: Conor Dooley To: stage TC Cc: qemu-riscv@nongnu.org, Bin Meng Subject: Re: qemu icicle kit es Message-ID: References: MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="0pieKFcSjvi0SwLC" Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=139.178.84.217; envelope-from=conor@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 18:03:33 -0000 --0pieKFcSjvi0SwLC Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable +CC Bin Meng On Thu, Jan 12, 2023 at 10:52:39AM +0100, stage TC wrote: > Le mer. 11 janv. 2023 =E0 17:40, Conor Dooley a =E9cri= t : > >On Wed, Jan 11, 2023 at 03:21:26PM +0100, stage TC wrote: > >> Hello, > >> Sorry in advance if this is not the right way to do it but I'm a stude= nt > >> and not very used to this kind of stuff (first mailing list). >=20 > >Don't worry, you are doing fine :) One thing to note, this mail appears to be in html form. I am not sure what the QEMU mailing lists stance on html mail is, but on other lists it is frowned upon. Just an FYI if you end up using other mailing lists in the future. > >> I'm trying to run qemu for the Microchip PolarFire SoC Icicle kit but = I'm > >> facing a few issues and the wiki page about that seems obsolete. >=20 > >I must admit, it's a long time since I tried to use a v2020.x release of > >any MPFS software. Last time I did give the steps in the docs a go, > >with a suitably vintage version of QEMU, things worked as expected. > >However, using more recent versions of QEMU I ran into some problems > >with the sd/mmc emulation & never get into U-Boot. >=20 > I was using qemu 7.1 and then came back to qemu 5.2 to try using the same > version as the wiki, does the version of qemu have an impact ? In theory, it shouldn't. I was just suggesting that you use the version in the Wiki as it had obviously been tested at some point in time. > Should I use a more recent one ? Ideally yes, but, like you, I wasn't able to get the example to boot on recent versions. We had some patches internally that supposedly got things working for later versions of QEMU but I never got them to work unfortunately. Bin Meng, you're listed as a supporter (in master anyway) but is that still accurate? I figure there's a good chance it isn't anymore? Have you tested the platform from HSS init at all lately? > >> I follow almost exactly what the wiki does (except I use a terminal as= a > >> tty instead of the socket bc it didn't work) but my HSS won't boot on > >> versions more recent than 2020.10 or 0.99.12. >=20 > >What does "my HSS won't boot" mean? E.g: > >- Does the MICROCHIP logo banner appear (if it existed back then!)? > > If it didnt, the version string I think was. > >- Does the HSS console appear? > >- Does it fail to launch the next bootloader stage? >=20 > With the 0.99.12 and the v2021.02 image the MICROCHIP logo banner appears > with the HSS console and the next bootloader stage seems to launch > correctly (see the logs in the attachment). There is no attachment :( > With the 0.99.15 the MICROCHIP logo banner appears but the HSS console is > stuck at "Selecting SD Card ..." > With a more recent one nothing appends. Right. I think this one is because a change was made to the FPGA bitstream around this time so that the eMMC and SD card are muxxed using a register in the FPGA fabric rather than a GPIO. Which version of QEMU is this? I can try and see if the emulation is missing (or broken). That sort of thing I do have time for (anything I do for QEMU is in my spare time). > >> However I can't find any image compatible for versions older than 2020= =2E10 > >> or 0.99.12 (mines hang at "starting kernel ...". >=20 > >By that do you mean you cannot find a pre-built yocto image? I am not > >sure that there are any that pre-date the one linked in the wiki that > >are still available, as those on GitHub only go back as far as v2021.02 >=20 > Yes, that is what I was talking about. The link in the wiki is obsolete a= nd > the v2021.2 (the only one left with an sdcard specific version) looks to > have been tested on HSS 0.99.15. I'm not sure if there's much point trying an older version of the image than that that was mentioned in the wiki anyway. Because it's an FPGA, changes can (*and have been*) be made to the bitstream that made it incompatible with the emulation of the SoC in QEMU - memory layout, etc - so I'd likely not suggest using newer versions either! > >> Is there any newer version of the tutorial ? Or does anyone have an id= ea > on > >> how to deal with this issue and use qemu for newer versions of the HSS= ? >=20 > >I do my testing with something like: > >$(QEMU)/qemu-system-riscv64 \ > > -M microchip-icicle-kit \ > > -m 2G -smp 5 \ > > -kernel $(vmlinux_bin) \ > > -dtb $(devkit).dtb \ > > -initrd $(initramfs) \ > > -display none \ > > -serial null \ > > -serial stdio >=20 > >This loads a kernel directly rather than using the HSS - for recent > >versions of the HSS, implementations of some peripherals need to be > >added, for example, it checks things like the cache configuration > >during boot, which are not emulated in QEMU. >=20 > >For that reason, I've stuck with doing direct kernel boots. Linux > >v6.0.18 (and the associated devicetree) is the most recent combination > >that I have booted unmodified using the master branch of QEMU using > >this method. >=20 > Thanks, I will try to study and use this method, it may be useful. >=20 > >More recent (linux) kernels come with a device tree that will require > >changes in QEMU to support & I have unfortunately not had the time > >to work on that recently. > >Sorry that I am really of no help to you. >=20 > It helps me at least to know that this is not just something easy that I'm > not able to do for no reason. Thanks. Yeah, I am sorry :/ Conor. --0pieKFcSjvi0SwLC Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY8BLYwAKCRB4tDGHoIJi 0g0/AP94GwR8wLhQYRkVJRsmEg4DqsHEx48aMUgcEKr11gIVBQD8CgRgXM2nbhpE lX3wQNLBLaw3ztOqevppbQViX3MItQE= =Rd5q -----END PGP SIGNATURE----- --0pieKFcSjvi0SwLC-- From MAILER-DAEMON Thu Jan 12 17:34:59 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pG69z-00008h-9q for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 17:34:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG69y-00008F-3X for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 17:34:58 -0500 Received: from mail-oo1-xc42.google.com ([2607:f8b0:4864:20::c42]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pG69v-0008II-Ke for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 17:34:57 -0500 Received: by mail-oo1-xc42.google.com with SMTP id d9-20020a4aa589000000b004af737509f4so5162420oom.11 for ; Thu, 12 Jan 2023 14:34:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=OE84YYKjoFuqo0u9NWqw6q7gCrIwMHdGUeaSVIGT2ls=; b=CviH951q7QV7L4hrftd9zhLpv571+bGcqypr6RtQpfbeVP+dXSbzW7xFTlq5HHvMC+ 9EmdW9DidyO6/IkcV32Sev7WcZ6NPYn1FADmYtP9hfSPisC57mzMbAPld6mQT2k9A4SP iQIc8pQIgPo5370RgCw2rJTxreALMZWtGc4V/1dXwOjfC8M6BOZTwqaia/fVHS8pAP0c XNPPdLHsj4knvKu1e2SgOvEAsh+Z6XzfIdwWXL8aI6RcIZhS73O/1DWIeyMs+0rECkU5 MCPUCxNzr2LtzZHRpt2eqICaWIV80Chfvga3bIC1UJeinuA00Gjc8Qz8PmmeoW7q/iEg YcXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=OE84YYKjoFuqo0u9NWqw6q7gCrIwMHdGUeaSVIGT2ls=; b=XCJkD1ntwE5nrabqcq0DNBqfP6i3+PHL+bToaF3BYDgN2tRqRwqryeSQDaVgXGqR/V 5AtQrYU7kRrnXhg1Zc9yBIj/hnabaRJMdmtdnZUvRmHvpd5mq5YkmCOdqRE38B0mY0ID 5X/UTR1LLEiPNkWDsimFqtvXxOEZpedXQlPCRKrJhuaEH0zySMP+P4K4yQym3NR4M6Cw fPaoUduS2Vknj4aG5gWmlUnwsmLinBVWh2hX9A3IEy3MYbeWhKC3x6uWgak9TO1RBQs3 NbNaR0zIy/fdaJHNCDTJ81vfx0R/fE3S+qccUMV96PYsyTr5DMEdJlsXVNajEpM8NM1m aOgg== X-Gm-Message-State: AFqh2kr5DGnTj8BI0TMzxN+fRqFgU7UALpoWjrQmUuM7WELoXTkqXgbM j4EkqHcBRIxDq/fz+BWVrka2gA== X-Google-Smtp-Source: AMrXdXsjqmveLeam8IXE5jHe5PlwxIQRUAG9R7bCFW7i3BvJa73ql1Uz4gY6n3md5rDhiA0AEvXOhA== X-Received: by 2002:a4a:97b1:0:b0:49f:dba7:5e65 with SMTP id w46-20020a4a97b1000000b0049fdba75e65mr31872147ooi.3.1673562891394; Thu, 12 Jan 2023 14:34:51 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id h4-20020a4a9404000000b004a532a32408sm8946830ooi.16.2023.01.12.14.34.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jan 2023 14:34:50 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v6 0/2] hw/riscv: consolidate kernel init in riscv_load_kernel() Date: Thu, 12 Jan 2023 19:34:42 -0300 Message-Id: <20230112223444.484879-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c42; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc42.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 22:34:58 -0000 Hi, These are the 2 remaining patches, patches 10 and 11, of: "[PATCH v5 00/11] riscv: OpenSBI boot test and cleanups" The first 9 patches are already available in riscv-to-apply.next. The only change made was in patch 10 where we're now handling the case where load_elf_ram_sym is padding the resulting kernel_entry with 1s for 32 bits. Patch 11 is unchanged. Changes from v5: - former patches 1-9: already pushed to riscv-to-apply.next - patch 10: - added an 'is_32bit' flag in riscv_load_kernel(). Use it to eliminate the sign-extension from load_elf() if we're running a 32-bit guest. v5 link: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg00051.html Daniel Henrique Barboza (2): hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() hw/riscv/boot.c: make riscv_load_initrd() static hw/riscv/boot.c | 98 ++++++++++++++++++++++++-------------- hw/riscv/microchip_pfsoc.c | 12 +---- hw/riscv/opentitan.c | 3 +- hw/riscv/sifive_e.c | 4 +- hw/riscv/sifive_u.c | 13 ++--- hw/riscv/spike.c | 10 +--- hw/riscv/virt.c | 13 ++--- include/hw/riscv/boot.h | 3 +- 8 files changed, 77 insertions(+), 79 deletions(-) -- 2.39.0 From MAILER-DAEMON Thu Jan 12 17:34:59 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pG69z-00008r-G3 for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 17:34:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG69y-00008H-5V for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 17:34:58 -0500 Received: from mail-oa1-x36.google.com ([2001:4860:4864:20::36]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pG69v-0008IS-L2 for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 17:34:57 -0500 Received: by mail-oa1-x36.google.com with SMTP id 586e51a60fabf-142b72a728fso20482262fac.9 for ; Thu, 12 Jan 2023 14:34:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qUktm9MRkM4oFfoZsjTS+V+n1+HkAj9zGJHLXb9PJx8=; b=NDUoN7nFbRbnru84cwipGwI4ksQfqacU8UmVBT8gyP26yWNhwxdxcue+ssvYC/Nm+i tkgk3noQ0mGKbjD59pXMqRoKHYesMrALv3tZ+qNOdTOt10/gr+v1qWsJL2/YLCqYfSXK pRM2gj75Eu6N4wpHvvwRXW+hYsHRbdRQ5iigraYpVNDhB6FTL9jxNw5RC6JApRvBIMuX Jwm/bRqMJqPNQWq8ULuSa0ro21/3j6wxzqnfOm1zPIXGPUUZK06uOvYLaaAF5RbjIvEI 3+LuKgIvg3gGwLM6dOzIKgIliohsA1YDD6b172JVvaIiAWk3E6rg1tJVmmJODxXhXjwD +N5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qUktm9MRkM4oFfoZsjTS+V+n1+HkAj9zGJHLXb9PJx8=; b=KmFEmL+sj2E99g7f8hvWpGWxejrQRBs8SdwQTd2MAesWqx9wa9oFtFxMuLhBL0GqVs jVTEAO69QglrDUjcjmdcPpLnSjiEAfSvB16PwG9nF4keGwZu+MbsiC9IdMAM/vxyGiEZ WGhms+USsoWXwfiW75Pk1qXn/4Y4sfoNu12KgXVphCusJs8WznmBM0yoItjor2lAlM+E P1GpeyZ9irLCYLdixu1Xw5lkVey42BHV8LRZFpkzfD+H7l78kFt8e1zIw6CulMivO3M3 ceo1iiMUSDbRYq/SR8O0o8xhT41t5W6LlucYKwQIa3/HilTzTbHKyx1tUv9vgeA2AjNj KbnA== X-Gm-Message-State: AFqh2kpO+NfrnYnV0zqJiz3sVWeAH/+ckueBL6lMV0n2lgEhu6i3PX8s BwKyi4VO9V4W1qyIGe8Fw78Efw== X-Google-Smtp-Source: AMrXdXvPr78a9iy8MIo1ApCbWxaGDJDVzkXkXYU9Aw6HH3FIqO/FC1OF6/tyfWia7a4OEDltUZL1kw== X-Received: by 2002:a05:6870:c985:b0:15e:ceb9:9b67 with SMTP id hi5-20020a056870c98500b0015eceb99b67mr1637885oab.52.1673562894027; Thu, 12 Jan 2023 14:34:54 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id h4-20020a4a9404000000b004a532a32408sm8946830ooi.16.2023.01.12.14.34.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jan 2023 14:34:53 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Palmer Dabbelt Subject: [PATCH v6 1/2] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() Date: Thu, 12 Jan 2023 19:34:43 -0300 Message-Id: <20230112223444.484879-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230112223444.484879-1-dbarboza@ventanamicro.com> References: <20230112223444.484879-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 22:34:58 -0000 The microchip_icicle_kit, sifive_u, spike and virt boards are now doing the same steps when '-kernel' is used: - execute load_kernel() - load init_rd() - write kernel_cmdline Let's fold everything inside riscv_load_kernel() to avoid code repetition. To not change the behavior of boards that aren't calling riscv_load_initrd(), add an 'load_initrd' flag to riscv_load_kernel() and allow these boards to opt out from initrd loading. Cc: Palmer Dabbelt Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 30 +++++++++++++++++++++++++++--- hw/riscv/microchip_pfsoc.c | 12 ++---------- hw/riscv/opentitan.c | 3 ++- hw/riscv/sifive_e.c | 4 +++- hw/riscv/sifive_u.c | 13 +++---------- hw/riscv/spike.c | 10 +--------- hw/riscv/virt.c | 13 +++---------- include/hw/riscv/boot.h | 2 ++ 8 files changed, 43 insertions(+), 44 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 2594276223..e8e8b8517c 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -175,10 +175,12 @@ target_ulong riscv_load_firmware(const char *firmware_filename, target_ulong riscv_load_kernel(MachineState *machine, target_ulong kernel_start_addr, + bool load_initrd, bool is_32bits, symbol_fn_t sym_cb) { const char *kernel_filename = machine->kernel_filename; uint64_t kernel_load_base, kernel_entry; + void *fdt = machine->fdt; g_assert(kernel_filename != NULL); @@ -192,21 +194,43 @@ target_ulong riscv_load_kernel(MachineState *machine, if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL, &kernel_load_base, NULL, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { - return kernel_load_base; + kernel_entry = kernel_load_base; + /* + * kernel_load_base is sign-extended for 32 bits and can + * be padded with '1's. Do an uint32_t cast to avoid the + * padding if we're running a 32 bit CPU. + */ + if (is_32bits) { + kernel_entry = (uint32_t)kernel_load_base; + } + goto out; } if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, NULL, NULL, NULL) > 0) { - return kernel_entry; + goto out; } if (load_image_targphys_as(kernel_filename, kernel_start_addr, current_machine->ram_size, NULL) > 0) { - return kernel_start_addr; + kernel_entry = kernel_start_addr; + goto out; } error_report("could not load kernel '%s'", kernel_filename); exit(1); + +out: + if (load_initrd && machine->initrd_filename) { + riscv_load_initrd(machine, kernel_entry); + } + + if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } + + return kernel_entry; } void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 82ae5e7023..cb9e126827 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -629,16 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", - "bootargs", machine->kernel_cmdline); - } + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, + true, false, NULL); /* Compute the fdt load address in dram */ fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 64d5d435b9..05f2cfde32 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -101,7 +101,8 @@ static void opentitan_board_init(MachineState *machine) } if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); + riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, + false, true, NULL); } } diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 3e3f4b0088..5969ae8131 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -114,7 +114,9 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL); + riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, + false, riscv_is_32bit(&s->soc.cpus), + NULL); } } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index bac394c959..44f5a2ba27 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -598,16 +598,9 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, + true, riscv_is_32bit(&s->soc.u_cpus), + NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index bff9475686..4766152429 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -308,16 +308,8 @@ static void spike_board_init(MachineState *machine) firmware_end_addr); kernel_entry = riscv_load_kernel(machine, kernel_start_addr, + true, riscv_is_32bit(&s->soc[0]), htif_symbol_callback); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c8e35f861e..91f6b02983 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1281,16 +1281,9 @@ static void virt_machine_done(Notifier *notifier, void *data) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, + true, riscv_is_32bit(&s->soc[0]), + NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index f94653a09b..d34f61e280 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -45,6 +45,8 @@ target_ulong riscv_load_firmware(const char *firmware_filename, symbol_fn_t sym_cb); target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, + bool load_initrd, + bool is_32bits, symbol_fn_t sym_cb); void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); -- 2.39.0 From MAILER-DAEMON Thu Jan 12 17:35:01 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pG6A1-00009p-Cu for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 17:35:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG6A0-00009X-C0 for qemu-riscv@nongnu.org; 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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id h4-20020a4a9404000000b004a532a32408sm8946830ooi.16.2023.01.12.14.34.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Jan 2023 14:34:56 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v6 2/2] hw/riscv/boot.c: make riscv_load_initrd() static Date: Thu, 12 Jan 2023 19:34:44 -0300 Message-Id: <20230112223444.484879-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230112223444.484879-1-dbarboza@ventanamicro.com> References: <20230112223444.484879-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c34; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 12 Jan 2023 22:35:00 -0000 The only remaining caller is riscv_load_kernel_and_initrd() which belongs to the same file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng --- hw/riscv/boot.c | 80 ++++++++++++++++++++--------------------- include/hw/riscv/boot.h | 1 - 2 files changed, 40 insertions(+), 41 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index e8e8b8517c..9ec041f727 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -173,6 +173,46 @@ target_ulong riscv_load_firmware(const char *firmware_filename, exit(1); } +static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) +{ + const char *filename = machine->initrd_filename; + uint64_t mem_size = machine->ram_size; + void *fdt = machine->fdt; + hwaddr start, end; + ssize_t size; + + g_assert(filename != NULL); + + /* + * We want to put the initrd far enough into RAM that when the + * kernel is uncompressed it will not clobber the initrd. However + * on boards without much RAM we must ensure that we still leave + * enough room for a decent sized initrd, and on boards with large + * amounts of RAM we must avoid the initrd being so far up in RAM + * that it is outside lowmem and inaccessible to the kernel. + * So for boards with less than 256MB of RAM we put the initrd + * halfway into RAM, and for boards with 256MB of RAM or more we put + * the initrd at 128MB. + */ + start = kernel_entry + MIN(mem_size / 2, 128 * MiB); + + size = load_ramdisk(filename, start, mem_size - start); + if (size == -1) { + size = load_image_targphys(filename, start, mem_size - start); + if (size == -1) { + error_report("could not load ramdisk '%s'", filename); + exit(1); + } + } + + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ + if (fdt) { + end = start + size; + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); + } +} + target_ulong riscv_load_kernel(MachineState *machine, target_ulong kernel_start_addr, bool load_initrd, bool is_32bits, @@ -233,46 +273,6 @@ out: return kernel_entry; } -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) -{ - const char *filename = machine->initrd_filename; - uint64_t mem_size = machine->ram_size; - void *fdt = machine->fdt; - hwaddr start, end; - ssize_t size; - - g_assert(filename != NULL); - - /* - * We want to put the initrd far enough into RAM that when the - * kernel is uncompressed it will not clobber the initrd. However - * on boards without much RAM we must ensure that we still leave - * enough room for a decent sized initrd, and on boards with large - * amounts of RAM we must avoid the initrd being so far up in RAM - * that it is outside lowmem and inaccessible to the kernel. - * So for boards with less than 256MB of RAM we put the initrd - * halfway into RAM, and for boards with 256MB of RAM or more we put - * the initrd at 128MB. - */ - start = kernel_entry + MIN(mem_size / 2, 128 * MiB); - - size = load_ramdisk(filename, start, mem_size - start); - if (size == -1) { - size = load_image_targphys(filename, start, mem_size - start); - if (size == -1) { - error_report("could not load ramdisk '%s'", filename); - exit(1); - } - } - - /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ - if (fdt) { - end = start + size; - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); - } -} - uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) { uint64_t temp, fdt_addr; diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index d34f61e280..85c58c49c8 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -48,7 +48,6 @@ target_ulong riscv_load_kernel(MachineState *machine, bool load_initrd, bool is_32bits, symbol_fn_t sym_cb); -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr, -- 2.39.0 From MAILER-DAEMON Thu Jan 12 19:35:28 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pG82a-0001Hq-Ql for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 19:35:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG82Z-0001Hh-M9 for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 19:35:27 -0500 Received: from mail-ej1-x62a.google.com ([2a00:1450:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pG82X-00013z-Op for qemu-riscv@nongnu.org; Thu, 12 Jan 2023 19:35:27 -0500 Received: by mail-ej1-x62a.google.com with SMTP id mp20so2144751ejc.7 for ; Thu, 12 Jan 2023 16:35:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=Zi9Qa6AMt3W1+CqMED0j4YVa5KH2LsR4xQ1CXfU4iUg=; b=UG+X8Afz74dIGO60ON5PS1+YGE9u7Zi1++4pOZAPSbom0aZKZ5kTEFLS4oewq+7GmF WaFrrNNF8DycV6U01S1NXo20Q/7i4pbX84E/Inls2vfWsNw/f/bjjsH6OR2L16+FvNtI TL3R/1kVCLCGd8o/fqYwmkwMY1Ek2VKnjmwITewb8FtcdIJvqUABWTSi5wocBvMk0ksT 5+ZaMzQB7AqJhwXZ02KmjBjVxUX6KIm58OdfeYcJKawx+nEf1Yy981ZROYbX3m/+Ljn+ tLeGg4P05MJecPmCzeVuZhKJbRO+IM3Phdtd3C/1d77C/0NF9xIi4CR8yZywMk87DUB7 0rCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 00:35:27 -0000 On Fri, Jan 13, 2023 at 2:03 AM Conor Dooley wrote: > > +CC Bin Meng > > On Thu, Jan 12, 2023 at 10:52:39AM +0100, stage TC wrote: > > Le mer. 11 janv. 2023 =C3=A0 17:40, Conor Dooley a = =C3=A9crit : > > >On Wed, Jan 11, 2023 at 03:21:26PM +0100, stage TC wrote: > > >> Hello, > > >> Sorry in advance if this is not the right way to do it but I'm a stu= dent > > >> and not very used to this kind of stuff (first mailing list). > > > > >Don't worry, you are doing fine :) > > One thing to note, this mail appears to be in html form. I am not sure > what the QEMU mailing lists stance on html mail is, but on other lists > it is frowned upon. > Just an FYI if you end up using other mailing lists in the future. > > > >> I'm trying to run qemu for the Microchip PolarFire SoC Icicle kit bu= t I'm > > >> facing a few issues and the wiki page about that seems obsolete. > > > > >I must admit, it's a long time since I tried to use a v2020.x release = of > > >any MPFS software. Last time I did give the steps in the docs a go, > > >with a suitably vintage version of QEMU, things worked as expected. > > >However, using more recent versions of QEMU I ran into some problems > > >with the sd/mmc emulation & never get into U-Boot. > > > > I was using qemu 7.1 and then came back to qemu 5.2 to try using the sa= me > > version as the wiki, does the version of qemu have an impact ? > > In theory, it shouldn't. I was just suggesting that you use the version > in the Wiki as it had obviously been tested at some point in time. > > > Should I use a more recent one ? > > Ideally yes, but, like you, I wasn't able to get the example to boot on > recent versions. We had some patches internally that supposedly got > things working for later versions of QEMU but I never got them to work > unfortunately. > > Bin Meng, you're listed as a supporter (in master anyway) but is that > still accurate? I figure there's a good chance it isn't anymore? > Have you tested the platform from HSS init at all lately? Yes, I am still maintaining the QEMU PolarFire SoC. The WiKi page listed the exact HSS version I tested and if it doesn't, it should be a regression in QEMU. If yes, I would like to have a look at that. Running more recent HSS is known to break, because QEMU does not follow up quite closely with the HSS implementation as HSS has evolved quite quickly in the past. > > > >> I follow almost exactly what the wiki does (except I use a terminal = as a > > >> tty instead of the socket bc it didn't work) but my HSS won't boot o= n > > >> versions more recent than 2020.10 or 0.99.12. > > > > >What does "my HSS won't boot" mean? E.g: > > >- Does the MICROCHIP logo banner appear (if it existed back then!)? > > > If it didnt, the version string I think was. > > >- Does the HSS console appear? > > >- Does it fail to launch the next bootloader stage? > > > > With the 0.99.12 and the v2021.02 image the MICROCHIP logo banner appea= rs > > with the HSS console and the next bootloader stage seems to launch > > correctly (see the logs in the attachment). > > There is no attachment :( > > > With the 0.99.15 the MICROCHIP logo banner appears but the HSS console = is > > stuck at "Selecting SD Card ..." > > With a more recent one nothing appends. > > Right. I think this one is because a change was made to the FPGA > bitstream around this time so that the eMMC and SD card are muxxed using > a register in the FPGA fabric rather than a GPIO. > > Which version of QEMU is this? I can try and see if the emulation is > missing (or broken). That sort of thing I do have time for (anything I > do for QEMU is in my spare time). > > > >> However I can't find any image compatible for versions older than 20= 20.10 > > >> or 0.99.12 (mines hang at "starting kernel ...". > > > > >By that do you mean you cannot find a pre-built yocto image? I am not > > >sure that there are any that pre-date the one linked in the wiki that > > >are still available, as those on GitHub only go back as far as v2021.0= 2 > > > > Yes, that is what I was talking about. The link in the wiki is obsolete= and > > the v2021.2 (the only one left with an sdcard specific version) looks t= o > > have been tested on HSS 0.99.15. > > I'm not sure if there's much point trying an older version of the image > than that that was mentioned in the wiki anyway. > > Because it's an FPGA, changes can (*and have been*) be made to the > bitstream that made it incompatible with the emulation of the SoC in > QEMU - memory layout, etc - so I'd likely not suggest using newer > versions either! > > > >> Is there any newer version of the tutorial ? Or does anyone have an = idea > > on > > >> how to deal with this issue and use qemu for newer versions of the H= SS ? > > > > >I do my testing with something like: > > >$(QEMU)/qemu-system-riscv64 \ > > > -M microchip-icicle-kit \ > > > -m 2G -smp 5 \ > > > -kernel $(vmlinux_bin) \ > > > -dtb $(devkit).dtb \ > > > -initrd $(initramfs) \ > > > -display none \ > > > -serial null \ > > > -serial stdio > > > > >This loads a kernel directly rather than using the HSS - for recent > > >versions of the HSS, implementations of some peripherals need to be > > >added, for example, it checks things like the cache configuration > > >during boot, which are not emulated in QEMU. > > > > >For that reason, I've stuck with doing direct kernel boots. Linux > > >v6.0.18 (and the associated devicetree) is the most recent combination > > >that I have booted unmodified using the master branch of QEMU using > > >this method. > > > > Thanks, I will try to study and use this method, it may be useful. > > > > >More recent (linux) kernels come with a device tree that will require > > >changes in QEMU to support & I have unfortunately not had the time > > >to work on that recently. > > >Sorry that I am really of no help to you. > > > > It helps me at least to know that this is not just something easy that = I'm > > not able to do for no reason. Thanks. > > Yeah, I am sorry :/ > Regards, Bin From MAILER-DAEMON Thu Jan 12 20:29:06 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pG8sT-0001Rw-QR for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 20:29:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pG8sR-0001Ph-0P; Thu, 12 Jan 2023 20:29:04 -0500 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pG8sP-0002YS-5Z; Thu, 12 Jan 2023 20:29:02 -0500 Received: by mail-ej1-x62e.google.com with SMTP id qk9so48973704ejc.3; Thu, 12 Jan 2023 17:28:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=9A1ZZW2o7YNRm6qWBBlZkKmOqbhIJuRs6thTCITuwEU=; b=FR7UVVraxh14X29L8+KryP397lnzkobLwlyfzTtphYHUcNQxh+Yf36Lb7LV8ZMQaei cbXIZV9u+C/IpX65oJBNarhol1adjVemp9MRuWrVJaTJpHFFqpHiwyHhcEndRTX59v9z NbqsXp6+mnqnXIqyGcmWB3KNCMtYuz/EcDGrTX68b0lxVmod+TqxY23DTAeor2X43TkA GW80RfHQ9fT+TV76lwvfg0I/y9ZXbQrPZOI6bdxkXMyfUKnRF4z7cvI0vOWG7R6jewC3 rH1Ls0mx2dER93iBU/QVYqtljBZopETOFwIoDQyYeyqwlifAXvq64yD6AXeS3x9lnrzU HsoQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=9A1ZZW2o7YNRm6qWBBlZkKmOqbhIJuRs6thTCITuwEU=; b=RF1eL4SDRsRJTgtqSOkYvB3b9LsjfxF4ZZqYSpjkALxrwCwhLj53hR7u90B2KAcvjH zS7yJxHfintwR4Orc0K18knkZ+ENdVD72OYL4V+TkyIIVGdgrIZ9cSqM19cTu4aN1PId oufHfHA+UVjYCrDLDglIi186btrxrDF61FkhIrX6ur3Bm9eyy5fb0ToohmH7gkyrQl5m M+3R94yO5y5YTkVc198Il3fEUqwrEB+1LuPV4O6wHg2VRMHUvtxKTw0kc2MNypl+cDAn iZ7RTn5iKIwMDjjbrKiWdxxNPfMLC1xDUyqXenhynZvcWRy4YcB+eqefb2HXYhu6j7eh H4Ig== X-Gm-Message-State: AFqh2koQXRyxBnITlFNnJHCzPqbPe7exPoFIZOJF8JNGZo2uh8u5oTzv OECnqyjLaHnhqQ31xUlMXf4oCUIlOtx3/6d4uKU= X-Google-Smtp-Source: AMrXdXsaTbzxk+401PKXru+axyeK5eKwYNpvB+MOw8VVvc65tF0v4WSsf5Ds+Xr2ITdMQ/3VEEIpOFhpQ0K4hCnZ93A= X-Received: by 2002:a17:906:1945:b0:7c0:bb4c:e792 with SMTP id b5-20020a170906194500b007c0bb4ce792mr6334293eje.618.1673573338504; Thu, 12 Jan 2023 17:28:58 -0800 (PST) MIME-Version: 1.0 References: <20230110201405.247785-1-dbarboza@ventanamicro.com> In-Reply-To: From: Bin Meng Date: Fri, 13 Jan 2023 09:28:37 +0800 Message-ID: Subject: Re: [PATCH 0/2] target/riscv/cpu: fix sifive_u 32/64bits boot in riscv-to-apply.next To: Alistair Francis Cc: Daniel Henrique Barboza , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, richard.henderson@linaro.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 01:29:04 -0000 Hi Daniel, On Wed, Jan 11, 2023 at 1:03 PM Alistair Francis wrote: > > On Wed, Jan 11, 2023 at 6:17 AM Daniel Henrique Barboza > wrote: > > > > Hi, > > > > I found this bug when testing my avocado changes in riscv-to-apply.next. > > The sifive_u board, both 32 and 64 bits, stopped booting OpenSBI. The > > guest hangs indefinitely. > > > > Git bisect points that this patch broke things: > > > > 8c3f35d25e7e98655c609b6c1e9f103b9240f8f8 is the first bad commit > > commit 8c3f35d25e7e98655c609b6c1e9f103b9240f8f8 > > Author: Weiwei Li > > Date: Wed Dec 28 14:20:21 2022 +0800 > > > > target/riscv: add support for Zca extension > > > > Modify the check for C extension to Zca (C implies Zca) > > (https://github.com/alistair23/qemu/commit/8c3f35d25e7e98655c609b6c1e9f103b9240f8f8) > > > > > > But this patch per se isn't doing anything wrong. The root of the > > problem is that this patch makes assumptions based on the previous > > patch: > > > > commit a2b409aa6cadc1ed9715e1ab916ddd3dade0ba85 > > Author: Weiwei Li > > Date: Wed Dec 28 14:20:20 2022 +0800 > > > > target/riscv: add cfg properties for Zc* extension > > (https://github.com/alistair23/qemu/commit/a2b409aa6cadc1ed9715e1ab916ddd3dade0ba85) > > > > Which added a lot of logic and assumptions that are being skipped by all > > the SiFive boards because, during riscv_cpu_realize(), we have this > > code: > > > > /* If only MISA_EXT is unset for misa, then set it from properties */ > > if (env->misa_ext == 0) { > > uint32_t ext = 0; > > (...) > > } > > > > In short, we have a lot of code that are being skipped by all SiFive > > CPUs because these CPUs are setting a non-zero value in set_misa() in > > their respective cpu_init() functions. > > > > It's possible to just hack in and fix the SiFive problem in isolate, but > > I believe we can do better and allow all riscv_cpu_realize() to be executed > > for all CPUs, regardless of what they've done during their cpu_init(). > > > > > > Daniel Henrique Barboza (2): > > target/riscv/cpu: set cpu->cfg in register_cpu_props() > > target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() > > Thanks for the patches > > I have rebased these onto the latest master and dropped the other > series. That way when the other series is applied we don't break > bisectability. It seems these 2 patches are already in Alistair's tree. Richard had a suggestion for patch 1 and I had some minor comments too. Do you plan to resend a v2 for that? Regards, Bin From MAILER-DAEMON Thu Jan 12 21:48:24 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pGA73-0005z3-Uk for mharc-qemu-riscv@gnu.org; Thu, 12 Jan 2023 21:48:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGA72-0005yd-8B; Thu, 12 Jan 2023 21:48:12 -0500 Received: from mail-lj1-x236.google.com ([2a00:1450:4864:20::236]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pGA70-0003WL-74; Thu, 12 Jan 2023 21:48:12 -0500 Received: by mail-lj1-x236.google.com with SMTP id s25so21255503lji.2; Thu, 12 Jan 2023 18:48:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=nJIyrwmDZagShhmrMf90K26Db2y0lkWYZWLOFyQFuec=; b=l5FGQvm6UaRnMtIiVd9fbvY8n71R/cYSY6clpaaq8M/UkdS4aI6LX2pA5ZxJzYOjKG Faqjd829hc9wEzHwluMTzwL3oLSfEUFVQlQ/vY3aD5Ie/Wqn5HQQBvCRBkH6twaP/eeT gkYGGav7V8NHF/C5tmgjIrBS3grUEeGRHgh/yo/xZiQ3FyrYHWEEFVxqMD7ytrphK10Z BzGXSd2TICQFDPXNqFr+2JBKTek3KUR4yW84HD+UC6iVxL/rSApASiRqahQtus6Frcmq OVYC8lowMbTC5xN+itwyIn7KKKNWEdnVuQQ6pQOwKkk7ckaApP93HllbhzoGHyHeAxGP 75pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=nJIyrwmDZagShhmrMf90K26Db2y0lkWYZWLOFyQFuec=; b=Bo+1ln+IL3ZiZ3Q2fhognNF+o2K/g69vj+iY377z/kajxj2soz1MucQuqnniPWPPf9 oVmA3QcGU6RwFJ3b5h1hvQXxq6+0F7+T2NOufWphw2usFOTwNDvLbObgTO9saXA8emsj 2BgMI3frDJSQ2i6EAzrBUfZJ4LZwz7ozfjOV6+xULhA3fyZE/Zyatcg9Z3xZ4QdNB20r ZQAm+amOIdYU9GF8TpOSbFUfJJcBup/xYlTTl5+M4vVdRKc1hdsB4+vsIMEB19HxdZoX 8zlykLQ3g68Dy72pUtlMovqs381Hkj5M69giXmqOmlYIZ7IxiT2dzH1/tWHQApL6j2d2 KCeA== X-Gm-Message-State: AFqh2kr1WfzytZ7q6OlF0YBLZzFjOUJpBjuuXPB8ig8eVmE8qqP850qn MsAwoIMtvOeqXiZv4aJC/840CrQS6SCpdpVPbYY= X-Google-Smtp-Source: AMrXdXuER2kLsLwcE4lnp9ItRd4etqztiRCQDmuoLWYUcDt5ksGG3RHk9GFnmdOcA9DiJdW52nTIaiJRky5WDXZO+dk= X-Received: by 2002:a2e:7c19:0:b0:285:6c31:f069 with SMTP id x25-20020a2e7c19000000b002856c31f069mr860403ljc.523.1673578087958; Thu, 12 Jan 2023 18:48:07 -0800 (PST) MIME-Version: 1.0 References: <20230112223444.484879-1-dbarboza@ventanamicro.com> <20230112223444.484879-2-dbarboza@ventanamicro.com> In-Reply-To: <20230112223444.484879-2-dbarboza@ventanamicro.com> From: Bin Meng Date: Fri, 13 Jan 2023 10:47:56 +0800 Message-ID: Subject: Re: [PATCH v6 1/2] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Palmer Dabbelt Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::236; envelope-from=bmeng.cn@gmail.com; helo=mail-lj1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 02:48:13 -0000 On Fri, Jan 13, 2023 at 6:37 AM Daniel Henrique Barboza wrote: > > The microchip_icicle_kit, sifive_u, spike and virt boards are now doing > the same steps when '-kernel' is used: > > - execute load_kernel() > - load init_rd() > - write kernel_cmdline > > Let's fold everything inside riscv_load_kernel() to avoid code > repetition. To not change the behavior of boards that aren't calling > riscv_load_initrd(), add an 'load_initrd' flag to riscv_load_kernel() > and allow these boards to opt out from initrd loading. > > Cc: Palmer Dabbelt > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/boot.c | 30 +++++++++++++++++++++++++++--- > hw/riscv/microchip_pfsoc.c | 12 ++---------- > hw/riscv/opentitan.c | 3 ++- > hw/riscv/sifive_e.c | 4 +++- > hw/riscv/sifive_u.c | 13 +++---------- > hw/riscv/spike.c | 10 +--------- > hw/riscv/virt.c | 13 +++---------- > include/hw/riscv/boot.h | 2 ++ > 8 files changed, 43 insertions(+), 44 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 2594276223..e8e8b8517c 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -175,10 +175,12 @@ target_ulong riscv_load_firmware(const char *firmware_filename, > > target_ulong riscv_load_kernel(MachineState *machine, > target_ulong kernel_start_addr, > + bool load_initrd, bool is_32bits, > symbol_fn_t sym_cb) > { > const char *kernel_filename = machine->kernel_filename; > uint64_t kernel_load_base, kernel_entry; > + void *fdt = machine->fdt; > > g_assert(kernel_filename != NULL); > > @@ -192,21 +194,43 @@ target_ulong riscv_load_kernel(MachineState *machine, > if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, > NULL, &kernel_load_base, NULL, NULL, 0, > EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { > - return kernel_load_base; > + kernel_entry = kernel_load_base; > + /* > + * kernel_load_base is sign-extended for 32 bits and can > + * be padded with '1's. Do an uint32_t cast to avoid the > + * padding if we're running a 32 bit CPU. > + */ I see both kernel_load_base and kernel_entry are declared as a uint64_t, and load_elf_ram_sym() accepts a uint64_t parameter. Where does the sign-extension happen? > + if (is_32bits) { > + kernel_entry = (uint32_t)kernel_load_base; > + } > + goto out; > } > > if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, > NULL, NULL, NULL) > 0) { > - return kernel_entry; > + goto out; > } > > if (load_image_targphys_as(kernel_filename, kernel_start_addr, > current_machine->ram_size, NULL) > 0) { > - return kernel_start_addr; > + kernel_entry = kernel_start_addr; > + goto out; > } > > error_report("could not load kernel '%s'", kernel_filename); > exit(1); > + > +out: > + if (load_initrd && machine->initrd_filename) { > + riscv_load_initrd(machine, kernel_entry); > + } > + > + if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { > + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", > + machine->kernel_cmdline); > + } > + > + return kernel_entry; > } > > void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index 82ae5e7023..cb9e126827 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -629,16 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) > kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, > firmware_end_addr); > > - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); > - > - if (machine->initrd_filename) { > - riscv_load_initrd(machine, kernel_entry); > - } > - > - if (machine->kernel_cmdline && *machine->kernel_cmdline) { > - qemu_fdt_setprop_string(machine->fdt, "/chosen", > - "bootargs", machine->kernel_cmdline); > - } > + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, > + true, false, NULL); > > /* Compute the fdt load address in dram */ > fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, > diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c > index 64d5d435b9..05f2cfde32 100644 > --- a/hw/riscv/opentitan.c > +++ b/hw/riscv/opentitan.c > @@ -101,7 +101,8 @@ static void opentitan_board_init(MachineState *machine) > } > > if (machine->kernel_filename) { > - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); > + riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, > + false, true, NULL); > } > } > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > index 3e3f4b0088..5969ae8131 100644 > --- a/hw/riscv/sifive_e.c > +++ b/hw/riscv/sifive_e.c > @@ -114,7 +114,9 @@ static void sifive_e_machine_init(MachineState *machine) > memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); > > if (machine->kernel_filename) { > - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL); > + riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, > + false, riscv_is_32bit(&s->soc.cpus), > + NULL); > } > } > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index bac394c959..44f5a2ba27 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -598,16 +598,9 @@ static void sifive_u_machine_init(MachineState *machine) > kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, > firmware_end_addr); > > - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); > - > - if (machine->initrd_filename) { > - riscv_load_initrd(machine, kernel_entry); > - } > - > - if (machine->kernel_cmdline && *machine->kernel_cmdline) { > - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", > - machine->kernel_cmdline); > - } > + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, > + true, riscv_is_32bit(&s->soc.u_cpus), > + NULL); > } else { > /* > * If dynamic firmware is used, it doesn't know where is the next mode > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index bff9475686..4766152429 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -308,16 +308,8 @@ static void spike_board_init(MachineState *machine) > firmware_end_addr); > > kernel_entry = riscv_load_kernel(machine, kernel_start_addr, > + true, riscv_is_32bit(&s->soc[0]), > htif_symbol_callback); > - > - if (machine->initrd_filename) { > - riscv_load_initrd(machine, kernel_entry); > - } > - > - if (machine->kernel_cmdline && *machine->kernel_cmdline) { > - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", > - machine->kernel_cmdline); > - } > } else { > /* > * If dynamic firmware is used, it doesn't know where is the next mode > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index c8e35f861e..91f6b02983 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -1281,16 +1281,9 @@ static void virt_machine_done(Notifier *notifier, void *data) > kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], > firmware_end_addr); > > - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); > - > - if (machine->initrd_filename) { > - riscv_load_initrd(machine, kernel_entry); > - } > - > - if (machine->kernel_cmdline && *machine->kernel_cmdline) { > - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", > - machine->kernel_cmdline); > - } > + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, > + true, riscv_is_32bit(&s->soc[0]), > + NULL); > } else { > /* > * If dynamic firmware is used, it doesn't know where is the next mode > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h > index f94653a09b..d34f61e280 100644 > --- a/include/hw/riscv/boot.h > +++ b/include/hw/riscv/boot.h > @@ -45,6 +45,8 @@ target_ulong riscv_load_firmware(const char *firmware_filename, > symbol_fn_t sym_cb); > target_ulong riscv_load_kernel(MachineState *machine, > target_ulong firmware_end_addr, > + bool load_initrd, > + bool is_32bits, > symbol_fn_t sym_cb); > void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); > uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); > -- Regards, Bin From MAILER-DAEMON Fri Jan 13 00:23:42 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pGCXV-00077R-VG for mharc-qemu-riscv@gnu.org; Fri, 13 Jan 2023 00:23:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGCXT-000775-9W; Fri, 13 Jan 2023 00:23:40 -0500 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pGCXQ-0004Hi-VJ; Fri, 13 Jan 2023 00:23:38 -0500 Received: by mail-ej1-x631.google.com with SMTP id ss4so42507627ejb.11; Thu, 12 Jan 2023 21:23:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; 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Thu, 12 Jan 2023 21:23:34 -0800 (PST) MIME-Version: 1.0 References: <20230102115241.25733-1-dbarboza@ventanamicro.com> <20230102115241.25733-11-dbarboza@ventanamicro.com> In-Reply-To: From: Bin Meng Date: Fri, 13 Jan 2023 13:23:22 +0800 Message-ID: Subject: Re: [PATCH v5 10/11] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() To: Alistair Francis Cc: Daniel Henrique Barboza , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng , Palmer Dabbelt Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 05:23:40 -0000 Hi Alistair, On Thu, Jan 12, 2023 at 8:36 AM Alistair Francis wrote: > > On Mon, Jan 2, 2023 at 9:55 PM Daniel Henrique Barboza > wrote: > > > > The microchip_icicle_kit, sifive_u, spike and virt boards are now doing > > the same steps when '-kernel' is used: > > > > - execute load_kernel() > > - load init_rd() > > - write kernel_cmdline > > > > Let's fold everything inside riscv_load_kernel() to avoid code > > repetition. To not change the behavior of boards that aren't calling > > riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and > > allow these boards to opt out from initrd loading. > > > > Cc: Palmer Dabbelt > > Signed-off-by: Daniel Henrique Barboza > > --- > > hw/riscv/boot.c | 22 +++++++++++++++++++--- > > hw/riscv/microchip_pfsoc.c | 12 ++---------- > > hw/riscv/opentitan.c | 2 +- > > hw/riscv/sifive_e.c | 3 ++- > > hw/riscv/sifive_u.c | 12 ++---------- > > hw/riscv/spike.c | 11 +---------- > > hw/riscv/virt.c | 12 ++---------- > > include/hw/riscv/boot.h | 1 + > > 8 files changed, 30 insertions(+), 45 deletions(-) > > > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > > index 2594276223..4888d5c1e0 100644 > > --- a/hw/riscv/boot.c > > +++ b/hw/riscv/boot.c > > @@ -175,10 +175,12 @@ target_ulong riscv_load_firmware(const char *firmware_filename, > > > > target_ulong riscv_load_kernel(MachineState *machine, > > target_ulong kernel_start_addr, > > + bool load_initrd, > > symbol_fn_t sym_cb) > > { > > const char *kernel_filename = machine->kernel_filename; > > uint64_t kernel_load_base, kernel_entry; > > + void *fdt = machine->fdt; > > > > g_assert(kernel_filename != NULL); > > > > @@ -192,21 +194,35 @@ target_ulong riscv_load_kernel(MachineState *machine, > > if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, > > NULL, &kernel_load_base, NULL, NULL, 0, > > EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { > > - return kernel_load_base; > > + kernel_entry = kernel_load_base; > > This breaks 32-bit Xvisor loading. It seems that for the 32-bit guest > we get a value of 0xffffffff80000000. Shouldn't the bug be the 32-bit Xvisor image? How can a 32-bit image return an address of 0xffffffff80000000? > > Previously the top bits would be lost as we return a target_ulong from > this function, but with this change we pass the value > 0xffffffff80000000 to riscv_load_initrd() which causes failures. > > This diff fixes the failure for me > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 4888d5c1e0..f08ed44b97 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -194,7 +194,7 @@ target_ulong riscv_load_kernel(MachineState *machine, > if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, > NULL, &kernel_load_base, NULL, NULL, 0, > EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { > - kernel_entry = kernel_load_base; > + kernel_entry = (target_ulong) kernel_load_base; > goto out; > } > > > but I don't think that's the right fix. We should instead look at the > CPU XLEN and drop the high bits if required. > > I'm going to drop this patch, do you mind looking into a proper fix? > Regards, Bin From MAILER-DAEMON Fri Jan 13 02:13:46 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pGEG2-0001uU-AG for mharc-qemu-riscv@gnu.org; Fri, 13 Jan 2023 02:13:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGEG0-0001tY-Dx for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 02:13:44 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pGEFy-00008e-3Z for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 02:13:44 -0500 Received: by mail-wr1-x42e.google.com with SMTP id r2so20182302wrv.7 for ; Thu, 12 Jan 2023 23:13:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=hd5wX4mhBiOqr2EsJItmpSvHE6MDIX5pIKPGQitnuL4=; b=MGQ7EXL7j+DMWVtATEkizi3CLfQOxVV3S79osvy7FxtGM+UFqVuLNZPa5vRDY4Kp/c GEvalByOMW+pcRTYx10c41gnS800wFmiSjGiR9hY1IVriQqqXsYuwl9TitqcvhgIQOW9 o15LFq3hGgK++DAVdpcJIrxF8RRB1n2imJckq6ZtYUc8k8IE0d1XymrbXRJvs20CEWW1 v1BqHFncxagzpHx/pElk/KgOVztRnqeMCLu516+P4KnqiNQTxkE9g8mk3e8wV6b5Mabw ZJHUURuV4LS1tObpnKLsGa4sDNOw9kTYJWFbnjaiqkU2VgucDGA8wndb0s67QNjNaMhR /wMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=hd5wX4mhBiOqr2EsJItmpSvHE6MDIX5pIKPGQitnuL4=; b=R4ncZ73g+tzT+t/dt8J9LDezXquxchv6Z+pNLgyQL49BWJUlz4YvD74rbTdQnUK9XH aUf+z/VEwugSAOYyDBgF5z/m352QD8KzhubTtlWJumLySlwOTRv2CDpy5gO/J4VfIi+k Sl8ADP5CBC++z498WKgw+Yvhj/7R9TQ8+7KnfgV9OHyxGsaWAYD8LNKjV57upqqq8Ofq 4e3A64R0tTiYfatwwFabYHCWgYt7RPbgKRJRXuxNbgp/74FaHCXNnEkbncbVq6bwgynu G5FtMLyK9NQyJsjPQoLOC268M8hQd4ZeDVZK7aq9RnyrqUDQ7Bd4Nu+yBbHHZRgHNJ6w sH0A== X-Gm-Message-State: AFqh2koaQ94EPo5VcMGCPeTV8kgj8aPPiiNZa5thr6WfkaLBvMfQHZK+ Ihiz3EfoDL57uQMu1JqH7Qm89A== X-Google-Smtp-Source: AMrXdXtF8eE4F8PMAgc9XyMHqvggyvSWUbD+cfVLEjMvZf9li7c02pZEC98WKoM09gfr0tRuABqpkA== X-Received: by 2002:a5d:5685:0:b0:2bb:4b40:2d18 with SMTP id f5-20020a5d5685000000b002bb4b402d18mr15573749wrv.62.1673594019392; Thu, 12 Jan 2023 23:13:39 -0800 (PST) Received: from [192.168.30.216] ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id s1-20020a5d4ec1000000b002882600e8a0sm18222921wrv.12.2023.01.12.23.13.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Jan 2023 23:13:38 -0800 (PST) Message-ID: <9bc6b28f-2f12-e774-3bb2-73d835540ecb@linaro.org> Date: Fri, 13 Jan 2023 08:13:37 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v6 1/2] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() Content-Language: en-US To: Bin Meng , Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Palmer Dabbelt References: <20230112223444.484879-1-dbarboza@ventanamicro.com> <20230112223444.484879-2-dbarboza@ventanamicro.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=philmd@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 07:13:44 -0000 On 13/1/23 03:47, Bin Meng wrote: > On Fri, Jan 13, 2023 at 6:37 AM Daniel Henrique Barboza > wrote: >> >> The microchip_icicle_kit, sifive_u, spike and virt boards are now doing >> the same steps when '-kernel' is used: >> >> - execute load_kernel() >> - load init_rd() >> - write kernel_cmdline >> >> Let's fold everything inside riscv_load_kernel() to avoid code >> repetition. To not change the behavior of boards that aren't calling >> riscv_load_initrd(), add an 'load_initrd' flag to riscv_load_kernel() >> and allow these boards to opt out from initrd loading. >> >> Cc: Palmer Dabbelt >> Signed-off-by: Daniel Henrique Barboza >> --- >> hw/riscv/boot.c | 30 +++++++++++++++++++++++++++--- >> hw/riscv/microchip_pfsoc.c | 12 ++---------- >> hw/riscv/opentitan.c | 3 ++- >> hw/riscv/sifive_e.c | 4 +++- >> hw/riscv/sifive_u.c | 13 +++---------- >> hw/riscv/spike.c | 10 +--------- >> hw/riscv/virt.c | 13 +++---------- >> include/hw/riscv/boot.h | 2 ++ >> 8 files changed, 43 insertions(+), 44 deletions(-) >> >> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c >> index 2594276223..e8e8b8517c 100644 >> --- a/hw/riscv/boot.c >> +++ b/hw/riscv/boot.c >> @@ -175,10 +175,12 @@ target_ulong riscv_load_firmware(const char *firmware_filename, >> >> target_ulong riscv_load_kernel(MachineState *machine, >> target_ulong kernel_start_addr, >> + bool load_initrd, bool is_32bits, >> symbol_fn_t sym_cb) >> { >> const char *kernel_filename = machine->kernel_filename; >> uint64_t kernel_load_base, kernel_entry; >> + void *fdt = machine->fdt; >> >> g_assert(kernel_filename != NULL); >> >> @@ -192,21 +194,43 @@ target_ulong riscv_load_kernel(MachineState *machine, >> if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, >> NULL, &kernel_load_base, NULL, NULL, 0, >> EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { >> - return kernel_load_base; >> + kernel_entry = kernel_load_base; >> + /* >> + * kernel_load_base is sign-extended for 32 bits and can >> + * be padded with '1's. Do an uint32_t cast to avoid the >> + * padding if we're running a 32 bit CPU. >> + */ > > I see both kernel_load_base and kernel_entry are declared as a > uint64_t, and load_elf_ram_sym() accepts a uint64_t parameter. Where > does the sign-extension happen? Likely load_elf_ram_sym()'s translate_fn() argument is missing? * @translate_fn: optional function to translate load addresses * @translate_opaque: opaque data passed to @translate_fn Others archs provide: $ git grep -F '(void *opaque, uint64_t' hw/alpha/dp264.c:23:static uint64_t cpu_alpha_superpage_to_phys(void *opaque, uint64_t addr) hw/cris/boot.c:62:static uint64_t translate_kernel_address(void *opaque, uint64_t addr) hw/hppa/machine.c:107:static uint64_t cpu_hppa_to_phys(void *opaque, uint64_t addr) hw/intc/openpic.c:857:static uint64_t openpic_src_read(void *opaque, uint64_t addr, unsigned len) hw/loongarch/virt.c:390:static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr) hw/microblaze/boot.c:112:static uint64_t translate_kernel_address(void *opaque, uint64_t addr) hw/nios2/boot.c:78:static uint64_t translate_kernel_address(void *opaque, uint64_t addr) hw/ppc/mac_newworld.c:117:static uint64_t translate_kernel_address(void *opaque, uint64_t addr) hw/ppc/mac_oldworld.c:75:static uint64_t translate_kernel_address(void *opaque, uint64_t addr) hw/ppc/spapr.c:1263:static uint64_t translate_kernel_address(void *opaque, uint64_t addr) hw/s390x/ipl.c:106:static uint64_t bios_translate_addr(void *opaque, uint64_t srcaddr) hw/sparc/sun4m.c:217:static uint64_t translate_kernel_address(void *opaque, uint64_t addr) hw/sparc/sun4m.c:673:static uint64_t translate_prom_address(void *opaque, uint64_t addr) hw/sparc64/sun4u.c:412:static uint64_t translate_prom_address(void *opaque, uint64_t addr) hw/ssi/xlnx-versal-ospi.c:1613:static void ospi_indac_write(void *opaque, uint64_t value, unsigned int size) hw/timer/pxa2xx_timer.c:117:static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu) hw/timer/pxa2xx_timer.c:134:static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n) hw/xtensa/sim.c:40:static uint64_t translate_phys_addr(void *opaque, uint64_t addr) hw/xtensa/xtfpga.c:189:static uint64_t translate_phys_addr(void *opaque, uint64_t addr) >> + if (is_32bits) { >> + kernel_entry = (uint32_t)kernel_load_base; >> + } >> + goto out; >> } From MAILER-DAEMON Fri Jan 13 02:17:11 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pGEJL-0004Bb-0B for mharc-qemu-riscv@gnu.org; Fri, 13 Jan 2023 02:17:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGEJF-00049U-A8 for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 02:17:05 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pGEJC-000195-2h for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 02:17:03 -0500 Received: by mail-wm1-x32f.google.com with SMTP id f25-20020a1c6a19000000b003da221fbf48so406101wmc.1 for ; Thu, 12 Jan 2023 23:17:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; 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Thu, 12 Jan 2023 23:17:00 -0800 (PST) Received: from [192.168.30.216] ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id d6-20020a05600c3ac600b003da0dc39872sm6626785wms.6.2023.01.12.23.16.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Jan 2023 23:16:59 -0800 (PST) Message-ID: Date: Fri, 13 Jan 2023 08:16:58 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v5 10/11] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() Content-Language: en-US To: Alistair Francis , Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng , Palmer Dabbelt References: <20230102115241.25733-1-dbarboza@ventanamicro.com> <20230102115241.25733-11-dbarboza@ventanamicro.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 07:17:05 -0000 On 12/1/23 01:34, Alistair Francis wrote: > On Mon, Jan 2, 2023 at 9:55 PM Daniel Henrique Barboza > wrote: >> >> The microchip_icicle_kit, sifive_u, spike and virt boards are now doing >> the same steps when '-kernel' is used: >> >> - execute load_kernel() >> - load init_rd() >> - write kernel_cmdline >> >> Let's fold everything inside riscv_load_kernel() to avoid code >> repetition. To not change the behavior of boards that aren't calling >> riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and >> allow these boards to opt out from initrd loading. >> >> Cc: Palmer Dabbelt >> Signed-off-by: Daniel Henrique Barboza >> --- >> hw/riscv/boot.c | 22 +++++++++++++++++++--- >> hw/riscv/microchip_pfsoc.c | 12 ++---------- >> hw/riscv/opentitan.c | 2 +- >> hw/riscv/sifive_e.c | 3 ++- >> hw/riscv/sifive_u.c | 12 ++---------- >> hw/riscv/spike.c | 11 +---------- >> hw/riscv/virt.c | 12 ++---------- >> include/hw/riscv/boot.h | 1 + >> 8 files changed, 30 insertions(+), 45 deletions(-) >> @@ -192,21 +194,35 @@ target_ulong riscv_load_kernel(MachineState *machine, >> if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, >> NULL, &kernel_load_base, NULL, NULL, 0, >> EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { >> - return kernel_load_base; >> + kernel_entry = kernel_load_base; > > This breaks 32-bit Xvisor loading. It seems that for the 32-bit guest > we get a value of 0xffffffff80000000. > > Previously the top bits would be lost as we return a target_ulong from > this function, but with this change we pass the value > 0xffffffff80000000 to riscv_load_initrd() which causes failures. > > This diff fixes the failure for me > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 4888d5c1e0..f08ed44b97 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -194,7 +194,7 @@ target_ulong riscv_load_kernel(MachineState *machine, > if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, > NULL, &kernel_load_base, NULL, NULL, 0, > EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { > - kernel_entry = kernel_load_base; > + kernel_entry = (target_ulong) kernel_load_base; > goto out; > } > > > but I don't think that's the right fix. We should instead look at the > CPU XLEN and drop the high bits if required. Ah, that is what should be done in load_elf_ram_sym()'s missing translate_fn() handler. From MAILER-DAEMON Fri Jan 13 05:20:14 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pGHAU-0007mb-Fd for mharc-qemu-riscv@gnu.org; Fri, 13 Jan 2023 05:20:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGHAT-0007mL-H0 for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 05:20:13 -0500 Received: from mail-oa1-x41.google.com ([2001:4860:4864:20::41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pGHAR-0005Wy-Nl for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 05:20:13 -0500 Received: by mail-oa1-x41.google.com with SMTP id 586e51a60fabf-15027746720so21758360fac.13 for ; Fri, 13 Jan 2023 02:20:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=QtQwRfF+ulK+aqGp72w++VL8SNUDal9NahqXeCW1cRk=; b=V12qxT57idfmBA+iwRFqkLRyevXQLy2fji9UNSgWVy/UjC83U0YHbJY+cYtzK3LFfo EmIEsSPTZLMpXoqHprFgHHKvACdc3NqdhvrW7dgahn4hGNQUOp6VbUIEdTwD4kjd1ooO rOMBSf/0jlxgxPSN8mlhprYkubM04vcEhneWiGFm4N5i94GwgSoQzig9HbbTRGqSFMNC rqTDM7vIbEBcs2IwyY/pxJEj4MfYgf3nzbrQ/vxXmr5QRYIGVfvsdDEXNFvZrilsUs6l AC9RAjKQG6FM2RwHamlnWTcLf+2PpKmVds5INTBvLjPauRwlzNBaxfpIBdGNVYAVQ2Gu fB5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=QtQwRfF+ulK+aqGp72w++VL8SNUDal9NahqXeCW1cRk=; b=lVh5NBwoYkx7HNJdT8puBPFdlvpwgyk8OQQHvu1/X4nLftX1gPyW6agYtnpdR5Xuy6 fWDtQ3RnQeQIRafjEglztGC2CVLu5Q+NfzHN01MjwL2+J7mouKfZi8Wkf9SsrVYtiPnx JmT0/jkRjEOJY9QXsWn+fthMcc229lOYapDwAdIcG9dRhUV4FhkKX3g33aIjggk11HYo NXb9gU76kmEATc3YGtONPKjq5ySIs+HylUluhhkIECf7mp3eAuELT8ccMg9HRu8Y+7DM LtfmmdXpvrqSSu1rsffAIHK5T7EfT1Nob0GuaGjiIVFLbwh8ZMETqx2vpIXzZu9ZwSoZ mCpQ== X-Gm-Message-State: AFqh2kowghmIESUPsaQUvc6rvT8WAlcg7xwyd6zQEoJSr455Nt5R4tNg jX+6RvJ+XIYWmkvjiXtzfbjtKQ== X-Google-Smtp-Source: AMrXdXv6i2Ck5Z4gPG/Bqs6MnvV487Yy6xIFsqz2q0C2vbFneesOpYSOXneilrLYqHqS90kSyYpgMg== X-Received: by 2002:a05:6871:b12:b0:152:d0dc:2bba with SMTP id fq18-20020a0568710b1200b00152d0dc2bbamr17402091oab.15.1673605210221; Fri, 13 Jan 2023 02:20:10 -0800 (PST) Received: from [192.168.68.107] ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id bd13-20020a056870d78d00b0014fe4867dc7sm10142801oab.56.2023.01.13.02.20.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Jan 2023 02:20:09 -0800 (PST) Message-ID: Date: Fri, 13 Jan 2023 07:20:06 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH 0/2] target/riscv/cpu: fix sifive_u 32/64bits boot in riscv-to-apply.next To: Bin Meng , Alistair Francis Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, richard.henderson@linaro.org References: <20230110201405.247785-1-dbarboza@ventanamicro.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2001:4860:4864:20::41; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x41.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 10:20:13 -0000 Hi Bin! On 1/12/23 22:28, Bin Meng wrote: > Hi Daniel, > > On Wed, Jan 11, 2023 at 1:03 PM Alistair Francis wrote: >> On Wed, Jan 11, 2023 at 6:17 AM Daniel Henrique Barboza >> wrote: >>> Hi, >>> >>> I found this bug when testing my avocado changes in riscv-to-apply.next. >>> The sifive_u board, both 32 and 64 bits, stopped booting OpenSBI. The >>> guest hangs indefinitely. >>> >>> Git bisect points that this patch broke things: >>> >>> 8c3f35d25e7e98655c609b6c1e9f103b9240f8f8 is the first bad commit >>> commit 8c3f35d25e7e98655c609b6c1e9f103b9240f8f8 >>> Author: Weiwei Li >>> Date: Wed Dec 28 14:20:21 2022 +0800 >>> >>> target/riscv: add support for Zca extension >>> >>> Modify the check for C extension to Zca (C implies Zca) >>> (https://github.com/alistair23/qemu/commit/8c3f35d25e7e98655c609b6c1e9f103b9240f8f8) >>> >>> >>> But this patch per se isn't doing anything wrong. The root of the >>> problem is that this patch makes assumptions based on the previous >>> patch: >>> >>> commit a2b409aa6cadc1ed9715e1ab916ddd3dade0ba85 >>> Author: Weiwei Li >>> Date: Wed Dec 28 14:20:20 2022 +0800 >>> >>> target/riscv: add cfg properties for Zc* extension >>> (https://github.com/alistair23/qemu/commit/a2b409aa6cadc1ed9715e1ab916ddd3dade0ba85) >>> >>> Which added a lot of logic and assumptions that are being skipped by all >>> the SiFive boards because, during riscv_cpu_realize(), we have this >>> code: >>> >>> /* If only MISA_EXT is unset for misa, then set it from properties */ >>> if (env->misa_ext == 0) { >>> uint32_t ext = 0; >>> (...) >>> } >>> >>> In short, we have a lot of code that are being skipped by all SiFive >>> CPUs because these CPUs are setting a non-zero value in set_misa() in >>> their respective cpu_init() functions. >>> >>> It's possible to just hack in and fix the SiFive problem in isolate, but >>> I believe we can do better and allow all riscv_cpu_realize() to be executed >>> for all CPUs, regardless of what they've done during their cpu_init(). >>> >>> >>> Daniel Henrique Barboza (2): >>> target/riscv/cpu: set cpu->cfg in register_cpu_props() >>> target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() >> Thanks for the patches >> >> I have rebased these onto the latest master and dropped the other >> series. That way when the other series is applied we don't break >> bisectability. > It seems these 2 patches are already in Alistair's tree. > > Richard had a suggestion for patch 1 and I had some minor comments > too. Do you plan to resend a v2 for that? I'll re-send the v2 with your comments addressed. About Richard's suggestion, I believe I replied that it would require more thought because, as it is now, it would break boards that are setting their properties after register_cpu_props(). The overall simplification of the cpu_init() code across all RISC-V boards is good thing to do in the future as a follow up, IMO. Thanks, Daniel > > Regards, > Bin From MAILER-DAEMON Fri Jan 13 05:21:33 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pGHBl-0008OZ-4F for mharc-qemu-riscv@gnu.org; Fri, 13 Jan 2023 05:21:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGHBj-0008N8-7j for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 05:21:31 -0500 Received: from mail-oi1-x232.google.com ([2607:f8b0:4864:20::232]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pGHBh-0005ks-Hk for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 05:21:31 -0500 Received: by mail-oi1-x232.google.com with SMTP id s124so568800oif.1 for ; Fri, 13 Jan 2023 02:21:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=/QjALvLmossEhKT/lFtmq9q4aFTAAfWiOsIVEH6r/Ps=; b=HLrRWxu6eHyvXo4CV1qc8d436Jfwj1CUuLC8rHHDOt4T5igUkSB3uEcG86xTZQ9Zuq dMGV8N0rXM7w5AZXgm0aoGQb5WVja97eNTmqSbodF8A82VlLj98YsyNX/7RIU4TH7zGJ izJa+oFa8jNeQnq9xAjiq2ces+51q7fIqu4yDIKt6maBBHT6ZctmQm9Y6RyhPtlsfNOG h63Nwi0ALPzos7yTLiz+NY51oMn80cSXA3lE+xq93ndRpwqPwdMcuEWuIZenXvNOh2bH tx+TiVeoYdY1DFhqnlPVrgvqLngSOdLufZJ3aQKmkzVTfAeOceM1Ix04yfANaoC0YYW2 GRog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=/QjALvLmossEhKT/lFtmq9q4aFTAAfWiOsIVEH6r/Ps=; b=lPbVwy5ALP/i4virnFz/orSOUVJyOVsayKS2fVNOKbImWz/JhEpjyslBzsQUUkssPx EB+B/DZZ0CAz7vRHXFhMTolW51amRmq0GMaLWbSi0KXyScGzMU0jOHAenApiySKoNVl4 od4WTPp5DRv8OSdbsPn0A+WPcjqUX0YkX8yuDcoClZqsXfJIMun96L/yJruqi9hzI/jo To6FWmy1a7zAzyfH8GUHDSNdw6L6ODwDfj7YgCRC/kJ/HVpKcZ0ZbN77GPccNiyaR8yQ 5i+/8XeRbpn4/5yrrD1HHCmuMiVdcuIHlfvzbPM+lXhbjQjr2vQ0t9rFlHFxJCzi8kLv YB7Q== X-Gm-Message-State: AFqh2kpDpGShUGVSX6iLztaqutwQGEQvpYttK6hi3lo2dw9P8UPQ7VNS yHU2RZm0oz3vRB8IfPYIi9GJgg== X-Google-Smtp-Source: AMrXdXvU6DpwS8+MJcFGs+uTsRwuWB2+2O4NRKqHPO7DBuyVXeozReQ5bVYNPbn/J47AJgmlFn3pLg== X-Received: by 2002:a05:6808:2391:b0:364:5a39:ec53 with SMTP id bp17-20020a056808239100b003645a39ec53mr8891098oib.22.1673605288515; Fri, 13 Jan 2023 02:21:28 -0800 (PST) Received: from [192.168.68.107] ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id dp6-20020a056808424600b003458d346a60sm8996156oib.25.2023.01.13.02.21.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Jan 2023 02:21:27 -0800 (PST) Message-ID: <0ba72b27-0c3d-2d3d-adec-899717f40594@ventanamicro.com> Date: Fri, 13 Jan 2023 07:21:23 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH v5 10/11] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() Content-Language: en-US To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Alistair Francis Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng , Palmer Dabbelt References: <20230102115241.25733-1-dbarboza@ventanamicro.com> <20230102115241.25733-11-dbarboza@ventanamicro.com> From: Daniel Henrique Barboza In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 10:21:31 -0000 On 1/13/23 04:16, Philippe Mathieu-Daudé wrote: > On 12/1/23 01:34, Alistair Francis wrote: >> On Mon, Jan 2, 2023 at 9:55 PM Daniel Henrique Barboza >> wrote: >>> >>> The microchip_icicle_kit, sifive_u, spike and virt boards are now doing >>> the same steps when '-kernel' is used: >>> >>> - execute load_kernel() >>> - load init_rd() >>> - write kernel_cmdline >>> >>> Let's fold everything inside riscv_load_kernel() to avoid code >>> repetition. To not change the behavior of boards that aren't calling >>> riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and >>> allow these boards to opt out from initrd loading. >>> >>> Cc: Palmer Dabbelt >>> Signed-off-by: Daniel Henrique Barboza >>> --- >>>   hw/riscv/boot.c            | 22 +++++++++++++++++++--- >>>   hw/riscv/microchip_pfsoc.c | 12 ++---------- >>>   hw/riscv/opentitan.c       |  2 +- >>>   hw/riscv/sifive_e.c        |  3 ++- >>>   hw/riscv/sifive_u.c        | 12 ++---------- >>>   hw/riscv/spike.c           | 11 +---------- >>>   hw/riscv/virt.c            | 12 ++---------- >>>   include/hw/riscv/boot.h    |  1 + >>>   8 files changed, 30 insertions(+), 45 deletions(-) > >>> @@ -192,21 +194,35 @@ target_ulong riscv_load_kernel(MachineState *machine, >>>       if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, >>>                            NULL, &kernel_load_base, NULL, NULL, 0, >>>                            EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { >>> -        return kernel_load_base; >>> +        kernel_entry = kernel_load_base; >> >> This breaks 32-bit Xvisor loading. It seems that for the 32-bit guest >> we get a value of 0xffffffff80000000. >> >> Previously the top bits would be lost as we return a target_ulong from >> this function, but with this change we pass the value >> 0xffffffff80000000 to riscv_load_initrd() which causes failures. >> >> This diff fixes the failure for me >> >> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c >> index 4888d5c1e0..f08ed44b97 100644 >> --- a/hw/riscv/boot.c >> +++ b/hw/riscv/boot.c >> @@ -194,7 +194,7 @@ target_ulong riscv_load_kernel(MachineState *machine, >>      if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, >>                           NULL, &kernel_load_base, NULL, NULL, 0, >>                           EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { >> -        kernel_entry = kernel_load_base; >> +        kernel_entry = (target_ulong) kernel_load_base; >>          goto out; >>      } >> >> >> but I don't think that's the right fix. We should instead look at the >> CPU XLEN and drop the high bits if required. > > Ah, that is what should be done in load_elf_ram_sym()'s missing > translate_fn() handler. Interesting. I'll try it again and re-send. Daniel From MAILER-DAEMON Fri Jan 13 05:31:15 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pGHL9-0002NU-Gn for mharc-qemu-riscv@gnu.org; Fri, 13 Jan 2023 05:31:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGHL0-0002Md-MT; Fri, 13 Jan 2023 05:31:11 -0500 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pGHKy-0007Pr-MQ; Fri, 13 Jan 2023 05:31:06 -0500 Received: by mail-ej1-x62d.google.com with SMTP id v6so8267401ejg.6; Fri, 13 Jan 2023 02:31:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=6qrn/zWQrhD5PIOBLhjVXgOsoJ6B2+uxbzYQSooNaAs=; b=Y0YCvWo/JE9mXQna7OorEEyeWvGvKHWULX5dPmLoZUwgzsjKxkJ6WeKsFJ8nzobOTk Qxp0OnhhojIbtVXPdVDICNQRpkLVxN2pm6l7lXi6NE4C0znO2xwfl7ymh4SilO94fQfm IPA2WwsPcPjh4SnPMdY/6LlvDD8+m903Wk6W/IZr/PC+ZhtsDzGGs+IayaBXRLTKa4sv QO+y4KjR0nQ84z8zVgSSU9X+jCopfL6nA4+ETurqEWOFnx+4OrbsOGHUIQ790S6VNVJw F8Bl03jgMlKYKgoRvr0lnJU5c20GkKFzBjjQgWwZlyAcWbqs81KEDp/iuF1jio30T/Tk G9Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6qrn/zWQrhD5PIOBLhjVXgOsoJ6B2+uxbzYQSooNaAs=; b=UA+7XKra+TCB5ZCKboZEIOmRwUeplfris7lRGAESjYV6cIR/eOZwm9RyTGVnIkD0Fg dtl3siqypBYhS0GYWhixxyhR8zAGwgCNcV8/6J0qZ9dZ+QPuzy+mK4aOcWf7knKkiZek F8ruogpxdByPOo8qQCLm6SEmztMM/xcXTCxMJKxaCBA0o4wft92YGLMpZOOwK22304SY DUlaz5ZPGjUeGf8/d7pkIcTNRKszcuESPZAMowIioIza+Y4Qb5D3Cn2kVG61aAm5y/Hg Nixu0nR0jRSHA1KgYVvyfw4YQ0xar5aeXxozD7Oji2Z3ANoqxCdLRiGJyRMdaejSjsnl RLmw== X-Gm-Message-State: AFqh2krKPp9QXNNt+2fzySo424hmp0O7Pcc+5RYElG7VYUHy+TJ30BKW ABwwCKjjD59SthvisEZtFGBTEebFa6ztkyvmXH0= X-Google-Smtp-Source: AMrXdXuT44KBmeejHuFfZ/DEN35/2hRbRBxJGWf5yUGepuv6L+Owisu2DvKn9XAbRJWNInTY6C8EnumJnTMthSY6rvo= X-Received: by 2002:a17:906:9f25:b0:84d:49c3:51ea with SMTP id fy37-20020a1709069f2500b0084d49c351eamr1773337ejc.13.1673605861716; Fri, 13 Jan 2023 02:31:01 -0800 (PST) MIME-Version: 1.0 References: <20230102115241.25733-1-dbarboza@ventanamicro.com> <20230102115241.25733-11-dbarboza@ventanamicro.com> <0ba72b27-0c3d-2d3d-adec-899717f40594@ventanamicro.com> In-Reply-To: <0ba72b27-0c3d-2d3d-adec-899717f40594@ventanamicro.com> From: Bin Meng Date: Fri, 13 Jan 2023 18:30:49 +0800 Message-ID: Subject: Re: [PATCH v5 10/11] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() To: Daniel Henrique Barboza Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng , Palmer Dabbelt Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 10:31:13 -0000 On Fri, Jan 13, 2023 at 6:23 PM Daniel Henrique Barboza wrote: > > > > On 1/13/23 04:16, Philippe Mathieu-Daud=C3=A9 wrote: > > On 12/1/23 01:34, Alistair Francis wrote: > >> On Mon, Jan 2, 2023 at 9:55 PM Daniel Henrique Barboza > >> wrote: > >>> > >>> The microchip_icicle_kit, sifive_u, spike and virt boards are now doi= ng > >>> the same steps when '-kernel' is used: > >>> > >>> - execute load_kernel() > >>> - load init_rd() > >>> - write kernel_cmdline > >>> > >>> Let's fold everything inside riscv_load_kernel() to avoid code > >>> repetition. To not change the behavior of boards that aren't calling > >>> riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() a= nd > >>> allow these boards to opt out from initrd loading. > >>> > >>> Cc: Palmer Dabbelt > >>> Signed-off-by: Daniel Henrique Barboza > >>> --- > >>> hw/riscv/boot.c | 22 +++++++++++++++++++--- > >>> hw/riscv/microchip_pfsoc.c | 12 ++---------- > >>> hw/riscv/opentitan.c | 2 +- > >>> hw/riscv/sifive_e.c | 3 ++- > >>> hw/riscv/sifive_u.c | 12 ++---------- > >>> hw/riscv/spike.c | 11 +---------- > >>> hw/riscv/virt.c | 12 ++---------- > >>> include/hw/riscv/boot.h | 1 + > >>> 8 files changed, 30 insertions(+), 45 deletions(-) > > > >>> @@ -192,21 +194,35 @@ target_ulong riscv_load_kernel(MachineState *ma= chine, > >>> if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, > >>> NULL, &kernel_load_base, NULL, NULL, 0, > >>> EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { > >>> - return kernel_load_base; > >>> + kernel_entry =3D kernel_load_base; > >> > >> This breaks 32-bit Xvisor loading. It seems that for the 32-bit guest > >> we get a value of 0xffffffff80000000. > >> > >> Previously the top bits would be lost as we return a target_ulong from > >> this function, but with this change we pass the value > >> 0xffffffff80000000 to riscv_load_initrd() which causes failures. > >> > >> This diff fixes the failure for me > >> > >> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > >> index 4888d5c1e0..f08ed44b97 100644 > >> --- a/hw/riscv/boot.c > >> +++ b/hw/riscv/boot.c > >> @@ -194,7 +194,7 @@ target_ulong riscv_load_kernel(MachineState *machi= ne, > >> if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, > >> NULL, &kernel_load_base, NULL, NULL, 0, > >> EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { > >> - kernel_entry =3D kernel_load_base; > >> + kernel_entry =3D (target_ulong) kernel_load_base; > >> goto out; > >> } > >> > >> > >> but I don't think that's the right fix. We should instead look at the > >> CPU XLEN and drop the high bits if required. > > > > Ah, that is what should be done in load_elf_ram_sym()'s missing > > translate_fn() handler. > > Interesting. I'll try it again and re-send. > If that fixes the problem, it should be a separate patch. I still don't understand why 32-bit xvisor image has a 64-bit address encod= ed? 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[2.7.42.160]) by smtp.gmail.com with ESMTPSA id t12-20020a05600c198c00b003d9de0c39fasm30691591wmq.36.2023.01.13.02.34.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 02:34:57 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v5 0/2] riscv: Allow user to set the satp mode Date: Fri, 13 Jan 2023 11:34:51 +0100 Message-Id: <20230113103453.42776-1-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x335.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 10:35:01 -0000 This introduces new properties to allow the user to set the satp mode, see patch 1 for full syntax. v5: - Simplify v4 implementation by leveraging valid_vm_1_10_32/64, as suggested by Andrew - Split the v4 patch into 2 patches as suggested by Andrew - Lot of other minor corrections, from Andrew - Set the satp mode N by disabling the satp mode N + 1 - Add a helper to set satp mode from a string, as suggested by Frank v4: - Use custom boolean properties instead of OnOffAuto properties, based on ARMVQMap, as suggested by Andrew v3: - Free sv_name as pointed by Bin - Replace satp-mode with boolean properties as suggested by Andrew - Removed RB from Atish as the patch considerably changed v2: - Use error_setg + return as suggested by Alistair - Add RB from Atish - Fixed checkpatch issues missed in v1 - Replaced Ludovic email address with the rivos one Alexandre Ghiti (2): riscv: Pass Object to register_cpu_props instead of DeviceState riscv: Allow user to set the satp mode hw/riscv/virt.c | 19 ++-- target/riscv/cpu.c | 236 +++++++++++++++++++++++++++++++++++++++++++-- target/riscv/cpu.h | 19 ++++ target/riscv/csr.c | 17 +++- 4 files changed, 270 insertions(+), 21 deletions(-) -- 2.37.2 From MAILER-DAEMON Fri Jan 13 05:36:03 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pGHPn-0003qK-0R for mharc-qemu-riscv@gnu.org; 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[2.7.42.160]) by smtp.gmail.com with ESMTPSA id k30-20020a05600c1c9e00b003d9b89a39b2sm27341414wms.10.2023.01.13.02.35.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 02:35:58 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v5 1/2] riscv: Pass Object to register_cpu_props instead of DeviceState Date: Fri, 13 Jan 2023 11:34:52 +0100 Message-Id: <20230113103453.42776-2-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230113103453.42776-1-alexghiti@rivosinc.com> References: <20230113103453.42776-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 10:36:02 -0000 One can extract the DeviceState pointer from the Object pointer, so pass the Object for future commits to access other fields of Object. No functional changes intended. Signed-off-by: Alexandre Ghiti --- target/riscv/cpu.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cc75ca7667..7181b34f86 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -200,7 +200,7 @@ static const char * const riscv_intr_names[] = { "reserved" }; -static void register_cpu_props(DeviceState *dev); +static void register_cpu_props(Object *obj); const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { @@ -238,7 +238,7 @@ static void riscv_any_cpu_init(Object *obj) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif set_priv_version(env, PRIV_VERSION_1_12_0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); } #if defined(TARGET_RISCV64) @@ -247,7 +247,7 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -280,7 +280,7 @@ static void rv128_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -290,7 +290,7 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -343,7 +343,7 @@ static void riscv_host_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, 0); #endif - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); } #endif @@ -1083,9 +1083,10 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_END_OF_LIST(), }; -static void register_cpu_props(DeviceState *dev) +static void register_cpu_props(Object *obj) { Property *prop; + DeviceState *dev = DEVICE(obj); for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); -- 2.37.2 From MAILER-DAEMON Fri Jan 13 05:37:06 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pGHQo-0004Rm-MW for mharc-qemu-riscv@gnu.org; Fri, 13 Jan 2023 05:37:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGHQm-0004Qt-Fm for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 05:37:04 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pGHQj-0008Ju-QP for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 05:37:04 -0500 Received: by mail-wm1-x334.google.com with SMTP id ay40so14973348wmb.2 for ; Fri, 13 Jan 2023 02:37:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bTx5bej53p4aZG7Y8vT5uMw2vQpJvrGmkuGu4VWPpck=; b=jLHr+o1UKMvZPmjkM9ZMLpVMUqu/JOljzFOPFq+nJZF9U6YAR+pUk41D6eMyzNl7WP yEN/igpmYaO0pmHvu5Lc+4aknbivW4D+kQI+GYUEyZB3oXJbtS5UijZsRz7D1qgoNk2/ g4OIoL6RAQmM7WIDkpbX67jULdtvybsIsuKw8esB6cJaaRJxXGAEC/aC2+OapCOJBuO6 fvShetiAgP/nQD9LUg4hBKder2H9RIiH62QSaw9jXj3QhxMcESovUGXE0hDUFGbrSCVM nPlOSxMtUzQs9ufv4ygxyzhLwLyKc9kVhD66mqoX4M1M9qCbNkvDEpkg6sB7N+ZKY/G3 ZLaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bTx5bej53p4aZG7Y8vT5uMw2vQpJvrGmkuGu4VWPpck=; b=RLHu8aU0NzbmQSigl0qyul23vVfKFYATMl+nW0W2dRa/IdewTu05hDepdvTwRs90Lx H56Wk/HxkGOCfiXg33RFrJ4Er5FvuU65X73YZO7Qj7Vfl2M6mSvHpLk/aNljdeCOPl7D yP7XJhLWDgsOleKFZ6teJxMpyFfyrRjS/wpmoPBOoLORlFCNzA6U6JmEuIezRIb2gSV5 /06HQzqhhfwziEB6JGvy8p/zgoyxl0h2UqtGFTaRdpYObzgyxjFkO5P0z+ynZ5vocKi3 CmTjhTlvriWrbSyUCiafXHnRkx4ruWqj01Nm0rXpz0P1egZjO1ih3P3r2x2zj+sEDI61 EzTg== X-Gm-Message-State: AFqh2kodumE+hVciKgMpghndRQMSRMzfnAY3/NBVzj8OUEV+aPQu9IJE Dn/ccV+envW+EtGOj0pWBQnw1Q== X-Google-Smtp-Source: AMrXdXskE3MuCNe2xeoHERH8Ho8VUeeNCyMvUlIOduGhoynOW3RRgRDxzZdwZ+xIY0quEWC/FFjCUg== X-Received: by 2002:a05:600c:3b93:b0:3d2:1bf6:5796 with SMTP id n19-20020a05600c3b9300b003d21bf65796mr58945798wms.35.1673606219900; Fri, 13 Jan 2023 02:36:59 -0800 (PST) Received: from alex-rivos.ba.rivosinc.com (lfbn-lyo-1-450-160.w2-7.abo.wanadoo.fr. [2.7.42.160]) by smtp.gmail.com with ESMTPSA id h10-20020a1ccc0a000000b003d237d60318sm24696480wmb.2.2023.01.13.02.36.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 02:36:59 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Ludovic Henry Subject: [PATCH v5 2/2] riscv: Allow user to set the satp mode Date: Fri, 13 Jan 2023 11:34:53 +0100 Message-Id: <20230113103453.42776-3-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230113103453.42776-1-alexghiti@rivosinc.com> References: <20230113103453.42776-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x334.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 10:37:04 -0000 RISC-V specifies multiple sizes for addressable memory and Linux probes for the machine's support at startup via the satp CSR register (done in csr.c:validate_vm). As per the specification, sv64 must support sv57, which in turn must support sv48...etc. So we can restrict machine support by simply setting the "highest" supported mode and the bare mode is always supported. You can set the satp mode using the new properties "sv32", "sv39", "sv48", "sv57" and "sv64" as follows: -cpu rv64,sv57=on # Linux will boot using sv57 scheme -cpu rv64,sv39=on # Linux will boot using sv39 scheme -cpu rv64,sv57=off # Linux will boot using sv48 scheme -cpu rv64 # Linux will boot using sv57 scheme by default We take the highest level set by the user: -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme We make sure that invalid configurations are rejected: -cpu rv64,sv32=on # Can't enable 32-bit satp mode in 64-bit -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are # enabled We accept "redundant" configurations: -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme -cpu rv64,sv32=on,sv32=off # Linux will boot using sv57 scheme (the default) In addition, we now correctly set the device-tree entry 'mmu-type' using those new properties. Co-Developed-by: Ludovic Henry Signed-off-by: Ludovic Henry Signed-off-by: Alexandre Ghiti --- hw/riscv/virt.c | 19 ++-- target/riscv/cpu.c | 221 +++++++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 19 ++++ target/riscv/csr.c | 17 +++- 4 files changed, 262 insertions(+), 14 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 94ff2a1584..48d034a5f7 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -228,7 +228,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, int cpu; uint32_t cpu_phandle; MachineState *mc = MACHINE(s); - char *name, *cpu_name, *core_name, *intc_name; + uint8_t satp_mode_max; + char *name, *cpu_name, *core_name, *intc_name, *sv_name; for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { cpu_phandle = (*phandle)++; @@ -236,14 +237,14 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(mc->fdt, cpu_name); - if (riscv_feature(&s->soc[socket].harts[cpu].env, - RISCV_FEATURE_MMU)) { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", - (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); - } else { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", - "riscv,none"); - } + + satp_mode_max = satp_mode_max_from_map( + s->soc[socket].harts[cpu].cfg.satp_mode.map); + sv_name = g_strdup_printf("riscv,%s", + satp_mode_str(satp_mode_max, is_32_bit)); + qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", sv_name); + g_free(sv_name); + name = riscv_isa_string(&s->soc[socket].harts[cpu]); qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); g_free(name); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7181b34f86..1f0d040a80 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -27,6 +27,7 @@ #include "time_helper.h" #include "exec/exec-all.h" #include "qapi/error.h" +#include "qapi/visitor.h" #include "qemu/error-report.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" @@ -229,6 +230,85 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) env->vext_ver = vext_ver; } +static uint8_t satp_mode_from_str(const char *satp_mode_str) +{ + if (!strncmp(satp_mode_str, "sv32", 4)) { + return VM_1_10_SV32; + } + + if (!strncmp(satp_mode_str, "sv39", 4)) { + return VM_1_10_SV39; + } + + if (!strncmp(satp_mode_str, "sv48", 4)) { + return VM_1_10_SV48; + } + + if (!strncmp(satp_mode_str, "sv57", 4)) { + return VM_1_10_SV57; + } + + if (!strncmp(satp_mode_str, "sv64", 4)) { + return VM_1_10_SV64; + } + + g_assert_not_reached(); +} + +uint8_t satp_mode_max_from_map(uint32_t map) +{ + /* map here has at least one bit set, so no problem with clz */ + return 31 - __builtin_clz(map); +} + +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) +{ + if (is_32_bit) { + switch (satp_mode) { + case VM_1_10_SV32: + return "sv32"; + case VM_1_10_MBARE: + return "none"; + } + } else { + switch (satp_mode) { + case VM_1_10_SV64: + return "sv64"; + case VM_1_10_SV57: + return "sv57"; + case VM_1_10_SV48: + return "sv48"; + case VM_1_10_SV39: + return "sv39"; + case VM_1_10_MBARE: + return "none"; + } + } + + g_assert_not_reached(); +} + +static void set_satp_mode(RISCVCPU *cpu, const char *satp_mode_str) +{ + cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str(satp_mode_str)); +} + +static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit) +{ + /* + * If an mmu is present, the default satp mode is: + * - sv32 for 32-bit + * - sv57 for 64-bit + * Otherwise, it is mbare. + */ + + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { + set_satp_mode(cpu, is_32_bit ? "sv32" : "sv57"); + } else { + set_satp_mode(cpu, "mbare"); + } +} + static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; @@ -619,6 +699,53 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) } } +static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) +{ + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; + const char *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; + + /* Get rid of 32-bit/64-bit incompatibility */ + for (int i = 0; i < 16; ++i) { + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { + error_setg(errp, "satp_mode %s is not valid", + satp_mode_str(i, !rv32)); + return; + } + } + + /* + * Make sure the user did not ask for an invalid configuration as per + * the specification. + */ + if (!rv32) { + uint8_t satp_mode_max; + + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); + + for (int i = satp_mode_max - 1; i >= 0; --i) { + if (!(cpu->cfg.satp_mode.map & (1 << i)) && + (cpu->cfg.satp_mode.init & (1 << i)) && + valid_vm[i]) { + error_setg(errp, "cannot disable %s satp mode if %s " + "is enabled", satp_mode_str(i, false), + satp_mode_str(satp_mode_max, false)); + return; + } + } + } +} + +static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) +{ + Error *local_err = NULL; + + riscv_cpu_satp_mode_finalize(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } +} + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -919,6 +1046,55 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } #endif + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; + + if (cpu->cfg.satp_mode.map == 0) { + /* + * If unset by both the user and the cpu, we fallback to the default + * satp mode. + */ + if (cpu->cfg.satp_mode.init == 0) { + set_satp_mode_default(cpu, rv32); + } else { + /* + * Find the lowest level that was disabled and then enable the + * first valid level below which can be found in + * valid_vm_1_10_32/64. + */ + const char *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; + + for (int i = 0; i < 16; ++i) { + if (!(cpu->cfg.satp_mode.map & (1 << i)) && + (cpu->cfg.satp_mode.init & (1 << i)) && + valid_vm[i]) { + for (int j = i - 1; j >= 0; --j) { + if (valid_vm[j]) { + cpu->cfg.satp_mode.map |= (1 << j); + break; + } + } + break; + } + } + + /* + * The user actually init a satp mode but appears to be invalid + * (ex: "-cpu rv64,sv32=on,sv32=off"). Fallback to the default + * mode. + */ + if (cpu->cfg.satp_mode.map == 0) { + set_satp_mode_default(cpu, rv32); + } + } + } + + riscv_cpu_finalize_features(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + + riscv_cpu_register_gdb_regs_for_features(cs); qemu_init_vcpu(cs); @@ -927,6 +1103,49 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) mcc->parent_realize(dev, errp); } +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVSATPMap *satp_map = opaque; + uint8_t satp = satp_mode_from_str(name); + bool value; + + value = (satp_map->map & (1 << satp)); + + visit_type_bool(v, name, &value, errp); +} + +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVSATPMap *satp_map = opaque; + uint8_t satp = satp_mode_from_str(name); + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + satp_map->map = deposit32(satp_map->map, satp, 1, value); + satp_map->init |= 1 << satp; +} + +static void riscv_add_satp_mode_properties(Object *obj) +{ + RISCVCPU *cpu = RISCV_CPU(obj); + + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); +} + #ifndef CONFIG_USER_ONLY static void riscv_cpu_set_irq(void *opaque, int irq, int level) { @@ -1091,6 +1310,8 @@ static void register_cpu_props(Object *obj) for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } + + riscv_add_satp_mode_properties(obj); } static Property riscv_cpu_properties[] = { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f5609b62a2..0ffa1bcfd5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -27,6 +27,7 @@ #include "qom/object.h" #include "qemu/int128.h" #include "cpu_bits.h" +#include "qapi/qapi-types-common.h" #define TCG_GUEST_DEFAULT_MO 0 @@ -413,6 +414,17 @@ struct RISCVCPUClass { ResettablePhases parent_phases; }; +/* + * map is a 16-bit bitmap: the most significant set bit in map is the maximum + * satp mode that is supported. + * + * init is a 16-bit bitmap used to make sure the user selected a correct + * configuration as per the specification. + */ +typedef struct { + uint16_t map, init; +} RISCVSATPMap; + struct RISCVCPUConfig { bool ext_i; bool ext_e; @@ -488,6 +500,8 @@ struct RISCVCPUConfig { bool debug; bool short_isa_string; + + RISCVSATPMap satp_mode; }; typedef struct RISCVCPUConfig RISCVCPUConfig; @@ -794,9 +808,14 @@ enum riscv_pmu_event_idx { /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; +extern const char valid_vm_1_10_32[], valid_vm_1_10_64[]; + void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); +uint8_t satp_mode_max_from_map(uint32_t map); +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); + #endif /* RISCV_CPU_H */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0db2c233e5..6e27299761 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1117,12 +1117,12 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; static const target_ulong vsip_writable_mask = MIP_VSSIP; -static const char valid_vm_1_10_32[16] = { +const char valid_vm_1_10_32[16] = { [VM_1_10_MBARE] = 1, [VM_1_10_SV32] = 1 }; -static const char valid_vm_1_10_64[16] = { +const char valid_vm_1_10_64[16] = { [VM_1_10_MBARE] = 1, [VM_1_10_SV39] = 1, [VM_1_10_SV48] = 1, @@ -1211,10 +1211,17 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, static int validate_vm(CPURISCVState *env, target_ulong vm) { - if (riscv_cpu_mxl(env) == MXL_RV32) { - return valid_vm_1_10_32[vm & 0xf]; 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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH v5 10/11] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() Content-Language: en-US To: Bin Meng Cc: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng , Palmer Dabbelt References: <20230102115241.25733-1-dbarboza@ventanamicro.com> <20230102115241.25733-11-dbarboza@ventanamicro.com> <0ba72b27-0c3d-2d3d-adec-899717f40594@ventanamicro.com> From: Daniel Henrique Barboza In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 10:49:15 -0000 On 1/13/23 07:30, Bin Meng wrote: > On Fri, Jan 13, 2023 at 6:23 PM Daniel Henrique Barboza > wrote: >> >> >> On 1/13/23 04:16, Philippe Mathieu-Daudé wrote: >>> On 12/1/23 01:34, Alistair Francis wrote: >>>> On Mon, Jan 2, 2023 at 9:55 PM Daniel Henrique Barboza >>>> wrote: >>>>> The microchip_icicle_kit, sifive_u, spike and virt boards are now doing >>>>> the same steps when '-kernel' is used: >>>>> >>>>> - execute load_kernel() >>>>> - load init_rd() >>>>> - write kernel_cmdline >>>>> >>>>> Let's fold everything inside riscv_load_kernel() to avoid code >>>>> repetition. To not change the behavior of boards that aren't calling >>>>> riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and >>>>> allow these boards to opt out from initrd loading. >>>>> >>>>> Cc: Palmer Dabbelt >>>>> Signed-off-by: Daniel Henrique Barboza >>>>> --- >>>>> hw/riscv/boot.c | 22 +++++++++++++++++++--- >>>>> hw/riscv/microchip_pfsoc.c | 12 ++---------- >>>>> hw/riscv/opentitan.c | 2 +- >>>>> hw/riscv/sifive_e.c | 3 ++- >>>>> hw/riscv/sifive_u.c | 12 ++---------- >>>>> hw/riscv/spike.c | 11 +---------- >>>>> hw/riscv/virt.c | 12 ++---------- >>>>> include/hw/riscv/boot.h | 1 + >>>>> 8 files changed, 30 insertions(+), 45 deletions(-) >>>>> @@ -192,21 +194,35 @@ target_ulong riscv_load_kernel(MachineState *machine, >>>>> if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, >>>>> NULL, &kernel_load_base, NULL, NULL, 0, >>>>> EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { >>>>> - return kernel_load_base; >>>>> + kernel_entry = kernel_load_base; >>>> This breaks 32-bit Xvisor loading. It seems that for the 32-bit guest >>>> we get a value of 0xffffffff80000000. >>>> >>>> Previously the top bits would be lost as we return a target_ulong from >>>> this function, but with this change we pass the value >>>> 0xffffffff80000000 to riscv_load_initrd() which causes failures. >>>> >>>> This diff fixes the failure for me >>>> >>>> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c >>>> index 4888d5c1e0..f08ed44b97 100644 >>>> --- a/hw/riscv/boot.c >>>> +++ b/hw/riscv/boot.c >>>> @@ -194,7 +194,7 @@ target_ulong riscv_load_kernel(MachineState *machine, >>>> if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, >>>> NULL, &kernel_load_base, NULL, NULL, 0, >>>> EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { >>>> - kernel_entry = kernel_load_base; >>>> + kernel_entry = (target_ulong) kernel_load_base; >>>> goto out; >>>> } >>>> >>>> >>>> but I don't think that's the right fix. We should instead look at the >>>> CPU XLEN and drop the high bits if required. >>> Ah, that is what should be done in load_elf_ram_sym()'s missing >>> translate_fn() handler. >> Interesting. I'll try it again and re-send. >> > If that fixes the problem, it should be a separate patch. Fair enough. I'll keep this patch as is and fix it in a separated patch. Daniel > > I still don't understand why 32-bit xvisor image has a 64-bit address encoded? > > Regards, > Bin From MAILER-DAEMON Fri Jan 13 07:57:09 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pGJcL-0008AO-2W for mharc-qemu-riscv@gnu.org; Fri, 13 Jan 2023 07:57:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGJcJ-0008AD-Ct for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 07:57:07 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGJcH-000227-Az for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 07:57:07 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E77D861A69; Fri, 13 Jan 2023 12:57:03 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 867CCC433D2; Fri, 13 Jan 2023 12:57:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673614623; bh=wCJ/S3iFoqSUJG0SoJig84YphylbsgMs7DTrMA8CTbY=; h=Date:From:To:CC:Subject:In-Reply-To:References:From; b=aQPq123Xbu70FmbdC7YjooRaqp/EVph+d8yQZmS/7gxeLEEf3tIyyx6n17q9cPAU+ M1ZXW7zdvdHj9fsy1EJ01IlQnm8a1gI+xKnwqU6ko41SLKISEba2dQECmJmkvhBQVX ihZTiFoh1EBclRknRPylcV8d8VLg9chju6rjHbVOeMm5iOoRRjTW/laL5MpWjZUXas jxMSRJyZK/5CjS7Y1zDUcPChhQdDBCttOWZ4RKBPr2AF86kH/6ruzD2nO6r+k9E88o cwSQmzrHpm8DicKoENQBPGksQZ3ARdDGVWkgXutJuY6gwCnLwjlcIOfEMxX7ViSJjs evAwBvomE3O/A== Date: Fri, 13 Jan 2023 12:56:57 +0000 From: Conor Dooley To: Bin Meng CC: stage TC , qemu-riscv@nongnu.org Subject: Re: qemu icicle kit es User-Agent: K-9 Mail for Android In-Reply-To: References: Message-ID: <2882065D-831B-4E8C-BFD3-677BB8ECA2AD@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=139.178.84.217; envelope-from=conor@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 12:57:07 -0000 On 13 January 2023 00:35:11 GMT, Bin Meng wrote: >On Fri, Jan 13, 2023 at 2:03 AM Conor Dooley wrote: >> >> +CC Bin Meng >> >> Bin Meng, you're listed as a supporter (in master anyway) but is that >> still accurate? I figure there's a good chance it isn't anymore? >> Have you tested the platform from HSS init at all lately? > >Yes, I am still maintaining the QEMU PolarFire SoC=2E The WiKi page >listed the exact HSS version I tested and if it doesn't, it should be >a regression in QEMU=2E If yes, I would like to have a look at that=2E That'd be great=2E I submitted a few patches for fixing the direct kernel boot & hopefully ha= ven't broken anything! I'll try to test it also, if I get some time=2E >Running more recent HSS is known to break, because QEMU does not >follow up quite closely with the HSS implementation as HSS has evolved >quite quickly in the past=2E Yeah, although the rate of change has slowed down now=2E I think there's a decent but of emulation missing though to get a recent v= ersion of the HSS working=2E Thanks, Conor=2E From MAILER-DAEMON Fri Jan 13 12:18:18 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pGNh3-0001Sv-PG for mharc-qemu-riscv@gnu.org; Fri, 13 Jan 2023 12:18:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGNgz-0001Qq-Sr for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 12:18:15 -0500 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pGNgx-0001JG-Nl for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 12:18:13 -0500 Received: by mail-ot1-x342.google.com with SMTP id f88-20020a9d03e1000000b00684c4041ff1so2874128otf.8 for ; Fri, 13 Jan 2023 09:18:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=hJBrxLI6QmmeeITsOzUvZaX/VcVW/UkeGDy9RzOvnNw=; b=bi+he8/9ip9JE8Do8cE3WvPHlrPyDBRdi5m51xCgYTEA+EHeKD3bmlDRQRdd7E4Clr OofxQVk3yqV2DjPg4BIsqBMU++23/TJNvf8usEJdHcfa/5Fw0LqasV7HIVHnS/drt8LV WC5gaBm3Mr0AJ6IcMaRw9cCknkSd4ol8RzsWu6RU0HalWxhbn5E20cHKjthMz96tO0fv oVw/XJrOF/XgPDii1E5TIiSxAKbH5/EibId8aUQBuqvvAlKsCm1X5PZo+mw0+w4SmvoS lieCDqQKREoaQ6BcdywyUb7o2VcZG+QnO6tEkKnS1gzuYemSrg1OZrrvXQtips9aPk+B tvGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=hJBrxLI6QmmeeITsOzUvZaX/VcVW/UkeGDy9RzOvnNw=; b=Ilf1BTK0ygK5CS6wZUFU7q8zVbq95zdsd/g8SWH4SdBIianzV3NQQS9e27Zk3gZtEa HYExTNAJ3+DazAq3BgHHZsUr3qLIlkIWfeKo0cIHtJH2J+/QuCOsecGfwOOIfWqP8jIU RC8xKXpwwaw+Nbg2cXNbONe2vKsF7+e4gurH5BeWqymXGErXUKHVeHxy5qYFJAMFjncd 0JvJqSWinQy5Qs6uCd5YFIfOdOe40kQk9UccAdqAkqTr4dzEmHr3bfkiFddrbO0i/DCq HGdT4UC+HYa2SPvPc2ECH4H1jtwOuUTTdJIfqs80Gsato8WntEPFEWRbD9KvjLK0xCnp yMYw== X-Gm-Message-State: AFqh2kpWVnpF1nV8026KHFAHDcCp6MpPTcq/3E1o9ocLV5ek+flO1r4h XmL8XKGpFHrMLWt5hYOF4Q0x8g== X-Google-Smtp-Source: AMrXdXtJk8eyNnj5qxKu3U5oACPJ+Vp67zXOx7zqHqf5goEV3gqJ4UBcpG+1/yVVart/iWYjfato8Q== X-Received: by 2002:a9d:6451:0:b0:684:c8ff:8844 with SMTP id m17-20020a9d6451000000b00684c8ff8844mr2588992otl.12.1673630290203; Fri, 13 Jan 2023 09:18:10 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id v25-20020a05683011d900b00683e4084740sm10695872otq.10.2023.01.13.09.18.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 09:18:09 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v7 0/3] hw/riscv: clear kernel_entry high bits with 32bit CPUs Date: Fri, 13 Jan 2023 14:18:02 -0300 Message-Id: <20230113171805.470252-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::342; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 17:18:15 -0000 Hi, In this version I followed Bin Meng's suggestion and reverted patch 1 back from what it was in the v5, acks included, and added a new patch (3) to fix the problem detected with the Xvisor use case. I believe this reflects that there is nothing particularly wrong with what we did in the v5 patch and we're going an extra mile to fix what, at first glance, is a bug somewhere else. In patch 3 I also followed Phil's idea and used a translate_fn() callback to do the bit clearing. Changes from v6: - patch 1: - restored to the state it was in v5, acks included - patch 3 (new): - clear the higher bits from the result of load_elf_ram_sym() using a translate_fn() callback for 32 bit CPUs v6 link: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02630.html Daniel Henrique Barboza (3): hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() hw/riscv/boot.c: make riscv_load_initrd() static hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym() hw/riscv/boot.c | 111 ++++++++++++++++++++++++------------- hw/riscv/microchip_pfsoc.c | 12 +--- hw/riscv/opentitan.c | 3 +- hw/riscv/sifive_e.c | 4 +- hw/riscv/sifive_u.c | 12 +--- hw/riscv/spike.c | 13 +---- hw/riscv/virt.c | 12 +--- include/hw/riscv/boot.h | 3 +- 8 files changed, 89 insertions(+), 81 deletions(-) -- 2.39.0 From MAILER-DAEMON Fri Jan 13 12:18:26 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pGNhC-0001gN-Pa for mharc-qemu-riscv@gnu.org; Fri, 13 Jan 2023 12:18:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGNh2-0001S7-7i for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 12:18:16 -0500 Received: from mail-ot1-x335.google.com ([2607:f8b0:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pGNh0-0001Ju-4b for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 12:18:15 -0500 Received: by mail-ot1-x335.google.com with SMTP id v15-20020a9d69cf000000b006709b5a534aso12564167oto.11 for ; Fri, 13 Jan 2023 09:18:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TC3+HEkqoyLKCQZFIMQ4soj6fRNa9o31XWX9UANzsT4=; b=EY0xOLiCeIeVgYgy0ufpUrU1/thogjzve78OPTumIVxgL3mDwx2HtUODaZQu6wLDlX pYPqnl/oiYBIPgAjCfxiOa9dRC/JBPVpsOsFzx7lmb/JPw5EbAvJM9Jlf7UroWpnppGs lMZkZkjqTFf+FWoWmrzdyNVWRzDYJEiUFQm6gVW7Gti17tIP7cII7JpKv3CnfRsdEAts 1uLTSD7M2R2GXJhVKckpGxLeAYBvmJwrZlClrEs3ooQe6mE8+R0CFFNZCWJo4HvKYLt2 wk6tk6z8mVyy+BTddiHAqdZRriDM5aZrw+j1dHbEvI+W7+iRSd5fcv5bWLOjQeOR6VJz xZyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TC3+HEkqoyLKCQZFIMQ4soj6fRNa9o31XWX9UANzsT4=; b=2xGVR3Qvv+y+dZ3fRNCbJThveI2i3rT8EJ4ubWwi7hx3XSkoX/9q+Dv2DHEM3K2NQ/ MK03H8C1gO1+m6JLl25SELRSONnJp/YehYrVjTSHTxuL4QwIDwUysHJF+i9YOVoAXiv3 Z8WSFipcKPtcV/R6xrkeIeXcrsIv2tf4L4lxtBbYP39bitcaXane86TBQgdQAh0bpdzv d0vxPezF06Xx8EoQNEe4CBFqPDHdRsLFCgT/ZMUvF4rqUeaEtPlf9tNYrNdzDMEhm1/v J2l8KAgIhFO7u4yr49tgoFQqTPQJiiipxUbRzN10JIS2iOll27Hb9K4voeaTUz6DigMU 01iw== X-Gm-Message-State: AFqh2kowPFyAjuxvsmwoeMdFu7wz5k8YDbltI6Tx3WbcEHLSDH/jvc3R h/e0MTvLhuuxTV6o1M2WeD4tnQ== X-Google-Smtp-Source: AMrXdXvKXwRgGqA7vqbL3Ku3IEWptW3M4EuOm72mO+oEHWtaAHN29zvS0FZsre+kuWTj1uvnx2/eYw== X-Received: by 2002:a9d:1ea:0:b0:684:b26e:84ba with SMTP id e97-20020a9d01ea000000b00684b26e84bamr5675041ote.11.1673630292660; Fri, 13 Jan 2023 09:18:12 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id v25-20020a05683011d900b00683e4084740sm10695872otq.10.2023.01.13.09.18.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 09:18:12 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Palmer Dabbelt , Bin Meng Subject: [PATCH v7 1/3] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() Date: Fri, 13 Jan 2023 14:18:03 -0300 Message-Id: <20230113171805.470252-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230113171805.470252-1-dbarboza@ventanamicro.com> References: <20230113171805.470252-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 17:18:17 -0000 The microchip_icicle_kit, sifive_u, spike and virt boards are now doing the same steps when '-kernel' is used: - execute load_kernel() - load init_rd() - write kernel_cmdline Let's fold everything inside riscv_load_kernel() to avoid code repetition. To not change the behavior of boards that aren't calling riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and allow these boards to opt out from initrd loading. Cc: Palmer Dabbelt Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 22 +++++++++++++++++++--- hw/riscv/microchip_pfsoc.c | 12 ++---------- hw/riscv/opentitan.c | 2 +- hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 12 ++---------- hw/riscv/spike.c | 11 +---------- hw/riscv/virt.c | 12 ++---------- include/hw/riscv/boot.h | 1 + 8 files changed, 30 insertions(+), 45 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 2594276223..4888d5c1e0 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -175,10 +175,12 @@ target_ulong riscv_load_firmware(const char *firmware_filename, target_ulong riscv_load_kernel(MachineState *machine, target_ulong kernel_start_addr, + bool load_initrd, symbol_fn_t sym_cb) { const char *kernel_filename = machine->kernel_filename; uint64_t kernel_load_base, kernel_entry; + void *fdt = machine->fdt; g_assert(kernel_filename != NULL); @@ -192,21 +194,35 @@ target_ulong riscv_load_kernel(MachineState *machine, if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL, &kernel_load_base, NULL, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { - return kernel_load_base; + kernel_entry = kernel_load_base; + goto out; } if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, NULL, NULL, NULL) > 0) { - return kernel_entry; + goto out; } if (load_image_targphys_as(kernel_filename, kernel_start_addr, current_machine->ram_size, NULL) > 0) { - return kernel_start_addr; + kernel_entry = kernel_start_addr; + goto out; } error_report("could not load kernel '%s'", kernel_filename); exit(1); + +out: + if (load_initrd && machine->initrd_filename) { + riscv_load_initrd(machine, kernel_entry); + } + + if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } + + return kernel_entry; } void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 82ae5e7023..c45023a2b1 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -629,16 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", - "bootargs", machine->kernel_cmdline); - } + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, + true, NULL); /* Compute the fdt load address in dram */ fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 64d5d435b9..f6fd9725a5 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -101,7 +101,7 @@ static void opentitan_board_init(MachineState *machine) } if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); + riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, false, NULL); } } diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 3e3f4b0088..6835d1c807 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL); + riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, + false, NULL); } } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index bac394c959..9a75d4aa62 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -598,16 +598,8 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, + true, NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index bff9475686..c517885e6e 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -308,16 +308,7 @@ static void spike_board_init(MachineState *machine) firmware_end_addr); kernel_entry = riscv_load_kernel(machine, kernel_start_addr, - htif_symbol_callback); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + true, htif_symbol_callback); } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c8e35f861e..a931ed05ab 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1281,16 +1281,8 @@ static void virt_machine_done(Notifier *notifier, void *data) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, + true, NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index f94653a09b..c3de897371 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -45,6 +45,7 @@ target_ulong riscv_load_firmware(const char *firmware_filename, symbol_fn_t sym_cb); target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, + bool load_initrd, symbol_fn_t sym_cb); void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); -- 2.39.0 From MAILER-DAEMON Fri Jan 13 12:18:28 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pGNhD-0001hh-Ur for mharc-qemu-riscv@gnu.org; Fri, 13 Jan 2023 12:18:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGNh6-0001U6-Ub for qemu-riscv@nongnu.org; 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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id v25-20020a05683011d900b00683e4084740sm10695872otq.10.2023.01.13.09.18.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 09:18:17 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v7 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym() Date: Fri, 13 Jan 2023 14:18:05 -0300 Message-Id: <20230113171805.470252-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230113171805.470252-1-dbarboza@ventanamicro.com> References: <20230113171805.470252-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::341; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x341.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 17:18:24 -0000 Recent hw/risc/boot.c changes caused a regression in an use case with the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel' stopped working. The reason seems to be that Xvisor is using 64 bit to encode the 32 bit addresses from the guest, and load_elf_ram_sym() is sign-extending the result with '1's [1]. This can very well be an issue with Xvisor, but since it's not hard to amend it in our side we're going for it. Use a translate_fn() callback to be called by load_elf_ram_sym() and clear the higher bits of the result if we're running a 32 bit CPU. [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html Suggested-by: Philippe Mathieu-Daudé Suggested-by: Bin Meng Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 23 ++++++++++++++++++++++- hw/riscv/microchip_pfsoc.c | 4 ++-- hw/riscv/opentitan.c | 3 ++- hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 4 ++-- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 4 ++-- include/hw/riscv/boot.h | 1 + 8 files changed, 34 insertions(+), 10 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index e868fb6ade..7f8295bf5e 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -213,7 +213,27 @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) } } +static uint64_t translate_kernel_address(void *opaque, uint64_t addr) +{ + RISCVHartArrayState *harts = opaque; + + /* + * For 32 bit CPUs, kernel_load_base is sign-extended (i.e. + * it can be padded with '1's) if the hypervisor, for some + * reason, is using 64 bit addresses with 32 bit guests. + * + * Clear the higher bits to avoid the padding if we're + * running a 32 bit CPU. + */ + if (riscv_is_32bit(harts)) { + return addr & 0x0fffffff; + } + + return addr; +} + target_ulong riscv_load_kernel(MachineState *machine, + RISCVHartArrayState *harts, target_ulong kernel_start_addr, bool load_initrd, symbol_fn_t sym_cb) @@ -231,7 +251,8 @@ target_ulong riscv_load_kernel(MachineState *machine, * the (expected) load address load address. This allows kernels to have * separate SBI and ELF entry points (used by FreeBSD, for example). */ - if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, + if (load_elf_ram_sym(kernel_filename, NULL, + translate_kernel_address, NULL, NULL, &kernel_load_base, NULL, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { kernel_entry = kernel_load_base; diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index c45023a2b1..b7e171b605 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -629,8 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, - true, NULL); + kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, + kernel_start_addr, true, NULL); /* Compute the fdt load address in dram */ fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index f6fd9725a5..1404a52da0 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -101,7 +101,8 @@ static void opentitan_board_init(MachineState *machine) } if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, false, NULL); + riscv_load_kernel(machine, &s->soc.cpus, + memmap[IBEX_DEV_RAM].base, false, NULL); } } diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 6835d1c807..04939b60c3 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, + riscv_load_kernel(machine, &s->soc.cpus, + memmap[SIFIVE_E_DEV_DTIM].base, false, NULL); } } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9a75d4aa62..214430d40c 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -598,8 +598,8 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, - true, NULL); + kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, + kernel_start_addr, true, NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index c517885e6e..b3aac2178b 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -307,7 +307,7 @@ static void spike_board_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, + kernel_entry = riscv_load_kernel(machine, &s->soc[0], kernel_start_addr, true, htif_symbol_callback); } else { /* diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index a931ed05ab..60c8729b5f 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1281,8 +1281,8 @@ static void virt_machine_done(Notifier *notifier, void *data) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, - true, NULL); + kernel_entry = riscv_load_kernel(machine, &s->soc[0], + kernel_start_addr, true, NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index cbd131bad7..bc9faed397 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -44,6 +44,7 @@ target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr, symbol_fn_t sym_cb); target_ulong riscv_load_kernel(MachineState *machine, + RISCVHartArrayState *harts, target_ulong firmware_end_addr, bool load_initrd, symbol_fn_t sym_cb); -- 2.39.0 From MAILER-DAEMON Fri Jan 13 12:18:28 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pGNhE-0001hl-3J for mharc-qemu-riscv@gnu.org; Fri, 13 Jan 2023 12:18:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGNh5-0001Ta-4g for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 12:18:24 -0500 Received: from mail-oa1-x32.google.com ([2001:4860:4864:20::32]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pGNh2-0001KS-LQ for qemu-riscv@nongnu.org; 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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id v25-20020a05683011d900b00683e4084740sm10695872otq.10.2023.01.13.09.18.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 09:18:14 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v7 2/3] hw/riscv/boot.c: make riscv_load_initrd() static Date: Fri, 13 Jan 2023 14:18:04 -0300 Message-Id: <20230113171805.470252-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230113171805.470252-1-dbarboza@ventanamicro.com> References: <20230113171805.470252-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 17:18:24 -0000 The only remaining caller is riscv_load_kernel_and_initrd() which belongs to the same file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng --- hw/riscv/boot.c | 80 ++++++++++++++++++++--------------------- include/hw/riscv/boot.h | 1 - 2 files changed, 40 insertions(+), 41 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 4888d5c1e0..e868fb6ade 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -173,6 +173,46 @@ target_ulong riscv_load_firmware(const char *firmware_filename, exit(1); } +static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) +{ + const char *filename = machine->initrd_filename; + uint64_t mem_size = machine->ram_size; + void *fdt = machine->fdt; + hwaddr start, end; + ssize_t size; + + g_assert(filename != NULL); + + /* + * We want to put the initrd far enough into RAM that when the + * kernel is uncompressed it will not clobber the initrd. However + * on boards without much RAM we must ensure that we still leave + * enough room for a decent sized initrd, and on boards with large + * amounts of RAM we must avoid the initrd being so far up in RAM + * that it is outside lowmem and inaccessible to the kernel. + * So for boards with less than 256MB of RAM we put the initrd + * halfway into RAM, and for boards with 256MB of RAM or more we put + * the initrd at 128MB. + */ + start = kernel_entry + MIN(mem_size / 2, 128 * MiB); + + size = load_ramdisk(filename, start, mem_size - start); + if (size == -1) { + size = load_image_targphys(filename, start, mem_size - start); + if (size == -1) { + error_report("could not load ramdisk '%s'", filename); + exit(1); + } + } + + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ + if (fdt) { + end = start + size; + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); + } +} + target_ulong riscv_load_kernel(MachineState *machine, target_ulong kernel_start_addr, bool load_initrd, @@ -225,46 +265,6 @@ out: return kernel_entry; } -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) -{ - const char *filename = machine->initrd_filename; - uint64_t mem_size = machine->ram_size; - void *fdt = machine->fdt; - hwaddr start, end; - ssize_t size; - - g_assert(filename != NULL); - - /* - * We want to put the initrd far enough into RAM that when the - * kernel is uncompressed it will not clobber the initrd. However - * on boards without much RAM we must ensure that we still leave - * enough room for a decent sized initrd, and on boards with large - * amounts of RAM we must avoid the initrd being so far up in RAM - * that it is outside lowmem and inaccessible to the kernel. - * So for boards with less than 256MB of RAM we put the initrd - * halfway into RAM, and for boards with 256MB of RAM or more we put - * the initrd at 128MB. - */ - start = kernel_entry + MIN(mem_size / 2, 128 * MiB); - - size = load_ramdisk(filename, start, mem_size - start); - if (size == -1) { - size = load_image_targphys(filename, start, mem_size - start); - if (size == -1) { - error_report("could not load ramdisk '%s'", filename); - exit(1); - } - } - - /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ - if (fdt) { - end = start + size; - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); - } -} - uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) { uint64_t temp, fdt_addr; diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index c3de897371..cbd131bad7 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -47,7 +47,6 @@ target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, bool load_initrd, symbol_fn_t sym_cb); -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr, -- 2.39.0 From MAILER-DAEMON Fri Jan 13 12:52:44 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pGOEM-0000zJ-JQ for mharc-qemu-riscv@gnu.org; Fri, 13 Jan 2023 12:52:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGOEK-0000ty-0Q for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 12:52:40 -0500 Received: from mail-oi1-x244.google.com ([2607:f8b0:4864:20::244]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pGOEH-0001Xc-GB for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 12:52:38 -0500 Received: by mail-oi1-x244.google.com with SMTP id r130so18266016oih.2 for ; Fri, 13 Jan 2023 09:52:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=sxp+GM5ymPv6TyvkEfOVeU9wh4EBckYHO6VlmxtLwwQ=; b=W3/jNkNoP1yswlxOKBBSpZ4by/K4sh5PxE0QUkXnn8DER2vDe8s2mqypFYdxz7NIsY xZaiFoIjtEgTP2Db3migiXHXH/uxnwDhdRYHeN9pp/y6HM0pHqlBsO13OUdoIxHzDo/i 2kguM0+EPL+JyJGLQMSM+9g7TNpM+1Lv3TINTDwPA4Ksjz00BeEgzBpZP4rniUb9Pb9q nS8t4/IUecZhOjFJlZNq833lea6jeH/Cxx6KmbE5vo8pCpbwi/wpVNtTYq1Gm2GIeBSV mCi+LwzpoNipYEuiFnJKVyn5gE/1Zak9UvbJULZ34HO/wYW3hx8Jn1/fS49l+pozxr0J PIlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=sxp+GM5ymPv6TyvkEfOVeU9wh4EBckYHO6VlmxtLwwQ=; b=01v31CZ/P8kpfCCAtngGhwZ70kkc8zYflLswwXLnfCL5RoArKx0zIKGtGnsUz7HRG2 7mrNz4D8jkJnBjuBlCbRfJTSQrhy467mTWPhyvRqsdDpSGnR28G3V9HiFTgirv2vofwc dlvMWq2uPK/tA43Nbdm+dASIIaxQJiC2sn6N5dCTR6/s0cmKvQQW24hRVgPgDuXjHUjK iAkLyeCkdYW2pj+8S5lPZsQa2uR44qdatAQYLx3WQL27cmsC+xI+9ou3UobfNPKrHKZe IU2nrUkziLuRrPLMWtM0YDTi/JZ5wll1QgaR5cDphmJf/CdSD/ev5hYO5KeDfUgEapfm ZKSw== X-Gm-Message-State: AFqh2koOComNt+Zc8iYA9NhQQzqX39E6dO0b+FXGGWyhBS1s9XIlK3T6 X6yb+hvLU/Qq6Z8ysyOLCvI3Qw== X-Google-Smtp-Source: AMrXdXsVcgC2kJbiG9atFWHOvQnLsLwMd7OGoMOTJoImoPzQvoVU4dm2uABhwsltgbHlqM++8QD3Uw== X-Received: by 2002:aca:2b04:0:b0:364:5f65:952a with SMTP id i4-20020aca2b04000000b003645f65952amr6600094oik.27.1673632356264; Fri, 13 Jan 2023 09:52:36 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id 2-20020aca0702000000b00363ea5be014sm9549276oih.3.2023.01.13.09.52.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 09:52:35 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng.cn@gmail.com, Daniel Henrique Barboza Subject: [PATCH v2 0/2] target/riscv/cpu: fix sifive_u 32/64bits boot in riscv-to-apply.next Date: Fri, 13 Jan 2023 14:52:28 -0300 Message-Id: <20230113175230.473975-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::244; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x244.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 17:52:40 -0000 Hi, In this version I fixed the commit message typos pointed by Bin. I've also added some notes about the code repetition the fix is introducing in the cpu_init() functions. The patches are based on riscv-to-apply.next at c1e76da3e668 ("target/riscv/cpu.c: Fix elen check"). Changes from v1: - patch 1: - fixed commit message typos v1 review: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02035.html Daniel Henrique Barboza (2): target/riscv/cpu: set cpu->cfg in register_cpu_props() target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() target/riscv/cpu.c | 439 +++++++++++++++++++++++++-------------------- target/riscv/cpu.h | 4 + 2 files changed, 249 insertions(+), 194 deletions(-) -- 2.39.0 From MAILER-DAEMON Fri Jan 13 12:52:57 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pGOEb-0001HP-5Z for mharc-qemu-riscv@gnu.org; Fri, 13 Jan 2023 12:52:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGOEN-000105-MC for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 12:52:43 -0500 Received: from mail-oi1-x22a.google.com ([2607:f8b0:4864:20::22a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pGOEK-0001YB-PP for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 12:52:43 -0500 Received: by mail-oi1-x22a.google.com with SMTP id r9so7503816oie.13 for ; Fri, 13 Jan 2023 09:52:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DOI8/iNH0q6l/+yMdTICroh3zdczF3J2qooInPAT9oE=; b=RVBiQun9XRl8KInbmhhawpk6XxxloM0jX+ADLqXprtKLR0Ih7x0dkeRU2B9BRHmvXr wDrS8gBiLOBkbiXnXoqZoTeSeW+cPxchsT8LgaWwMte274DKv7NFBBadIB9IEyPK+2+j Zj3xi/3p20H/93sIhLBht7CiBNLG3u8+WIjPbPRsCg3ZVDHLB4oQnuVQiBYhRMLvTa9k oSm2tmMeGh4kOpAAQc48R/zo8lc0kBoqByqqhyicoP6StyxShiqAv4qtAF/otYtj9q86 ptSy2DzIOnPo2v25ZoOCB2EtN1AeUUFzrmaBlYSPkPQKFY3n0/4t1VNJDlhDyigLnKTv zg8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DOI8/iNH0q6l/+yMdTICroh3zdczF3J2qooInPAT9oE=; b=ga+rCuz4W2VDOogUyZQFSjPAnnzsAx6C9pD5iSsj16/icHcAWfVAkRZqPd/5YICeDy GKRNfNzwXj5vL7YzhybyfFYEJ6BBbimXBeyvwMhQBHxhBrl61N0Z2q2Z16Hc2xv07EPo ppPesyOvbP6ybHIRqzcR/xpPxrdWwYIm6sZZqDwYCZ35oYA/mwApM8H3ylrG98qFB+aw 148kaodqdv1T6NydUXylSu6zY0VIZs0LhULiTcHG56SjtmQUAWlqE4kB0nFTFnZETlDB RoGql514dfMFwneyHkDSH/GfXFh+qVhzpTglYKnmwA13Wgiy5jYjRJZT3jC28Ukvau/I /lHQ== X-Gm-Message-State: AFqh2krCcEeI+/MeXPNsuAw/42nMKVMYZsNRTEvpmoR336f0cZEzcMLS 3OpZIuNtYcjUdDPo9tPkK8YroQ== X-Google-Smtp-Source: AMrXdXs6o9QIBwQamHhUW5EiVMXRubpJdXKLlkWI2pkOP4cu61snHCusURQIa0jtCdPFh5aA3zFXcA== X-Received: by 2002:a05:6808:238f:b0:360:d951:28bf with SMTP id bp15-20020a056808238f00b00360d95128bfmr7025696oib.19.1673632359407; Fri, 13 Jan 2023 09:52:39 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id 2-20020aca0702000000b00363ea5be014sm9549276oih.3.2023.01.13.09.52.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 09:52:38 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng.cn@gmail.com, Daniel Henrique Barboza Subject: [PATCH v2 1/2] target/riscv/cpu: set cpu->cfg in register_cpu_props() Date: Fri, 13 Jan 2023 14:52:29 -0300 Message-Id: <20230113175230.473975-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230113175230.473975-1-dbarboza@ventanamicro.com> References: <20230113175230.473975-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 17:52:46 -0000 There is an informal contract between the cpu_init() functions and riscv_cpu_realize(): if cpu->env.misa_ext is zero, assume that the default settings were loaded via register_cpu_props() and do validations to set env.misa_ext. If it's not zero, skip this whole process and assume that the board somehow did everything. At this moment, all SiFive CPUs are setting a non-zero misa_ext during their cpu_init() and skipping a good chunk of riscv_cpu_realize(). This causes problems when the code being skipped in riscv_cpu_realize() contains fixes or assumptions that affects all CPUs, meaning that SiFive CPUs are missing out. To allow this code to not be skipped anymore, all the cpu->cfg.ext_* attributes needs to be set during cpu_init() time. At this moment this is being done in register_cpu_props(). The SiFive boards are setting their own extensions during cpu_init() though, meaning that they don't want all the defaults from register_cpu_props(). Let's move the contract between *_cpu_init() and riscv_cpu_realize() to register_cpu_props(). Inside this function we'll check if cpu->env.misa_ext was set and, if that's the case, set all relevant cpu->cfg.ext_* attributes, and only that. Leave the 'misa_ext' = 0 case as is today, i.e. loading all the defaults from riscv_cpu_extensions[]. register_cpu_props() can then be called by all the cpu_init() functions, including the SiFive ones. This will make all CPUs behave more in line with what riscv_cpu_realize() expects. This will also make the cpu_init() functions even more alike, but at this moment we would need some design changes in how we're initializing extensions/attributes (e.g. some CPUs are setting cfg options after register_cpu_props(), so we can't simply add the function to a common post_init() hook) to make a common cpu_init() code across all CPUs. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 40 ++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 4 ++++ 2 files changed, 44 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a2e6238bd7..e682102c2a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -256,6 +256,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); } @@ -265,6 +266,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; } @@ -299,6 +301,7 @@ static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); } @@ -308,6 +311,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; } @@ -318,6 +322,7 @@ static void rv32_ibex_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.mmu = false; cpu->cfg.epmp = true; @@ -329,6 +334,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); + register_cpu_props(DEVICE(obj)); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; } @@ -1083,10 +1089,44 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_END_OF_LIST(), }; +/* + * Register CPU props based on env.misa_ext. If a non-zero + * value was set, register only the required cpu->cfg.ext_* + * properties and leave. env.misa_ext = 0 means that we want + * all the default properties to be registered. + */ static void register_cpu_props(DeviceState *dev) { + RISCVCPU *cpu = RISCV_CPU(OBJECT(dev)); + uint32_t misa_ext = cpu->env.misa_ext; Property *prop; + /* + * If misa_ext is not zero, set cfg properties now to + * allow them to be read during riscv_cpu_realize() + * later on. + */ + if (cpu->env.misa_ext != 0) { + cpu->cfg.ext_i = misa_ext & RVI; + cpu->cfg.ext_e = misa_ext & RVE; + cpu->cfg.ext_m = misa_ext & RVM; + cpu->cfg.ext_a = misa_ext & RVA; + cpu->cfg.ext_f = misa_ext & RVF; + cpu->cfg.ext_d = misa_ext & RVD; + cpu->cfg.ext_v = misa_ext & RVV; + cpu->cfg.ext_c = misa_ext & RVC; + cpu->cfg.ext_s = misa_ext & RVS; + cpu->cfg.ext_u = misa_ext & RVU; + cpu->cfg.ext_h = misa_ext & RVH; + cpu->cfg.ext_j = misa_ext & RVJ; + + /* + * We don't want to set the default riscv_cpu_extensions + * in this case. + */ + return; + } + for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 61a9a40958..bcf0826753 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -63,6 +63,10 @@ #define RV(x) ((target_ulong)1 << (x - 'A')) +/* + * Consider updating register_cpu_props() when adding + * new MISA bits here. + */ #define RVI RV('I') #define RVE RV('E') /* E and I are mutually exclusive */ #define RVM RV('M') -- 2.39.0 From MAILER-DAEMON Fri Jan 13 12:52:57 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pGOEb-0001I7-Ay for mharc-qemu-riscv@gnu.org; Fri, 13 Jan 2023 12:52:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGOEQ-000140-21 for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 12:52:47 -0500 Received: from mail-oi1-x22d.google.com ([2607:f8b0:4864:20::22d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pGOEN-0001Yt-JZ for qemu-riscv@nongnu.org; Fri, 13 Jan 2023 12:52:45 -0500 Received: by mail-oi1-x22d.google.com with SMTP id j130so18266816oif.4 for ; Fri, 13 Jan 2023 09:52:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+M3ohrTeofqSkxQ7pQ8d32nm7gQpOvTOJJgz+5YPODI=; b=I3Bqn2WaKfFzvTGHB1XDo+/dS7wrPeIblMrVgn7Ot7asibUjWTd07osgrAAD9XDaWS H0fbwOOd8sXVAiBdZRAmboUXZ7UnKwNgoN6Ypi0+zSZ/NkfCLiSAd+SarTRljGdwDupD xlBSbyALyUaygBe5TmNYZg9rGH3r6K45Dmp9p8usDPwZxC9hA3qhllfUQOUKqh6dZkdM ocbwVIBDM43qxVYy3Q0B+2Oww9wXopQg5ncTjEzJFGR+UYeM4M1SXDcqE2rYH9bjM5Iq oH+EoBQkyDfP5Ev94qDa5MScn5KEmBPy85QwTy/LjzI1IxJT6590E+oEPBLdMT7ldgZS P7aQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+M3ohrTeofqSkxQ7pQ8d32nm7gQpOvTOJJgz+5YPODI=; b=I8d6XA6A+iwFRG2pV5mCfnAMnk+4HPQLdr7eS5IChBiWr0ySXDXu5CaV7DQl/Rc8Ke iKrKDqVFRmE/RMAhTdGx0MlUTQCBBmJVIqunT2OYTYRLGMwWcieiPKX1vMSGPtieK8hD 9gESPxsOckOiAFiDE34R67Q7BOmfy7zb168Zjk7u5+vkpaAmfbgdt0Azi64if4VPF1Ze 4jeBRRKEq0VXkhjh4g1a4u/VuoZN/kM1DZJ3EDem3Xq/saURg5eeR24rte+W54fpQiNm A3L1tQl8Gsi0GZEfVTh/QAkmN44bYIo/i7nzUFgQiHRHLYEs+tiBh7TpMO+3fn3M1guj sCVg== X-Gm-Message-State: AFqh2kqg/+VquSf2TYQok+LUJNA21xqzydL+zI8YikJuyZyNRYyRpE6/ r4QAYgGnKJo6IQ8SZvlpg8o9Bg== X-Google-Smtp-Source: AMrXdXtKIeD/7iP4Pt8RPrlRQs3ONt642d3Zw3NxvfGwr+L25uqxIN3S4IzaiuV+x+x/hbmGEuYJgg== X-Received: by 2002:aca:ba08:0:b0:363:b22:6532 with SMTP id k8-20020acaba08000000b003630b226532mr33463790oif.7.1673632362225; Fri, 13 Jan 2023 09:52:42 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id 2-20020aca0702000000b00363ea5be014sm9549276oih.3.2023.01.13.09.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 09:52:41 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng.cn@gmail.com, Daniel Henrique Barboza Subject: [PATCH v2 2/2] target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() Date: Fri, 13 Jan 2023 14:52:30 -0300 Message-Id: <20230113175230.473975-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230113175230.473975-1-dbarboza@ventanamicro.com> References: <20230113175230.473975-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jan 2023 17:52:51 -0000 All RISCV CPUs are setting cpu->cfg during their cpu_init() functions, meaning that there's no reason to skip all the misa validation and setup if misa_ext was set beforehand - especially since we're setting an updated value in set_misa() in the end. Put this code chunk into a new riscv_cpu_validate_set_extensions() helper and always execute it regardless of what the board set in env->misa_ext. This will put more responsibility in how each board is going to init their attributes and extensions if they're not using the defaults. It'll also allow realize() to do its job looking only at the extensions enabled per se, not corner cases that some CPUs might have, and we won't have to change multiple code paths to fix or change how extensions work. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis [ Changes by AF: - Rebase ] Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 399 +++++++++++++++++++++++---------------------- 1 file changed, 205 insertions(+), 194 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e682102c2a..c192d96a94 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -625,6 +625,207 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) } } +/* + * Check consistency between chosen extensions while setting + * cpu->cfg accordingly, doing a set_misa() in the end. + */ +static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env = &cpu->env; + uint32_t ext = 0; + + /* Do some ISA extension error checking */ + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && + cpu->cfg.ext_a && cpu->cfg.ext_f && + cpu->cfg.ext_d && + cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { + warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); + cpu->cfg.ext_i = true; + cpu->cfg.ext_m = true; + cpu->cfg.ext_a = true; + cpu->cfg.ext_f = true; + cpu->cfg.ext_d = true; + cpu->cfg.ext_icsr = true; + cpu->cfg.ext_ifencei = true; + } + + if (cpu->cfg.ext_i && cpu->cfg.ext_e) { + error_setg(errp, + "I and E extensions are incompatible"); + return; + } + + if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { + error_setg(errp, + "Either I or E extension must be set"); + return; + } + + if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { + error_setg(errp, + "Setting S extension without U extension is illegal"); + return; + } + + if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { + error_setg(errp, + "H depends on an I base integer ISA with 32 x registers"); + return; + } + + if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { + error_setg(errp, "H extension implicitly requires S-mode"); + return; + } + + if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { + error_setg(errp, "F extension requires Zicsr"); + return; + } + + if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { + error_setg(errp, "Zawrs extension requires A extension"); + return; + } + + if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { + error_setg(errp, "Zfh/Zfhmin extensions require F extension"); + return; + } + + if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { + error_setg(errp, "D extension requires F extension"); + return; + } + + if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { + error_setg(errp, "V extension requires D extension"); + return; + } + + if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { + error_setg(errp, "Zve32f/Zve64f extensions require F extension"); + return; + } + + /* Set the ISA extensions, checks should have happened above */ + if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || + cpu->cfg.ext_zhinxmin) { + cpu->cfg.ext_zfinx = true; + } + + if (cpu->cfg.ext_zfinx) { + if (!cpu->cfg.ext_icsr) { + error_setg(errp, "Zfinx extension requires Zicsr"); + return; + } + if (cpu->cfg.ext_f) { + error_setg(errp, + "Zfinx cannot be supported together with F extension"); + return; + } + } + + if (cpu->cfg.ext_zk) { + cpu->cfg.ext_zkn = true; + cpu->cfg.ext_zkr = true; + cpu->cfg.ext_zkt = true; + } + + if (cpu->cfg.ext_zkn) { + cpu->cfg.ext_zbkb = true; + cpu->cfg.ext_zbkc = true; + cpu->cfg.ext_zbkx = true; + cpu->cfg.ext_zkne = true; + cpu->cfg.ext_zknd = true; + cpu->cfg.ext_zknh = true; + } + + if (cpu->cfg.ext_zks) { + cpu->cfg.ext_zbkb = true; + cpu->cfg.ext_zbkc = true; + cpu->cfg.ext_zbkx = true; + cpu->cfg.ext_zksed = true; + cpu->cfg.ext_zksh = true; + } + + if (cpu->cfg.ext_i) { + ext |= RVI; + } + if (cpu->cfg.ext_e) { + ext |= RVE; + } + if (cpu->cfg.ext_m) { + ext |= RVM; + } + if (cpu->cfg.ext_a) { + ext |= RVA; + } + if (cpu->cfg.ext_f) { + ext |= RVF; + } + if (cpu->cfg.ext_d) { + ext |= RVD; + } + if (cpu->cfg.ext_c) { + ext |= RVC; + } + if (cpu->cfg.ext_s) { + ext |= RVS; + } + if (cpu->cfg.ext_u) { + ext |= RVU; + } + if (cpu->cfg.ext_h) { + ext |= RVH; + } + if (cpu->cfg.ext_v) { + int vext_version = VEXT_VERSION_1_00_0; + ext |= RVV; + if (!is_power_of_2(cpu->cfg.vlen)) { + error_setg(errp, + "Vector extension VLEN must be power of 2"); + return; + } + if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { + error_setg(errp, + "Vector extension implementation only supports VLEN " + "in the range [128, %d]", RV_VLEN_MAX); + return; + } + if (!is_power_of_2(cpu->cfg.elen)) { + error_setg(errp, + "Vector extension ELEN must be power of 2"); + return; + } + if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { + error_setg(errp, + "Vector extension implementation only supports ELEN " + "in the range [8, 64]"); + return; + } + if (cpu->cfg.vext_spec) { + if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { + vext_version = VEXT_VERSION_1_00_0; + } else { + error_setg(errp, + "Unsupported vector spec version '%s'", + cpu->cfg.vext_spec); + return; + } + } else { + qemu_log("vector version is not specified, " + "use the default value v1.0\n"); + } + set_vext_version(env, vext_version); + } + if (cpu->cfg.ext_j) { + ext |= RVJ; + } + + set_misa(env, env->misa_mxl, ext); +} + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -720,200 +921,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } assert(env->misa_mxl_max == env->misa_mxl); - /* If only MISA_EXT is unset for misa, then set it from properties */ - if (env->misa_ext == 0) { - uint32_t ext = 0; - - /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && - cpu->cfg.ext_a && cpu->cfg.ext_f && - cpu->cfg.ext_d && - cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { - warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_i = true; - cpu->cfg.ext_m = true; - cpu->cfg.ext_a = true; - cpu->cfg.ext_f = true; - cpu->cfg.ext_d = true; - cpu->cfg.ext_icsr = true; - cpu->cfg.ext_ifencei = true; - } - - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { - error_setg(errp, - "I and E extensions are incompatible"); - return; - } - - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { - error_setg(errp, - "Either I or E extension must be set"); - return; - } - - if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { - error_setg(errp, - "Setting S extension without U extension is illegal"); - return; - } - - if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { - error_setg(errp, - "H depends on an I base integer ISA with 32 x registers"); - return; - } - - if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { - error_setg(errp, "H extension implicitly requires S-mode"); - return; - } - - if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { - error_setg(errp, "F extension requires Zicsr"); - return; - } - - if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { - error_setg(errp, "Zawrs extension requires A extension"); - return; - } - - if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { - error_setg(errp, "Zfh/Zfhmin extensions require F extension"); - return; - } - - if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { - error_setg(errp, "D extension requires F extension"); - return; - } - - if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { - error_setg(errp, "V extension requires D extension"); - return; - } - - if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { - error_setg(errp, "Zve32f/Zve64f extensions require F extension"); - return; - } - - /* Set the ISA extensions, checks should have happened above */ - if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || - cpu->cfg.ext_zhinxmin) { - cpu->cfg.ext_zfinx = true; - } - - if (cpu->cfg.ext_zfinx) { - if (!cpu->cfg.ext_icsr) { - error_setg(errp, "Zfinx extension requires Zicsr"); - return; - } - if (cpu->cfg.ext_f) { - error_setg(errp, - "Zfinx cannot be supported together with F extension"); - return; - } - } - - if (cpu->cfg.ext_zk) { - cpu->cfg.ext_zkn = true; - cpu->cfg.ext_zkr = true; - cpu->cfg.ext_zkt = true; - } - - if (cpu->cfg.ext_zkn) { - cpu->cfg.ext_zbkb = true; - cpu->cfg.ext_zbkc = true; - cpu->cfg.ext_zbkx = true; - cpu->cfg.ext_zkne = true; - cpu->cfg.ext_zknd = true; - cpu->cfg.ext_zknh = true; - } - - if (cpu->cfg.ext_zks) { - cpu->cfg.ext_zbkb = true; - cpu->cfg.ext_zbkc = true; - cpu->cfg.ext_zbkx = true; - cpu->cfg.ext_zksed = true; - cpu->cfg.ext_zksh = true; - } - - if (cpu->cfg.ext_i) { - ext |= RVI; - } - if (cpu->cfg.ext_e) { - ext |= RVE; - } - if (cpu->cfg.ext_m) { - ext |= RVM; - } - if (cpu->cfg.ext_a) { - ext |= RVA; - } - if (cpu->cfg.ext_f) { - ext |= RVF; - } - if (cpu->cfg.ext_d) { - ext |= RVD; - } - if (cpu->cfg.ext_c) { - ext |= RVC; - } - if (cpu->cfg.ext_s) { - ext |= RVS; - } - if (cpu->cfg.ext_u) { - ext |= RVU; - } - if (cpu->cfg.ext_h) { - ext |= RVH; - } - if (cpu->cfg.ext_v) { - int vext_version = VEXT_VERSION_1_00_0; - ext |= RVV; - if (!is_power_of_2(cpu->cfg.vlen)) { - error_setg(errp, - "Vector extension VLEN must be power of 2"); - return; - } - if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { - error_setg(errp, - "Vector extension implementation only supports VLEN " - "in the range [128, %d]", RV_VLEN_MAX); - return; - } - if (!is_power_of_2(cpu->cfg.elen)) { - error_setg(errp, - "Vector extension ELEN must be power of 2"); - return; - } - if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { - error_setg(errp, - "Vector extension implementation only supports ELEN " - "in the range [8, 64]"); - return; - } - if (cpu->cfg.vext_spec) { - if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { - vext_version = VEXT_VERSION_1_00_0; - } else { - error_setg(errp, - "Unsupported vector spec version '%s'", - cpu->cfg.vext_spec); - return; - } - } else { - qemu_log("vector version is not specified, " - "use the default value v1.0\n"); - } - set_vext_version(env, vext_version); - } - if (cpu->cfg.ext_j) { - ext |= RVJ; - } - - set_misa(env, env->misa_mxl, ext); + riscv_cpu_validate_set_extensions(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; } #ifndef CONFIG_USER_ONLY -- 2.39.0 From MAILER-DAEMON Sat Jan 14 08:40:41 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pGgm0-0001GJ-Cx for mharc-qemu-riscv@gnu.org; Sat, 14 Jan 2023 08:40:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGgly-0001Fn-D8; Sat, 14 Jan 2023 08:40:38 -0500 Received: from mail-ej1-x633.google.com ([2a00:1450:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pGglw-0006GC-9J; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Jan 2023 13:40:38 -0000 On Sat, Jan 14, 2023 at 1:18 AM Daniel Henrique Barboza wrote: > > Recent hw/risc/boot.c changes caused a regression in an use case with > the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel' > stopped working. The reason seems to be that Xvisor is using 64 bit to > encode the 32 bit addresses from the guest, and load_elf_ram_sym() is > sign-extending the result with '1's [1]. I would say it's not a regression of QEMU but something weird happened to Alistair's 32-bit Xvisor image. I just built a 32-bit Xvisor image from the latest Xvisor head following the instructions provided in its source tree. With the mainline QEMU only BIN file boots, but ELF does not. My 32-bit Xvisor image has an address of 0x10000000. Apparently this address is not correct, and the issue I saw is different from Alistair's. Alistair, could you investigate why your 32-bit Xvisor ELF image has an address of 0xffffffff80000000 set to kernel_load_base? > > This can very well be an issue with Xvisor, but since it's not hard to > amend it in our side we're going for it. Use a translate_fn() callback > to be called by load_elf_ram_sym() and clear the higher bits of the > result if we're running a 32 bit CPU. > > [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html > > Suggested-by: Philippe Mathieu-Daud=C3=A9 > Suggested-by: Bin Meng > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/boot.c | 23 ++++++++++++++++++++++- > hw/riscv/microchip_pfsoc.c | 4 ++-- > hw/riscv/opentitan.c | 3 ++- > hw/riscv/sifive_e.c | 3 ++- > hw/riscv/sifive_u.c | 4 ++-- > hw/riscv/spike.c | 2 +- > hw/riscv/virt.c | 4 ++-- > include/hw/riscv/boot.h | 1 + > 8 files changed, 34 insertions(+), 10 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index e868fb6ade..7f8295bf5e 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -213,7 +213,27 @@ static void riscv_load_initrd(MachineState *machine,= uint64_t kernel_entry) > } > } > > +static uint64_t translate_kernel_address(void *opaque, uint64_t addr) > +{ > + RISCVHartArrayState *harts =3D opaque; > + > + /* > + * For 32 bit CPUs, kernel_load_base is sign-extended (i.e. > + * it can be padded with '1's) if the hypervisor, for some > + * reason, is using 64 bit addresses with 32 bit guests. > + * > + * Clear the higher bits to avoid the padding if we're > + * running a 32 bit CPU. > + */ > + if (riscv_is_32bit(harts)) { > + return addr & 0x0fffffff; > + } > + > + return addr; > +} > + > target_ulong riscv_load_kernel(MachineState *machine, > + RISCVHartArrayState *harts, > target_ulong kernel_start_addr, > bool load_initrd, > symbol_fn_t sym_cb) > @@ -231,7 +251,8 @@ target_ulong riscv_load_kernel(MachineState *machine, > * the (expected) load address load address. This allows kernels to = have > * separate SBI and ELF entry points (used by FreeBSD, for example). > */ > - if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, > + if (load_elf_ram_sym(kernel_filename, NULL, > + translate_kernel_address, NULL, > NULL, &kernel_load_base, NULL, NULL, 0, > EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { > kernel_entry =3D kernel_load_base; > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index c45023a2b1..b7e171b605 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -629,8 +629,8 @@ static void microchip_icicle_kit_machine_init(Machine= State *machine) > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpu= s, > firmware_end_ad= dr); > > - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, > - true, NULL); > + kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, > + kernel_start_addr, true, NULL); > > /* Compute the fdt load address in dram */ > fdt_load_addr =3D riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO]= .base, > diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c > index f6fd9725a5..1404a52da0 100644 > --- a/hw/riscv/opentitan.c > +++ b/hw/riscv/opentitan.c > @@ -101,7 +101,8 @@ static void opentitan_board_init(MachineState *machin= e) > } > > if (machine->kernel_filename) { > - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, false, NUL= L); > + riscv_load_kernel(machine, &s->soc.cpus, > + memmap[IBEX_DEV_RAM].base, false, NULL); > } > } > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > index 6835d1c807..04939b60c3 100644 > --- a/hw/riscv/sifive_e.c > +++ b/hw/riscv/sifive_e.c > @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machi= ne) > memmap[SIFIVE_E_DEV_MROM].base, &address_space= _memory); > > if (machine->kernel_filename) { > - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, > + riscv_load_kernel(machine, &s->soc.cpus, > + memmap[SIFIVE_E_DEV_DTIM].base, > false, NULL); > } > } > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 9a75d4aa62..214430d40c 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -598,8 +598,8 @@ static void sifive_u_machine_init(MachineState *machi= ne) > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpu= s, > firmware_end_ad= dr); > > - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, > - true, NULL); > + kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, > + kernel_start_addr, true, NULL); > } else { > /* > * If dynamic firmware is used, it doesn't know where is the next= mode > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index c517885e6e..b3aac2178b 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -307,7 +307,7 @@ static void spike_board_init(MachineState *machine) > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], > firmware_end_ad= dr); > > - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, > + kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], kernel_s= tart_addr, > true, htif_symbol_callback); > } else { > /* > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index a931ed05ab..60c8729b5f 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -1281,8 +1281,8 @@ static void virt_machine_done(Notifier *notifier, v= oid *data) > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], > firmware_end_ad= dr); > > - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, > - true, NULL); > + kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], > + kernel_start_addr, true, NULL); > } else { > /* > * If dynamic firmware is used, it doesn't know where is the next= mode > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h > index cbd131bad7..bc9faed397 100644 > --- a/include/hw/riscv/boot.h > +++ b/include/hw/riscv/boot.h > @@ -44,6 +44,7 @@ target_ulong riscv_load_firmware(const char *firmware_f= ilename, > hwaddr firmware_load_addr, > symbol_fn_t sym_cb); > target_ulong riscv_load_kernel(MachineState *machine, > + RISCVHartArrayState *harts, > target_ulong firmware_end_addr, > bool load_initrd, > symbol_fn_t sym_cb); Regards, Bin From MAILER-DAEMON Sat Jan 14 09:30:32 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pGhYG-0002jm-2i for mharc-qemu-riscv@gnu.org; Sat, 14 Jan 2023 09:30:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGhY8-0002hr-HZ for qemu-riscv@nongnu.org; Sat, 14 Jan 2023 09:30:26 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pGhY5-0005Dg-L1 for qemu-riscv@nongnu.org; Sat, 14 Jan 2023 09:30:23 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 4201660B42; Sat, 14 Jan 2023 14:30:11 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AAEB4C433EF; Sat, 14 Jan 2023 14:30:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1673706610; bh=Pl0+C9LzOQU3BhGL7BLYAYlyhYrGrlzHcNe6ifoW2W0=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=pRlmKKsWE7XHiZOd+oWm/ozhu77eAEccf3M44tctsq6uF22Z5aKSQ+xmvwFjntzyM ibxuW5vc/cVP8ngWjBdZnTUlkmOtcbokSTiVkeqChlRbnjw9ELY0sF6ReSmBFQWk7/ DUU6uWBujAbJxMGstnDnzJsWiqgl2Ku7KVMOzyHedRchAon0W9SGn9ExvtSWwjSwX5 mTOX0bKcCJWmIs6Qz/tKxwR4rmUfJ8468wjvG+J6WsKYmEkG0IfKdWKFyD8Y+x3Cp/ 7uilz+SEeqSqiEzpMokPg/A2N2ZJC84vzfRrjG4G9VYtll73zskXQyEyOV95frw+E8 6rPyZVEKDFUcA== Date: Sat, 14 Jan 2023 14:30:07 +0000 From: Conor Dooley To: Bin Meng Cc: stage TC , qemu-riscv@nongnu.org Subject: Re: qemu icicle kit es Message-ID: References: <2882065D-831B-4E8C-BFD3-677BB8ECA2AD@kernel.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="qaLxkvU7yOL0xQ3H" Content-Disposition: inline In-Reply-To: <2882065D-831B-4E8C-BFD3-677BB8ECA2AD@kernel.org> Received-SPF: pass client-ip=139.178.84.217; envelope-from=conor@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 14 Jan 2023 14:30:30 -0000 --qaLxkvU7yOL0xQ3H Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Jan 13, 2023 at 12:56:57PM +0000, Conor Dooley wrote: >=20 >=20 > On 13 January 2023 00:35:11 GMT, Bin Meng wrote: > >On Fri, Jan 13, 2023 at 2:03 AM Conor Dooley wrote: > >> > >> +CC Bin Meng > >> >=20 > >> Bin Meng, you're listed as a supporter (in master anyway) but is that > >> still accurate? I figure there's a good chance it isn't anymore? > >> Have you tested the platform from HSS init at all lately? > > > >Yes, I am still maintaining the QEMU PolarFire SoC. The WiKi page > >listed the exact HSS version I tested and if it doesn't, it should be > >a regression in QEMU. If yes, I would like to have a look at that. >=20 > That'd be great. > I submitted a few patches for fixing the direct kernel boot & hopefully > haven't broken anything! > I'll try to test it also, if I get some time. Gave 7.2.0 a go yesterday afternoon. The URL from the documentation is no longer accessible, I cannot wget the image! I'll try and find out what happened there, AFAIU that FTP is still in use, so dunno why that file doesn't seem to be there. I'll try to find out. I dug out the commit from the docs for the HSS, built that. Generated a payload using the nearest payload generator commit to that was compilable, which I passed as the image instead of the wic. The HSS would load, get as far as trying to extract the payload containing the next stage bootloader & fail. Specifically, it was complaining that the magic number for the payload was all zeros. Perhaps if you still have the original wic image you'll have more luck! Thanks, Conor. | qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \ | -bios path/to/hss.bin -sd path/to/sdcard.img \ | -nic user,model=3Dcadence_gem \ | -nic tap,ifname=3Dtap,model=3Dcadence_gem,script=3Dno \ | -display none -serial stdio \ | -chardev socket,id=3Dserial1,path=3Dserial1.sock,server=3Don,wait=3Do= n \ | -serial chardev:serial1 btw, I built my QEMU with `./configure --target-list=3Driscv64-softmmu && make`, and got a complaint from the above command that user mode NICs were not present in my QEMU. --qaLxkvU7yOL0xQ3H Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY8K8bwAKCRB4tDGHoIJi 0qnUAQCU28JUbzk5FXczBq7yOVcPEvvK618bEAS9SXf8NNhkLwD/cGvAg6fu/FDz TnKyv2v67T5gVTJun/YkvoitAHNs8wQ= =S6xP -----END PGP SIGNATURE----- --qaLxkvU7yOL0xQ3H-- From MAILER-DAEMON Sun Jan 15 11:07:18 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pH5XQ-0003v0-Jm for mharc-qemu-riscv@gnu.org; Sun, 15 Jan 2023 11:07:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pH5XH-0003tk-6G for qemu-riscv@nongnu.org; Sun, 15 Jan 2023 11:07:08 -0500 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pH5XD-0002ks-Da for qemu-riscv@nongnu.org; Sun, 15 Jan 2023 11:07:06 -0500 Received: by mail-pf1-x42c.google.com with SMTP id w2so3959158pfc.11 for ; Sun, 15 Jan 2023 08:07:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=GZTFHxNlAhNRHDbBvjazOuY2CHtPtEz62uheZE/u1Xc=; b=EJcatYdOLfY+WlTy6Cmxm4tivhdP4s9IgPDXWZi7S89mmohLtbgEO1T4mXXse1llW6 2tJR0DPvCEha7PDUSGRAztMGVAdx9lGsGL7Fjiu9kGL0g2vV83IeST49SndffxtyO2II G6FVQz4iYFnEa8YSldbaOr2fFagepzj0xUTvcHlEfQr8YcpdEgkUxrgpPZtd6e3nzgPW dbnZxDs4GniRq1WPa7xF9ToaOiqXQX8ge03Y6ukAJkSdQCH9Pma0JgRXoxlqWfuLCNvv +ae3Ju21UKwbmWAmInZ+xPeBbGnNNQjH6trGXcO0CZ+tJMGUJLR+By7ohdxtqKJ3//cN 252A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=GZTFHxNlAhNRHDbBvjazOuY2CHtPtEz62uheZE/u1Xc=; b=xgyttzuR+bDgVJJhpTzXVIkiw+5ZZBq5gdEJbCEGytEHXkK+xY5pM2MFpHDylAPfGk kFi2sqK/zatVHY0fVwbRUeynq5Gh7LukQTdC4NCg87qOj9sf4Q6GLyAsxSHcxwUrJaDG GKGiNBuW8GyHnvslwYnzYs9LPTgtS2Iwp0BB7lWzwHx7tv6J/BXO9RE7c6kek+gynbLQ 8UFIqhjYX6vQP3DQ32z4/4fzTIOERfEv2ZgcHxztO8hliljxZdYLYiTQNDf1uY/X01hz du9CfV7uRol5N9aMPjjekiEBmVsPhCTJjkonO/E1fD7kytZCx4TxdcckCYd2jEbXvDYT yOXw== X-Gm-Message-State: AFqh2konXyAXCoJQHu1WjqWevF/OTNJp9PeCEZj2YPNowg81U4GBRZf4 SDemiEj53bxDu46mVvlCkB4P/Q== X-Google-Smtp-Source: AMrXdXt1JiQNS04IGj+F/FyZyK57Ko3hRxGIC3Hm/2aWvMrY+3ktQx5h8CWp8rEXSmRSYVRg0iesTA== X-Received: by 2002:a05:6a00:1d95:b0:58d:aac3:a8cb with SMTP id z21-20020a056a001d9500b0058daac3a8cbmr633460pfw.0.1673798821246; Sun, 15 Jan 2023 08:07:01 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id c76-20020a624e4f000000b00589c467ed88sm11422735pfb.69.2023.01.15.08.06.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jan 2023 08:07:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bin.meng@windriver.com, abdulras@google.com Subject: [PATCH 0/2] target/riscv: Fix double calls to gen_set_rm [#1411] Date: Sun, 15 Jan 2023 06:06:55 -1000 Message-Id: <20230115160657.3169274-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 15 Jan 2023 16:07:11 -0000 These double calls tickle an assertion in decode_save_opc, and isn't efficient anyway. Introduce a new helper to do exactly what was desired. r~ Richard Henderson (2): target/arm: Introduce helper_set_rounding_mode_chkfrm target/riscv: Remove helper_set_rod_rounding_mode target/riscv/helper.h | 2 +- target/riscv/fpu_helper.c | 36 +++++++++++++++++++++++-- target/riscv/translate.c | 21 ++++++++++++--- target/riscv/insn_trans/trans_rvv.c.inc | 24 +++-------------- 4 files changed, 57 insertions(+), 26 deletions(-) -- 2.34.1 From MAILER-DAEMON Sun Jan 15 11:07:29 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pH5Xd-0003wk-7s for mharc-qemu-riscv@gnu.org; Sun, 15 Jan 2023 11:07:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pH5XI-0003tt-0K for qemu-riscv@nongnu.org; Sun, 15 Jan 2023 11:07:09 -0500 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pH5XF-0002l8-2d for qemu-riscv@nongnu.org; Sun, 15 Jan 2023 11:07:07 -0500 Received: by mail-pj1-x102c.google.com with SMTP id u1-20020a17090a450100b0022936a63a21so5182092pjg.4 for ; Sun, 15 Jan 2023 08:07:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UWv9juEM30TaG2ZFbroRk3W9f3EJ/62euGE8qgUSwqI=; b=drpqhCMrAm+voinh4wQ4z+vF4cdkJ9MMQXohQytUB6e33Memlg+pjisHGZIJ8/4WMz ElcgkhoTxEPNwvsNZ//f1E7Equ7NQArfC9Pq2PHE3ZDfE/PL9wEi4IaTiK+N6zbAXhB6 WAKKpb/huIEFcS7VZAhMR1U4xAmMEn1faPof5rgrWOfEb9PfCAUzubmeLk/zGZiN2iJw k3oFQfFKc0PPpOg7XNBMYIDrhqHOyqknZKSwdWlNUapX9hnu+vRatGSz4GuURxoFlqU5 S7NCTGY9hYLeKV1ugsqCUqYv2HUdy0Az0hx69g2FWtfYRQWkiLlrWIG1GN+iT4Oc/vlM tb5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UWv9juEM30TaG2ZFbroRk3W9f3EJ/62euGE8qgUSwqI=; b=fQmAVVKQjY8RfIZ/cEApMI3dP9lBpCPtnS/YV8J13az/N1ms+zi7Vj4eL8H9+ofn/5 YZYgekiOouFb8y/k7A8yiYI+YxvSNb0FjwmkF+NaJ7sC5moCb1xRsQ9wHdsgBHcCo3jw MOD5dC23ViDK1jRwS/uzig9Tkgo7eSCYOYthdE8CRfNmBe1bzAPv4VH2/owptlaUyTFh zXGOP3DrBu95dnHm0vw4mcP9y6HB2Aon6GglxMvyS3qRXW2qPypjS8hAlXmLYml+Vo77 HWcHBG8Lx52lBk6nNJLnSLUgAgp028vZh1Z20dxMlt8wU/LOC1US3HXSyPJI+FTQ0EYL yarA== X-Gm-Message-State: AFqh2kr9KwuvEKlQKLotEA1z/Hg5/2khURGfQrsh3Cra82TwV20Jh7Hb nkTBmkVEr6eihze0Xiqtzu0njg== X-Google-Smtp-Source: AMrXdXs/yBB0VVxXrCYncxYQEdyG06qSYjZeq3rNHNqOtQQlkXE257Ezrn60q098cvpwXmj4KMohUg== X-Received: by 2002:a05:6a20:1a8a:b0:b8:65b8:a37 with SMTP id ci10-20020a056a201a8a00b000b865b80a37mr2911364pzb.53.1673798822892; Sun, 15 Jan 2023 08:07:02 -0800 (PST) Received: from stoup.. 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id c76-20020a624e4f000000b00589c467ed88sm11422735pfb.69.2023.01.15.08.07.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jan 2023 08:07:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bin.meng@windriver.com, abdulras@google.com Subject: [PATCH 1/2] target/arm: Introduce helper_set_rounding_mode_chkfrm Date: Sun, 15 Jan 2023 06:06:56 -1000 Message-Id: <20230115160657.3169274-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230115160657.3169274-1-richard.henderson@linaro.org> References: <20230115160657.3169274-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 15 Jan 2023 16:07:12 -0000 The new helper always validates the contents of FRM, even if the new rounding mode is not DYN. This is required by the vector unit. Track whether we've validated FRM separately from whether we've updated fp_status with a given rounding mode, so that we can elide calls correctly. This partially reverts d6c4d3f2a69 which attempted the to do the same thing, but with two calls to gen_set_rm(), which is both inefficient and tickles an assertion in decode_save_opc. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1441 Signed-off-by: Richard Henderson --- target/riscv/helper.h | 1 + target/riscv/fpu_helper.c | 37 +++++++++++++++++++++++++ target/riscv/translate.c | 19 +++++++++++++ target/riscv/insn_trans/trans_rvv.c.inc | 24 +++------------- 4 files changed, 61 insertions(+), 20 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 227c7122ef..9792ab5086 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -3,6 +3,7 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32) /* Floating Point - rounding mode */ DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) +DEF_HELPER_FLAGS_2(set_rounding_mode_chkfrm, TCG_CALL_NO_WG, void, env, i32) DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env) /* Floating Point - fused */ diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 5699c9517f..96817df8ef 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -81,6 +81,43 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) set_float_rounding_mode(softrm, &env->fp_status); } +void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm) +{ + int softrm; + + /* Always validate frm, even if rm != DYN. */ + if (unlikely(env->frm >= 5)) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + if (rm == RISCV_FRM_DYN) { + rm = env->frm; + } + switch (rm) { + case RISCV_FRM_RNE: + softrm = float_round_nearest_even; + break; + case RISCV_FRM_RTZ: + softrm = float_round_to_zero; + break; + case RISCV_FRM_RDN: + softrm = float_round_down; + break; + case RISCV_FRM_RUP: + softrm = float_round_up; + break; + case RISCV_FRM_RMM: + softrm = float_round_ties_away; + break; + case RISCV_FRM_ROD: + softrm = float_round_to_odd; + break; + default: + g_assert_not_reached(); + } + + set_float_rounding_mode(softrm, &env->fp_status); +} + void helper_set_rod_rounding_mode(CPURISCVState *env) { set_float_rounding_mode(float_round_to_odd, &env->fp_status); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index df38db7553..493c3815e1 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -114,6 +114,8 @@ typedef struct DisasContext { bool pm_base_enabled; /* Use icount trigger for native debug */ bool itrigger; + /* FRM is known to contain a valid value. */ + bool frm_valid; /* TCG of the current insn_start */ TCGOp *insn_start; } DisasContext; @@ -674,12 +676,29 @@ static void gen_set_rm(DisasContext *ctx, int rm) gen_helper_set_rod_rounding_mode(cpu_env); return; } + if (rm == RISCV_FRM_DYN) { + /* The helper will return only if frm valid. */ + ctx->frm_valid = true; + } /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ decode_save_opc(ctx); gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); } +static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) +{ + if (ctx->frm == rm && ctx->frm_valid) { + return; + } + ctx->frm = rm; + ctx->frm_valid = true; + + /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ + decode_save_opc(ctx); + gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm)); +} + static int ex_plus_1(DisasContext *ctx, int nf) { return nf + 1; diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index d455acedbf..bbb5c3a7b5 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -2679,13 +2679,9 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, int rm) { if (checkfn(s, a)) { - if (rm != RISCV_FRM_DYN) { - gen_set_rm(s, RISCV_FRM_DYN); - } - uint32_t data = 0; TCGLabel *over = gen_new_label(); - gen_set_rm(s, rm); + gen_set_rm_chkfrm(s, rm); tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); @@ -2882,17 +2878,13 @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a) static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ if (CHECK(s, a)) { \ - if (FRM != RISCV_FRM_DYN) { \ - gen_set_rm(s, RISCV_FRM_DYN); \ - } \ - \ uint32_t data = 0; \ static gen_helper_gvec_3_ptr * const fns[2] = { \ gen_helper_##HELPER##_h, \ gen_helper_##HELPER##_w, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, FRM); \ + gen_set_rm_chkfrm(s, FRM); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ @@ -3005,17 +2997,13 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ if (CHECK(s, a)) { \ - if (FRM != RISCV_FRM_DYN) { \ - gen_set_rm(s, RISCV_FRM_DYN); \ - } \ - \ uint32_t data = 0; \ static gen_helper_gvec_3_ptr * const fns[2] = { \ gen_helper_##HELPER##_h, \ gen_helper_##HELPER##_w, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, FRM); \ + gen_set_rm_chkfrm(s, FRM); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ \ @@ -3060,10 +3048,6 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a) static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ { \ if (opxfv_narrow_check(s, a)) { \ - if (FRM != RISCV_FRM_DYN) { \ - gen_set_rm(s, RISCV_FRM_DYN); \ - } \ - \ uint32_t data = 0; \ static gen_helper_gvec_3_ptr * const fns[3] = { \ gen_helper_##HELPER##_b, \ @@ -3071,7 +3055,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ gen_helper_##HELPER##_w, \ }; \ TCGLabel *over = gen_new_label(); \ - gen_set_rm(s, FRM); \ + gen_set_rm_chkfrm(s, FRM); \ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id c76-20020a624e4f000000b00589c467ed88sm11422735pfb.69.2023.01.15.08.07.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Jan 2023 08:07:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bin.meng@windriver.com, abdulras@google.com Subject: [PATCH 2/2] target/riscv: Remove helper_set_rod_rounding_mode Date: Sun, 15 Jan 2023 06:06:57 -1000 Message-Id: <20230115160657.3169274-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230115160657.3169274-1-richard.henderson@linaro.org> References: <20230115160657.3169274-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 15 Jan 2023 16:07:11 -0000 The only setting of RISCV_FRM_ROD is from the vector unit, and now handled by helper_set_rounding_mode_chkfrm. This helper is now unused. Signed-off-by: Richard Henderson --- target/riscv/helper.h | 1 - target/riscv/fpu_helper.c | 5 ----- target/riscv/translate.c | 4 ---- 3 files changed, 10 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 9792ab5086..58a30f03d6 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -4,7 +4,6 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32) /* Floating Point - rounding mode */ DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) DEF_HELPER_FLAGS_2(set_rounding_mode_chkfrm, TCG_CALL_NO_WG, void, env, i32) -DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env) /* Floating Point - fused */ DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 96817df8ef..449d236df6 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -118,11 +118,6 @@ void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm) set_float_rounding_mode(softrm, &env->fp_status); } -void helper_set_rod_rounding_mode(CPURISCVState *env) -{ - set_float_rounding_mode(float_round_to_odd, &env->fp_status); -} - static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2, uint64_t rs3, int flags) { diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 493c3815e1..01cc30a365 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -672,10 +672,6 @@ static void gen_set_rm(DisasContext *ctx, int rm) } ctx->frm = rm; - if (rm == RISCV_FRM_ROD) { - gen_helper_set_rod_rounding_mode(cpu_env); - return; - } if (rm == RISCV_FRM_DYN) { /* The helper will return only if frm valid. */ ctx->frm_valid = true; -- 2.34.1 From MAILER-DAEMON Sun Jan 15 11:21:19 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pH5l1-00080F-3f for mharc-qemu-riscv@gnu.org; Sun, 15 Jan 2023 11:21:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pH5kz-0007zy-TD for qemu-riscv@nongnu.org; Sun, 15 Jan 2023 11:21:17 -0500 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pH5ky-0005JO-8v for qemu-riscv@nongnu.org; Sun, 15 Jan 2023 11:21:17 -0500 Received: by mail-pj1-x1035.google.com with SMTP id q5so742517pjh.1 for ; Sun, 15 Jan 2023 08:21:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:references:cc:to:from :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=4HwwwRKOC4pP2N7Adzj1yCmXUkvFj0ZXVMfEZ0ETB38=; b=QoFZZ8mB7bQokSlrgqQsSL2yPxK71ns/UCSzNXOTmSc7Yi9UVAIMEvoGp2YcDKIJWK sPpC4m9tESJlayKKVMi6epCRKVTsFPqrsqpHvwxX5hT/ZCGuvQBinRH6wskBZ6HB0PQX 8FWkIhs6kIsYgSctWgn4DYHKngrcxT7LzQJNoyspAzSgudEWJ8wcuSjeiyBhUZVZQlSy f0EKHDbWICdJpPDEhXwdU5ac3hlbcgYGamrh6YM+q4OLr5D0Nrcycp23Hi4d/p9fOxHQ HXCfJ11eQGcUoaOvd5g4+u8BCPPKTFhOItQaZzjHziOV6wOd5DmJ4KbHQs4CLWNdct9I /oBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:references:cc:to:from :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=4HwwwRKOC4pP2N7Adzj1yCmXUkvFj0ZXVMfEZ0ETB38=; b=xobyzqcObhX9bULxBelIAekudzLWb5rK5KTbUgAKDobAOTvsPHA7bYz083u5Lc4lov Tf7M9ZdeIUAsvqAkHVwmQnjBfLibY4MVyY/wFrQJ8SdiSftPb+s4G1CC6Rbi8HtUdsWL Tg31M0MSw3pmR1Ud2IFlZHRSu0/8gAyRNEKU0glKI/a1juwWlP4/kYnp1p2/UtGjLdst GF2BD1nAnK3/ktMkpAvbpw8FOgmnGmuPaYAGqUmmF2LgUGOfFZXKROY3rAzqACNgMomM +n+fPUB5Lm0jLVNbkN9fC28SQySPxOdQj/7U/PU7wqRrjdHS7RogTV7dh7xQAt/OxX3s AjEw== X-Gm-Message-State: AFqh2krcaSD61Mq7HSniCPTUs4V6Qf8cf6IWHblcOzxpQmgvfJfT4JmP sd+Aj2HfLCYPknwbva4A8AiV0A== X-Google-Smtp-Source: AMrXdXtJJIaAnsWSODYUf+UTLmaaEGkX+PvPs4RERMwp6l5t5f3OxsG6X+w9fOoYX8Y+dldhZ223Xg== X-Received: by 2002:a05:6a20:ce4c:b0:b6:9694:5ab2 with SMTP id id12-20020a056a20ce4c00b000b696945ab2mr11359710pzb.44.1673799674384; Sun, 15 Jan 2023 08:21:14 -0800 (PST) Received: from [192.168.5.146] (rrcs-173-198-77-218.west.biz.rr.com. [173.198.77.218]) by smtp.gmail.com with ESMTPSA id b15-20020a170902650f00b00188f3970d4asm17582497plk.163.2023.01.15.08.21.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 15 Jan 2023 08:21:13 -0800 (PST) Message-ID: <1cc50520-32a2-035a-8b47-98aaf1093354@linaro.org> Date: Sun, 15 Jan 2023 06:21:09 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH 0/2] target/riscv: Fix double calls to gen_set_rm [#1411] Content-Language: en-US From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bin.meng@windriver.com References: <20230115160657.3169274-1-richard.henderson@linaro.org> In-Reply-To: <20230115160657.3169274-1-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 15 Jan 2023 16:21:18 -0000 On 1/15/23 06:06, Richard Henderson wrote: > These double calls tickle an assertion in decode_save_opc, > and isn't efficient anyway. Introduce a new helper to do > exactly what was desired. Also #1339. r~ From MAILER-DAEMON Sun Jan 15 21:56:19 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHFfX-0001Gd-8C for mharc-qemu-riscv@gnu.org; Sun, 15 Jan 2023 21:56:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHFfV-0001GO-QO; Sun, 15 Jan 2023 21:56:17 -0500 Received: from mail-vs1-xe31.google.com ([2607:f8b0:4864:20::e31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHFfU-0001SH-6J; Sun, 15 Jan 2023 21:56:17 -0500 Received: by mail-vs1-xe31.google.com with SMTP id o63so27752714vsc.10; Sun, 15 Jan 2023 18:56:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=yb3gZmrf+v4Ba0K6ZEkHww3+50rssjbTaGOUxxpOU2s=; b=BjS3TfjPiFSRiAdsXPn06PYOJVrpAZwHl1Ryfia+pNTxZVLJjvpHkPmkqLz3x/IUix uXHp1N6JHldTmxiElufUGww8QYFrLffUgPAlIVzYjYYiGJGKNEY6DZSswVbye1OErNSg RUt6YJaAiJcrl1FLi4pMvCw9lmbUwRQ6K535mbuDOkzTOjJPdCKdOyJFZmfLGhpBgbo1 +NRodYCIRcmRGFA5/XOgzMP+S4ZY0apqG/SaSNbnwT/Rj4MM80HuSJiJYJAhmOjgDUrL BID9YO5aghr33hwxQYdsuPIHeB7NSdQA3jNQMj51DZDS5Tj0750I9FaasligwokypfiO vsXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yb3gZmrf+v4Ba0K6ZEkHww3+50rssjbTaGOUxxpOU2s=; b=MLaJozEo7ULhI1givm+8aBzuBCy5MB0Mn8YWuVkoxpm6Y8SivSVFk7pb0LXOBoNz+e AlEiOjRoHqoXU4RtXgp+T60u/AwWm8d2+7EqqvuY4zgwix/ujr5cUxz733kERts+H4dz Z2r+cOfX+BRfPN7Qh/tf6wIuqQ8pbjEXAAmkx4yOwUngc3nw4zC6+wSNfkNjwF8tAyeT UDP6w2C0HeKBhZdz8fviOK8EuyDRO70ZZXbfU3nz6aRR3z9ZSZVrkafhXEDtRTV4LUvO wvQ9MH7CdiKK3g0ASYTpcAWTFxlYu30y2Yg2GQQ/z3Tk6G5UZLgBxo9HT6TEZ5euhVOG dQ9g== X-Gm-Message-State: AFqh2kruBDGEr+T5IQPuFeuKi5fgiWrhfQ1TjjrnSjya+Py4DNPlg55y need0A7NKyj+etSw2VbglfybdAX4ydIksEPcmfM= X-Google-Smtp-Source: AMrXdXshapRqyZPBjzSsNd6H2uSXZIVTsCQzp0VjwdkTpI29/vbIUdwmbUVVVWZUMskuSwDUCkHbBS3HlStn/jeUqEs= X-Received: by 2002:a67:e052:0:b0:3d0:c2e9:cb77 with SMTP id n18-20020a67e052000000b003d0c2e9cb77mr3003019vsl.54.1673837774674; Sun, 15 Jan 2023 18:56:14 -0800 (PST) MIME-Version: 1.0 References: <20230113171805.470252-1-dbarboza@ventanamicro.com> <20230113171805.470252-3-dbarboza@ventanamicro.com> In-Reply-To: <20230113171805.470252-3-dbarboza@ventanamicro.com> From: Alistair Francis Date: Mon, 16 Jan 2023 12:55:48 +1000 Message-ID: Subject: Re: [PATCH v7 2/3] hw/riscv/boot.c: make riscv_load_initrd() static To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Bin Meng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e31; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe31.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 02:56:18 -0000 On Sat, Jan 14, 2023 at 3:39 AM Daniel Henrique Barboza wrote: > > The only remaining caller is riscv_load_kernel_and_initrd() which > belongs to the same file. > > Signed-off-by: Daniel Henrique Barboza > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/boot.c | 80 ++++++++++++++++++++--------------------- > include/hw/riscv/boot.h | 1 - > 2 files changed, 40 insertions(+), 41 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 4888d5c1e0..e868fb6ade 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -173,6 +173,46 @@ target_ulong riscv_load_firmware(const char *firmwar= e_filename, > exit(1); > } > > +static void riscv_load_initrd(MachineState *machine, uint64_t kernel_ent= ry) > +{ > + const char *filename =3D machine->initrd_filename; > + uint64_t mem_size =3D machine->ram_size; > + void *fdt =3D machine->fdt; > + hwaddr start, end; > + ssize_t size; > + > + g_assert(filename !=3D NULL); > + > + /* > + * We want to put the initrd far enough into RAM that when the > + * kernel is uncompressed it will not clobber the initrd. However > + * on boards without much RAM we must ensure that we still leave > + * enough room for a decent sized initrd, and on boards with large > + * amounts of RAM we must avoid the initrd being so far up in RAM > + * that it is outside lowmem and inaccessible to the kernel. > + * So for boards with less than 256MB of RAM we put the initrd > + * halfway into RAM, and for boards with 256MB of RAM or more we put > + * the initrd at 128MB. > + */ > + start =3D kernel_entry + MIN(mem_size / 2, 128 * MiB); > + > + size =3D load_ramdisk(filename, start, mem_size - start); > + if (size =3D=3D -1) { > + size =3D load_image_targphys(filename, start, mem_size - start); > + if (size =3D=3D -1) { > + error_report("could not load ramdisk '%s'", filename); > + exit(1); > + } > + } > + > + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ > + if (fdt) { > + end =3D start + size; > + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", star= t); > + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); > + } > +} > + > target_ulong riscv_load_kernel(MachineState *machine, > target_ulong kernel_start_addr, > bool load_initrd, > @@ -225,46 +265,6 @@ out: > return kernel_entry; > } > > -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) > -{ > - const char *filename =3D machine->initrd_filename; > - uint64_t mem_size =3D machine->ram_size; > - void *fdt =3D machine->fdt; > - hwaddr start, end; > - ssize_t size; > - > - g_assert(filename !=3D NULL); > - > - /* > - * We want to put the initrd far enough into RAM that when the > - * kernel is uncompressed it will not clobber the initrd. However > - * on boards without much RAM we must ensure that we still leave > - * enough room for a decent sized initrd, and on boards with large > - * amounts of RAM we must avoid the initrd being so far up in RAM > - * that it is outside lowmem and inaccessible to the kernel. > - * So for boards with less than 256MB of RAM we put the initrd > - * halfway into RAM, and for boards with 256MB of RAM or more we put > - * the initrd at 128MB. > - */ > - start =3D kernel_entry + MIN(mem_size / 2, 128 * MiB); > - > - size =3D load_ramdisk(filename, start, mem_size - start); > - if (size =3D=3D -1) { > - size =3D load_image_targphys(filename, start, mem_size - start); > - if (size =3D=3D -1) { > - error_report("could not load ramdisk '%s'", filename); > - exit(1); > - } > - } > - > - /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ > - if (fdt) { > - end =3D start + size; > - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", star= t); > - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); > - } > -} > - > uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) > { > uint64_t temp, fdt_addr; > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h > index c3de897371..cbd131bad7 100644 > --- a/include/hw/riscv/boot.h > +++ b/include/hw/riscv/boot.h > @@ -47,7 +47,6 @@ target_ulong riscv_load_kernel(MachineState *machine, > target_ulong firmware_end_addr, > bool load_initrd, > symbol_fn_t sym_cb); > -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); > uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt= ); > void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayStat= e *harts, > hwaddr saddr, > -- > 2.39.0 > > From MAILER-DAEMON Sun Jan 15 22:09:32 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHFsK-0004Wl-Jv for mharc-qemu-riscv@gnu.org; Sun, 15 Jan 2023 22:09:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHFsK-0004WY-0E; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::a2e; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 03:09:32 -0000 On Sat, Jan 14, 2023 at 3:55 AM Daniel Henrique Barboza wrote: > > Hi, > > In this version I fixed the commit message typos pointed by Bin. I've > also added some notes about the code repetition the fix is introducing > in the cpu_init() functions. > > The patches are based on riscv-to-apply.next at c1e76da3e668 > ("target/riscv/cpu.c: Fix elen check"). > > Changes from v1: > - patch 1: > - fixed commit message typos > v1 review: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02035.html > > Daniel Henrique Barboza (2): > target/riscv/cpu: set cpu->cfg in register_cpu_props() > target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu.c | 439 +++++++++++++++++++++++++-------------------- > target/riscv/cpu.h | 4 + > 2 files changed, 249 insertions(+), 194 deletions(-) > > -- > 2.39.0 > > From MAILER-DAEMON Sun Jan 15 22:15:22 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHFxy-00060q-7T for mharc-qemu-riscv@gnu.org; Sun, 15 Jan 2023 22:15:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHFxw-0005yr-EY; Sun, 15 Jan 2023 22:15:20 -0500 Received: from mail-vs1-xe30.google.com ([2607:f8b0:4864:20::e30]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHFxv-0003zF-0h; Sun, 15 Jan 2023 22:15:20 -0500 Received: by mail-vs1-xe30.google.com with SMTP id l125so8460936vsc.2; Sun, 15 Jan 2023 19:15:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=1eDUDW3Do32BbxoncT7Oy8ZChkgrOKCbEGNkcCpFceg=; b=Ii4nyuQPcHFYqg5af3RE1trVE7Vb6QCMpalMaRtJgQVe7pk4HoYvRhm4x1YNm/OV8c hiW0K0gB9OML7MPzFeN7PKI2snHPx86hlBfUey0H2Jfm3rgAlHHvRwFsd/spe8G0oeyt 54ELgqMqU6wr5xbtfUBlTJtugce0INdJbP2E9H7dcc4UOZckoYiX6B2svLxYr4qT434f 2oObkUtv7ycXQdchUBH0KVH4iHnfrW74xH+iuVb3HmaoK//11oQ5H8lsE+EhfALiJYhS zSrg0tOVA4btJrYSYwPnMo9tmaWMxpi9PrYn3V5npMjw0+O0lzCgKWDsWQrLfXJmF3t0 f4YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=1eDUDW3Do32BbxoncT7Oy8ZChkgrOKCbEGNkcCpFceg=; b=aLmfhSZJoqWDU7cKSSUY+bW8b/kymbXFZG9oo3B1cBr4QbygDcSOB/d8DjmFGgu60H JVmjSQi/RwQ3LEZeblaojAyJlnTiYv/znMXP57rQyye2eaH9H2LGwugIFLNm8NJlhII/ PgmF8pU8H8m/q2LK1hvynhUmRFgXREKRAbTfWVhSkAXE5Dv8LNQeQCzvKAWvty1tg77a FZuiYl51HLFYEqKxaNc5RXXb/TJqw29Rx2r2jW3ScIJyBVjtSbVuVCYycThgsyzDvyij Sn98Q2hNeO2AEyV9rEiTR02z03FWccydkHEiymUpxQtFyrxerRxeTIbscLHuI9p0lnZv HY9w== X-Gm-Message-State: AFqh2koQWPi0LGeizvhXVQN/10rBLEg1ERlWHlB2bd/xPO0a2CEgOZ2A XAbdZdN2Uz8pniSlXMSRmh6TZRkE0XuhBtRO8apVoHSuCA1WeQ== X-Google-Smtp-Source: AMrXdXt8obYTEIgAMVuX20EbSIvAgxHGAZj9VZknW6VoBvPjsfyACeUlDJr6eeGCaNQ+TgJ1rdSG9LAGDm9mAbH4g2s= X-Received: by 2002:a05:6102:510e:b0:3b1:2b83:1861 with SMTP id bm14-20020a056102510e00b003b12b831861mr11644412vsb.10.1673838917653; Sun, 15 Jan 2023 19:15:17 -0800 (PST) MIME-Version: 1.0 References: <20230109152655.340114-1-bmeng@tinylab.org> In-Reply-To: <20230109152655.340114-1-bmeng@tinylab.org> From: Alistair Francis Date: Mon, 16 Jan 2023 13:14:51 +1000 Message-ID: Subject: Re: [PATCH] target/riscv: Use TARGET_FMT_lx for env->mhartid To: Bin Meng Cc: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e30; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe30.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 03:15:20 -0000 On Tue, Jan 10, 2023 at 1:28 AM Bin Meng wrote: > > env->mhartid is currently casted to long before printed, which drops > the high 32-bit for rv64 on 32-bit host. Use TARGET_FMT_lx instead. > > Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Alistair > --- > > target/riscv/cpu.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index cc75ca7667..a5ed6d3f63 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -660,9 +660,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > (env->priv_ver < isa_edata_arr[i].min_version)) { > isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); > #ifndef CONFIG_USER_ONLY > - warn_report("disabling %s extension for hart 0x%lx because " > - "privilege spec version does not match", > - isa_edata_arr[i].name, (unsigned long)env->mhartid); > + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx > + " because privilege spec version does not match", > + isa_edata_arr[i].name, env->mhartid); > #else > warn_report("disabling %s extension because " > "privilege spec version does not match", > -- > 2.34.1 > > From MAILER-DAEMON Sun Jan 15 22:47:10 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHGSj-0004eU-WD for mharc-qemu-riscv@gnu.org; Sun, 15 Jan 2023 22:47:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHGSW-0004dn-LR; Sun, 15 Jan 2023 22:46:56 -0500 Received: from mail-vk1-xa35.google.com ([2607:f8b0:4864:20::a35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHGSV-0000A9-3I; Sun, 15 Jan 2023 22:46:56 -0500 Received: by mail-vk1-xa35.google.com with SMTP id w72so12790367vkw.7; Sun, 15 Jan 2023 19:46:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=/ZgL6g3tzzrMslCgpZr3vadgb8PKA9WFOnNxCm/ITvI=; b=htmbcobEpHfS93Ks3RHW4DOSkq8KMoXf96WyCaoIp+8dcCl49C4fjhKcC+3VPp5gsA 97UzodAaEANyhCgGL5cNXcj3PpZCfYD6rdIfRGybbbsm+VPYv1aV+gcZEVJilGhVhjMk juo8NYDT3dmF6V0yNu2g8YRwd+1fo3lCboul68FGpv359dnXOYY4A/SP80UDDs2bN9Ht 0DaQN1GC6J8q7dVgX27Q+cGzsvP0Ypa0eQAhFOct97rbewjf+kPCuVfhtObqKKtLisPZ 5RRx8GRdytT+WZvOQsCvNEC0x3qlbDOrVmod9gWkIkS0/CiRXD8ATQEqY7QXfif0m0JM OtjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=/ZgL6g3tzzrMslCgpZr3vadgb8PKA9WFOnNxCm/ITvI=; b=39lEBspzdg3ArnsmtHKFtuj0JsIMZ18ax9O6/4g+cEazNH+hVBCiAuOCFLLn+VlqS7 bYy0/6SF4cTv7493lRjYjuGBRhJbCzicpM4BqgMlmpWI5j5fIuOzCTMeln55rXf5cJxW eQiKnIZc4Ix+lKg/KFmSiqXstf92VPaE49VMewT5d0MRMySUe9BbJ5l6Y9AbMB10f8je c4la5/xjH/ETB1L+4U3+5yPOp1KQrYM19cTWn+ni0OMQfpnFhzB3jwKQY0p81dZiTAVN bLFbhbBKHQl3uOZGtWJyBdrttQr/N6JxhjWqMdfWIQJwzdjKxzgD5cX6ZhHoUQSTDP01 zpsg== X-Gm-Message-State: AFqh2kr74ByG6EG6d4iDqqcczb12+HJu4B1GYIGZnB2GqS/MTA5EWGFF LyCmOGp4+7BySi93Swl/3s3+1OAAFp01TklXark+PGDYcg8G9g== X-Google-Smtp-Source: AMrXdXtvL53wz9NGlckclGMTwP74RrlGTym9tdiiRpWVuHOmBHhj8O7gKNiMCOpFLmeHFs1VX/sUUD1oQog6gFanBDA= X-Received: by 2002:a1f:c703:0:b0:3d5:6ccb:8748 with SMTP id x3-20020a1fc703000000b003d56ccb8748mr9255079vkf.26.1673840805637; Sun, 15 Jan 2023 19:46:45 -0800 (PST) MIME-Version: 1.0 References: <20230109152655.340114-1-bmeng@tinylab.org> In-Reply-To: <20230109152655.340114-1-bmeng@tinylab.org> From: Alistair Francis Date: Mon, 16 Jan 2023 13:46:19 +1000 Message-ID: Subject: Re: [PATCH] target/riscv: Use TARGET_FMT_lx for env->mhartid To: Bin Meng Cc: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::a35; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa35.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 03:47:08 -0000 On Tue, Jan 10, 2023 at 1:28 AM Bin Meng wrote: > > env->mhartid is currently casted to long before printed, which drops > the high 32-bit for rv64 on 32-bit host. Use TARGET_FMT_lx instead. > > Signed-off-by: Bin Meng Thanks! Applied to riscv-to-apply.next Alistair > --- > > target/riscv/cpu.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index cc75ca7667..a5ed6d3f63 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -660,9 +660,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > (env->priv_ver < isa_edata_arr[i].min_version)) { > isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); > #ifndef CONFIG_USER_ONLY > - warn_report("disabling %s extension for hart 0x%lx because " > - "privilege spec version does not match", > - isa_edata_arr[i].name, (unsigned long)env->mhartid); > + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx > + " because privilege spec version does not match", > + isa_edata_arr[i].name, env->mhartid); > #else > warn_report("disabling %s extension because " > "privilege spec version does not match", > -- > 2.34.1 > > From MAILER-DAEMON Sun Jan 15 22:53:54 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHGZG-0005vf-MG for mharc-qemu-riscv@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e29; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe29.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 03:53:54 -0000 On Thu, Jan 12, 2023 at 3:21 AM Daniel Henrique Barboza wrote: > > 'mem_size' and 'cmdline' are unused. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/spike.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index c517885e6e..4a66016d69 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -49,7 +49,6 @@ static const MemMapEntry spike_memmap[] = { > }; > > static void create_fdt(SpikeState *s, const MemMapEntry *memmap, > - uint64_t mem_size, const char *cmdline, > bool is_32_bit, bool htif_custom_base) > { > void *fdt; > @@ -299,8 +298,7 @@ static void spike_board_init(MachineState *machine) > } > > /* Create device tree */ > - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, > - riscv_is_32bit(&s->soc[0]), htif_custom_base); > + create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base); > > /* Load kernel */ > if (machine->kernel_filename) { > -- > 2.39.0 > > From MAILER-DAEMON Sun Jan 15 22:55:12 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHGaW-0006iX-JF for mharc-qemu-riscv@gnu.org; Sun, 15 Jan 2023 22:55:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHGaU-0006hq-6u; Sun, 15 Jan 2023 22:55:10 -0500 Received: from mail-vs1-xe2a.google.com ([2607:f8b0:4864:20::e2a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHGaS-0001BG-Rk; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e2a; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 03:55:10 -0000 On Thu, Jan 12, 2023 at 3:18 AM Daniel Henrique Barboza wrote: > > 'mem_size' and 'cmdline' aren't being used. Remove them. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/virt.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index a931ed05ab..89c99ec1af 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -999,7 +999,7 @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) > } > > static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, > - uint64_t mem_size, const char *cmdline, bool is_32_bit) > + bool is_32_bit) > { > MachineState *mc = MACHINE(s); > uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; > @@ -1499,8 +1499,7 @@ static void virt_machine_init(MachineState *machine) > virt_flash_map(s, system_memory); > > /* create device tree */ > - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, > - riscv_is_32bit(&s->soc[0])); > + create_fdt(s, memmap, riscv_is_32bit(&s->soc[0])); > > s->machine_done.notify = virt_machine_done; > qemu_add_machine_init_done_notifier(&s->machine_done); > -- > 2.39.0 > > From MAILER-DAEMON Sun Jan 15 22:57:53 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHGd7-0007d3-Ix for mharc-qemu-riscv@gnu.org; Sun, 15 Jan 2023 22:57:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHGd4-0007cI-Ka; Sun, 15 Jan 2023 22:57:50 -0500 Received: from mail-vs1-xe2b.google.com ([2607:f8b0:4864:20::e2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHGcn-0001bC-Cu; Sun, 15 Jan 2023 22:57:34 -0500 Received: by mail-vs1-xe2b.google.com with SMTP id k4so27843141vsc.4; Sun, 15 Jan 2023 19:57:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=54s5sY9wHfUM7Myt1094eNvwMqve0Qi7RZp9Mc8ByHs=; b=YW4xs5ivjHMipAqtQGvnBkTDGgktxPuUES5RQAvbZwuU5AhTZRJrXL3lGRq0RbWQWC ofu6tXOGUoCVtfvtoqUfpJecHn79PAyxTfyqMl4RcQ8sVCE6DT6zIruKpX28IVIsOgnN xMB7quA+mciAxWjtobce0RR7zIHUU3U8GqzKlb9Np+jDvu+esCD/IbF9EUkTKiRVkOBe dZWzAzokv8TtE1jZOQ/HDPzUpV+LD4/YA8/9aMYrV1/jTJuz9ZCWw5Wm05KLHp5Hn2KX TrIygDDTjjwvzDVjJmc2K57kHnkPVUedjtNo+ZIEbRuzWtRnHtxEEL5yWmZfom2ruPUw BVqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=54s5sY9wHfUM7Myt1094eNvwMqve0Qi7RZp9Mc8ByHs=; b=uvB3GpAS283WVhXjizgXGm0q1s+3EMEwE0bfmbMA25TJRSt8DK6edZwSOOgF55Xoj8 W0UODto/UF0v6jwyvIK08MiStIURLwF3LvStN44EyOaRjisULqVFOwihB9i4xAF8/mwF 2kTJ30wmquxg3oA3sgR6txh55h9Rty3PogF58CPiL0t4iXfsmxb3m+Cr2vpHTJTFrE8x 1StbLG3qUzXvdK2XfN4kQ1NETsr0iv3jGIs1zwhLMzGU84WepELovr1cnrtGH4qK9jVf 9xibl+3ujyt+ZSOufvlgyhg4HW/ggAABbsPdJmX2TuaYXLLv8xhJzpLTBbQxYeGhr1sn 40kQ== X-Gm-Message-State: AFqh2kqV5+9szqCl+gcPtG+CFGfywB3aFxv0fGZ2qaIt1c/h5/kub8xR NZjZ1raBo/sAo9BR6/aZTrC39mLL3GRxvVY5kkM= X-Google-Smtp-Source: AMrXdXvPC65LVXFZRVtfYcSwMEWjlc0tTrMtLkVoCeTBO5lozcnrbsW36W+JUKF75I9zEP1Pg1eGbMAx8yYIDffftYs= X-Received: by 2002:a67:c508:0:b0:3d3:c7d9:7b62 with SMTP id e8-20020a67c508000000b003d3c7d97b62mr443380vsk.72.1673841451896; Sun, 15 Jan 2023 19:57:31 -0800 (PST) MIME-Version: 1.0 References: <20230111170948.316276-1-dbarboza@ventanamicro.com> <20230111170948.316276-4-dbarboza@ventanamicro.com> In-Reply-To: <20230111170948.316276-4-dbarboza@ventanamicro.com> From: Alistair Francis Date: Mon, 16 Jan 2023 13:57:05 +1000 Message-ID: Subject: Re: [PATCH 03/10] hw/riscv/sifive_u.c: simplify create_fdt() To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Palmer Dabbelt Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e2b; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 03:57:51 -0000 On Thu, Jan 12, 2023 at 3:25 AM Daniel Henrique Barboza wrote: > > 'cmdline' isn't being used. Remove it. > > A MachineState pointer is being retrieved via a MACHINE() macro calling > qdev_get_machine(). Use MACHINE(s) instead to avoid calling qdev(). > > 'mem_size' is being set as machine->ram_size by the caller. Retrieve it > via ms->ram_size. > > Cc: Palmer Dabbelt > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/sifive_u.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 9a75d4aa62..ccad386920 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -94,9 +94,10 @@ static const MemMapEntry sifive_u_memmap[] = { > #define GEM_REVISION 0x10070109 > > static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, > - uint64_t mem_size, const char *cmdline, bool is_32_bit) > + bool is_32_bit) > { > - MachineState *ms = MACHINE(qdev_get_machine()); > + MachineState *ms = MACHINE(s); > + uint64_t mem_size = ms->ram_size; > void *fdt; > int cpu, fdt_size; > uint32_t *cells; > @@ -560,8 +561,7 @@ static void sifive_u_machine_init(MachineState *machine) > qemu_allocate_irq(sifive_u_machine_reset, NULL, 0)); > > /* create device tree */ > - create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline, > - riscv_is_32bit(&s->soc.u_cpus)); > + create_fdt(s, memmap, riscv_is_32bit(&s->soc.u_cpus)); > > if (s->start_in_flash) { > /* > -- > 2.39.0 > > From MAILER-DAEMON Sun Jan 15 22:59:25 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHGeb-0008Mq-OW for mharc-qemu-riscv@gnu.org; Sun, 15 Jan 2023 22:59:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHGea-0008MZ-80; Sun, 15 Jan 2023 22:59:24 -0500 Received: from mail-vs1-xe34.google.com ([2607:f8b0:4864:20::e34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHGeY-0001gV-Dp; Sun, 15 Jan 2023 22:59:23 -0500 Received: by mail-vs1-xe34.google.com with SMTP id k4so27845439vsc.4; Sun, 15 Jan 2023 19:59:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=B23PUcYuSBn2pTz5X3It7LWM7r/dqGJ6/3fXVTJ4pHc=; b=OKj7fFKxhruFpZVqoKAaO148AKwgaAR1RPynYU9rITZJ51wU/C00G6tqKXM/WhbeyM iVTXUlsU4ZfMBd90N7iHmfCAWhHiFwIcFeRR0TJlT1l7i6GSfguAi8d0rfS0Hb5y2wU8 UPkQ/MelNhNZlQI6xwbxImuiN6tGFKzZMl639Mmsvw2onHCijYnmYjo+xJuAyXZlMtRX wJ016seGui8ylFaQRbRnVY1T8U3I49Cvi/n/Awsp7PP+3VTt1nOOc3miL8wl6b8MHBFf m5uArEnwm45CxP+62YPeBWbSRous80dS7sz8brCAXh3aVDVQNdOw2kB51JOtMVBLgIN0 Ljaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=B23PUcYuSBn2pTz5X3It7LWM7r/dqGJ6/3fXVTJ4pHc=; b=v42zKd91YXyBCJTlEU9zGwEydWfWBP7bwQoIefevq+byHUVwyWzq59k8k2UM56snYc hGrL4BiRJGexu5FJiO009FtEVVkx5GWkm0IDQvddzKwyPL6oP2ucbzB9QbtCVc2uTccP VlX0GZvgId/Yl2dskfbSkol7xrfeZHYfeFw2/VDkMJXYuXMuDYmlmxR4nrQXmBImh0Lv 1/dG0sJOP8IFcVzH5KDsbn2XjQNyPCp12j4EH1KAw/XG0s2WH5S34l4wyIPxsVddPJPw mEsjlWBmHVd2yLUEeMjo5KfbAdI4tH04+km7OMZ/5leUi7RKOrWYKyQCkZ8FbvzSDHZc GK8g== X-Gm-Message-State: AFqh2kq/JYul+d4D+6pfsGH4uLc920RxyXh6f4mCHO2CWqHGmk91TiMn Md6P1mgqGD8ELku2AUSGlZFSEjF4TopOdyyeGqc= X-Google-Smtp-Source: AMrXdXsHeNvWPFmhXl2DM9hTWvExde37ALLZGFcfre12/rUsrhwnMLH1mGmT7o3OppbzdjYtWthHlRiDBf8W4VmVw7Y= X-Received: by 2002:a05:6102:f8c:b0:3c9:8cc2:dd04 with SMTP id e12-20020a0561020f8c00b003c98cc2dd04mr10389475vsv.73.1673841560995; Sun, 15 Jan 2023 19:59:20 -0800 (PST) MIME-Version: 1.0 References: <20230111170948.316276-1-dbarboza@ventanamicro.com> <20230111170948.316276-5-dbarboza@ventanamicro.com> In-Reply-To: <20230111170948.316276-5-dbarboza@ventanamicro.com> From: Alistair Francis Date: Mon, 16 Jan 2023 13:58:54 +1000 Message-ID: Subject: Re: [PATCH 04/10] hw/riscv/virt.c: remove 'is_32_bit' param from create_fdt_socket_cpus() To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e34; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe34.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 03:59:24 -0000 On Thu, Jan 12, 2023 at 3:22 AM Daniel Henrique Barboza wrote: > > create_fdt_socket_cpus() writes a different 'mmu-type' value if we're > running in 32 or 64 bits. However, the flag is being calculated during > virt_machine_init(), and is passed around in create_fdt(), then > create_fdt_socket(), and then finally create_fdt_socket_cpus(). None of > the intermediate functions are using the flag, which is a bit > misleading. > > Remove 'is_32_bit' flag from create_fdt_socket_cpus() and calculate it > using the already available RISCVVirtState pointer. This will also > change the signature of create_fdt_socket() and create_fdt(), making it > clear that these functions don't do anything special when we're running > in 32 bit mode. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/virt.c | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 89c99ec1af..99a0a43a73 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -223,12 +223,13 @@ static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodename, > > static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > char *clust_name, uint32_t *phandle, > - bool is_32_bit, uint32_t *intc_phandles) > + uint32_t *intc_phandles) > { > int cpu; > uint32_t cpu_phandle; > MachineState *mc = MACHINE(s); > char *name, *cpu_name, *core_name, *intc_name; > + bool is_32_bit = riscv_is_32bit(&s->soc[0]); > > for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { > cpu_phandle = (*phandle)++; > @@ -721,7 +722,7 @@ static void create_fdt_pmu(RISCVVirtState *s) > } > > static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, > - bool is_32_bit, uint32_t *phandle, > + uint32_t *phandle, > uint32_t *irq_mmio_phandle, > uint32_t *irq_pcie_phandle, > uint32_t *irq_virtio_phandle, > @@ -750,7 +751,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, > qemu_fdt_add_subnode(mc->fdt, clust_name); > > create_fdt_socket_cpus(s, socket, clust_name, phandle, > - is_32_bit, &intc_phandles[phandle_pos]); > + &intc_phandles[phandle_pos]); > > create_fdt_socket_memory(s, memmap, socket); > > @@ -998,8 +999,7 @@ static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) > g_free(nodename); > } > > -static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, > - bool is_32_bit) > +static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) > { > MachineState *mc = MACHINE(s); > uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; > @@ -1031,9 +1031,9 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, > qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); > qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); > > - create_fdt_sockets(s, memmap, is_32_bit, &phandle, > - &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, > - &msi_pcie_phandle); > + create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle, > + &irq_pcie_phandle, &irq_virtio_phandle, > + &msi_pcie_phandle); > > create_fdt_virtio(s, memmap, irq_virtio_phandle); > > @@ -1499,7 +1499,7 @@ static void virt_machine_init(MachineState *machine) > virt_flash_map(s, system_memory); > > /* create device tree */ > - create_fdt(s, memmap, riscv_is_32bit(&s->soc[0])); > + create_fdt(s, memmap); > > s->machine_done.notify = virt_machine_done; > qemu_add_machine_init_done_notifier(&s->machine_done); > -- > 2.39.0 > > From MAILER-DAEMON Sun Jan 15 23:02:42 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHGhl-0000uj-5F for mharc-qemu-riscv@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e31; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe31.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 04:02:38 -0000 On Thu, Jan 12, 2023 at 3:28 AM Daniel Henrique Barboza wrote: > > There's no need to use a MachineState pointer and a fdt pointer now that > all RISC-V machines are using the FDT from the MachineState. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/numa.c | 6 +++--- > hw/riscv/spike.c | 6 +++--- > hw/riscv/virt.c | 18 +++++++++--------- > include/hw/riscv/numa.h | 6 +++--- > 4 files changed, 18 insertions(+), 18 deletions(-) > > diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c > index 7fe92d402f..f4343f5cde 100644 > --- a/hw/riscv/numa.c > +++ b/hw/riscv/numa.c > @@ -156,11 +156,11 @@ uint64_t riscv_socket_mem_size(const MachineState *ms, int socket_id) > ms->numa_state->nodes[socket_id].node_mem : 0; > } > > -void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt, > - const char *node_name, int socket_id) > +void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, > + int socket_id) > { > if (numa_enabled(ms)) { > - qemu_fdt_setprop_cell(fdt, node_name, "numa-node-id", socket_id); > + qemu_fdt_setprop_cell(ms->fdt, node_name, "numa-node-id", socket_id); > } > } > > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index 4a66016d69..05d34651cb 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -121,7 +121,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, > qemu_fdt_setprop_cell(fdt, cpu_name, "reg", > s->soc[socket].hartid_base + cpu); > qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); > - riscv_socket_fdt_write_id(mc, fdt, cpu_name, socket); > + riscv_socket_fdt_write_id(mc, cpu_name, socket); > qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); > > intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); > @@ -154,7 +154,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, > qemu_fdt_setprop_cells(fdt, mem_name, "reg", > addr >> 32, addr, size >> 32, size); > qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); > - riscv_socket_fdt_write_id(mc, fdt, mem_name, socket); > + riscv_socket_fdt_write_id(mc, mem_name, socket); > g_free(mem_name); > > clint_addr = memmap[SPIKE_CLINT].base + > @@ -167,7 +167,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, > 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); > qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", > clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); > - riscv_socket_fdt_write_id(mc, fdt, clint_name, socket); > + riscv_socket_fdt_write_id(mc, clint_name, socket); > > g_free(clint_name); > g_free(clint_cells); > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 99a0a43a73..1d3bd25cb5 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -253,7 +253,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", > s->soc[socket].hartid_base + cpu); > qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); > - riscv_socket_fdt_write_id(mc, mc->fdt, cpu_name, socket); > + riscv_socket_fdt_write_id(mc, cpu_name, socket); > qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); > > intc_phandles[cpu] = (*phandle)++; > @@ -291,7 +291,7 @@ static void create_fdt_socket_memory(RISCVVirtState *s, > qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", > addr >> 32, addr, size >> 32, size); > qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); > - riscv_socket_fdt_write_id(mc, mc->fdt, mem_name, socket); > + riscv_socket_fdt_write_id(mc, mem_name, socket); > g_free(mem_name); > } > > @@ -327,7 +327,7 @@ static void create_fdt_socket_clint(RISCVVirtState *s, > 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); > qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", > clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); > - riscv_socket_fdt_write_id(mc, mc->fdt, clint_name, socket); > + riscv_socket_fdt_write_id(mc, clint_name, socket); > g_free(clint_name); > > g_free(clint_cells); > @@ -372,7 +372,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, > aclint_mswi_cells, aclint_cells_size); > qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); > qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); > - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); > + riscv_socket_fdt_write_id(mc, name, socket); > g_free(name); > } > > @@ -396,7 +396,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, > 0x0, RISCV_ACLINT_DEFAULT_MTIME); > qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", > aclint_mtimer_cells, aclint_cells_size); > - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); > + riscv_socket_fdt_write_id(mc, name, socket); > g_free(name); > > if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { > @@ -412,7 +412,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, > aclint_sswi_cells, aclint_cells_size); > qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); > qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); > - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); > + riscv_socket_fdt_write_id(mc, name, socket); > g_free(name); > } > > @@ -471,7 +471,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s, > 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); > qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", > VIRT_IRQCHIP_NUM_SOURCES - 1); > - riscv_socket_fdt_write_id(mc, mc->fdt, plic_name, socket); > + riscv_socket_fdt_write_id(mc, plic_name, socket); > qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", > plic_phandles[socket]); > > @@ -663,7 +663,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, > aplic_s_phandle); > qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", > aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); > - riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); > + riscv_socket_fdt_write_id(mc, aplic_name, socket); > qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); > g_free(aplic_name); > > @@ -691,7 +691,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, > 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); > qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", > VIRT_IRQCHIP_NUM_SOURCES); > - riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); > + riscv_socket_fdt_write_id(mc, aplic_name, socket); > qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); > > if (!socket) { > diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h > index 1a9cce3344..634df6673f 100644 > --- a/include/hw/riscv/numa.h > +++ b/include/hw/riscv/numa.h > @@ -90,10 +90,10 @@ bool riscv_socket_check_hartids(const MachineState *ms, int socket_id); > * @ms: pointer to machine state > * @socket_id: socket index > * > - * Write NUMA node-id FDT property for given FDT node > + * Write NUMA node-id FDT property in MachineState->fdt > */ > -void riscv_socket_fdt_write_id(const MachineState *ms, void *fdt, > - const char *node_name, int socket_id); > +void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, > + int socket_id); > > /** > * riscv_socket_fdt_write_distance_matrix: > -- > 2.39.0 > > From MAILER-DAEMON Sun Jan 15 23:04:52 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHGjs-00020J-3w for mharc-qemu-riscv@gnu.org; Sun, 15 Jan 2023 23:04:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHGjk-0001z6-Hy; Sun, 15 Jan 2023 23:04:44 -0500 Received: from mail-vk1-xa29.google.com ([2607:f8b0:4864:20::a29]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHGji-0002JK-Hz; Sun, 15 Jan 2023 23:04:43 -0500 Received: by mail-vk1-xa29.google.com with SMTP id 6so12804406vkz.0; Sun, 15 Jan 2023 20:04:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; 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Sun, 15 Jan 2023 20:04:40 -0800 (PST) MIME-Version: 1.0 References: <20230111170948.316276-1-dbarboza@ventanamicro.com> <20230111170948.316276-7-dbarboza@ventanamicro.com> In-Reply-To: <20230111170948.316276-7-dbarboza@ventanamicro.com> From: Alistair Francis Date: Mon, 16 Jan 2023 14:04:14 +1000 Message-ID: Subject: Re: [PATCH 06/10] hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::a29; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa29.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 04:04:46 -0000 On Thu, Jan 12, 2023 at 3:26 AM Daniel Henrique Barboza wrote: > > There's no need to use a MachineState pointer and a fdt pointer now that > all RISC-V machines are using the FDT from the MachineState. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/numa.c | 8 ++++---- > hw/riscv/spike.c | 2 +- > hw/riscv/virt.c | 2 +- > include/hw/riscv/numa.h | 4 ++-- > 4 files changed, 8 insertions(+), 8 deletions(-) > > diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c > index f4343f5cde..4720102561 100644 > --- a/hw/riscv/numa.c > +++ b/hw/riscv/numa.c > @@ -164,7 +164,7 @@ void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, > } > } > > -void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt) > +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms) > { > int i, j, idx; > uint32_t *dist_matrix, dist_matrix_size; > @@ -184,10 +184,10 @@ void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt) > } > } > > - qemu_fdt_add_subnode(fdt, "/distance-map"); > - qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", > + qemu_fdt_add_subnode(ms->fdt, "/distance-map"); > + qemu_fdt_setprop_string(ms->fdt, "/distance-map", "compatible", > "numa-distance-map-v1"); > - qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", > + qemu_fdt_setprop(ms->fdt, "/distance-map", "distance-matrix", > dist_matrix, dist_matrix_size); > g_free(dist_matrix); > } > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index 05d34651cb..91bf194ec1 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -174,7 +174,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, > g_free(clust_name); > } > > - riscv_socket_fdt_write_distance_matrix(mc, fdt); > + riscv_socket_fdt_write_distance_matrix(mc); > > qemu_fdt_add_subnode(fdt, "/chosen"); > qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 1d3bd25cb5..e374b58f89 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -805,7 +805,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, > } > } > > - riscv_socket_fdt_write_distance_matrix(mc, mc->fdt); > + riscv_socket_fdt_write_distance_matrix(mc); > } > > static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, > diff --git a/include/hw/riscv/numa.h b/include/hw/riscv/numa.h > index 634df6673f..8f5280211d 100644 > --- a/include/hw/riscv/numa.h > +++ b/include/hw/riscv/numa.h > @@ -100,9 +100,9 @@ void riscv_socket_fdt_write_id(const MachineState *ms, const char *node_name, > * @ms: pointer to machine state > * @socket_id: socket index > * > - * Write NUMA distance matrix in FDT for given machine > + * Write NUMA distance matrix in MachineState->fdt > */ > -void riscv_socket_fdt_write_distance_matrix(const MachineState *ms, void *fdt); > +void riscv_socket_fdt_write_distance_matrix(const MachineState *ms); > > CpuInstanceProperties > riscv_numa_cpu_index_to_props(MachineState *ms, unsigned cpu_index); > -- > 2.39.0 > > From MAILER-DAEMON Sun Jan 15 23:05:16 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHGkG-0002VJ-Mp for mharc-qemu-riscv@gnu.org; Sun, 15 Jan 2023 23:05:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHGkE-0002PQ-GL; Sun, 15 Jan 2023 23:05:14 -0500 Received: from mail-vs1-xe2b.google.com ([2607:f8b0:4864:20::e2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHGkA-0002XW-Au; Sun, 15 Jan 2023 23:05:12 -0500 Received: by mail-vs1-xe2b.google.com with SMTP id p1so11092375vsr.5; Sun, 15 Jan 2023 20:05:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; 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Sun, 15 Jan 2023 20:05:08 -0800 (PST) MIME-Version: 1.0 References: <20230111170948.316276-1-dbarboza@ventanamicro.com> In-Reply-To: <20230111170948.316276-1-dbarboza@ventanamicro.com> From: Alistair Francis Date: Mon, 16 Jan 2023 14:04:42 +1000 Message-ID: Subject: Re: [PATCH 00/10] riscv: create_fdt() related cleanups To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e2b; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 04:05:15 -0000 On Thu, Jan 12, 2023 at 3:12 AM Daniel Henrique Barboza wrote: > > Hi, > > This is a follow-up of: > > "[PATCH v5 00/11] riscv: OpenSBI boot test and cleanups" > > Patches were based on top of riscv-to-apply.next [1] + the series above. > > The recent FDT changes made in hw/riscv (all machines are now using the > FDT via MachineState::fdt) allowed for most of the cleanups made here. > > Patches 9 and 10 were based on a suggestion made by Phil a few weeks ago. > I decided to go for it. > > [1] https://github.com/alistair23/qemu/tree/riscv-to-apply.next > > Daniel Henrique Barboza (10): > hw/riscv/spike.c: simplify create_fdt() > hw/riscv/virt.c: simplify create_fdt() > hw/riscv/sifive_u.c: simplify create_fdt() > hw/riscv/virt.c: remove 'is_32_bit' param from > create_fdt_socket_cpus() > hw/riscv: use MachineState::fdt in riscv_socket_fdt_write_id() > hw/riscv: use ms->fdt in riscv_socket_fdt_write_distance_matrix() > hw/riscv: simplify riscv_load_fdt() > hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() > hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' > hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' Applied patches 1 to 6. Alistair > > hw/riscv/boot.c | 4 +- > hw/riscv/microchip_pfsoc.c | 4 +- > hw/riscv/numa.c | 14 +- > hw/riscv/sifive_u.c | 11 +- > hw/riscv/spike.c | 25 +- > hw/riscv/virt.c | 484 +++++++++++++++++++------------------ > include/hw/riscv/boot.h | 2 +- > include/hw/riscv/numa.h | 10 +- > 8 files changed, 277 insertions(+), 277 deletions(-) > > -- > 2.39.0 > > From MAILER-DAEMON Sun Jan 15 23:07:19 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHGmE-0003xn-WE for mharc-qemu-riscv@gnu.org; Sun, 15 Jan 2023 23:07:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHGmD-0003xV-Fh; Sun, 15 Jan 2023 23:07:17 -0500 Received: from mail-vs1-xe2b.google.com ([2607:f8b0:4864:20::e2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHGmC-0002u8-0q; Sun, 15 Jan 2023 23:07:17 -0500 Received: by mail-vs1-xe2b.google.com with SMTP id 3so27877563vsq.7; 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Sun, 15 Jan 2023 20:07:14 -0800 (PST) MIME-Version: 1.0 References: <20230113103453.42776-1-alexghiti@rivosinc.com> <20230113103453.42776-2-alexghiti@rivosinc.com> In-Reply-To: <20230113103453.42776-2-alexghiti@rivosinc.com> From: Alistair Francis Date: Mon, 16 Jan 2023 14:06:48 +1000 Message-ID: Subject: Re: [PATCH v5 1/2] riscv: Pass Object to register_cpu_props instead of DeviceState To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e2b; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 04:07:17 -0000 On Fri, Jan 13, 2023 at 8:36 PM Alexandre Ghiti wrote: > > One can extract the DeviceState pointer from the Object pointer, so pass > the Object for future commits to access other fields of Object. > > No functional changes intended. > > Signed-off-by: Alexandre Ghiti Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 15 ++++++++------- > 1 file changed, 8 insertions(+), 7 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index cc75ca7667..7181b34f86 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -200,7 +200,7 @@ static const char * const riscv_intr_names[] = { > "reserved" > }; > > -static void register_cpu_props(DeviceState *dev); > +static void register_cpu_props(Object *obj); > > const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) > { > @@ -238,7 +238,7 @@ static void riscv_any_cpu_init(Object *obj) > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > #endif > set_priv_version(env, PRIV_VERSION_1_12_0); > - register_cpu_props(DEVICE(obj)); > + register_cpu_props(obj); > } > > #if defined(TARGET_RISCV64) > @@ -247,7 +247,7 @@ static void rv64_base_cpu_init(Object *obj) > CPURISCVState *env = &RISCV_CPU(obj)->env; > /* We set this in the realise function */ > set_misa(env, MXL_RV64, 0); > - register_cpu_props(DEVICE(obj)); > + register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > } > @@ -280,7 +280,7 @@ static void rv128_base_cpu_init(Object *obj) > CPURISCVState *env = &RISCV_CPU(obj)->env; > /* We set this in the realise function */ > set_misa(env, MXL_RV128, 0); > - register_cpu_props(DEVICE(obj)); > + register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > } > @@ -290,7 +290,7 @@ static void rv32_base_cpu_init(Object *obj) > CPURISCVState *env = &RISCV_CPU(obj)->env; > /* We set this in the realise function */ > set_misa(env, MXL_RV32, 0); > - register_cpu_props(DEVICE(obj)); > + register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > } > @@ -343,7 +343,7 @@ static void riscv_host_cpu_init(Object *obj) > #elif defined(TARGET_RISCV64) > set_misa(env, MXL_RV64, 0); > #endif > - register_cpu_props(DEVICE(obj)); > + register_cpu_props(obj); > } > #endif > > @@ -1083,9 +1083,10 @@ static Property riscv_cpu_extensions[] = { > DEFINE_PROP_END_OF_LIST(), > }; > > -static void register_cpu_props(DeviceState *dev) > +static void register_cpu_props(Object *obj) > { > Property *prop; > + DeviceState *dev = DEVICE(obj); > > for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > qdev_property_add_static(dev, prop); > -- > 2.37.2 > > From MAILER-DAEMON Sun Jan 15 23:29:00 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHH7D-0007aQ-UF for mharc-qemu-riscv@gnu.org; Sun, 15 Jan 2023 23:28:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHH7B-0007a8-Vg; Sun, 15 Jan 2023 23:28:58 -0500 Received: from mail-vs1-xe2e.google.com ([2607:f8b0:4864:20::e2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHH79-0006CY-UJ; Sun, 15 Jan 2023 23:28:57 -0500 Received: by mail-vs1-xe2e.google.com with SMTP id v127so23521397vsb.12; Sun, 15 Jan 2023 20:28:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; 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Sun, 15 Jan 2023 20:28:54 -0800 (PST) MIME-Version: 1.0 References: <20230113171805.470252-1-dbarboza@ventanamicro.com> <20230113171805.470252-4-dbarboza@ventanamicro.com> In-Reply-To: From: Alistair Francis Date: Mon, 16 Jan 2023 14:28:28 +1000 Message-ID: Subject: Re: [PATCH v7 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym() To: Bin Meng Cc: Daniel Henrique Barboza , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e2e; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 04:28:58 -0000 On Sat, Jan 14, 2023 at 11:41 PM Bin Meng wrote: > > On Sat, Jan 14, 2023 at 1:18 AM Daniel Henrique Barboza > wrote: > > > > Recent hw/risc/boot.c changes caused a regression in an use case with > > the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel' > > stopped working. The reason seems to be that Xvisor is using 64 bit to > > encode the 32 bit addresses from the guest, and load_elf_ram_sym() is > > sign-extending the result with '1's [1]. > > I would say it's not a regression of QEMU but something weird happened > to Alistair's 32-bit Xvisor image. I don't think it's a Xvisor issue. > > I just built a 32-bit Xvisor image from the latest Xvisor head > following the instructions provided in its source tree. With the > mainline QEMU only BIN file boots, but ELF does not. My 32-bit Xvisor > image has an address of 0x10000000. Apparently this address is not > correct, and the issue I saw is different from Alistair's. Alistair, > could you investigate why your 32-bit Xvisor ELF image has an address > of 0xffffffff80000000 set to kernel_load_base? Looking in load_elf() in include/hw/elf_ops.h at this line: if (lowaddr) *lowaddr =3D (uint64_t)(elf_sword)low; I can see that `low` is 0x80000000 but lowaddr is set to 0xffffffff80000000. So the address is being sign extended with 1s. This patch seems to be the correct fix. Alistair > > > > > This can very well be an issue with Xvisor, but since it's not hard to > > amend it in our side we're going for it. Use a translate_fn() callback > > to be called by load_elf_ram_sym() and clear the higher bits of the > > result if we're running a 32 bit CPU. > > > > [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html > > > > Suggested-by: Philippe Mathieu-Daud=C3=A9 > > Suggested-by: Bin Meng > > Signed-off-by: Daniel Henrique Barboza Thanks for the patch. This should be the first patch of the series though, so that we never break guest loading. > > --- > > hw/riscv/boot.c | 23 ++++++++++++++++++++++- > > hw/riscv/microchip_pfsoc.c | 4 ++-- > > hw/riscv/opentitan.c | 3 ++- > > hw/riscv/sifive_e.c | 3 ++- > > hw/riscv/sifive_u.c | 4 ++-- > > hw/riscv/spike.c | 2 +- > > hw/riscv/virt.c | 4 ++-- > > include/hw/riscv/boot.h | 1 + > > 8 files changed, 34 insertions(+), 10 deletions(-) > > > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > > index e868fb6ade..7f8295bf5e 100644 > > --- a/hw/riscv/boot.c > > +++ b/hw/riscv/boot.c > > @@ -213,7 +213,27 @@ static void riscv_load_initrd(MachineState *machin= e, uint64_t kernel_entry) > > } > > } > > > > +static uint64_t translate_kernel_address(void *opaque, uint64_t addr) > > +{ > > + RISCVHartArrayState *harts =3D opaque; > > + > > + /* > > + * For 32 bit CPUs, kernel_load_base is sign-extended (i.e. > > + * it can be padded with '1's) if the hypervisor, for some > > + * reason, is using 64 bit addresses with 32 bit guests. > > + * > > + * Clear the higher bits to avoid the padding if we're > > + * running a 32 bit CPU. > > + */ > > + if (riscv_is_32bit(harts)) { > > + return addr & 0x0fffffff; > > + } > > + > > + return addr; > > +} > > + > > target_ulong riscv_load_kernel(MachineState *machine, > > + RISCVHartArrayState *harts, > > target_ulong kernel_start_addr, > > bool load_initrd, > > symbol_fn_t sym_cb) > > @@ -231,7 +251,8 @@ target_ulong riscv_load_kernel(MachineState *machin= e, > > * the (expected) load address load address. This allows kernels t= o have > > * separate SBI and ELF entry points (used by FreeBSD, for example= ). > > */ > > - if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, > > + if (load_elf_ram_sym(kernel_filename, NULL, > > + translate_kernel_address, NULL, > > NULL, &kernel_load_base, NULL, NULL, 0, > > EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { > > kernel_entry =3D kernel_load_base; > > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > > index c45023a2b1..b7e171b605 100644 > > --- a/hw/riscv/microchip_pfsoc.c > > +++ b/hw/riscv/microchip_pfsoc.c > > @@ -629,8 +629,8 @@ static void microchip_icicle_kit_machine_init(Machi= neState *machine) > > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_c= pus, > > firmware_end_= addr); > > > > - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, > > - true, NULL); > > + kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, > > + kernel_start_addr, true, NULL= ); > > > > /* Compute the fdt load address in dram */ > > fdt_load_addr =3D riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_L= O].base, > > diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c > > index f6fd9725a5..1404a52da0 100644 > > --- a/hw/riscv/opentitan.c > > +++ b/hw/riscv/opentitan.c > > @@ -101,7 +101,8 @@ static void opentitan_board_init(MachineState *mach= ine) > > } > > > > if (machine->kernel_filename) { > > - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, false, N= ULL); > > + riscv_load_kernel(machine, &s->soc.cpus, > > + memmap[IBEX_DEV_RAM].base, false, NULL); > > } > > } > > > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > > index 6835d1c807..04939b60c3 100644 > > --- a/hw/riscv/sifive_e.c > > +++ b/hw/riscv/sifive_e.c > > @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *mac= hine) > > memmap[SIFIVE_E_DEV_MROM].base, &address_spa= ce_memory); > > > > if (machine->kernel_filename) { > > - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, > > + riscv_load_kernel(machine, &s->soc.cpus, > > + memmap[SIFIVE_E_DEV_DTIM].base, > > false, NULL); > > } > > } > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > > index 9a75d4aa62..214430d40c 100644 > > --- a/hw/riscv/sifive_u.c > > +++ b/hw/riscv/sifive_u.c > > @@ -598,8 +598,8 @@ static void sifive_u_machine_init(MachineState *mac= hine) > > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_c= pus, > > firmware_end_= addr); > > > > - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, > > - true, NULL); > > + kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, > > + kernel_start_addr, true, NULL= ); > > } else { > > /* > > * If dynamic firmware is used, it doesn't know where is the ne= xt mode > > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > > index c517885e6e..b3aac2178b 100644 > > --- a/hw/riscv/spike.c > > +++ b/hw/riscv/spike.c > > @@ -307,7 +307,7 @@ static void spike_board_init(MachineState *machine) > > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], > > firmware_end_= addr); > > > > - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, > > + kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], kernel= _start_addr, > > true, htif_symbol_callback); > > } else { > > /* > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > > index a931ed05ab..60c8729b5f 100644 > > --- a/hw/riscv/virt.c > > +++ b/hw/riscv/virt.c > > @@ -1281,8 +1281,8 @@ static void virt_machine_done(Notifier *notifier,= void *data) > > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], > > firmware_end_= addr); > > > > - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, > > - true, NULL); > > + kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], > > + kernel_start_addr, true, NULL= ); > > } else { > > /* > > * If dynamic firmware is used, it doesn't know where is the ne= xt mode > > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h > > index cbd131bad7..bc9faed397 100644 > > --- a/include/hw/riscv/boot.h > > +++ b/include/hw/riscv/boot.h > > @@ -44,6 +44,7 @@ target_ulong riscv_load_firmware(const char *firmware= _filename, > > hwaddr firmware_load_addr, > > symbol_fn_t sym_cb); > > target_ulong riscv_load_kernel(MachineState *machine, > > + RISCVHartArrayState *harts, > > target_ulong firmware_end_addr, > > bool load_initrd, > > symbol_fn_t sym_cb); > > Regards, > Bin > From MAILER-DAEMON Sun Jan 15 23:35:52 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHHDq-00016r-Au for mharc-qemu-riscv@gnu.org; Sun, 15 Jan 2023 23:35:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHHDj-0000wm-Hv; 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c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=z2i207XY0wpyl4uN0PC9a2HsYtkx8YDQWX6ZUNhml+I=; b=bednxPcnEeNSihUUzxg1vtqWP5SmyMHQ5HSMECwuEOnt8NSpiuYodKBzdCwBshHM/U peqaYCk64p32HT9JySOu9hbsm2GYtfcqRq/7nYU0E1WRfjED9ZQJ+AlQzgDhzhR1rgkq ApM4BaXQ/zuIicQzzMjrSstbuY4iCoTfonScL1ZaaUGhzrzfLiaZTiUXzbYpQPGpdrVR 9gteZWCCpMCnehRUfKFQUHsXcdcxK/8yUpVlJ3SHs/+4yoZebgvfXJf4m5IbrDTj1+CP h9r7AA6uHS+fCpdctqqLoHx7wTicz4M2U3nkE/NsW+dY+UIk4GW8xi56l9xygQd2CyZB ZWVA== X-Gm-Message-State: AFqh2koxpYWMzY/QDupbYDPc++JHmjBtgpf1Ue7+ABHIn+aOdIK0bdri RzQDw74g/V62W1Or+9NEdSZS477Zhp7M2Y1txcY= X-Google-Smtp-Source: AMrXdXskC5cDKi8qnbzagpSV6KLpmw7eIOoZVaASEvfFh99vIu1lqZHd5ZYgTZgZdtKnsTiHwwP+l5bTEFYD6vE9bKA= X-Received: by 2002:a05:6122:2323:b0:3e1:7e08:a117 with SMTP id bq35-20020a056122232300b003e17e08a117mr23133vkb.34.1673843740643; Sun, 15 Jan 2023 20:35:40 -0800 (PST) MIME-Version: 1.0 References: <20221215224541.1423431-1-abrestic@rivosinc.com> In-Reply-To: <20221215224541.1423431-1-abrestic@rivosinc.com> From: Alistair Francis Date: Mon, 16 Jan 2023 14:35:14 +1000 Message-ID: Subject: Re: [PATCH 1/2] target/riscv: Fix up masking of vsip/vsie accesses To: Andrew Bresticker Cc: qemu-devel@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng , qemu-riscv@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::a2e; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 04:35:45 -0000 On Fri, Dec 16, 2022 at 8:46 AM Andrew Bresticker wrote: > > The current logic attempts to shift the VS-level bits into their correct > position in mip while leaving the remaining bits in-tact. This is both > pointless and likely incorrect since one would expect that any new, future > VS-level interrupts will get their own position in mip rather than sharing > with their (H)S-level equivalent. Fix this, and make the logic more > readable, by just making off the VS-level bits and shifting them into > position. > > This also fixes reads of vsip, which would only ever report vsip.VSSIP > since the non-writable bits got masked off as well. > > Fixes: d028ac7512f1 ("arget/riscv: Implement AIA CSRs for 64 local interrupts on RV32") > Signed-off-by: Andrew Bresticker Reviewed-by: Alistair Francis Alistair > --- > target/riscv/csr.c | 35 +++++++++++------------------------ > 1 file changed, 11 insertions(+), 24 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 5c9a7ee287..984548bf87 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1975,22 +1975,15 @@ static RISCVException rmw_vsie64(CPURISCVState *env, int csrno, > uint64_t new_val, uint64_t wr_mask) > { > RISCVException ret; > - uint64_t rval, vsbits, mask = env->hideleg & VS_MODE_INTERRUPTS; > + uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS; > > /* Bring VS-level bits to correct position */ > - vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); > - new_val &= ~(VS_MODE_INTERRUPTS >> 1); > - new_val |= vsbits << 1; > - vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); > - wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); > - wr_mask |= vsbits << 1; > + new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1; > + wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1; > > ret = rmw_mie64(env, csrno, &rval, new_val, wr_mask & mask); > if (ret_val) { > - rval &= mask; > - vsbits = rval & VS_MODE_INTERRUPTS; > - rval &= ~VS_MODE_INTERRUPTS; > - *ret_val = rval | (vsbits >> 1); > + *ret_val = (rval & mask) >> 1; > } > > return ret; > @@ -2191,22 +2184,16 @@ static RISCVException rmw_vsip64(CPURISCVState *env, int csrno, > uint64_t new_val, uint64_t wr_mask) > { > RISCVException ret; > - uint64_t rval, vsbits, mask = env->hideleg & vsip_writable_mask; > + uint64_t rval, mask = env->hideleg & VS_MODE_INTERRUPTS; > > /* Bring VS-level bits to correct position */ > - vsbits = new_val & (VS_MODE_INTERRUPTS >> 1); > - new_val &= ~(VS_MODE_INTERRUPTS >> 1); > - new_val |= vsbits << 1; > - vsbits = wr_mask & (VS_MODE_INTERRUPTS >> 1); > - wr_mask &= ~(VS_MODE_INTERRUPTS >> 1); > - wr_mask |= vsbits << 1; > - > - ret = rmw_mip64(env, csrno, &rval, new_val, wr_mask & mask); > + new_val = (new_val & (VS_MODE_INTERRUPTS >> 1)) << 1; > + wr_mask = (wr_mask & (VS_MODE_INTERRUPTS >> 1)) << 1; > + > + ret = rmw_mip64(env, csrno, &rval, new_val, > + wr_mask & mask & vsip_writable_mask); > if (ret_val) { > - rval &= mask; > - vsbits = rval & VS_MODE_INTERRUPTS; > - rval &= ~VS_MODE_INTERRUPTS; > - *ret_val = rval | (vsbits >> 1); > + *ret_val = (rval & mask) >> 1; > } > > return ret; > -- > 2.25.1 > > From MAILER-DAEMON Sun Jan 15 23:39:01 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHHGv-0002lS-5E for mharc-qemu-riscv@gnu.org; Sun, 15 Jan 2023 23:39:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHHGt-0002l8-MM; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e35; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe35.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 04:39:00 -0000 On Fri, Dec 16, 2022 at 8:46 AM Andrew Bresticker wrote: > > Per the AIA specification, writes to stimecmp from VS level should > trap when hvictl.VTI is set since the write may cause vsip.STIP to > become unset. > > Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp support") > Signed-off-by: Andrew Bresticker Reviewed-by: Alistair Francis Alistair > --- > target/riscv/csr.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 984548bf87..7d9035e7bb 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -935,6 +935,9 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno, > RISCVCPU *cpu = env_archcpu(env); > > if (riscv_cpu_virt_enabled(env)) { > + if (env->hvictl & HVICTL_VTI) { > + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; > + } > return write_vstimecmp(env, csrno, val); > } > > @@ -955,6 +958,9 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno, > RISCVCPU *cpu = env_archcpu(env); > > if (riscv_cpu_virt_enabled(env)) { > + if (env->hvictl & HVICTL_VTI) { > + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; > + } > return write_vstimecmph(env, csrno, val); > } > > -- > 2.25.1 > > From MAILER-DAEMON Mon Jan 16 00:57:21 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHIUj-0006ii-3d for mharc-qemu-riscv@gnu.org; Mon, 16 Jan 2023 00:57:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHIUh-0006iP-D3 for qemu-riscv@nongnu.org; Mon, 16 Jan 2023 00:57:19 -0500 Received: from mail-qv1-xf2a.google.com ([2607:f8b0:4864:20::f2a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHIUe-0003oK-P4 for qemu-riscv@nongnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::f2a; envelope-from=apatel@ventanamicro.com; helo=mail-qv1-xf2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 05:57:19 -0000 Hi Alistair, On Tue, Jan 3, 2023 at 9:43 PM Anup Patel wrote: > > Hi Alistair, > > On Wed, Dec 28, 2022 at 11:08 AM Alistair Francis wrote: > > > > On Fri, Dec 23, 2022 at 11:14 PM Anup Patel wrote: > > > > > > On Thu, Dec 15, 2022 at 8:55 AM Alistair Francis wrote: > > > > > > > > On Mon, Dec 12, 2022 at 9:12 PM Anup Patel wrote: > > > > > > > > > > On Mon, Dec 12, 2022 at 11:23 AM Alistair Francis wrote: > > > > > > > > > > > > On Thu, Dec 8, 2022 at 6:41 PM Anup Patel wrote: > > > > > > > > > > > > > > On Thu, Dec 8, 2022 at 9:00 AM Alistair Francis wrote: > > > > > > > > > > > > > > > > On Tue, Nov 8, 2022 at 11:07 PM Anup Patel wrote: > > > > > > > > > > > > > > > > > > The htimedelta[h] CSR has impact on the VS timer comparison so we > > > > > > > > > should call riscv_timer_write_timecmp() whenever htimedelta changes. > > > > > > > > > > > > > > > > > > Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") > > > > > > > > > Signed-off-by: Anup Patel > > > > > > > > > Reviewed-by: Alistair Francis > > > > > > > > > > > > > > > > This patch breaks my Xvisor test. When running OpenSBI and Xvisor like this: > > > > > > > > > > > > > > > > qemu-system-riscv64 -machine virt \ > > > > > > > > -m 1G -serial mon:stdio -serial null -nographic \ > > > > > > > > -append 'vmm.console=uart@10000000 vmm.bootcmd="vfs mount initrd > > > > > > > > /;vfs run /boot.xscript;vfs cat /system/banner.txt; guest kick guest0; > > > > > > > > vserial bind guest0/uart0"' \ > > > > > > > > -smp 4 -d guest_errors \ > > > > > > > > -bios none \ > > > > > > > > -device loader,file=./images/qemuriscv64/vmm.bin,addr=0x80200000 \ > > > > > > > > -kernel ./images/qemuriscv64/fw_jump.elf \ > > > > > > > > -initrd ./images/qemuriscv64/vmm-disk-linux.img -cpu rv64,h=true > > > > > > > > > > > > > > > > Running: > > > > > > > > > > > > > > > > Xvisor v0.3.0-129-gbc33f339 (Jan 1 1970 00:00:00) > > > > > > > > > > > > > > > > I see this failure: > > > > > > > > > > > > > > > > INIT: bootcmd: guest kick guest0 > > > > > > > > > > > > > > > > guest0: Kicked > > > > > > > > > > > > > > > > INIT: bootcmd: vserial bind guest0/uart0 > > > > > > > > > > > > > > > > [guest0/uart0] cpu_vcpu_stage2_map: guest_phys=0x000000003B9AC000 > > > > > > > > size=0x4096 map failed > > > > > > > > > > > > > > > > do_error: CPU3: VCPU=guest0/vcpu0 page fault failed (error -1) > > > > > > > > > > > > > > > > zero=0x0000000000000000 ra=0x0000000080001B4E > > > > > > > > > > > > > > > > sp=0x000000008001CF80 gp=0x0000000000000000 > > > > > > > > > > > > > > > > tp=0x0000000000000000 s0=0x000000008001CFB0 > > > > > > > > > > > > > > > > s1=0x0000000000000000 a0=0x0000000010001048 > > > > > > > > > > > > > > > > a1=0x0000000000000000 a2=0x0000000000989680 > > > > > > > > > > > > > > > > a3=0x000000003B9ACA00 a4=0x0000000000000048 > > > > > > > > > > > > > > > > a5=0x0000000000000000 a6=0x0000000000019000 > > > > > > > > > > > > > > > > a7=0x0000000000000000 s2=0x0000000000000000 > > > > > > > > > > > > > > > > s3=0x0000000000000000 s4=0x0000000000000000 > > > > > > > > > > > > > > > > s5=0x0000000000000000 s6=0x0000000000000000 > > > > > > > > > > > > > > > > s7=0x0000000000000000 s8=0x0000000000000000 > > > > > > > > > > > > > > > > s9=0x0000000000000000 s10=0x0000000000000000 > > > > > > > > > > > > > > > > s11=0x0000000000000000 t0=0x0000000000004000 > > > > > > > > > > > > > > > > t1=0x0000000000000100 t2=0x0000000000000000 > > > > > > > > > > > > > > > > t3=0x0000000000000000 t4=0x0000000000000000 > > > > > > > > > > > > > > > > t5=0x0000000000000000 t6=0x0000000000000000 > > > > > > > > > > > > > > > > sepc=0x0000000080001918 sstatus=0x0000000200004120 > > > > > > > > > > > > > > > > hstatus=0x00000002002001C0 sp_exec=0x0000000010A64000 > > > > > > > > > > > > > > > > scause=0x0000000000000017 stval=0x000000003B9ACAF8 > > > > > > > > > > > > > > > > htval=0x000000000EE6B2BE htinst=0x0000000000D03021 > > > > > > > > > > > > > > > > I have tried updating to a newer Xvisor release, but with that I don't > > > > > > > > get any serial output. > > > > > > > > > > > > > > > > Can you help get the Xvisor tests back up and running? > > > > > > > > > > > > > > I tried the latest Xvisor-next (https://github.com/avpatel/xvisor-next) > > > > > > > with your QEMU riscv-to-apply.next branch and it works fine (both > > > > > > > with and without Sstc). > > > > > > > > > > > > Does it work with the latest release? > > > > > > > > > > Yes, the latest Xvisor-next repo works for QEMU v7.2.0-rc4 and > > > > > your riscv-to-apply.next branch (commit 51bb9de2d188) > > > > > > > > I can't get anything to work with this patch. I have dropped this and > > > > the patches after this. > > > > > > > > I'm building the latest Xvisor release with: > > > > > > > > export CROSS_COMPILE=riscv64-linux-gnu- > > > > ARCH=riscv make generic-64b-defconfig > > > > make > > > > > > > > and running it as above, yet nothing. What am I missing here? > > > > > > I tried multiple times with the latest Xvisor on different machines but > > > still can't reproduce the issue you are seeing. > > > > Odd > > > > > > > > We generally provide pre-built binaries with every Xvisor release > > > so I will share with you pre-built binaries of the upcoming Xvisor-0.3.2 > > > release. Maybe that would help you ? > > > > That would work. Let me know when the release happens and I can update > > my images. > > Please download the Xvisor v0.3.2 pre-built binary tarball from: > https://xhypervisor.org/tarball/xvisor-0.3.2-bins.tar.xz > > After untarring the above tarball, you can try the following command: > $ qemu-system-riscv64 -M virt -m 512M -nographic -bios > opensbi/build/platform/generic/firmware/fw_jump.bin -kernel > xvisor-0.3.2-bins/riscv/rv64/xvisor/vmm.bin -initrd > xvisor-0.3.2-bins/riscv/rv64/guest/virt64/disk-linux-6.1.1-one_guest_virt64.ext2 > -append "vmm.bootcmd=\"vfs mount initrd /;vfs run /boot.xscript;vfs > cat /system/banner.txt\"" > OR > $ qemu-system-riscv32 -M virt -m 512M -nographic -bios > opensbi/build/platform/generic/firmware/fw_jump.bin -kernel > xvisor-0.3.2-bins/riscv/rv32/xvisor/vmm.bin -initrd > xvisor-0.3.2-bins/riscv/rv32/guest/virt32/disk-linux-6.1.1-one_guest_virt32.ext2 > -append "vmm.bootcmd=\"vfs mount initrd /;vfs run /boot.xscript;vfs > cat /system/banner.txt\"" Do you want me to rebase and resend the patches which are not merged ? Regards, Anup From MAILER-DAEMON Mon Jan 16 00:59:24 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHIWh-0007nC-FA for mharc-qemu-riscv@gnu.org; Mon, 16 Jan 2023 00:59:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHIWW-0007aB-7p; Mon, 16 Jan 2023 00:59:15 -0500 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHIWR-0004Yq-Bh; Mon, 16 Jan 2023 00:59:08 -0500 Received: by mail-pg1-x532.google.com with SMTP id f3so18944835pgc.2; Sun, 15 Jan 2023 21:59:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=PZSoNavF47DlJv5tWW3a381+KKvDxpiX/lXLvUhxTV0=; b=Dlb1lROXKoBri2a9SMtNtbqa70brVxlW+PCeySPhTZm2e3jXlYaFC6rVAln+nWgy2x K3H74Mo2wnMoFmhqFY8SAHU1th0FKtLggbhcH3GdPw5z0B9pUobYCDnN64SRJ7GdWAMk L1uW8vug3q0Oua0R2FWRBMGXZDbJkotjLvOcqcuD7bVjuFfB0zR2D5sHrK1svqVofpGN ab9ecmjOWnWL2i6EXJl26DGYmWkMaMDw8AH1TmhnxlWIILoMt7gbwG40epfGhCQwhj82 Ga6fMYLZT10oi7bYdrBVGSOCgVoocdpGLsz1MCvfyuhcQsXlQi9nBjCq9JjSgBa+izie B5uA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=PZSoNavF47DlJv5tWW3a381+KKvDxpiX/lXLvUhxTV0=; b=iyBNWqDKS8CxEedKQJQ2eV1c1HVSkcw6UMmCi9gAn3umKZMw2d21IuJFtSZRpdulFe BWGsqU2fh8/5f8563YYi0QaWLYG6iQVxGSC4UgVqHvNQZAe+RgjQTzskG1Tl/54Jg1l7 e2XRh8GPgXUkPLeCgB3Kl18367f2D4dhYwrow0K7LoSz2vBla1qrQs41Zz8IYKloel2s zO5CwUq7lraMJEv9tlTQmOJsLV81YaFl4pbB1h1JlVXJst4QsKD6ra9APKpwDtgxmB83 u1grl4Ep7zo9llflM7zafKbZCmvq/BQDQRrb1bzMlkOXv24PzOs7pt9eVS9szMTy7wQh pPEA== X-Gm-Message-State: AFqh2kqw3o/O+6IvKTqh31ddof2kdcHW1VIf8wXatp+w/npb3EpYAJ3R Zi272zjvXmjv7bw8rWOphNRtqJYPH5syBPTKTQ1gOQGZ+7/xTw== X-Google-Smtp-Source: AMrXdXsaIBsO6AqGITE932OfiU1DBlDTxyuYRkjQFKuSOs+ST6OLkpXQKmpqk4o19XzUTIDzHpgwrCHKGrj3LNcpx1g= X-Received: by 2002:a05:6102:510e:b0:3b1:2b83:1861 with SMTP id bm14-20020a056102510e00b003b12b831861mr11678769vsb.10.1673846709549; Sun, 15 Jan 2023 21:25:09 -0800 (PST) MIME-Version: 1.0 References: <20221215224541.1423431-1-abrestic@rivosinc.com> <20221215224541.1423431-2-abrestic@rivosinc.com> In-Reply-To: <20221215224541.1423431-2-abrestic@rivosinc.com> From: Alistair Francis Date: Mon, 16 Jan 2023 15:24:43 +1000 Message-ID: Subject: Re: [PATCH 2/2] target/riscv: Trap on writes to stimecmp from VS when hvictl.VTI=1 To: Andrew Bresticker Cc: qemu-devel@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng , qemu-riscv@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=alistair23@gmail.com; helo=mail-pg1-x532.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 05:59:21 -0000 On Fri, Dec 16, 2022 at 8:46 AM Andrew Bresticker wrote: > > Per the AIA specification, writes to stimecmp from VS level should > trap when hvictl.VTI is set since the write may cause vsip.STIP to > become unset. > > Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp support") > Signed-off-by: Andrew Bresticker Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/csr.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 984548bf87..7d9035e7bb 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -935,6 +935,9 @@ static RISCVException write_stimecmp(CPURISCVState *env, int csrno, > RISCVCPU *cpu = env_archcpu(env); > > if (riscv_cpu_virt_enabled(env)) { > + if (env->hvictl & HVICTL_VTI) { > + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; > + } > return write_vstimecmp(env, csrno, val); > } > > @@ -955,6 +958,9 @@ static RISCVException write_stimecmph(CPURISCVState *env, int csrno, > RISCVCPU *cpu = env_archcpu(env); > > if (riscv_cpu_virt_enabled(env)) { > + if (env->hvictl & HVICTL_VTI) { > + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; > + } > return write_vstimecmph(env, csrno, val); > } > > -- > 2.25.1 > > From MAILER-DAEMON Mon Jan 16 04:25:42 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHLkD-0005M1-P0 for mharc-qemu-riscv@gnu.org; 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Mon, 16 Jan 2023 01:25:21 -0800 (PST) Message-ID: <1ff4c868-f39f-21e0-2030-a78163143233@linaro.org> Date: Mon, 16 Jan 2023 10:25:19 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v7 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym() Content-Language: en-US To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng References: <20230113171805.470252-1-dbarboza@ventanamicro.com> <20230113171805.470252-4-dbarboza@ventanamicro.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230113171805.470252-4-dbarboza@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 09:25:30 -0000 On 13/1/23 18:18, Daniel Henrique Barboza wrote: > Recent hw/risc/boot.c changes caused a regression in an use case with > the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel' > stopped working. The reason seems to be that Xvisor is using 64 bit to > encode the 32 bit addresses from the guest, and load_elf_ram_sym() is > sign-extending the result with '1's [1]. > > This can very well be an issue with Xvisor, but since it's not hard to > amend it in our side we're going for it. Use a translate_fn() callback > to be called by load_elf_ram_sym() and clear the higher bits of the > result if we're running a 32 bit CPU. > > [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html > > Suggested-by: Philippe Mathieu-Daudé > Suggested-by: Bin Meng > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/boot.c | 23 ++++++++++++++++++++++- > hw/riscv/microchip_pfsoc.c | 4 ++-- > hw/riscv/opentitan.c | 3 ++- > hw/riscv/sifive_e.c | 3 ++- > hw/riscv/sifive_u.c | 4 ++-- > hw/riscv/spike.c | 2 +- > hw/riscv/virt.c | 4 ++-- > include/hw/riscv/boot.h | 1 + > 8 files changed, 34 insertions(+), 10 deletions(-) > +static uint64_t translate_kernel_address(void *opaque, uint64_t addr) > +{ > + RISCVHartArrayState *harts = opaque; > + > + /* > + * For 32 bit CPUs, kernel_load_base is sign-extended (i.e. > + * it can be padded with '1's) if the hypervisor, for some > + * reason, is using 64 bit addresses with 32 bit guests. > + * > + * Clear the higher bits to avoid the padding if we're > + * running a 32 bit CPU. > + */ > + if (riscv_is_32bit(harts)) { > + return addr & 0x0fffffff; Instead of this magic mask, can we add some architectural definition in target/riscv/cpu_bits.h and use it as: return extract64(addr, 0, xxx_ADDR_BITS); to make the code self-descriptive? Otherwise LGTM, thanks! > + } > + > + return addr; > +} From MAILER-DAEMON Mon Jan 16 07:30:06 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHOco-0008Tq-5s for mharc-qemu-riscv@gnu.org; Mon, 16 Jan 2023 07:30:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHOcj-0008Po-50 for qemu-riscv@nongnu.org; Mon, 16 Jan 2023 07:30:01 -0500 Received: from mail-oi1-x22f.google.com ([2607:f8b0:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHOcg-0003H8-Nd for qemu-riscv@nongnu.org; Mon, 16 Jan 2023 07:30:00 -0500 Received: by mail-oi1-x22f.google.com with SMTP id n8so23246037oih.0 for ; Mon, 16 Jan 2023 04:29:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RmlaSf4agWGz7+gWU7Vna+xOkpByetLr1UplEidZSlY=; b=ncuTX8Jhn+wW3IUD+9wGSMQMdtl4tJSwvCdS9K4NNNZVA0yUPR4U2WAHbavcWbzQaz ghVbLHJ/0d+IvzLx6lq/Vqw4pS3kfcJfxHylyz2y42i7KiACluqVnwOfsGQManF/1Q7N buLYh/mkUrgYzohD8rbFUmifLrm1RcqFl8j/G+OWFyAk0ltS2HDxjnHEkmRKWjIcadYl 35quM0sK0YTyDAgOASnxiRg237Yd8U8muU9Uto2h5xFTN0L563LeoC1zIRsZ1zW3WvVp C1+bkIMYmFQHu1CI6QMLO8PkuUKcnOdpAnulINgN5iPolpjQG1xrr5lcEMY1pER9AxbI 6HAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RmlaSf4agWGz7+gWU7Vna+xOkpByetLr1UplEidZSlY=; b=JLYJhRJFkBOsdQ6jcrsZVn2cq+nkq7Li54FItIaGQkYDAfiSavMTaGLeC4LLiIzFwe fEygPl3ZEpbc5WXude6iP+GZMs3p8ZO5KrXA8Jy58M1uGuLz/kD586VzpRPMoJJmx6yt vKQiTY4VTNLc+6p3w64z/TFrRRWlWhWN3gxR449frc73ot4tl5Xgf++GkVfOpWiC9kKs aDZnPHD6Bwj2ZXV6pxDPjo5rgpo+KcJANoSyd0JXPDkVY1tDH5ofNW6aeVCXlIUlPgGd XTfOSh46vLIehqiTt9FbmO/vbURaxGjtDheUtwcCJ4sF6K9pNBv3HunSVWTSIOcpA3XL LZ/g== X-Gm-Message-State: AFqh2krwshLv+2WEqq72ALiQqs2BhWI/zRxxLrC7JiNaTgHFHKFADJiv 0CrBrHCCHjouvODFj+5EwetV6z3ZFiSi0OZybUY= X-Google-Smtp-Source: AMrXdXsT8K0WhEgNbu90eYblQ6J3JRsS/N51z0C1f/Y/sN97zIqDE1ZYhWnIvVNrkbEl6hxwrvhn4Q== X-Received: by 2002:aca:e155:0:b0:364:ebef:819b with SMTP id y82-20020acae155000000b00364ebef819bmr2280124oig.28.1673872197323; Mon, 16 Jan 2023 04:29:57 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id g21-20020a0568080dd500b00360f68d509csm12814540oic.49.2023.01.16.04.29.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 04:29:56 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Palmer Dabbelt , Bin Meng Subject: [PATCH v8 1/3] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() Date: Mon, 16 Jan 2023 09:29:46 -0300 Message-Id: <20230116122948.757515-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230116122948.757515-1-dbarboza@ventanamicro.com> References: <20230116122948.757515-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 12:30:03 -0000 The microchip_icicle_kit, sifive_u, spike and virt boards are now doing the same steps when '-kernel' is used: - execute load_kernel() - load init_rd() - write kernel_cmdline Let's fold everything inside riscv_load_kernel() to avoid code repetition. To not change the behavior of boards that aren't calling riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and allow these boards to opt out from initrd loading. Cc: Palmer Dabbelt Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 22 +++++++++++++++++++--- hw/riscv/microchip_pfsoc.c | 12 ++---------- hw/riscv/opentitan.c | 2 +- hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 12 ++---------- hw/riscv/spike.c | 11 +---------- hw/riscv/virt.c | 12 ++---------- include/hw/riscv/boot.h | 1 + 8 files changed, 30 insertions(+), 45 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 2594276223..4888d5c1e0 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -175,10 +175,12 @@ target_ulong riscv_load_firmware(const char *firmware_filename, target_ulong riscv_load_kernel(MachineState *machine, target_ulong kernel_start_addr, + bool load_initrd, symbol_fn_t sym_cb) { const char *kernel_filename = machine->kernel_filename; uint64_t kernel_load_base, kernel_entry; + void *fdt = machine->fdt; g_assert(kernel_filename != NULL); @@ -192,21 +194,35 @@ target_ulong riscv_load_kernel(MachineState *machine, if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL, &kernel_load_base, NULL, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { - return kernel_load_base; + kernel_entry = kernel_load_base; + goto out; } if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, NULL, NULL, NULL) > 0) { - return kernel_entry; + goto out; } if (load_image_targphys_as(kernel_filename, kernel_start_addr, current_machine->ram_size, NULL) > 0) { - return kernel_start_addr; + kernel_entry = kernel_start_addr; + goto out; } error_report("could not load kernel '%s'", kernel_filename); exit(1); + +out: + if (load_initrd && machine->initrd_filename) { + riscv_load_initrd(machine, kernel_entry); + } + + if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } + + return kernel_entry; } void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 82ae5e7023..c45023a2b1 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -629,16 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", - "bootargs", machine->kernel_cmdline); - } + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, + true, NULL); /* Compute the fdt load address in dram */ fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 64d5d435b9..f6fd9725a5 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -101,7 +101,7 @@ static void opentitan_board_init(MachineState *machine) } if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); + riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, false, NULL); } } diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 3e3f4b0088..6835d1c807 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL); + riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, + false, NULL); } } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 2fb6ee231f..ccad386920 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -598,16 +598,8 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, + true, NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index badc11ec43..91bf194ec1 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -306,16 +306,7 @@ static void spike_board_init(MachineState *machine) firmware_end_addr); kernel_entry = riscv_load_kernel(machine, kernel_start_addr, - htif_symbol_callback); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + true, htif_symbol_callback); } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e6d4f06e8d..e374b58f89 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1281,16 +1281,8 @@ static void virt_machine_done(Notifier *notifier, void *data) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, + true, NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index f94653a09b..c3de897371 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -45,6 +45,7 @@ target_ulong riscv_load_firmware(const char *firmware_filename, symbol_fn_t sym_cb); target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, + bool load_initrd, symbol_fn_t sym_cb); void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); -- 2.39.0 From MAILER-DAEMON Mon Jan 16 07:30:07 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHOco-0008VF-RI for mharc-qemu-riscv@gnu.org; Mon, 16 Jan 2023 07:30:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHOcj-0008Pu-Uh for qemu-riscv@nongnu.org; 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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id g21-20020a0568080dd500b00360f68d509csm12814540oic.49.2023.01.16.04.29.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 04:29:54 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v8 0/3] hw/riscv: clear kernel_entry high bits with 32bit CPUs Date: Mon, 16 Jan 2023 09:29:45 -0300 Message-Id: <20230116122948.757515-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::41; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x41.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 12:30:03 -0000 Hi, This version has changes in patch 3 where we're now using extract64() instead of a plain bit mask to return the 32 bit address in translate_fn(). Changes from v7: - patch 2: - added Alistair's r-b - patch 3: - use extract64() to return the 32 bit address v7 link: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02916.html Daniel Henrique Barboza (3): hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() hw/riscv/boot.c: make riscv_load_initrd() static hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym() hw/riscv/boot.c | 108 ++++++++++++++++++++++++------------- hw/riscv/microchip_pfsoc.c | 12 +---- hw/riscv/opentitan.c | 3 +- hw/riscv/sifive_e.c | 4 +- hw/riscv/sifive_u.c | 12 +---- hw/riscv/spike.c | 13 +---- hw/riscv/virt.c | 12 +---- include/hw/riscv/boot.h | 3 +- target/riscv/cpu_bits.h | 1 + 9 files changed, 87 insertions(+), 81 deletions(-) -- 2.39.0 From MAILER-DAEMON Mon Jan 16 07:30:08 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHOcq-00006d-2u for mharc-qemu-riscv@gnu.org; Mon, 16 Jan 2023 07:30:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHOcm-0008RJ-AU for qemu-riscv@nongnu.org; Mon, 16 Jan 2023 07:30:04 -0500 Received: from mail-oi1-x236.google.com ([2607:f8b0:4864:20::236]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHOcj-0003HU-15 for qemu-riscv@nongnu.org; Mon, 16 Jan 2023 07:30:02 -0500 Received: by mail-oi1-x236.google.com with SMTP id p185so2116089oif.2 for ; Mon, 16 Jan 2023 04:30:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f0lm/oJWWa+MhCTCBNn1qSE+0b1IOIjShGN0DTgF9G0=; b=h1+4w2EBwnvQF8wqn49/RJfMEkwMYGDou0CpmL1o0Vf/KaZUTyA5ln/1BWC8uSEXMV rKKBuN2QA6kGEu9Lhmjqq2Zsuugt9cIM+aCVREde3DYU/XFpF9RAMaupu2B+6Cou2/Ya plTDLvB0ZrRXo7xm3oycHNzldUm7R5g9szc/qvCuYqxS/vuNHRZgcn1pXO/hCQIjey/U FoWA0YLcfX7LrhMZpanfrjc4qdnf6RpfS87+dpxthTjmw3HIUrC4PZXVdx8bGLvKXp2u OYhlf+3ipSUoRwndsg/iel/v8aagJnAJbCTbhXqW5wUbal4RdNbQhcs9TJH5bcqs7UT/ hKng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f0lm/oJWWa+MhCTCBNn1qSE+0b1IOIjShGN0DTgF9G0=; b=TFMnH1sJbiXTmEsHWPrT1YWPCHE6tDha0CYQ7qA9dIVYJE3fy+afjyithfm/m0ial0 USKvHx9NGP7D0wh4jfQcCE2/rE7aNppRw4a5dxVpnmCy8J5WgR2ImQAqRs8QzPlcpLPS JIbksZHcZPODQufBUzY0eItZ3WIiwKk6agQ0vlBNMxEPxVYtAKq47Ap0hDqMqqYoBwHf 3XmvrldKWOJPc5zbUjbGSsjpRpZ+lwwoX7N4/FL9f6vCBXtPisfDKpr3oESMmpgGeuS6 lkVrri+wUjJTegrJvaAG5lgv8nsYj3mlYXznKGJy8Z8lP5xjbT7ybI8oIoevtwf2u6+W rJvQ== X-Gm-Message-State: AFqh2koDsbNSzS/FxQunzCGSMAfnSeKAbn8LVxSjnxALb6NMSTPZ4YPf jbbcJCGQsgA04aWlw/2ccCw2RQ== X-Google-Smtp-Source: AMrXdXsWgbJjcH3qLpHVUENAO3DAbs8UbuOsMr9zpY20u4pAyk/6/Lt9TjT6ozCnGHxjpf/00obJMA== X-Received: by 2002:a05:6808:21a9:b0:364:5c9b:5f7d with SMTP id be41-20020a05680821a900b003645c9b5f7dmr13813466oib.22.1673872200017; Mon, 16 Jan 2023 04:30:00 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id g21-20020a0568080dd500b00360f68d509csm12814540oic.49.2023.01.16.04.29.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 04:29:59 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v8 2/3] hw/riscv/boot.c: make riscv_load_initrd() static Date: Mon, 16 Jan 2023 09:29:47 -0300 Message-Id: <20230116122948.757515-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230116122948.757515-1-dbarboza@ventanamicro.com> References: <20230116122948.757515-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 12:30:04 -0000 The only remaining caller is riscv_load_kernel_and_initrd() which belongs to the same file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/boot.c | 80 ++++++++++++++++++++--------------------- include/hw/riscv/boot.h | 1 - 2 files changed, 40 insertions(+), 41 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 4888d5c1e0..e868fb6ade 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -173,6 +173,46 @@ target_ulong riscv_load_firmware(const char *firmware_filename, exit(1); } +static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) +{ + const char *filename = machine->initrd_filename; + uint64_t mem_size = machine->ram_size; + void *fdt = machine->fdt; + hwaddr start, end; + ssize_t size; + + g_assert(filename != NULL); + + /* + * We want to put the initrd far enough into RAM that when the + * kernel is uncompressed it will not clobber the initrd. However + * on boards without much RAM we must ensure that we still leave + * enough room for a decent sized initrd, and on boards with large + * amounts of RAM we must avoid the initrd being so far up in RAM + * that it is outside lowmem and inaccessible to the kernel. + * So for boards with less than 256MB of RAM we put the initrd + * halfway into RAM, and for boards with 256MB of RAM or more we put + * the initrd at 128MB. + */ + start = kernel_entry + MIN(mem_size / 2, 128 * MiB); + + size = load_ramdisk(filename, start, mem_size - start); + if (size == -1) { + size = load_image_targphys(filename, start, mem_size - start); + if (size == -1) { + error_report("could not load ramdisk '%s'", filename); + exit(1); + } + } + + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ + if (fdt) { + end = start + size; + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); + } +} + target_ulong riscv_load_kernel(MachineState *machine, target_ulong kernel_start_addr, bool load_initrd, @@ -225,46 +265,6 @@ out: return kernel_entry; } -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) -{ - const char *filename = machine->initrd_filename; - uint64_t mem_size = machine->ram_size; - void *fdt = machine->fdt; - hwaddr start, end; - ssize_t size; - - g_assert(filename != NULL); - - /* - * We want to put the initrd far enough into RAM that when the - * kernel is uncompressed it will not clobber the initrd. However - * on boards without much RAM we must ensure that we still leave - * enough room for a decent sized initrd, and on boards with large - * amounts of RAM we must avoid the initrd being so far up in RAM - * that it is outside lowmem and inaccessible to the kernel. - * So for boards with less than 256MB of RAM we put the initrd - * halfway into RAM, and for boards with 256MB of RAM or more we put - * the initrd at 128MB. - */ - start = kernel_entry + MIN(mem_size / 2, 128 * MiB); - - size = load_ramdisk(filename, start, mem_size - start); - if (size == -1) { - size = load_image_targphys(filename, start, mem_size - start); - if (size == -1) { - error_report("could not load ramdisk '%s'", filename); - exit(1); - } - } - - /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ - if (fdt) { - end = start + size; - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); - } -} - uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) { uint64_t temp, fdt_addr; diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index c3de897371..cbd131bad7 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -47,7 +47,6 @@ target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, bool load_initrd, symbol_fn_t sym_cb); -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr, -- 2.39.0 From MAILER-DAEMON Mon Jan 16 07:30:08 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHOcq-00007Y-OF for mharc-qemu-riscv@gnu.org; Mon, 16 Jan 2023 07:30:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHOco-0008Uz-LQ for qemu-riscv@nongnu.org; Mon, 16 Jan 2023 07:30:06 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHOcm-0003Ie-1w for qemu-riscv@nongnu.org; Mon, 16 Jan 2023 07:30:06 -0500 Received: by mail-oi1-x241.google.com with SMTP id r132so12649276oif.10 for ; Mon, 16 Jan 2023 04:30:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=R4qtclHJ1n0/XaLxnevTHDvTqEpS8d67utZqEr3tpBw=; b=htuXy9SD87E8R9pP8uRDP3IyBjjuXm3hoc5DGjzLq80oW+k8FFcUr5faLmD04H/dDt trBgOxRQzHot0XjrxYCjvqkUJHGkI8QkMoGUdjJYhdmcRBc7v3y7rPPkGpOt6zcxPp8L a+0cg/rwQFnrTc9JaGaa9M7EXIXkz5NvB6JqUETu5ugfbmMraJtC86gR15ebyMAOelYx FLns4uNQH8dCn6uATc8Qj5GSrM9pahQGOT/zTq704K67BXt+8Z+8gLhDhsN3xNEBSYAa 2D5o2byp4atJGXww9csS2WXoE8iArDOd65/yyscFJOMpV1wosemUn9JA17ZI5JOchR83 FHOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=R4qtclHJ1n0/XaLxnevTHDvTqEpS8d67utZqEr3tpBw=; b=xnKASBikcu3MwIdOWK5a4GsN5xCQGHvDDXlmI0D4Cg5wgY+8wK27yxj5Ly9iMSSnMR 0SNYD0I66OkFwW3QpfG3k/j5wacfQQxkRHR5n57wCulYA7xj0/lEzelzAD6CgmPRrh+T sofD7iPq08/l7KjCmQ//INOs/zZKRgp5gLMUzbBygThGp40FDPM9RQHOjuj8tq3GKMMQ bXNcE6OoDETxvZyw4xQn7Zh6qK6Clw/vM25QsPOhZ15PHNvUZInT3i0cQYzGsPNTv7Eh cf5brZW3ckel4WzFO+UDKUwIUAe+hewmbn9ngIWMnXwVbjSwWcg7GFp+94FFVj/XN+lt H+rg== X-Gm-Message-State: AFqh2koT4awOcTVSDG216p5rlLtAh1JB9EFe0UriYCJYk15niLJ2Zz2T +ntBZwt3kvAC2a/UGVjH3tHCyQ== X-Google-Smtp-Source: AMrXdXul1tSBWV0KSY3iZ5MKWWAvMSMrRvaXaVTrknAUi02w+e8gHs1KvewRhzuiHStfvh+tlh6XAA== X-Received: by 2002:a05:6808:657:b0:364:914b:2f02 with SMTP id z23-20020a056808065700b00364914b2f02mr6929775oih.40.1673872202399; Mon, 16 Jan 2023 04:30:02 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id g21-20020a0568080dd500b00360f68d509csm12814540oic.49.2023.01.16.04.30.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 04:30:01 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v8 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym() Date: Mon, 16 Jan 2023 09:29:48 -0300 Message-Id: <20230116122948.757515-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230116122948.757515-1-dbarboza@ventanamicro.com> References: <20230116122948.757515-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::241; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x241.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 12:30:07 -0000 Recent hw/risc/boot.c changes caused a regression in an use case with the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel' stopped working. The reason seems to be that Xvisor is using 64 bit to encode the 32 bit addresses from the guest, and load_elf_ram_sym() is sign-extending the result with '1's [1]. Use a translate_fn() callback to be called by load_elf_ram_sym() and return only the 32 bits address if we're running a 32 bit CPU. [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html Suggested-by: Philippe Mathieu-Daudé Suggested-by: Bin Meng Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 20 +++++++++++++++++++- hw/riscv/microchip_pfsoc.c | 4 ++-- hw/riscv/opentitan.c | 3 ++- hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 4 ++-- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 4 ++-- include/hw/riscv/boot.h | 1 + target/riscv/cpu_bits.h | 1 + 9 files changed, 32 insertions(+), 10 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index e868fb6ade..0fd39df7f3 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -213,7 +213,24 @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) } } +static uint64_t translate_kernel_address(void *opaque, uint64_t addr) +{ + RISCVHartArrayState *harts = opaque; + + /* + * For 32 bit CPUs, kernel_load_base is sign-extended (i.e. + * it can be padded with '1's) if the hypervisor is using + * 64 bit addresses with 32 bit guests. + */ + if (riscv_is_32bit(harts)) { + return extract64(addr, 0, RV32_KERNEL_ADDR_LEN); + } + + return addr; +} + target_ulong riscv_load_kernel(MachineState *machine, + RISCVHartArrayState *harts, target_ulong kernel_start_addr, bool load_initrd, symbol_fn_t sym_cb) @@ -231,7 +248,8 @@ target_ulong riscv_load_kernel(MachineState *machine, * the (expected) load address load address. This allows kernels to have * separate SBI and ELF entry points (used by FreeBSD, for example). */ - if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, + if (load_elf_ram_sym(kernel_filename, NULL, + translate_kernel_address, NULL, NULL, &kernel_load_base, NULL, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { kernel_entry = kernel_load_base; diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index c45023a2b1..b7e171b605 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -629,8 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, - true, NULL); + kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, + kernel_start_addr, true, NULL); /* Compute the fdt load address in dram */ fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index f6fd9725a5..1404a52da0 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -101,7 +101,8 @@ static void opentitan_board_init(MachineState *machine) } if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, false, NULL); + riscv_load_kernel(machine, &s->soc.cpus, + memmap[IBEX_DEV_RAM].base, false, NULL); } } diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 6835d1c807..04939b60c3 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, + riscv_load_kernel(machine, &s->soc.cpus, + memmap[SIFIVE_E_DEV_DTIM].base, false, NULL); } } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index ccad386920..b0b3e6f03a 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -598,8 +598,8 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, - true, NULL); + kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, + kernel_start_addr, true, NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 91bf194ec1..3c0ac916c0 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -305,7 +305,7 @@ static void spike_board_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, + kernel_entry = riscv_load_kernel(machine, &s->soc[0], kernel_start_addr, true, htif_symbol_callback); } else { /* diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e374b58f89..cf64da65bf 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1281,8 +1281,8 @@ static void virt_machine_done(Notifier *notifier, void *data) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, - true, NULL); + kernel_entry = riscv_load_kernel(machine, &s->soc[0], + kernel_start_addr, true, NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index cbd131bad7..bc9faed397 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -44,6 +44,7 @@ target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr, symbol_fn_t sym_cb); target_ulong riscv_load_kernel(MachineState *machine, + RISCVHartArrayState *harts, target_ulong firmware_end_addr, bool load_initrd, symbol_fn_t sym_cb); diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8b0d7e20ea..8fcaeae342 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -751,6 +751,7 @@ typedef enum RISCVException { #define MENVCFG_STCE (1ULL << 63) /* For RV32 */ +#define RV32_KERNEL_ADDR_LEN 32 #define MENVCFGH_PBMTE BIT(30) #define MENVCFGH_STCE BIT(31) -- 2.39.0 From MAILER-DAEMON Mon Jan 16 07:37:47 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHOkD-0005zo-U3 for mharc-qemu-riscv@gnu.org; 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Mon, 16 Jan 2023 04:37:29 -0800 (PST) Message-ID: Date: Mon, 16 Jan 2023 13:37:28 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v8 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym() Content-Language: en-US To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng References: <20230116122948.757515-1-dbarboza@ventanamicro.com> <20230116122948.757515-4-dbarboza@ventanamicro.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230116122948.757515-4-dbarboza@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.097, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 12:37:43 -0000 On 16/1/23 13:29, Daniel Henrique Barboza wrote: > Recent hw/risc/boot.c changes caused a regression in an use case with > the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel' > stopped working. The reason seems to be that Xvisor is using 64 bit to > encode the 32 bit addresses from the guest, and load_elf_ram_sym() is > sign-extending the result with '1's [1]. > > Use a translate_fn() callback to be called by load_elf_ram_sym() and > return only the 32 bits address if we're running a 32 bit CPU. > > [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html > > Suggested-by: Philippe Mathieu-Daudé > Suggested-by: Bin Meng > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/boot.c | 20 +++++++++++++++++++- > hw/riscv/microchip_pfsoc.c | 4 ++-- > hw/riscv/opentitan.c | 3 ++- > hw/riscv/sifive_e.c | 3 ++- > hw/riscv/sifive_u.c | 4 ++-- > hw/riscv/spike.c | 2 +- > hw/riscv/virt.c | 4 ++-- > include/hw/riscv/boot.h | 1 + > target/riscv/cpu_bits.h | 1 + > 9 files changed, 32 insertions(+), 10 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index e868fb6ade..0fd39df7f3 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -213,7 +213,24 @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) > } > } > > +static uint64_t translate_kernel_address(void *opaque, uint64_t addr) > +{ > + RISCVHartArrayState *harts = opaque; > + > + /* > + * For 32 bit CPUs, kernel_load_base is sign-extended (i.e. > + * it can be padded with '1's) if the hypervisor is using > + * 64 bit addresses with 32 bit guests. > + */ > + if (riscv_is_32bit(harts)) { Maybe move the comment within the if() and add " so remove the sign extension by truncating to 32-bit". > + return extract64(addr, 0, RV32_KERNEL_ADDR_LEN); For 32-bit maybe a definition is not necessary, I asked before you used 24-bit in the previous version. As the maintainer prefer :) > + } > + > + return addr; > +} > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 8b0d7e20ea..8fcaeae342 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -751,6 +751,7 @@ typedef enum RISCVException { > #define MENVCFG_STCE (1ULL << 63) > > /* For RV32 */ > +#define RV32_KERNEL_ADDR_LEN 32 > #define MENVCFGH_PBMTE BIT(30) > #define MENVCFGH_STCE BIT(31) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Mon Jan 16 07:45:45 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHOrx-0001H3-1V for mharc-qemu-riscv@gnu.org; Mon, 16 Jan 2023 07:45:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHOrp-0001Fj-8e for qemu-riscv@nongnu.org; Mon, 16 Jan 2023 07:45:40 -0500 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHOrm-0006RN-Tp for qemu-riscv@nongnu.org; Mon, 16 Jan 2023 07:45:36 -0500 Received: by mail-ot1-x343.google.com with SMTP id cc13-20020a05683061cd00b00684b8cf2f4dso7833882otb.12 for ; Mon, 16 Jan 2023 04:45:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=KE91TYLWyiD6yHTxNJUq3DQXstHHwUD4q0xYP1meHdg=; b=VEF6BYhK2oFREsQdleTy8M20XUjOjXeOcjzLVQxVhhGQJNV9bAoYivQJT/XS4aGphV qDNhcx4RLODT9VMIZpeHniLg0GZ2IIMPspKUhSW6yughvzJfN/1GSJh5Mky0cxTTr2/Z fsNxKYwC9O8qJRkhPXVO+W1y8rsuR9e6tgggyxx8GQCiK7QHsaa2nhmR8h0dRlz8+VVl +kSyKRKDLGTLNr4Un1h7ct8KAXBTlK07xvDRmclPdBwax923wetNjoPk0obQMpPGZ6GZ Vb8YGo5Cwk/U9mLA/MB7Rr510NDsUOp3d3UozjrpqTF6VwKxItK7rD3ZXSWi5IojsyBl 8sLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=KE91TYLWyiD6yHTxNJUq3DQXstHHwUD4q0xYP1meHdg=; b=Mjum5qYVzm9109LLAyEtGp3GNc8lPkKo8+x3NSULyo4MJcpOL3WWPiBdE5EZkazFn/ VcZIv3LSbdo9Ply8V+lOKmi1DoItSdfFWeow9YNm14/jRHaIhIo+t3fNkmsBQT5yQ/yc C0enED7LwehN1w4AHlDfxcQQDvuXHcaNjCp6G9MlL8RrlBvefvILnB+tO7TQhSWHmb2m DM3M1i7lTZK+DGgl2rZBcSSeE/DYUpF+P/a8hcq76bNWB6s66aYFg9PARI/Kyg/oMP80 zbOIgdaltjTsgO5begC4MWaNBasf2fDT7MHTywfrrr11uJPs77euoLMxmXhDMdWOWCK5 siIQ== X-Gm-Message-State: AFqh2koGF8UAjoQPi7Kh2wRYiGok9SsjJYt0Ut/Zxzp1dehBYxXbbOnz DIf7LFVoMj3QmXPVe1bo0rUEJg== X-Google-Smtp-Source: AMrXdXsrXOt+XqOgfqVA9kishfCc3Hl3sO7FadaC4VzCfyDw2IFTSrRVkL616JfxuCaOju95Km0ozQ== X-Received: by 2002:a05:6830:6502:b0:66e:316b:a603 with SMTP id cm2-20020a056830650200b0066e316ba603mr53941500otb.3.1673873133091; Mon, 16 Jan 2023 04:45:33 -0800 (PST) Received: from [192.168.68.107] ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id y18-20020a0568302a1200b0066f7e1188f0sm14573779otu.68.2023.01.16.04.45.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 16 Jan 2023 04:45:32 -0800 (PST) Message-ID: <61fd483d-5d3a-587b-5c98-4b81afe21d7d@ventanamicro.com> Date: Mon, 16 Jan 2023 09:45:29 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH v8 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym() Content-Language: en-US To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng References: <20230116122948.757515-1-dbarboza@ventanamicro.com> <20230116122948.757515-4-dbarboza@ventanamicro.com> From: Daniel Henrique Barboza In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::343; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x343.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.097, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 12:45:41 -0000 On 1/16/23 09:37, Philippe Mathieu-Daudé wrote: > On 16/1/23 13:29, Daniel Henrique Barboza wrote: >> Recent hw/risc/boot.c changes caused a regression in an use case with >> the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel' >> stopped working. The reason seems to be that Xvisor is using 64 bit to >> encode the 32 bit addresses from the guest, and load_elf_ram_sym() is >> sign-extending the result with '1's [1]. >> >> Use a translate_fn() callback to be called by load_elf_ram_sym() and >> return only the 32 bits address if we're running a 32 bit CPU. >> >> [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html >> >> Suggested-by: Philippe Mathieu-Daudé >> Suggested-by: Bin Meng >> Signed-off-by: Daniel Henrique Barboza >> --- >>   hw/riscv/boot.c            | 20 +++++++++++++++++++- >>   hw/riscv/microchip_pfsoc.c |  4 ++-- >>   hw/riscv/opentitan.c       |  3 ++- >>   hw/riscv/sifive_e.c        |  3 ++- >>   hw/riscv/sifive_u.c        |  4 ++-- >>   hw/riscv/spike.c           |  2 +- >>   hw/riscv/virt.c            |  4 ++-- >>   include/hw/riscv/boot.h    |  1 + >>   target/riscv/cpu_bits.h    |  1 + >>   9 files changed, 32 insertions(+), 10 deletions(-) >> >> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c >> index e868fb6ade..0fd39df7f3 100644 >> --- a/hw/riscv/boot.c >> +++ b/hw/riscv/boot.c >> @@ -213,7 +213,24 @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) >>       } >>   } >>   +static uint64_t translate_kernel_address(void *opaque, uint64_t addr) >> +{ >> +    RISCVHartArrayState *harts = opaque; >> + >> +    /* >> +     * For 32 bit CPUs, kernel_load_base is sign-extended (i.e. >> +     * it can be padded with '1's) if the hypervisor is using >> +     * 64 bit addresses with 32 bit guests. >> +     */ >> +    if (riscv_is_32bit(harts)) { > > Maybe move the comment within the if() and add " so remove the sign > extension by truncating to 32-bit". > >> +        return extract64(addr, 0, RV32_KERNEL_ADDR_LEN); > > For 32-bit maybe a definition is not necessary, I asked before > you used 24-bit in the previous version. As the maintainer prefer :) That was unintentional. I missed a 'f' in that 0x0fffffff, which I noticed only now when doing this version. It's curious because Alistair mentioned that the patch apparently solved the bug .... I don't mind creating a macro for the 32 bit value. If we decide it's unneeded I can remove it and just put a '32' there. I'll also make the comment change you mentioned above. Thanks, Daniel > >> +    } >> + >> +    return addr; >> +} > >> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h >> index 8b0d7e20ea..8fcaeae342 100644 >> --- a/target/riscv/cpu_bits.h >> +++ b/target/riscv/cpu_bits.h >> @@ -751,6 +751,7 @@ typedef enum RISCVException { >>   #define MENVCFG_STCE                       (1ULL << 63) >>     /* For RV32 */ >> +#define RV32_KERNEL_ADDR_LEN               32 >>   #define MENVCFGH_PBMTE                     BIT(30) >>   #define MENVCFGH_STCE                      BIT(31) > > Reviewed-by: Philippe Mathieu-Daudé > > From MAILER-DAEMON Mon Jan 16 09:16:43 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHQHz-0004is-FN for mharc-qemu-riscv@gnu.org; Mon, 16 Jan 2023 09:16:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHQHx-0004hL-2z for qemu-riscv@nongnu.org; Mon, 16 Jan 2023 09:16:41 -0500 Received: from mail-ot1-x32c.google.com ([2607:f8b0:4864:20::32c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHQHu-00039C-U0 for qemu-riscv@nongnu.org; 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boundary="0000000000002cd55b05f2623b98" Received-SPF: pass client-ip=2607:f8b0:4864:20::32c; envelope-from=frank.chang@sifive.com; helo=mail-ot1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 14:16:42 -0000 --0000000000002cd55b05f2623b98 Content-Type: text/plain; charset="UTF-8" Reviewed-by: Frank Chang On Fri, Jan 13, 2023 at 6:35 PM Alexandre Ghiti wrote: > One can extract the DeviceState pointer from the Object pointer, so pass > the Object for future commits to access other fields of Object. > > No functional changes intended. > > Signed-off-by: Alexandre Ghiti > --- > target/riscv/cpu.c | 15 ++++++++------- > 1 file changed, 8 insertions(+), 7 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index cc75ca7667..7181b34f86 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -200,7 +200,7 @@ static const char * const riscv_intr_names[] = { > "reserved" > }; > > -static void register_cpu_props(DeviceState *dev); > +static void register_cpu_props(Object *obj); > > const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) > { > @@ -238,7 +238,7 @@ static void riscv_any_cpu_init(Object *obj) > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > #endif > set_priv_version(env, PRIV_VERSION_1_12_0); > - register_cpu_props(DEVICE(obj)); > + register_cpu_props(obj); > } > > #if defined(TARGET_RISCV64) > @@ -247,7 +247,7 @@ static void rv64_base_cpu_init(Object *obj) > CPURISCVState *env = &RISCV_CPU(obj)->env; > /* We set this in the realise function */ > set_misa(env, MXL_RV64, 0); > - register_cpu_props(DEVICE(obj)); > + register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > } > @@ -280,7 +280,7 @@ static void rv128_base_cpu_init(Object *obj) > CPURISCVState *env = &RISCV_CPU(obj)->env; > /* We set this in the realise function */ > set_misa(env, MXL_RV128, 0); > - register_cpu_props(DEVICE(obj)); > + register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > } > @@ -290,7 +290,7 @@ static void rv32_base_cpu_init(Object *obj) > CPURISCVState *env = &RISCV_CPU(obj)->env; > /* We set this in the realise function */ > set_misa(env, MXL_RV32, 0); > - register_cpu_props(DEVICE(obj)); > + register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > } > @@ -343,7 +343,7 @@ static void riscv_host_cpu_init(Object *obj) > #elif defined(TARGET_RISCV64) > set_misa(env, MXL_RV64, 0); > #endif > - register_cpu_props(DEVICE(obj)); > + register_cpu_props(obj); > } > #endif > > @@ -1083,9 +1083,10 @@ static Property riscv_cpu_extensions[] = { > DEFINE_PROP_END_OF_LIST(), > }; > > -static void register_cpu_props(DeviceState *dev) > +static void register_cpu_props(Object *obj) > { > Property *prop; > + DeviceState *dev = DEVICE(obj); > > for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > qdev_property_add_static(dev, prop); > -- > 2.37.2 > > --0000000000002cd55b05f2623b98 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Reviewed-by: Frank Chang <frank.chang@sifive.com>

On Fri, Jan 13, 2023 at 6:35 PM = Alexandre Ghiti <alexghiti@riv= osinc.com> wrote:
One can extract the DeviceState pointer from the Object pointer,= so pass
the Object for future commits to access other fields of Object.

No functional changes intended.

Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
---
=C2=A0target/riscv/cpu.c | 15 ++++++++-------
=C2=A01 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index cc75ca7667..7181b34f86 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -200,7 +200,7 @@ static const char * const riscv_intr_names[] =3D {
=C2=A0 =C2=A0 =C2=A0"reserved"
=C2=A0};

-static void register_cpu_props(DeviceState *dev);
+static void register_cpu_props(Object *obj);

=C2=A0const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) =C2=A0{
@@ -238,7 +238,7 @@ static void riscv_any_cpu_init(Object *obj)
=C2=A0 =C2=A0 =C2=A0set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | R= VC | RVU);
=C2=A0#endif
=C2=A0 =C2=A0 =C2=A0set_priv_version(env, PRIV_VERSION_1_12_0);
-=C2=A0 =C2=A0 register_cpu_props(DEVICE(obj));
+=C2=A0 =C2=A0 register_cpu_props(obj);
=C2=A0}

=C2=A0#if defined(TARGET_RISCV64)
@@ -247,7 +247,7 @@ static void rv64_base_cpu_init(Object *obj)
=C2=A0 =C2=A0 =C2=A0CPURISCVState *env =3D &RISCV_CPU(obj)->env;
=C2=A0 =C2=A0 =C2=A0/* We set this in the realise function */
=C2=A0 =C2=A0 =C2=A0set_misa(env, MXL_RV64, 0);
-=C2=A0 =C2=A0 register_cpu_props(DEVICE(obj));
+=C2=A0 =C2=A0 register_cpu_props(obj);
=C2=A0 =C2=A0 =C2=A0/* Set latest version of privileged specification */ =C2=A0 =C2=A0 =C2=A0set_priv_version(env, PRIV_VERSION_1_12_0);
=C2=A0}
@@ -280,7 +280,7 @@ static void rv128_base_cpu_init(Object *obj)
=C2=A0 =C2=A0 =C2=A0CPURISCVState *env =3D &RISCV_CPU(obj)->env;
=C2=A0 =C2=A0 =C2=A0/* We set this in the realise function */
=C2=A0 =C2=A0 =C2=A0set_misa(env, MXL_RV128, 0);
-=C2=A0 =C2=A0 register_cpu_props(DEVICE(obj));
+=C2=A0 =C2=A0 register_cpu_props(obj);
=C2=A0 =C2=A0 =C2=A0/* Set latest version of privileged specification */ =C2=A0 =C2=A0 =C2=A0set_priv_version(env, PRIV_VERSION_1_12_0);
=C2=A0}
@@ -290,7 +290,7 @@ static void rv32_base_cpu_init(Object *obj)
=C2=A0 =C2=A0 =C2=A0CPURISCVState *env =3D &RISCV_CPU(obj)->env;
=C2=A0 =C2=A0 =C2=A0/* We set this in the realise function */
=C2=A0 =C2=A0 =C2=A0set_misa(env, MXL_RV32, 0);
-=C2=A0 =C2=A0 register_cpu_props(DEVICE(obj));
+=C2=A0 =C2=A0 register_cpu_props(obj);
=C2=A0 =C2=A0 =C2=A0/* Set latest version of privileged specification */ =C2=A0 =C2=A0 =C2=A0set_priv_version(env, PRIV_VERSION_1_12_0);
=C2=A0}
@@ -343,7 +343,7 @@ static void riscv_host_cpu_init(Object *obj)
=C2=A0#elif defined(TARGET_RISCV64)
=C2=A0 =C2=A0 =C2=A0set_misa(env, MXL_RV64, 0);
=C2=A0#endif
-=C2=A0 =C2=A0 register_cpu_props(DEVICE(obj));
+=C2=A0 =C2=A0 register_cpu_props(obj);
=C2=A0}
=C2=A0#endif

@@ -1083,9 +1083,10 @@ static Property riscv_cpu_extensions[] =3D {
=C2=A0 =C2=A0 =C2=A0DEFINE_PROP_END_OF_LIST(),
=C2=A0};

-static void register_cpu_props(DeviceState *dev)
+static void register_cpu_props(Object *obj)
=C2=A0{
=C2=A0 =C2=A0 =C2=A0Property *prop;
+=C2=A0 =C2=A0 DeviceState *dev =3D DEVICE(obj);

=C2=A0 =C2=A0 =C2=A0for (prop =3D riscv_cpu_extensions; prop && pro= p->name; prop++) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0qdev_property_add_static(dev, prop);
--
2.37.2

--0000000000002cd55b05f2623b98-- From MAILER-DAEMON Mon Jan 16 12:34:30 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHTNO-0006TI-GV for mharc-qemu-riscv@gnu.org; Mon, 16 Jan 2023 12:34:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHTNM-0006Se-H8 for qemu-riscv@nongnu.org; Mon, 16 Jan 2023 12:34:28 -0500 Received: from mail-oa1-x42.google.com ([2001:4860:4864:20::42]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHTNK-0004m5-RG for qemu-riscv@nongnu.org; Mon, 16 Jan 2023 12:34:28 -0500 Received: by mail-oa1-x42.google.com with SMTP id 586e51a60fabf-15ee27bb0a8so9141749fac.7 for ; Mon, 16 Jan 2023 09:34:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=ua2DEWhTSYbOeDX9Z8sLTigQK0JhqYjB/hFbj3gHy5A=; b=jSk4UOGPGyJK34h9BSHaT1Xv0wRXgwsW5O/sWyt9KN286zD9yrM0s7bqvTZcXuG0Ds MpRF0ANzXV4F/8KAEdR2Z+ZeUKovvHsvyX0P1JGU/ntUygLCOBO3ugHTN5gRy2NTVxzH 2qw/qmAUbaLsPfQHzPwVVWyTSWaZI6Yuidlf8VSfHdaV45vsV2YWymkfhTm0d1FDSqKw plE73M1v1BrFGqKHZR7jlBv709TOtiLi6UNer0VpVgzn0V0tr+HOpezJmEbsvidljsRl vYJQqqsdiic6+MLODumuXgw6UqtNN8mZq+xuzwnIXUM82D3U6oRaUpMK302crVbNXzG7 m+pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=ua2DEWhTSYbOeDX9Z8sLTigQK0JhqYjB/hFbj3gHy5A=; b=TuJKqh+mYSut93rmCOz4qGvkOI5N+fAUxY6HPtx+CrOsYUl/M0x8dKiBUmM0VD7EN7 tVREH7iOrh8OVbInYheufGvL13Pv6qy0W9YSIDYQf+R/yywJgX/ygpaPlUIY1S8phzSQ bu8Hu1MkpiTiN0Uk6Iz+r94THnKA2w5VbLL4oZ7SEPEJFx2uHZ+pJssbTpMizfp56lZR 4sjgz7w/3Ku9HhJG2ut6/xtRzRY4QUq7MPzef87Ch5X5CkcP0m9B76METqqAc9oJ+s+T hs5ROLru3QADAaKOi2B83PtBqA62daYgOuUg3houbcbUuswEeE9guWq5HGtlZeHU9Bdd fPbw== X-Gm-Message-State: AFqh2kqjVQHqbbnFl6E7DJoEOUlPJL7Zf0JW9WQfeKSeez6AVns+qYl3 uleus8YxguGeILTHy70Dsp3krw== X-Google-Smtp-Source: AMrXdXtkHxvzggjf80qyfA6fpbxPt0WD4cM4jJUUlhgwLu7I57oet0CcQjB3NPyQtsKa6Ri1AdrW/w== X-Received: by 2002:a05:6871:440c:b0:15e:9cf2:5163 with SMTP id nd12-20020a056871440c00b0015e9cf25163mr299571oab.41.1673890465427; Mon, 16 Jan 2023 09:34:25 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id f23-20020a4ae617000000b0049fd5c02d25sm1353802oot.12.2023.01.16.09.34.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 09:34:24 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 0/6] riscv: fdt related cleanups Date: Mon, 16 Jan 2023 14:34:14 -0300 Message-Id: <20230116173420.1146808-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::42; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x42.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 17:34:28 -0000 Hi, In this version I included a rework in riscv_load_fdt() to separate the fdt address calculation from the fdt load process. Having both in the same function doesn't give us much and can lead to confusion due to how other archs handle their respective load_fdt() functions. Patches are based on riscv-to-apply.next. Changes from v1: - former patches 1-6: already applied to riscv-to-apply.next - former patch 7: removed - patch 1 (new): - fix a potential issue with fdt_pack() called after fdt_totalsize() - patch 2 (new): - split fdt address compute from fdt load logic - patch 3 (new): - simplify the new riscv_compute_fdt_addr() by using MachineState - patches 4,5,6: - added Phil's r-b v1 link: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02246.html Daniel Henrique Barboza (6): hw/riscv/boot.c: calculate fdt size after fdt_pack() hw/riscv: split fdt address calculation from fdt load hw/riscv: simplify riscv_compute_fdt_addr() hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' hw/riscv/boot.c | 33 ++- hw/riscv/microchip_pfsoc.c | 6 +- hw/riscv/sifive_u.c | 7 +- hw/riscv/spike.c | 24 +- hw/riscv/virt.c | 468 +++++++++++++++++++------------------ include/hw/riscv/boot.h | 3 +- 6 files changed, 281 insertions(+), 260 deletions(-) -- 2.39.0 From MAILER-DAEMON Mon Jan 16 12:34:31 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHTNP-0006U5-L0 for mharc-qemu-riscv@gnu.org; Mon, 16 Jan 2023 12:34:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHTNO-0006TG-Bk for qemu-riscv@nongnu.org; Mon, 16 Jan 2023 12:34:30 -0500 Received: from mail-oa1-x32.google.com ([2001:4860:4864:20::32]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHTNM-0004nD-TH for qemu-riscv@nongnu.org; Mon, 16 Jan 2023 12:34:30 -0500 Received: by mail-oa1-x32.google.com with SMTP id 586e51a60fabf-15bb8ec196aso17763950fac.3 for ; Mon, 16 Jan 2023 09:34:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6uR+Za30JTgq3Im6TQb73kibUHGAIkzY+HrHZCNg0m4=; b=ZSnYryTm8RNQ5onlHeT8MIUDh93cRReLTHFZEvKESE9/R8CP5fvbYQJuLSiYO0Y6A8 8hyNoM3gj7srs/7/TjckWXbRm0M5KbgygUBT1ufDiBa324xrhtuk1P0fxNOznuk6YqJy pESTqv6y6sUiGwmOKDU40JAwHt/WJXw61c5FP9SDKVxmhf0toDni3+o0aN9kdC0tq0X6 yOtvTlCQ5Xdv0Q/xLgBrUX8AcGq9ot7AN3p9gV6mvC5aHLcS+ouaZwop+NoIBOG40OtH bN6vtdQfFQ0yq/brZTVXW3wI3KaxjNEve8on18/ih91bqTzJy8ucAYJxVIF2jONfxu57 Ae/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6uR+Za30JTgq3Im6TQb73kibUHGAIkzY+HrHZCNg0m4=; b=f6DGo/R2llgzxx4HThVVz4nNbT9nVOKQFM5ATFFQGiZopi8XgQqlW2glZL/FCJ7FQR 0T2dKE8zIth5G37kOV11G89e644LDETB5Odlw3jrNjYv4Ix5WNhpRoj11XT6VUSfrIoJ ycvjlp5EA7o8SDnNIx1m9Ldzy9HWA2SD/ImX032+p/waPCiPd2jdJjc6tG5AOmKq3sA6 yZ7B+relSlx+6CmgkAVohrtRZ55iZZ+dOoea6jrU/tCKgzpYJU/xKR+EDsmi8i8TePNz SPDwCT5uKc7r2ZOfleV5kqfUofQgRNtNpLNODPpLeBSFHRA7Tt3M2v9H7iVZcVDIYz2p FnfA== X-Gm-Message-State: AFqh2kom07ptoaTKGrmswEAww7csZNsNS39WZ0jrmRG5pHVRP/pqjX16 0FQv93rS7s21ldyRb95jornG3Q== X-Google-Smtp-Source: AMrXdXtfdg2RGEsqD83xhYVsT8gg12B1EYJGHUtRUkRlaax9PWrwm8QPkImkB+jhTVBAicTbmUniVg== X-Received: by 2002:a05:6870:c43:b0:151:fd0f:1b59 with SMTP id lf3-20020a0568700c4300b00151fd0f1b59mr11194407oab.5.1673890467601; Mon, 16 Jan 2023 09:34:27 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id f23-20020a4ae617000000b0049fd5c02d25sm1353802oot.12.2023.01.16.09.34.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 09:34:27 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 1/6] hw/riscv/boot.c: calculate fdt size after fdt_pack() Date: Mon, 16 Jan 2023 14:34:15 -0300 Message-Id: <20230116173420.1146808-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230116173420.1146808-1-dbarboza@ventanamicro.com> References: <20230116173420.1146808-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 17:34:30 -0000 fdt_pack() can change the fdt size, meaning that fdt_totalsize() can contain a now deprecated (bigger) value. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 2594276223..dc14d8cd14 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -253,8 +253,13 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) { uint64_t temp, fdt_addr; hwaddr dram_end = dram_base + mem_size; - int ret, fdtsize = fdt_totalsize(fdt); + int ret = fdt_pack(fdt); + int fdtsize; + /* Should only fail if we've built a corrupted tree */ + g_assert(ret == 0); + + fdtsize = fdt_totalsize(fdt); if (fdtsize <= 0) { error_report("invalid device-tree"); exit(1); -- 2.39.0 From MAILER-DAEMON Mon Jan 16 12:34:33 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHTNR-0006Ux-R4 for mharc-qemu-riscv@gnu.org; Mon, 16 Jan 2023 12:34:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHTNR-0006Uh-77 for qemu-riscv@nongnu.org; Mon, 16 Jan 2023 12:34:33 -0500 Received: from mail-oa1-x30.google.com ([2001:4860:4864:20::30]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHTNP-0004nx-7P for qemu-riscv@nongnu.org; Mon, 16 Jan 2023 12:34:32 -0500 Received: by mail-oa1-x30.google.com with SMTP id 586e51a60fabf-15b9c93848dso21249562fac.1 for ; Mon, 16 Jan 2023 09:34:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=huCIRm4fE2nXe/svvkMVa8+PPFhI8IrQIUTuoYZHTXw=; b=JYjDjzV4uXKC4s6VOuEK0dQS4BByh96eviDf3ur7jbJwOeJAuhree8vhiTdbM9wvD8 R/in0u/HezWDleEsjSuTg24jXCOeIMZLfhdOm2VfyF03mLtYAheYGYriDBF5n7ZisusX rHV5Z4rjdBLv9B5objEndiRSjPfQT4nAiTju1BUhJi3YP1A+EfnTT7LpMD7UvyAYKLhC G1B4uj0yQ3Fs3614uX8zIHrB/OZ/0gFPu71mlKro4kFM4PDyU1fS/OiqgtGmp+1Kb5YZ YWS42fX4IVBh+cJOI32dDuNKetbk1LCPK/YWWH6NWIOQB2VtJjzm3m2400Ks1+GJRTa8 qlDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=huCIRm4fE2nXe/svvkMVa8+PPFhI8IrQIUTuoYZHTXw=; b=rDGpwyw/xxMCqufTeZE09Hv490Vxd5F4QCDyF7o80cG1K5vkRf1iaGLBfNfYS7YRgc g/8GEEHIt7cpOyVZJx0NtcJWK6JqbJhYkFKACbgG79EXMlcQxV9uuc4+NMyJyScxfVjj nksYvAv6VmR8bJ1Td8ugm1woZ8ZifIunQdxCVwPl/FqhQLbbwdQe0cbiqrTn9OwgWntx LkYC/BFRiS2mpbx0LiI4Dg8wGW2vOd4KN7M1UpN5BLLI5tbdkgHtlYAl5lU/korXpT8d e3Jm//P022KXu3F8LsrnjcD5b3OUDM1j/cKTMnG9xrUYXnSrGwwZldzXNHzG0LFOdfMX upXg== X-Gm-Message-State: AFqh2krwWmD6DWpXmeW4BmRtDJz5DP9O8+fzsggqYNjQXVjIcrHmClob sL8hSltqwCJt1EdgRRm4fS9PPuLl34nPlsUFuzY= X-Google-Smtp-Source: AMrXdXsLLBtVJH/ZJ6W6mep69I0j/nRsIAzf/m/jyF6VUvdG0XLjbq0ErhokQUQyIlQdc4W3ax0GCQ== X-Received: by 2002:a05:6870:80cf:b0:150:3588:3359 with SMTP id r15-20020a05687080cf00b0015035883359mr12835714oab.2.1673890470045; Mon, 16 Jan 2023 09:34:30 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id f23-20020a4ae617000000b0049fd5c02d25sm1353802oot.12.2023.01.16.09.34.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 09:34:29 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 2/6] hw/riscv: split fdt address calculation from fdt load Date: Mon, 16 Jan 2023 14:34:16 -0300 Message-Id: <20230116173420.1146808-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230116173420.1146808-1-dbarboza@ventanamicro.com> References: <20230116173420.1146808-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::30; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 17:34:33 -0000 A common trend in other archs is to calculate the fdt address, which is usually straightforward, and then calling a function that loads the fdt/dtb by using that address. riscv_load_fdt() is doing a bit too much in comparison. It's calculating the fdt address via an elaborated heuristic to put the FDT at the bottom of DRAM, and "bottom of DRAM" will vary across boards and configurations, then it's actually loading the fdt, and finally it's returning the fdt address used to the caller. Reduce the existing complexity of riscv_load_fdt() by splitting its code into a new function, riscv_compute_fdt_addr(), that will take care of all fdt address logic. riscv_load_fdt() can then be a simple function that just loads a fdt at the given fdt address. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 24 ++++++++++++++++-------- hw/riscv/microchip_pfsoc.c | 6 ++++-- hw/riscv/sifive_u.c | 7 ++++--- hw/riscv/spike.c | 6 +++--- hw/riscv/virt.c | 7 ++++--- include/hw/riscv/boot.h | 3 ++- 6 files changed, 33 insertions(+), 20 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index dc14d8cd14..b213a32157 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -249,9 +249,16 @@ void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) } } -uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) +/* + * The FDT should be put at the farthest point possible to + * avoid overwriting it with the kernel/initrd. + * + * The FDT is fdt_packed() during the calculation. + */ +uint32_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size, + void *fdt) { - uint64_t temp, fdt_addr; + uint64_t temp; hwaddr dram_end = dram_base + mem_size; int ret = fdt_pack(fdt); int fdtsize; @@ -272,11 +279,14 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) * end of dram or 3GB whichever is lesser. */ temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; - fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); - ret = fdt_pack(fdt); - /* Should only fail if we've built a corrupted tree */ - g_assert(ret == 0); + return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); +} + +void riscv_load_fdt(uint32_t fdt_addr, void *fdt) +{ + uint32_t fdtsize = fdt_totalsize(fdt); + /* copy in the device tree */ qemu_fdt_dumpdtb(fdt, fdtsize); @@ -284,8 +294,6 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) &address_space_memory); qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize)); - - return fdt_addr; } void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 82ae5e7023..dcdbc2cac3 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -641,8 +641,10 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) } /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base, + machine->ram_size, machine->fdt); + riscv_load_fdt(fdt_load_addr, machine->fdt); + /* Load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr, memmap[MICROCHIP_PFSOC_ENVM_DATA].base, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 2fb6ee231f..626d4dc2f3 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -616,9 +616,10 @@ static void sifive_u_machine_init(MachineState *machine) kernel_entry = 0; } - /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, + machine->ram_size, machine->fdt); + riscv_load_fdt(fdt_load_addr, machine->fdt); + if (!riscv_is_32bit(&s->soc.u_cpus)) { start_addr_hi32 = (uint64_t)start_addr >> 32; } diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index badc11ec43..88b9fdfc36 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -324,9 +324,9 @@ static void spike_board_init(MachineState *machine) kernel_entry = 0; } - /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, + machine->ram_size, machine->fdt); + riscv_load_fdt(fdt_load_addr, machine->fdt); /* load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e6d4f06e8d..839dfaa125 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1307,9 +1307,10 @@ static void virt_machine_done(Notifier *notifier, void *data) start_addr = virt_memmap[VIRT_FLASH].base; } - /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, + machine->ram_size, machine->fdt); + riscv_load_fdt(fdt_load_addr, machine->fdt); + /* load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, virt_memmap[VIRT_MROM].base, diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index f94653a09b..9aea7b9c46 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -47,7 +47,8 @@ target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, symbol_fn_t sym_cb); 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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id f23-20020a4ae617000000b0049fd5c02d25sm1353802oot.12.2023.01.16.09.34.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 09:34:31 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 3/6] hw/riscv: simplify riscv_compute_fdt_addr() Date: Mon, 16 Jan 2023 14:34:17 -0300 Message-Id: <20230116173420.1146808-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230116173420.1146808-1-dbarboza@ventanamicro.com> References: <20230116173420.1146808-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::32; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x32.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 17:34:35 -0000 All callers are using attributes from the MachineState object. Use a pointer to it instead of passing dram_size (which is always machine->ram_size) and fdt (always machine->fdt). Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 6 +++--- hw/riscv/microchip_pfsoc.c | 4 ++-- hw/riscv/sifive_u.c | 4 ++-- hw/riscv/spike.c | 4 ++-- hw/riscv/virt.c | 3 +-- include/hw/riscv/boot.h | 2 +- 6 files changed, 11 insertions(+), 12 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index b213a32157..508da3f5c7 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -255,11 +255,11 @@ void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) * * The FDT is fdt_packed() during the calculation. */ -uint32_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size, - void *fdt) +uint32_t riscv_compute_fdt_addr(MachineState *machine, hwaddr dram_base) { + void *fdt = machine->fdt; uint64_t temp; - hwaddr dram_end = dram_base + mem_size; + hwaddr dram_end = dram_base + machine->ram_size; int ret = fdt_pack(fdt); int fdtsize; diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index dcdbc2cac3..a53e48e996 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -641,8 +641,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) } /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(machine, + memmap[MICROCHIP_PFSOC_DRAM_LO].base); riscv_load_fdt(fdt_load_addr, machine->fdt); /* Load the reset vector */ diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 626d4dc2f3..ebfddf161d 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -616,8 +616,8 @@ static void sifive_u_machine_init(MachineState *machine) kernel_entry = 0; } - fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(machine, + memmap[SIFIVE_U_DEV_DRAM].base); riscv_load_fdt(fdt_load_addr, machine->fdt); if (!riscv_is_32bit(&s->soc.u_cpus)) { diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 88b9fdfc36..afd581436b 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -324,8 +324,8 @@ static void spike_board_init(MachineState *machine) kernel_entry = 0; } - fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(machine, + memmap[SPIKE_DRAM].base); riscv_load_fdt(fdt_load_addr, machine->fdt); /* load the reset vector */ diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 839dfaa125..cbba0b8930 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1307,8 +1307,7 @@ static void virt_machine_done(Notifier *notifier, void *data) start_addr = virt_memmap[VIRT_FLASH].base; } - fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(machine, memmap[VIRT_DRAM].base); riscv_load_fdt(fdt_load_addr, machine->fdt); /* load the reset vector */ diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 9aea7b9c46..f933de88fb 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -47,7 +47,7 @@ target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, symbol_fn_t sym_cb); void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); -uint32_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, void *fdt); +uint32_t riscv_compute_fdt_addr(MachineState *machine, hwaddr dram_start); void riscv_load_fdt(uint32_t fdt_addr, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr, -- 2.39.0 From MAILER-DAEMON Mon Jan 16 12:34:39 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHTNX-0006Wl-Ba for mharc-qemu-riscv@gnu.org; Mon, 16 Jan 2023 12:34:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHTNV-0006WL-Tc for qemu-riscv@nongnu.org; Mon, 16 Jan 2023 12:34:37 -0500 Received: from mail-oo1-xc34.google.com ([2607:f8b0:4864:20::c34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHTNT-0004oe-Py for qemu-riscv@nongnu.org; Mon, 16 Jan 2023 12:34:37 -0500 Received: by mail-oo1-xc34.google.com with SMTP id d2-20020a4ab202000000b004ae3035538bso7401239ooo.12 for ; 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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id f23-20020a4ae617000000b0049fd5c02d25sm1353802oot.12.2023.01.16.09.34.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 09:34:34 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 4/6] hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() Date: Mon, 16 Jan 2023 14:34:18 -0300 Message-Id: <20230116173420.1146808-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230116173420.1146808-1-dbarboza@ventanamicro.com> References: <20230116173420.1146808-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c34; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 17:34:38 -0000 riscv_socket_count() returns either ms->numa_state->num_nodes or 1 depending on NUMA support. In any case the value can be retrieved only once and used in the rest of the function. This will also alleviate the rename we're going to do next by reducing the instances of MachineState 'mc' inside hw/riscv/virt.c. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index cbba0b8930..8ff89c217f 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -505,13 +505,14 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, int cpu, socket; char *imsic_name; MachineState *mc = MACHINE(s); + int socket_count = riscv_socket_count(mc); uint32_t imsic_max_hart_per_socket, imsic_guest_bits; uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; *msi_m_phandle = (*phandle)++; *msi_s_phandle = (*phandle)++; imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2); - imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4); + imsic_regs = g_new0(uint32_t, socket_count * 4); /* M-level IMSIC node */ for (cpu = 0; cpu < mc->smp.cpus; cpu++) { @@ -519,7 +520,7 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); } imsic_max_hart_per_socket = 0; - for (socket = 0; socket < riscv_socket_count(mc); socket++) { + for (socket = 0; socket < socket_count; socket++) { imsic_addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; @@ -545,14 +546,14 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, - riscv_socket_count(mc) * sizeof(uint32_t) * 4); + socket_count * sizeof(uint32_t) * 4); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); - if (riscv_socket_count(mc) > 1) { + if (socket_count > 1) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", - imsic_num_bits(riscv_socket_count(mc))); + imsic_num_bits(socket_count)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); } @@ -567,7 +568,7 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, } imsic_guest_bits = imsic_num_bits(s->aia_guests + 1); imsic_max_hart_per_socket = 0; - for (socket = 0; socket < riscv_socket_count(mc); socket++) { + for (socket = 0; socket < socket_count; socket++) { imsic_addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * @@ -594,18 +595,18 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, - riscv_socket_count(mc) * sizeof(uint32_t) * 4); + socket_count * sizeof(uint32_t) * 4); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); if (imsic_guest_bits) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits", imsic_guest_bits); } - if (riscv_socket_count(mc) > 1) { + if (socket_count > 1) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", - imsic_num_bits(riscv_socket_count(mc))); + imsic_num_bits(socket_count)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); } @@ -733,6 +734,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, MachineState *mc = MACHINE(s); uint32_t msi_m_phandle = 0, msi_s_phandle = 0; uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; + int socket_count = riscv_socket_count(mc); qemu_fdt_add_subnode(mc->fdt, "/cpus"); qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", @@ -744,7 +746,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, intc_phandles = g_new0(uint32_t, mc->smp.cpus); phandle_pos = mc->smp.cpus; - for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { + for (socket = (socket_count - 1); socket >= 0; socket--) { phandle_pos -= s->soc[socket].num_harts; clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); @@ -775,7 +777,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, } phandle_pos = mc->smp.cpus; - for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { + for (socket = (socket_count - 1); socket >= 0; socket--) { phandle_pos -= s->soc[socket].num_harts; if (s->aia_type == VIRT_AIA_TYPE_NONE) { @@ -790,7 +792,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, g_free(intc_phandles); - for (socket = 0; socket < riscv_socket_count(mc); socket++) { + for (socket = 0; socket < socket_count; socket++) { if (socket == 0) { *irq_mmio_phandle = xplic_phandles[socket]; *irq_virtio_phandle = xplic_phandles[socket]; @@ -1051,7 +1053,8 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) /* Pass seed to RNG */ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); - qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); + qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", + rng_seed, sizeof(rng_seed)); } static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, @@ -1335,9 +1338,10 @@ static void virt_machine_init(MachineState *machine) char *soc_name; DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; int i, base_hartid, hart_count; + int socket_count = riscv_socket_count(machine); /* Check socket count limit */ - if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { + if (VIRT_SOCKETS_MAX < socket_count) { error_report("number of sockets/nodes should be less than %d", VIRT_SOCKETS_MAX); exit(1); @@ -1345,7 +1349,7 @@ static void virt_machine_init(MachineState *machine) /* Initialize sockets */ mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; - for (i = 0; i < riscv_socket_count(machine); i++) { + for (i = 0; i < socket_count; i++) { if (!riscv_socket_check_hartids(machine, i)) { error_report("discontinuous hartids in socket%d", i); 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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id f23-20020a4ae617000000b0049fd5c02d25sm1353802oot.12.2023.01.16.09.34.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 09:34:39 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 6/6] hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' Date: Mon, 16 Jan 2023 14:34:20 -0300 Message-Id: <20230116173420.1146808-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230116173420.1146808-1-dbarboza@ventanamicro.com> References: <20230116173420.1146808-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::2a; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 17:34:42 -0000 Follow the QEMU convention of naming MachineState pointers as 'ms' by renaming the instances where we're calling it 'mc'. Suggested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Daniel Henrique Barboza --- hw/riscv/spike.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index afd581436b..222fde0c5c 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -56,7 +56,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, uint64_t addr, size; unsigned long clint_addr; int cpu, socket; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); uint32_t *clint_cells; uint32_t cpu_phandle, intc_phandle, phandle = 1; char *name, *mem_name, *clint_name, *clust_name; @@ -65,7 +65,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, "sifive,clint0", "riscv,clint0" }; - fdt = mc->fdt = create_device_tree(&fdt_size); + fdt = ms->fdt = create_device_tree(&fdt_size); if (!fdt) { error_report("create_device_tree() failed"); exit(1); @@ -96,7 +96,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); - for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { + for (socket = (riscv_socket_count(ms) - 1); socket >= 0; socket--) { clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); qemu_fdt_add_subnode(fdt, clust_name); @@ -121,7 +121,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, qemu_fdt_setprop_cell(fdt, cpu_name, "reg", s->soc[socket].hartid_base + cpu); qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, cpu_name, socket); + riscv_socket_fdt_write_id(ms, cpu_name, socket); qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); @@ -147,14 +147,14 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, g_free(cpu_name); } - addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket); - size = riscv_socket_mem_size(mc, socket); + addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(ms, socket); + size = riscv_socket_mem_size(ms, socket); mem_name = g_strdup_printf("/memory@%lx", (long)addr); qemu_fdt_add_subnode(fdt, mem_name); qemu_fdt_setprop_cells(fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, mem_name, socket); + riscv_socket_fdt_write_id(ms, mem_name, socket); g_free(mem_name); clint_addr = memmap[SPIKE_CLINT].base + @@ -167,14 +167,14 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, clint_name, socket); + riscv_socket_fdt_write_id(ms, clint_name, socket); g_free(clint_name); g_free(clint_cells); g_free(clust_name); } - riscv_socket_fdt_write_distance_matrix(mc); + riscv_socket_fdt_write_distance_matrix(ms); qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); 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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id f23-20020a4ae617000000b0049fd5c02d25sm1353802oot.12.2023.01.16.09.34.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Jan 2023 09:34:36 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, philmd@linaro.org, Daniel Henrique Barboza Subject: [PATCH v2 5/6] hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' Date: Mon, 16 Jan 2023 14:34:19 -0300 Message-Id: <20230116173420.1146808-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230116173420.1146808-1-dbarboza@ventanamicro.com> References: <20230116173420.1146808-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jan 2023 17:34:42 -0000 We have a convention in other QEMU boards/archs to name MachineState pointers as either 'machine' or 'ms'. MachineClass pointers are usually called 'mc'. The 'virt' RISC-V machine has a lot of instances where MachineState pointers are named 'mc'. There is nothing wrong with that, but we gain more compatibility with the rest of the QEMU code base, and easier reviews, if we follow QEMU conventions. Rename all 'mc' MachineState pointers to 'ms'. This is a very tedious and mechanical patch that was produced by doing the following: - find/replace all 'MachineState *mc' to 'MachineState *ms'; - find/replace all 'mc->fdt' to 'ms->fdt'; - find/replace all 'mc->smp.cpus' to 'ms->smp.cpus'; - replace any remaining occurrences of 'mc' that the compiler complained about. Suggested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 434 ++++++++++++++++++++++++------------------------ 1 file changed, 217 insertions(+), 217 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 8ff89c217f..479a90b3d5 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -227,7 +227,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, { int cpu; uint32_t cpu_phandle; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); char *name, *cpu_name, *core_name, *intc_name; bool is_32_bit = riscv_is_32bit(&s->soc[0]); @@ -236,40 +236,40 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); - qemu_fdt_add_subnode(mc->fdt, cpu_name); + qemu_fdt_add_subnode(ms->fdt, cpu_name); if (riscv_feature(&s->soc[socket].harts[cpu].env, RISCV_FEATURE_MMU)) { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", + qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); } else { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", + qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", "riscv,none"); } name = riscv_isa_string(&s->soc[socket].harts[cpu]); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); + qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name); g_free(name); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv"); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay"); - qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", + qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); + qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); + qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", s->soc[socket].hartid_base + cpu); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, cpu_name, socket); - qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); + qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); + riscv_socket_fdt_write_id(ms, cpu_name, socket); + qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); intc_phandles[cpu] = (*phandle)++; intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); - qemu_fdt_add_subnode(mc->fdt, intc_name); - qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", + qemu_fdt_add_subnode(ms->fdt, intc_name); + qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", intc_phandles[cpu]); - qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", + qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", "riscv,cpu-intc"); - qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); + qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); core_name = g_strdup_printf("%s/core%d", clust_name, cpu); - qemu_fdt_add_subnode(mc->fdt, core_name); - qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle); + qemu_fdt_add_subnode(ms->fdt, core_name); + qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); g_free(core_name); g_free(intc_name); @@ -282,16 +282,16 @@ static void create_fdt_socket_memory(RISCVVirtState *s, { char *mem_name; uint64_t addr, size; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); - addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); - size = riscv_socket_mem_size(mc, socket); + addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); + size = riscv_socket_mem_size(ms, socket); mem_name = g_strdup_printf("/memory@%lx", (long)addr); - qemu_fdt_add_subnode(mc->fdt, mem_name); - qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", + qemu_fdt_add_subnode(ms->fdt, mem_name); + qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); - qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, mem_name, socket); + qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); + riscv_socket_fdt_write_id(ms, mem_name, socket); g_free(mem_name); } @@ -303,7 +303,7 @@ static void create_fdt_socket_clint(RISCVVirtState *s, char *clint_name; uint32_t *clint_cells; unsigned long clint_addr; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); static const char * const clint_compat[2] = { "sifive,clint0", "riscv,clint0" }; @@ -319,15 +319,15 @@ static void create_fdt_socket_clint(RISCVVirtState *s, clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); - qemu_fdt_add_subnode(mc->fdt, clint_name); - qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible", + qemu_fdt_add_subnode(ms->fdt, clint_name); + qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", (char **)&clint_compat, ARRAY_SIZE(clint_compat)); - qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); - qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, clint_name, socket); + riscv_socket_fdt_write_id(ms, clint_name, socket); g_free(clint_name); g_free(clint_cells); @@ -344,7 +344,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, uint32_t *aclint_mswi_cells; uint32_t *aclint_sswi_cells; uint32_t *aclint_mtimer_cells; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); @@ -363,16 +363,16 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); name = g_strdup_printf("/soc/mswi@%lx", addr); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-mswi"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", aclint_mswi_cells, aclint_cells_size); - qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, name, socket); + qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); + riscv_socket_fdt_write_id(ms, name, socket); g_free(name); } @@ -386,33 +386,33 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; } name = g_strdup_printf("/soc/mtimer@%lx", addr); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-mtimer"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 0x0, RISCV_ACLINT_DEFAULT_MTIME); - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", aclint_mtimer_cells, aclint_cells_size); - riscv_socket_fdt_write_id(mc, name, socket); + riscv_socket_fdt_write_id(ms, name, socket); g_free(name); if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { addr = memmap[VIRT_ACLINT_SSWI].base + (memmap[VIRT_ACLINT_SSWI].size * socket); name = g_strdup_printf("/soc/sswi@%lx", addr); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-sswi"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", aclint_sswi_cells, aclint_cells_size); - qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, name, socket); + qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); + riscv_socket_fdt_write_id(ms, name, socket); g_free(name); } @@ -430,7 +430,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s, char *plic_name; uint32_t *plic_cells; unsigned long plic_addr; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); static const char * const plic_compat[2] = { "sifive,plic-1.0.0", "riscv,plic0" }; @@ -456,27 +456,27 @@ static void create_fdt_socket_plic(RISCVVirtState *s, plic_phandles[socket] = (*phandle)++; plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); - qemu_fdt_add_subnode(mc->fdt, plic_name); - qemu_fdt_setprop_cell(mc->fdt, plic_name, + qemu_fdt_add_subnode(ms->fdt, plic_name); + qemu_fdt_setprop_cell(ms->fdt, plic_name, "#interrupt-cells", FDT_PLIC_INT_CELLS); - qemu_fdt_setprop_cell(mc->fdt, plic_name, + qemu_fdt_setprop_cell(ms->fdt, plic_name, "#address-cells", FDT_PLIC_ADDR_CELLS); - qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", + qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", (char **)&plic_compat, ARRAY_SIZE(plic_compat)); - qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); - qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", + qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", VIRT_IRQCHIP_NUM_SOURCES - 1); - riscv_socket_fdt_write_id(mc, plic_name, socket); - qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", + riscv_socket_fdt_write_id(ms, plic_name, socket); + qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", plic_phandles[socket]); if (!socket) { - platform_bus_add_all_fdt_nodes(mc->fdt, plic_name, + platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, memmap[VIRT_PLATFORM_BUS].base, memmap[VIRT_PLATFORM_BUS].size, VIRT_PLATFORM_BUS_IRQ); @@ -504,18 +504,18 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, { int cpu, socket; char *imsic_name; - MachineState *mc = MACHINE(s); - int socket_count = riscv_socket_count(mc); + MachineState *ms = MACHINE(s); + int socket_count = riscv_socket_count(ms); uint32_t imsic_max_hart_per_socket, imsic_guest_bits; uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; *msi_m_phandle = (*phandle)++; *msi_s_phandle = (*phandle)++; - imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2); + imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); imsic_regs = g_new0(uint32_t, socket_count * 4); /* M-level IMSIC node */ - for (cpu = 0; cpu < mc->smp.cpus; cpu++) { + for (cpu = 0; cpu < ms->smp.cpus; cpu++) { imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); } @@ -534,35 +534,35 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, } imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)memmap[VIRT_IMSIC_M].base); - qemu_fdt_add_subnode(mc->fdt, imsic_name); - qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", + qemu_fdt_add_subnode(ms->fdt, imsic_name); + qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", FDT_IMSIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", - imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); - qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", + imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); + qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, socket_count * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); if (socket_count > 1) { - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", imsic_num_bits(socket_count)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); } - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle); + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phandle); g_free(imsic_name); /* S-level IMSIC node */ - for (cpu = 0; cpu < mc->smp.cpus; cpu++) { + for (cpu = 0; cpu < ms->smp.cpus; cpu++) { imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); } @@ -583,34 +583,34 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, } imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)memmap[VIRT_IMSIC_S].base); - qemu_fdt_add_subnode(mc->fdt, imsic_name); - qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", + qemu_fdt_add_subnode(ms->fdt, imsic_name); + qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", FDT_IMSIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", - imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); - qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", + imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); + qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, socket_count * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); if (imsic_guest_bits) { - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", imsic_guest_bits); } if (socket_count > 1) { - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", imsic_num_bits(socket_count)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); } - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle); + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_s_phandle); g_free(imsic_name); g_free(imsic_regs); @@ -629,7 +629,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, char *aplic_name; uint32_t *aplic_cells; unsigned long aplic_addr; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); uint32_t aplic_m_phandle, aplic_s_phandle; aplic_m_phandle = (*phandle)++; @@ -644,28 +644,28 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_addr = memmap[VIRT_APLIC_M].base + (memmap[VIRT_APLIC_M].size * socket); aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); - qemu_fdt_add_subnode(mc->fdt, aplic_name); - qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, + qemu_fdt_add_subnode(ms->fdt, aplic_name); + qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#interrupt-cells", FDT_APLIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); if (s->aia_type == VIRT_AIA_TYPE_APLIC) { - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); } else { - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_m_phandle); } - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", VIRT_IRQCHIP_NUM_SOURCES); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", aplic_s_phandle); - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(mc, aplic_name, socket); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); + riscv_socket_fdt_write_id(ms, aplic_name, socket); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phandle); g_free(aplic_name); /* S-level APLIC node */ @@ -676,27 +676,27 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_addr = memmap[VIRT_APLIC_S].base + (memmap[VIRT_APLIC_S].size * socket); aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); - qemu_fdt_add_subnode(mc->fdt, aplic_name); - qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, + qemu_fdt_add_subnode(ms->fdt, aplic_name); + qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#interrupt-cells", FDT_APLIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); if (s->aia_type == VIRT_AIA_TYPE_APLIC) { - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); } else { - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_s_phandle); } - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(mc, aplic_name, socket); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); + riscv_socket_fdt_write_id(ms, aplic_name, socket); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_s_phandle); if (!socket) { - platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name, + platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, memmap[VIRT_PLATFORM_BUS].base, memmap[VIRT_PLATFORM_BUS].size, VIRT_PLATFORM_BUS_IRQ); @@ -711,13 +711,13 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, static void create_fdt_pmu(RISCVVirtState *s) { char *pmu_name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); RISCVCPU hart = s->soc[0].harts[0]; pmu_name = g_strdup_printf("/soc/pmu"); - qemu_fdt_add_subnode(mc->fdt, pmu_name); - qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu"); - riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name); + qemu_fdt_add_subnode(ms->fdt, pmu_name); + qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); + riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name); g_free(pmu_name); } @@ -731,26 +731,26 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, { char *clust_name; int socket, phandle_pos; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); uint32_t msi_m_phandle = 0, msi_s_phandle = 0; uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; - int socket_count = riscv_socket_count(mc); + int socket_count = riscv_socket_count(ms); - qemu_fdt_add_subnode(mc->fdt, "/cpus"); - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", + qemu_fdt_add_subnode(ms->fdt, "/cpus"); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); - qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); + qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); - intc_phandles = g_new0(uint32_t, mc->smp.cpus); + intc_phandles = g_new0(uint32_t, ms->smp.cpus); - phandle_pos = mc->smp.cpus; + phandle_pos = ms->smp.cpus; for (socket = (socket_count - 1); socket >= 0; socket--) { phandle_pos -= s->soc[socket].num_harts; clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); - qemu_fdt_add_subnode(mc->fdt, clust_name); + qemu_fdt_add_subnode(ms->fdt, clust_name); create_fdt_socket_cpus(s, socket, clust_name, phandle, &intc_phandles[phandle_pos]); @@ -776,7 +776,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, *msi_pcie_phandle = msi_s_phandle; } - phandle_pos = mc->smp.cpus; + phandle_pos = ms->smp.cpus; for (socket = (socket_count - 1); socket >= 0; socket--) { phandle_pos -= s->soc[socket].num_harts; @@ -807,7 +807,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, } } - riscv_socket_fdt_write_distance_matrix(mc); + riscv_socket_fdt_write_distance_matrix(ms); } static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, @@ -815,23 +815,23 @@ static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, { int i; char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); for (i = 0; i < VIRTIO_COUNT; i++) { name = g_strdup_printf("/soc/virtio_mmio@%lx", (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 0x0, memmap[VIRT_VIRTIO].size); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_virtio_phandle); if (s->aia_type == VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", VIRTIO_IRQ + i); } else { - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", VIRTIO_IRQ + i, 0x4); } g_free(name); @@ -843,29 +843,29 @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, uint32_t msi_pcie_phandle) { char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); name = g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS); - qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "pci-host-ecam-generic"); - qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci"); - qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0); - qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0, + qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); + qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); + qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); - qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0); + qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { - qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); } - qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0, + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); - qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges", + qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 1, FDT_PCI_RANGE_IOPORT, 2, 0, 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 1, FDT_PCI_RANGE_MMIO, @@ -875,7 +875,7 @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); - create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle); + create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); g_free(name); } @@ -884,39 +884,39 @@ static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, { char *name; uint32_t test_phandle; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); test_phandle = (*phandle)++; name = g_strdup_printf("/soc/test@%lx", (long)memmap[VIRT_TEST].base); - qemu_fdt_add_subnode(mc->fdt, name); + qemu_fdt_add_subnode(ms->fdt, name); { static const char * const compat[3] = { "sifive,test1", "sifive,test0", "syscon" }; - qemu_fdt_setprop_string_array(mc->fdt, name, "compatible", + qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", (char **)&compat, ARRAY_SIZE(compat)); } - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); - qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle); - test_phandle = qemu_fdt_get_phandle(mc->fdt, name); + qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); + test_phandle = qemu_fdt_get_phandle(ms->fdt, name); g_free(name); name = g_strdup_printf("/reboot"); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot"); - qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); - qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); - qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET); + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); + qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); + qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); g_free(name); name = g_strdup_printf("/poweroff"); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff"); - qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); - qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); - qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS); + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); + qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); + qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); g_free(name); } @@ -924,24 +924,24 @@ static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, uint32_t irq_mmio_phandle) { char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_UART0].base, 0x0, memmap[VIRT_UART0].size); - qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); if (s->aia_type == VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); } else { - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4); + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); } - qemu_fdt_add_subnode(mc->fdt, "/chosen"); - qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); + qemu_fdt_add_subnode(ms->fdt, "/chosen"); + qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); g_free(name); } @@ -949,20 +949,20 @@ static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, uint32_t irq_mmio_phandle) { char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "google,goldfish-rtc"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); if (s->aia_type == VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); } else { - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4); + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); } g_free(name); } @@ -970,68 +970,68 @@ static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) { char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; hwaddr flashbase = virt_memmap[VIRT_FLASH].base; name = g_strdup_printf("/flash@%" PRIx64, flashbase); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); - qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); + qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2, flashbase, 2, flashsize, 2, flashbase + flashsize, 2, flashsize); - qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); + qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); g_free(name); } static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) { char *nodename; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); hwaddr base = memmap[VIRT_FW_CFG].base; hwaddr size = memmap[VIRT_FW_CFG].size; nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); - qemu_fdt_add_subnode(mc->fdt, nodename); - qemu_fdt_setprop_string(mc->fdt, nodename, + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "qemu,fw-cfg-mmio"); - qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", + qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); - qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); + qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); g_free(nodename); } static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) { - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; uint8_t rng_seed[32]; - if (mc->dtb) { - mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); - if (!mc->fdt) { + if (ms->dtb) { + ms->fdt = load_device_tree(ms->dtb, &s->fdt_size); + if (!ms->fdt) { error_report("load_device_tree() failed"); exit(1); } } else { - mc->fdt = create_device_tree(&s->fdt_size); - if (!mc->fdt) { + ms->fdt = create_device_tree(&s->fdt_size); + if (!ms->fdt) { error_report("create_device_tree() failed"); exit(1); } } - qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu"); - qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio"); - qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2); - qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2); + qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); + qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); + qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); + qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); - qemu_fdt_add_subnode(mc->fdt, "/soc"); - qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0); - qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus"); - qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); - qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); + qemu_fdt_add_subnode(ms->fdt, "/soc"); + qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); + qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); + qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); + qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, @@ -1053,7 +1053,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) /* Pass seed to RNG */ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); - qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", + qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); } @@ -1106,14 +1106,14 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, return dev; } -static FWCfgState *create_fw_cfg(const MachineState *mc) +static FWCfgState *create_fw_cfg(const MachineState *ms) { hwaddr base = virt_memmap[VIRT_FW_CFG].base; FWCfgState *fw_cfg; fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, &address_space_memory); - fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); + fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); return fw_cfg; } -- 2.39.0 From MAILER-DAEMON Tue Jan 17 08:28:08 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHm0V-0004vt-Rx for mharc-qemu-riscv@gnu.org; Tue, 17 Jan 2023 08:28:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHm0V-0004vL-1U for qemu-riscv@nongnu.org; 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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id v12-20020a056870b50c00b0014fc049fc0asm16538270oap.57.2023.01.17.05.28.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jan 2023 05:28:02 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng.cn@gmail.com, Daniel Henrique Barboza Subject: [PATCH 0/1] move create_fw_cfg() to init() (Gitlab #1343) Date: Tue, 17 Jan 2023 10:27:50 -0300 Message-Id: <20230117132751.229738-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::44; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x44.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Jan 2023 13:28:07 -0000 Hi, This patch fixes a regression introduced with 1c20d3ff6004 ("hw/riscv: virt: Add a machine done notifier") that is preventing qemu-system-riscv64 to use the ramfb device starting in QEMU 7.1. Fix is based on top of Alistair's riscv-to-apply.next: https://github.com/alistair23/qemu/tree/riscv-to-apply.next Daniel Henrique Barboza (1): hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init() hw/riscv/virt.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) -- 2.39.0 From MAILER-DAEMON Tue Jan 17 08:28:11 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHm0Z-0004xQ-3W for mharc-qemu-riscv@gnu.org; Tue, 17 Jan 2023 08:28:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHm0X-0004wh-6N for qemu-riscv@nongnu.org; Tue, 17 Jan 2023 08:28:09 -0500 Received: from mail-oa1-x43.google.com ([2001:4860:4864:20::43]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHm0V-0001TR-7g for qemu-riscv@nongnu.org; Tue, 17 Jan 2023 08:28:08 -0500 Received: by mail-oa1-x43.google.com with SMTP id 586e51a60fabf-1322d768ba7so31907371fac.5 for ; Tue, 17 Jan 2023 05:28:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wjDJws69/b2lYY2Ofw7BKsKud7AlxZ3crKbm2ST0OU4=; b=aR3tSfMsvJ+SmHFzbT/w+DElJ7g9fi31QtuEa6rM94lWQ2a4eIt9nC1DmHdSVDLLd1 VsMUpKqTDwzduyubmt3feJBwOBLDhyEuJby0nmGO9NHCn9SXmEyb1GujCywp4lHqs9us 4HCFCqK0rm37Tze0rmxVFs0ZBhsH88bVEy1IcZ2zedTPKdqmA0PEXUaeA5CwDxGUsWZG WtyeDXJk913imfQJBSCvl70c/pbeRz8i5KXKsV+ummo9+CKXts0w+YFw6lLn7vpfWERx L6/4mMfs1Ba+olDQtT9qS34pOnkbeVQRrXB4bUpnWtdWLEQbfHplGFbvLFoG20GxXP1P scig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wjDJws69/b2lYY2Ofw7BKsKud7AlxZ3crKbm2ST0OU4=; b=0aXecKXHmFP1XEYbMtvhLeLQtT1kWHwYCcsZM8R61V3vVBc9fVjI7dFMo5v+gVQ4/K fpeMKq9JCLmZQIxIQwuHkv3up0ZcfbKw9hMQASUtszgLJA6ZGSNo4GPe2YxHAU0SCeHA kxcFiMNEep01CJwIPKXOVIvijQTEEV9S5JUcqVUCXL5/lE6WXZJUDBt3Aqwe0LR0w6+s ApNVIiIK4YuFyjBL+Q8DSX2uDtnuISr2G/ll7KKY06AmpScc4nV8LTAuLsFXMQvHkqyP uygRt8VAO5517a9aQ85WVWmWqXpNKohHOoDK4chBhG07Y1lyTY8DeBeSduU/XxQokoEK PwTQ== X-Gm-Message-State: AFqh2kr0GnfpSvDDt3ooRGUT+DByNlpBgZSkrlqIZ3vbA0vhynOEOuND 2rSeP+l0/TANVMCdeghz+y6jbQ== X-Google-Smtp-Source: AMrXdXuF7p4oLukFB/Lfsv/eQe9Rs9KexoHqHaeBwnHzi4gN34CSglv0AWY07Q9TMJupm9Nlg9RGgA== X-Received: by 2002:a05:6870:8999:b0:13c:2539:216 with SMTP id f25-20020a056870899900b0013c25390216mr1769389oaq.10.1673962085978; Tue, 17 Jan 2023 05:28:05 -0800 (PST) Received: from grind.. ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id v12-20020a056870b50c00b0014fc049fc0asm16538270oap.57.2023.01.17.05.28.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jan 2023 05:28:05 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng.cn@gmail.com, Daniel Henrique Barboza Subject: [PATCH 1/1] hw/riscv/virt.c: move create_fw_cfg() back to virt_machine_init() Date: Tue, 17 Jan 2023 10:27:51 -0300 Message-Id: <20230117132751.229738-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230117132751.229738-1-dbarboza@ventanamicro.com> References: <20230117132751.229738-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::43; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x43.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Jan 2023 13:28:09 -0000 Commit 1c20d3ff6004 ("hw/riscv: virt: Add a machine done notifier") moved the initialization of fw_cfg to the virt_machine_done() callback. Problem is that the validation of fw_cfg by devices such as ramfb is done before the machine done notifier is called. Moving create_fw_cfg() to machine_done() results in QEMU failing to boot when using a ramfb device: ./qemu-system-riscv64 -machine virt -device ramfb -serial stdio qemu-system-riscv64: -device ramfb: ramfb device requires fw_cfg with DMA The fix is simple: move create_fw_cfg() config back to virt_machine_init(). This happens to be the same way the ARM 'virt' machine deals with fw_cfg (see machvirt_init() and virt_machine_done() in hw/arm/virt.c), so we're keeping consistency with how other machines handle this device. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1343 Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e6d4f06e8d..4a11b4b010 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1254,13 +1254,6 @@ static void virt_machine_done(Notifier *notifier, void *data) firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, start_addr, NULL); - /* - * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device - * tree cannot be altered and we get FDT_ERR_NOSPACE. - */ - s->fw_cfg = create_fw_cfg(machine); - rom_set_fw(s->fw_cfg); - if (drive_get(IF_PFLASH, 0, 1)) { /* * S-mode FW like EDK2 will be kept in second plash (unit 1). @@ -1468,6 +1461,13 @@ static void virt_machine_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, mask_rom); + /* + * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the + * device tree cannot be altered and we get FDT_ERR_NOSPACE. + */ + s->fw_cfg = create_fw_cfg(machine); + rom_set_fw(s->fw_cfg); + /* SiFive Test MMIO device */ sifive_test_create(memmap[VIRT_TEST].base); -- 2.39.0 From MAILER-DAEMON Tue Jan 17 09:21:45 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHmqP-0005iB-BY for mharc-qemu-riscv@gnu.org; Tue, 17 Jan 2023 09:21:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHmqN-0005hd-GN for qemu-riscv@nongnu.org; Tue, 17 Jan 2023 09:21:43 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHmqL-00029v-IS for qemu-riscv@nongnu.org; Tue, 17 Jan 2023 09:21:42 -0500 Received: by mail-wm1-x32d.google.com with SMTP id m15so1172787wms.4 for ; Tue, 17 Jan 2023 06:21:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=zun9R1HnhsYpIBEgRGSUZTaf8sxjD8dhuMNZisat7OE=; b=izHMtbuWbUucEUuHTTlFDItCol7+bADhZ8vPpw+vOs3DapJ8eG6INbA16ISgsOKgCW 8lWRjrp6+IBf8DkSUuB1kgMqGvdwadXzGHzFaAOgrVNBqdJwgh3+wEZWKI7u2lyAKJb0 fEJ4fY2sRWLw6X/wH9epcCUqZneGbDCGWsOdUU6ZPoxANZvCBwiMRBdbMptPZTERBs3J swOeLd0sOBdDSCDqn8sYCFfqia665gypxQL9CpBnf0dDvm/+bbYzW3Fqz5iQjtizT7g2 DuNhgS53jotsEq3e1cog8/JUA152Ve1jCyBGQucQ3diz9h4d6Ixe7P7SOW4lk6KrI45l JLvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=zun9R1HnhsYpIBEgRGSUZTaf8sxjD8dhuMNZisat7OE=; b=ZaX2WAFrmWvP8Y02KdAIiK1SHcX2D3m6yZ55uh1hveQ7FVurJC51R/zXxCIe9hRuC8 nQXNGyeutAkHCMbw2mwmsjgpUELk+pjIW6Erm3nMAv0xDXwI0fRw4aDInEik8UtRFusw 7owy4d4bdYYnxDPe29KkWdDMDEbeE5+AIejKXPz2z0N3UnaU0S9l7ibh/bRhIaUZsQ7m w7Fp6iu6v6jvK7PauPFdsjPZnpMNJoOa5qPierI7mjAvJaGTmMbKx65naqeYgH4QU2fR zbK6n4IjcmbCJQC1brhRRb8rSHoYJXRMdM1vPqkQLqLbuzifmyQ293hruErd9J5+AxYp EAEw== X-Gm-Message-State: AFqh2kq5EC3rhouAnL7kaqEVRC5Mar9eKHTvdCpgkT4bEKeexYDJYUIj S9GccOsMDIqSvOBfGR6dsnjGuQ== X-Google-Smtp-Source: AMrXdXuqMMdgEqpTq0Kqpst9s4vegKgZPQtwgIb+WdRlWyAn+Bj0fQOyi4fE5wuBq+qS/Lx0mHC7zw== X-Received: by 2002:a05:600c:4a27:b0:3db:3ef:2369 with SMTP id c39-20020a05600c4a2700b003db03ef2369mr3755143wmp.40.1673965299712; Tue, 17 Jan 2023 06:21:39 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id j20-20020a05600c1c1400b003daf89e01d3sm8505849wms.11.2023.01.17.06.21.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jan 2023 06:21:39 -0800 (PST) Date: Tue, 17 Jan 2023 15:21:38 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: Re: [PATCH v5 1/2] riscv: Pass Object to register_cpu_props instead of DeviceState Message-ID: <20230117142138.j2cv2lzvppiuzpne@orel> References: <20230113103453.42776-1-alexghiti@rivosinc.com> <20230113103453.42776-2-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230113103453.42776-2-alexghiti@rivosinc.com> Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Jan 2023 14:21:43 -0000 On Fri, Jan 13, 2023 at 11:34:52AM +0100, Alexandre Ghiti wrote: > One can extract the DeviceState pointer from the Object pointer, so pass > the Object for future commits to access other fields of Object. > > No functional changes intended. > > Signed-off-by: Alexandre Ghiti > --- > target/riscv/cpu.c | 15 ++++++++------- > 1 file changed, 8 insertions(+), 7 deletions(-) > Reviewed-by: Andrew Jones From MAILER-DAEMON Tue Jan 17 11:31:48 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHosG-00062M-HH for mharc-qemu-riscv@gnu.org; Tue, 17 Jan 2023 11:31:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHosF-00061j-14 for qemu-riscv@nongnu.org; Tue, 17 Jan 2023 11:31:47 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHos9-0006vS-SQ for qemu-riscv@nongnu.org; Tue, 17 Jan 2023 11:31:44 -0500 Received: by mail-wm1-x330.google.com with SMTP id o17-20020a05600c511100b003db021ef437so3529306wms.4 for ; Tue, 17 Jan 2023 08:31:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=rZlt9WVMcLeg+H81wpGYFJQ7WRooxp8oGyk3f4lXtKM=; b=N9bl67XKF8TzPtKY1EuTL/TYSgXD8XdzSdFsnMPYuoip24L7XPa8bp7pRtGxUWiZTl w8vrbpIxD4cYxJS4IlJrl8G/qY9ZntKxGJFGrqAVzrAkP47wfY/ZJi0QTpT9Tmg/Oq8x fhg4g0gQbjYZXKhRtg2FhxkXcXXAeqYR/WCd3WThbuUsaXBcpVTJkOWuBSKS6aECTahE 5hCxEm4Ty29Hu5MJWwniBf4za6HdP5KxgrFmJ0mMMEtYf5T3DoThx8FkAy26m4eOPRXt UfJnCB4SiNtl7cLeLJ7Z4vrpmzlWFlKQL+lmq+V216KEfKOq36itqyVlPGvWqjAkSKsJ AtmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=rZlt9WVMcLeg+H81wpGYFJQ7WRooxp8oGyk3f4lXtKM=; b=MCA2GMHUh3UvQlnzUB8oPs4EaSF3KmmOUCzkoDRctqj72CFqAGmG7skkcGqTvFmKeB h0yC5RkjbcLay+ZaxR96t64UC8npSHNe0otLoMZcXocLkZ7yTZJkCpXJcPLYr62F1T4c +d2+cbdLZcz37N9S1kFrP8xtG9ZWm+tZi1FsVsmx37F64C8g2INh3uYZchifzOVhc59F Fa20dpsxHHHaRXSscYEzUrbswonMMfl9FvjSc1kmvKj/rB20B9LNiMBxReGD26EgBYKy +YeXk3iUHJ8WHwTb+oGXY54o6+t1Y6YOLrDCYCMfzkhMut8Wu0wF5Wor+6wlWYQ1f1hz JN/Q== X-Gm-Message-State: AFqh2kqfxpb0v3afDlQDBvn3LwLPLCdOnBYoKZYci1OVDYQrex+CnELM 97kHms0ajTocZ79nndq3zhzVqw== X-Google-Smtp-Source: AMrXdXvbdpn0/xQU/MWpltZ+o07Bq8Aqm1QzhQyxY89Mqsg10UigurvWVFldi7QiUz4RnOypcPiFWg== X-Received: by 2002:a7b:cc14:0:b0:3da:50b0:e96a with SMTP id f20-20020a7bcc14000000b003da50b0e96amr3641031wmh.29.1673973100293; Tue, 17 Jan 2023 08:31:40 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id o37-20020a05600c512500b003db09eaddb5sm2853316wms.3.2023.01.17.08.31.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jan 2023 08:31:39 -0800 (PST) Date: Tue, 17 Jan 2023 17:31:38 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Subject: Re: [PATCH v5 2/2] riscv: Allow user to set the satp mode Message-ID: <20230117163138.jze47hjeeuwu2k4j@orel> References: <20230113103453.42776-1-alexghiti@rivosinc.com> <20230113103453.42776-3-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230113103453.42776-3-alexghiti@rivosinc.com> Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Jan 2023 16:31:47 -0000 On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote: > RISC-V specifies multiple sizes for addressable memory and Linux probes for > the machine's support at startup via the satp CSR register (done in > csr.c:validate_vm). > > As per the specification, sv64 must support sv57, which in turn must > support sv48...etc. So we can restrict machine support by simply setting the > "highest" supported mode and the bare mode is always supported. > > You can set the satp mode using the new properties "sv32", "sv39", "sv48", > "sv57" and "sv64" as follows: > -cpu rv64,sv57=on # Linux will boot using sv57 scheme > -cpu rv64,sv39=on # Linux will boot using sv39 scheme > -cpu rv64,sv57=off # Linux will boot using sv48 scheme > -cpu rv64 # Linux will boot using sv57 scheme by default > > We take the highest level set by the user: > -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme > > We make sure that invalid configurations are rejected: > -cpu rv64,sv32=on # Can't enable 32-bit satp mode in 64-bit > -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are > # enabled > > We accept "redundant" configurations: > -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme > -cpu rv64,sv32=on,sv32=off # Linux will boot using sv57 scheme (the default) > > In addition, we now correctly set the device-tree entry 'mmu-type' using > those new properties. > > Co-Developed-by: Ludovic Henry > Signed-off-by: Ludovic Henry > Signed-off-by: Alexandre Ghiti > --- > hw/riscv/virt.c | 19 ++-- > target/riscv/cpu.c | 221 +++++++++++++++++++++++++++++++++++++++++++++ > target/riscv/cpu.h | 19 ++++ > target/riscv/csr.c | 17 +++- > 4 files changed, 262 insertions(+), 14 deletions(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 94ff2a1584..48d034a5f7 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -228,7 +228,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > int cpu; > uint32_t cpu_phandle; > MachineState *mc = MACHINE(s); > - char *name, *cpu_name, *core_name, *intc_name; > + uint8_t satp_mode_max; > + char *name, *cpu_name, *core_name, *intc_name, *sv_name; > > for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { > cpu_phandle = (*phandle)++; > @@ -236,14 +237,14 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > cpu_name = g_strdup_printf("/cpus/cpu@%d", > s->soc[socket].hartid_base + cpu); > qemu_fdt_add_subnode(mc->fdt, cpu_name); > - if (riscv_feature(&s->soc[socket].harts[cpu].env, > - RISCV_FEATURE_MMU)) { > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > - (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); I just noticed that for the virt machine type, when the user doesn't provide a satp mode cpu property on the command line, and hence gets the default mode, they'll be silently changed from sv48 to sv57. That default change should be a separate patch which comes after this one. BTW, why sv57 and not sv48 or sv64? > - } else { > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > - "riscv,none"); > - } > + > + satp_mode_max = satp_mode_max_from_map( > + s->soc[socket].harts[cpu].cfg.satp_mode.map); > + sv_name = g_strdup_printf("riscv,%s", > + satp_mode_str(satp_mode_max, is_32_bit)); > + qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", sv_name); > + g_free(sv_name); > + > name = riscv_isa_string(&s->soc[socket].harts[cpu]); > qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); > g_free(name); > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 7181b34f86..1f0d040a80 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -27,6 +27,7 @@ > #include "time_helper.h" > #include "exec/exec-all.h" > #include "qapi/error.h" > +#include "qapi/visitor.h" > #include "qemu/error-report.h" > #include "hw/qdev-properties.h" > #include "migration/vmstate.h" > @@ -229,6 +230,85 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) > env->vext_ver = vext_ver; > } > > +static uint8_t satp_mode_from_str(const char *satp_mode_str) > +{ > + if (!strncmp(satp_mode_str, "sv32", 4)) { > + return VM_1_10_SV32; > + } > + > + if (!strncmp(satp_mode_str, "sv39", 4)) { > + return VM_1_10_SV39; > + } > + > + if (!strncmp(satp_mode_str, "sv48", 4)) { > + return VM_1_10_SV48; > + } > + > + if (!strncmp(satp_mode_str, "sv57", 4)) { > + return VM_1_10_SV57; > + } > + > + if (!strncmp(satp_mode_str, "sv64", 4)) { > + return VM_1_10_SV64; > + } > + > + g_assert_not_reached(); > +} > + > +uint8_t satp_mode_max_from_map(uint32_t map) > +{ > + /* map here has at least one bit set, so no problem with clz */ > + return 31 - __builtin_clz(map); > +} > + > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > +{ > + if (is_32_bit) { > + switch (satp_mode) { > + case VM_1_10_SV32: > + return "sv32"; > + case VM_1_10_MBARE: > + return "none"; > + } > + } else { > + switch (satp_mode) { > + case VM_1_10_SV64: > + return "sv64"; > + case VM_1_10_SV57: > + return "sv57"; > + case VM_1_10_SV48: > + return "sv48"; > + case VM_1_10_SV39: > + return "sv39"; > + case VM_1_10_MBARE: > + return "none"; > + } > + } > + > + g_assert_not_reached(); > +} > + > +static void set_satp_mode(RISCVCPU *cpu, const char *satp_mode_str) > +{ > + cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str(satp_mode_str)); > +} > + > +static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit) > +{ > + /* > + * If an mmu is present, the default satp mode is: > + * - sv32 for 32-bit > + * - sv57 for 64-bit > + * Otherwise, it is mbare. > + */ I'd drop the above comment since it only repeats what the code says. > + > + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > + set_satp_mode(cpu, is_32_bit ? "sv32" : "sv57"); > + } else { > + set_satp_mode(cpu, "mbare"); nit: Could probably integrate set_satp_mode() into this function since this function is the only place it's used. > + } > +} > + > static void riscv_any_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > @@ -619,6 +699,53 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > } > } > > +static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > +{ > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > + const char *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; Not a problem of this patch, but valid_vm_1_10_32/64 has a strange type. It's used like a boolean, so should be bool. Since you're touching the arrays and validate_vm() it'd be nice to change the array type and the return value of validate_vm() with a separate patch first. > + > + /* Get rid of 32-bit/64-bit incompatibility */ > + for (int i = 0; i < 16; ++i) { > + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { If we ever define mode=1 for rv64, then 'sv32=on' will be incorrectly accepted as an alias. I think we should simply not define the sv32 property for rv64 nor the rv64-only modes for rv32. So, down in riscv_add_satp_mode_properties() we can add some #if defined(TARGET_RISCV32) ... #elif defined(TARGET_RISCV64) ... #endif and then drop the check here. > + error_setg(errp, "satp_mode %s is not valid", > + satp_mode_str(i, !rv32)); > + return; > + } > + } > + > + /* > + * Make sure the user did not ask for an invalid configuration as per > + * the specification. > + */ > + if (!rv32) { > + uint8_t satp_mode_max; > + > + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > + > + for (int i = satp_mode_max - 1; i >= 0; --i) { > + if (!(cpu->cfg.satp_mode.map & (1 << i)) && > + (cpu->cfg.satp_mode.init & (1 << i)) && > + valid_vm[i]) { > + error_setg(errp, "cannot disable %s satp mode if %s " > + "is enabled", satp_mode_str(i, false), > + satp_mode_str(satp_mode_max, false)); > + return; > + } > + } > + } > +} > + > +static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > +{ > + Error *local_err = NULL; > + > + riscv_cpu_satp_mode_finalize(cpu, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > + } > +} > + > static void riscv_cpu_realize(DeviceState *dev, Error **errp) > { > CPUState *cs = CPU(dev); > @@ -919,6 +1046,55 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > #endif > > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > + > + if (cpu->cfg.satp_mode.map == 0) { > + /* > + * If unset by both the user and the cpu, we fallback to the default > + * satp mode. > + */ > + if (cpu->cfg.satp_mode.init == 0) { > + set_satp_mode_default(cpu, rv32); > + } else { > + /* > + * Find the lowest level that was disabled and then enable the > + * first valid level below which can be found in > + * valid_vm_1_10_32/64. > + */ > + const char *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > + > + for (int i = 0; i < 16; ++i) { 'init' will never have bit0 (mbare) set, so we can start at i=1, which is good, because the condition below assumes it can index an array at i-1. > + if (!(cpu->cfg.satp_mode.map & (1 << i)) && > + (cpu->cfg.satp_mode.init & (1 << i)) && > + valid_vm[i]) { > + for (int j = i - 1; j >= 0; --j) { > + if (valid_vm[j]) { > + cpu->cfg.satp_mode.map |= (1 << j); > + break; > + } > + } > + break; > + } > + } > + > + /* > + * The user actually init a satp mode but appears to be invalid > + * (ex: "-cpu rv64,sv32=on,sv32=off"). Fallback to the default This example, where sv32 is used with rv64, won't be possible if we don't give rv64 the sv32 property. > + * mode. > + */ > + if (cpu->cfg.satp_mode.map == 0) { > + set_satp_mode_default(cpu, rv32); If the user does rv64,sv39=on,sv39=off, then I think we should be creating an mbare machine, rather than using the default. > + } > + } > + } Why isn't all this 'if (cpu->cfg.satp_mode.map == 0)' block above at the top of riscv_cpu_satp_mode_finalize() instead of here? > + > + riscv_cpu_finalize_features(cpu, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > + } > + > + extra blank line > riscv_cpu_register_gdb_regs_for_features(cs); > > qemu_init_vcpu(cs); > @@ -927,6 +1103,49 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > mcc->parent_realize(dev, errp); > } > > +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + RISCVSATPMap *satp_map = opaque; > + uint8_t satp = satp_mode_from_str(name); > + bool value; > + > + value = (satp_map->map & (1 << satp)); > + > + visit_type_bool(v, name, &value, errp); > +} > + > +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + RISCVSATPMap *satp_map = opaque; > + uint8_t satp = satp_mode_from_str(name); > + bool value; > + > + if (!visit_type_bool(v, name, &value, errp)) { > + return; > + } > + > + satp_map->map = deposit32(satp_map->map, satp, 1, value); > + satp_map->init |= 1 << satp; > +} > + > +static void riscv_add_satp_mode_properties(Object *obj) > +{ > + RISCVCPU *cpu = RISCV_CPU(obj); As mentioned above, I think we want to do > + #if defined(TARGET_RISCV32) > + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); #elif defined(TARGET_RISCV64) > + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); #endif > +} > + > #ifndef CONFIG_USER_ONLY > static void riscv_cpu_set_irq(void *opaque, int irq, int level) > { > @@ -1091,6 +1310,8 @@ static void register_cpu_props(Object *obj) > for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > qdev_property_add_static(dev, prop); > } > + > + riscv_add_satp_mode_properties(obj); > } > > static Property riscv_cpu_properties[] = { > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index f5609b62a2..0ffa1bcfd5 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -27,6 +27,7 @@ > #include "qom/object.h" > #include "qemu/int128.h" > #include "cpu_bits.h" > +#include "qapi/qapi-types-common.h" > > #define TCG_GUEST_DEFAULT_MO 0 > > @@ -413,6 +414,17 @@ struct RISCVCPUClass { > ResettablePhases parent_phases; > }; > > +/* > + * map is a 16-bit bitmap: the most significant set bit in map is the maximum > + * satp mode that is supported. > + * > + * init is a 16-bit bitmap used to make sure the user selected a correct > + * configuration as per the specification. > + */ > +typedef struct { > + uint16_t map, init; > +} RISCVSATPMap; > + > struct RISCVCPUConfig { > bool ext_i; > bool ext_e; > @@ -488,6 +500,8 @@ struct RISCVCPUConfig { > bool debug; > > bool short_isa_string; > + > + RISCVSATPMap satp_mode; > }; > > typedef struct RISCVCPUConfig RISCVCPUConfig; > @@ -794,9 +808,14 @@ enum riscv_pmu_event_idx { > /* CSR function table */ > extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; > > +extern const char valid_vm_1_10_32[], valid_vm_1_10_64[]; > + > void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); > void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); > > void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); > > +uint8_t satp_mode_max_from_map(uint32_t map); > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); > + > #endif /* RISCV_CPU_H */ > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 0db2c233e5..6e27299761 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1117,12 +1117,12 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; > static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; > static const target_ulong vsip_writable_mask = MIP_VSSIP; > > -static const char valid_vm_1_10_32[16] = { > +const char valid_vm_1_10_32[16] = { > [VM_1_10_MBARE] = 1, > [VM_1_10_SV32] = 1 > }; > > -static const char valid_vm_1_10_64[16] = { > +const char valid_vm_1_10_64[16] = { > [VM_1_10_MBARE] = 1, > [VM_1_10_SV39] = 1, > [VM_1_10_SV48] = 1, > @@ -1211,10 +1211,17 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, > > static int validate_vm(CPURISCVState *env, target_ulong vm) > { > - if (riscv_cpu_mxl(env) == MXL_RV32) { > - return valid_vm_1_10_32[vm & 0xf]; > + uint8_t satp_mode_max; > + RISCVCPU *cpu = RISCV_CPU(env_cpu(env)); > + bool is_32_bit = riscv_cpu_mxl(env) == MXL_RV32; > + > + vm &= 0xf; > + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > + > + if (is_32_bit) { > + return valid_vm_1_10_32[vm] && (vm <= satp_mode_max); > } else { > - return valid_vm_1_10_64[vm & 0xf]; > + return valid_vm_1_10_64[vm] && (vm <= satp_mode_max); > } > } > > -- > 2.37.2 > Thanks, drew From MAILER-DAEMON Tue Jan 17 18:04:30 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHv0H-00017M-Gu for mharc-qemu-riscv@gnu.org; Tue, 17 Jan 2023 18:04:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHv0C-000156-7j for qemu-riscv@nongnu.org; Tue, 17 Jan 2023 18:04:24 -0500 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHv09-0008PP-7N for qemu-riscv@nongnu.org; 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id y13-20020a63e24d000000b00478eb777d18sm17996936pgj.72.2023.01.17.15.04.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Jan 2023 15:04:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, Alistair.Francis@wdc.com Subject: [PATCH] tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldst Date: Tue, 17 Jan 2023 13:04:15 -1000 Message-Id: <20230117230415.354239-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Jan 2023 23:04:24 -0000 We failed to update this with the w^x split, so misses the fact that true pc-relative offsets are usually small. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index fc0edd811f..01cb67ef7b 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -599,7 +599,7 @@ static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, intptr_t imm12 = sextreg(offset, 0, 12); if (offset != imm12) { - intptr_t diff = offset - (uintptr_t)s->code_ptr; + intptr_t diff = tcg_pcrel_diff(s, (void *)offset); if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { imm12 = sextreg(diff, 0, 12); -- 2.34.1 From MAILER-DAEMON Tue Jan 17 19:26:23 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHwHX-0003F8-Lh for mharc-qemu-riscv@gnu.org; Tue, 17 Jan 2023 19:26:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHwHW-0003Dc-6R; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::92f; envelope-from=alistair23@gmail.com; helo=mail-ua1-x92f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jan 2023 00:26:22 -0000 On Wed, Jan 18, 2023 at 9:05 AM Richard Henderson wrote: > > We failed to update this with the w^x split, so misses the fact > that true pc-relative offsets are usually small. > > Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > tcg/riscv/tcg-target.c.inc | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index fc0edd811f..01cb67ef7b 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -599,7 +599,7 @@ static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, > intptr_t imm12 = sextreg(offset, 0, 12); > > if (offset != imm12) { > - intptr_t diff = offset - (uintptr_t)s->code_ptr; > + intptr_t diff = tcg_pcrel_diff(s, (void *)offset); > > if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { > imm12 = sextreg(diff, 0, 12); > -- > 2.34.1 > > From MAILER-DAEMON Tue Jan 17 19:29:20 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pHwKM-00045T-VY for mharc-qemu-riscv@gnu.org; Tue, 17 Jan 2023 19:29:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pHwKK-000456-W1; Tue, 17 Jan 2023 19:29:17 -0500 Received: from mail-vs1-xe2e.google.com ([2607:f8b0:4864:20::e2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pHwKI-0004Af-9f; Tue, 17 Jan 2023 19:29:16 -0500 Received: by mail-vs1-xe2e.google.com with SMTP id l125so14769840vsc.2; Tue, 17 Jan 2023 16:29:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; 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Tue, 17 Jan 2023 16:29:12 -0800 (PST) MIME-Version: 1.0 References: <20230113103453.42776-1-alexghiti@rivosinc.com> <20230113103453.42776-3-alexghiti@rivosinc.com> <20230117163138.jze47hjeeuwu2k4j@orel> In-Reply-To: <20230117163138.jze47hjeeuwu2k4j@orel> From: Alistair Francis Date: Wed, 18 Jan 2023 10:28:46 +1000 Message-ID: Subject: Re: [PATCH v5 2/2] riscv: Allow user to set the satp mode To: Andrew Jones Cc: Alexandre Ghiti , Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e2e; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jan 2023 00:29:17 -0000 On Wed, Jan 18, 2023 at 2:32 AM Andrew Jones wrote: > > On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote: > > RISC-V specifies multiple sizes for addressable memory and Linux probes for > > the machine's support at startup via the satp CSR register (done in > > csr.c:validate_vm). > > > > As per the specification, sv64 must support sv57, which in turn must > > support sv48...etc. So we can restrict machine support by simply setting the > > "highest" supported mode and the bare mode is always supported. > > > > You can set the satp mode using the new properties "sv32", "sv39", "sv48", > > "sv57" and "sv64" as follows: > > -cpu rv64,sv57=on # Linux will boot using sv57 scheme > > -cpu rv64,sv39=on # Linux will boot using sv39 scheme > > -cpu rv64,sv57=off # Linux will boot using sv48 scheme > > -cpu rv64 # Linux will boot using sv57 scheme by default > > > > We take the highest level set by the user: > > -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme > > > > We make sure that invalid configurations are rejected: > > -cpu rv64,sv32=on # Can't enable 32-bit satp mode in 64-bit > > -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are > > # enabled > > > > We accept "redundant" configurations: > > -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme > > -cpu rv64,sv32=on,sv32=off # Linux will boot using sv57 scheme (the default) > > > > In addition, we now correctly set the device-tree entry 'mmu-type' using > > those new properties. > > > > Co-Developed-by: Ludovic Henry > > Signed-off-by: Ludovic Henry > > Signed-off-by: Alexandre Ghiti > > --- > > hw/riscv/virt.c | 19 ++-- > > target/riscv/cpu.c | 221 +++++++++++++++++++++++++++++++++++++++++++++ > > target/riscv/cpu.h | 19 ++++ > > target/riscv/csr.c | 17 +++- > > 4 files changed, 262 insertions(+), 14 deletions(-) > > > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > > index 94ff2a1584..48d034a5f7 100644 > > --- a/hw/riscv/virt.c > > +++ b/hw/riscv/virt.c > > @@ -228,7 +228,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > > int cpu; > > uint32_t cpu_phandle; > > MachineState *mc = MACHINE(s); > > - char *name, *cpu_name, *core_name, *intc_name; > > + uint8_t satp_mode_max; > > + char *name, *cpu_name, *core_name, *intc_name, *sv_name; > > > > for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { > > cpu_phandle = (*phandle)++; > > @@ -236,14 +237,14 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > > cpu_name = g_strdup_printf("/cpus/cpu@%d", > > s->soc[socket].hartid_base + cpu); > > qemu_fdt_add_subnode(mc->fdt, cpu_name); > > - if (riscv_feature(&s->soc[socket].harts[cpu].env, > > - RISCV_FEATURE_MMU)) { > > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > > - (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); > > I just noticed that for the virt machine type, when the user doesn't > provide a satp mode cpu property on the command line, and hence gets > the default mode, they'll be silently changed from sv48 to sv57. That > default change should be a separate patch which comes after this one. > BTW, why sv57 and not sv48 or sv64? > > > - } else { > > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > > - "riscv,none"); > > - } > > + > > + satp_mode_max = satp_mode_max_from_map( > > + s->soc[socket].harts[cpu].cfg.satp_mode.map); > > + sv_name = g_strdup_printf("riscv,%s", > > + satp_mode_str(satp_mode_max, is_32_bit)); > > + qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", sv_name); > > + g_free(sv_name); > > + > > name = riscv_isa_string(&s->soc[socket].harts[cpu]); > > qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); > > g_free(name); > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 7181b34f86..1f0d040a80 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -27,6 +27,7 @@ > > #include "time_helper.h" > > #include "exec/exec-all.h" > > #include "qapi/error.h" > > +#include "qapi/visitor.h" > > #include "qemu/error-report.h" > > #include "hw/qdev-properties.h" > > #include "migration/vmstate.h" > > @@ -229,6 +230,85 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) > > env->vext_ver = vext_ver; > > } > > > > +static uint8_t satp_mode_from_str(const char *satp_mode_str) > > +{ > > + if (!strncmp(satp_mode_str, "sv32", 4)) { > > + return VM_1_10_SV32; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv39", 4)) { > > + return VM_1_10_SV39; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv48", 4)) { > > + return VM_1_10_SV48; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv57", 4)) { > > + return VM_1_10_SV57; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv64", 4)) { > > + return VM_1_10_SV64; > > + } > > + > > + g_assert_not_reached(); > > +} > > + > > +uint8_t satp_mode_max_from_map(uint32_t map) > > +{ > > + /* map here has at least one bit set, so no problem with clz */ > > + return 31 - __builtin_clz(map); > > +} > > + > > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > > +{ > > + if (is_32_bit) { > > + switch (satp_mode) { > > + case VM_1_10_SV32: > > + return "sv32"; > > + case VM_1_10_MBARE: > > + return "none"; > > + } > > + } else { > > + switch (satp_mode) { > > + case VM_1_10_SV64: > > + return "sv64"; > > + case VM_1_10_SV57: > > + return "sv57"; > > + case VM_1_10_SV48: > > + return "sv48"; > > + case VM_1_10_SV39: > > + return "sv39"; > > + case VM_1_10_MBARE: > > + return "none"; > > + } > > + } > > + > > + g_assert_not_reached(); > > +} > > + > > +static void set_satp_mode(RISCVCPU *cpu, const char *satp_mode_str) > > +{ > > + cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str(satp_mode_str)); > > +} > > + > > +static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit) > > +{ > > + /* > > + * If an mmu is present, the default satp mode is: > > + * - sv32 for 32-bit > > + * - sv57 for 64-bit > > + * Otherwise, it is mbare. > > + */ > > I'd drop the above comment since it only repeats what the code says. > > > + > > + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > > + set_satp_mode(cpu, is_32_bit ? "sv32" : "sv57"); > > + } else { > > + set_satp_mode(cpu, "mbare"); > > nit: Could probably integrate set_satp_mode() into this function since > this function is the only place it's used. > > > + } > > +} > > + > > static void riscv_any_cpu_init(Object *obj) > > { > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > @@ -619,6 +699,53 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > > } > > } > > > > +static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > > +{ > > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > > + const char *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > > Not a problem of this patch, but valid_vm_1_10_32/64 has a strange type. > It's used like a boolean, so should be bool. Since you're touching the > arrays and validate_vm() it'd be nice to change the array type and > the return value of validate_vm() with a separate patch first. > > > + > > + /* Get rid of 32-bit/64-bit incompatibility */ > > + for (int i = 0; i < 16; ++i) { > > + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > > If we ever define mode=1 for rv64, then 'sv32=on' will be incorrectly > accepted as an alias. I think we should simply not define the sv32 > property for rv64 nor the rv64-only modes for rv32. So, down in > riscv_add_satp_mode_properties() we can add some > > #if defined(TARGET_RISCV32) > ... > #elif defined(TARGET_RISCV64) > ... > #endif Do not add any #if defined(TARGET_RISCV32) to QEMU. We are aiming for the riscv64-softmmu to be able to emulate 32-bit CPUs and compile time macros are the wrong solution here. Instead you can get the xlen of the hart and use that. Alistair > > and then drop the check here. > > > + error_setg(errp, "satp_mode %s is not valid", > > + satp_mode_str(i, !rv32)); > > + return; > > + } > > + } > > + > > + /* > > + * Make sure the user did not ask for an invalid configuration as per > > + * the specification. > > + */ > > + if (!rv32) { > > + uint8_t satp_mode_max; > > + > > + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > > + > > + for (int i = satp_mode_max - 1; i >= 0; --i) { > > + if (!(cpu->cfg.satp_mode.map & (1 << i)) && > > + (cpu->cfg.satp_mode.init & (1 << i)) && > > + valid_vm[i]) { > > + error_setg(errp, "cannot disable %s satp mode if %s " > > + "is enabled", satp_mode_str(i, false), > > + satp_mode_str(satp_mode_max, false)); > > + return; > > + } > > + } > > + } > > +} > > + > > +static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > > +{ > > + Error *local_err = NULL; > > + > > + riscv_cpu_satp_mode_finalize(cpu, &local_err); > > + if (local_err != NULL) { > > + error_propagate(errp, local_err); > > + return; > > + } > > +} > > + > > static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > { > > CPUState *cs = CPU(dev); > > @@ -919,6 +1046,55 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > } > > #endif > > > > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > > + > > + if (cpu->cfg.satp_mode.map == 0) { > > + /* > > + * If unset by both the user and the cpu, we fallback to the default > > + * satp mode. > > + */ > > + if (cpu->cfg.satp_mode.init == 0) { > > + set_satp_mode_default(cpu, rv32); > > + } else { > > + /* > > + * Find the lowest level that was disabled and then enable the > > + * first valid level below which can be found in > > + * valid_vm_1_10_32/64. > > + */ > > + const char *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > > + > > + for (int i = 0; i < 16; ++i) { > > 'init' will never have bit0 (mbare) set, so we can start at i=1, which is > good, because the condition below assumes it can index an array at i-1. > > > + if (!(cpu->cfg.satp_mode.map & (1 << i)) && > > + (cpu->cfg.satp_mode.init & (1 << i)) && > > + valid_vm[i]) { > > + for (int j = i - 1; j >= 0; --j) { > > + if (valid_vm[j]) { > > + cpu->cfg.satp_mode.map |= (1 << j); > > + break; > > + } > > + } > > + break; > > + } > > + } > > + > > + /* > > + * The user actually init a satp mode but appears to be invalid > > + * (ex: "-cpu rv64,sv32=on,sv32=off"). Fallback to the default > > This example, where sv32 is used with rv64, won't be possible if we don't > give rv64 the sv32 property. > > > + * mode. > > + */ > > + if (cpu->cfg.satp_mode.map == 0) { > > + set_satp_mode_default(cpu, rv32); > > If the user does rv64,sv39=on,sv39=off, then I think we should be creating > an mbare machine, rather than using the default. > > > + } > > + } > > + } > > Why isn't all this 'if (cpu->cfg.satp_mode.map == 0)' block above at the > top of riscv_cpu_satp_mode_finalize() instead of here? > > > + > > + riscv_cpu_finalize_features(cpu, &local_err); > > + if (local_err != NULL) { > > + error_propagate(errp, local_err); > > + return; > > + } > > + > > + > > extra blank line > > > riscv_cpu_register_gdb_regs_for_features(cs); > > > > qemu_init_vcpu(cs); > > @@ -927,6 +1103,49 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > mcc->parent_realize(dev, errp); > > } > > > > +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, > > + void *opaque, Error **errp) > > +{ > > + RISCVSATPMap *satp_map = opaque; > > + uint8_t satp = satp_mode_from_str(name); > > + bool value; > > + > > + value = (satp_map->map & (1 << satp)); > > + > > + visit_type_bool(v, name, &value, errp); > > +} > > + > > +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, > > + void *opaque, Error **errp) > > +{ > > + RISCVSATPMap *satp_map = opaque; > > + uint8_t satp = satp_mode_from_str(name); > > + bool value; > > + > > + if (!visit_type_bool(v, name, &value, errp)) { > > + return; > > + } > > + > > + satp_map->map = deposit32(satp_map->map, satp, 1, value); > > + satp_map->init |= 1 << satp; > > +} > > + > > +static void riscv_add_satp_mode_properties(Object *obj) > > +{ > > + RISCVCPU *cpu = RISCV_CPU(obj); > > As mentioned above, I think we want to do > > > + > #if defined(TARGET_RISCV32) > > + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > #elif defined(TARGET_RISCV64) > > + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > #endif > > +} > > + > > #ifndef CONFIG_USER_ONLY > > static void riscv_cpu_set_irq(void *opaque, int irq, int level) > > { > > @@ -1091,6 +1310,8 @@ static void register_cpu_props(Object *obj) > > for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > > qdev_property_add_static(dev, prop); > > } > > + > > + riscv_add_satp_mode_properties(obj); > > } > > > > static Property riscv_cpu_properties[] = { > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index f5609b62a2..0ffa1bcfd5 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -27,6 +27,7 @@ > > #include "qom/object.h" > > #include "qemu/int128.h" > > #include "cpu_bits.h" > > +#include "qapi/qapi-types-common.h" > > > > #define TCG_GUEST_DEFAULT_MO 0 > > > > @@ -413,6 +414,17 @@ struct RISCVCPUClass { > > ResettablePhases parent_phases; > > }; > > > > +/* > > + * map is a 16-bit bitmap: the most significant set bit in map is the maximum > > + * satp mode that is supported. > > + * > > + * init is a 16-bit bitmap used to make sure the user selected a correct > > + * configuration as per the specification. > > + */ > > +typedef struct { > > + uint16_t map, init; > > +} RISCVSATPMap; > > + > > struct RISCVCPUConfig { > > bool ext_i; > > bool ext_e; > > @@ -488,6 +500,8 @@ struct RISCVCPUConfig { > > bool debug; > > > > bool short_isa_string; > > + > > + RISCVSATPMap satp_mode; > > }; > > > > typedef struct RISCVCPUConfig RISCVCPUConfig; > > @@ -794,9 +808,14 @@ enum riscv_pmu_event_idx { > > /* CSR function table */ > > extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; > > > > +extern const char valid_vm_1_10_32[], valid_vm_1_10_64[]; > > + > > void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); > > void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); > > > > void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); > > > > +uint8_t satp_mode_max_from_map(uint32_t map); > > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); > > + > > #endif /* RISCV_CPU_H */ > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 0db2c233e5..6e27299761 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -1117,12 +1117,12 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; > > static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; > > static const target_ulong vsip_writable_mask = MIP_VSSIP; > > > > -static const char valid_vm_1_10_32[16] = { > > +const char valid_vm_1_10_32[16] = { > > [VM_1_10_MBARE] = 1, > > [VM_1_10_SV32] = 1 > > }; > > > > -static const char valid_vm_1_10_64[16] = { > > +const char valid_vm_1_10_64[16] = { > > [VM_1_10_MBARE] = 1, > > [VM_1_10_SV39] = 1, > > [VM_1_10_SV48] = 1, > > @@ -1211,10 +1211,17 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, > > > > static int validate_vm(CPURISCVState *env, target_ulong vm) > > { > > - if (riscv_cpu_mxl(env) == MXL_RV32) { > > - return valid_vm_1_10_32[vm & 0xf]; > > + uint8_t satp_mode_max; > > + RISCVCPU *cpu = RISCV_CPU(env_cpu(env)); > > + bool is_32_bit = riscv_cpu_mxl(env) == MXL_RV32; > > + > > + vm &= 0xf; > > + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > > + > > + if (is_32_bit) { > > + return valid_vm_1_10_32[vm] && (vm <= satp_mode_max); > > } else { > > - return valid_vm_1_10_64[vm & 0xf]; > > + return valid_vm_1_10_64[vm] && (vm <= satp_mode_max); > > } > > } > > > > -- > > 2.37.2 > > > > Thanks, > drew > From MAILER-DAEMON Wed Jan 18 05:01:06 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pI5Fi-0004vP-O8 for mharc-qemu-riscv@gnu.org; Wed, 18 Jan 2023 05:01:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pI5Fh-0004tQ-Gk for qemu-riscv@nongnu.org; Wed, 18 Jan 2023 05:01:05 -0500 Received: from mail-oi1-x244.google.com ([2607:f8b0:4864:20::244]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pI5Fc-0006bS-Sq for qemu-riscv@nongnu.org; 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boundary="------------KV11qSCFGCDoxBrJM0rPUfbN" Message-ID: Date: Wed, 18 Jan 2023 07:00:38 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH 1/2] target/arm: Introduce helper_set_rounding_mode_chkfrm Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bin.meng@windriver.com, abdulras@google.com References: <20230115160657.3169274-1-richard.henderson@linaro.org> <20230115160657.3169274-2-richard.henderson@linaro.org> From: Daniel Henrique Barboza In-Reply-To: <20230115160657.3169274-2-richard.henderson@linaro.org> Received-SPF: pass client-ip=2607:f8b0:4864:20::244; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x244.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, NICE_REPLY_A=-0.097, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jan 2023 10:01:05 -0000 This is a multi-part message in MIME format. --------------KV11qSCFGCDoxBrJM0rPUfbN Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit s/arm/riscv in subject/commit title ^ On 1/15/23 13:06, Richard Henderson wrote: > The new helper always validates the contents of FRM, even > if the new rounding mode is not DYN. This is required by > the vector unit. > > Track whether we've validated FRM separately from whether > we've updated fp_status with a given rounding mode, so that > we can elide calls correctly. > > This partially reverts d6c4d3f2a69 which attempted the to do > the same thing, but with two calls to gen_set_rm(), which is > both inefficient and tickles an assertion in decode_save_opc. > > Resolves:https://gitlab.com/qemu-project/qemu/-/issues/1441 > Signed-off-by: Richard Henderson > --- Reviewed-by: Daniel Henrique Barboza > target/riscv/helper.h | 1 + > target/riscv/fpu_helper.c | 37 +++++++++++++++++++++++++ > target/riscv/translate.c | 19 +++++++++++++ > target/riscv/insn_trans/trans_rvv.c.inc | 24 +++------------- > 4 files changed, 61 insertions(+), 20 deletions(-) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index 227c7122ef..9792ab5086 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -3,6 +3,7 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32) > > /* Floating Point - rounding mode */ > DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) > +DEF_HELPER_FLAGS_2(set_rounding_mode_chkfrm, TCG_CALL_NO_WG, void, env, i32) > DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env) > > /* Floating Point - fused */ > diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c > index 5699c9517f..96817df8ef 100644 > --- a/target/riscv/fpu_helper.c > +++ b/target/riscv/fpu_helper.c > @@ -81,6 +81,43 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) > set_float_rounding_mode(softrm, &env->fp_status); > } > > +void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm) > +{ > + int softrm; > + > + /* Always validate frm, even if rm != DYN. */ > + if (unlikely(env->frm >= 5)) { > + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); > + } > + if (rm == RISCV_FRM_DYN) { > + rm = env->frm; > + } > + switch (rm) { > + case RISCV_FRM_RNE: > + softrm = float_round_nearest_even; > + break; > + case RISCV_FRM_RTZ: > + softrm = float_round_to_zero; > + break; > + case RISCV_FRM_RDN: > + softrm = float_round_down; > + break; > + case RISCV_FRM_RUP: > + softrm = float_round_up; > + break; > + case RISCV_FRM_RMM: > + softrm = float_round_ties_away; > + break; > + case RISCV_FRM_ROD: > + softrm = float_round_to_odd; > + break; > + default: > + g_assert_not_reached(); > + } > + > + set_float_rounding_mode(softrm, &env->fp_status); > +} > + > void helper_set_rod_rounding_mode(CPURISCVState *env) > { > set_float_rounding_mode(float_round_to_odd, &env->fp_status); > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index df38db7553..493c3815e1 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -114,6 +114,8 @@ typedef struct DisasContext { > bool pm_base_enabled; > /* Use icount trigger for native debug */ > bool itrigger; > + /* FRM is known to contain a valid value. */ > + bool frm_valid; > /* TCG of the current insn_start */ > TCGOp *insn_start; > } DisasContext; > @@ -674,12 +676,29 @@ static void gen_set_rm(DisasContext *ctx, int rm) > gen_helper_set_rod_rounding_mode(cpu_env); > return; > } > + if (rm == RISCV_FRM_DYN) { > + /* The helper will return only if frm valid. */ > + ctx->frm_valid = true; > + } > > /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ > decode_save_opc(ctx); > gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); > } > > +static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) > +{ > + if (ctx->frm == rm && ctx->frm_valid) { > + return; > + } > + ctx->frm = rm; > + ctx->frm_valid = true; > + > + /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ > + decode_save_opc(ctx); > + gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm)); > +} > + > static int ex_plus_1(DisasContext *ctx, int nf) > { > return nf + 1; > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index d455acedbf..bbb5c3a7b5 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -2679,13 +2679,9 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, > int rm) > { > if (checkfn(s, a)) { > - if (rm != RISCV_FRM_DYN) { > - gen_set_rm(s, RISCV_FRM_DYN); > - } > - > uint32_t data = 0; > TCGLabel *over = gen_new_label(); > - gen_set_rm(s, rm); > + gen_set_rm_chkfrm(s, rm); > tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); > tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); > > @@ -2882,17 +2878,13 @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a) > static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ > { \ > if (CHECK(s, a)) { \ > - if (FRM != RISCV_FRM_DYN) { \ > - gen_set_rm(s, RISCV_FRM_DYN); \ > - } \ > - \ > uint32_t data = 0; \ > static gen_helper_gvec_3_ptr * const fns[2] = { \ > gen_helper_##HELPER##_h, \ > gen_helper_##HELPER##_w, \ > }; \ > TCGLabel *over = gen_new_label(); \ > - gen_set_rm(s, FRM); \ > + gen_set_rm_chkfrm(s, FRM); \ > tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ > tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ > \ > @@ -3005,17 +2997,13 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) > static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ > { \ > if (CHECK(s, a)) { \ > - if (FRM != RISCV_FRM_DYN) { \ > - gen_set_rm(s, RISCV_FRM_DYN); \ > - } \ > - \ > uint32_t data = 0; \ > static gen_helper_gvec_3_ptr * const fns[2] = { \ > gen_helper_##HELPER##_h, \ > gen_helper_##HELPER##_w, \ > }; \ > TCGLabel *over = gen_new_label(); \ > - gen_set_rm(s, FRM); \ > + gen_set_rm_chkfrm(s, FRM); \ > tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ > tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ > \ > @@ -3060,10 +3048,6 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a) > static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ > { \ > if (opxfv_narrow_check(s, a)) { \ > - if (FRM != RISCV_FRM_DYN) { \ > - gen_set_rm(s, RISCV_FRM_DYN); \ > - } \ > - \ > uint32_t data = 0; \ > static gen_helper_gvec_3_ptr * const fns[3] = { \ > gen_helper_##HELPER##_b, \ > @@ -3071,7 +3055,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ > gen_helper_##HELPER##_w, \ > }; \ > TCGLabel *over = gen_new_label(); \ > - gen_set_rm(s, FRM); \ > + gen_set_rm_chkfrm(s, FRM); \ > tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ > tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ > \ --------------KV11qSCFGCDoxBrJM0rPUfbN Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 7bit s/arm/riscv in subject/commit title ^

On 1/15/23 13:06, Richard Henderson wrote:
The new helper always validates the contents of FRM, even
if the new rounding mode is not DYN.  This is required by
the vector unit.

Track whether we've validated FRM separately from whether
we've updated fp_status with a given rounding mode, so that
we can elide calls correctly.

This partially reverts d6c4d3f2a69 which attempted the to do
the same thing, but with two calls to gen_set_rm(), which is
both inefficient and tickles an assertion in decode_save_opc.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1441
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---

Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

 target/riscv/helper.h                   |  1 +
 target/riscv/fpu_helper.c               | 37 +++++++++++++++++++++++++
 target/riscv/translate.c                | 19 +++++++++++++
 target/riscv/insn_trans/trans_rvv.c.inc | 24 +++-------------
 4 files changed, 61 insertions(+), 20 deletions(-)

diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 227c7122ef..9792ab5086 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -3,6 +3,7 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32)
 
 /* Floating Point - rounding mode */
 DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32)
+DEF_HELPER_FLAGS_2(set_rounding_mode_chkfrm, TCG_CALL_NO_WG, void, env, i32)
 DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env)
 
 /* Floating Point - fused */
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 5699c9517f..96817df8ef 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -81,6 +81,43 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
     set_float_rounding_mode(softrm, &env->fp_status);
 }
 
+void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm)
+{
+    int softrm;
+
+    /* Always validate frm, even if rm != DYN. */
+    if (unlikely(env->frm >= 5)) {
+        riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
+    }
+    if (rm == RISCV_FRM_DYN) {
+        rm = env->frm;
+    }
+    switch (rm) {
+    case RISCV_FRM_RNE:
+        softrm = float_round_nearest_even;
+        break;
+    case RISCV_FRM_RTZ:
+        softrm = float_round_to_zero;
+        break;
+    case RISCV_FRM_RDN:
+        softrm = float_round_down;
+        break;
+    case RISCV_FRM_RUP:
+        softrm = float_round_up;
+        break;
+    case RISCV_FRM_RMM:
+        softrm = float_round_ties_away;
+        break;
+    case RISCV_FRM_ROD:
+        softrm = float_round_to_odd;
+        break;
+    default:
+        g_assert_not_reached();
+    }
+
+    set_float_rounding_mode(softrm, &env->fp_status);
+}
+
 void helper_set_rod_rounding_mode(CPURISCVState *env)
 {
     set_float_rounding_mode(float_round_to_odd, &env->fp_status);
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index df38db7553..493c3815e1 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -114,6 +114,8 @@ typedef struct DisasContext {
     bool pm_base_enabled;
     /* Use icount trigger for native debug */
     bool itrigger;
+    /* FRM is known to contain a valid value. */
+    bool frm_valid;
     /* TCG of the current insn_start */
     TCGOp *insn_start;
 } DisasContext;
@@ -674,12 +676,29 @@ static void gen_set_rm(DisasContext *ctx, int rm)
         gen_helper_set_rod_rounding_mode(cpu_env);
         return;
     }
+    if (rm == RISCV_FRM_DYN) {
+        /* The helper will return only if frm valid. */
+        ctx->frm_valid = true;
+    }
 
     /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
     decode_save_opc(ctx);
     gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm));
 }
 
+static void gen_set_rm_chkfrm(DisasContext *ctx, int rm)
+{
+    if (ctx->frm == rm && ctx->frm_valid) {
+        return;
+    }
+    ctx->frm = rm;
+    ctx->frm_valid = true;
+
+    /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */
+    decode_save_opc(ctx);
+    gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm));
+}
+
 static int ex_plus_1(DisasContext *ctx, int nf)
 {
     return nf + 1;
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index d455acedbf..bbb5c3a7b5 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2679,13 +2679,9 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
                     int rm)
 {
     if (checkfn(s, a)) {
-        if (rm != RISCV_FRM_DYN) {
-            gen_set_rm(s, RISCV_FRM_DYN);
-        }
-
         uint32_t data = 0;
         TCGLabel *over = gen_new_label();
-        gen_set_rm(s, rm);
+        gen_set_rm_chkfrm(s, rm);
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over);
 
@@ -2882,17 +2878,13 @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a)
 static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
 {                                                                  \
     if (CHECK(s, a)) {                                             \
-        if (FRM != RISCV_FRM_DYN) {                                \
-            gen_set_rm(s, RISCV_FRM_DYN);                          \
-        }                                                          \
-                                                                   \
         uint32_t data = 0;                                         \
         static gen_helper_gvec_3_ptr * const fns[2] = {            \
             gen_helper_##HELPER##_h,                               \
             gen_helper_##HELPER##_w,                               \
         };                                                         \
         TCGLabel *over = gen_new_label();                          \
-        gen_set_rm(s, FRM);                                        \
+        gen_set_rm_chkfrm(s, FRM);                                 \
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
@@ -3005,17 +2997,13 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a)
 static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
 {                                                                  \
     if (CHECK(s, a)) {                                             \
-        if (FRM != RISCV_FRM_DYN) {                                \
-            gen_set_rm(s, RISCV_FRM_DYN);                          \
-        }                                                          \
-                                                                   \
         uint32_t data = 0;                                         \
         static gen_helper_gvec_3_ptr * const fns[2] = {            \
             gen_helper_##HELPER##_h,                               \
             gen_helper_##HELPER##_w,                               \
         };                                                         \
         TCGLabel *over = gen_new_label();                          \
-        gen_set_rm(s, FRM);                                        \
+        gen_set_rm_chkfrm(s, FRM);                                 \
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \
@@ -3060,10 +3048,6 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a)
 static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
 {                                                                  \
     if (opxfv_narrow_check(s, a)) {                                \
-        if (FRM != RISCV_FRM_DYN) {                                \
-            gen_set_rm(s, RISCV_FRM_DYN);                          \
-        }                                                          \
-                                                                   \
         uint32_t data = 0;                                         \
         static gen_helper_gvec_3_ptr * const fns[3] = {            \
             gen_helper_##HELPER##_b,                               \
@@ -3071,7 +3055,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)              \
             gen_helper_##HELPER##_w,                               \
         };                                                         \
         TCGLabel *over = gen_new_label();                          \
-        gen_set_rm(s, FRM);                                        \
+        gen_set_rm_chkfrm(s, FRM);                                 \
         tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over);          \
         tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \
                                                                    \

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Wed, 18 Jan 2023 02:01:14 -0800 (PST) Received: from [192.168.68.107] ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id v63-20020acaac42000000b003670342726fsm3871949oie.12.2023.01.18.02.01.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Jan 2023 02:01:13 -0800 (PST) Message-ID: Date: Wed, 18 Jan 2023 07:01:10 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH 2/2] target/riscv: Remove helper_set_rod_rounding_mode Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bin.meng@windriver.com, abdulras@google.com References: <20230115160657.3169274-1-richard.henderson@linaro.org> <20230115160657.3169274-3-richard.henderson@linaro.org> From: Daniel Henrique Barboza In-Reply-To: <20230115160657.3169274-3-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x22e.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.097, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jan 2023 10:01:17 -0000 X-List-Received-Date: Wed, 18 Jan 2023 10:01:17 -0000 On 1/15/23 13:06, Richard Henderson wrote: > The only setting of RISCV_FRM_ROD is from the vector unit, > and now handled by helper_set_rounding_mode_chkfrm. > This helper is now unused. > > Signed-off-by: Richard Henderson > --- Reviewed-by: Daniel Henrique Barboza > target/riscv/helper.h | 1 - > target/riscv/fpu_helper.c | 5 ----- > target/riscv/translate.c | 4 ---- > 3 files changed, 10 deletions(-) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index 9792ab5086..58a30f03d6 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -4,7 +4,6 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32) > /* Floating Point - rounding mode */ > DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) > DEF_HELPER_FLAGS_2(set_rounding_mode_chkfrm, TCG_CALL_NO_WG, void, env, i32) > -DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env) > > /* Floating Point - fused */ > DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) > diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c > index 96817df8ef..449d236df6 100644 > --- a/target/riscv/fpu_helper.c > +++ b/target/riscv/fpu_helper.c > @@ -118,11 +118,6 @@ void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm) > set_float_rounding_mode(softrm, &env->fp_status); > } > > -void helper_set_rod_rounding_mode(CPURISCVState *env) > -{ > - set_float_rounding_mode(float_round_to_odd, &env->fp_status); > -} > - > static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2, > uint64_t rs3, int flags) > { > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 493c3815e1..01cc30a365 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -672,10 +672,6 @@ static void gen_set_rm(DisasContext *ctx, int rm) > } > ctx->frm = rm; > > - if (rm == RISCV_FRM_ROD) { > - gen_helper_set_rod_rounding_mode(cpu_env); > - return; > - } > if (rm == RISCV_FRM_DYN) { > /* The helper will return only if frm valid. */ > ctx->frm_valid = true; From MAILER-DAEMON Wed Jan 18 07:19:40 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pI7Po-0004vV-Le for mharc-qemu-riscv@gnu.org; Wed, 18 Jan 2023 07:19:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pI7PV-0004uc-4q for qemu-riscv@nongnu.org; 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[2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id z12-20020adfd0cc000000b002bdff778d87sm8344053wrh.34.2023.01.18.04.19.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 04:19:16 -0800 (PST) Date: Wed, 18 Jan 2023 13:19:16 +0100 From: Andrew Jones To: Alistair Francis Cc: Alexandre Ghiti , Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Subject: Re: [PATCH v5 2/2] riscv: Allow user to set the satp mode Message-ID: <20230118121916.6aqj57leen72z5tz@orel> References: <20230113103453.42776-1-alexghiti@rivosinc.com> <20230113103453.42776-3-alexghiti@rivosinc.com> <20230117163138.jze47hjeeuwu2k4j@orel> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=ajones@ventanamicro.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jan 2023 12:19:24 -0000 On Wed, Jan 18, 2023 at 10:28:46AM +1000, Alistair Francis wrote: > On Wed, Jan 18, 2023 at 2:32 AM Andrew Jones wrote: > > > > On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote: ... > > > + > > > + /* Get rid of 32-bit/64-bit incompatibility */ > > > + for (int i = 0; i < 16; ++i) { > > > + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > > > > If we ever define mode=1 for rv64, then 'sv32=on' will be incorrectly > > accepted as an alias. I think we should simply not define the sv32 > > property for rv64 nor the rv64-only modes for rv32. So, down in > > riscv_add_satp_mode_properties() we can add some > > > > #if defined(TARGET_RISCV32) > > ... > > #elif defined(TARGET_RISCV64) > > ... > > #endif > > Do not add any #if defined(TARGET_RISCV32) to QEMU. > > We are aiming for the riscv64-softmmu to be able to emulate 32-bit > CPUs and compile time macros are the wrong solution here. Instead you > can get the xlen of the hart and use that. > Does this mean we want to be able to do the following? qemu-system-riscv64 -cpu rv32,sv32=on ... If so, then can we move the object_property_add() for sv32 to rv32_base_cpu_init() and the rest to rv64_base_cpu_init()? Currently, that would be doing the same thing as proposed above, since those functions are under TARGET_RISCV* defines, but I guess the object_property_add()'s would then be in more or less the right places for when the 32-bit emulation support work is started. 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[80.187.99.5]) by smtp.gmail.com with ESMTPSA id l14-20020a05620a28ce00b007062139ecb3sm10885240qkp.95.2023.01.18.08.09.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Jan 2023 08:09:34 -0800 (PST) Message-ID: Date: Wed, 18 Jan 2023 17:09:31 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 Subject: Re: [PATCH v2 2/4] bulk: Coding style fixes To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, Richard Henderson References: <20230111083909.42624-1-philmd@linaro.org> <20230111083909.42624-3-philmd@linaro.org> From: Thomas Huth In-Reply-To: <20230111083909.42624-3-philmd@linaro.org> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.089, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jan 2023 16:09:39 -0000 On 11/01/2023 09.39, Philippe Mathieu-Daudé wrote: > Fix the following checkpatch.pl violation on lines using the > TARGET_FMT_plx definition to avoid: > > WARNING: line over 80 characters It's just a warning... > @@ -420,8 +421,9 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx, > hwaddr curaddr; > uint32_t a0, a1, a2, a3; > > - qemu_log("Page table: " TARGET_FMT_plx " len " TARGET_FMT_plx > - "\n", ppc_hash32_hpt_base(cpu), > + qemu_log("Page table: " TARGET_FMT_plx > + " len " TARGET_FMT_plx "\n", > + ppc_hash32_hpt_base(cpu), > ppc_hash32_hpt_mask(cpu) + 0x80); > for (curaddr = ppc_hash32_hpt_base(cpu); > curaddr < (ppc_hash32_hpt_base(cpu) ... and in cases like this, I'd really prefer the original line. I think it would be better to just fix it if checkpatch.pl really throws an ERROR instead of a WARNING. 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Wed, 18 Jan 2023 08:29:53 -0800 (PST) MIME-Version: 1.0 References: <20230113103453.42776-1-alexghiti@rivosinc.com> <20230113103453.42776-3-alexghiti@rivosinc.com> <20230117163138.jze47hjeeuwu2k4j@orel> In-Reply-To: <20230117163138.jze47hjeeuwu2k4j@orel> From: Alexandre Ghiti Date: Wed, 18 Jan 2023 17:29:43 +0100 Message-ID: Subject: Re: [PATCH v5 2/2] riscv: Allow user to set the satp mode To: Andrew Jones Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jan 2023 16:29:59 -0000 Hey Andrew, On Tue, Jan 17, 2023 at 5:31 PM Andrew Jones wrote: > > On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote: > > RISC-V specifies multiple sizes for addressable memory and Linux probes for > > the machine's support at startup via the satp CSR register (done in > > csr.c:validate_vm). > > > > As per the specification, sv64 must support sv57, which in turn must > > support sv48...etc. So we can restrict machine support by simply setting the > > "highest" supported mode and the bare mode is always supported. > > > > You can set the satp mode using the new properties "sv32", "sv39", "sv48", > > "sv57" and "sv64" as follows: > > -cpu rv64,sv57=on # Linux will boot using sv57 scheme > > -cpu rv64,sv39=on # Linux will boot using sv39 scheme > > -cpu rv64,sv57=off # Linux will boot using sv48 scheme > > -cpu rv64 # Linux will boot using sv57 scheme by default > > > > We take the highest level set by the user: > > -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme > > > > We make sure that invalid configurations are rejected: > > -cpu rv64,sv32=on # Can't enable 32-bit satp mode in 64-bit > > -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are > > # enabled > > > > We accept "redundant" configurations: > > -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme > > -cpu rv64,sv32=on,sv32=off # Linux will boot using sv57 scheme (the default) > > > > In addition, we now correctly set the device-tree entry 'mmu-type' using > > those new properties. > > > > Co-Developed-by: Ludovic Henry > > Signed-off-by: Ludovic Henry > > Signed-off-by: Alexandre Ghiti > > --- > > hw/riscv/virt.c | 19 ++-- > > target/riscv/cpu.c | 221 +++++++++++++++++++++++++++++++++++++++++++++ > > target/riscv/cpu.h | 19 ++++ > > target/riscv/csr.c | 17 +++- > > 4 files changed, 262 insertions(+), 14 deletions(-) > > > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > > index 94ff2a1584..48d034a5f7 100644 > > --- a/hw/riscv/virt.c > > +++ b/hw/riscv/virt.c > > @@ -228,7 +228,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > > int cpu; > > uint32_t cpu_phandle; > > MachineState *mc = MACHINE(s); > > - char *name, *cpu_name, *core_name, *intc_name; > > + uint8_t satp_mode_max; > > + char *name, *cpu_name, *core_name, *intc_name, *sv_name; > > > > for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { > > cpu_phandle = (*phandle)++; > > @@ -236,14 +237,14 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > > cpu_name = g_strdup_printf("/cpus/cpu@%d", > > s->soc[socket].hartid_base + cpu); > > qemu_fdt_add_subnode(mc->fdt, cpu_name); > > - if (riscv_feature(&s->soc[socket].harts[cpu].env, > > - RISCV_FEATURE_MMU)) { > > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > > - (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); > > I just noticed that for the virt machine type, when the user doesn't > provide a satp mode cpu property on the command line, and hence gets > the default mode, they'll be silently changed from sv48 to sv57. That > default change should be a separate patch which comes after this one. > BTW, why sv57 and not sv48 or sv64? The device tree entry should match the max available satp mode even though it makes little sense to have this entry in the first place: the max satp mode is easily discoverable at runtime (the kernel does that and does not care about the device tree entry). But yes, this fix was mentioned at the very end of the commit log, which was weird anyway, so I'll move that to its own patch. > > > - } else { > > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > > - "riscv,none"); > > - } > > + > > + satp_mode_max = satp_mode_max_from_map( > > + s->soc[socket].harts[cpu].cfg.satp_mode.map); > > + sv_name = g_strdup_printf("riscv,%s", > > + satp_mode_str(satp_mode_max, is_32_bit)); > > + qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", sv_name); > > + g_free(sv_name); > > + > > name = riscv_isa_string(&s->soc[socket].harts[cpu]); > > qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); > > g_free(name); > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 7181b34f86..1f0d040a80 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -27,6 +27,7 @@ > > #include "time_helper.h" > > #include "exec/exec-all.h" > > #include "qapi/error.h" > > +#include "qapi/visitor.h" > > #include "qemu/error-report.h" > > #include "hw/qdev-properties.h" > > #include "migration/vmstate.h" > > @@ -229,6 +230,85 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) > > env->vext_ver = vext_ver; > > } > > > > +static uint8_t satp_mode_from_str(const char *satp_mode_str) > > +{ > > + if (!strncmp(satp_mode_str, "sv32", 4)) { > > + return VM_1_10_SV32; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv39", 4)) { > > + return VM_1_10_SV39; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv48", 4)) { > > + return VM_1_10_SV48; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv57", 4)) { > > + return VM_1_10_SV57; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv64", 4)) { > > + return VM_1_10_SV64; > > + } > > + > > + g_assert_not_reached(); > > +} > > + > > +uint8_t satp_mode_max_from_map(uint32_t map) > > +{ > > + /* map here has at least one bit set, so no problem with clz */ > > + return 31 - __builtin_clz(map); > > +} > > + > > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > > +{ > > + if (is_32_bit) { > > + switch (satp_mode) { > > + case VM_1_10_SV32: > > + return "sv32"; > > + case VM_1_10_MBARE: > > + return "none"; > > + } > > + } else { > > + switch (satp_mode) { > > + case VM_1_10_SV64: > > + return "sv64"; > > + case VM_1_10_SV57: > > + return "sv57"; > > + case VM_1_10_SV48: > > + return "sv48"; > > + case VM_1_10_SV39: > > + return "sv39"; > > + case VM_1_10_MBARE: > > + return "none"; > > + } > > + } > > + > > + g_assert_not_reached(); > > +} > > + > > +static void set_satp_mode(RISCVCPU *cpu, const char *satp_mode_str) > > +{ > > + cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str(satp_mode_str)); > > +} > > + > > +static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit) > > +{ > > + /* > > + * If an mmu is present, the default satp mode is: > > + * - sv32 for 32-bit > > + * - sv57 for 64-bit > > + * Otherwise, it is mbare. > > + */ > > I'd drop the above comment since it only repeats what the code says. Ok > > > + > > + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > > + set_satp_mode(cpu, is_32_bit ? "sv32" : "sv57"); > > + } else { > > + set_satp_mode(cpu, "mbare"); > > nit: Could probably integrate set_satp_mode() into this function since > this function is the only place it's used. At the moment yes, but this was a request from Frank to have a helper set the default satp mode in the cpu init functions, which I did not do here because I was unsure: @Frank Chang What should I use for sifive_e and sifive_u? rv64 will use the default mode. > > > + } > > +} > > + > > static void riscv_any_cpu_init(Object *obj) > > { > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > @@ -619,6 +699,53 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > > } > > } > > > > +static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > > +{ > > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > > + const char *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > > Not a problem of this patch, but valid_vm_1_10_32/64 has a strange type. > It's used like a boolean, so should be bool. Since you're touching the > arrays and validate_vm() it'd be nice to change the array type and > the return value of validate_vm() with a separate patch first. Sure, I can do that. > > > + > > + /* Get rid of 32-bit/64-bit incompatibility */ > > + for (int i = 0; i < 16; ++i) { > > + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > > If we ever define mode=1 for rv64, then 'sv32=on' will be incorrectly > accepted as an alias. I think we should simply not define the sv32 > property for rv64 nor the rv64-only modes for rv32. So, down in > riscv_add_satp_mode_properties() we can add some > > #if defined(TARGET_RISCV32) > ... > #elif defined(TARGET_RISCV64) > ... > #endif > > and then drop the check here. > > > + error_setg(errp, "satp_mode %s is not valid", > > + satp_mode_str(i, !rv32)); > > + return; > > + } > > + } > > + > > + /* > > + * Make sure the user did not ask for an invalid configuration as per > > + * the specification. > > + */ > > + if (!rv32) { > > + uint8_t satp_mode_max; > > + > > + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > > + > > + for (int i = satp_mode_max - 1; i >= 0; --i) { > > + if (!(cpu->cfg.satp_mode.map & (1 << i)) && > > + (cpu->cfg.satp_mode.init & (1 << i)) && > > + valid_vm[i]) { > > + error_setg(errp, "cannot disable %s satp mode if %s " > > + "is enabled", satp_mode_str(i, false), > > + satp_mode_str(satp_mode_max, false)); > > + return; > > + } > > + } > > + } > > +} > > + > > +static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > > +{ > > + Error *local_err = NULL; > > + > > + riscv_cpu_satp_mode_finalize(cpu, &local_err); > > + if (local_err != NULL) { > > + error_propagate(errp, local_err); > > + return; > > + } > > +} > > + > > static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > { > > CPUState *cs = CPU(dev); > > @@ -919,6 +1046,55 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > } > > #endif > > > > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > > + > > + if (cpu->cfg.satp_mode.map == 0) { > > + /* > > + * If unset by both the user and the cpu, we fallback to the default > > + * satp mode. > > + */ > > + if (cpu->cfg.satp_mode.init == 0) { > > + set_satp_mode_default(cpu, rv32); > > + } else { > > + /* > > + * Find the lowest level that was disabled and then enable the > > + * first valid level below which can be found in > > + * valid_vm_1_10_32/64. > > + */ > > + const char *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > > + > > + for (int i = 0; i < 16; ++i) { > > 'init' will never have bit0 (mbare) set, so we can start at i=1, which is > good, because the condition below assumes it can index an array at i-1. Yes, that will be clearer indeed :) > > > + if (!(cpu->cfg.satp_mode.map & (1 << i)) && > > + (cpu->cfg.satp_mode.init & (1 << i)) && > > + valid_vm[i]) { > > + for (int j = i - 1; j >= 0; --j) { > > + if (valid_vm[j]) { > > + cpu->cfg.satp_mode.map |= (1 << j); > > + break; > > + } > > + } > > + break; > > + } > > + } > > + > > + /* > > + * The user actually init a satp mode but appears to be invalid > > + * (ex: "-cpu rv64,sv32=on,sv32=off"). Fallback to the default > > This example, where sv32 is used with rv64, won't be possible if we don't > give rv64 the sv32 property. > > > + * mode. > > + */ > > + if (cpu->cfg.satp_mode.map == 0) { > > + set_satp_mode_default(cpu, rv32); > > If the user does rv64,sv39=on,sv39=off, then I think we should be creating > an mbare machine, rather than using the default. > This will be possible when we remove this condition which was meant for the sv32 case above. > > + } > > + } > > + } > > Why isn't all this 'if (cpu->cfg.satp_mode.map == 0)' block above at the > top of riscv_cpu_satp_mode_finalize() instead of here? > Because the realize function seemed to do the properties processing and I thought the finalize one was meant to check the consistency of the configuration that resulted: I can change that if you don't agree. > > + > > + riscv_cpu_finalize_features(cpu, &local_err); > > + if (local_err != NULL) { > > + error_propagate(errp, local_err); > > + return; > > + } > > + > > + > > extra blank line Oops > > > riscv_cpu_register_gdb_regs_for_features(cs); > > > > qemu_init_vcpu(cs); > > @@ -927,6 +1103,49 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > mcc->parent_realize(dev, errp); > > } > > > > +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, > > + void *opaque, Error **errp) > > +{ > > + RISCVSATPMap *satp_map = opaque; > > + uint8_t satp = satp_mode_from_str(name); > > + bool value; > > + > > + value = (satp_map->map & (1 << satp)); > > + > > + visit_type_bool(v, name, &value, errp); > > +} > > + > > +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, > > + void *opaque, Error **errp) > > +{ > > + RISCVSATPMap *satp_map = opaque; > > + uint8_t satp = satp_mode_from_str(name); > > + bool value; > > + > > + if (!visit_type_bool(v, name, &value, errp)) { > > + return; > > + } > > + > > + satp_map->map = deposit32(satp_map->map, satp, 1, value); > > + satp_map->init |= 1 << satp; > > +} > > + > > +static void riscv_add_satp_mode_properties(Object *obj) > > +{ > > + RISCVCPU *cpu = RISCV_CPU(obj); > > As mentioned above, I think we want to do > > > + > #if defined(TARGET_RISCV32) > > + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > #elif defined(TARGET_RISCV64) > > + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > #endif > > +} > > + > > #ifndef CONFIG_USER_ONLY > > static void riscv_cpu_set_irq(void *opaque, int irq, int level) > > { > > @@ -1091,6 +1310,8 @@ static void register_cpu_props(Object *obj) > > for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > > qdev_property_add_static(dev, prop); > > } > > + > > + riscv_add_satp_mode_properties(obj); > > } > > > > static Property riscv_cpu_properties[] = { > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index f5609b62a2..0ffa1bcfd5 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -27,6 +27,7 @@ > > #include "qom/object.h" > > #include "qemu/int128.h" > > #include "cpu_bits.h" > > +#include "qapi/qapi-types-common.h" > > > > #define TCG_GUEST_DEFAULT_MO 0 > > > > @@ -413,6 +414,17 @@ struct RISCVCPUClass { > > ResettablePhases parent_phases; > > }; > > > > +/* > > + * map is a 16-bit bitmap: the most significant set bit in map is the maximum > > + * satp mode that is supported. > > + * > > + * init is a 16-bit bitmap used to make sure the user selected a correct > > + * configuration as per the specification. > > + */ > > +typedef struct { > > + uint16_t map, init; > > +} RISCVSATPMap; > > + > > struct RISCVCPUConfig { > > bool ext_i; > > bool ext_e; > > @@ -488,6 +500,8 @@ struct RISCVCPUConfig { > > bool debug; > > > > bool short_isa_string; > > + > > + RISCVSATPMap satp_mode; > > }; > > > > typedef struct RISCVCPUConfig RISCVCPUConfig; > > @@ -794,9 +808,14 @@ enum riscv_pmu_event_idx { > > /* CSR function table */ > > extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; > > > > +extern const char valid_vm_1_10_32[], valid_vm_1_10_64[]; > > + > > void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); > > void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); > > > > void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); > > > > +uint8_t satp_mode_max_from_map(uint32_t map); > > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); > > + > > #endif /* RISCV_CPU_H */ > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 0db2c233e5..6e27299761 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -1117,12 +1117,12 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; > > static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; > > static const target_ulong vsip_writable_mask = MIP_VSSIP; > > > > -static const char valid_vm_1_10_32[16] = { > > +const char valid_vm_1_10_32[16] = { > > [VM_1_10_MBARE] = 1, > > [VM_1_10_SV32] = 1 > > }; > > > > -static const char valid_vm_1_10_64[16] = { > > +const char valid_vm_1_10_64[16] = { > > [VM_1_10_MBARE] = 1, > > [VM_1_10_SV39] = 1, > > [VM_1_10_SV48] = 1, > > @@ -1211,10 +1211,17 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, > > > > static int validate_vm(CPURISCVState *env, target_ulong vm) > > { > > - if (riscv_cpu_mxl(env) == MXL_RV32) { > > - return valid_vm_1_10_32[vm & 0xf]; > > + uint8_t satp_mode_max; > > + RISCVCPU *cpu = RISCV_CPU(env_cpu(env)); > > + bool is_32_bit = riscv_cpu_mxl(env) == MXL_RV32; > > + > > + vm &= 0xf; > > + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > > + > > + if (is_32_bit) { > > + return valid_vm_1_10_32[vm] && (vm <= satp_mode_max); > > } else { > > - return valid_vm_1_10_64[vm & 0xf]; > > + return valid_vm_1_10_64[vm] && (vm <= satp_mode_max); > > } > > } > > > > -- > > 2.37.2 > > > I'll wait for Alistair feedback on how to handle the sv32 issue, and I'll be back with a new version. Again, thank you, your review is much appreciated. Alex > Thanks, > drew From MAILER-DAEMON Wed Jan 18 12:04:52 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIBro-0001Tm-HQ for mharc-qemu-riscv@gnu.org; Wed, 18 Jan 2023 12:04:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIBrW-0001Q4-Cs for qemu-riscv@nongnu.org; Wed, 18 Jan 2023 12:04:42 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIBrU-0004uO-11 for qemu-riscv@nongnu.org; Wed, 18 Jan 2023 12:04:34 -0500 Received: by mail-wm1-x32b.google.com with SMTP id c10-20020a05600c0a4a00b003db0636ff84so2082663wmq.0 for ; Wed, 18 Jan 2023 09:04:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; 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Wed, 18 Jan 2023 09:04:29 -0800 (PST) Received: from [192.168.30.216] ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id j10-20020a05600c074a00b003db0ee277b2sm2324070wmn.5.2023.01.18.09.04.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Jan 2023 09:04:29 -0800 (PST) Message-ID: <5f6c99eb-fca8-2270-fa4d-758e548b05b1@linaro.org> Date: Wed, 18 Jan 2023 18:04:12 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v2 2/4] bulk: Coding style fixes Content-Language: en-US To: Thomas Huth , qemu-devel@nongnu.org, Lucas Mateus Castro , Gan Qixin Cc: qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org, Richard Henderson , Markus Armbruster , =?UTF-8?Q?Daniel_P=2e_Berrang=c3=a9?= References: <20230111083909.42624-1-philmd@linaro.org> <20230111083909.42624-3-philmd@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.089, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jan 2023 17:04:43 -0000 On 18/1/23 17:09, Thomas Huth wrote: > On 11/01/2023 09.39, Philippe Mathieu-Daudé wrote: >> Fix the following checkpatch.pl violation on lines using the >> TARGET_FMT_plx definition to avoid: >> >>    WARNING: line over 80 characters > > It's just a warning... > >> @@ -420,8 +421,9 @@ static int get_segment_6xx_tlb(CPUPPCState *env, >> mmu_ctx_t *ctx, >>                   hwaddr curaddr; >>                   uint32_t a0, a1, a2, a3; >> -                qemu_log("Page table: " TARGET_FMT_plx " len " >> TARGET_FMT_plx >> -                         "\n", ppc_hash32_hpt_base(cpu), >> +                qemu_log("Page table: " TARGET_FMT_plx >> +                         " len " TARGET_FMT_plx "\n", >> +                         ppc_hash32_hpt_base(cpu), >>                            ppc_hash32_hpt_mask(cpu) + 0x80); >>                   for (curaddr = ppc_hash32_hpt_base(cpu); >>                        curaddr < (ppc_hash32_hpt_base(cpu) > > ... and in cases like this, I'd really prefer the original line. > > I think it would be better to just fix it if checkpatch.pl really throws > an ERROR instead of a WARNING. See this thread and its references ¯\_(ツ)_/¯ https://lore.kernel.org/qemu-devel/CAFEAcA-yMZjJW=AJm=XLbrub1D-8iX0OKE78V_TzQmfC2RdXyw@mail.gmail.com/ From MAILER-DAEMON Wed Jan 18 12:42:15 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pICRz-0004yW-5X for mharc-qemu-riscv@gnu.org; Wed, 18 Jan 2023 12:42:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pICRx-0004y2-UW for qemu-riscv@nongnu.org; Wed, 18 Jan 2023 12:42:14 -0500 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pICRO-00038X-VD for qemu-riscv@nongnu.org; Wed, 18 Jan 2023 12:41:43 -0500 Received: by mail-ej1-x632.google.com with SMTP id mg12so12731414ejc.5 for ; Wed, 18 Jan 2023 09:41:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=Z5QJE31641kROvra3WExSxS6lpGGaSkBajcAx4YcGvo=; b=Lf+9bDc2F+LQAg4RA5u/0SGsBzq6YcSlEKHWYkCLAyg0v5lA+wUG1htzXAv8w2cKyS 1WGPGL/2ra0yo6iOVWYPJ0XOFYU2OqRuWodLpd98X3/Mc+4ktXvt7dJzmG9V/YB0aram hOft4rtXkQY8S5MiMykwjl90Xlcx04o42Ya+cblhVi5obXq/qqwFMYPuTdiNxZ+a+NEz NUDVqEhx2Tk9EYsfXSLPxctVCGREfbv5TwS8UaNmxyYpoPCyzofc2+zdG7JxBvb3g33K +T8sQM98W6t9hwshi4llTNc1A1fyW0kMP1E6+1pmFinhQ7pLStBc6wUBGBIylufGuiHx bfRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=Z5QJE31641kROvra3WExSxS6lpGGaSkBajcAx4YcGvo=; b=kZGZEpDHqbKMda3ZLl2+ooMRIshnPQUwnvTBs9XuMNoOBTVOgs5FxmvAn9ZEW/KEzm jVbuRd7NybrAI3qTlOVdM55C3gJkpMFAVzuXpWJldGl9vK27CL2GpvNEKlLjYo9odjuU DbcuvNsSryLYoMAcTcCzAF88B0g74bFc8uHzzubLrNc3lSj5XhKdIFGGbvv3G4a4GxX5 hkeQtYM4AS6e7+qMKvpgBhbf+RsBIY3AkbzhgEGnb2QyJ/L/yRjYjIQ8KrS50NZry3Um lo+RmvgGvMG3Q1sE4JSbT5WX+rxgjkVKkDiEOkDXhzjdJd2WPmSzcr3Et7l1EjxekKhc RPew== X-Gm-Message-State: AFqh2krlCIm7Xyict0c14GEl2swYn1Tdn0E+wdUTj6r5cQTQ5elUJcob Jt4pj9Ml0o68reQDGtIT1wlxGw== X-Google-Smtp-Source: AMrXdXsB472RsXiXUJZ5kiB12NkmZPLo8OlPX2ACDrQrKlgz6c9Sed+OTUwinGe0cTraWhMcQBMTSw== X-Received: by 2002:a17:907:6745:b0:86c:f7ac:71f7 with SMTP id qm5-20020a170907674500b0086cf7ac71f7mr8567457ejc.8.1674063696332; Wed, 18 Jan 2023 09:41:36 -0800 (PST) Received: from localhost (cst2-173-16.cust.vodafone.cz. [31.30.173.16]) by smtp.gmail.com with ESMTPSA id kr12-20020a1709079a0c00b0084d44553af9sm12880091ejc.215.2023.01.18.09.41.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 09:41:35 -0800 (PST) Date: Wed, 18 Jan 2023 18:41:34 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Subject: Re: [PATCH v5 2/2] riscv: Allow user to set the satp mode Message-ID: <20230118174134.7zgola3w7tcpxayy@orel> References: <20230113103453.42776-1-alexghiti@rivosinc.com> <20230113103453.42776-3-alexghiti@rivosinc.com> <20230117163138.jze47hjeeuwu2k4j@orel> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=ajones@ventanamicro.com; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jan 2023 17:42:14 -0000 On Wed, Jan 18, 2023 at 05:29:43PM +0100, Alexandre Ghiti wrote: > Hey Andrew, > > On Tue, Jan 17, 2023 at 5:31 PM Andrew Jones wrote: > > > > On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote: > > > RISC-V specifies multiple sizes for addressable memory and Linux probes for > > > the machine's support at startup via the satp CSR register (done in > > > csr.c:validate_vm). > > > > > > As per the specification, sv64 must support sv57, which in turn must > > > support sv48...etc. So we can restrict machine support by simply setting the > > > "highest" supported mode and the bare mode is always supported. > > > > > > You can set the satp mode using the new properties "sv32", "sv39", "sv48", > > > "sv57" and "sv64" as follows: > > > -cpu rv64,sv57=on # Linux will boot using sv57 scheme > > > -cpu rv64,sv39=on # Linux will boot using sv39 scheme > > > -cpu rv64,sv57=off # Linux will boot using sv48 scheme > > > -cpu rv64 # Linux will boot using sv57 scheme by default > > > > > > We take the highest level set by the user: > > > -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme > > > > > > We make sure that invalid configurations are rejected: > > > -cpu rv64,sv32=on # Can't enable 32-bit satp mode in 64-bit > > > -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are > > > # enabled > > > > > > We accept "redundant" configurations: > > > -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme > > > -cpu rv64,sv32=on,sv32=off # Linux will boot using sv57 scheme (the default) > > > > > > In addition, we now correctly set the device-tree entry 'mmu-type' using > > > those new properties. > > > > > > Co-Developed-by: Ludovic Henry > > > Signed-off-by: Ludovic Henry > > > Signed-off-by: Alexandre Ghiti > > > --- > > > hw/riscv/virt.c | 19 ++-- > > > target/riscv/cpu.c | 221 +++++++++++++++++++++++++++++++++++++++++++++ > > > target/riscv/cpu.h | 19 ++++ > > > target/riscv/csr.c | 17 +++- > > > 4 files changed, 262 insertions(+), 14 deletions(-) > > > > > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > > > index 94ff2a1584..48d034a5f7 100644 > > > --- a/hw/riscv/virt.c > > > +++ b/hw/riscv/virt.c > > > @@ -228,7 +228,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > > > int cpu; > > > uint32_t cpu_phandle; > > > MachineState *mc = MACHINE(s); > > > - char *name, *cpu_name, *core_name, *intc_name; > > > + uint8_t satp_mode_max; > > > + char *name, *cpu_name, *core_name, *intc_name, *sv_name; > > > > > > for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { > > > cpu_phandle = (*phandle)++; > > > @@ -236,14 +237,14 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > > > cpu_name = g_strdup_printf("/cpus/cpu@%d", > > > s->soc[socket].hartid_base + cpu); > > > qemu_fdt_add_subnode(mc->fdt, cpu_name); > > > - if (riscv_feature(&s->soc[socket].harts[cpu].env, > > > - RISCV_FEATURE_MMU)) { > > > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > > > - (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); > > > > I just noticed that for the virt machine type, when the user doesn't > > provide a satp mode cpu property on the command line, and hence gets > > the default mode, they'll be silently changed from sv48 to sv57. That > > default change should be a separate patch which comes after this one. > > BTW, why sv57 and not sv48 or sv64? > > The device tree entry should match the max available satp mode even > though it makes little sense to have this entry in the first place: > the max satp mode is easily discoverable at runtime (the kernel does > that and does not care about the device tree entry). > > But yes, this fix was mentioned at the very end of the commit log, > which was weird anyway, so I'll move that to its own patch. Ah, I interpreted that part of the commit message as simply pointing out that the mmu-type is getting set per the user's input. Thanks for moving this change to another patch. ... > > > + > > > + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > > > + set_satp_mode(cpu, is_32_bit ? "sv32" : "sv57"); > > > + } else { > > > + set_satp_mode(cpu, "mbare"); > > > > nit: Could probably integrate set_satp_mode() into this function since > > this function is the only place it's used. > > At the moment yes, but this was a request from Frank to have a helper > set the default satp mode in the cpu init functions, which I did not > do here because I was unsure: @Frank Chang What should I use for > sifive_e and sifive_u? rv64 will use the default mode. The sifive stuff should probably be a separate patch. If that patch will be part of this series then the proactive refactoring makes sense as we can immediately see the users. ... > > Why isn't all this 'if (cpu->cfg.satp_mode.map == 0)' block above at the > > top of riscv_cpu_satp_mode_finalize() instead of here? > > > > Because the realize function seemed to do the properties processing > and I thought the finalize one was meant to check the consistency of > the configuration that resulted: I can change that if you don't agree. finalize should do all the processing and checking, basically everything not done in the property's set function. realize should call finalize_features, which then calls each feature's finalize. Take a look at arm's call chain, for example arm_cpu_realizefn arm_cpu_finalize_features arm_cpu_sve_finalize Thanks, drew From MAILER-DAEMON Wed Jan 18 17:42:19 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIH8N-0006B2-9I for mharc-qemu-riscv@gnu.org; Wed, 18 Jan 2023 17:42:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIH8L-0006AY-Fr; Wed, 18 Jan 2023 17:42:17 -0500 Received: from mail-vs1-xe2f.google.com ([2607:f8b0:4864:20::e2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIH8K-0002eb-2i; Wed, 18 Jan 2023 17:42:17 -0500 Received: by mail-vs1-xe2f.google.com with SMTP id 187so310743vsv.10; Wed, 18 Jan 2023 14:42:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=uMTygGtvu9QDzRsEHTqZjArkniSbvHqg2cfy0eZ9Ca8=; b=ixxvLDGSBBzGaELE2ixcl/f9IQ5d8g2x653GsysiBfxiUpfVxNmjENjXlm2JYyTWZQ ncEsnNRTn6bOyvayLHZ27nZLwefSYpc1xUF6HgdqBi6bJ69KkXEAYKLJMQ0JwdvKejwN h8B02nJ3BmIXSbIZYaPJFb8BpR/RTxew+vf5uUlXXo9cf1mpmt40n1at1h9ma9z9PzgR 3nkt+YCrpCa8PkhgN6CZIKcLxkUhIDq10yYlQvqZGVhFlX3POVRkUTgTgm/3xUkuAdEp Dc+S5JHDH5MRaYiWU1LaclIrBnXkod8+iox5cHjIXxOSsypnRv2qJHZ+A/gX5WCSlLC9 lXrQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=uMTygGtvu9QDzRsEHTqZjArkniSbvHqg2cfy0eZ9Ca8=; b=uc6OTHK3kAiiqXrxH0p6CkpT/KkPCoFSFEZ72USXNAfYBkIaYJDvO6/11SB+azt6uG DE7dDW0OMfgTvHw5LWqWaNB2kggvqyogG9UJMumtggl4qkcTfADV8NJ+mP4UNAZIEXqf oV2QIhDJ4H1Nx6AS0/DViOptbTVc7V2YX10PXlykq3s7d2iDQFpZ7NbeZTPx3QsgKny+ QS2KML9QsUEMdFIrm042G0/h4yL23teg20PfvdU1530UgarOQHVorfUMRlpo5Sf0NBtJ oBqZuHtLADl3APXMyvWj1z7EpSwnhxzpsGprpfuT4uxJQg5nL0JPeIruARVh0yJId/wc SFIg== X-Gm-Message-State: AFqh2kqwBAT6LDSK8iOJ5qNPHxh8FIcerxSW43N8pYhrn5DTKh2sC/6P lSqixzYtgOpheMqFqzr9yhsF4cDAcAl1fYSzTjY= X-Google-Smtp-Source: AMrXdXuwi7BC2xb2J0pKWi8dRY+00Gtj/YoYnqFmZDC3KAGzknAVcenfIB1TU/ZBfkgBHTpeqC4OwuQg0TZdN6hz5Pc= X-Received: by 2002:a67:e14a:0:b0:3d3:f10a:4f56 with SMTP id o10-20020a67e14a000000b003d3f10a4f56mr1183786vsl.10.1674081734376; Wed, 18 Jan 2023 14:42:14 -0800 (PST) MIME-Version: 1.0 References: <20230117230415.354239-1-richard.henderson@linaro.org> In-Reply-To: <20230117230415.354239-1-richard.henderson@linaro.org> From: Alistair Francis Date: Thu, 19 Jan 2023 08:41:48 +1000 Message-ID: Subject: Re: [PATCH] tcg/riscv: Use tcg_pcrel_diff in tcg_out_ldst To: Richard Henderson Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Alistair.Francis@wdc.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e2f; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jan 2023 22:42:17 -0000 On Wed, Jan 18, 2023 at 9:05 AM Richard Henderson wrote: > > We failed to update this with the w^x split, so misses the fact > that true pc-relative offsets are usually small. > > Signed-off-by: Richard Henderson Thanks! Applied to riscv-to-apply.next Alistair > --- > tcg/riscv/tcg-target.c.inc | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index fc0edd811f..01cb67ef7b 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -599,7 +599,7 @@ static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, > intptr_t imm12 = sextreg(offset, 0, 12); > > if (offset != imm12) { > - intptr_t diff = offset - (uintptr_t)s->code_ptr; > + intptr_t diff = tcg_pcrel_diff(s, (void *)offset); > > if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { > imm12 = sextreg(diff, 0, 12); > -- > 2.34.1 > > From MAILER-DAEMON Wed Jan 18 17:44:16 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIHAF-00078j-Uc for mharc-qemu-riscv@gnu.org; Wed, 18 Jan 2023 17:44:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIHAA-000781-Tt; Wed, 18 Jan 2023 17:44:11 -0500 Received: from mail-ua1-x92c.google.com ([2607:f8b0:4864:20::92c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIHA9-0002mf-08; Wed, 18 Jan 2023 17:44:10 -0500 Received: by mail-ua1-x92c.google.com with SMTP id j1so76310uan.1; Wed, 18 Jan 2023 14:44:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=JP9u+24Rk71TnWOoC1b+3gprI4qTPzwLIfUqOvEspHo=; b=GPTqCl5WDfuyi5Go/iW2kyuq2M6TAtI8Kg/I5Dqaobec2xlzSuigJhbcWTWou3JZ3T Mz25yTzrkfImQiRoQfPMhGqxamU0ZlOr5U/PaRDzrcp5rq3lv74R900nqHBjwwL5qtJN 0YmohTbz2k9L7SyiiGjOIOA+SsEzIdUatrCIPCOgwmdlyY5aRhd59hQ2HWIPtKDuk7uE jv4WaD98gA+ndKuPtvjOmjhCo5SEZYNojpsC498V56KDxAwv0OIlUrhHnBt+fPmS8/z6 f49m7dM3xRwJxmm6J3SwaCTtM7w8QR1e+7IaBF/v+tx+zBTt1l53wpRkvitCAMFuMamc 9xSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=JP9u+24Rk71TnWOoC1b+3gprI4qTPzwLIfUqOvEspHo=; b=NosetM5GOHxeGZb47ooBfEhE+/USA27QUTcbXg/fHqJUC5YaKkp/nZHkP1ZCpfVv65 x607MQFHT0PYZAz1QJXEdsTvFc75dsV9fyW3KwtxYe8u1xsHG6W69BFmcCWsiEnCNueW nqwhRv38KMtW2y8bVtB+La5XV34SfRugqyfT7gAx2KuizIzU7r6rpAYMzoUUlNdJTlSo 4EB/n0TO+MdeV4ulQ/ajINVKefDkfpjmiyBOxMy+MHafk6ZHff6A5Ei1M6CBFhwIHxy1 uQA/buui03TeQOhr5mTzwE+FGXFMFJ3RSZexoyoOiC9Acrcz4VXx4Sr7Zrds4XbF0e2g ywgw== X-Gm-Message-State: AFqh2kptf57Brlz/1+zeg+8WYu3W4VZMPencKrYSy4XUALCjjxIQv7Bg fnU7I1Srpr80RB2XkCWGJsOW3GzYi790gifrjaI= X-Google-Smtp-Source: AMrXdXvQgJnwyl4vv8ZxjEIBv/moGkEXZsgoDXC1tMYgz1ILY6MTTKUz3rjuWGHgcFHvH8cRDJmL5gVrBkJMwo1PSjw= X-Received: by 2002:a9f:31b2:0:b0:418:f948:259f with SMTP id v47-20020a9f31b2000000b00418f948259fmr969555uad.38.1674081847237; Wed, 18 Jan 2023 14:44:07 -0800 (PST) MIME-Version: 1.0 References: <20230116122948.757515-1-dbarboza@ventanamicro.com> <20230116122948.757515-2-dbarboza@ventanamicro.com> In-Reply-To: <20230116122948.757515-2-dbarboza@ventanamicro.com> From: Alistair Francis Date: Thu, 19 Jan 2023 08:43:41 +1000 Message-ID: Subject: Re: [PATCH v8 1/3] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Palmer Dabbelt , Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::92c; envelope-from=alistair23@gmail.com; helo=mail-ua1-x92c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jan 2023 22:44:12 -0000 On Mon, Jan 16, 2023 at 10:31 PM Daniel Henrique Barboza wrote: > > The microchip_icicle_kit, sifive_u, spike and virt boards are now doing > the same steps when '-kernel' is used: > > - execute load_kernel() > - load init_rd() > - write kernel_cmdline > > Let's fold everything inside riscv_load_kernel() to avoid code > repetition. To not change the behavior of boards that aren't calling > riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and > allow these boards to opt out from initrd loading. > > Cc: Palmer Dabbelt > Reviewed-by: Bin Meng > Reviewed-by: Alistair Francis > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/boot.c | 22 +++++++++++++++++++--- > hw/riscv/microchip_pfsoc.c | 12 ++---------- > hw/riscv/opentitan.c | 2 +- > hw/riscv/sifive_e.c | 3 ++- > hw/riscv/sifive_u.c | 12 ++---------- > hw/riscv/spike.c | 11 +---------- > hw/riscv/virt.c | 12 ++---------- > include/hw/riscv/boot.h | 1 + > 8 files changed, 30 insertions(+), 45 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 2594276223..4888d5c1e0 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -175,10 +175,12 @@ target_ulong riscv_load_firmware(const char *firmware_filename, > > target_ulong riscv_load_kernel(MachineState *machine, > target_ulong kernel_start_addr, > + bool load_initrd, > symbol_fn_t sym_cb) > { > const char *kernel_filename = machine->kernel_filename; > uint64_t kernel_load_base, kernel_entry; > + void *fdt = machine->fdt; > > g_assert(kernel_filename != NULL); > > @@ -192,21 +194,35 @@ target_ulong riscv_load_kernel(MachineState *machine, > if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, > NULL, &kernel_load_base, NULL, NULL, 0, > EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { > - return kernel_load_base; > + kernel_entry = kernel_load_base; > + goto out; > } > > if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, > NULL, NULL, NULL) > 0) { > - return kernel_entry; > + goto out; > } > > if (load_image_targphys_as(kernel_filename, kernel_start_addr, > current_machine->ram_size, NULL) > 0) { > - return kernel_start_addr; > + kernel_entry = kernel_start_addr; > + goto out; > } > > error_report("could not load kernel '%s'", kernel_filename); > exit(1); > + > +out: > + if (load_initrd && machine->initrd_filename) { > + riscv_load_initrd(machine, kernel_entry); This breaks 32-bit loading as kernel_entry might be sign extended with 1s Alistair > + } > + > + if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { > + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", > + machine->kernel_cmdline); > + } > + > + return kernel_entry; > } > > void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index 82ae5e7023..c45023a2b1 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -629,16 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) > kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, > firmware_end_addr); > > - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); > - > - if (machine->initrd_filename) { > - riscv_load_initrd(machine, kernel_entry); > - } > - > - if (machine->kernel_cmdline && *machine->kernel_cmdline) { > - qemu_fdt_setprop_string(machine->fdt, "/chosen", > - "bootargs", machine->kernel_cmdline); > - } > + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, > + true, NULL); > > /* Compute the fdt load address in dram */ > fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, > diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c > index 64d5d435b9..f6fd9725a5 100644 > --- a/hw/riscv/opentitan.c > +++ b/hw/riscv/opentitan.c > @@ -101,7 +101,7 @@ static void opentitan_board_init(MachineState *machine) > } > > if (machine->kernel_filename) { > - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); > + riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, false, NULL); > } > } > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > index 3e3f4b0088..6835d1c807 100644 > --- a/hw/riscv/sifive_e.c > +++ b/hw/riscv/sifive_e.c > @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machine) > memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); > > if (machine->kernel_filename) { > - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL); > + riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, > + false, NULL); > } > } > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 2fb6ee231f..ccad386920 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -598,16 +598,8 @@ static void sifive_u_machine_init(MachineState *machine) > kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, > firmware_end_addr); > > - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); > - > - if (machine->initrd_filename) { > - riscv_load_initrd(machine, kernel_entry); > - } > - > - if (machine->kernel_cmdline && *machine->kernel_cmdline) { > - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", > - machine->kernel_cmdline); > - } > + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, > + true, NULL); > } else { > /* > * If dynamic firmware is used, it doesn't know where is the next mode > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index badc11ec43..91bf194ec1 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -306,16 +306,7 @@ static void spike_board_init(MachineState *machine) > firmware_end_addr); > > kernel_entry = riscv_load_kernel(machine, kernel_start_addr, > - htif_symbol_callback); > - > - if (machine->initrd_filename) { > - riscv_load_initrd(machine, kernel_entry); > - } > - > - if (machine->kernel_cmdline && *machine->kernel_cmdline) { > - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", > - machine->kernel_cmdline); > - } > + true, htif_symbol_callback); > } else { > /* > * If dynamic firmware is used, it doesn't know where is the next mode > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index e6d4f06e8d..e374b58f89 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -1281,16 +1281,8 @@ static void virt_machine_done(Notifier *notifier, void *data) > kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], > firmware_end_addr); > > - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); > - > - if (machine->initrd_filename) { > - riscv_load_initrd(machine, kernel_entry); > - } > - > - if (machine->kernel_cmdline && *machine->kernel_cmdline) { > - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", > - machine->kernel_cmdline); > - } > + kernel_entry = riscv_load_kernel(machine, kernel_start_addr, > + true, NULL); > } else { > /* > * If dynamic firmware is used, it doesn't know where is the next mode > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h > index f94653a09b..c3de897371 100644 > --- a/include/hw/riscv/boot.h > +++ b/include/hw/riscv/boot.h > @@ -45,6 +45,7 @@ target_ulong riscv_load_firmware(const char *firmware_filename, > symbol_fn_t sym_cb); > target_ulong riscv_load_kernel(MachineState *machine, > target_ulong firmware_end_addr, > + bool load_initrd, > symbol_fn_t sym_cb); > void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); > uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); 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Wed, 18 Jan 2023 14:46:04 -0800 (PST) MIME-Version: 1.0 References: <20230116122948.757515-1-dbarboza@ventanamicro.com> <20230116122948.757515-4-dbarboza@ventanamicro.com> <61fd483d-5d3a-587b-5c98-4b81afe21d7d@ventanamicro.com> In-Reply-To: <61fd483d-5d3a-587b-5c98-4b81afe21d7d@ventanamicro.com> From: Alistair Francis Date: Thu, 19 Jan 2023 08:45:38 +1000 Message-ID: Subject: Re: [PATCH v8 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym() To: Daniel Henrique Barboza Cc: =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::92c; envelope-from=alistair23@gmail.com; helo=mail-ua1-x92c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jan 2023 22:46:17 -0000 On Mon, Jan 16, 2023 at 10:46 PM Daniel Henrique Barboza wrote: > > > > On 1/16/23 09:37, Philippe Mathieu-Daud=C3=A9 wrote: > > On 16/1/23 13:29, Daniel Henrique Barboza wrote: > >> Recent hw/risc/boot.c changes caused a regression in an use case with > >> the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel' > >> stopped working. The reason seems to be that Xvisor is using 64 bit to > >> encode the 32 bit addresses from the guest, and load_elf_ram_sym() is > >> sign-extending the result with '1's [1]. > >> > >> Use a translate_fn() callback to be called by load_elf_ram_sym() and > >> return only the 32 bits address if we're running a 32 bit CPU. > >> > >> [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.htm= l > >> > >> Suggested-by: Philippe Mathieu-Daud=C3=A9 > >> Suggested-by: Bin Meng > >> Signed-off-by: Daniel Henrique Barboza > >> --- > >> hw/riscv/boot.c | 20 +++++++++++++++++++- > >> hw/riscv/microchip_pfsoc.c | 4 ++-- > >> hw/riscv/opentitan.c | 3 ++- > >> hw/riscv/sifive_e.c | 3 ++- > >> hw/riscv/sifive_u.c | 4 ++-- > >> hw/riscv/spike.c | 2 +- > >> hw/riscv/virt.c | 4 ++-- > >> include/hw/riscv/boot.h | 1 + > >> target/riscv/cpu_bits.h | 1 + > >> 9 files changed, 32 insertions(+), 10 deletions(-) > >> > >> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > >> index e868fb6ade..0fd39df7f3 100644 > >> --- a/hw/riscv/boot.c > >> +++ b/hw/riscv/boot.c > >> @@ -213,7 +213,24 @@ static void riscv_load_initrd(MachineState *machi= ne, uint64_t kernel_entry) > >> } > >> } > >> +static uint64_t translate_kernel_address(void *opaque, uint64_t add= r) > >> +{ > >> + RISCVHartArrayState *harts =3D opaque; > >> + > >> + /* > >> + * For 32 bit CPUs, kernel_load_base is sign-extended (i.e. > >> + * it can be padded with '1's) if the hypervisor is using > >> + * 64 bit addresses with 32 bit guests. > >> + */ > >> + if (riscv_is_32bit(harts)) { > > > > Maybe move the comment within the if() and add " so remove the sign > > extension by truncating to 32-bit". > > > >> + return extract64(addr, 0, RV32_KERNEL_ADDR_LEN); > > > > For 32-bit maybe a definition is not necessary, I asked before > > you used 24-bit in the previous version. As the maintainer prefer :) > > That was unintentional. I missed a 'f' in that 0x0fffffff, which I notice= d only > now when doing this version. It's curious because Alistair mentioned that > the patch apparently solved the bug .... I never tested it, I'm not sure if this solves the problem or not. This patch needs to be merged *before* the initrd patch (patch 1 of this series) to avoid breaking users. > > I don't mind creating a macro for the 32 bit value. If we decide it's unn= eeded > I can remove it and just put a '32' there. I'll also make the comment cha= nge > you mentioned above. I think 32 if fine, I don't think we need a macro Alistair > > > Thanks, > > > Daniel > > > > >> + } > >> + > >> + return addr; > >> +} > > > >> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > >> index 8b0d7e20ea..8fcaeae342 100644 > >> --- a/target/riscv/cpu_bits.h > >> +++ b/target/riscv/cpu_bits.h > >> @@ -751,6 +751,7 @@ typedef enum RISCVException { > >> #define MENVCFG_STCE (1ULL << 63) > >> /* For RV32 */ > >> +#define RV32_KERNEL_ADDR_LEN 32 > >> #define MENVCFGH_PBMTE BIT(30) > >> #define MENVCFGH_STCE BIT(31) > > > > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > > > > > > From MAILER-DAEMON Wed Jan 18 17:52:41 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIHIJ-0000mX-4O for mharc-qemu-riscv@gnu.org; Wed, 18 Jan 2023 17:52:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIHIA-0000ly-TW; Wed, 18 Jan 2023 17:52:27 -0500 Received: from mail-vs1-xe2e.google.com ([2607:f8b0:4864:20::e2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIHI8-00042O-Qv; Wed, 18 Jan 2023 17:52:26 -0500 Received: by mail-vs1-xe2e.google.com with SMTP id 3so347528vsq.7; Wed, 18 Jan 2023 14:52:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=6NXKZzdVvEDImZrj5tf8O3Vb7baVleyp6hXqcDwEm1o=; b=SQwheuOVcIDwPreRQ/k58H/TtKgUxFB0gqkfb5TovXhN/ZLL1yPA3zTHlJBxQ8lN1s zosWSuPCUqtIc6EGIJeGHLxVPPnLA+LNP8fovaUEucDjR2fDzxTlj4usgUldrwXWfOPJ 8kCL/zusQhM4gZsAbW3PPaLHjaDl+Uk8eEqsdFLRuYP3wWhdI31Awp6PfZAt2nUucv4x 3BaulrKZLbdjLYn4VKjavXuXdwqQlyAyseuKVF9PkJZSctTo8tHe9Bn5WZFxlZPk2ze0 6+WvsjSaFKZtXGERzVrtvFthU/r/UnU0wqYrfzwGjVEx3hY/HKCeHEAhPh1jpdPt93tj nWew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=6NXKZzdVvEDImZrj5tf8O3Vb7baVleyp6hXqcDwEm1o=; b=7+E75+Y+dinWStM0SCuvIC/+0SPEVDJr6310uqbKwe4gZwkevXVAm3xiZ572FPuJvG KjiBZzy4D7ql8jilkqcTNB7e2UWVeOtqATTDAo1K/tjRvPIzDkiPXQclKUtXoryL4psw 7bY+5V/s3M1q4LA8uDNec0ZGGxcz8Nt63naCTJyQ2n+/6YpYxyjxDQVUuaXVz7/UsN7L AIzpDniAS48GQFQTemK30vxEIy4DaBT3mQpP2UYTEaCCMgwck2xYH7C7C6RMDySatLC6 XWTe32j5JRNUSm4fuMeDVHJchcUMJj0l3pPVtvE8Y43TVoNFQQc1NzR1jG8zHED7YFjm vYcQ== X-Gm-Message-State: AFqh2krahJACRi7dUQTBnvy2GSn3rblH1ATQHqXY6fhgbxCJnTAFw3Ek djWVG2RUO1YLPT4q3PWBoxht095xg8VTzXW3BDk= X-Google-Smtp-Source: AMrXdXvq3SKaCjUNdfIk6Qw1jsC6FW2r98Mf1Oox5Vy1EEflfri+ql46YdjkTF6VDGDCHWe4M1S5gUGsr1jW2YxWGFE= X-Received: by 2002:a67:eb10:0:b0:3c9:8cc2:dd04 with SMTP id a16-20020a67eb10000000b003c98cc2dd04mr1292936vso.73.1674082342510; Wed, 18 Jan 2023 14:52:22 -0800 (PST) MIME-Version: 1.0 References: <20230115160657.3169274-1-richard.henderson@linaro.org> <20230115160657.3169274-2-richard.henderson@linaro.org> In-Reply-To: <20230115160657.3169274-2-richard.henderson@linaro.org> From: Alistair Francis Date: Thu, 19 Jan 2023 08:51:56 +1000 Message-ID: Subject: Re: [PATCH 1/2] target/arm: Introduce helper_set_rounding_mode_chkfrm To: Richard Henderson Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bin.meng@windriver.com, abdulras@google.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e2e; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jan 2023 22:52:29 -0000 On Mon, Jan 16, 2023 at 2:08 AM Richard Henderson wrote: > > The new helper always validates the contents of FRM, even > if the new rounding mode is not DYN. This is required by > the vector unit. > > Track whether we've validated FRM separately from whether > we've updated fp_status with a given rounding mode, so that > we can elide calls correctly. > > This partially reverts d6c4d3f2a69 which attempted the to do > the same thing, but with two calls to gen_set_rm(), which is > both inefficient and tickles an assertion in decode_save_opc. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1441 > Signed-off-by: Richard Henderson Acked-by: Alistair Francis Alistair > --- > target/riscv/helper.h | 1 + > target/riscv/fpu_helper.c | 37 +++++++++++++++++++++++++ > target/riscv/translate.c | 19 +++++++++++++ > target/riscv/insn_trans/trans_rvv.c.inc | 24 +++------------- > 4 files changed, 61 insertions(+), 20 deletions(-) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index 227c7122ef..9792ab5086 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -3,6 +3,7 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32) > > /* Floating Point - rounding mode */ > DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) > +DEF_HELPER_FLAGS_2(set_rounding_mode_chkfrm, TCG_CALL_NO_WG, void, env, i32) > DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env) > > /* Floating Point - fused */ > diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c > index 5699c9517f..96817df8ef 100644 > --- a/target/riscv/fpu_helper.c > +++ b/target/riscv/fpu_helper.c > @@ -81,6 +81,43 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) > set_float_rounding_mode(softrm, &env->fp_status); > } > > +void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm) > +{ > + int softrm; > + > + /* Always validate frm, even if rm != DYN. */ > + if (unlikely(env->frm >= 5)) { > + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); > + } > + if (rm == RISCV_FRM_DYN) { > + rm = env->frm; > + } > + switch (rm) { > + case RISCV_FRM_RNE: > + softrm = float_round_nearest_even; > + break; > + case RISCV_FRM_RTZ: > + softrm = float_round_to_zero; > + break; > + case RISCV_FRM_RDN: > + softrm = float_round_down; > + break; > + case RISCV_FRM_RUP: > + softrm = float_round_up; > + break; > + case RISCV_FRM_RMM: > + softrm = float_round_ties_away; > + break; > + case RISCV_FRM_ROD: > + softrm = float_round_to_odd; > + break; > + default: > + g_assert_not_reached(); > + } > + > + set_float_rounding_mode(softrm, &env->fp_status); > +} > + > void helper_set_rod_rounding_mode(CPURISCVState *env) > { > set_float_rounding_mode(float_round_to_odd, &env->fp_status); > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index df38db7553..493c3815e1 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -114,6 +114,8 @@ typedef struct DisasContext { > bool pm_base_enabled; > /* Use icount trigger for native debug */ > bool itrigger; > + /* FRM is known to contain a valid value. */ > + bool frm_valid; > /* TCG of the current insn_start */ > TCGOp *insn_start; > } DisasContext; > @@ -674,12 +676,29 @@ static void gen_set_rm(DisasContext *ctx, int rm) > gen_helper_set_rod_rounding_mode(cpu_env); > return; > } > + if (rm == RISCV_FRM_DYN) { > + /* The helper will return only if frm valid. */ > + ctx->frm_valid = true; > + } > > /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ > decode_save_opc(ctx); > gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); > } > > +static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) > +{ > + if (ctx->frm == rm && ctx->frm_valid) { > + return; > + } > + ctx->frm = rm; > + ctx->frm_valid = true; > + > + /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ > + decode_save_opc(ctx); > + gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm)); > +} > + > static int ex_plus_1(DisasContext *ctx, int nf) > { > return nf + 1; > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index d455acedbf..bbb5c3a7b5 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -2679,13 +2679,9 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, > int rm) > { > if (checkfn(s, a)) { > - if (rm != RISCV_FRM_DYN) { > - gen_set_rm(s, RISCV_FRM_DYN); > - } > - > uint32_t data = 0; > TCGLabel *over = gen_new_label(); > - gen_set_rm(s, rm); > + gen_set_rm_chkfrm(s, rm); > tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); > tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); > > @@ -2882,17 +2878,13 @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a) > static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ > { \ > if (CHECK(s, a)) { \ > - if (FRM != RISCV_FRM_DYN) { \ > - gen_set_rm(s, RISCV_FRM_DYN); \ > - } \ > - \ > uint32_t data = 0; \ > static gen_helper_gvec_3_ptr * const fns[2] = { \ > gen_helper_##HELPER##_h, \ > gen_helper_##HELPER##_w, \ > }; \ > TCGLabel *over = gen_new_label(); \ > - gen_set_rm(s, FRM); \ > + gen_set_rm_chkfrm(s, FRM); \ > tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ > tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ > \ > @@ -3005,17 +2997,13 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) > static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ > { \ > if (CHECK(s, a)) { \ > - if (FRM != RISCV_FRM_DYN) { \ > - gen_set_rm(s, RISCV_FRM_DYN); \ > - } \ > - \ > uint32_t data = 0; \ > static gen_helper_gvec_3_ptr * const fns[2] = { \ > gen_helper_##HELPER##_h, \ > gen_helper_##HELPER##_w, \ > }; \ > TCGLabel *over = gen_new_label(); \ > - gen_set_rm(s, FRM); \ > + gen_set_rm_chkfrm(s, FRM); \ > tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ > tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ > \ > @@ -3060,10 +3048,6 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a) > static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ > { \ > if (opxfv_narrow_check(s, a)) { \ > - if (FRM != RISCV_FRM_DYN) { \ > - gen_set_rm(s, RISCV_FRM_DYN); \ > - } \ > - \ > uint32_t data = 0; \ > static gen_helper_gvec_3_ptr * const fns[3] = { \ > gen_helper_##HELPER##_b, \ > @@ -3071,7 +3055,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ > gen_helper_##HELPER##_w, \ > }; \ > TCGLabel *over = gen_new_label(); \ > - gen_set_rm(s, FRM); \ > + gen_set_rm_chkfrm(s, FRM); \ > tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ > tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ > \ > -- > 2.34.1 > > From MAILER-DAEMON Wed Jan 18 17:53:42 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIHJN-0001aE-Us for mharc-qemu-riscv@gnu.org; Wed, 18 Jan 2023 17:53:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIHJG-0001R3-EU; Wed, 18 Jan 2023 17:53:35 -0500 Received: from mail-vk1-xa2e.google.com ([2607:f8b0:4864:20::a2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIHJD-00048s-NO; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::a2e; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jan 2023 22:53:40 -0000 On Mon, Jan 16, 2023 at 2:08 AM Richard Henderson wrote: > > The only setting of RISCV_FRM_ROD is from the vector unit, > and now handled by helper_set_rounding_mode_chkfrm. > This helper is now unused. > > Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/helper.h | 1 - > target/riscv/fpu_helper.c | 5 ----- > target/riscv/translate.c | 4 ---- > 3 files changed, 10 deletions(-) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index 9792ab5086..58a30f03d6 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -4,7 +4,6 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32) > /* Floating Point - rounding mode */ > DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) > DEF_HELPER_FLAGS_2(set_rounding_mode_chkfrm, TCG_CALL_NO_WG, void, env, i32) > -DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env) > > /* Floating Point - fused */ > DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) > diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c > index 96817df8ef..449d236df6 100644 > --- a/target/riscv/fpu_helper.c > +++ b/target/riscv/fpu_helper.c > @@ -118,11 +118,6 @@ void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm) > set_float_rounding_mode(softrm, &env->fp_status); > } > > -void helper_set_rod_rounding_mode(CPURISCVState *env) > -{ > - set_float_rounding_mode(float_round_to_odd, &env->fp_status); > -} > - > static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2, > uint64_t rs3, int flags) > { > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 493c3815e1..01cc30a365 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -672,10 +672,6 @@ static void gen_set_rm(DisasContext *ctx, int rm) > } > ctx->frm = rm; > > - if (rm == RISCV_FRM_ROD) { > - gen_helper_set_rod_rounding_mode(cpu_env); > - return; > - } > if (rm == RISCV_FRM_DYN) { > /* The helper will return only if frm valid. */ > ctx->frm_valid = true; > -- > 2.34.1 > > From MAILER-DAEMON Wed Jan 18 17:56:48 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIHMO-0002gN-J8 for mharc-qemu-riscv@gnu.org; Wed, 18 Jan 2023 17:56:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIHMI-0002fl-8Y; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e2a; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2a.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jan 2023 22:56:46 -0000 On Tue, Jan 17, 2023 at 11:28 PM Daniel Henrique Barboza wrote: > > Commit 1c20d3ff6004 ("hw/riscv: virt: Add a machine done notifier") > moved the initialization of fw_cfg to the virt_machine_done() callback. > > Problem is that the validation of fw_cfg by devices such as ramfb is > done before the machine done notifier is called. Moving create_fw_cfg() > to machine_done() results in QEMU failing to boot when using a ramfb > device: > > ./qemu-system-riscv64 -machine virt -device ramfb -serial stdio > qemu-system-riscv64: -device ramfb: ramfb device requires fw_cfg with DMA > > The fix is simple: move create_fw_cfg() config back to > virt_machine_init(). This happens to be the same way the ARM 'virt' > machine deals with fw_cfg (see machvirt_init() and virt_machine_done() > in hw/arm/virt.c), so we're keeping consistency with how other machines > handle this device. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1343 > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Thanks for the fix! Alistair > --- > hw/riscv/virt.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index e6d4f06e8d..4a11b4b010 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -1254,13 +1254,6 @@ static void virt_machine_done(Notifier *notifier, void *data) > firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, > start_addr, NULL); > > - /* > - * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device > - * tree cannot be altered and we get FDT_ERR_NOSPACE. > - */ > - s->fw_cfg = create_fw_cfg(machine); > - rom_set_fw(s->fw_cfg); > - > if (drive_get(IF_PFLASH, 0, 1)) { > /* > * S-mode FW like EDK2 will be kept in second plash (unit 1). > @@ -1468,6 +1461,13 @@ static void virt_machine_init(MachineState *machine) > memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, > mask_rom); > > + /* > + * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the > + * device tree cannot be altered and we get FDT_ERR_NOSPACE. > + */ > + s->fw_cfg = create_fw_cfg(machine); > + rom_set_fw(s->fw_cfg); > + > /* SiFive Test MMIO device */ > sifive_test_create(memmap[VIRT_TEST].base); > > -- > 2.39.0 > > From MAILER-DAEMON Wed Jan 18 18:34:51 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIHxC-00040A-MF for mharc-qemu-riscv@gnu.org; Wed, 18 Jan 2023 18:34:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIHxB-0003zi-6g for qemu-riscv@nongnu.org; Wed, 18 Jan 2023 18:34:49 -0500 Received: from mail-oa1-x41.google.com ([2001:4860:4864:20::41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIHx9-0001tQ-As for qemu-riscv@nongnu.org; Wed, 18 Jan 2023 18:34:48 -0500 Received: by mail-oa1-x41.google.com with SMTP id 586e51a60fabf-15ebfdf69adso836568fac.0 for ; Wed, 18 Jan 2023 15:34:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=wgNU1Xh+K8IsXuabeBLqgeZkgdUbC7XlpmEoFtDGWn4=; b=RI7hqWwZDegu/nz0LPNfCXKJ9tOvil5rOHKAAgSpGl35OKNIbdzUgHw7EFlRR/qGlc 8yoO1MT0e7SqWoiokCA1tr3I6BvMtz9IJS4xK6k9GcYsvTbbW5y4ed1d/5CbTMK7zdt8 KvYB+2EA2h+7wOtXqh8/E8IYx1EtdcIaRQqvZwCh/I3cNjbxn4evtLCSLuUMNYQo87kM 045pqmH6w4rI0nFCzZKiMAGyyMnp/V41Ajow/pXAGIxBH1jQc0QLTPkp/rORYM3tQKeC y81W8hgWi67Kmw/8qMaemsXZ46RfiFLruxY3UcVKFaXQevwqL4hIFmkrY1lXlvrOtLms ADhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=wgNU1Xh+K8IsXuabeBLqgeZkgdUbC7XlpmEoFtDGWn4=; b=OCHJxqTLt6hoEljh+AvhglJeo/smSV6lRmduh3YMVYV67pLHvPOGfum9s9570Mutmg t7nsArTXfJj4OwBu3m6D8JJ84+WyJuvvCyT8FVIcODdgPjjFzo5MdYvv0qsOEQXx8jhC 91vYZxypOM0XgmVk8GYkoTTXb5uczDhq7fApby/5OSkPRunGq2GucLLdxJEXsZs7sksA 3+f8UCLT7yC4wfeUg8dtMMX4m2Gwz7f8eYutd46Vp0N2grysmHkIGSNp8TSfpJ1eoojh KjcpykFA+sE893Z/94UJE98JKrWCOZkFnp0iK5DG4QZvyjjkbrZVH3Q0xq24TaNDVhC1 NicQ== X-Gm-Message-State: AFqh2kraPGizyhiEzfoGGLkcm8OhDmHIqsaQ2MJ8fRYqgnKgW8dFSbgx yPI7ibUUu9aUIWiZTxqsq6CeaA== X-Google-Smtp-Source: AMrXdXunysWxJFJD6+40UImxvaXnGtVNYgV3mPUvYU6+sqLsvncgY2idzqLO+oSeUmlsgSuC420Ujg== X-Received: by 2002:a05:6870:289a:b0:15e:9b5b:e2c9 with SMTP id gy26-20020a056870289a00b0015e9b5be2c9mr5229234oab.3.1674084885661; Wed, 18 Jan 2023 15:34:45 -0800 (PST) Received: from [192.168.68.107] ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id em33-20020a0568705ba100b0014fd7e7c3fesm18998356oab.27.2023.01.18.15.34.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Jan 2023 15:34:45 -0800 (PST) Message-ID: <99e76807-83db-e7f8-4c44-cd9c1f15441a@ventanamicro.com> Date: Wed, 18 Jan 2023 20:34:41 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH v8 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym() To: Alistair Francis Cc: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, Bin Meng References: <20230116122948.757515-1-dbarboza@ventanamicro.com> <20230116122948.757515-4-dbarboza@ventanamicro.com> <61fd483d-5d3a-587b-5c98-4b81afe21d7d@ventanamicro.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::41; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x41.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.089, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jan 2023 23:34:49 -0000 On 1/18/23 19:45, Alistair Francis wrote: > On Mon, Jan 16, 2023 at 10:46 PM Daniel Henrique Barboza > wrote: >> >> >> On 1/16/23 09:37, Philippe Mathieu-Daudé wrote: >>> On 16/1/23 13:29, Daniel Henrique Barboza wrote: >>>> Recent hw/risc/boot.c changes caused a regression in an use case with >>>> the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel' >>>> stopped working. The reason seems to be that Xvisor is using 64 bit to >>>> encode the 32 bit addresses from the guest, and load_elf_ram_sym() is >>>> sign-extending the result with '1's [1]. >>>> >>>> Use a translate_fn() callback to be called by load_elf_ram_sym() and >>>> return only the 32 bits address if we're running a 32 bit CPU. >>>> >>>> [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html >>>> >>>> Suggested-by: Philippe Mathieu-Daudé >>>> Suggested-by: Bin Meng >>>> Signed-off-by: Daniel Henrique Barboza >>>> --- >>>> hw/riscv/boot.c | 20 +++++++++++++++++++- >>>> hw/riscv/microchip_pfsoc.c | 4 ++-- >>>> hw/riscv/opentitan.c | 3 ++- >>>> hw/riscv/sifive_e.c | 3 ++- >>>> hw/riscv/sifive_u.c | 4 ++-- >>>> hw/riscv/spike.c | 2 +- >>>> hw/riscv/virt.c | 4 ++-- >>>> include/hw/riscv/boot.h | 1 + >>>> target/riscv/cpu_bits.h | 1 + >>>> 9 files changed, 32 insertions(+), 10 deletions(-) >>>> >>>> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c >>>> index e868fb6ade..0fd39df7f3 100644 >>>> --- a/hw/riscv/boot.c >>>> +++ b/hw/riscv/boot.c >>>> @@ -213,7 +213,24 @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) >>>> } >>>> } >>>> +static uint64_t translate_kernel_address(void *opaque, uint64_t addr) >>>> +{ >>>> + RISCVHartArrayState *harts = opaque; >>>> + >>>> + /* >>>> + * For 32 bit CPUs, kernel_load_base is sign-extended (i.e. >>>> + * it can be padded with '1's) if the hypervisor is using >>>> + * 64 bit addresses with 32 bit guests. >>>> + */ >>>> + if (riscv_is_32bit(harts)) { >>> Maybe move the comment within the if() and add " so remove the sign >>> extension by truncating to 32-bit". >>> >>>> + return extract64(addr, 0, RV32_KERNEL_ADDR_LEN); >>> For 32-bit maybe a definition is not necessary, I asked before >>> you used 24-bit in the previous version. As the maintainer prefer :) >> That was unintentional. I missed a 'f' in that 0x0fffffff, which I noticed only >> now when doing this version. It's curious because Alistair mentioned that >> the patch apparently solved the bug .... > I never tested it, I'm not sure if this solves the problem or not. > > This patch needs to be merged *before* the initrd patch (patch 1 of > this series) to avoid breaking users. Makes sense. I'll change it in v9. Daniel >> I don't mind creating a macro for the 32 bit value. If we decide it's unneeded >> I can remove it and just put a '32' there. I'll also make the comment change >> you mentioned above. > I think 32 if fine, I don't think we need a macro > > Alistair > >> >> Thanks, >> >> >> Daniel >> >>>> + } >>>> + >>>> + return addr; >>>> +} >>>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h >>>> index 8b0d7e20ea..8fcaeae342 100644 >>>> --- a/target/riscv/cpu_bits.h >>>> +++ b/target/riscv/cpu_bits.h >>>> @@ -751,6 +751,7 @@ typedef enum RISCVException { >>>> #define MENVCFG_STCE (1ULL << 63) >>>> /* For RV32 */ >>>> +#define RV32_KERNEL_ADDR_LEN 32 >>>> #define MENVCFGH_PBMTE BIT(30) >>>> #define MENVCFGH_STCE BIT(31) >>> Reviewed-by: Philippe Mathieu-Daudé >>> >>> >> From MAILER-DAEMON Wed Jan 18 18:49:22 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIIBF-0007EJ-Sm for mharc-qemu-riscv@gnu.org; Wed, 18 Jan 2023 18:49:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIIBD-0007Dt-Ak; Wed, 18 Jan 2023 18:49:19 -0500 Received: from mail-vk1-xa35.google.com ([2607:f8b0:4864:20::a35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIIBB-0003x6-8a; Wed, 18 Jan 2023 18:49:19 -0500 Received: by mail-vk1-xa35.google.com with SMTP id c21so142501vkn.10; Wed, 18 Jan 2023 15:49:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=vna0pPr5HnnTDVV9ZDjbi0QYm8u2GZiyqeS0n87r68Y=; b=guZBighPl3xqX1uH697deqO1idGLhQ6ZTziviRAvDjoa5TRt8B+ZIBruKpHiV+sjBh 2qAGxBbuyCTKpqSYClB92Fim7Buoeu/5T5mbqMHEk5X3MmhCJLcWsJeqLRvbnUwgQzBo sYfe+fRkk0p48+obYAtY5qLdad06pJYZA7f1aN8jYCsi/N7bfwxq/J2uG0oyqQXXDR6/ E8uE2gGdVo0qRporY623CszNHsxVtBMG/zT7pc3HCIk8EpjI/ahX2rq2BSKZ/LZxZW+e SWHZ0esDuYliM93pnkQIjM6Krccu53lwsQtI+R/Fv01ydwcdNCmFPQpnlU38azE10lgi NwNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=vna0pPr5HnnTDVV9ZDjbi0QYm8u2GZiyqeS0n87r68Y=; b=PZ81Ovaf3sBNVS5JqN0QaT9md4ahdlx+dR6dbfMzTuJhVyKifI4PHvHN7GFIasRHUY V5Qn8OgpsEegXvl0mUdvKrcSD0XKwuGnNEZeGYNLiIidG9siuruD4KfAlzolanS/C2Tj 5gP9j6haGQA2JZDxBNZjOQycE9guXdE0QGuxC4MWxlglTYYUr5Q98nJFzfg7l/84dulV rsQcG4T3SnAtlXgi0NBjETWyHic2ltFP16wE0DHXKTVuYAsx66BjCPgfK5IhtdvlFfYX ccMHR+mj5bh7A/uG1OoAhB/nYNsFlwgHtU/9RpJGt2U5wrgCzdXA9JjgFbarLQgzyW6r CQUg== X-Gm-Message-State: AFqh2koVUv9CNK6lqIHrvOr1/9qf2tKAc+aRZIyUp6MG8AFYzQq+qLIC /aVXJ6samxJilsdvEqe3bnwUhJA6mHOTIXwq9p8= X-Google-Smtp-Source: AMrXdXvriwthG4ECLLHLbxfXjvnhnUCBQW9CM/40Ol0YHGgpeVd+1iCtz8Kyw70DkqnZV4tKU7HoZHPzZQOUdvgQNPE= X-Received: by 2002:a1f:a7ca:0:b0:3d5:86ff:6638 with SMTP id q193-20020a1fa7ca000000b003d586ff6638mr1247336vke.30.1674085755524; Wed, 18 Jan 2023 15:49:15 -0800 (PST) MIME-Version: 1.0 References: <20230115160657.3169274-1-richard.henderson@linaro.org> <20230115160657.3169274-2-richard.henderson@linaro.org> In-Reply-To: From: Alistair Francis Date: Thu, 19 Jan 2023 09:49:00 +1000 Message-ID: Subject: Re: [PATCH 1/2] target/arm: Introduce helper_set_rounding_mode_chkfrm To: Daniel Henrique Barboza Cc: Richard Henderson , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, bin.meng@windriver.com, abdulras@google.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::a35; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa35.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jan 2023 23:49:19 -0000 On Wed, Jan 18, 2023 at 8:02 PM Daniel Henrique Barboza wrote: > > s/arm/riscv in subject/commit title ^ Fixed when committing Thanks! Applied to riscv-to-apply.next Alistair > > On 1/15/23 13:06, Richard Henderson wrote: > > The new helper always validates the contents of FRM, even > if the new rounding mode is not DYN. This is required by > the vector unit. > > Track whether we've validated FRM separately from whether > we've updated fp_status with a given rounding mode, so that > we can elide calls correctly. > > This partially reverts d6c4d3f2a69 which attempted the to do > the same thing, but with two calls to gen_set_rm(), which is > both inefficient and tickles an assertion in decode_save_opc. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1441 > Signed-off-by: Richard Henderson > --- > > > Reviewed-by: Daniel Henrique Barboza > > target/riscv/helper.h | 1 + > target/riscv/fpu_helper.c | 37 +++++++++++++++++++++++++ > target/riscv/translate.c | 19 +++++++++++++ > target/riscv/insn_trans/trans_rvv.c.inc | 24 +++------------- > 4 files changed, 61 insertions(+), 20 deletions(-) > > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index 227c7122ef..9792ab5086 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -3,6 +3,7 @@ DEF_HELPER_2(raise_exception, noreturn, env, i32) > > /* Floating Point - rounding mode */ > DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) > +DEF_HELPER_FLAGS_2(set_rounding_mode_chkfrm, TCG_CALL_NO_WG, void, env, i32) > DEF_HELPER_FLAGS_1(set_rod_rounding_mode, TCG_CALL_NO_WG, void, env) > > /* Floating Point - fused */ > diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c > index 5699c9517f..96817df8ef 100644 > --- a/target/riscv/fpu_helper.c > +++ b/target/riscv/fpu_helper.c > @@ -81,6 +81,43 @@ void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) > set_float_rounding_mode(softrm, &env->fp_status); > } > > +void helper_set_rounding_mode_chkfrm(CPURISCVState *env, uint32_t rm) > +{ > + int softrm; > + > + /* Always validate frm, even if rm != DYN. */ > + if (unlikely(env->frm >= 5)) { > + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); > + } > + if (rm == RISCV_FRM_DYN) { > + rm = env->frm; > + } > + switch (rm) { > + case RISCV_FRM_RNE: > + softrm = float_round_nearest_even; > + break; > + case RISCV_FRM_RTZ: > + softrm = float_round_to_zero; > + break; > + case RISCV_FRM_RDN: > + softrm = float_round_down; > + break; > + case RISCV_FRM_RUP: > + softrm = float_round_up; > + break; > + case RISCV_FRM_RMM: > + softrm = float_round_ties_away; > + break; > + case RISCV_FRM_ROD: > + softrm = float_round_to_odd; > + break; > + default: > + g_assert_not_reached(); > + } > + > + set_float_rounding_mode(softrm, &env->fp_status); > +} > + > void helper_set_rod_rounding_mode(CPURISCVState *env) > { > set_float_rounding_mode(float_round_to_odd, &env->fp_status); > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index df38db7553..493c3815e1 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -114,6 +114,8 @@ typedef struct DisasContext { > bool pm_base_enabled; > /* Use icount trigger for native debug */ > bool itrigger; > + /* FRM is known to contain a valid value. */ > + bool frm_valid; > /* TCG of the current insn_start */ > TCGOp *insn_start; > } DisasContext; > @@ -674,12 +676,29 @@ static void gen_set_rm(DisasContext *ctx, int rm) > gen_helper_set_rod_rounding_mode(cpu_env); > return; > } > + if (rm == RISCV_FRM_DYN) { > + /* The helper will return only if frm valid. */ > + ctx->frm_valid = true; > + } > > /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ > decode_save_opc(ctx); > gen_helper_set_rounding_mode(cpu_env, tcg_constant_i32(rm)); > } > > +static void gen_set_rm_chkfrm(DisasContext *ctx, int rm) > +{ > + if (ctx->frm == rm && ctx->frm_valid) { > + return; > + } > + ctx->frm = rm; > + ctx->frm_valid = true; > + > + /* The helper may raise ILLEGAL_INSN -- record binv for unwind. */ > + decode_save_opc(ctx); > + gen_helper_set_rounding_mode_chkfrm(cpu_env, tcg_constant_i32(rm)); > +} > + > static int ex_plus_1(DisasContext *ctx, int nf) > { > return nf + 1; > diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc > index d455acedbf..bbb5c3a7b5 100644 > --- a/target/riscv/insn_trans/trans_rvv.c.inc > +++ b/target/riscv/insn_trans/trans_rvv.c.inc > @@ -2679,13 +2679,9 @@ static bool do_opfv(DisasContext *s, arg_rmr *a, > int rm) > { > if (checkfn(s, a)) { > - if (rm != RISCV_FRM_DYN) { > - gen_set_rm(s, RISCV_FRM_DYN); > - } > - > uint32_t data = 0; > TCGLabel *over = gen_new_label(); > - gen_set_rm(s, rm); > + gen_set_rm_chkfrm(s, rm); > tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); > tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); > > @@ -2882,17 +2878,13 @@ static bool opffv_widen_check(DisasContext *s, arg_rmr *a) > static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ > { \ > if (CHECK(s, a)) { \ > - if (FRM != RISCV_FRM_DYN) { \ > - gen_set_rm(s, RISCV_FRM_DYN); \ > - } \ > - \ > uint32_t data = 0; \ > static gen_helper_gvec_3_ptr * const fns[2] = { \ > gen_helper_##HELPER##_h, \ > gen_helper_##HELPER##_w, \ > }; \ > TCGLabel *over = gen_new_label(); \ > - gen_set_rm(s, FRM); \ > + gen_set_rm_chkfrm(s, FRM); \ > tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ > tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ > \ > @@ -3005,17 +2997,13 @@ static bool opffv_narrow_check(DisasContext *s, arg_rmr *a) > static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ > { \ > if (CHECK(s, a)) { \ > - if (FRM != RISCV_FRM_DYN) { \ > - gen_set_rm(s, RISCV_FRM_DYN); \ > - } \ > - \ > uint32_t data = 0; \ > static gen_helper_gvec_3_ptr * const fns[2] = { \ > gen_helper_##HELPER##_h, \ > gen_helper_##HELPER##_w, \ > }; \ > TCGLabel *over = gen_new_label(); \ > - gen_set_rm(s, FRM); \ > + gen_set_rm_chkfrm(s, FRM); \ > tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ > tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ > \ > @@ -3060,10 +3048,6 @@ static bool opxfv_narrow_check(DisasContext *s, arg_rmr *a) > static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ > { \ > if (opxfv_narrow_check(s, a)) { \ > - if (FRM != RISCV_FRM_DYN) { \ > - gen_set_rm(s, RISCV_FRM_DYN); \ > - } \ > - \ > uint32_t data = 0; \ > static gen_helper_gvec_3_ptr * const fns[3] = { \ > gen_helper_##HELPER##_b, \ > @@ -3071,7 +3055,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ > gen_helper_##HELPER##_w, \ > }; \ > TCGLabel *over = gen_new_label(); \ > - gen_set_rm(s, FRM); \ > + gen_set_rm_chkfrm(s, FRM); \ > tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ > tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ > \ > > From MAILER-DAEMON Wed Jan 18 19:18:12 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIId9-0006Ct-Tq for mharc-qemu-riscv@gnu.org; Wed, 18 Jan 2023 19:18:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIId8-0006CO-4c; Wed, 18 Jan 2023 19:18:10 -0500 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIId6-000879-D5; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=bmeng.cn@gmail.com; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 00:18:10 -0000 On Mon, Jan 16, 2023 at 8:37 PM Philippe Mathieu-Daud=C3=A9 wrote: > > On 16/1/23 13:29, Daniel Henrique Barboza wrote: > > Recent hw/risc/boot.c changes caused a regression in an use case with > > the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel' > > stopped working. The reason seems to be that Xvisor is using 64 bit to > > encode the 32 bit addresses from the guest, and load_elf_ram_sym() is > > sign-extending the result with '1's [1]. > > > > Use a translate_fn() callback to be called by load_elf_ram_sym() and > > return only the 32 bits address if we're running a 32 bit CPU. > > > > [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html > > > > Suggested-by: Philippe Mathieu-Daud=C3=A9 > > Suggested-by: Bin Meng > > Signed-off-by: Daniel Henrique Barboza > > --- > > hw/riscv/boot.c | 20 +++++++++++++++++++- > > hw/riscv/microchip_pfsoc.c | 4 ++-- > > hw/riscv/opentitan.c | 3 ++- > > hw/riscv/sifive_e.c | 3 ++- > > hw/riscv/sifive_u.c | 4 ++-- > > hw/riscv/spike.c | 2 +- > > hw/riscv/virt.c | 4 ++-- > > include/hw/riscv/boot.h | 1 + > > target/riscv/cpu_bits.h | 1 + > > 9 files changed, 32 insertions(+), 10 deletions(-) > > > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > > index e868fb6ade..0fd39df7f3 100644 > > --- a/hw/riscv/boot.c > > +++ b/hw/riscv/boot.c > > @@ -213,7 +213,24 @@ static void riscv_load_initrd(MachineState *machin= e, uint64_t kernel_entry) > > } > > } > > > > +static uint64_t translate_kernel_address(void *opaque, uint64_t addr) > > +{ > > + RISCVHartArrayState *harts =3D opaque; > > + > > + /* > > + * For 32 bit CPUs, kernel_load_base is sign-extended (i.e. > > + * it can be padded with '1's) if the hypervisor is using > > + * 64 bit addresses with 32 bit guests. > > + */ > > + if (riscv_is_32bit(harts)) { > > Maybe move the comment within the if() and add " so remove the sign > extension by truncating to 32-bit". > > > + return extract64(addr, 0, RV32_KERNEL_ADDR_LEN); > > For 32-bit maybe a definition is not necessary, I asked before > you used 24-bit in the previous version. As the maintainer prefer :) > > > + } > > + > > + return addr; > > +} > > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > > index 8b0d7e20ea..8fcaeae342 100644 > > --- a/target/riscv/cpu_bits.h > > +++ b/target/riscv/cpu_bits.h > > @@ -751,6 +751,7 @@ typedef enum RISCVException { > > #define MENVCFG_STCE (1ULL << 63) > > > > /* For RV32 */ > > +#define RV32_KERNEL_ADDR_LEN 32 > > #define MENVCFGH_PBMTE BIT(30) > > #define MENVCFGH_STCE BIT(31) > > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Isn't the problem in the ELF loader? Why does it return a 64-bit signed extended address given the 32-bit ELF im= age? Regards, Bin From MAILER-DAEMON Wed Jan 18 19:20:50 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIIfi-00072N-FC for mharc-qemu-riscv@gnu.org; Wed, 18 Jan 2023 19:20:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIIfg-000718-JO; Wed, 18 Jan 2023 19:20:48 -0500 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIIfe-0008QV-Bl; Wed, 18 Jan 2023 19:20:48 -0500 Received: by mail-ej1-x632.google.com with SMTP id vm8so1595119ejc.2; Wed, 18 Jan 2023 16:20:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=m4muWt7+KHIeYRqY0rLGpjneuhy1mnH2URYWVZbVF0o=; b=XCGuxh1ThPmujO7BrmtChkgejUb2vEbz8TGUoDhKzIp/T7pPrXNdVw1H85sDfXEHYD eQC1L0xu9S7CBrY/xLnJEpO2gvbR15twClU5sryNU2OtIdEgtLpW0O0Kr5dZlQ4fizlZ mcjamD1slv40xQ4xFnLK1IH36zyE+olb8OvScI71y0vMYkTFUszvVRBiBiol6LKDECs3 D7GKzD5ncp9pQM5GKzZX7rnDjXeBHOhRSn+fLTsXQXDVN3qb7Tn6x30SzCvJHkiOq4XG jOGbHt6ipWaM1QFQ9/IRnrT1VRX/qP1fohXDUhHo+sBXOY2z7dckueQDWAKwwtFE2lQF mjNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m4muWt7+KHIeYRqY0rLGpjneuhy1mnH2URYWVZbVF0o=; b=3xLPnga9VzjYuky4MMFc+UjC5ge+Uor52AdA7gMaGOhpP2VQOVrptf/R9ohxF7pKw7 BGZFcAtRJuchRmP1uXJLpOWePp5ZHJ1T2DPzaVXcZUD4QVX03Mrg/HIGiAPVbBSDOnkc HEnCQfad9mYGeIQzN5OzNisTDVn5oyBfuimU32s06NU4JtOIL7wqItpXfOPlyGDeIzLJ h7iQBqw0/k3+AwdkqJfSyjgM3bF2WpNMUWYrxbK8yO16kKnvYN2ly1b4LjKTCXXvFK1O o6aH11Svx2NEcTl9cAkxGcNBOPeanfANkMKME5IwXcDOCgaZ4pENRvdOA0oOAmMbqbfH K1QA== X-Gm-Message-State: AFqh2kqeSrlm3mPYOe6m0+Zm324jZ6nEpiqLd1NNGYruSrTx16c6Lw4J XFDAfWp7n91yKYjr0xhQwWe3C5nrEz6qOglxc0gcuwXV X-Google-Smtp-Source: AMrXdXsrBZ8xuUG6e2mIgVx6vxmP3nvZxXoA7GtGORbO9ZjE1CWbe8D/kCUzjYEZ7kOFZNLvhdBpx5m8E3Jwnvfn6Vk= X-Received: by 2002:a17:906:944:b0:86f:f270:b832 with SMTP id j4-20020a170906094400b0086ff270b832mr1033688ejd.26.1674087621683; Wed, 18 Jan 2023 16:20:21 -0800 (PST) MIME-Version: 1.0 References: <20230116122948.757515-1-dbarboza@ventanamicro.com> <20230116122948.757515-4-dbarboza@ventanamicro.com> In-Reply-To: <20230116122948.757515-4-dbarboza@ventanamicro.com> From: Bin Meng Date: Thu, 19 Jan 2023 08:20:15 +0800 Message-ID: Subject: Re: [PATCH v8 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym() To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 00:20:49 -0000 On Mon, Jan 16, 2023 at 8:30 PM Daniel Henrique Barboza wrote: > > Recent hw/risc/boot.c changes caused a regression in an use case with > the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel' > stopped working. The reason seems to be that Xvisor is using 64 bit to > encode the 32 bit addresses from the guest, and load_elf_ram_sym() is > sign-extending the result with '1's [1]. > > Use a translate_fn() callback to be called by load_elf_ram_sym() and > return only the 32 bits address if we're running a 32 bit CPU. > > [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html > > Suggested-by: Philippe Mathieu-Daud=C3=A9 > Suggested-by: Bin Meng > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/boot.c | 20 +++++++++++++++++++- > hw/riscv/microchip_pfsoc.c | 4 ++-- > hw/riscv/opentitan.c | 3 ++- > hw/riscv/sifive_e.c | 3 ++- > hw/riscv/sifive_u.c | 4 ++-- > hw/riscv/spike.c | 2 +- > hw/riscv/virt.c | 4 ++-- > include/hw/riscv/boot.h | 1 + > target/riscv/cpu_bits.h | 1 + > 9 files changed, 32 insertions(+), 10 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index e868fb6ade..0fd39df7f3 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -213,7 +213,24 @@ static void riscv_load_initrd(MachineState *machine,= uint64_t kernel_entry) > } > } > > +static uint64_t translate_kernel_address(void *opaque, uint64_t addr) > +{ > + RISCVHartArrayState *harts =3D opaque; > + > + /* > + * For 32 bit CPUs, kernel_load_base is sign-extended (i.e. > + * it can be padded with '1's) if the hypervisor is using > + * 64 bit addresses with 32 bit guests. This comment is not accurate. It has nothing to do with the hypervisor using a 64-bit address. It's the ELF loader that is sign-extending the 32-bit address. > + */ > + if (riscv_is_32bit(harts)) { > + return extract64(addr, 0, RV32_KERNEL_ADDR_LEN); > + } > + > + return addr; > +} > + > target_ulong riscv_load_kernel(MachineState *machine, > + RISCVHartArrayState *harts, > target_ulong kernel_start_addr, > bool load_initrd, > symbol_fn_t sym_cb) > @@ -231,7 +248,8 @@ target_ulong riscv_load_kernel(MachineState *machine, > * the (expected) load address load address. This allows kernels to = have > * separate SBI and ELF entry points (used by FreeBSD, for example). > */ > - if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, > + if (load_elf_ram_sym(kernel_filename, NULL, > + translate_kernel_address, NULL, > NULL, &kernel_load_base, NULL, NULL, 0, > EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { > kernel_entry =3D kernel_load_base; > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index c45023a2b1..b7e171b605 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -629,8 +629,8 @@ static void microchip_icicle_kit_machine_init(Machine= State *machine) > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpu= s, > firmware_end_ad= dr); > > - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, > - true, NULL); > + kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, > + kernel_start_addr, true, NULL); > > /* Compute the fdt load address in dram */ > fdt_load_addr =3D riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO]= .base, > diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c > index f6fd9725a5..1404a52da0 100644 > --- a/hw/riscv/opentitan.c > +++ b/hw/riscv/opentitan.c > @@ -101,7 +101,8 @@ static void opentitan_board_init(MachineState *machin= e) > } > > if (machine->kernel_filename) { > - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, false, NUL= L); > + riscv_load_kernel(machine, &s->soc.cpus, > + memmap[IBEX_DEV_RAM].base, false, NULL); > } > } > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > index 6835d1c807..04939b60c3 100644 > --- a/hw/riscv/sifive_e.c > +++ b/hw/riscv/sifive_e.c > @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machi= ne) > memmap[SIFIVE_E_DEV_MROM].base, &address_space= _memory); > > if (machine->kernel_filename) { > - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, > + riscv_load_kernel(machine, &s->soc.cpus, > + memmap[SIFIVE_E_DEV_DTIM].base, > false, NULL); > } > } > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index ccad386920..b0b3e6f03a 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -598,8 +598,8 @@ static void sifive_u_machine_init(MachineState *machi= ne) > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpu= s, > firmware_end_ad= dr); > > - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, > - true, NULL); > + kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, > + kernel_start_addr, true, NULL); > } else { > /* > * If dynamic firmware is used, it doesn't know where is the next= mode > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index 91bf194ec1..3c0ac916c0 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -305,7 +305,7 @@ static void spike_board_init(MachineState *machine) > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], > firmware_end_ad= dr); > > - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, > + kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], kernel_s= tart_addr, > true, htif_symbol_callback); > } else { > /* > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index e374b58f89..cf64da65bf 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -1281,8 +1281,8 @@ static void virt_machine_done(Notifier *notifier, v= oid *data) > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], > firmware_end_ad= dr); > > - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, > - true, NULL); > + kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], > + kernel_start_addr, true, NULL); > } else { > /* > * If dynamic firmware is used, it doesn't know where is the next= mode > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h > index cbd131bad7..bc9faed397 100644 > --- a/include/hw/riscv/boot.h > +++ b/include/hw/riscv/boot.h > @@ -44,6 +44,7 @@ target_ulong riscv_load_firmware(const char *firmware_f= ilename, > hwaddr firmware_load_addr, > symbol_fn_t sym_cb); > target_ulong riscv_load_kernel(MachineState *machine, > + RISCVHartArrayState *harts, > target_ulong firmware_end_addr, > bool load_initrd, > symbol_fn_t sym_cb); > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 8b0d7e20ea..8fcaeae342 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -751,6 +751,7 @@ typedef enum RISCVException { > #define MENVCFG_STCE (1ULL << 63) > > /* For RV32 */ > +#define RV32_KERNEL_ADDR_LEN 32 > #define MENVCFGH_PBMTE BIT(30) > #define MENVCFGH_STCE BIT(31) > > -- Regards, Bin From MAILER-DAEMON Wed Jan 18 19:23:47 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIIiY-0007w0-W4 for mharc-qemu-riscv@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::92b; envelope-from=alistair23@gmail.com; helo=mail-ua1-x92b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 00:23:45 -0000 On Tue, Jan 17, 2023 at 11:28 PM Daniel Henrique Barboza wrote: > > Commit 1c20d3ff6004 ("hw/riscv: virt: Add a machine done notifier") > moved the initialization of fw_cfg to the virt_machine_done() callback. > > Problem is that the validation of fw_cfg by devices such as ramfb is > done before the machine done notifier is called. Moving create_fw_cfg() > to machine_done() results in QEMU failing to boot when using a ramfb > device: > > ./qemu-system-riscv64 -machine virt -device ramfb -serial stdio > qemu-system-riscv64: -device ramfb: ramfb device requires fw_cfg with DMA > > The fix is simple: move create_fw_cfg() config back to > virt_machine_init(). This happens to be the same way the ARM 'virt' > machine deals with fw_cfg (see machvirt_init() and virt_machine_done() > in hw/arm/virt.c), so we're keeping consistency with how other machines > handle this device. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1343 > Signed-off-by: Daniel Henrique Barboza Thanks! Applied to riscv-to-apply.next Alistair > --- > hw/riscv/virt.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index e6d4f06e8d..4a11b4b010 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -1254,13 +1254,6 @@ static void virt_machine_done(Notifier *notifier, void *data) > firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, > start_addr, NULL); > > - /* > - * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the device > - * tree cannot be altered and we get FDT_ERR_NOSPACE. > - */ > - s->fw_cfg = create_fw_cfg(machine); > - rom_set_fw(s->fw_cfg); > - > if (drive_get(IF_PFLASH, 0, 1)) { > /* > * S-mode FW like EDK2 will be kept in second plash (unit 1). > @@ -1468,6 +1461,13 @@ static void virt_machine_init(MachineState *machine) > memory_region_add_subregion(system_memory, memmap[VIRT_MROM].base, > mask_rom); > > + /* > + * Init fw_cfg. Must be done before riscv_load_fdt, otherwise the > + * device tree cannot be altered and we get FDT_ERR_NOSPACE. > + */ > + s->fw_cfg = create_fw_cfg(machine); > + rom_set_fw(s->fw_cfg); > + > /* SiFive Test MMIO device */ > sifive_test_create(memmap[VIRT_TEST].base); > > -- > 2.39.0 > > From MAILER-DAEMON Wed Jan 18 19:25:40 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIIkO-0000GX-9N for mharc-qemu-riscv@gnu.org; Wed, 18 Jan 2023 19:25:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIIkM-0000GG-Ve; Wed, 18 Jan 2023 19:25:39 -0500 Received: from mail-vs1-xe32.google.com ([2607:f8b0:4864:20::e32]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIIkL-0000rs-F3; Wed, 18 Jan 2023 19:25:38 -0500 Received: by mail-vs1-xe32.google.com with SMTP id v127so509741vsb.12; Wed, 18 Jan 2023 16:25:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=HEdRdCDC7Rd8VCNhGbhhnwuK4D74h4j/IilETQOk5fg=; b=PjmjpmAoeJGImFxUY8J7CzbEOSIToMQOlL3ZLUE8aZE5cVUrcPR8KE92bnRcJ44pzl SoQzqzukgjBBBqK69lWGZuRVeXAOyQeK+UFPDaSslX+EcuBitjTFFl5WKuwdXRhAXcmA ABvdiyDcvIbfZGoIBvNGnlQYkXlQGrNc1/nlrIuBu8Pgg4vHvKBKGpps7VB+QZW5aR2+ 6OEWbX+u0TDO+wD4f1VY6jYZxWXafxVYVQefDbQXtSYEikexB/J0+ndBgGlR+RfW8MQL 9vrs1lDB7joUKkRA/XG5Qqv9lR6uLuoGbeyIYNFSamb2C9DP0mbMu7CfMCcQHo6MNgiI dx0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=HEdRdCDC7Rd8VCNhGbhhnwuK4D74h4j/IilETQOk5fg=; b=GIvwkesZ0nkBtkTaN/TVuPoUJehRv+lPX7sIKBn4BHU0O6kfgKQS/8sLM3LCc3C5Mu gSTVkYvZFdNnaJ3Z2WS+Ki31aX/b5q/fAsfQ0ua1aL+r+XAxNaie+7YQYifgzkzoTwqm lDxDfYj6mg/f/RHKa84gDwGUMILGPAex7wgl5qa7+CPoM3XCrBcJ7aMpXzw4izWiDxui 7651/H6Bu9aQSZHtF3wBaqNltaMjJt9hwFeThwnjQOcuTuVMsIPjzWfeb6ipU2e5Dfiv S/U6RYgVw8ipYej5W1qSizzc9qqGW0ZmoXkSJM2/X/hISZXZgVCTv9esxoUfnRuwDloy FfvA== X-Gm-Message-State: AFqh2ko/Uf6pQWKRTjyH0eynAa/6TmK1CaVVo7hqKwqe5g+QRCgWQlku iDhxJW4fXFEhgnAhzjIgY5gHRJpJNF1Z5R6FbQkkIYzGrjA= X-Google-Smtp-Source: AMrXdXu7BGwSlQNPAFe8ULRlsc5F+9kJ3nkFXtQlt7uInA/F/ZInI7z0wZRsxVFlwiqkYwI28sePTe2XrOLr3A+3G1g= X-Received: by 2002:a67:eb10:0:b0:3c9:8cc2:dd04 with SMTP id a16-20020a67eb10000000b003c98cc2dd04mr1325314vso.73.1674087936098; Wed, 18 Jan 2023 16:25:36 -0800 (PST) MIME-Version: 1.0 References: <20230113103453.42776-1-alexghiti@rivosinc.com> <20230113103453.42776-3-alexghiti@rivosinc.com> <20230117163138.jze47hjeeuwu2k4j@orel> <20230118121916.6aqj57leen72z5tz@orel> In-Reply-To: <20230118121916.6aqj57leen72z5tz@orel> From: Alistair Francis Date: Thu, 19 Jan 2023 10:25:10 +1000 Message-ID: Subject: Re: [PATCH v5 2/2] riscv: Allow user to set the satp mode To: Andrew Jones Cc: Alexandre Ghiti , Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e32; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe32.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 00:25:39 -0000 On Wed, Jan 18, 2023 at 10:19 PM Andrew Jones wrote: > > On Wed, Jan 18, 2023 at 10:28:46AM +1000, Alistair Francis wrote: > > On Wed, Jan 18, 2023 at 2:32 AM Andrew Jones wrote: > > > > > > On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote: > ... > > > > + > > > > + /* Get rid of 32-bit/64-bit incompatibility */ > > > > + for (int i = 0; i < 16; ++i) { > > > > + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > > > > > > If we ever define mode=1 for rv64, then 'sv32=on' will be incorrectly > > > accepted as an alias. I think we should simply not define the sv32 > > > property for rv64 nor the rv64-only modes for rv32. So, down in > > > riscv_add_satp_mode_properties() we can add some > > > > > > #if defined(TARGET_RISCV32) > > > ... > > > #elif defined(TARGET_RISCV64) > > > ... > > > #endif > > > > Do not add any #if defined(TARGET_RISCV32) to QEMU. > > > > We are aiming for the riscv64-softmmu to be able to emulate 32-bit > > CPUs and compile time macros are the wrong solution here. Instead you > > can get the xlen of the hart and use that. > > > > Does this mean we want to be able to do the following? > > qemu-system-riscv64 -cpu rv32,sv32=on ... That's the plan > > If so, then can we move the object_property_add() for sv32 to > rv32_base_cpu_init() and the rest to rv64_base_cpu_init()? > Currently, that would be doing the same thing as proposed above, > since those functions are under TARGET_RISCV* defines, but I guess > the object_property_add()'s would then be in more or less the right > places for when the 32-bit emulation support work is started. Sounds like a good idea :) Alistair > > Thanks, > drew From MAILER-DAEMON Wed Jan 18 19:36:42 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIIv4-000469-G4 for mharc-qemu-riscv@gnu.org; Wed, 18 Jan 2023 19:36:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIIv2-00045Z-2z; Wed, 18 Jan 2023 19:36:40 -0500 Received: from mail-vk1-xa2c.google.com ([2607:f8b0:4864:20::a2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIIv0-0002VJ-FS; Wed, 18 Jan 2023 19:36:39 -0500 Received: by mail-vk1-xa2c.google.com with SMTP id w72so193994vkw.7; Wed, 18 Jan 2023 16:36:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=Ef46n9SVz1wjhx9HrYZOJAYTKj+3Rcz0anhWanHanmg=; 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Wed, 18 Jan 2023 16:36:36 -0800 (PST) MIME-Version: 1.0 References: <20230116173420.1146808-1-dbarboza@ventanamicro.com> <20230116173420.1146808-2-dbarboza@ventanamicro.com> In-Reply-To: <20230116173420.1146808-2-dbarboza@ventanamicro.com> From: Alistair Francis Date: Thu, 19 Jan 2023 10:36:09 +1000 Message-ID: Subject: Re: [PATCH v2 1/6] hw/riscv/boot.c: calculate fdt size after fdt_pack() To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, philmd@linaro.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::a2c; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 00:36:40 -0000 On Tue, Jan 17, 2023 at 3:35 AM Daniel Henrique Barboza wrote: > > fdt_pack() can change the fdt size, meaning that fdt_totalsize() can > contain a now deprecated (bigger) value. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/boot.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 2594276223..dc14d8cd14 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -253,8 +253,13 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) > { > uint64_t temp, fdt_addr; > hwaddr dram_end = dram_base + mem_size; > - int ret, fdtsize = fdt_totalsize(fdt); > + int ret = fdt_pack(fdt); > + int fdtsize; > > + /* Should only fail if we've built a corrupted tree */ > + g_assert(ret == 0); > + > + fdtsize = fdt_totalsize(fdt); > if (fdtsize <= 0) { > error_report("invalid device-tree"); > exit(1); > -- > 2.39.0 > > From MAILER-DAEMON Wed Jan 18 21:06:17 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIKJl-0004nu-9T for mharc-qemu-riscv@gnu.org; Wed, 18 Jan 2023 21:06:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIKJk-0004nc-4I; Wed, 18 Jan 2023 21:06:16 -0500 Received: from mail-vs1-xe2e.google.com ([2607:f8b0:4864:20::e2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIKJi-0007Ql-1b; Wed, 18 Jan 2023 21:06:15 -0500 Received: by mail-vs1-xe2e.google.com with SMTP id i188so708437vsi.8; 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Wed, 18 Jan 2023 18:06:12 -0800 (PST) MIME-Version: 1.0 References: <20221108125703.1463577-1-apatel@ventanamicro.com> <20221108125703.1463577-3-apatel@ventanamicro.com> In-Reply-To: From: Alistair Francis Date: Thu, 19 Jan 2023 12:05:46 +1000 Message-ID: Subject: Re: [PATCH v2 2/5] target/riscv: Update VS timer whenever htimedelta changes To: Anup Patel Cc: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Atish Patra , Richard Henderson , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e2e; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 02:06:16 -0000 On Mon, Jan 16, 2023 at 3:20 PM Anup Patel wrote: > > Hi Alistair, > > On Tue, Jan 3, 2023 at 9:43 PM Anup Patel wrote: > > > > Hi Alistair, > > > > On Wed, Dec 28, 2022 at 11:08 AM Alistair Francis wrote: > > > > > > On Fri, Dec 23, 2022 at 11:14 PM Anup Patel wrote: > > > > > > > > On Thu, Dec 15, 2022 at 8:55 AM Alistair Francis wrote: > > > > > > > > > > On Mon, Dec 12, 2022 at 9:12 PM Anup Patel wrote: > > > > > > > > > > > > On Mon, Dec 12, 2022 at 11:23 AM Alistair Francis wrote: > > > > > > > > > > > > > > On Thu, Dec 8, 2022 at 6:41 PM Anup Patel wrote: > > > > > > > > > > > > > > > > On Thu, Dec 8, 2022 at 9:00 AM Alistair Francis wrote: > > > > > > > > > > > > > > > > > > On Tue, Nov 8, 2022 at 11:07 PM Anup Patel wrote: > > > > > > > > > > > > > > > > > > > > The htimedelta[h] CSR has impact on the VS timer comparison so we > > > > > > > > > > should call riscv_timer_write_timecmp() whenever htimedelta changes. > > > > > > > > > > > > > > > > > > > > Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") > > > > > > > > > > Signed-off-by: Anup Patel > > > > > > > > > > Reviewed-by: Alistair Francis > > > > > > > > > > > > > > > > > > This patch breaks my Xvisor test. When running OpenSBI and Xvisor like this: > > > > > > > > > > > > > > > > > > qemu-system-riscv64 -machine virt \ > > > > > > > > > -m 1G -serial mon:stdio -serial null -nographic \ > > > > > > > > > -append 'vmm.console=uart@10000000 vmm.bootcmd="vfs mount initrd > > > > > > > > > /;vfs run /boot.xscript;vfs cat /system/banner.txt; guest kick guest0; > > > > > > > > > vserial bind guest0/uart0"' \ > > > > > > > > > -smp 4 -d guest_errors \ > > > > > > > > > -bios none \ > > > > > > > > > -device loader,file=./images/qemuriscv64/vmm.bin,addr=0x80200000 \ > > > > > > > > > -kernel ./images/qemuriscv64/fw_jump.elf \ > > > > > > > > > -initrd ./images/qemuriscv64/vmm-disk-linux.img -cpu rv64,h=true > > > > > > > > > > > > > > > > > > Running: > > > > > > > > > > > > > > > > > > Xvisor v0.3.0-129-gbc33f339 (Jan 1 1970 00:00:00) > > > > > > > > > > > > > > > > > > I see this failure: > > > > > > > > > > > > > > > > > > INIT: bootcmd: guest kick guest0 > > > > > > > > > > > > > > > > > > guest0: Kicked > > > > > > > > > > > > > > > > > > INIT: bootcmd: vserial bind guest0/uart0 > > > > > > > > > > > > > > > > > > [guest0/uart0] cpu_vcpu_stage2_map: guest_phys=0x000000003B9AC000 > > > > > > > > > size=0x4096 map failed > > > > > > > > > > > > > > > > > > do_error: CPU3: VCPU=guest0/vcpu0 page fault failed (error -1) > > > > > > > > > > > > > > > > > > zero=0x0000000000000000 ra=0x0000000080001B4E > > > > > > > > > > > > > > > > > > sp=0x000000008001CF80 gp=0x0000000000000000 > > > > > > > > > > > > > > > > > > tp=0x0000000000000000 s0=0x000000008001CFB0 > > > > > > > > > > > > > > > > > > s1=0x0000000000000000 a0=0x0000000010001048 > > > > > > > > > > > > > > > > > > a1=0x0000000000000000 a2=0x0000000000989680 > > > > > > > > > > > > > > > > > > a3=0x000000003B9ACA00 a4=0x0000000000000048 > > > > > > > > > > > > > > > > > > a5=0x0000000000000000 a6=0x0000000000019000 > > > > > > > > > > > > > > > > > > a7=0x0000000000000000 s2=0x0000000000000000 > > > > > > > > > > > > > > > > > > s3=0x0000000000000000 s4=0x0000000000000000 > > > > > > > > > > > > > > > > > > s5=0x0000000000000000 s6=0x0000000000000000 > > > > > > > > > > > > > > > > > > s7=0x0000000000000000 s8=0x0000000000000000 > > > > > > > > > > > > > > > > > > s9=0x0000000000000000 s10=0x0000000000000000 > > > > > > > > > > > > > > > > > > s11=0x0000000000000000 t0=0x0000000000004000 > > > > > > > > > > > > > > > > > > t1=0x0000000000000100 t2=0x0000000000000000 > > > > > > > > > > > > > > > > > > t3=0x0000000000000000 t4=0x0000000000000000 > > > > > > > > > > > > > > > > > > t5=0x0000000000000000 t6=0x0000000000000000 > > > > > > > > > > > > > > > > > > sepc=0x0000000080001918 sstatus=0x0000000200004120 > > > > > > > > > > > > > > > > > > hstatus=0x00000002002001C0 sp_exec=0x0000000010A64000 > > > > > > > > > > > > > > > > > > scause=0x0000000000000017 stval=0x000000003B9ACAF8 > > > > > > > > > > > > > > > > > > htval=0x000000000EE6B2BE htinst=0x0000000000D03021 > > > > > > > > > > > > > > > > > > I have tried updating to a newer Xvisor release, but with that I don't > > > > > > > > > get any serial output. > > > > > > > > > > > > > > > > > > Can you help get the Xvisor tests back up and running? > > > > > > > > > > > > > > > > I tried the latest Xvisor-next (https://github.com/avpatel/xvisor-next) > > > > > > > > with your QEMU riscv-to-apply.next branch and it works fine (both > > > > > > > > with and without Sstc). > > > > > > > > > > > > > > Does it work with the latest release? > > > > > > > > > > > > Yes, the latest Xvisor-next repo works for QEMU v7.2.0-rc4 and > > > > > > your riscv-to-apply.next branch (commit 51bb9de2d188) > > > > > > > > > > I can't get anything to work with this patch. I have dropped this and > > > > > the patches after this. > > > > > > > > > > I'm building the latest Xvisor release with: > > > > > > > > > > export CROSS_COMPILE=riscv64-linux-gnu- > > > > > ARCH=riscv make generic-64b-defconfig > > > > > make > > > > > > > > > > and running it as above, yet nothing. What am I missing here? > > > > > > > > I tried multiple times with the latest Xvisor on different machines but > > > > still can't reproduce the issue you are seeing. > > > > > > Odd > > > > > > > > > > > We generally provide pre-built binaries with every Xvisor release > > > > so I will share with you pre-built binaries of the upcoming Xvisor-0.3.2 > > > > release. Maybe that would help you ? > > > > > > That would work. Let me know when the release happens and I can update > > > my images. > > > > Please download the Xvisor v0.3.2 pre-built binary tarball from: > > https://xhypervisor.org/tarball/xvisor-0.3.2-bins.tar.xz > > > > After untarring the above tarball, you can try the following command: > > $ qemu-system-riscv64 -M virt -m 512M -nographic -bios > > opensbi/build/platform/generic/firmware/fw_jump.bin -kernel > > xvisor-0.3.2-bins/riscv/rv64/xvisor/vmm.bin -initrd > > xvisor-0.3.2-bins/riscv/rv64/guest/virt64/disk-linux-6.1.1-one_guest_virt64.ext2 > > -append "vmm.bootcmd=\"vfs mount initrd /;vfs run /boot.xscript;vfs > > cat /system/banner.txt\"" > > OR > > $ qemu-system-riscv32 -M virt -m 512M -nographic -bios > > opensbi/build/platform/generic/firmware/fw_jump.bin -kernel > > xvisor-0.3.2-bins/riscv/rv32/xvisor/vmm.bin -initrd > > xvisor-0.3.2-bins/riscv/rv32/guest/virt32/disk-linux-6.1.1-one_guest_virt32.ext2 > > -append "vmm.bootcmd=\"vfs mount initrd /;vfs run /boot.xscript;vfs > > cat /system/banner.txt\"" Great! I have updated my tests and they are passing on the current QEMU master. > > Do you want me to rebase and resend the patches which > are not merged ? Yes please :) Alistair > > Regards, > Anup From MAILER-DAEMON Wed Jan 18 21:13:44 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIKQy-0006aQ-Oi for mharc-qemu-riscv@gnu.org; Wed, 18 Jan 2023 21:13:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIKQw-0006a4-KY; Wed, 18 Jan 2023 21:13:42 -0500 Received: from mail-vk1-xa2b.google.com ([2607:f8b0:4864:20::a2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIKQu-0008SN-LU; Wed, 18 Jan 2023 21:13:42 -0500 Received: by mail-vk1-xa2b.google.com with SMTP id 12so262923vkj.12; Wed, 18 Jan 2023 18:13:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=v2W7SXcjeLduz9XNKnGBLcG3e1m2QlJ/Rnmpk1M4XR0=; b=bC57CVGuAOdwjYUD3ikjXBo/R8tRM/PSVxSUOHiCzJpPbvKyEQKcXoHz7qQJAPcgO/ fy6tMX5RFrdnRVPtptaDI6en4hmUtteC3Px5y2kKva3r0g5QuROEiqpqgaTiyKqkOoGG oPXeSdB8wkQ7ZI9OI2pF7WOXcwJCuwgcKAYAehU3rj/bkfPGAmHyfqHEpWnPMDpxNd// yt1K8vnn4HYC2q9iHTsByQ1+XswBGL1wUScsHB7dUcvsMtpXroa4dRSwyXKSE8NJO0I6 crgyAFz47s42Eueq1v16T351oE0k1HGFn/L5iEl/YXQHpC9TFD2UAdeMPcRHmuWptb2P R80Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=v2W7SXcjeLduz9XNKnGBLcG3e1m2QlJ/Rnmpk1M4XR0=; b=rrkREh3eg47KxQuVcyaZT6lG+Kyb6StHvlK801ee2H3/0m/PIt1Qc0XyTiSEJcGReo OWuvry56/fO9ZWZ/5qNb2kBKdhZqh37XCdXrj4iFMcmDehyzBTra1Zmhl7gbHMDyOV14 HajfVRORB74RkeWsTNN2oqFVS4X/orArY8wVNij7GiXgd7dQTvEKL+hqr2HjRAdnRnSZ ca8mLK/cWUlmtYuPPn74iTeYaH6FSv5E2n+T0vg7iQguXZJEP3a6fa4sdtA2im41BG1u Zr/oknoAC2JULwsiy0ZBehR4qN+OixYkSRZnjf6PfySTimPSba18409vcw7ExH87IHK9 Z3IA== X-Gm-Message-State: AFqh2krDIYfeyPEF0XJzf8ljVrGd51qkIbo4GuyOS+f95l3cyhJoa5i4 wyuP1oi7NcI80koPl+55BlDk8BR2tah2xCG5908= X-Google-Smtp-Source: AMrXdXuDM/b/CEqy59UU3F940Ti6Nb+2aClYzypDKWw2m7kClbiR+bewJ3KcxL1UEXq/ojBsl8DUzcVmNLrczVSj6Jc= X-Received: by 2002:a1f:2c0c:0:b0:3e1:7e08:a117 with SMTP id s12-20020a1f2c0c000000b003e17e08a117mr1266096vks.34.1674094419077; Wed, 18 Jan 2023 18:13:39 -0800 (PST) MIME-Version: 1.0 References: <20230116173420.1146808-1-dbarboza@ventanamicro.com> <20230116173420.1146808-3-dbarboza@ventanamicro.com> In-Reply-To: <20230116173420.1146808-3-dbarboza@ventanamicro.com> From: Alistair Francis Date: Thu, 19 Jan 2023 12:13:13 +1000 Message-ID: Subject: Re: [PATCH v2 2/6] hw/riscv: split fdt address calculation from fdt load To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, philmd@linaro.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::a2b; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 02:13:43 -0000 On Tue, Jan 17, 2023 at 3:35 AM Daniel Henrique Barboza wrote: > > A common trend in other archs is to calculate the fdt address, which is > usually straightforward, and then calling a function that loads the > fdt/dtb by using that address. > > riscv_load_fdt() is doing a bit too much in comparison. It's calculating > the fdt address via an elaborated heuristic to put the FDT at the bottom > of DRAM, and "bottom of DRAM" will vary across boards and > configurations, then it's actually loading the fdt, and finally it's > returning the fdt address used to the caller. > > Reduce the existing complexity of riscv_load_fdt() by splitting its code > into a new function, riscv_compute_fdt_addr(), that will take care of > all fdt address logic. riscv_load_fdt() can then be a simple function > that just loads a fdt at the given fdt address. > > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/boot.c | 24 ++++++++++++++++-------- > hw/riscv/microchip_pfsoc.c | 6 ++++-- > hw/riscv/sifive_u.c | 7 ++++--- > hw/riscv/spike.c | 6 +++--- > hw/riscv/virt.c | 7 ++++--- > include/hw/riscv/boot.h | 3 ++- > 6 files changed, 33 insertions(+), 20 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index dc14d8cd14..b213a32157 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -249,9 +249,16 @@ void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) > } > } > > -uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) > +/* > + * The FDT should be put at the farthest point possible to > + * avoid overwriting it with the kernel/initrd. > + * > + * The FDT is fdt_packed() during the calculation. > + */ > +uint32_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size, > + void *fdt) > { > - uint64_t temp, fdt_addr; > + uint64_t temp; > hwaddr dram_end = dram_base + mem_size; > int ret = fdt_pack(fdt); > int fdtsize; > @@ -272,11 +279,14 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) > * end of dram or 3GB whichever is lesser. > */ > temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; > - fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); > > - ret = fdt_pack(fdt); > - /* Should only fail if we've built a corrupted tree */ > - g_assert(ret == 0); > + return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); > +} > + > +void riscv_load_fdt(uint32_t fdt_addr, void *fdt) > +{ > + uint32_t fdtsize = fdt_totalsize(fdt); > + > /* copy in the device tree */ > qemu_fdt_dumpdtb(fdt, fdtsize); > > @@ -284,8 +294,6 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) > &address_space_memory); > qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, > rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize)); > - > - return fdt_addr; > } > > void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index 82ae5e7023..dcdbc2cac3 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -641,8 +641,10 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) > } > > /* Compute the fdt load address in dram */ > - fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, > - machine->ram_size, machine->fdt); > + fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base, > + machine->ram_size, machine->fdt); > + riscv_load_fdt(fdt_load_addr, machine->fdt); > + > /* Load the reset vector */ > riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr, > memmap[MICROCHIP_PFSOC_ENVM_DATA].base, > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 2fb6ee231f..626d4dc2f3 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -616,9 +616,10 @@ static void sifive_u_machine_init(MachineState *machine) > kernel_entry = 0; > } > > - /* Compute the fdt load address in dram */ > - fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, > - machine->ram_size, machine->fdt); > + fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, > + machine->ram_size, machine->fdt); > + riscv_load_fdt(fdt_load_addr, machine->fdt); > + > if (!riscv_is_32bit(&s->soc.u_cpus)) { > start_addr_hi32 = (uint64_t)start_addr >> 32; > } > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index badc11ec43..88b9fdfc36 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -324,9 +324,9 @@ static void spike_board_init(MachineState *machine) > kernel_entry = 0; > } > > - /* Compute the fdt load address in dram */ > - fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, > - machine->ram_size, machine->fdt); > + fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, > + machine->ram_size, machine->fdt); > + riscv_load_fdt(fdt_load_addr, machine->fdt); > > /* load the reset vector */ > riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index e6d4f06e8d..839dfaa125 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -1307,9 +1307,10 @@ static void virt_machine_done(Notifier *notifier, void *data) > start_addr = virt_memmap[VIRT_FLASH].base; > } > > - /* Compute the fdt load address in dram */ > - fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, > - machine->ram_size, machine->fdt); > + fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, > + machine->ram_size, machine->fdt); > + riscv_load_fdt(fdt_load_addr, machine->fdt); > + > /* load the reset vector */ > riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, > virt_memmap[VIRT_MROM].base, > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h > index f94653a09b..9aea7b9c46 100644 > --- a/include/hw/riscv/boot.h > +++ b/include/hw/riscv/boot.h > @@ -47,7 +47,8 @@ target_ulong riscv_load_kernel(MachineState *machine, > target_ulong firmware_end_addr, > symbol_fn_t sym_cb); > void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); > -uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); > +uint32_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, void *fdt); > +void riscv_load_fdt(uint32_t fdt_addr, void *fdt); > void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, > hwaddr saddr, > hwaddr rom_base, hwaddr rom_size, > -- > 2.39.0 > > From MAILER-DAEMON Wed Jan 18 21:16:00 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIKTA-0007Pn-B0 for mharc-qemu-riscv@gnu.org; Wed, 18 Jan 2023 21:16:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIKT8-0007PU-9e; Wed, 18 Jan 2023 21:15:58 -0500 Received: from mail-vs1-xe33.google.com ([2607:f8b0:4864:20::e33]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIKT6-0000Ps-FM; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e33; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe33.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 02:15:58 -0000 On Tue, Jan 17, 2023 at 3:36 AM Daniel Henrique Barboza wrote: > > riscv_socket_count() returns either ms->numa_state->num_nodes or 1 > depending on NUMA support. In any case the value can be retrieved only > once and used in the rest of the function. > > This will also alleviate the rename we're going to do next by reducing > the instances of MachineState 'mc' inside hw/riscv/virt.c. > > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/virt.c | 34 +++++++++++++++++++--------------- > 1 file changed, 19 insertions(+), 15 deletions(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index cbba0b8930..8ff89c217f 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -505,13 +505,14 @@ static void create_fdt_imsic(RISCVVirtState *s, con= st MemMapEntry *memmap, > int cpu, socket; > char *imsic_name; > MachineState *mc =3D MACHINE(s); > + int socket_count =3D riscv_socket_count(mc); > uint32_t imsic_max_hart_per_socket, imsic_guest_bits; > uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; > > *msi_m_phandle =3D (*phandle)++; > *msi_s_phandle =3D (*phandle)++; > imsic_cells =3D g_new0(uint32_t, mc->smp.cpus * 2); > - imsic_regs =3D g_new0(uint32_t, riscv_socket_count(mc) * 4); > + imsic_regs =3D g_new0(uint32_t, socket_count * 4); > > /* M-level IMSIC node */ > for (cpu =3D 0; cpu < mc->smp.cpus; cpu++) { > @@ -519,7 +520,7 @@ static void create_fdt_imsic(RISCVVirtState *s, const= MemMapEntry *memmap, > imsic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_EXT); > } > imsic_max_hart_per_socket =3D 0; > - for (socket =3D 0; socket < riscv_socket_count(mc); socket++) { > + for (socket =3D 0; socket < socket_count; socket++) { > imsic_addr =3D memmap[VIRT_IMSIC_M].base + > socket * VIRT_IMSIC_GROUP_MAX_SIZE; > imsic_size =3D IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; > @@ -545,14 +546,14 @@ static void create_fdt_imsic(RISCVVirtState *s, con= st MemMapEntry *memmap, > qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", > imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); > qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, > - riscv_socket_count(mc) * sizeof(uint32_t) * 4); > + socket_count * sizeof(uint32_t) * 4); > qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", > VIRT_IRQCHIP_NUM_MSIS); > - if (riscv_socket_count(mc) > 1) { > + if (socket_count > 1) { > qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bit= s", > imsic_num_bits(imsic_max_hart_per_socket)); > qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bi= ts", > - imsic_num_bits(riscv_socket_count(mc))); > + imsic_num_bits(socket_count)); > qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-sh= ift", > IMSIC_MMIO_GROUP_MIN_SHIFT); > } > @@ -567,7 +568,7 @@ static void create_fdt_imsic(RISCVVirtState *s, const= MemMapEntry *memmap, > } > imsic_guest_bits =3D imsic_num_bits(s->aia_guests + 1); > imsic_max_hart_per_socket =3D 0; > - for (socket =3D 0; socket < riscv_socket_count(mc); socket++) { > + for (socket =3D 0; socket < socket_count; socket++) { > imsic_addr =3D memmap[VIRT_IMSIC_S].base + > socket * VIRT_IMSIC_GROUP_MAX_SIZE; > imsic_size =3D IMSIC_HART_SIZE(imsic_guest_bits) * > @@ -594,18 +595,18 @@ static void create_fdt_imsic(RISCVVirtState *s, con= st MemMapEntry *memmap, > qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", > imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); > qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, > - riscv_socket_count(mc) * sizeof(uint32_t) * 4); > + socket_count * sizeof(uint32_t) * 4); > qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", > VIRT_IRQCHIP_NUM_MSIS); > if (imsic_guest_bits) { > qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bi= ts", > imsic_guest_bits); > } > - if (riscv_socket_count(mc) > 1) { > + if (socket_count > 1) { > qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bit= s", > imsic_num_bits(imsic_max_hart_per_socket)); > qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bi= ts", > - imsic_num_bits(riscv_socket_count(mc))); > + imsic_num_bits(socket_count)); > qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-sh= ift", > IMSIC_MMIO_GROUP_MIN_SHIFT); > } > @@ -733,6 +734,7 @@ static void create_fdt_sockets(RISCVVirtState *s, con= st MemMapEntry *memmap, > MachineState *mc =3D MACHINE(s); > uint32_t msi_m_phandle =3D 0, msi_s_phandle =3D 0; > uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; > + int socket_count =3D riscv_socket_count(mc); > > qemu_fdt_add_subnode(mc->fdt, "/cpus"); > qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", > @@ -744,7 +746,7 @@ static void create_fdt_sockets(RISCVVirtState *s, con= st MemMapEntry *memmap, > intc_phandles =3D g_new0(uint32_t, mc->smp.cpus); > > phandle_pos =3D mc->smp.cpus; > - for (socket =3D (riscv_socket_count(mc) - 1); socket >=3D 0; socket-= -) { > + for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { > phandle_pos -=3D s->soc[socket].num_harts; > > clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", socket= ); > @@ -775,7 +777,7 @@ static void create_fdt_sockets(RISCVVirtState *s, con= st MemMapEntry *memmap, > } > > phandle_pos =3D mc->smp.cpus; > - for (socket =3D (riscv_socket_count(mc) - 1); socket >=3D 0; socket-= -) { > + for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { > phandle_pos -=3D s->soc[socket].num_harts; > > if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { > @@ -790,7 +792,7 @@ static void create_fdt_sockets(RISCVVirtState *s, con= st MemMapEntry *memmap, > > g_free(intc_phandles); > > - for (socket =3D 0; socket < riscv_socket_count(mc); socket++) { > + for (socket =3D 0; socket < socket_count; socket++) { > if (socket =3D=3D 0) { > *irq_mmio_phandle =3D xplic_phandles[socket]; > *irq_virtio_phandle =3D xplic_phandles[socket]; > @@ -1051,7 +1053,8 @@ static void create_fdt(RISCVVirtState *s, const Mem= MapEntry *memmap) > > /* Pass seed to RNG */ > qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); > - qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rn= g_seed)); > + qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", > + rng_seed, sizeof(rng_seed)); > } > > static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, > @@ -1335,9 +1338,10 @@ static void virt_machine_init(MachineState *machin= e) > char *soc_name; > DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; > int i, base_hartid, hart_count; > + int socket_count =3D riscv_socket_count(machine); > > /* Check socket count limit */ > - if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { > + if (VIRT_SOCKETS_MAX < socket_count) { > error_report("number of sockets/nodes should be less than %d", > VIRT_SOCKETS_MAX); > exit(1); > @@ -1345,7 +1349,7 @@ static void virt_machine_init(MachineState *machine= ) > > /* Initialize sockets */ > mmio_irqchip =3D virtio_irqchip =3D pcie_irqchip =3D NULL; > - for (i =3D 0; i < riscv_socket_count(machine); i++) { > + for (i =3D 0; i < socket_count; i++) { > if (!riscv_socket_check_hartids(machine, i)) { > error_report("discontinuous hartids in socket%d", i); > exit(1); > -- > 2.39.0 > > From MAILER-DAEMON Wed Jan 18 21:18:07 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIKVC-0008HR-MZ for mharc-qemu-riscv@gnu.org; Wed, 18 Jan 2023 21:18:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIKUb-0008DS-7H; Wed, 18 Jan 2023 21:17:31 -0500 Received: from mail-vs1-xe34.google.com ([2607:f8b0:4864:20::e34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIKUY-0000Zt-Cw; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e34; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe34.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 02:18:04 -0000 On Tue, Jan 17, 2023 at 3:35 AM Daniel Henrique Barboza wrote: > > Follow the QEMU convention of naming MachineState pointers as 'ms' by > renaming the instances where we're calling it 'mc'. > > Suggested-by: Philippe Mathieu-Daud=C3=A9 > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/spike.c | 18 +++++++++--------- > 1 file changed, 9 insertions(+), 9 deletions(-) > > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index afd581436b..222fde0c5c 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -56,7 +56,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry= *memmap, > uint64_t addr, size; > unsigned long clint_addr; > int cpu, socket; > - MachineState *mc =3D MACHINE(s); > + MachineState *ms =3D MACHINE(s); > uint32_t *clint_cells; > uint32_t cpu_phandle, intc_phandle, phandle =3D 1; > char *name, *mem_name, *clint_name, *clust_name; > @@ -65,7 +65,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry= *memmap, > "sifive,clint0", "riscv,clint0" > }; > > - fdt =3D mc->fdt =3D create_device_tree(&fdt_size); > + fdt =3D ms->fdt =3D create_device_tree(&fdt_size); > if (!fdt) { > error_report("create_device_tree() failed"); > exit(1); > @@ -96,7 +96,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry= *memmap, > qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); > qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); > > - for (socket =3D (riscv_socket_count(mc) - 1); socket >=3D 0; socket-= -) { > + for (socket =3D (riscv_socket_count(ms) - 1); socket >=3D 0; socket-= -) { > clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", socket= ); > qemu_fdt_add_subnode(fdt, clust_name); > > @@ -121,7 +121,7 @@ static void create_fdt(SpikeState *s, const MemMapEnt= ry *memmap, > qemu_fdt_setprop_cell(fdt, cpu_name, "reg", > s->soc[socket].hartid_base + cpu); > qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu")= ; > - riscv_socket_fdt_write_id(mc, cpu_name, socket); > + riscv_socket_fdt_write_id(ms, cpu_name, socket); > qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle)= ; > > intc_name =3D g_strdup_printf("%s/interrupt-controller", cpu= _name); > @@ -147,14 +147,14 @@ static void create_fdt(SpikeState *s, const MemMapE= ntry *memmap, > g_free(cpu_name); > } > > - addr =3D memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, s= ocket); > - size =3D riscv_socket_mem_size(mc, socket); > + addr =3D memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(ms, s= ocket); > + size =3D riscv_socket_mem_size(ms, socket); > mem_name =3D g_strdup_printf("/memory@%lx", (long)addr); > qemu_fdt_add_subnode(fdt, mem_name); > qemu_fdt_setprop_cells(fdt, mem_name, "reg", > addr >> 32, addr, size >> 32, size); > qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); > - riscv_socket_fdt_write_id(mc, mem_name, socket); > + riscv_socket_fdt_write_id(ms, mem_name, socket); > g_free(mem_name); > > clint_addr =3D memmap[SPIKE_CLINT].base + > @@ -167,14 +167,14 @@ static void create_fdt(SpikeState *s, const MemMapE= ntry *memmap, > 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); > qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", > clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4= ); > - riscv_socket_fdt_write_id(mc, clint_name, socket); > + riscv_socket_fdt_write_id(ms, clint_name, socket); > > g_free(clint_name); > g_free(clint_cells); > g_free(clust_name); > } > > - riscv_socket_fdt_write_distance_matrix(mc); > + riscv_socket_fdt_write_distance_matrix(ms); > > qemu_fdt_add_subnode(fdt, "/chosen"); > qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); > -- > 2.39.0 > > From MAILER-DAEMON Wed Jan 18 21:18:14 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIKVD-0008Hy-Jt for mharc-qemu-riscv@gnu.org; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e34; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe34.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 02:17:32 -0000 On Tue, Jan 17, 2023 at 3:36 AM Daniel Henrique Barboza wrote: > > We have a convention in other QEMU boards/archs to name MachineState > pointers as either 'machine' or 'ms'. MachineClass pointers are usually > called 'mc'. > > The 'virt' RISC-V machine has a lot of instances where MachineState > pointers are named 'mc'. There is nothing wrong with that, but we gain > more compatibility with the rest of the QEMU code base, and easier > reviews, if we follow QEMU conventions. > > Rename all 'mc' MachineState pointers to 'ms'. This is a very tedious > and mechanical patch that was produced by doing the following: > > - find/replace all 'MachineState *mc' to 'MachineState *ms'; > - find/replace all 'mc->fdt' to 'ms->fdt'; > - find/replace all 'mc->smp.cpus' to 'ms->smp.cpus'; > - replace any remaining occurrences of 'mc' that the compiler complained > about. > > Suggested-by: Philippe Mathieu-Daud=C3=A9 > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/virt.c | 434 ++++++++++++++++++++++++------------------------ > 1 file changed, 217 insertions(+), 217 deletions(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 8ff89c217f..479a90b3d5 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -227,7 +227,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s,= int socket, > { > int cpu; > uint32_t cpu_phandle; > - MachineState *mc =3D MACHINE(s); > + MachineState *ms =3D MACHINE(s); > char *name, *cpu_name, *core_name, *intc_name; > bool is_32_bit =3D riscv_is_32bit(&s->soc[0]); > > @@ -236,40 +236,40 @@ static void create_fdt_socket_cpus(RISCVVirtState *= s, int socket, > > cpu_name =3D g_strdup_printf("/cpus/cpu@%d", > s->soc[socket].hartid_base + cpu); > - qemu_fdt_add_subnode(mc->fdt, cpu_name); > + qemu_fdt_add_subnode(ms->fdt, cpu_name); > if (riscv_feature(&s->soc[socket].harts[cpu].env, > RISCV_FEATURE_MMU)) { > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > + qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", > (is_32_bit) ? "riscv,sv32" : "riscv,= sv48"); > } else { > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > + qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", > "riscv,none"); > } > name =3D riscv_isa_string(&s->soc[socket].harts[cpu]); > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); > + qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name); > g_free(name); > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv"= ); > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay"); > - qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", > + qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"= ); > + qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); > + qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", > s->soc[socket].hartid_base + cpu); > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu")= ; > - riscv_socket_fdt_write_id(mc, cpu_name, socket); > - qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle)= ; > + qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu")= ; > + riscv_socket_fdt_write_id(ms, cpu_name, socket); > + qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle)= ; > > intc_phandles[cpu] =3D (*phandle)++; > > intc_name =3D g_strdup_printf("%s/interrupt-controller", cpu_nam= e); > - qemu_fdt_add_subnode(mc->fdt, intc_name); > - qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", > + qemu_fdt_add_subnode(ms->fdt, intc_name); > + qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", > intc_phandles[cpu]); > - qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", > + qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", > "riscv,cpu-intc"); > - qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NUL= L, 0); > - qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1)= ; > + qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NUL= L, 0); > + qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1)= ; > > core_name =3D g_strdup_printf("%s/core%d", clust_name, cpu); > - qemu_fdt_add_subnode(mc->fdt, core_name); > - qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle); > + qemu_fdt_add_subnode(ms->fdt, core_name); > + qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); > > g_free(core_name); > g_free(intc_name); > @@ -282,16 +282,16 @@ static void create_fdt_socket_memory(RISCVVirtState= *s, > { > char *mem_name; > uint64_t addr, size; > - MachineState *mc =3D MACHINE(s); > + MachineState *ms =3D MACHINE(s); > > - addr =3D memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket= ); > - size =3D riscv_socket_mem_size(mc, socket); > + addr =3D memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket= ); > + size =3D riscv_socket_mem_size(ms, socket); > mem_name =3D g_strdup_printf("/memory@%lx", (long)addr); > - qemu_fdt_add_subnode(mc->fdt, mem_name); > - qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", > + qemu_fdt_add_subnode(ms->fdt, mem_name); > + qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", > addr >> 32, addr, size >> 32, size); > - qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); > - riscv_socket_fdt_write_id(mc, mem_name, socket); > + qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); > + riscv_socket_fdt_write_id(ms, mem_name, socket); > g_free(mem_name); > } > > @@ -303,7 +303,7 @@ static void create_fdt_socket_clint(RISCVVirtState *s= , > char *clint_name; > uint32_t *clint_cells; > unsigned long clint_addr; > - MachineState *mc =3D MACHINE(s); > + MachineState *ms =3D MACHINE(s); > static const char * const clint_compat[2] =3D { > "sifive,clint0", "riscv,clint0" > }; > @@ -319,15 +319,15 @@ static void create_fdt_socket_clint(RISCVVirtState = *s, > > clint_addr =3D memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * = socket); > clint_name =3D g_strdup_printf("/soc/clint@%lx", clint_addr); > - qemu_fdt_add_subnode(mc->fdt, clint_name); > - qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible", > + qemu_fdt_add_subnode(ms->fdt, clint_name); > + qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", > (char **)&clint_compat, > ARRAY_SIZE(clint_compat)); > - qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg", > + qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", > 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); > - qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", > + qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", > clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); > - riscv_socket_fdt_write_id(mc, clint_name, socket); > + riscv_socket_fdt_write_id(ms, clint_name, socket); > g_free(clint_name); > > g_free(clint_cells); > @@ -344,7 +344,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *= s, > uint32_t *aclint_mswi_cells; > uint32_t *aclint_sswi_cells; > uint32_t *aclint_mtimer_cells; > - MachineState *mc =3D MACHINE(s); > + MachineState *ms =3D MACHINE(s); > > aclint_mswi_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 2)= ; > aclint_mtimer_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * = 2); > @@ -363,16 +363,16 @@ static void create_fdt_socket_aclint(RISCVVirtState= *s, > if (s->aia_type !=3D VIRT_AIA_TYPE_APLIC_IMSIC) { > addr =3D memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * so= cket); > name =3D g_strdup_printf("/soc/mswi@%lx", addr); > - qemu_fdt_add_subnode(mc->fdt, name); > - qemu_fdt_setprop_string(mc->fdt, name, "compatible", > + qemu_fdt_add_subnode(ms->fdt, name); > + qemu_fdt_setprop_string(ms->fdt, name, "compatible", > "riscv,aclint-mswi"); > - qemu_fdt_setprop_cells(mc->fdt, name, "reg", > + qemu_fdt_setprop_cells(ms->fdt, name, "reg", > 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); > - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", > + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", > aclint_mswi_cells, aclint_cells_size); > - qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0)= ; > - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); > - riscv_socket_fdt_write_id(mc, name, socket); > + qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0)= ; > + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); > + riscv_socket_fdt_write_id(ms, name, socket); > g_free(name); > } > > @@ -386,33 +386,33 @@ static void create_fdt_socket_aclint(RISCVVirtState= *s, > size =3D memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; > } > name =3D g_strdup_printf("/soc/mtimer@%lx", addr); > - qemu_fdt_add_subnode(mc->fdt, name); > - qemu_fdt_setprop_string(mc->fdt, name, "compatible", > + qemu_fdt_add_subnode(ms->fdt, name); > + qemu_fdt_setprop_string(ms->fdt, name, "compatible", > "riscv,aclint-mtimer"); > - qemu_fdt_setprop_cells(mc->fdt, name, "reg", > + qemu_fdt_setprop_cells(ms->fdt, name, "reg", > 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, > 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, > 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, > 0x0, RISCV_ACLINT_DEFAULT_MTIME); > - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", > + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", > aclint_mtimer_cells, aclint_cells_size); > - riscv_socket_fdt_write_id(mc, name, socket); > + riscv_socket_fdt_write_id(ms, name, socket); > g_free(name); > > if (s->aia_type !=3D VIRT_AIA_TYPE_APLIC_IMSIC) { > addr =3D memmap[VIRT_ACLINT_SSWI].base + > (memmap[VIRT_ACLINT_SSWI].size * socket); > name =3D g_strdup_printf("/soc/sswi@%lx", addr); > - qemu_fdt_add_subnode(mc->fdt, name); > - qemu_fdt_setprop_string(mc->fdt, name, "compatible", > + qemu_fdt_add_subnode(ms->fdt, name); > + qemu_fdt_setprop_string(ms->fdt, name, "compatible", > "riscv,aclint-sswi"); > - qemu_fdt_setprop_cells(mc->fdt, name, "reg", > + qemu_fdt_setprop_cells(ms->fdt, name, "reg", > 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); > - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", > + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", > aclint_sswi_cells, aclint_cells_size); > - qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0)= ; > - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); > - riscv_socket_fdt_write_id(mc, name, socket); > + qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0)= ; > + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); > + riscv_socket_fdt_write_id(ms, name, socket); > g_free(name); > } > > @@ -430,7 +430,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s, > char *plic_name; > uint32_t *plic_cells; > unsigned long plic_addr; > - MachineState *mc =3D MACHINE(s); > + MachineState *ms =3D MACHINE(s); > static const char * const plic_compat[2] =3D { > "sifive,plic-1.0.0", "riscv,plic0" > }; > @@ -456,27 +456,27 @@ static void create_fdt_socket_plic(RISCVVirtState *= s, > plic_phandles[socket] =3D (*phandle)++; > plic_addr =3D memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * soc= ket); > plic_name =3D g_strdup_printf("/soc/plic@%lx", plic_addr); > - qemu_fdt_add_subnode(mc->fdt, plic_name); > - qemu_fdt_setprop_cell(mc->fdt, plic_name, > + qemu_fdt_add_subnode(ms->fdt, plic_name); > + qemu_fdt_setprop_cell(ms->fdt, plic_name, > "#interrupt-cells", FDT_PLIC_INT_CELLS); > - qemu_fdt_setprop_cell(mc->fdt, plic_name, > + qemu_fdt_setprop_cell(ms->fdt, plic_name, > "#address-cells", FDT_PLIC_ADDR_CELLS); > - qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", > + qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", > (char **)&plic_compat, > ARRAY_SIZE(plic_compat)); > - qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0= ); > - qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended", > + qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0= ); > + qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", > plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); > - qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg", > + qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", > 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); > - qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", > + qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", > VIRT_IRQCHIP_NUM_SOURCES - 1); > - riscv_socket_fdt_write_id(mc, plic_name, socket); > - qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", > + riscv_socket_fdt_write_id(ms, plic_name, socket); > + qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", > plic_phandles[socket]); > > if (!socket) { > - platform_bus_add_all_fdt_nodes(mc->fdt, plic_name, > + platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, > memmap[VIRT_PLATFORM_BUS].base, > memmap[VIRT_PLATFORM_BUS].size, > VIRT_PLATFORM_BUS_IRQ); > @@ -504,18 +504,18 @@ static void create_fdt_imsic(RISCVVirtState *s, con= st MemMapEntry *memmap, > { > int cpu, socket; > char *imsic_name; > - MachineState *mc =3D MACHINE(s); > - int socket_count =3D riscv_socket_count(mc); > + MachineState *ms =3D MACHINE(s); > + int socket_count =3D riscv_socket_count(ms); > uint32_t imsic_max_hart_per_socket, imsic_guest_bits; > uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; > > *msi_m_phandle =3D (*phandle)++; > *msi_s_phandle =3D (*phandle)++; > - imsic_cells =3D g_new0(uint32_t, mc->smp.cpus * 2); > + imsic_cells =3D g_new0(uint32_t, ms->smp.cpus * 2); > imsic_regs =3D g_new0(uint32_t, socket_count * 4); > > /* M-level IMSIC node */ > - for (cpu =3D 0; cpu < mc->smp.cpus; cpu++) { > + for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { > imsic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); > imsic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_EXT); > } > @@ -534,35 +534,35 @@ static void create_fdt_imsic(RISCVVirtState *s, con= st MemMapEntry *memmap, > } > imsic_name =3D g_strdup_printf("/soc/imsics@%lx", > (unsigned long)memmap[VIRT_IMSIC_M].base); > - qemu_fdt_add_subnode(mc->fdt, imsic_name); > - qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", > + qemu_fdt_add_subnode(ms->fdt, imsic_name); > + qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", > "riscv,imsics"); > - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", > + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", > FDT_IMSIC_INT_CELLS); > - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", > + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", > NULL, 0); > - qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", > + qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", > NULL, 0); > - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", > - imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); > - qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, > + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", > + imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); > + qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, > socket_count * sizeof(uint32_t) * 4); > - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", > + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", > VIRT_IRQCHIP_NUM_MSIS); > if (socket_count > 1) { > - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bit= s", > + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bit= s", > imsic_num_bits(imsic_max_hart_per_socket)); > - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bi= ts", > + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bi= ts", > imsic_num_bits(socket_count)); > - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-sh= ift", > + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-sh= ift", > IMSIC_MMIO_GROUP_MIN_SHIFT); > } > - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle= ); > + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phandle= ); > > g_free(imsic_name); > > /* S-level IMSIC node */ > - for (cpu =3D 0; cpu < mc->smp.cpus; cpu++) { > + for (cpu =3D 0; cpu < ms->smp.cpus; cpu++) { > imsic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); > imsic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_S_EXT); > } > @@ -583,34 +583,34 @@ static void create_fdt_imsic(RISCVVirtState *s, con= st MemMapEntry *memmap, > } > imsic_name =3D g_strdup_printf("/soc/imsics@%lx", > (unsigned long)memmap[VIRT_IMSIC_S].base); > - qemu_fdt_add_subnode(mc->fdt, imsic_name); > - qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", > + qemu_fdt_add_subnode(ms->fdt, imsic_name); > + qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", > "riscv,imsics"); > - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", > + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", > FDT_IMSIC_INT_CELLS); > - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", > + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", > NULL, 0); > - qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", > + qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", > NULL, 0); > - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", > - imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); > - qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, > + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", > + imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); > + qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, > socket_count * sizeof(uint32_t) * 4); > - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", > + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", > VIRT_IRQCHIP_NUM_MSIS); > if (imsic_guest_bits) { > - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bi= ts", > + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bi= ts", > imsic_guest_bits); > } > if (socket_count > 1) { > - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bit= s", > + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bit= s", > imsic_num_bits(imsic_max_hart_per_socket)); > - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bi= ts", > + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bi= ts", > imsic_num_bits(socket_count)); > - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-sh= ift", > + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-sh= ift", > IMSIC_MMIO_GROUP_MIN_SHIFT); > } > - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle= ); > + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_s_phandle= ); > g_free(imsic_name); > > g_free(imsic_regs); > @@ -629,7 +629,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s= , > char *aplic_name; > uint32_t *aplic_cells; > unsigned long aplic_addr; > - MachineState *mc =3D MACHINE(s); > + MachineState *ms =3D MACHINE(s); > uint32_t aplic_m_phandle, aplic_s_phandle; > > aplic_m_phandle =3D (*phandle)++; > @@ -644,28 +644,28 @@ static void create_fdt_socket_aplic(RISCVVirtState = *s, > aplic_addr =3D memmap[VIRT_APLIC_M].base + > (memmap[VIRT_APLIC_M].size * socket); > aplic_name =3D g_strdup_printf("/soc/aplic@%lx", aplic_addr); > - qemu_fdt_add_subnode(mc->fdt, aplic_name); > - qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,ap= lic"); > - qemu_fdt_setprop_cell(mc->fdt, aplic_name, > + qemu_fdt_add_subnode(ms->fdt, aplic_name); > + qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,ap= lic"); > + qemu_fdt_setprop_cell(ms->fdt, aplic_name, > "#interrupt-cells", FDT_APLIC_INT_CELLS); > - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, = 0); > + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, = 0); > if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC) { > - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", > + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", > aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2= ); > } else { > - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", > + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", > msi_m_phandle); > } > - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", > + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", > 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); > - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", > + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", > VIRT_IRQCHIP_NUM_SOURCES); > - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children", > + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", > aplic_s_phandle); > - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", > + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", > aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); > - riscv_socket_fdt_write_id(mc, aplic_name, socket); > - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandl= e); > + riscv_socket_fdt_write_id(ms, aplic_name, socket); > + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phandl= e); > g_free(aplic_name); > > /* S-level APLIC node */ > @@ -676,27 +676,27 @@ static void create_fdt_socket_aplic(RISCVVirtState = *s, > aplic_addr =3D memmap[VIRT_APLIC_S].base + > (memmap[VIRT_APLIC_S].size * socket); > aplic_name =3D g_strdup_printf("/soc/aplic@%lx", aplic_addr); > - qemu_fdt_add_subnode(mc->fdt, aplic_name); > - qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,ap= lic"); > - qemu_fdt_setprop_cell(mc->fdt, aplic_name, > + qemu_fdt_add_subnode(ms->fdt, aplic_name); > + qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,ap= lic"); > + qemu_fdt_setprop_cell(ms->fdt, aplic_name, > "#interrupt-cells", FDT_APLIC_INT_CELLS); > - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, = 0); > + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, = 0); > if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC) { > - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", > + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", > aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2= ); > } else { > - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", > + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", > msi_s_phandle); > } > - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", > + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", > 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); > - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", > + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", > VIRT_IRQCHIP_NUM_SOURCES); > - riscv_socket_fdt_write_id(mc, aplic_name, socket); > - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandl= e); > + riscv_socket_fdt_write_id(ms, aplic_name, socket); > + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_s_phandl= e); > > if (!socket) { > - platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name, > + platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, > memmap[VIRT_PLATFORM_BUS].base, > memmap[VIRT_PLATFORM_BUS].size, > VIRT_PLATFORM_BUS_IRQ); > @@ -711,13 +711,13 @@ static void create_fdt_socket_aplic(RISCVVirtState = *s, > static void create_fdt_pmu(RISCVVirtState *s) > { > char *pmu_name; > - MachineState *mc =3D MACHINE(s); > + MachineState *ms =3D MACHINE(s); > RISCVCPU hart =3D s->soc[0].harts[0]; > > pmu_name =3D g_strdup_printf("/soc/pmu"); > - qemu_fdt_add_subnode(mc->fdt, pmu_name); > - qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu"= ); > - riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name); > + qemu_fdt_add_subnode(ms->fdt, pmu_name); > + qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"= ); > + riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name); > > g_free(pmu_name); > } > @@ -731,26 +731,26 @@ static void create_fdt_sockets(RISCVVirtState *s, c= onst MemMapEntry *memmap, > { > char *clust_name; > int socket, phandle_pos; > - MachineState *mc =3D MACHINE(s); > + MachineState *ms =3D MACHINE(s); > uint32_t msi_m_phandle =3D 0, msi_s_phandle =3D 0; > uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; > - int socket_count =3D riscv_socket_count(mc); > + int socket_count =3D riscv_socket_count(ms); > > - qemu_fdt_add_subnode(mc->fdt, "/cpus"); > - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", > + qemu_fdt_add_subnode(ms->fdt, "/cpus"); > + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", > RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); > - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); > - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); > - qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); > + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); > + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); > + qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); > > - intc_phandles =3D g_new0(uint32_t, mc->smp.cpus); > + intc_phandles =3D g_new0(uint32_t, ms->smp.cpus); > > - phandle_pos =3D mc->smp.cpus; > + phandle_pos =3D ms->smp.cpus; > for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { > phandle_pos -=3D s->soc[socket].num_harts; > > clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", socket= ); > - qemu_fdt_add_subnode(mc->fdt, clust_name); > + qemu_fdt_add_subnode(ms->fdt, clust_name); > > create_fdt_socket_cpus(s, socket, clust_name, phandle, > &intc_phandles[phandle_pos]); > @@ -776,7 +776,7 @@ static void create_fdt_sockets(RISCVVirtState *s, con= st MemMapEntry *memmap, > *msi_pcie_phandle =3D msi_s_phandle; > } > > - phandle_pos =3D mc->smp.cpus; > + phandle_pos =3D ms->smp.cpus; > for (socket =3D (socket_count - 1); socket >=3D 0; socket--) { > phandle_pos -=3D s->soc[socket].num_harts; > > @@ -807,7 +807,7 @@ static void create_fdt_sockets(RISCVVirtState *s, con= st MemMapEntry *memmap, > } > } > > - riscv_socket_fdt_write_distance_matrix(mc); > + riscv_socket_fdt_write_distance_matrix(ms); > } > > static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memm= ap, > @@ -815,23 +815,23 @@ static void create_fdt_virtio(RISCVVirtState *s, co= nst MemMapEntry *memmap, > { > int i; > char *name; > - MachineState *mc =3D MACHINE(s); > + MachineState *ms =3D MACHINE(s); > > for (i =3D 0; i < VIRTIO_COUNT; i++) { > name =3D g_strdup_printf("/soc/virtio_mmio@%lx", > (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].si= ze)); > - qemu_fdt_add_subnode(mc->fdt, name); > - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmi= o"); > - qemu_fdt_setprop_cells(mc->fdt, name, "reg", > + qemu_fdt_add_subnode(ms->fdt, name); > + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmi= o"); > + qemu_fdt_setprop_cells(ms->fdt, name, "reg", > 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size= , > 0x0, memmap[VIRT_VIRTIO].size); > - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", > + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", > irq_virtio_phandle); > if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { > - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", > + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", > VIRTIO_IRQ + i); > } else { > - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", > + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", > VIRTIO_IRQ + i, 0x4); > } > g_free(name); > @@ -843,29 +843,29 @@ static void create_fdt_pcie(RISCVVirtState *s, cons= t MemMapEntry *memmap, > uint32_t msi_pcie_phandle) > { > char *name; > - MachineState *mc =3D MACHINE(s); > + MachineState *ms =3D MACHINE(s); > > name =3D g_strdup_printf("/soc/pci@%lx", > (long) memmap[VIRT_PCIE_ECAM].base); > - qemu_fdt_add_subnode(mc->fdt, name); > - qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells", > + qemu_fdt_add_subnode(ms->fdt, name); > + qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", > FDT_PCI_ADDR_CELLS); > - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", > + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", > FDT_PCI_INT_CELLS); > - qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2); > - qemu_fdt_setprop_string(mc->fdt, name, "compatible", > + qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); > + qemu_fdt_setprop_string(ms->fdt, name, "compatible", > "pci-host-ecam-generic"); > - qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci"); > - qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0); > - qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0, > + qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); > + qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); > + qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, > memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); > - qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0); > + qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); > if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) { > - qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phan= dle); > + qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phan= dle); > } > - qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0, > + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, > memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); > - qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges", > + qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", > 1, FDT_PCI_RANGE_IOPORT, 2, 0, > 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, > 1, FDT_PCI_RANGE_MMIO, > @@ -875,7 +875,7 @@ static void create_fdt_pcie(RISCVVirtState *s, const = MemMapEntry *memmap, > 2, virt_high_pcie_memmap.base, > 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); > > - create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle); > + create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); > g_free(name); > } > > @@ -884,39 +884,39 @@ static void create_fdt_reset(RISCVVirtState *s, con= st MemMapEntry *memmap, > { > char *name; > uint32_t test_phandle; > - MachineState *mc =3D MACHINE(s); > + MachineState *ms =3D MACHINE(s); > > test_phandle =3D (*phandle)++; > name =3D g_strdup_printf("/soc/test@%lx", > (long)memmap[VIRT_TEST].base); > - qemu_fdt_add_subnode(mc->fdt, name); > + qemu_fdt_add_subnode(ms->fdt, name); > { > static const char * const compat[3] =3D { > "sifive,test1", "sifive,test0", "syscon" > }; > - qemu_fdt_setprop_string_array(mc->fdt, name, "compatible", > + qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", > (char **)&compat, ARRAY_SIZE(compa= t)); > } > - qemu_fdt_setprop_cells(mc->fdt, name, "reg", > + qemu_fdt_setprop_cells(ms->fdt, name, "reg", > 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); > - qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle); > - test_phandle =3D qemu_fdt_get_phandle(mc->fdt, name); > + qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); > + test_phandle =3D qemu_fdt_get_phandle(ms->fdt, name); > g_free(name); > > name =3D g_strdup_printf("/reboot"); > - qemu_fdt_add_subnode(mc->fdt, name); > - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot"= ); > - qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); > - qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); > - qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET); > + qemu_fdt_add_subnode(ms->fdt, name); > + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"= ); > + qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); > + qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); > + qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); > g_free(name); > > name =3D g_strdup_printf("/poweroff"); > - qemu_fdt_add_subnode(mc->fdt, name); > - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-powerof= f"); > - qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); > - qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); > - qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS); > + qemu_fdt_add_subnode(ms->fdt, name); > + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-powerof= f"); > + qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); > + qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); > + qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); > g_free(name); > } > > @@ -924,24 +924,24 @@ static void create_fdt_uart(RISCVVirtState *s, cons= t MemMapEntry *memmap, > uint32_t irq_mmio_phandle) > { > char *name; > - MachineState *mc =3D MACHINE(s); > + MachineState *ms =3D MACHINE(s); > > name =3D g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0]= .base); > - qemu_fdt_add_subnode(mc->fdt, name); > - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a"); > - qemu_fdt_setprop_cells(mc->fdt, name, "reg", > + qemu_fdt_add_subnode(ms->fdt, name); > + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); > + qemu_fdt_setprop_cells(ms->fdt, name, "reg", > 0x0, memmap[VIRT_UART0].base, > 0x0, memmap[VIRT_UART0].size); > - qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); > - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_ph= andle); > + qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); > + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_ph= andle); > if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { > - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); > + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); > } else { > - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0= x4); > + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0= x4); > } > > - qemu_fdt_add_subnode(mc->fdt, "/chosen"); > - qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); > + qemu_fdt_add_subnode(ms->fdt, "/chosen"); > + qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); > g_free(name); > } > > @@ -949,20 +949,20 @@ static void create_fdt_rtc(RISCVVirtState *s, const= MemMapEntry *memmap, > uint32_t irq_mmio_phandle) > { > char *name; > - MachineState *mc =3D MACHINE(s); > + MachineState *ms =3D MACHINE(s); > > name =3D g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base= ); > - qemu_fdt_add_subnode(mc->fdt, name); > - qemu_fdt_setprop_string(mc->fdt, name, "compatible", > + qemu_fdt_add_subnode(ms->fdt, name); > + qemu_fdt_setprop_string(ms->fdt, name, "compatible", > "google,goldfish-rtc"); > - qemu_fdt_setprop_cells(mc->fdt, name, "reg", > + qemu_fdt_setprop_cells(ms->fdt, name, "reg", > 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); > - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", > + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", > irq_mmio_phandle); > if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { > - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); > + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); > } else { > - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4= ); > + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4= ); > } > g_free(name); > } > @@ -970,68 +970,68 @@ static void create_fdt_rtc(RISCVVirtState *s, const= MemMapEntry *memmap, > static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memma= p) > { > char *name; > - MachineState *mc =3D MACHINE(s); > + MachineState *ms =3D MACHINE(s); > hwaddr flashsize =3D virt_memmap[VIRT_FLASH].size / 2; > hwaddr flashbase =3D virt_memmap[VIRT_FLASH].base; > > name =3D g_strdup_printf("/flash@%" PRIx64, flashbase); > - qemu_fdt_add_subnode(mc->fdt, name); > - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); > - qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", > + qemu_fdt_add_subnode(ms->fdt, name); > + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); > + qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", > 2, flashbase, 2, flashsize, > 2, flashbase + flashsize, 2, flashsize)= ; > - qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); > + qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); > g_free(name); > } > > static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memm= ap) > { > char *nodename; > - MachineState *mc =3D MACHINE(s); > + MachineState *ms =3D MACHINE(s); > hwaddr base =3D memmap[VIRT_FW_CFG].base; > hwaddr size =3D memmap[VIRT_FW_CFG].size; > > nodename =3D g_strdup_printf("/fw-cfg@%" PRIx64, base); > - qemu_fdt_add_subnode(mc->fdt, nodename); > - qemu_fdt_setprop_string(mc->fdt, nodename, > + qemu_fdt_add_subnode(ms->fdt, nodename); > + qemu_fdt_setprop_string(ms->fdt, nodename, > "compatible", "qemu,fw-cfg-mmio"); > - qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", > + qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", > 2, base, 2, size); > - qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); > + qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); > g_free(nodename); > } > > static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) > { > - MachineState *mc =3D MACHINE(s); > + MachineState *ms =3D MACHINE(s); > uint32_t phandle =3D 1, irq_mmio_phandle =3D 1, msi_pcie_phandle =3D= 1; > uint32_t irq_pcie_phandle =3D 1, irq_virtio_phandle =3D 1; > uint8_t rng_seed[32]; > > - if (mc->dtb) { > - mc->fdt =3D load_device_tree(mc->dtb, &s->fdt_size); > - if (!mc->fdt) { > + if (ms->dtb) { > + ms->fdt =3D load_device_tree(ms->dtb, &s->fdt_size); > + if (!ms->fdt) { > error_report("load_device_tree() failed"); > exit(1); > } > } else { > - mc->fdt =3D create_device_tree(&s->fdt_size); > - if (!mc->fdt) { > + ms->fdt =3D create_device_tree(&s->fdt_size); > + if (!ms->fdt) { > error_report("create_device_tree() failed"); > exit(1); > } > } > > - qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu"); > - qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio"); > - qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2); > - qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2); > + qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); > + qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); > + qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); > + qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); > > - qemu_fdt_add_subnode(mc->fdt, "/soc"); > - qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0); > - qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus")= ; > - qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); > - qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); > + qemu_fdt_add_subnode(ms->fdt, "/soc"); > + qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); > + qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus")= ; > + qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); > + qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); > > create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle, > &irq_pcie_phandle, &irq_virtio_phandle, > @@ -1053,7 +1053,7 @@ static void create_fdt(RISCVVirtState *s, const Mem= MapEntry *memmap) > > /* Pass seed to RNG */ > qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); > - qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", > + qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", > rng_seed, sizeof(rng_seed)); > } > > @@ -1106,14 +1106,14 @@ static inline DeviceState *gpex_pcie_init(MemoryR= egion *sys_mem, > return dev; > } > > -static FWCfgState *create_fw_cfg(const MachineState *mc) > +static FWCfgState *create_fw_cfg(const MachineState *ms) > { > hwaddr base =3D virt_memmap[VIRT_FW_CFG].base; > FWCfgState *fw_cfg; > > fw_cfg =3D fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, > &address_space_memory); > - fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); > + fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); > > return fw_cfg; > } > -- > 2.39.0 > > From MAILER-DAEMON Wed Jan 18 21:23:56 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIKaq-0001jA-Ie for mharc-qemu-riscv@gnu.org; Wed, 18 Jan 2023 21:23:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIKap-0001iu-OQ; Wed, 18 Jan 2023 21:23:55 -0500 Received: from mail-ua1-x932.google.com ([2607:f8b0:4864:20::932]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIKan-0001Et-Uz; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::932; envelope-from=alistair23@gmail.com; helo=mail-ua1-x932.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 02:23:56 -0000 On Tue, Jan 17, 2023 at 3:34 AM Daniel Henrique Barboza wrote: > > All callers are using attributes from the MachineState object. Use a > pointer to it instead of passing dram_size (which is always > machine->ram_size) and fdt (always machine->fdt). > > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/boot.c | 6 +++--- > hw/riscv/microchip_pfsoc.c | 4 ++-- > hw/riscv/sifive_u.c | 4 ++-- > hw/riscv/spike.c | 4 ++-- > hw/riscv/virt.c | 3 +-- > include/hw/riscv/boot.h | 2 +- > 6 files changed, 11 insertions(+), 12 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index b213a32157..508da3f5c7 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -255,11 +255,11 @@ void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) > * > * The FDT is fdt_packed() during the calculation. > */ > -uint32_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size, > - void *fdt) > +uint32_t riscv_compute_fdt_addr(MachineState *machine, hwaddr dram_base) > { > + void *fdt = machine->fdt; > uint64_t temp; > - hwaddr dram_end = dram_base + mem_size; > + hwaddr dram_end = dram_base + machine->ram_size; > int ret = fdt_pack(fdt); > int fdtsize; > > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index dcdbc2cac3..a53e48e996 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -641,8 +641,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) > } > > /* Compute the fdt load address in dram */ > - fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base, > - machine->ram_size, machine->fdt); > + fdt_load_addr = riscv_compute_fdt_addr(machine, > + memmap[MICROCHIP_PFSOC_DRAM_LO].base); I don't think this is correct here. So, first up I understand we don't correctly handle this today, *but* I see this change as a step in the wrong direction. The problem here is that ram is split over two areas. So if machine->ram_size is larger then 0x40000000 it is going to overflow MICROCHIP_PFSOC_DRAM_LO and jump to MICROCHIP_PFSOC_DRAM_HI (0x1000000000). So we really want something like this /* Compute the fdt load address in dram */ if (machine->ram_size > memmap[MICROCHIP_PFSOC_DRAM_LO].size) { fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_HI].base, machine->ram_size - memmap[MICROCHIP_PFSOC_DRAM_LO].size, machine->fdt); } else { fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, machine->ram_size, machine->fdt); } to handle overflowing MICROCHIP_PFSOC_DRAM_LO. While this patch is going in the wrong direction and making that more difficult Alistair > riscv_load_fdt(fdt_load_addr, machine->fdt); > > /* Load the reset vector */ > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 626d4dc2f3..ebfddf161d 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -616,8 +616,8 @@ static void sifive_u_machine_init(MachineState *machine) > kernel_entry = 0; > } > > - fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, > - machine->ram_size, machine->fdt); > + fdt_load_addr = riscv_compute_fdt_addr(machine, > + memmap[SIFIVE_U_DEV_DRAM].base); > riscv_load_fdt(fdt_load_addr, machine->fdt); > > if (!riscv_is_32bit(&s->soc.u_cpus)) { > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index 88b9fdfc36..afd581436b 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -324,8 +324,8 @@ static void spike_board_init(MachineState *machine) > kernel_entry = 0; > } > > - fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, > - machine->ram_size, machine->fdt); > + fdt_load_addr = riscv_compute_fdt_addr(machine, > + memmap[SPIKE_DRAM].base); > riscv_load_fdt(fdt_load_addr, machine->fdt); > > /* load the reset vector */ > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 839dfaa125..cbba0b8930 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -1307,8 +1307,7 @@ static void virt_machine_done(Notifier *notifier, void *data) > start_addr = virt_memmap[VIRT_FLASH].base; > } > > - fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, > - machine->ram_size, machine->fdt); > + fdt_load_addr = riscv_compute_fdt_addr(machine, memmap[VIRT_DRAM].base); > riscv_load_fdt(fdt_load_addr, machine->fdt); > > /* load the reset vector */ > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h > index 9aea7b9c46..f933de88fb 100644 > --- a/include/hw/riscv/boot.h > +++ b/include/hw/riscv/boot.h > @@ -47,7 +47,7 @@ target_ulong riscv_load_kernel(MachineState *machine, > target_ulong firmware_end_addr, > symbol_fn_t sym_cb); > void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); > -uint32_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, void *fdt); > +uint32_t riscv_compute_fdt_addr(MachineState *machine, hwaddr dram_start); > void riscv_load_fdt(uint32_t fdt_addr, void *fdt); > void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, > hwaddr saddr, > -- > 2.39.0 > > From MAILER-DAEMON Thu Jan 19 00:46:29 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pINkr-00022y-4i for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 00:46:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pINkj-0001zZ-2k for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 00:46:21 -0500 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pINka-0005Vr-7u for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 00:46:20 -0500 Received: by mail-ej1-x62c.google.com with SMTP id mg12so2871135ejc.5 for ; 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Wed, 18 Jan 2023 21:46:05 -0800 (PST) MIME-Version: 1.0 References: <2882065D-831B-4E8C-BFD3-677BB8ECA2AD@kernel.org> In-Reply-To: From: Bin Meng Date: Thu, 19 Jan 2023 13:45:58 +0800 Message-ID: Subject: Re: qemu icicle kit es To: Conor Dooley Cc: stage TC , qemu-riscv@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 05:46:22 -0000 Hi Conor, On Sat, Jan 14, 2023 at 10:30 PM Conor Dooley wrote: > > On Fri, Jan 13, 2023 at 12:56:57PM +0000, Conor Dooley wrote: > > > > > > On 13 January 2023 00:35:11 GMT, Bin Meng wrote: > > >On Fri, Jan 13, 2023 at 2:03 AM Conor Dooley wrote: > > >> > > >> +CC Bin Meng > > >> > > > > >> Bin Meng, you're listed as a supporter (in master anyway) but is that > > >> still accurate? I figure there's a good chance it isn't anymore? > > >> Have you tested the platform from HSS init at all lately? > > > > > >Yes, I am still maintaining the QEMU PolarFire SoC. The WiKi page > > >listed the exact HSS version I tested and if it doesn't, it should be > > >a regression in QEMU. If yes, I would like to have a look at that. > > > > That'd be great. > > I submitted a few patches for fixing the direct kernel boot & hopefully > > haven't broken anything! > > I'll try to test it also, if I get some time. > > Gave 7.2.0 a go yesterday afternoon. > The URL from the documentation is no longer accessible, I cannot wget > the image! I'll try and find out what happened there, AFAIU that FTP is > still in use, so dunno why that file doesn't seem to be there. > I'll try to find out. > > I dug out the commit from the docs for the HSS, built that. Generated a > payload using the nearest payload generator commit to that was > compilable, which I passed as the image instead of the wic. > > The HSS would load, get as far as trying to extract the payload > containing the next stage bootloader & fail. Specifically, it was > complaining that the magic number for the payload was all zeros. > > Perhaps if you still have the original wic image you'll have more luck! > > Thanks, > Conor. > > | qemu-system-riscv64 -M microchip-icicle-kit -smp 5 \ > | -bios path/to/hss.bin -sd path/to/sdcard.img \ > | -nic user,model=cadence_gem \ > | -nic tap,ifname=tap,model=cadence_gem,script=no \ > | -display none -serial stdio \ > | -chardev socket,id=serial1,path=serial1.sock,server=on,wait=on \ > | -serial chardev:serial1 > > btw, I built my QEMU with `./configure --target-list=riscv64-softmmu && > make`, and got a complaint from the above command that user mode NICs > were not present in my QEMU. > The user mode NICs issue is because since QEMU 7.2, libslirp dependency was changed to an external build host dependency, so you need to manually install via something like "apt install libslirq-dev" in Ubuntu. Regards, Bin From MAILER-DAEMON Thu Jan 19 02:00:24 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIOuO-0006Q3-3O for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 02:00:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuC-0006KM-FL for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:14 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOu5-00087A-R4 for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674111604; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=QTrWewGIoykx+XnmrhebmHvWrWCti1OGcSiNiQ2VxVs=; b=IuyJ5vRIEhHiC9hcI0AJuiLg8ZJLMD0K4LXeC4rsijPxg2f0omVzihewISpEfWV6eC8dpd 9wL2Dy+5z7dnZtVq/YtuoX4DbqupLsct6La5fVFRsk14Mxm7tPgsTeuDpSQFDZNiXtbOyZ yJGmDzc7I/ek6kkf3HJKI/dVm66rzUk= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-330-wX_zTMW7Nn-CQSAWYa1Fkg-1; Thu, 19 Jan 2023 02:00:02 -0500 X-MC-Unique: wX_zTMW7Nn-CQSAWYa1Fkg-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 0583D1C05ACA; Thu, 19 Jan 2023 07:00:02 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 00F6B2166B29; Thu, 19 Jan 2023 07:00:00 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 3E01821E6A28; Thu, 19 Jan 2023 07:59:59 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 00/19] Clean up includes Date: Thu, 19 Jan 2023 07:59:40 +0100 Message-Id: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.6 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:00:14 -0000 Back in 2016, we discussed[1] rules for headers, and these were generally liked: 1. Have a carefully curated header that's included everywhere first. We got that already thanks to Peter: osdep.h. 2. Headers should normally include everything they need beyond osdep.h. If exceptions are needed for some reason, they must be documented in the header. If all that's needed from a header is typedefs, put those into qemu/typedefs.h instead of including the header. 3. Cyclic inclusion is forbidden. This series fixes violations of rule 2. I may have split patches too aggressively. Let me know if you want some squashed together. v4: * PATCH 01-03: New * PATCH 04-15: Previous version redone with scripts/clean-includes, result split up for review * PATCH 16-19: New v3: * Rebased, old PATCH 1+2+4 are in master as commit 881e019770..f07ceffdf5 * PATCH 1: Fix bsd-user v2: * Rebased * PATCH 3: v1 posted separately * PATCH 4: New [1] Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org> https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html Markus Armbruster (19): scripts/clean-includes: Fully skip / ignore files scripts/clean-includes: Don't claim duplicate headers found when not scripts/clean-includes: Skip symbolic links bsd-user: Clean up includes crypto: Clean up includes hw/cxl: Clean up includes hw/input: Clean up includes hw/tricore: Clean up includes qga: Clean up includes migration: Clean up includes net: Clean up includes target/hexagon: Clean up includes riscv: Clean up includes block: Clean up includes accel: Clean up includes Fix non-first inclusions of qemu/osdep.h Don't include headers already included by qemu/osdep.h 9p: Drop superfluous include of linux/limits.h Drop duplicate #include backends/tpm/tpm_ioctl.h | 2 -- bsd-user/bsd-proc.h | 4 ---- bsd-user/qemu.h | 1 - crypto/block-luks-priv.h | 1 - fsdev/p9array.h | 2 -- include/block/graph-lock.h | 1 - include/block/write-threshold.h | 2 -- include/hw/arm/fsl-imx6ul.h | 1 - include/hw/arm/fsl-imx7.h | 1 - include/hw/cxl/cxl_component.h | 2 -- include/hw/cxl/cxl_host.h | 1 - include/hw/cxl/cxl_pci.h | 1 - include/hw/input/pl050.h | 1 - include/hw/misc/aspeed_lpc.h | 2 -- include/hw/pci/pcie_doe.h | 1 - include/hw/tricore/triboard.h | 1 - include/qemu/async-teardown.h | 2 -- include/qemu/dbus.h | 1 - include/qemu/host-utils.h | 1 - include/qemu/userfaultfd.h | 1 - include/sysemu/accel-blocker.h | 1 - include/sysemu/event-loop-base.h | 1 - net/vmnet_int.h | 1 - qga/cutils.h | 2 -- target/hexagon/hex_arch_types.h | 1 - target/hexagon/mmvec/macros.h | 1 - target/riscv/pmu.h | 1 - accel/tcg/cpu-exec.c | 1 - audio/sndioaudio.c | 2 +- backends/hostmem-epc.c | 2 +- backends/tpm/tpm_emulator.c | 1 - block/export/vduse-blk.c | 2 +- block/qapi.c | 1 - bsd-user/arm/signal.c | 1 + bsd-user/arm/target_arch_cpu.c | 2 ++ bsd-user/freebsd/os-sys.c | 1 + bsd-user/i386/signal.c | 1 + bsd-user/i386/target_arch_cpu.c | 3 +-- bsd-user/main.c | 4 +--- bsd-user/strace.c | 1 - bsd-user/x86_64/signal.c | 1 + bsd-user/x86_64/target_arch_cpu.c | 3 +-- hw/9pfs/9p.c | 5 ----- hw/acpi/piix4.c | 1 - hw/alpha/dp264.c | 1 - hw/arm/virt.c | 1 - hw/arm/xlnx-versal.c | 1 - hw/block/pflash_cfi01.c | 1 - hw/core/machine.c | 1 - hw/display/virtio-gpu-udmabuf.c | 1 - hw/hppa/machine.c | 1 - hw/hyperv/syndbg.c | 2 +- hw/i2c/pmbus_device.c | 1 - hw/i386/acpi-build.c | 1 - hw/input/tsc210x.c | 1 - hw/loongarch/acpi-build.c | 1 - hw/misc/macio/cuda.c | 1 - hw/misc/macio/pmu.c | 1 - hw/net/xilinx_axienet.c | 1 - hw/ppc/ppc405_uc.c | 2 -- hw/ppc/ppc440_bamboo.c | 1 - hw/ppc/spapr_drc.c | 1 - hw/rdma/vmw/pvrdma_dev_ring.c | 1 - hw/remote/machine.c | 1 - hw/remote/proxy-memory-listener.c | 1 - hw/remote/remote-obj.c | 1 - hw/rtc/mc146818rtc.c | 1 - hw/s390x/virtio-ccw-serial.c | 1 - hw/sensor/adm1272.c | 1 - hw/usb/dev-storage-bot.c | 1 - hw/usb/dev-storage-classic.c | 1 - migration/postcopy-ram.c | 2 -- qga/commands-posix.c | 1 - qga/cutils.c | 3 ++- softmmu/dirtylimit.c | 1 - softmmu/runstate.c | 1 - softmmu/vl.c | 3 --- target/loongarch/translate.c | 1 - target/mips/tcg/translate.c | 1 - target/nios2/translate.c | 2 -- tcg/tci.c | 1 - tests/unit/test-cutils.c | 1 - tests/unit/test-seccomp.c | 1 - ui/gtk.c | 1 - ui/udmabuf.c | 1 - util/async-teardown.c | 12 ++++-------- util/main-loop.c | 1 - util/oslib-posix.c | 6 ------ scripts/clean-includes | 15 ++++++++++----- 89 files changed, 29 insertions(+), 123 deletions(-) -- 2.39.0 From MAILER-DAEMON Thu Jan 19 02:00:25 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIOuP-0006Sb-K4 for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 02:00:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuI-0006LX-Ms for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:20 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuG-0008AE-Ad for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:17 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674111608; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qwTU95ZFOsRMbuXZPZ33ukGTvyvrp8C5a1rdKoTsKuE=; b=cfOPArNWyxctvuVp34QdRPIORpBbDtqhaHQ8cKHW0q8ySpQaSwZb15wSu/P5tSkUGmbKQB NiACMEukCyk2WYpcXRVWZfDhb/8EDQmDGMCcxlNwKv7ZhCHF5FzR8AHyDnsgo3AzKEas37 E/Br2aoi/pekQx8f6CQB5p2MFwhCeP4= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-302-hwPOV9wiMhGKR87GHQhkUg-1; Thu, 19 Jan 2023 02:00:02 -0500 X-MC-Unique: hwPOV9wiMhGKR87GHQhkUg-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id CC85D8533DF; Thu, 19 Jan 2023 07:00:01 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 01168140EBF6; Thu, 19 Jan 2023 07:00:00 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 3FD1221E6806; Thu, 19 Jan 2023 07:59:59 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 01/19] scripts/clean-includes: Fully skip / ignore files Date: Thu, 19 Jan 2023 07:59:41 +0100 Message-Id: <20230119065959.3104012-2-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:00:23 -0000 When clean-includes claims to skip or ignore a file, only the part that sanitizes use of qemu/osdep.h skips the file. The part that looks for duplicate #include does not, and neither does committing to Git. The latter can get unrelated stuff included in the commit, but only if you run clean-includes in a dirty tree, which is unwise. Messed up when we added skipping in commit fd3e39a40c "scripts/clean-includes: Enhance to handle header files". The former can cause bogus reports for --check-dup-head. Added in commit d66253e46a "scripts/clean-includes: added duplicate #include check", duplicating the prior mistake. Fix the script to fully skip files. Fixes: fd3e39a40ca2ee26b09a5de3149af8b056b85233 Fixes: d66253e46ae2b9c36a9dd90b2b74c0dfa5804b22 Signed-off-by: Markus Armbruster --- scripts/clean-includes | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/scripts/clean-includes b/scripts/clean-includes index d37bd4f692..86944f27fc 100755 --- a/scripts/clean-includes +++ b/scripts/clean-includes @@ -111,6 +111,7 @@ cat >"$COCCIFILE" < 1) print $0}' if [ $? -eq 0 ]; then echo "Found duplicate header file includes. Please check the above files manually." @@ -184,7 +186,7 @@ if [ "$DUPHEAD" = "yes" ]; then fi if [ "$GIT" = "yes" ]; then - git add -- "$@" + git add -- $files git commit --signoff -F - <) id 1pIOuK-0006MY-Fr for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:22 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuG-0008AH-Du for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674111608; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rlmxNJSVO7GqLGy91wM0ekp2hbEv83W0/JnJaieGtI8=; b=HDmuJZpy7b1vWQmtfDm/t7drH+yG0qcaaqB+6K9Y5URb+apx5cGx6eM0qNJ5HeqcYpaOS9 ujTS02BQJ0EJzmjVDjGtb99EZQvanf/b9l2GpfK2JQLFAXmX3ysdNSBa9I0M5G06olqoT4 Oley2ZcwyZoACDzlIdRUvhFN+tGyRvw= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-265-JW2PeW3zPven5T6VEfRQig-1; Thu, 19 Jan 2023 02:00:05 -0500 X-MC-Unique: JW2PeW3zPven5T6VEfRQig-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id BAA2138107A4; Thu, 19 Jan 2023 07:00:03 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 4AE722166B29; Thu, 19 Jan 2023 07:00:03 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 5CA9921E6604; Thu, 19 Jan 2023 07:59:59 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 10/19] migration: Clean up includes Date: Thu, 19 Jan 2023 07:59:50 +0100 Message-Id: <20230119065959.3104012-11-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.6 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:00:23 -0000 Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster --- include/qemu/userfaultfd.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/qemu/userfaultfd.h b/include/qemu/userfaultfd.h index 6b74f92792..55c95998e8 100644 --- a/include/qemu/userfaultfd.h +++ b/include/qemu/userfaultfd.h @@ -13,7 +13,6 @@ #ifndef USERFAULTFD_H #define USERFAULTFD_H -#include "qemu/osdep.h" #include "exec/hwaddr.h" #include -- 2.39.0 From MAILER-DAEMON Thu Jan 19 02:00:35 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIOuY-0006XX-0x for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 02:00:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuG-0006LR-MH for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:19 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuE-00089E-AC for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:16 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674111607; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vhEyU3lG/HddlFOPbY0juv1v7ZnJ12wqNCac3xMgqpY=; b=SdbbhrVjiBkDD3jEa+pM+2Yn9hUeLTTcLNIryqDssuvr8o3uOZBaeHXiYxQoemn8bsXndh k7a8+mAWE+Q5d0LhHqgrkcUe7AZTWODnQ59xnbi4NxKA33IsjFQcUh6oFnE7gTNzyma/hF keztZEFes3NRZeX86rJgIshZ5m2RtvY= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-70-tT4Km-04Mlqzxd9U-zU7jg-1; Thu, 19 Jan 2023 02:00:04 -0500 X-MC-Unique: tT4Km-04Mlqzxd9U-zU7jg-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.rdu2.redhat.com [10.11.54.8]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id C24881C05AC4; Thu, 19 Jan 2023 07:00:03 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 86C2EC15BAD; Thu, 19 Jan 2023 07:00:03 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 6955C21E64D9; Thu, 19 Jan 2023 07:59:59 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 14/19] block: Clean up includes Date: Thu, 19 Jan 2023 07:59:54 +0100 Message-Id: <20230119065959.3104012-15-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.8 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:00:20 -0000 Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster --- include/block/graph-lock.h | 1 - include/block/write-threshold.h | 2 -- block/qapi.c | 1 - 3 files changed, 4 deletions(-) diff --git a/include/block/graph-lock.h b/include/block/graph-lock.h index 4c92cd8edf..ed9263b84e 100644 --- a/include/block/graph-lock.h +++ b/include/block/graph-lock.h @@ -20,7 +20,6 @@ #ifndef GRAPH_LOCK_H #define GRAPH_LOCK_H -#include "qemu/osdep.h" #include "qemu/clang-tsa.h" #include "qemu/coroutine.h" diff --git a/include/block/write-threshold.h b/include/block/write-threshold.h index f50f923e7e..63d1583887 100644 --- a/include/block/write-threshold.h +++ b/include/block/write-threshold.h @@ -13,8 +13,6 @@ #ifndef BLOCK_WRITE_THRESHOLD_H #define BLOCK_WRITE_THRESHOLD_H -#include "qemu/typedefs.h" - /* * bdrv_write_threshold_set: * diff --git a/block/qapi.c b/block/qapi.c index fea808425b..aede6a40d8 100644 --- a/block/qapi.c +++ b/block/qapi.c @@ -39,7 +39,6 @@ #include "qapi/qmp/qstring.h" #include "qemu/qemu-print.h" #include "sysemu/block-backend.h" -#include "qemu/cutils.h" BlockDeviceInfo *bdrv_block_device_info(BlockBackend *blk, BlockDriverState *bs, -- 2.39.0 From MAILER-DAEMON Thu Jan 19 02:00:37 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIOuZ-0006Y7-JY for mharc-qemu-riscv@gnu.org; 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Thu, 19 Jan 2023 02:00:03 -0500 X-MC-Unique: Cg00en9dPXqDrSzG9Rq4PQ-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.rdu2.redhat.com [10.11.54.8]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 3D36D857A85; Thu, 19 Jan 2023 07:00:02 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 013C8C15BAD; Thu, 19 Jan 2023 07:00:00 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 46D5621E66F2; Thu, 19 Jan 2023 07:59:59 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 03/19] scripts/clean-includes: Skip symbolic links Date: Thu, 19 Jan 2023 07:59:43 +0100 Message-Id: <20230119065959.3104012-4-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.8 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:00:20 -0000 When a symbolic link points to a file that needs cleaning, the script replaces the link with a cleaned regular file. Not wanted; skip them. We have a few symbolic links under subprojects/libvduse/ and subprojects/libvhost-user/. Signed-off-by: Markus Armbruster --- scripts/clean-includes | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/scripts/clean-includes b/scripts/clean-includes index 8e8420d785..f0466a6262 100755 --- a/scripts/clean-includes +++ b/scripts/clean-includes @@ -113,6 +113,10 @@ EOT files= for f in "$@"; do + if [ -L "$f" ]; then + echo "SKIPPING $f (symbolic link)" + continue + fi case "$f" in *.c.inc) # These aren't standalone C source files -- 2.39.0 From MAILER-DAEMON Thu Jan 19 02:00:39 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIOuc-0006aN-VU for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 02:00:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuK-0006Mh-Ik for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:22 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuG-0008ES-Ay for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674111614; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1UWK5caNJxvHgELn4bDbjg1pqfNuB1qVPvh1ja+y4EU=; b=KRgvRTZdDuUK/pl4IJTsFLRD2l5FzKH3TOLzthqx5Y7AMmFhoFkMoZ6HjgQfD+BI4gABov ZI2NNnfCbRIJY+BopHKUugTtP9C0wUZ6r/yPjUDakbyD+R0cGygbfdc7+UTxcBhmztbEt3 4ToidaGvjOE+ayzKkHCBFRfFCPJtUbk= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-495-oPfKJ0njPLC-22ldkbVsBg-1; Thu, 19 Jan 2023 02:00:03 -0500 X-MC-Unique: oPfKJ0njPLC-22ldkbVsBg-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id CC31A280BCA5; Thu, 19 Jan 2023 07:00:01 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 01259492B00; Thu, 19 Jan 2023 07:00:00 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 436D421E66CD; Thu, 19 Jan 2023 07:59:59 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 02/19] scripts/clean-includes: Don't claim duplicate headers found when not Date: Thu, 19 Jan 2023 07:59:42 +0100 Message-Id: <20230119065959.3104012-3-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:00:23 -0000 When running with --check-dup-head, the script always claims it "Found duplicate header file includes." Fix to do it only when it actually found some. Fixes: d66253e46ae2b9c36a9dd90b2b74c0dfa5804b22 Signed-off-by: Markus Armbruster --- scripts/clean-includes | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/scripts/clean-includes b/scripts/clean-includes index 86944f27fc..8e8420d785 100755 --- a/scripts/clean-includes +++ b/scripts/clean-includes @@ -177,9 +177,8 @@ for f in "$@"; do done if [ "$DUPHEAD" = "yes" ] && [ -n "$files" ]; then - egrep "^[[:space:]]*#[[:space:]]*include" $files | tr -d '[:blank:]' \ - | sort | uniq -c | awk '{if ($1 > 1) print $0}' - if [ $? -eq 0 ]; then + if egrep "^[[:space:]]*#[[:space:]]*include" $files | tr -d '[:blank:]' \ + | sort | uniq -c | grep -v '^ *1 '; then echo "Found duplicate header file includes. Please check the above files manually." exit 1 fi -- 2.39.0 From MAILER-DAEMON Thu Jan 19 02:00:41 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIOuf-0006b7-50 for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 02:00:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuC-0006KN-Ch for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:14 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOu6-00087K-Fr for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674111605; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=f/VVKT1WHi4fvcl9ZZ90491J4Of9RC38BDq4Nz8FniA=; b=WaXOb2QoxXPJC0A6TdgsHBvJLlv/QryPr++hPkYT/rSXWuusf1LoDpwnOXnR3zsfCf5oVx y7ybb4rv6xV0ebfN6RowmuBLH+XPjs8tonx4uYbIVWvJCyEpwRfl9X4F5SGLejzmUizfkP igpQ3dyB0APFWJArUwiURaRNU/I489w= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-484-h0uIO5eLMuGsc7HOrq1grQ-1; Thu, 19 Jan 2023 02:00:03 -0500 X-MC-Unique: h0uIO5eLMuGsc7HOrq1grQ-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 054D780D0E3; Thu, 19 Jan 2023 07:00:02 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 00F952166B2A; Thu, 19 Jan 2023 07:00:00 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 4A6DA21E6681; Thu, 19 Jan 2023 07:59:59 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 04/19] bsd-user: Clean up includes Date: Thu, 19 Jan 2023 07:59:44 +0100 Message-Id: <20230119065959.3104012-5-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.6 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:00:14 -0000 Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster --- bsd-user/bsd-proc.h | 4 ---- bsd-user/qemu.h | 1 - bsd-user/arm/signal.c | 1 + bsd-user/arm/target_arch_cpu.c | 2 ++ bsd-user/freebsd/os-sys.c | 1 + bsd-user/i386/signal.c | 1 + bsd-user/i386/target_arch_cpu.c | 3 +-- bsd-user/main.c | 4 +--- bsd-user/strace.c | 1 - bsd-user/x86_64/signal.c | 1 + bsd-user/x86_64/target_arch_cpu.c | 3 +-- 11 files changed, 9 insertions(+), 13 deletions(-) diff --git a/bsd-user/bsd-proc.h b/bsd-user/bsd-proc.h index 68b66e571d..a1061bffb8 100644 --- a/bsd-user/bsd-proc.h +++ b/bsd-user/bsd-proc.h @@ -20,11 +20,7 @@ #ifndef BSD_PROC_H_ #define BSD_PROC_H_ -#include -#include -#include #include -#include /* exit(2) */ static inline abi_long do_bsd_exit(void *cpu_env, abi_long arg1) diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index be6105385e..0ceecfb6df 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -17,7 +17,6 @@ #ifndef QEMU_H #define QEMU_H -#include "qemu/osdep.h" #include "cpu.h" #include "qemu/units.h" #include "exec/cpu_ldst.h" diff --git a/bsd-user/arm/signal.c b/bsd-user/arm/signal.c index 2b1dd745d1..9734407543 100644 --- a/bsd-user/arm/signal.c +++ b/bsd-user/arm/signal.c @@ -17,6 +17,7 @@ * along with this program; if not, see . */ +#include "qemu/osdep.h" #include "qemu.h" /* diff --git a/bsd-user/arm/target_arch_cpu.c b/bsd-user/arm/target_arch_cpu.c index 02bf9149d5..fe38ae2210 100644 --- a/bsd-user/arm/target_arch_cpu.c +++ b/bsd-user/arm/target_arch_cpu.c @@ -16,6 +16,8 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, see . */ + +#include "qemu/osdep.h" #include "target_arch.h" void target_cpu_set_tls(CPUARMState *env, target_ulong newtls) diff --git a/bsd-user/freebsd/os-sys.c b/bsd-user/freebsd/os-sys.c index 309e27b9d6..1676ec10f8 100644 --- a/bsd-user/freebsd/os-sys.c +++ b/bsd-user/freebsd/os-sys.c @@ -17,6 +17,7 @@ * along with this program; if not, see . */ +#include "qemu/osdep.h" #include "qemu.h" #include "target_arch_sysarch.h" diff --git a/bsd-user/i386/signal.c b/bsd-user/i386/signal.c index 5dd975ce56..a3131047b8 100644 --- a/bsd-user/i386/signal.c +++ b/bsd-user/i386/signal.c @@ -17,6 +17,7 @@ * along with this program; if not, see . */ +#include "qemu/osdep.h" #include "qemu.h" /* diff --git a/bsd-user/i386/target_arch_cpu.c b/bsd-user/i386/target_arch_cpu.c index d349e45299..2a3af2ddef 100644 --- a/bsd-user/i386/target_arch_cpu.c +++ b/bsd-user/i386/target_arch_cpu.c @@ -17,9 +17,8 @@ * along with this program; if not, see . */ -#include - #include "qemu/osdep.h" + #include "cpu.h" #include "qemu.h" #include "qemu/timer.h" diff --git a/bsd-user/main.c b/bsd-user/main.c index 6f09180d65..41290e16f9 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -18,12 +18,10 @@ * along with this program; if not, see . */ -#include -#include +#include "qemu/osdep.h" #include #include -#include "qemu/osdep.h" #include "qemu/help-texts.h" #include "qemu/units.h" #include "qemu/accel.h" diff --git a/bsd-user/strace.c b/bsd-user/strace.c index a77d10dd6b..96499751eb 100644 --- a/bsd-user/strace.c +++ b/bsd-user/strace.c @@ -20,7 +20,6 @@ #include #include #include -#include #include "qemu.h" diff --git a/bsd-user/x86_64/signal.c b/bsd-user/x86_64/signal.c index c3875bc4c6..46cb865180 100644 --- a/bsd-user/x86_64/signal.c +++ b/bsd-user/x86_64/signal.c @@ -16,6 +16,7 @@ * along with this program; if not, see . */ +#include "qemu/osdep.h" #include "qemu.h" /* diff --git a/bsd-user/x86_64/target_arch_cpu.c b/bsd-user/x86_64/target_arch_cpu.c index be7bd10720..1d32f18907 100644 --- a/bsd-user/x86_64/target_arch_cpu.c +++ b/bsd-user/x86_64/target_arch_cpu.c @@ -17,9 +17,8 @@ * along with this program; if not, see . */ -#include - #include "qemu/osdep.h" + #include "cpu.h" #include "qemu.h" #include "qemu/timer.h" -- 2.39.0 From MAILER-DAEMON Thu Jan 19 02:00:43 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIOuh-0006cc-KL for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 02:00:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuI-0006LZ-Mz for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:20 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuF-0008CM-1a for qemu-riscv@nongnu.org; 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Thu, 19 Jan 2023 07:00:05 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id BCBC22166B29; Thu, 19 Jan 2023 07:00:04 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 6C88621E5DCF; Thu, 19 Jan 2023 07:59:59 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 15/19] accel: Clean up includes Date: Thu, 19 Jan 2023 07:59:55 +0100 Message-Id: <20230119065959.3104012-16-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.6 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:00:23 -0000 Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster --- include/sysemu/accel-blocker.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/sysemu/accel-blocker.h b/include/sysemu/accel-blocker.h index 72020529ef..0733783bcc 100644 --- a/include/sysemu/accel-blocker.h +++ b/include/sysemu/accel-blocker.h @@ -14,7 +14,6 @@ #ifndef ACCEL_BLOCKER_H #define ACCEL_BLOCKER_H -#include "qemu/osdep.h" #include "sysemu/cpus.h" extern void accel_blocker_init(void); -- 2.39.0 From MAILER-DAEMON Thu Jan 19 02:00:44 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIOui-0006e0-Fh for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 02:00:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuK-0006Md-Hv for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:22 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuG-00089z-AM for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674111607; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=osxuc13IOeeQnt/BeEajhTLlc11XxWiHUgCrHTX7RbI=; b=dms9iDgdml0V5rcUcqR0Ikt3s8DIBM1ruYsVi0q7WRuiYF1+QE7ZSbfiRx1upcw41hXHpP V3m7LMWRoanAp8mqhMIsTU+8lnqXOhMiyG3IrEEjg2oCyyv6IGSQOLbe/iP1viwnLooIg1 qgRQcY/EhkhwUDr+5P9OISfF7moCCpc= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-57-ivgpKZvLNv-GQ1VCnY-zlw-1; Thu, 19 Jan 2023 02:00:04 -0500 X-MC-Unique: ivgpKZvLNv-GQ1VCnY-zlw-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 5578E1C05AC6; Thu, 19 Jan 2023 07:00:03 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 1C700492B00; Thu, 19 Jan 2023 07:00:03 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 4DB3A21E669F; Thu, 19 Jan 2023 07:59:59 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 05/19] crypto: Clean up includes Date: Thu, 19 Jan 2023 07:59:45 +0100 Message-Id: <20230119065959.3104012-6-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:00:23 -0000 Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster --- crypto/block-luks-priv.h | 1 - 1 file changed, 1 deletion(-) diff --git a/crypto/block-luks-priv.h b/crypto/block-luks-priv.h index 90a20d432b..1066df0307 100644 --- a/crypto/block-luks-priv.h +++ b/crypto/block-luks-priv.h @@ -18,7 +18,6 @@ * */ -#include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/bswap.h" -- 2.39.0 From MAILER-DAEMON Thu Jan 19 02:00:59 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIOuw-0006js-W1 for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 02:00:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuN-0006OD-AD for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:23 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuK-00089u-4D for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674111607; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HSvmGx9pg7RM2UEWG6YDDRKexZJzuEM2p+pEafedpfY=; b=VJbzcXUprM3JPj3Hey/rT+HjiEiFiQBPjCuYnf0/4+d+Z7IPunYqmaRgyinI60HquMbE8D xOPaq2rmknwItW128uNcqKmdpHzfO6JDu8dAvkG37T3hKoa4kMERUO22i5AEImA+hiwBYZ 5LGsDMzKIttjF9vv32iJUGvXOFXhG0k= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-191-RftXGxXaP_auvQ_IYat3Fg-1; Thu, 19 Jan 2023 02:00:04 -0500 X-MC-Unique: RftXGxXaP_auvQ_IYat3Fg-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 8E42680D0F1; Thu, 19 Jan 2023 07:00:03 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 45BED53AA; Thu, 19 Jan 2023 07:00:03 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 599D921E6602; Thu, 19 Jan 2023 07:59:59 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 09/19] qga: Clean up includes Date: Thu, 19 Jan 2023 07:59:49 +0100 Message-Id: <20230119065959.3104012-10-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.5 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:00:23 -0000 Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster --- qga/cutils.h | 2 -- qga/commands-posix.c | 1 - qga/cutils.c | 3 ++- 3 files changed, 2 insertions(+), 4 deletions(-) diff --git a/qga/cutils.h b/qga/cutils.h index f0f30a7d28..c1f2f4b17a 100644 --- a/qga/cutils.h +++ b/qga/cutils.h @@ -1,8 +1,6 @@ #ifndef CUTILS_H_ #define CUTILS_H_ -#include "qemu/osdep.h" - int qga_open_cloexec(const char *name, int flags, mode_t mode); #endif /* CUTILS_H_ */ diff --git a/qga/commands-posix.c b/qga/commands-posix.c index ebd33a643c..079689d79a 100644 --- a/qga/commands-posix.c +++ b/qga/commands-posix.c @@ -51,7 +51,6 @@ #else #include #endif -#include #ifdef CONFIG_SOLARIS #include #endif diff --git a/qga/cutils.c b/qga/cutils.c index b8e142ef64..b21bcf3683 100644 --- a/qga/cutils.c +++ b/qga/cutils.c @@ -2,8 +2,9 @@ * This work is licensed under the terms of the GNU GPL, version 2 or later. * See the COPYING file in the top-level directory. */ -#include "cutils.h" +#include "qemu/osdep.h" +#include "cutils.h" #include "qapi/error.h" /** -- 2.39.0 From MAILER-DAEMON Thu Jan 19 02:01:07 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIOv5-0006w3-Ev for mharc-qemu-riscv@gnu.org; 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Thu, 19 Jan 2023 02:00:06 -0500 X-MC-Unique: k0ksHQ5UPmaK26KYeiBTfg-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 10CCE8533DC; Thu, 19 Jan 2023 07:00:05 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C72D1492B00; Thu, 19 Jan 2023 07:00:04 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 763DE21E5A10; Thu, 19 Jan 2023 07:59:59 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 18/19] 9p: Drop superfluous include of linux/limits.h Date: Thu, 19 Jan 2023 07:59:58 +0100 Message-Id: <20230119065959.3104012-19-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:00:35 -0000 Signed-off-by: Markus Armbruster --- hw/9pfs/9p.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/hw/9pfs/9p.c b/hw/9pfs/9p.c index 9621ec1341..aa736af380 100644 --- a/hw/9pfs/9p.c +++ b/hw/9pfs/9p.c @@ -17,9 +17,6 @@ */ #include "qemu/osdep.h" -#ifdef CONFIG_LINUX -#include -#endif #include #include "hw/virtio/virtio.h" #include "qapi/error.h" -- 2.39.0 From MAILER-DAEMON Thu Jan 19 02:01:08 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIOv6-0006wt-33 for mharc-qemu-riscv@gnu.org; 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Thu, 19 Jan 2023 02:00:04 -0500 X-MC-Unique: Zxhx27h3OOuE5zFfnbZVtA-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.rdu2.redhat.com [10.11.54.1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id C63C18533EB; Thu, 19 Jan 2023 07:00:03 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 82B4640AE1E9; Thu, 19 Jan 2023 07:00:03 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 664A421E660B; Thu, 19 Jan 2023 07:59:59 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 13/19] riscv: Clean up includes Date: Thu, 19 Jan 2023 07:59:53 +0100 Message-Id: <20230119065959.3104012-14-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.1 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:00:32 -0000 Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster --- target/riscv/pmu.h | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 3004ce37b6..0c819ca983 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -16,7 +16,6 @@ * this program. If not, see . */ -#include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" #include "qemu/main-loop.h" -- 2.39.0 From MAILER-DAEMON Thu Jan 19 02:01:09 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIOv6-0006xi-Pg for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 02:01:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuR-0006U1-4v for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:29 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuM-0008Dg-2G for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674111612; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2nRzSBI+z71BQtIowwh7PoYogxSqubchXssS1ZNYabo=; b=HvteqmGoyOutRhSTwGcFsTpBTEPqvhlVXafBgY8FXMCiRvDJ5N1tzRmfGMPrkA1Q9vYD6j oIPhFJDgYNK0MPiHlvenWj7J0jufETsnvA6TzMhgmy7tf5EOfk85PlkJFEnmputaghgYul LSacvlibAipeMyWfgCchOrLAcUviTsw= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-92-omVfXSvrOdeCbhWsJH-HdA-1; Thu, 19 Jan 2023 02:00:06 -0500 X-MC-Unique: omVfXSvrOdeCbhWsJH-HdA-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 41BFF3810795; Thu, 19 Jan 2023 07:00:05 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C85982166B2A; Thu, 19 Jan 2023 07:00:04 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 7993121E5A11; Thu, 19 Jan 2023 07:59:59 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 19/19] Drop duplicate #include Date: Thu, 19 Jan 2023 07:59:59 +0100 Message-Id: <20230119065959.3104012-20-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.6 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:00:32 -0000 Tracked down with the help of scripts/clean-includes. Signed-off-by: Markus Armbruster --- include/hw/arm/fsl-imx6ul.h | 1 - include/hw/arm/fsl-imx7.h | 1 - backends/tpm/tpm_emulator.c | 1 - hw/acpi/piix4.c | 1 - hw/alpha/dp264.c | 1 - hw/arm/virt.c | 1 - hw/arm/xlnx-versal.c | 1 - hw/block/pflash_cfi01.c | 1 - hw/core/machine.c | 1 - hw/hppa/machine.c | 1 - hw/i386/acpi-build.c | 1 - hw/loongarch/acpi-build.c | 1 - hw/misc/macio/cuda.c | 1 - hw/misc/macio/pmu.c | 1 - hw/net/xilinx_axienet.c | 1 - hw/ppc/ppc405_uc.c | 2 -- hw/ppc/ppc440_bamboo.c | 1 - hw/ppc/spapr_drc.c | 1 - hw/rdma/vmw/pvrdma_dev_ring.c | 1 - hw/remote/machine.c | 1 - hw/remote/remote-obj.c | 1 - hw/rtc/mc146818rtc.c | 1 - hw/s390x/virtio-ccw-serial.c | 1 - migration/postcopy-ram.c | 2 -- softmmu/dirtylimit.c | 1 - softmmu/runstate.c | 1 - softmmu/vl.c | 1 - target/loongarch/translate.c | 1 - target/mips/tcg/translate.c | 1 - target/nios2/translate.c | 2 -- tests/unit/test-cutils.c | 1 - ui/gtk.c | 1 - util/oslib-posix.c | 4 ---- 33 files changed, 39 deletions(-) diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index 7812e516a5..1952cb984d 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -30,7 +30,6 @@ #include "hw/timer/imx_gpt.h" #include "hw/timer/imx_epit.h" #include "hw/i2c/imx_i2c.h" -#include "hw/gpio/imx_gpio.h" #include "hw/sd/sdhci.h" #include "hw/ssi/imx_spi.h" #include "hw/net/imx_fec.h" diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 4e5e071864..355bd8ea83 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -32,7 +32,6 @@ #include "hw/timer/imx_gpt.h" #include "hw/timer/imx_epit.h" #include "hw/i2c/imx_i2c.h" -#include "hw/gpio/imx_gpio.h" #include "hw/sd/sdhci.h" #include "hw/ssi/imx_spi.h" #include "hw/net/imx_fec.h" diff --git a/backends/tpm/tpm_emulator.c b/backends/tpm/tpm_emulator.c index 49cc3d749d..2b440d2c9a 100644 --- a/backends/tpm/tpm_emulator.c +++ b/backends/tpm/tpm_emulator.c @@ -35,7 +35,6 @@ #include "sysemu/runstate.h" #include "sysemu/tpm_backend.h" #include "sysemu/tpm_util.h" -#include "sysemu/runstate.h" #include "tpm_int.h" #include "tpm_ioctl.h" #include "migration/blocker.h" diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 0a81f1ad93..df39f91294 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -35,7 +35,6 @@ #include "sysemu/xen.h" #include "qapi/error.h" #include "qemu/range.h" -#include "hw/acpi/pcihp.h" #include "hw/acpi/cpu_hotplug.h" #include "hw/acpi/cpu.h" #include "hw/hotplug.h" diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c index c502c8c62a..4161f559a7 100644 --- a/hw/alpha/dp264.c +++ b/hw/alpha/dp264.c @@ -18,7 +18,6 @@ #include "net/net.h" #include "qemu/cutils.h" #include "qemu/datadir.h" -#include "net/net.h" static uint64_t cpu_alpha_superpage_to_phys(void *opaque, uint64_t addr) { diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ea2413a0ba..d3849d7233 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -33,7 +33,6 @@ #include "qemu/units.h" #include "qemu/option.h" #include "monitor/qdev.h" -#include "qapi/error.h" #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "hw/arm/primecell.h" diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 57276e1506..69b1b99e93 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -22,7 +22,6 @@ #include "hw/misc/unimp.h" #include "hw/arm/xlnx-versal.h" #include "qemu/log.h" -#include "hw/sysbus.h" #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 0cbc2fb4cb..d11406eada 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -45,7 +45,6 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/bitops.h" -#include "qemu/error-report.h" #include "qemu/host-utils.h" #include "qemu/log.h" #include "qemu/module.h" diff --git a/hw/core/machine.c b/hw/core/machine.c index 616f3a207c..67cf9f9dcd 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -39,7 +39,6 @@ #include "exec/confidential-guest-support.h" #include "hw/virtio/virtio.h" #include "hw/virtio/virtio-pci.h" -#include "qom/object_interfaces.h" GlobalProperty hw_compat_7_2[] = {}; const size_t hw_compat_7_2_len = G_N_ELEMENTS(hw_compat_7_2); diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index de1cc7ab71..7ac68c943f 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -28,7 +28,6 @@ #include "qapi/error.h" #include "net/net.h" #include "qemu/log.h" -#include "net/net.h" #define MIN_SEABIOS_HPPA_VERSION 6 /* require at least this fw version */ diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 127c4e2d50..14f6f75454 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -76,7 +76,6 @@ #include "hw/acpi/hmat.h" #include "hw/acpi/viot.h" -#include "hw/acpi/cxl.h" #include CONFIG_DEVICES diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c index c2b237736d..f551296a0e 100644 --- a/hw/loongarch/acpi-build.c +++ b/hw/loongarch/acpi-build.c @@ -22,7 +22,6 @@ /* Supported chipsets: */ #include "hw/pci-host/ls7a.h" #include "hw/loongarch/virt.h" -#include "hw/acpi/aml-build.h" #include "hw/acpi/utils.h" #include "hw/acpi/pci.h" diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index 853e88bfed..29a8e5ed19 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -30,7 +30,6 @@ #include "hw/input/adb.h" #include "hw/misc/mos6522.h" #include "hw/misc/macio/cuda.h" -#include "qapi/error.h" #include "qemu/timer.h" #include "sysemu/runstate.h" #include "sysemu/rtc.h" diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c index 97ef8c771b..5a788e595a 100644 --- a/hw/misc/macio/pmu.c +++ b/hw/misc/macio/pmu.c @@ -36,7 +36,6 @@ #include "hw/misc/mos6522.h" #include "hw/misc/macio/gpio.h" #include "hw/misc/macio/pmu.h" -#include "qapi/error.h" #include "qemu/timer.h" #include "sysemu/runstate.h" #include "sysemu/rtc.h" diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index 990ff3a1c2..673af7da26 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -31,7 +31,6 @@ #include "net/net.h" #include "net/checksum.h" -#include "hw/hw.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/stream.h" diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index c973cfb04e..0cc68178ad 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -38,8 +38,6 @@ #include "sysemu/sysemu.h" #include "exec/address-spaces.h" #include "hw/intc/ppc-uic.h" -#include "hw/qdev-properties.h" -#include "qapi/error.h" #include "trace.h" /*****************************************************************************/ diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index 81d71adf34..2880c81cb1 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -13,7 +13,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" -#include "qemu/error-report.h" #include "qemu/datadir.h" #include "qemu/error-report.h" #include "net/net.h" diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c index 4923435a8b..b5c400a94d 100644 --- a/hw/ppc/spapr_drc.c +++ b/hw/ppc/spapr_drc.c @@ -17,7 +17,6 @@ #include "hw/ppc/spapr_drc.h" #include "qom/object.h" #include "migration/vmstate.h" -#include "qapi/error.h" #include "qapi/qapi-events-qdev.h" #include "qapi/visitor.h" #include "qemu/error-report.h" diff --git a/hw/rdma/vmw/pvrdma_dev_ring.c b/hw/rdma/vmw/pvrdma_dev_ring.c index 598e6adc5e..30ce22a5be 100644 --- a/hw/rdma/vmw/pvrdma_dev_ring.c +++ b/hw/rdma/vmw/pvrdma_dev_ring.c @@ -14,7 +14,6 @@ */ #include "qemu/osdep.h" -#include "qemu/cutils.h" #include "hw/pci/pci.h" #include "cpu.h" #include "qemu/cutils.h" diff --git a/hw/remote/machine.c b/hw/remote/machine.c index 519f855ec1..fdc6c441bb 100644 --- a/hw/remote/machine.c +++ b/hw/remote/machine.c @@ -22,7 +22,6 @@ #include "hw/remote/iohub.h" #include "hw/remote/iommu.h" #include "hw/qdev-core.h" -#include "hw/remote/iommu.h" #include "hw/remote/vfio-user-obj.h" #include "hw/pci/msi.h" diff --git a/hw/remote/remote-obj.c b/hw/remote/remote-obj.c index 333e5ac443..65b6f7cc86 100644 --- a/hw/remote/remote-obj.c +++ b/hw/remote/remote-obj.c @@ -12,7 +12,6 @@ #include "qemu/error-report.h" #include "qemu/notify.h" #include "qom/object_interfaces.h" -#include "hw/qdev-core.h" #include "io/channel.h" #include "hw/qdev-core.h" #include "hw/remote/machine.h" diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c index bc1192b7ae..ba612a151d 100644 --- a/hw/rtc/mc146818rtc.c +++ b/hw/rtc/mc146818rtc.c @@ -43,7 +43,6 @@ #include "qapi/error.h" #include "qapi/qapi-events-misc.h" #include "qapi/visitor.h" -#include "hw/rtc/mc146818rtc_regs.h" //#define DEBUG_CMOS //#define DEBUG_COALESCED diff --git a/hw/s390x/virtio-ccw-serial.c b/hw/s390x/virtio-ccw-serial.c index bf8057880f..8f8d2302f8 100644 --- a/hw/s390x/virtio-ccw-serial.c +++ b/hw/s390x/virtio-ccw-serial.c @@ -15,7 +15,6 @@ #include "hw/qdev-properties.h" #include "hw/virtio/virtio-serial.h" #include "virtio-ccw.h" -#include "hw/virtio/virtio-serial.h" #define TYPE_VIRTIO_SERIAL_CCW "virtio-serial-ccw" OBJECT_DECLARE_SIMPLE_TYPE(VirtioSerialCcw, VIRTIO_SERIAL_CCW) diff --git a/migration/postcopy-ram.c b/migration/postcopy-ram.c index b9a37ef255..8b7d1af75d 100644 --- a/migration/postcopy-ram.c +++ b/migration/postcopy-ram.c @@ -17,7 +17,6 @@ */ #include "qemu/osdep.h" -#include "qemu/rcu.h" #include "qemu/madvise.h" #include "exec/target_page.h" #include "migration.h" @@ -34,7 +33,6 @@ #include "hw/boards.h" #include "exec/ramblock.h" #include "socket.h" -#include "qemu-file.h" #include "yank_functions.h" #include "tls.h" diff --git a/softmmu/dirtylimit.c b/softmmu/dirtylimit.c index 12668555f2..c56f0f58c8 100644 --- a/softmmu/dirtylimit.c +++ b/softmmu/dirtylimit.c @@ -11,7 +11,6 @@ */ #include "qemu/osdep.h" -#include "qapi/error.h" #include "qemu/main-loop.h" #include "qapi/qapi-commands-migration.h" #include "qapi/qmp/qdict.h" diff --git a/softmmu/runstate.c b/softmmu/runstate.c index cab9f6fc07..f9ad88e6a7 100644 --- a/softmmu/runstate.c +++ b/softmmu/runstate.c @@ -41,7 +41,6 @@ #include "qapi/qapi-commands-run-state.h" #include "qapi/qapi-events-run-state.h" #include "qemu/error-report.h" -#include "qemu/log.h" #include "qemu/job.h" #include "qemu/log.h" #include "qemu/module.h" diff --git a/softmmu/vl.c b/softmmu/vl.c index 5355a7fe5a..b2ee3fee3f 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -129,7 +129,6 @@ #include "qapi/qapi-commands-misc.h" #include "qapi/qapi-visit-qom.h" #include "qapi/qapi-commands-ui.h" -#include "qapi/qmp/qdict.h" #include "block/qdict.h" #include "qapi/qmp/qerror.h" #include "sysemu/iothread.h" diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 38ced69803..72a6275665 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -12,7 +12,6 @@ #include "exec/helper-proto.h" #include "exec/helper-gen.h" -#include "exec/translator.h" #include "exec/log.h" #include "qemu/qemu-print.h" #include "fpu/softfloat.h" diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 624e6b7786..aa12bb708a 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -32,7 +32,6 @@ #include "semihosting/semihost.h" #include "trace.h" -#include "exec/translator.h" #include "exec/log.h" #include "qemu/qemu-print.h" #include "fpu_helper.h" diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 4db8b47744..7aee65a089 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -938,8 +938,6 @@ static const char * const cr_regnames[NUM_CR_REGS] = { }; #endif -#include "exec/gen-icount.h" - /* generate intermediate code for basic block 'tb'. */ static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { diff --git a/tests/unit/test-cutils.c b/tests/unit/test-cutils.c index 2126b46391..3c4f875420 100644 --- a/tests/unit/test-cutils.c +++ b/tests/unit/test-cutils.c @@ -26,7 +26,6 @@ */ #include "qemu/osdep.h" -#include "qemu/units.h" #include "qemu/cutils.h" #include "qemu/units.h" diff --git a/ui/gtk.c b/ui/gtk.c index 4817623c8f..7f752d8b7d 100644 --- a/ui/gtk.c +++ b/ui/gtk.c @@ -53,7 +53,6 @@ #include #include "trace.h" -#include "qemu/cutils.h" #include "ui/input.h" #include "sysemu/runstate.h" #include "sysemu/sysemu.h" diff --git a/util/oslib-posix.c b/util/oslib-posix.c index fd03fd32c8..77d882e681 100644 --- a/util/oslib-posix.c +++ b/util/oslib-posix.c @@ -59,10 +59,6 @@ #include "qemu/mmap-alloc.h" -#ifdef CONFIG_DEBUG_STACK_USAGE -#include "qemu/error-report.h" -#endif - #define MAX_MEM_PREALLOC_THREAD_COUNT 16 struct MemsetThread; -- 2.39.0 From MAILER-DAEMON Thu Jan 19 02:01:09 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIOv7-0006xx-0v for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 02:01:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps 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imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 12/19] target/hexagon: Clean up includes Date: Thu, 19 Jan 2023 07:59:52 +0100 Message-Id: <20230119065959.3104012-13-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.4 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:00:32 -0000 Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Changes to standalone programs dropped, because I can't tell whether them not using qemu/osdep.h is intentional: target/hexagon/gen_dectree_import.c target/hexagon/gen_semantics.c target/hexagon/idef-parser/idef-parser.h target/hexagon/idef-parser/parser-helpers.c target/hexagon/idef-parser/parser-helpers.h Signed-off-by: Markus Armbruster --- target/hexagon/hex_arch_types.h | 1 - target/hexagon/mmvec/macros.h | 1 - 2 files changed, 2 deletions(-) diff --git a/target/hexagon/hex_arch_types.h b/target/hexagon/hex_arch_types.h index 885f68f760..52a7f2b2f3 100644 --- a/target/hexagon/hex_arch_types.h +++ b/target/hexagon/hex_arch_types.h @@ -18,7 +18,6 @@ #ifndef HEXAGON_HEX_ARCH_TYPES_H #define HEXAGON_HEX_ARCH_TYPES_H -#include "qemu/osdep.h" #include "mmvec/mmvec.h" #include "qemu/int128.h" diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index 8c864e8c68..1201d778d0 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -18,7 +18,6 @@ #ifndef HEXAGON_MMVEC_MACROS_H #define HEXAGON_MMVEC_MACROS_H -#include "qemu/osdep.h" #include "qemu/host-utils.h" #include "arch.h" #include "mmvec/system_ext_mmvec.h" -- 2.39.0 From MAILER-DAEMON Thu Jan 19 02:01:09 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIOv7-0006yV-CN for mharc-qemu-riscv@gnu.org; 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Thu, 19 Jan 2023 02:00:04 -0500 X-MC-Unique: bVRH3SPrNY2cI3zHhj89iQ-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 5E3AF183B3C1; Thu, 19 Jan 2023 07:00:03 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 228A6140EBF6; Thu, 19 Jan 2023 07:00:03 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 5398421E6600; Thu, 19 Jan 2023 07:59:59 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 07/19] hw/input: Clean up includes Date: Thu, 19 Jan 2023 07:59:47 +0100 Message-Id: <20230119065959.3104012-8-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:00:32 -0000 Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster --- include/hw/input/pl050.h | 1 - hw/input/tsc210x.c | 1 - 2 files changed, 2 deletions(-) diff --git a/include/hw/input/pl050.h b/include/hw/input/pl050.h index 89ec4fafc9..4cb8985f31 100644 --- a/include/hw/input/pl050.h +++ b/include/hw/input/pl050.h @@ -10,7 +10,6 @@ #ifndef HW_PL050_H #define HW_PL050_H -#include "qemu/osdep.h" #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/input/ps2.h" diff --git a/hw/input/tsc210x.c b/hw/input/tsc210x.c index fdd5ff87d9..7eae5989f7 100644 --- a/hw/input/tsc210x.c +++ b/hw/input/tsc210x.c @@ -20,7 +20,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "hw/hw.h" #include "audio/audio.h" #include "qemu/timer.h" -- 2.39.0 From MAILER-DAEMON Thu Jan 19 02:01:10 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIOv8-0006z3-04 for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 02:01:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuX-0006Wr-AE for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:33 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuM-0008Ac-9i for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:32 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674111608; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=3Q6JawOwNUX79rDzr8EPQtv6xKDyu95x0CthaLOBjJY=; b=Z/haToSue7U6YwxbAv/qcFpoYNxK5aQ4DdMXmgjrUYG1lZ5KIkX4TkUlhMdg3iVW2iyD1K CguL2b4CKXji8GkJrC0MrRwaYwx+xq27vffcJHJA1CtdTeZpQn0r5CGBxCPgkLaxg5SRSl vOuwK4ckKtXW5Qq4eXv1OYALDciiSBY= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-65-aajyhcBPO_if6EqpbgRvHA-1; Thu, 19 Jan 2023 02:00:04 -0500 X-MC-Unique: aajyhcBPO_if6EqpbgRvHA-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 637BE80D0EB; Thu, 19 Jan 2023 07:00:03 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 2CA0A492B01; Thu, 19 Jan 2023 07:00:03 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 568B721E6821; Thu, 19 Jan 2023 07:59:59 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 08/19] hw/tricore: Clean up includes Date: Thu, 19 Jan 2023 07:59:48 +0100 Message-Id: <20230119065959.3104012-9-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:00:33 -0000 Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster --- include/hw/tricore/triboard.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/hw/tricore/triboard.h b/include/hw/tricore/triboard.h index 094c8bd563..4fdd2d7d97 100644 --- a/include/hw/tricore/triboard.h +++ b/include/hw/tricore/triboard.h @@ -18,7 +18,6 @@ * License along with this library; if not, see . */ -#include "qemu/osdep.h" #include "qapi/error.h" #include "hw/boards.h" #include "sysemu/sysemu.h" -- 2.39.0 From MAILER-DAEMON Thu Jan 19 02:01:13 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIOvB-00072V-Go for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 02:01:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuY-0006Xc-Gr for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:35 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuM-0008CJ-SV for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674111610; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PM2W6BJvS1SCT2/L4hzmf86UBM6uCRYswhKFoahaeoE=; b=gAZkPldxUKVjOPST6FDgpvqIwMsM9MhD14Dvccm8XzN9FLZjnPClOq26QoWXOIG+rIrm+K qRyAO01rU1Oc9yoEA7j8U4fzD//YHL9ZM7dTgovyO1VTEUMjIt0uM2L/+UTwxf1tnnSj8I L/QkZBgQr8ZIoRABUvq4bxRjv8t/rMk= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-605-nYu3z3D-OOGiJSytUB5CKQ-1; Thu, 19 Jan 2023 02:00:06 -0500 X-MC-Unique: nYu3z3D-OOGiJSytUB5CKQ-1 Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.rdu2.redhat.com [10.11.54.2]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 15EE4101A55E; Thu, 19 Jan 2023 07:00:05 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C498040C6EC4; Thu, 19 Jan 2023 07:00:04 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 6FB0A21E5DE0; Thu, 19 Jan 2023 07:59:59 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 16/19] Fix non-first inclusions of qemu/osdep.h Date: Thu, 19 Jan 2023 07:59:56 +0100 Message-Id: <20230119065959.3104012-17-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.2 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:00:35 -0000 This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster --- audio/sndioaudio.c | 2 +- backends/hostmem-epc.c | 2 +- block/export/vduse-blk.c | 2 +- hw/hyperv/syndbg.c | 2 +- util/async-teardown.c | 12 ++++-------- 5 files changed, 8 insertions(+), 12 deletions(-) diff --git a/audio/sndioaudio.c b/audio/sndioaudio.c index 632b0e3825..3fde01fdbd 100644 --- a/audio/sndioaudio.c +++ b/audio/sndioaudio.c @@ -14,9 +14,9 @@ * to recording, which is what guest systems expect. */ +#include "qemu/osdep.h" #include #include -#include "qemu/osdep.h" #include "qemu/main-loop.h" #include "audio.h" #include "trace.h" diff --git a/backends/hostmem-epc.c b/backends/hostmem-epc.c index 037292d267..4e162d6789 100644 --- a/backends/hostmem-epc.c +++ b/backends/hostmem-epc.c @@ -9,9 +9,9 @@ * This work is licensed under the terms of the GNU GPL, version 2 or later. * See the COPYING file in the top-level directory. */ -#include #include "qemu/osdep.h" +#include #include "qom/object_interfaces.h" #include "qapi/error.h" #include "sysemu/hostmem.h" diff --git a/block/export/vduse-blk.c b/block/export/vduse-blk.c index 350d6fdaf0..f7ae44e3ce 100644 --- a/block/export/vduse-blk.c +++ b/block/export/vduse-blk.c @@ -10,9 +10,9 @@ * later. See the COPYING file in the top-level directory. */ +#include "qemu/osdep.h" #include -#include "qemu/osdep.h" #include "qapi/error.h" #include "block/export.h" #include "qemu/error-report.h" diff --git a/hw/hyperv/syndbg.c b/hw/hyperv/syndbg.c index 16d04cfdc6..94fe1b534b 100644 --- a/hw/hyperv/syndbg.c +++ b/hw/hyperv/syndbg.c @@ -5,8 +5,8 @@ * See the COPYING file in the top-level directory. */ -#include "qemu/ctype.h" #include "qemu/osdep.h" +#include "qemu/ctype.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" #include "qemu/sockets.h" diff --git a/util/async-teardown.c b/util/async-teardown.c index 62bfce1b3c..62cdeb0f20 100644 --- a/util/async-teardown.c +++ b/util/async-teardown.c @@ -10,16 +10,12 @@ * option) any later version. See the COPYING file in the top-level directory. * */ -#include -#include -#include -#include -#include -#include -#include -#include #include "qemu/osdep.h" +#include +#include +#include + #include "qemu/async-teardown.h" #ifdef _SC_THREAD_STACK_MIN -- 2.39.0 From MAILER-DAEMON Thu Jan 19 02:01:14 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIOvB-000734-V0 for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 02:01:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuZ-0006Yu-Rt for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:37 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuM-0008Al-Vs for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674111608; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=q7Aa4H8NxI3BfcTgY65K+THkgcyzhdU7KeXHSHDpbkE=; b=MJQvM0VG29xtmV+pgKVthHiIto91bsiL4cFpSKxU67p/e1zoPsgUdW9nYz93Hx4wtuYdpC vR5DuKQz/kQn7pi+2CihSDlTHiMQMGF1ZDABzNncY+0BPDtry7bAjx3NLALlMv6j09xyn4 yDhusL7pjtchDko0w8GmPNzZSxi/srw= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-65-bVDpfzNVOwS1e93czWbLvQ-1; Thu, 19 Jan 2023 02:00:04 -0500 X-MC-Unique: bVDpfzNVOwS1e93czWbLvQ-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 5E23A1C05AC8; Thu, 19 Jan 2023 07:00:03 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 229FA1415108; Thu, 19 Jan 2023 07:00:03 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 509DC21E66A4; Thu, 19 Jan 2023 07:59:59 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 06/19] hw/cxl: Clean up includes Date: Thu, 19 Jan 2023 07:59:46 +0100 Message-Id: <20230119065959.3104012-7-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:00:37 -0000 Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster --- include/hw/cxl/cxl_component.h | 2 -- include/hw/cxl/cxl_host.h | 1 - include/hw/cxl/cxl_pci.h | 1 - 3 files changed, 4 deletions(-) diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h index 5dca21e95b..692d7a5507 100644 --- a/include/hw/cxl/cxl_component.h +++ b/include/hw/cxl/cxl_component.h @@ -15,9 +15,7 @@ #define CXL2_COMPONENT_CM_REGION_SIZE 0x1000 #define CXL2_COMPONENT_BLOCK_SIZE 0x10000 -#include "qemu/compiler.h" #include "qemu/range.h" -#include "qemu/typedefs.h" #include "hw/cxl/cxl_cdat.h" #include "hw/register.h" #include "qapi/error.h" diff --git a/include/hw/cxl/cxl_host.h b/include/hw/cxl/cxl_host.h index a1b662ce40..c9bc9c7c50 100644 --- a/include/hw/cxl/cxl_host.h +++ b/include/hw/cxl/cxl_host.h @@ -7,7 +7,6 @@ * COPYING file in the top-level directory. */ -#include "qemu/osdep.h" #include "hw/cxl/cxl.h" #include "hw/boards.h" diff --git a/include/hw/cxl/cxl_pci.h b/include/hw/cxl/cxl_pci.h index 01e15ed5b4..407be95b9e 100644 --- a/include/hw/cxl/cxl_pci.h +++ b/include/hw/cxl/cxl_pci.h @@ -10,7 +10,6 @@ #ifndef CXL_PCI_H #define CXL_PCI_H -#include "qemu/compiler.h" #define CXL_VENDOR_ID 0x1e98 -- 2.39.0 From MAILER-DAEMON Thu Jan 19 02:01:14 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIOvC-00073M-3l for mharc-qemu-riscv@gnu.org; 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Thu, 19 Jan 2023 02:00:04 -0500 X-MC-Unique: XvfwCC2uPKeV3vVc_zCOJA-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 84854183B3CA; Thu, 19 Jan 2023 07:00:03 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 4B2231415113; Thu, 19 Jan 2023 07:00:03 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 5FF7A21E6608; Thu, 19 Jan 2023 07:59:59 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 11/19] net: Clean up includes Date: Thu, 19 Jan 2023 07:59:51 +0100 Message-Id: <20230119065959.3104012-12-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:00:37 -0000 Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster --- net/vmnet_int.h | 1 - 1 file changed, 1 deletion(-) diff --git a/net/vmnet_int.h b/net/vmnet_int.h index adf6e8c20d..d0b90594f2 100644 --- a/net/vmnet_int.h +++ b/net/vmnet_int.h @@ -10,7 +10,6 @@ #ifndef VMNET_INT_H #define VMNET_INT_H -#include "qemu/osdep.h" #include "vmnet_int.h" #include "clients.h" -- 2.39.0 From MAILER-DAEMON Thu Jan 19 02:01:10 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIOv8-0006zQ-AP for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 02:01:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOua-0006Z3-JM for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:37 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIOuN-0008Cr-01 for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 02:00:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674111612; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kurcA10CDa8OBC3t8KOxBZkJDy9234LfSV2y7uqUTw0=; b=dwmpuELMqoSrkdxf99jZJvr8Ld3Q5kIw+k8tVvZFkMToPhiy+FYkKv/UR17wca5xR5H6X8 N/fARzkrn7yReeZesJHLoLpWO2hhQav/9XUxTxp//rMUolsGts4AasljsvX+Ox5bge2a7Y OshVVbfztlint7F2yqOf1xaYz81US4w= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-375-QSb5smJkMiyyp6d3PZ77NQ-1; Thu, 19 Jan 2023 02:00:06 -0500 X-MC-Unique: QSb5smJkMiyyp6d3PZ77NQ-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 422AE101B42B; Thu, 19 Jan 2023 07:00:05 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C6C7A140EBF6; Thu, 19 Jan 2023 07:00:04 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 730C421E5A69; Thu, 19 Jan 2023 07:59:59 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v4 17/19] Don't include headers already included by qemu/osdep.h Date: Thu, 19 Jan 2023 07:59:57 +0100 Message-Id: <20230119065959.3104012-18-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:00:37 -0000 This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster --- backends/tpm/tpm_ioctl.h | 2 -- fsdev/p9array.h | 2 -- include/hw/misc/aspeed_lpc.h | 2 -- include/hw/pci/pcie_doe.h | 1 - include/qemu/async-teardown.h | 2 -- include/qemu/dbus.h | 1 - include/qemu/host-utils.h | 1 - include/sysemu/event-loop-base.h | 1 - accel/tcg/cpu-exec.c | 1 - hw/9pfs/9p.c | 2 -- hw/display/virtio-gpu-udmabuf.c | 1 - hw/i2c/pmbus_device.c | 1 - hw/remote/proxy-memory-listener.c | 1 - hw/sensor/adm1272.c | 1 - hw/usb/dev-storage-bot.c | 1 - hw/usb/dev-storage-classic.c | 1 - softmmu/vl.c | 2 -- tcg/tci.c | 1 - tests/unit/test-seccomp.c | 1 - ui/udmabuf.c | 1 - util/main-loop.c | 1 - util/oslib-posix.c | 2 -- 22 files changed, 29 deletions(-) diff --git a/backends/tpm/tpm_ioctl.h b/backends/tpm/tpm_ioctl.h index e506ef5160..b1d31768a6 100644 --- a/backends/tpm/tpm_ioctl.h +++ b/backends/tpm/tpm_ioctl.h @@ -12,8 +12,6 @@ # define __USE_LINUX_IOCTL_DEFS #endif -#include -#include #ifndef _WIN32 #include #include diff --git a/fsdev/p9array.h b/fsdev/p9array.h index 90e83a7c7b..50a1b15fe9 100644 --- a/fsdev/p9array.h +++ b/fsdev/p9array.h @@ -27,8 +27,6 @@ #ifndef QEMU_P9ARRAY_H #define QEMU_P9ARRAY_H -#include "qemu/compiler.h" - /** * P9Array provides a mechanism to access arrays in common C-style (e.g. by * square bracket [] operator) in conjunction with reference variables that diff --git a/include/hw/misc/aspeed_lpc.h b/include/hw/misc/aspeed_lpc.h index fd228731d2..fa398959af 100644 --- a/include/hw/misc/aspeed_lpc.h +++ b/include/hw/misc/aspeed_lpc.h @@ -12,8 +12,6 @@ #include "hw/sysbus.h" -#include - #define TYPE_ASPEED_LPC "aspeed.lpc" #define ASPEED_LPC(obj) OBJECT_CHECK(AspeedLPCState, (obj), TYPE_ASPEED_LPC) diff --git a/include/hw/pci/pcie_doe.h b/include/hw/pci/pcie_doe.h index ba4d8b03bd..87dc17dcef 100644 --- a/include/hw/pci/pcie_doe.h +++ b/include/hw/pci/pcie_doe.h @@ -11,7 +11,6 @@ #define PCIE_DOE_H #include "qemu/range.h" -#include "qemu/typedefs.h" #include "hw/register.h" /* diff --git a/include/qemu/async-teardown.h b/include/qemu/async-teardown.h index 092e7a37e7..b281da005b 100644 --- a/include/qemu/async-teardown.h +++ b/include/qemu/async-teardown.h @@ -13,8 +13,6 @@ #ifndef QEMU_ASYNC_TEARDOWN_H #define QEMU_ASYNC_TEARDOWN_H -#include "config-host.h" - #ifdef CONFIG_LINUX void init_async_teardown(void); #endif diff --git a/include/qemu/dbus.h b/include/qemu/dbus.h index 08f00dfd53..81d3de8a5a 100644 --- a/include/qemu/dbus.h +++ b/include/qemu/dbus.h @@ -15,7 +15,6 @@ #include "qom/object.h" #include "chardev/char.h" #include "qemu/notify.h" -#include "qemu/typedefs.h" /* glib/gio 2.68 */ #define DBUS_METHOD_INVOCATION_HANDLED TRUE diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index 88d476161c..3ce62bf4a5 100644 --- a/include/qemu/host-utils.h +++ b/include/qemu/host-utils.h @@ -30,7 +30,6 @@ #ifndef HOST_UTILS_H #define HOST_UTILS_H -#include "qemu/compiler.h" #include "qemu/bswap.h" #include "qemu/int128.h" diff --git a/include/sysemu/event-loop-base.h b/include/sysemu/event-loop-base.h index 2748bf6ae1..a6c24f1351 100644 --- a/include/sysemu/event-loop-base.h +++ b/include/sysemu/event-loop-base.h @@ -14,7 +14,6 @@ #include "qom/object.h" #include "block/aio.h" -#include "qemu/typedefs.h" #define TYPE_EVENT_LOOP_BASE "event-loop-base" OBJECT_DECLARE_TYPE(EventLoopBase, EventLoopBaseClass, diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 8927092537..dd8f54a415 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -28,7 +28,6 @@ #include "exec/exec-all.h" #include "tcg/tcg.h" #include "qemu/atomic.h" -#include "qemu/compiler.h" #include "qemu/timer.h" #include "qemu/rcu.h" #include "exec/log.h" diff --git a/hw/9pfs/9p.c b/hw/9pfs/9p.c index 072cf67956..9621ec1341 100644 --- a/hw/9pfs/9p.c +++ b/hw/9pfs/9p.c @@ -19,8 +19,6 @@ #include "qemu/osdep.h" #ifdef CONFIG_LINUX #include -#else -#include #endif #include #include "hw/virtio/virtio.h" diff --git a/hw/display/virtio-gpu-udmabuf.c b/hw/display/virtio-gpu-udmabuf.c index 8bdf4bac6e..847fa4c0cc 100644 --- a/hw/display/virtio-gpu-udmabuf.c +++ b/hw/display/virtio-gpu-udmabuf.c @@ -21,7 +21,6 @@ #include "exec/ramblock.h" #include "sysemu/hostmem.h" #include -#include #include #include "qemu/memfd.h" #include "standard-headers/linux/udmabuf.h" diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c index 4071a88cfc..c3d6046784 100644 --- a/hw/i2c/pmbus_device.c +++ b/hw/i2c/pmbus_device.c @@ -8,7 +8,6 @@ #include "qemu/osdep.h" #include -#include #include "hw/i2c/pmbus_device.h" #include "migration/vmstate.h" #include "qemu/module.h" diff --git a/hw/remote/proxy-memory-listener.c b/hw/remote/proxy-memory-listener.c index eb9918fe72..18d96a1d04 100644 --- a/hw/remote/proxy-memory-listener.c +++ b/hw/remote/proxy-memory-listener.c @@ -8,7 +8,6 @@ #include "qemu/osdep.h" -#include "qemu/compiler.h" #include "qemu/int128.h" #include "qemu/range.h" #include "exec/memory.h" diff --git a/hw/sensor/adm1272.c b/hw/sensor/adm1272.c index 7310c769be..8f4a1c2cd4 100644 --- a/hw/sensor/adm1272.c +++ b/hw/sensor/adm1272.c @@ -8,7 +8,6 @@ */ #include "qemu/osdep.h" -#include #include "hw/i2c/pmbus_device.h" #include "hw/irq.h" #include "migration/vmstate.h" diff --git a/hw/usb/dev-storage-bot.c b/hw/usb/dev-storage-bot.c index b24b3148c2..1e5c5c711f 100644 --- a/hw/usb/dev-storage-bot.c +++ b/hw/usb/dev-storage-bot.c @@ -8,7 +8,6 @@ */ #include "qemu/osdep.h" -#include "qemu/typedefs.h" #include "qapi/error.h" #include "hw/usb.h" #include "hw/usb/desc.h" diff --git a/hw/usb/dev-storage-classic.c b/hw/usb/dev-storage-classic.c index 00f25bade2..84d19752b5 100644 --- a/hw/usb/dev-storage-classic.c +++ b/hw/usb/dev-storage-classic.c @@ -8,7 +8,6 @@ */ #include "qemu/osdep.h" -#include "qemu/typedefs.h" #include "qapi/error.h" #include "qapi/visitor.h" #include "hw/usb.h" diff --git a/softmmu/vl.c b/softmmu/vl.c index 9177d95d4e..5355a7fe5a 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -136,8 +136,6 @@ #include "qemu/guest-random.h" #include "qemu/keyval.h" -#include "config-host.h" - #define MAX_VIRTIO_CONSOLES 1 typedef struct BlockdevOptionsQueueEntry { diff --git a/tcg/tci.c b/tcg/tci.c index 05a24163d3..e7ac74cab0 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -21,7 +21,6 @@ #include "exec/cpu_ldst.h" #include "tcg/tcg-op.h" #include "tcg/tcg-ldst.h" -#include "qemu/compiler.h" #include diff --git a/tests/unit/test-seccomp.c b/tests/unit/test-seccomp.c index 3d7771e46c..f02c79cafd 100644 --- a/tests/unit/test-seccomp.c +++ b/tests/unit/test-seccomp.c @@ -25,7 +25,6 @@ #include "qapi/error.h" #include "qemu/module.h" -#include #include static void test_seccomp_helper(const char *args, bool killed, diff --git a/ui/udmabuf.c b/ui/udmabuf.c index cebceb2610..cbf4357bb1 100644 --- a/ui/udmabuf.c +++ b/ui/udmabuf.c @@ -8,7 +8,6 @@ #include "qapi/error.h" #include "ui/console.h" -#include #include int udmabuf_fd(void) diff --git a/util/main-loop.c b/util/main-loop.c index 58f776a8c9..3c0f525192 100644 --- a/util/main-loop.c +++ b/util/main-loop.c @@ -33,7 +33,6 @@ #include "block/thread-pool.h" #include "qemu/error-report.h" #include "qemu/queue.h" -#include "qemu/compiler.h" #include "qom/object.h" #ifndef _WIN32 diff --git a/util/oslib-posix.c b/util/oslib-posix.c index 59a891b6a8..fd03fd32c8 100644 --- a/util/oslib-posix.c +++ b/util/oslib-posix.c @@ -40,7 +40,6 @@ #include "qemu/thread.h" #include #include "qemu/cutils.h" -#include "qemu/compiler.h" #include "qemu/units.h" #include "qemu/thread-context.h" @@ -50,7 +49,6 @@ #ifdef __FreeBSD__ #include -#include #include #include #endif -- 2.39.0 From MAILER-DAEMON Thu Jan 19 02:28:43 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIPLn-0002KW-Fp for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 02:28:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) 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qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: Re: completion timeouts with pin-based interrupts in QEMU hw/nvme Message-ID: References: <20230117160933.GB3091262@roeck-us.net> <20230117192115.GA2958104@roeck-us.net> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="b9PjqAhA9tYv0Qnk" Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=66.111.4.28; envelope-from=its@irrelevant.dk; helo=out4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 07:28:42 -0000 --b9PjqAhA9tYv0Qnk Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Jan 18 21:03, Keith Busch wrote: > On Thu, Jan 19, 2023 at 01:10:57PM +1000, Alistair Francis wrote: > > On Thu, Jan 19, 2023 at 12:44 PM Keith Busch wrote: > > > > > > Further up, it says the "interrupt gateway" is responsible for > > > forwarding new interrupt requests while the level remains asserted, b= ut > > > it doesn't look like anything is handling that, which essentially tur= ns > > > this into an edge interrupt. Am I missing something, or is this really > > > not being handled? > >=20 > > Yeah, that wouldn't be handled. In QEMU the PLIC relies on QEMUs > > internal GPIO lines to trigger an interrupt. So with the current setup > > we only support edge triggered interrupts. >=20 > Thanks for confirming! >=20 > Klaus, > I think we can justify introducing a work-around in the emulated device > now. My previous proposal with pci_irq_pulse() is no good since it does > assert+deassert, but it needs to be the other way around, so please > don't considert that one. >=20 > Also, we ought to revisit the intms/intmc usage in the linux driver for > threaded interrupts. +CC: qemu-riscv Keith, Thanks for digging into this! Yeah, you are probably right that we should only use the intms/intmc changes in the use_threaded_interrupts case, not in general. While my RFC patch does seem to "fix" this, it is just a workaround as your analysis indicate. --b9PjqAhA9tYv0Qnk Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCgAdFiEEUigzqnXi3OaiR2bATeGvMW1PDekFAmPI8R0ACgkQTeGvMW1P Den7Xwf/as8sQo8Blioh/lVMAozoftSiWaqZ4j1NZkaqDVAIy3Pv5tjDEVW62NTx O8zYegRxq52Iag48NGpvbeDY1nLJ050CyUKwrdb4VgqHOlmlSiHzqDIPV5I9AYck EM/2UNp9hGczLZtP+Zb4D+32ih+IUBcLpLUE1shr3zKB/y5rb/Y9fKksGBtCifBX +W6tiCm1v7IASYWtWNlZeJzfTLYcGIwWzqRtnq54I1Kfv6or71koCwNmQrUwt93L fHsPdNsbJIjIPCSGUvH5nYU7O9TYzbG1Vr93NxUC1X2FbQIsnAtchXuh31hRNYlH iqIAVkPtkHRNM+vce8uSGliwcLwDiw== =O9qQ -----END PGP SIGNATURE----- --b9PjqAhA9tYv0Qnk-- From MAILER-DAEMON Thu Jan 19 03:02:30 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIPsU-0008MH-6L for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 03:02:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIPsQ-0008Ll-9u; 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Thu, 19 Jan 2023 03:02:17 -0500 (EST) Date: Thu, 19 Jan 2023 09:02:15 +0100 From: Klaus Jensen To: Keith Busch Cc: Alistair Francis , Peter Maydell , Guenter Roeck , Jens Axboe , Christoph Hellwig , Sagi Grimberg , linux-nvme@lists.infradead.org, qemu-block@nongnu.org, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Subject: Re: completion timeouts with pin-based interrupts in QEMU hw/nvme Message-ID: References: <20230117192115.GA2958104@roeck-us.net> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="W4BUVAsMEMdcmc71" Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=66.111.4.28; envelope-from=its@irrelevant.dk; helo=out4-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 08:02:28 -0000 --W4BUVAsMEMdcmc71 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Jan 19 08:28, Klaus Jensen wrote: > On Jan 18 21:03, Keith Busch wrote: > > On Thu, Jan 19, 2023 at 01:10:57PM +1000, Alistair Francis wrote: > > > On Thu, Jan 19, 2023 at 12:44 PM Keith Busch wrot= e: > > > > > > > > Further up, it says the "interrupt gateway" is responsible for > > > > forwarding new interrupt requests while the level remains asserted,= but > > > > it doesn't look like anything is handling that, which essentially t= urns > > > > this into an edge interrupt. Am I missing something, or is this rea= lly > > > > not being handled? > > >=20 > > > Yeah, that wouldn't be handled. In QEMU the PLIC relies on QEMUs > > > internal GPIO lines to trigger an interrupt. So with the current setup > > > we only support edge triggered interrupts. > >=20 > > Thanks for confirming! > >=20 > > Klaus, > > I think we can justify introducing a work-around in the emulated device > > now. My previous proposal with pci_irq_pulse() is no good since it does > > assert+deassert, but it needs to be the other way around, so please > > don't considert that one. > >=20 > > Also, we ought to revisit the intms/intmc usage in the linux driver for > > threaded interrupts. >=20 > +CC: qemu-riscv >=20 > Keith, >=20 > Thanks for digging into this! >=20 > Yeah, you are probably right that we should only use the intms/intmc > changes in the use_threaded_interrupts case, not in general. While my > RFC patch does seem to "fix" this, it is just a workaround as your > analysis indicate. +CC: Philippe, I am observing these timeouts/aborts on mips as well, so I guess that emulation could suffer from the same issue? --W4BUVAsMEMdcmc71 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQEzBAEBCgAdFiEEUigzqnXi3OaiR2bATeGvMW1PDekFAmPI+QYACgkQTeGvMW1P DekHAwf+Ki1LlCBgmoe95m0vajU7TuDu1kMglgpZ9t7UsBwGa88syocxbt0Xbgi8 9EvIPkncL1hlzzimo/tFa4Ukr5qiCucctT9xW37x2EWpMOk8Dv1Vo3W0pC9X6Apx nASE5/LGq/hH1IhnewMKPwABXfpd/OCiNnlkbYtp7dQhk9Yls3WoyASZVnXAKk4P Gu8nsBRUutZT1VEjOIv8GYwQwaJ5IHEWULTndsiQZge/vWKgHLev3xDfOtKXKsmw mhZm9n1CUZBH2dF9hZCfxGqp1TpWZXKuH5rpw3wcLOFShd8CznI7PvtqNodfeVTo fveeCWF7UH05j2gpTGQjY1wKLvjxbA== =ZriN -----END PGP SIGNATURE----- --W4BUVAsMEMdcmc71-- From MAILER-DAEMON Thu Jan 19 04:20:29 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIR5w-0003Sw-Kk for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 04:20:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIR5t-0003Ro-S8 for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 04:20:25 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIR5s-0005gn-1g for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 04:20:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674120023; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=AJAH+PtgDJ2Ku6bGCKJxTD3hj9E448yvnHDUAJu5nvg=; b=KSN0owcrhr+Xr6WuO0WwlP6UEhu+KzpjrCos3O8EmsPSCoAlW2IcOtmrdlCTwQ65VMAYc2 Er/lH2hxsDuQqekNV9c4uEbcnQiGASiB7RhVjgfl29FUZNWUJXNN3EBFWNStnj8tuhcdAo d1ooi13VWs0w/VMoYzF4T/huzC+MJmE= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-627-oR98r5VaNw2EJ9lf181YHA-1; Thu, 19 Jan 2023 04:20:19 -0500 X-MC-Unique: oR98r5VaNw2EJ9lf181YHA-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 0CCD0185A78B; Thu, 19 Jan 2023 09:20:18 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 587FB1121315; Thu, 19 Jan 2023 09:20:17 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 2612321E6A28; Thu, 19 Jan 2023 10:20:16 +0100 (CET) From: Markus Armbruster To: Markus Armbruster Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 00/19] Clean up includes References: <20230119065959.3104012-1-armbru@redhat.com> Date: Thu, 19 Jan 2023 10:20:16 +0100 In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> (Markus Armbruster's message of "Thu, 19 Jan 2023 07:59:40 +0100") Message-ID: <87k01ix4mn.fsf@pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 09:20:26 -0000 Markus Armbruster writes: > Back in 2016, we discussed[1] rules for headers, and these were > generally liked: > > 1. Have a carefully curated header that's included everywhere first. We > got that already thanks to Peter: osdep.h. > > 2. Headers should normally include everything they need beyond osdep.h. > If exceptions are needed for some reason, they must be documented in > the header. If all that's needed from a header is typedefs, put > those into qemu/typedefs.h instead of including the header. > > 3. Cyclic inclusion is forbidden. > > This series fixes violations of rule 2. I may have split patches too > aggressively. Let me know if you want some squashed together. > > v4: > * PATCH 01-03: New > * PATCH 04-15: Previous version redone with scripts/clean-includes, > result split up for review Copying the R-bys for v3 to these patches is tempting. But I didn't. > * PATCH 16-19: New > > v3: > * Rebased, old PATCH 1+2+4 are in master as commit > 881e019770..f07ceffdf5 > * PATCH 1: Fix bsd-user > > v2: > * Rebased > * PATCH 3: v1 posted separately > * PATCH 4: New > > [1] Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org> > https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html From MAILER-DAEMON Thu Jan 19 04:34:21 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIRJM-00089Q-Vy for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 04:34:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIRJI-00088O-1J for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 04:34:20 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIRJF-0007ru-A2 for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 04:34:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674120852; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=oZLLlV4BGDvm510wcGYESS9p0wICXiApD4Uvqj34INw=; b=BTBPDPTD/oFp3q0wCEAR/SB5dXC5pa9Lu0kqF5wp8ykUElexGDbKqMVIzbIfTsER52LJHK MmaO26gqyi77R0jhtWfDRXFufm94iW7bnDIjzcf1wHBo337qqffwg9k7R2eGDVaORe3HQp 4UKwUTk1X+QQ6PVitxR/zbWaInTmnUI= Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-277-hYanFtl0P-u2wFDLYUFNiw-1; Thu, 19 Jan 2023 04:34:11 -0500 X-MC-Unique: hYanFtl0P-u2wFDLYUFNiw-1 Received: by mail-wm1-f71.google.com with SMTP id z22-20020a05600c0a1600b003db00dc4b69so2662079wmp.5 for ; Thu, 19 Jan 2023 01:34:11 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=user-agent:in-reply-to:content-disposition:mime-version:references :message-id:subject:cc:to:from:date:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oZLLlV4BGDvm510wcGYESS9p0wICXiApD4Uvqj34INw=; b=qN3cv66a5hIoMn5Xe70+8sjP3ZUd5n3DC5u2oKCCvGawCqes6oFNJ5ry4UBuHUumzm FEAngwLBY5dJoPUTadZ4VfMqN4POQ5LRHQMSGAmK0UDai8XVHzlo8+eZ0mldlYfY2eM0 wISrzipoNJlEHS5lWgqafGUfQnie8ko2pSTvsVD286cKRIHf2sn5UKIogZ4FSA/Nb87/ qYQGQfS4qqzaTL7kKyn3yxNTuv29QwYBiGHvco+rNvne5ymumNZQFr/rvvjz1AB8QMs1 +aaBcuFYJ/KF1p/2xDZPNsLmHPlWN2NHzghfpWY+22dKaQvLasVPLgIL79IGO5uzt2fL cy8w== X-Gm-Message-State: AFqh2kqv7d9Yawed9sEH9c4kKaTT7Q85/ODGj42eLN6rJLzltzsEWts8 Yru+c0XxZ3NmEUt2LENSstgLkbSjkJB+ChQf0ekzN5RtDrMyLk6rKjGjRWxi8WCcMjuUgPqZr3F WWcRnZBmnMhfmgIc= X-Received: by 2002:a05:600c:4f86:b0:3db:15b1:fb28 with SMTP id n6-20020a05600c4f8600b003db15b1fb28mr4970012wmq.19.1674120850181; Thu, 19 Jan 2023 01:34:10 -0800 (PST) X-Google-Smtp-Source: AMrXdXtACPYeEtXsWD3i8FPBn/RtzVqsOWE4KGdrLkI5m0zB+5vU5TS/iPFcqUFkLzM5CEzrV9UtVw== X-Received: by 2002:a05:600c:4f86:b0:3db:15b1:fb28 with SMTP id n6-20020a05600c4f8600b003db15b1fb28mr4969967wmq.19.1674120849904; Thu, 19 Jan 2023 01:34:09 -0800 (PST) Received: from work-vm (ward-16-b2-v4wan-166627-cust863.vm18.cable.virginm.net. [81.97.203.96]) by smtp.gmail.com with ESMTPSA id bd24-20020a05600c1f1800b003db122d5ac2sm4430267wmb.15.2023.01.19.01.34.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 01:34:09 -0800 (PST) Date: Thu, 19 Jan 2023 09:34:07 +0000 From: "Dr. David Alan Gilbert" To: Markus Armbruster Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 10/19] migration: Clean up includes Message-ID: References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-11-armbru@redhat.com> MIME-Version: 1.0 In-Reply-To: <20230119065959.3104012-11-armbru@redhat.com> User-Agent: Mutt/2.2.9 (2022-11-12) X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=170.10.129.124; envelope-from=dgilbert@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 09:34:20 -0000 * Markus Armbruster (armbru@redhat.com) wrote: > Clean up includes so that osdep.h is included first and headers > which it implies are not included manually. That change doesn't seem to match the message; the patch is removing the osdep.h include. Dave > This commit was created with scripts/clean-includes. > > Signed-off-by: Markus Armbruster > --- > include/qemu/userfaultfd.h | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/include/qemu/userfaultfd.h b/include/qemu/userfaultfd.h > index 6b74f92792..55c95998e8 100644 > --- a/include/qemu/userfaultfd.h > +++ b/include/qemu/userfaultfd.h > @@ -13,7 +13,6 @@ > #ifndef USERFAULTFD_H > #define USERFAULTFD_H > > -#include "qemu/osdep.h" > #include "exec/hwaddr.h" > #include > > -- > 2.39.0 > -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK From MAILER-DAEMON Thu Jan 19 04:51:14 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIRZi-0005p7-A9 for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 04:51:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIRZg-0005oC-AN; Thu, 19 Jan 2023 04:51:12 -0500 Received: from kylie.crudebyte.com ([5.189.157.229]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIRZc-0002rX-GX; Thu, 19 Jan 2023 04:51:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=crudebyte.com; s=kylie; h=Content-Type:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Content-ID:Content-Description; bh=jEiGaghMr6rpWAxosGe+WxtwHecKYx8iN/Wr+8lZdFk=; b=tiHK0clFRcXGYvtC+U5gmOB3Lz 3qkrcErCEsp4TJBujdXms/J1wM7mQMV8VbwtTBjyw6iwLND+MA/KpdJXRoo+uycWhQGIppBDvqVVT dCLCUV4rg4uhVqtwprx4x9GemGsc+m5kcGE1sazAzgoKFWt5U3O+h214/TesQeVjLJlwCil8M62AA nD7wBmtCuMdcnczhbY+piJkmzy1Hs/qGhyTtMIPMxrRkV9HUMmtCgKmQ3d+5+MxvtgytapMXCDWPX PMO0qlf7AJYAxPHH/fdomf5DzbMm2o/9BK8jYq84Fq1486LoyQskweYyq0RipwkZ4ja2mgxB5N5Du Y+fCyqzDx/216eZwXgAq1Ifz/I1p6SCt0g/oI+fJfPl+wjk2eimJAkEf79DVebGFaluzHRLrQDcUK yu3qnUfaG3Zgj9oynSjxlPVEQbTzb/C36aupE+rP/8eX1Qq0wjh0rFGxlrDa7tNwHpjS78WFgAaMR kIGfyilmSWvchIWhx1/vACIojrGQ1ER0Al2QeQQwycTK57bzKpr6i3FCjutKT6B9cgVNrFbalymtH MvhxvZOU/uNaewBsVGbosCY/Q11+w+JKp5FmrM0NBxqjyuNwu/kDyLthi+3Jz6GJL9xbvyiUBdzJM hbswTjcttV10R8IH9Zoxe/nMQQySq2OD1eUfiVlZA=; From: Christian Schoenebeck To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Markus Armbruster Subject: Re: [PATCH v4 18/19] 9p: Drop superfluous include of linux/limits.h Date: Thu, 19 Jan 2023 10:50:39 +0100 Message-ID: <5266030.ICAI56zT51@silver> In-Reply-To: <20230119065959.3104012-19-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-19-armbru@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Received-SPF: pass client-ip=5.189.157.229; envelope-from=qemu_oss@crudebyte.com; helo=kylie.crudebyte.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 09:51:13 -0000 On Thursday, January 19, 2023 7:59:58 AM CET Markus Armbruster wrote: > Signed-off-by: Markus Armbruster > --- > hw/9pfs/9p.c | 3 --- > 1 file changed, 3 deletions(-) > > diff --git a/hw/9pfs/9p.c b/hw/9pfs/9p.c > index 9621ec1341..aa736af380 100644 > --- a/hw/9pfs/9p.c > +++ b/hw/9pfs/9p.c > @@ -17,9 +17,6 @@ > */ > > #include "qemu/osdep.h" > -#ifdef CONFIG_LINUX > -#include > -#endif > #include > #include "hw/virtio/virtio.h" > #include "qapi/error.h" > Where did that base version come from? I don't see it anywhere in history. Last relevant change in context was a136d17590a. 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[81.97.203.96]) by smtp.gmail.com with ESMTPSA id p4-20020a05600c1d8400b003da286f8332sm4749548wms.18.2023.01.19.02.19.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 02:19:05 -0800 (PST) Date: Thu, 19 Jan 2023 10:19:02 +0000 From: "Dr. David Alan Gilbert" To: Markus Armbruster Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 19/19] Drop duplicate #include Message-ID: References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-20-armbru@redhat.com> MIME-Version: 1.0 In-Reply-To: <20230119065959.3104012-20-armbru@redhat.com> User-Agent: Mutt/2.2.9 (2022-11-12) X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=170.10.133.124; envelope-from=dgilbert@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 10:19:32 -0000 * Markus Armbruster (armbru@redhat.com) wrote: > Tracked down with the help of scripts/clean-includes. > > Signed-off-by: Markus Armbruster > --- > include/hw/arm/fsl-imx6ul.h | 1 - > include/hw/arm/fsl-imx7.h | 1 - > backends/tpm/tpm_emulator.c | 1 - > hw/acpi/piix4.c | 1 - > hw/alpha/dp264.c | 1 - > hw/arm/virt.c | 1 - > hw/arm/xlnx-versal.c | 1 - > hw/block/pflash_cfi01.c | 1 - > hw/core/machine.c | 1 - > hw/hppa/machine.c | 1 - > hw/i386/acpi-build.c | 1 - > hw/loongarch/acpi-build.c | 1 - > hw/misc/macio/cuda.c | 1 - > hw/misc/macio/pmu.c | 1 - > hw/net/xilinx_axienet.c | 1 - > hw/ppc/ppc405_uc.c | 2 -- > hw/ppc/ppc440_bamboo.c | 1 - > hw/ppc/spapr_drc.c | 1 - > hw/rdma/vmw/pvrdma_dev_ring.c | 1 - > hw/remote/machine.c | 1 - > hw/remote/remote-obj.c | 1 - > hw/rtc/mc146818rtc.c | 1 - > hw/s390x/virtio-ccw-serial.c | 1 - > migration/postcopy-ram.c | 2 -- > softmmu/dirtylimit.c | 1 - > softmmu/runstate.c | 1 - > softmmu/vl.c | 1 - > target/loongarch/translate.c | 1 - > target/mips/tcg/translate.c | 1 - > target/nios2/translate.c | 2 -- > tests/unit/test-cutils.c | 1 - > ui/gtk.c | 1 - > util/oslib-posix.c | 4 ---- > 33 files changed, 39 deletions(-) > > diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h > index 7812e516a5..1952cb984d 100644 > --- a/include/hw/arm/fsl-imx6ul.h > +++ b/include/hw/arm/fsl-imx6ul.h > @@ -30,7 +30,6 @@ > #include "hw/timer/imx_gpt.h" > #include "hw/timer/imx_epit.h" > #include "hw/i2c/imx_i2c.h" > -#include "hw/gpio/imx_gpio.h" > #include "hw/sd/sdhci.h" > #include "hw/ssi/imx_spi.h" > #include "hw/net/imx_fec.h" > diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h > index 4e5e071864..355bd8ea83 100644 > --- a/include/hw/arm/fsl-imx7.h > +++ b/include/hw/arm/fsl-imx7.h > @@ -32,7 +32,6 @@ > #include "hw/timer/imx_gpt.h" > #include "hw/timer/imx_epit.h" > #include "hw/i2c/imx_i2c.h" > -#include "hw/gpio/imx_gpio.h" > #include "hw/sd/sdhci.h" > #include "hw/ssi/imx_spi.h" > #include "hw/net/imx_fec.h" > diff --git a/backends/tpm/tpm_emulator.c b/backends/tpm/tpm_emulator.c > index 49cc3d749d..2b440d2c9a 100644 > --- a/backends/tpm/tpm_emulator.c > +++ b/backends/tpm/tpm_emulator.c > @@ -35,7 +35,6 @@ > #include "sysemu/runstate.h" > #include "sysemu/tpm_backend.h" > #include "sysemu/tpm_util.h" > -#include "sysemu/runstate.h" > #include "tpm_int.h" > #include "tpm_ioctl.h" > #include "migration/blocker.h" > diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c > index 0a81f1ad93..df39f91294 100644 > --- a/hw/acpi/piix4.c > +++ b/hw/acpi/piix4.c > @@ -35,7 +35,6 @@ > #include "sysemu/xen.h" > #include "qapi/error.h" > #include "qemu/range.h" > -#include "hw/acpi/pcihp.h" > #include "hw/acpi/cpu_hotplug.h" > #include "hw/acpi/cpu.h" > #include "hw/hotplug.h" > diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c > index c502c8c62a..4161f559a7 100644 > --- a/hw/alpha/dp264.c > +++ b/hw/alpha/dp264.c > @@ -18,7 +18,6 @@ > #include "net/net.h" > #include "qemu/cutils.h" > #include "qemu/datadir.h" > -#include "net/net.h" > > static uint64_t cpu_alpha_superpage_to_phys(void *opaque, uint64_t addr) > { > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index ea2413a0ba..d3849d7233 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -33,7 +33,6 @@ > #include "qemu/units.h" > #include "qemu/option.h" > #include "monitor/qdev.h" > -#include "qapi/error.h" > #include "hw/sysbus.h" > #include "hw/arm/boot.h" > #include "hw/arm/primecell.h" > diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c > index 57276e1506..69b1b99e93 100644 > --- a/hw/arm/xlnx-versal.c > +++ b/hw/arm/xlnx-versal.c > @@ -22,7 +22,6 @@ > #include "hw/misc/unimp.h" > #include "hw/arm/xlnx-versal.h" > #include "qemu/log.h" > -#include "hw/sysbus.h" > > #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") > #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") > diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c > index 0cbc2fb4cb..d11406eada 100644 > --- a/hw/block/pflash_cfi01.c > +++ b/hw/block/pflash_cfi01.c > @@ -45,7 +45,6 @@ > #include "qapi/error.h" > #include "qemu/error-report.h" > #include "qemu/bitops.h" > -#include "qemu/error-report.h" > #include "qemu/host-utils.h" > #include "qemu/log.h" > #include "qemu/module.h" > diff --git a/hw/core/machine.c b/hw/core/machine.c > index 616f3a207c..67cf9f9dcd 100644 > --- a/hw/core/machine.c > +++ b/hw/core/machine.c > @@ -39,7 +39,6 @@ > #include "exec/confidential-guest-support.h" > #include "hw/virtio/virtio.h" > #include "hw/virtio/virtio-pci.h" > -#include "qom/object_interfaces.h" > > GlobalProperty hw_compat_7_2[] = {}; > const size_t hw_compat_7_2_len = G_N_ELEMENTS(hw_compat_7_2); > diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c > index de1cc7ab71..7ac68c943f 100644 > --- a/hw/hppa/machine.c > +++ b/hw/hppa/machine.c > @@ -28,7 +28,6 @@ > #include "qapi/error.h" > #include "net/net.h" > #include "qemu/log.h" > -#include "net/net.h" > > #define MIN_SEABIOS_HPPA_VERSION 6 /* require at least this fw version */ > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > index 127c4e2d50..14f6f75454 100644 > --- a/hw/i386/acpi-build.c > +++ b/hw/i386/acpi-build.c > @@ -76,7 +76,6 @@ > > #include "hw/acpi/hmat.h" > #include "hw/acpi/viot.h" > -#include "hw/acpi/cxl.h" > > #include CONFIG_DEVICES > > diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c > index c2b237736d..f551296a0e 100644 > --- a/hw/loongarch/acpi-build.c > +++ b/hw/loongarch/acpi-build.c > @@ -22,7 +22,6 @@ > /* Supported chipsets: */ > #include "hw/pci-host/ls7a.h" > #include "hw/loongarch/virt.h" > -#include "hw/acpi/aml-build.h" > > #include "hw/acpi/utils.h" > #include "hw/acpi/pci.h" > diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c > index 853e88bfed..29a8e5ed19 100644 > --- a/hw/misc/macio/cuda.c > +++ b/hw/misc/macio/cuda.c > @@ -30,7 +30,6 @@ > #include "hw/input/adb.h" > #include "hw/misc/mos6522.h" > #include "hw/misc/macio/cuda.h" > -#include "qapi/error.h" > #include "qemu/timer.h" > #include "sysemu/runstate.h" > #include "sysemu/rtc.h" > diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c > index 97ef8c771b..5a788e595a 100644 > --- a/hw/misc/macio/pmu.c > +++ b/hw/misc/macio/pmu.c > @@ -36,7 +36,6 @@ > #include "hw/misc/mos6522.h" > #include "hw/misc/macio/gpio.h" > #include "hw/misc/macio/pmu.h" > -#include "qapi/error.h" > #include "qemu/timer.h" > #include "sysemu/runstate.h" > #include "sysemu/rtc.h" > diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c > index 990ff3a1c2..673af7da26 100644 > --- a/hw/net/xilinx_axienet.c > +++ b/hw/net/xilinx_axienet.c > @@ -31,7 +31,6 @@ > #include "net/net.h" > #include "net/checksum.h" > > -#include "hw/hw.h" > #include "hw/irq.h" > #include "hw/qdev-properties.h" > #include "hw/stream.h" > diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c > index c973cfb04e..0cc68178ad 100644 > --- a/hw/ppc/ppc405_uc.c > +++ b/hw/ppc/ppc405_uc.c > @@ -38,8 +38,6 @@ > #include "sysemu/sysemu.h" > #include "exec/address-spaces.h" > #include "hw/intc/ppc-uic.h" > -#include "hw/qdev-properties.h" > -#include "qapi/error.h" > #include "trace.h" > > /*****************************************************************************/ > diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c > index 81d71adf34..2880c81cb1 100644 > --- a/hw/ppc/ppc440_bamboo.c > +++ b/hw/ppc/ppc440_bamboo.c > @@ -13,7 +13,6 @@ > > #include "qemu/osdep.h" > #include "qemu/units.h" > -#include "qemu/error-report.h" > #include "qemu/datadir.h" > #include "qemu/error-report.h" > #include "net/net.h" > diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c > index 4923435a8b..b5c400a94d 100644 > --- a/hw/ppc/spapr_drc.c > +++ b/hw/ppc/spapr_drc.c > @@ -17,7 +17,6 @@ > #include "hw/ppc/spapr_drc.h" > #include "qom/object.h" > #include "migration/vmstate.h" > -#include "qapi/error.h" > #include "qapi/qapi-events-qdev.h" > #include "qapi/visitor.h" > #include "qemu/error-report.h" > diff --git a/hw/rdma/vmw/pvrdma_dev_ring.c b/hw/rdma/vmw/pvrdma_dev_ring.c > index 598e6adc5e..30ce22a5be 100644 > --- a/hw/rdma/vmw/pvrdma_dev_ring.c > +++ b/hw/rdma/vmw/pvrdma_dev_ring.c > @@ -14,7 +14,6 @@ > */ > > #include "qemu/osdep.h" > -#include "qemu/cutils.h" > #include "hw/pci/pci.h" > #include "cpu.h" > #include "qemu/cutils.h" > diff --git a/hw/remote/machine.c b/hw/remote/machine.c > index 519f855ec1..fdc6c441bb 100644 > --- a/hw/remote/machine.c > +++ b/hw/remote/machine.c > @@ -22,7 +22,6 @@ > #include "hw/remote/iohub.h" > #include "hw/remote/iommu.h" > #include "hw/qdev-core.h" > -#include "hw/remote/iommu.h" > #include "hw/remote/vfio-user-obj.h" > #include "hw/pci/msi.h" > > diff --git a/hw/remote/remote-obj.c b/hw/remote/remote-obj.c > index 333e5ac443..65b6f7cc86 100644 > --- a/hw/remote/remote-obj.c > +++ b/hw/remote/remote-obj.c > @@ -12,7 +12,6 @@ > #include "qemu/error-report.h" > #include "qemu/notify.h" > #include "qom/object_interfaces.h" > -#include "hw/qdev-core.h" > #include "io/channel.h" > #include "hw/qdev-core.h" > #include "hw/remote/machine.h" > diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c > index bc1192b7ae..ba612a151d 100644 > --- a/hw/rtc/mc146818rtc.c > +++ b/hw/rtc/mc146818rtc.c > @@ -43,7 +43,6 @@ > #include "qapi/error.h" > #include "qapi/qapi-events-misc.h" > #include "qapi/visitor.h" > -#include "hw/rtc/mc146818rtc_regs.h" > > //#define DEBUG_CMOS > //#define DEBUG_COALESCED > diff --git a/hw/s390x/virtio-ccw-serial.c b/hw/s390x/virtio-ccw-serial.c > index bf8057880f..8f8d2302f8 100644 > --- a/hw/s390x/virtio-ccw-serial.c > +++ b/hw/s390x/virtio-ccw-serial.c > @@ -15,7 +15,6 @@ > #include "hw/qdev-properties.h" > #include "hw/virtio/virtio-serial.h" > #include "virtio-ccw.h" > -#include "hw/virtio/virtio-serial.h" > > #define TYPE_VIRTIO_SERIAL_CCW "virtio-serial-ccw" > OBJECT_DECLARE_SIMPLE_TYPE(VirtioSerialCcw, VIRTIO_SERIAL_CCW) > diff --git a/migration/postcopy-ram.c b/migration/postcopy-ram.c > index b9a37ef255..8b7d1af75d 100644 > --- a/migration/postcopy-ram.c > +++ b/migration/postcopy-ram.c > @@ -17,7 +17,6 @@ > */ > > #include "qemu/osdep.h" > -#include "qemu/rcu.h" > #include "qemu/madvise.h" > #include "exec/target_page.h" > #include "migration.h" > @@ -34,7 +33,6 @@ > #include "hw/boards.h" > #include "exec/ramblock.h" > #include "socket.h" > -#include "qemu-file.h" > #include "yank_functions.h" > #include "tls.h" Acked-by: Dr. David Alan Gilbert > > diff --git a/softmmu/dirtylimit.c b/softmmu/dirtylimit.c > index 12668555f2..c56f0f58c8 100644 > --- a/softmmu/dirtylimit.c > +++ b/softmmu/dirtylimit.c > @@ -11,7 +11,6 @@ > */ > > #include "qemu/osdep.h" > -#include "qapi/error.h" > #include "qemu/main-loop.h" > #include "qapi/qapi-commands-migration.h" > #include "qapi/qmp/qdict.h" > diff --git a/softmmu/runstate.c b/softmmu/runstate.c > index cab9f6fc07..f9ad88e6a7 100644 > --- a/softmmu/runstate.c > +++ b/softmmu/runstate.c > @@ -41,7 +41,6 @@ > #include "qapi/qapi-commands-run-state.h" > #include "qapi/qapi-events-run-state.h" > #include "qemu/error-report.h" > -#include "qemu/log.h" > #include "qemu/job.h" > #include "qemu/log.h" > #include "qemu/module.h" > diff --git a/softmmu/vl.c b/softmmu/vl.c > index 5355a7fe5a..b2ee3fee3f 100644 > --- a/softmmu/vl.c > +++ b/softmmu/vl.c > @@ -129,7 +129,6 @@ > #include "qapi/qapi-commands-misc.h" > #include "qapi/qapi-visit-qom.h" > #include "qapi/qapi-commands-ui.h" > -#include "qapi/qmp/qdict.h" > #include "block/qdict.h" > #include "qapi/qmp/qerror.h" > #include "sysemu/iothread.h" > diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c > index 38ced69803..72a6275665 100644 > --- a/target/loongarch/translate.c > +++ b/target/loongarch/translate.c > @@ -12,7 +12,6 @@ > #include "exec/helper-proto.h" > #include "exec/helper-gen.h" > > -#include "exec/translator.h" > #include "exec/log.h" > #include "qemu/qemu-print.h" > #include "fpu/softfloat.h" > diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c > index 624e6b7786..aa12bb708a 100644 > --- a/target/mips/tcg/translate.c > +++ b/target/mips/tcg/translate.c > @@ -32,7 +32,6 @@ > #include "semihosting/semihost.h" > > #include "trace.h" > -#include "exec/translator.h" > #include "exec/log.h" > #include "qemu/qemu-print.h" > #include "fpu_helper.h" > diff --git a/target/nios2/translate.c b/target/nios2/translate.c > index 4db8b47744..7aee65a089 100644 > --- a/target/nios2/translate.c > +++ b/target/nios2/translate.c > @@ -938,8 +938,6 @@ static const char * const cr_regnames[NUM_CR_REGS] = { > }; > #endif > > -#include "exec/gen-icount.h" > - > /* generate intermediate code for basic block 'tb'. */ > static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > { > diff --git a/tests/unit/test-cutils.c b/tests/unit/test-cutils.c > index 2126b46391..3c4f875420 100644 > --- a/tests/unit/test-cutils.c > +++ b/tests/unit/test-cutils.c > @@ -26,7 +26,6 @@ > */ > > #include "qemu/osdep.h" > -#include "qemu/units.h" > #include "qemu/cutils.h" > #include "qemu/units.h" > > diff --git a/ui/gtk.c b/ui/gtk.c > index 4817623c8f..7f752d8b7d 100644 > --- a/ui/gtk.c > +++ b/ui/gtk.c > @@ -53,7 +53,6 @@ > #include > > #include "trace.h" > -#include "qemu/cutils.h" > #include "ui/input.h" > #include "sysemu/runstate.h" > #include "sysemu/sysemu.h" > diff --git a/util/oslib-posix.c b/util/oslib-posix.c > index fd03fd32c8..77d882e681 100644 > --- a/util/oslib-posix.c > +++ b/util/oslib-posix.c > @@ -59,10 +59,6 @@ > > #include "qemu/mmap-alloc.h" > > -#ifdef CONFIG_DEBUG_STACK_USAGE > -#include "qemu/error-report.h" > -#endif > - > #define MAX_MEM_PREALLOC_THREAD_COUNT 16 > > struct MemsetThread; > -- > 2.39.0 > -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK From MAILER-DAEMON Thu Jan 19 05:31:31 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pISCh-0007bF-N5 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To: "Dr. David Alan Gilbert" Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 10/19] migration: Clean up includes References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-11-armbru@redhat.com> Date: Thu, 19 Jan 2023 11:31:17 +0100 In-Reply-To: (David Alan Gilbert's message of "Thu, 19 Jan 2023 09:34:07 +0000") Message-ID: <87wn5ivmru.fsf@pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Scanned-By: MIMEDefang 3.1 on 10.11.54.2 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 10:31:30 -0000 "Dr. David Alan Gilbert" writes: > * Markus Armbruster (armbru@redhat.com) wrote: >> Clean up includes so that osdep.h is included first and headers >> which it implies are not included manually. > > That change doesn't seem to match the message; the patch is removing the > osdep.h include. It's the commit message scripts/clean-includes creates :) I can throw in another patch to the script so it mentions it also removes qemu/osdep.h from headers. >> This commit was created with scripts/clean-includes. >> >> Signed-off-by: Markus Armbruster >> --- >> include/qemu/userfaultfd.h | 1 - >> 1 file changed, 1 deletion(-) >> >> diff --git a/include/qemu/userfaultfd.h b/include/qemu/userfaultfd.h >> index 6b74f92792..55c95998e8 100644 >> --- a/include/qemu/userfaultfd.h >> +++ b/include/qemu/userfaultfd.h >> @@ -13,7 +13,6 @@ >> #ifndef USERFAULTFD_H >> #define USERFAULTFD_H >> >> -#include "qemu/osdep.h" >> #include "exec/hwaddr.h" >> #include >> >> -- >> 2.39.0 >> From MAILER-DAEMON Thu Jan 19 05:34:31 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pISFb-0002LX-1R for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 05:34:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pISFV-0002DN-Cv for qemu-riscv@nongnu.org; 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Thu, 19 Jan 2023 02:34:19 -0800 (PST) Message-ID: Date: Thu, 19 Jan 2023 11:34:16 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v4 08/19] hw/tricore: Clean up includes Content-Language: en-US To: Markus Armbruster , qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-9-armbru@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230119065959.3104012-9-armbru@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.089, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 10:34:28 -0000 On 19/1/23 07:59, Markus Armbruster wrote: > Clean up includes so that osdep.h is included first and headers > which it implies are not included manually. > > This commit was created with scripts/clean-includes. > > Signed-off-by: Markus Armbruster > --- > include/hw/tricore/triboard.h | 1 - > 1 file changed, 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 19 05:34:56 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pISG0-0003FA-3W for mharc-qemu-riscv@gnu.org; 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Thu, 19 Jan 2023 02:34:50 -0800 (PST) Message-ID: Date: Thu, 19 Jan 2023 11:34:48 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v4 05/19] crypto: Clean up includes Content-Language: en-US To: Markus Armbruster , qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-6-armbru@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230119065959.3104012-6-armbru@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.089, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 10:34:54 -0000 On 19/1/23 07:59, Markus Armbruster wrote: > Clean up includes so that osdep.h is included first and headers > which it implies are not included manually. > > This commit was created with scripts/clean-includes. > > Signed-off-by: Markus Armbruster > --- > crypto/block-luks-priv.h | 1 - > 1 file changed, 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 19 05:36:08 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pISHA-0006d5-DJ for mharc-qemu-riscv@gnu.org; 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Thu, 19 Jan 2023 02:36:01 -0800 (PST) Message-ID: Date: Thu, 19 Jan 2023 11:35:59 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v4 11/19] net: Clean up includes Content-Language: en-US To: Markus Armbruster , qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-12-armbru@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230119065959.3104012-12-armbru@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.089, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 10:36:06 -0000 On 19/1/23 07:59, Markus Armbruster wrote: > Clean up includes so that osdep.h is included first and headers > which it implies are not included manually. > > This commit was created with scripts/clean-includes. > > Signed-off-by: Markus Armbruster > --- > net/vmnet_int.h | 1 - > 1 file changed, 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 19 05:36:52 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pISHn-0007x4-LK for mharc-qemu-riscv@gnu.org; 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Thu, 19 Jan 2023 02:36:37 -0800 (PST) Message-ID: <823c1832-b165-f3a3-75a6-ff8de387dbb0@linaro.org> Date: Thu, 19 Jan 2023 11:36:35 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v4 15/19] accel: Clean up includes Content-Language: en-US To: Markus Armbruster , qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-16-armbru@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230119065959.3104012-16-armbru@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=philmd@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.089, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 10:36:45 -0000 On 19/1/23 07:59, Markus Armbruster wrote: > Clean up includes so that osdep.h is included first and headers > which it implies are not included manually. > > This commit was created with scripts/clean-includes. > > Signed-off-by: Markus Armbruster > --- > include/sysemu/accel-blocker.h | 1 - > 1 file changed, 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 19 05:37:17 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pISIF-0008Cq-CE for mharc-qemu-riscv@gnu.org; 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Thu, 19 Jan 2023 05:37:03 -0500 X-MC-Unique: yF-0uHIbPi-6cFyWOvTzDA-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 1CB3419705A9; Thu, 19 Jan 2023 10:37:02 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id C91291415126; Thu, 19 Jan 2023 10:37:01 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id A514221E6A28; Thu, 19 Jan 2023 11:37:00 +0100 (CET) From: Markus Armbruster To: Christian Schoenebeck Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Markus Armbruster Subject: Re: [PATCH v4 18/19] 9p: Drop superfluous include of linux/limits.h References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-19-armbru@redhat.com> <5266030.ICAI56zT51@silver> Date: Thu, 19 Jan 2023 11:37:00 +0100 In-Reply-To: <5266030.ICAI56zT51@silver> (Christian Schoenebeck's message of "Thu, 19 Jan 2023 10:50:39 +0100") Message-ID: <87ilh2vmib.fsf@pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 10:37:11 -0000 Christian Schoenebeck writes: > On Thursday, January 19, 2023 7:59:58 AM CET Markus Armbruster wrote: >> Signed-off-by: Markus Armbruster >> --- >> hw/9pfs/9p.c | 3 --- >> 1 file changed, 3 deletions(-) >> >> diff --git a/hw/9pfs/9p.c b/hw/9pfs/9p.c >> index 9621ec1341..aa736af380 100644 >> --- a/hw/9pfs/9p.c >> +++ b/hw/9pfs/9p.c >> @@ -17,9 +17,6 @@ >> */ >> >> #include "qemu/osdep.h" >> -#ifdef CONFIG_LINUX >> -#include >> -#endif >> #include >> #include "hw/virtio/virtio.h" >> #include "qapi/error.h" >> > > Where did that base version come from? I don't see it anywhere in history. > Last relevant change in context was a136d17590a. Current master (7ec8aeb6048) has #include "qemu/osdep.h" #ifdef CONFIG_LINUX #include #else #include #endif #include The previous commit changes it to #include "qemu/osdep.h" #ifdef CONFIG_LINUX #include #endif #include because "qemu/osdep.h" already includes . Clearer now? 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Thu, 19 Jan 2023 02:38:29 -0800 (PST) Received: from [192.168.30.216] ([81.0.6.76]) by smtp.gmail.com with ESMTPSA id w1-20020a1cf601000000b003daf681d05dsm4483347wmc.26.2023.01.19.02.38.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Jan 2023 02:38:28 -0800 (PST) Message-ID: <802eb2a3-e7bf-ca38-daf2-75275980e865@linaro.org> Date: Thu, 19 Jan 2023 11:38:26 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v4 13/19] riscv: Clean up includes Content-Language: en-US To: Markus Armbruster , qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-14-armbru@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230119065959.3104012-14-armbru@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.089, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 10:38:32 -0000 On 19/1/23 07:59, Markus Armbruster wrote: > Clean up includes so that osdep.h is included first and headers > which it implies are not included manually. > > This commit was created with scripts/clean-includes. > > Signed-off-by: Markus Armbruster > --- > target/riscv/pmu.h | 1 - > 1 file changed, 1 deletion(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 19 05:40:19 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pISLD-0004w6-8y for mharc-qemu-riscv@gnu.org; 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Thu, 19 Jan 2023 02:40:08 -0800 (PST) Message-ID: Date: Thu, 19 Jan 2023 11:40:06 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v4 16/19] Fix non-first inclusions of qemu/osdep.h Content-Language: en-US To: Markus Armbruster , qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-17-armbru@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230119065959.3104012-17-armbru@redhat.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.089, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 10:40:15 -0000 On 19/1/23 07:59, Markus Armbruster wrote: > This commit was created with scripts/clean-includes. > > Signed-off-by: Markus Armbruster > --- > audio/sndioaudio.c | 2 +- > backends/hostmem-epc.c | 2 +- > block/export/vduse-blk.c | 2 +- > hw/hyperv/syndbg.c | 2 +- > util/async-teardown.c | 12 ++++-------- > 5 files changed, 8 insertions(+), 12 deletions(-) > > diff --git a/audio/sndioaudio.c b/audio/sndioaudio.c > index 632b0e3825..3fde01fdbd 100644 > --- a/audio/sndioaudio.c > +++ b/audio/sndioaudio.c > @@ -14,9 +14,9 @@ > * to recording, which is what guest systems expect. > */ > > +#include "qemu/osdep.h" > #include > #include > -#include "qemu/osdep.h" > #include "qemu/main-loop.h" > #include "audio.h" > #include "trace.h" > diff --git a/backends/hostmem-epc.c b/backends/hostmem-epc.c > index 037292d267..4e162d6789 100644 > --- a/backends/hostmem-epc.c > +++ b/backends/hostmem-epc.c > @@ -9,9 +9,9 @@ > * This work is licensed under the terms of the GNU GPL, version 2 or later. > * See the COPYING file in the top-level directory. > */ > -#include > > #include "qemu/osdep.h" > +#include > #include "qom/object_interfaces.h" > #include "qapi/error.h" > #include "sysemu/hostmem.h" > diff --git a/block/export/vduse-blk.c b/block/export/vduse-blk.c > index 350d6fdaf0..f7ae44e3ce 100644 > --- a/block/export/vduse-blk.c > +++ b/block/export/vduse-blk.c > @@ -10,9 +10,9 @@ > * later. See the COPYING file in the top-level directory. > */ > > +#include "qemu/osdep.h" > #include > > -#include "qemu/osdep.h" > #include "qapi/error.h" > #include "block/export.h" > #include "qemu/error-report.h" > diff --git a/hw/hyperv/syndbg.c b/hw/hyperv/syndbg.c > index 16d04cfdc6..94fe1b534b 100644 > --- a/hw/hyperv/syndbg.c > +++ b/hw/hyperv/syndbg.c > @@ -5,8 +5,8 @@ > * See the COPYING file in the top-level directory. > */ > > -#include "qemu/ctype.h" > #include "qemu/osdep.h" > +#include "qemu/ctype.h" > #include "qemu/error-report.h" > #include "qemu/main-loop.h" > #include "qemu/sockets.h" Up to here: Reviewed-by: Philippe Mathieu-Daudé > diff --git a/util/async-teardown.c b/util/async-teardown.c > index 62bfce1b3c..62cdeb0f20 100644 > --- a/util/async-teardown.c > +++ b/util/async-teardown.c > @@ -10,16 +10,12 @@ > * option) any later version. See the COPYING file in the top-level directory. > * > */ > -#include > -#include > -#include > -#include > -#include > -#include > -#include > -#include > > #include "qemu/osdep.h" > +#include > +#include > +#include > + > #include "qemu/async-teardown.h" This file has more changes. From MAILER-DAEMON Thu Jan 19 06:41:34 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pITIU-0004D4-Mu for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 06:41:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pITIT-0004Ci-Ga for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 06:41:33 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pITIS-0006G8-4w for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 06:41:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674128491; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CmPsP3SGpWPOTwWlj7ijZlZ6iruaUyXHSnd1sesgPfw=; b=SJMcASpxV2OW5DSJD/wNF2Uff5T+vVZoE7Vz0oxvWPM50yA6Ne/oPfG8gBHRgU/l8AH+Do k/XmHokYw1jo59snF1VDs57T8VxqbWYzZ45QPk6BZQgsVx54q8ER4Y8wxqs6Ghb+N214of 74HQN97Ohcgh2ZgsmkPABtmju1gdw80= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-159-trcBebO8OVy3wISNSwH_cw-1; Thu, 19 Jan 2023 06:41:27 -0500 X-MC-Unique: trcBebO8OVy3wISNSwH_cw-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 5A3181C05148; Thu, 19 Jan 2023 11:41:26 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 95A082026D68; Thu, 19 Jan 2023 11:41:25 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 6A9A221E6A28; Thu, 19 Jan 2023 12:41:24 +0100 (CET) From: Markus Armbruster To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 16/19] Fix non-first inclusions of qemu/osdep.h References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-17-armbru@redhat.com> Date: Thu, 19 Jan 2023 12:41:24 +0100 In-Reply-To: ("Philippe =?utf-8?Q?Mathieu-Daud=C3=A9=22's?= message of "Thu, 19 Jan 2023 11:40:06 +0100") Message-ID: <873586u4yj.fsf@pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.1 on 10.11.54.4 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 11:41:34 -0000 Philippe Mathieu-Daud=C3=A9 writes: > On 19/1/23 07:59, Markus Armbruster wrote: >> This commit was created with scripts/clean-includes. >> Signed-off-by: Markus Armbruster [...] > Up to here: > > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > >> diff --git a/util/async-teardown.c b/util/async-teardown.c >> index 62bfce1b3c..62cdeb0f20 100644 >> --- a/util/async-teardown.c >> +++ b/util/async-teardown.c >> @@ -10,16 +10,12 @@ >> * option) any later version. See the COPYING file in the top-level d= irectory. >> * >> */ >> -#include >> -#include >> -#include >> -#include >> -#include >> -#include >> -#include >> -#include >>=20=20 >> #include "qemu/osdep.h" >> +#include >> +#include >> +#include >> + >> #include "qemu/async-teardown.h" > > This file has more changes. I'm not sure I understand. The patch does two related things: 1. It puts qemu/osdep.h first. The diff makes it look like we leave it in place and move other stuff across, but that's the same. 2. It deletes inclusions of headers qemu/osdep.h already includes: What would you like me to change or explain? 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[81.97.203.96]) by smtp.gmail.com with ESMTPSA id x23-20020a1c7c17000000b003d974076f13sm4504208wmc.3.2023.01.19.03.45.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 03:45:38 -0800 (PST) Date: Thu, 19 Jan 2023 11:45:36 +0000 From: "Dr. David Alan Gilbert" To: Markus Armbruster Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 10/19] migration: Clean up includes Message-ID: References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-11-armbru@redhat.com> <87wn5ivmru.fsf@pond.sub.org> MIME-Version: 1.0 In-Reply-To: <87wn5ivmru.fsf@pond.sub.org> User-Agent: Mutt/2.2.9 (2022-11-12) X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=170.10.129.124; envelope-from=dgilbert@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 11:45:44 -0000 * Markus Armbruster (armbru@redhat.com) wrote: > "Dr. David Alan Gilbert" writes: > > > * Markus Armbruster (armbru@redhat.com) wrote: > >> Clean up includes so that osdep.h is included first and headers > >> which it implies are not included manually. > > > > That change doesn't seem to match the message; the patch is removing the > > osdep.h include. > > It's the commit message scripts/clean-includes creates :) > > I can throw in another patch to the script so it mentions it also > removes qemu/osdep.h from headers. Oh hmm it would be clearer; but OK then, so Reviewed-by: Dr. David Alan Gilbert > >> This commit was created with scripts/clean-includes. > >> > >> Signed-off-by: Markus Armbruster > >> --- > >> include/qemu/userfaultfd.h | 1 - > >> 1 file changed, 1 deletion(-) > >> > >> diff --git a/include/qemu/userfaultfd.h b/include/qemu/userfaultfd.h > >> index 6b74f92792..55c95998e8 100644 > >> --- a/include/qemu/userfaultfd.h > >> +++ b/include/qemu/userfaultfd.h > >> @@ -13,7 +13,6 @@ > >> #ifndef USERFAULTFD_H > >> #define USERFAULTFD_H > >> > >> -#include "qemu/osdep.h" > >> #include "exec/hwaddr.h" > >> #include > >> > >> -- > >> 2.39.0 > >> > -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK From MAILER-DAEMON Thu Jan 19 06:49:38 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pITQI-0001JC-2T for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 06:49:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pITQG-0001IR-OT for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 06:49:36 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pITQF-0007gv-31 for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 06:49:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674128974; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=gXKBhQL1oyDDx1ruE2azlrsK+OKUgC5n4NqJsx1Hc+Q=; b=KY4VVJqscigx1NCemdZ1ZJnX7P6ncEZ745kLVeAZ2UxuB3hSFEAnvAOmK9Dd325T5ELgwu 8TYEnAR/4Yh5gWGnUYxy7w2xpab7VRB1bNQcV1QAv25q4HhSsMhr8P5iPoxTZq/YI6Y0H3 yd83kXnl0dwbFD0w4SWnFJfFBtSp9lo= Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-197-o_sCpEnuOVOUwbpGbjdFbQ-1; Thu, 19 Jan 2023 06:49:31 -0500 X-MC-Unique: o_sCpEnuOVOUwbpGbjdFbQ-1 Received: by mail-wm1-f71.google.com with SMTP id bg24-20020a05600c3c9800b003db0ddddb6fso1108191wmb.0 for ; Thu, 19 Jan 2023 03:49:31 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=gXKBhQL1oyDDx1ruE2azlrsK+OKUgC5n4NqJsx1Hc+Q=; b=PUrnlfylgob8vp+aqmEjZAigeQ1S0RUbr/RtYs1uVExlcAlVuuJDPSg1i5CvT81GRj l0kt72O4O0l7bSfs0YzC7CWwZHR1NzzzRFIvfKJyrlTUuA4ERFbem8bqas3q6Gc9p3uB GHuMu57xV5n6NTWHj1ouvptnvBpoffxr4tIS34ZAkU+YR4Zsua0LnD6uLEgD470obmL7 SdUkFzNfFo0ER2MgdUMVdWuiqIjQIhk6xHYKAtUuqOdGciS7WD3xLdCjX5qAl+wqSoDz rcJccdD+Xz/iKcTqryPie0mr4d9WSj+HztZV//qboucGeds/LPDvK2Zr4z4fyQOu0xSy Pijw== X-Gm-Message-State: AFqh2kqhlMJ7f8JE8/O6/GC2tQnQzdZ2B44CEi3JxcEUFDIwqdw8eBwS nXIpIn+w9J41SG9JZZCSUUqPwQytp5siJSgTyLnaHp4hf+ROTk288IqA3LNVyPfGi7QaULL69W3 rZjpMqif4XU8XKvo= X-Received: by 2002:a05:600c:995:b0:3da:f4f5:ad0e with SMTP id w21-20020a05600c099500b003daf4f5ad0emr9882105wmp.9.1674128970428; Thu, 19 Jan 2023 03:49:30 -0800 (PST) X-Google-Smtp-Source: AMrXdXtyFX5XBDNN1mc+shz+DynLpyHcpR1+tXEmRLr388f/3Iq/9VIoedm3n4a4NV+D1lBcrxBsjA== X-Received: by 2002:a05:600c:995:b0:3da:f4f5:ad0e with SMTP id w21-20020a05600c099500b003daf4f5ad0emr9882077wmp.9.1674128970208; Thu, 19 Jan 2023 03:49:30 -0800 (PST) Received: from redhat.com ([2.52.28.74]) by smtp.gmail.com with ESMTPSA id r1-20020a05600c35c100b003db06493ee7sm4939784wmq.47.2023.01.19.03.49.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 03:49:29 -0800 (PST) Date: Thu, 19 Jan 2023 06:49:24 -0500 From: "Michael S. Tsirkin" To: Markus Armbruster Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 00/19] Clean up includes Message-ID: <20230119064833-mutt-send-email-mst@kernel.org> References: <20230119065959.3104012-1-armbru@redhat.com> MIME-Version: 1.0 In-Reply-To: <20230119065959.3104012-1-armbru@redhat.com> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 11:49:37 -0000 On Thu, Jan 19, 2023 at 07:59:40AM +0100, Markus Armbruster wrote: > Back in 2016, we discussed[1] rules for headers, and these were > generally liked: > > 1. Have a carefully curated header that's included everywhere first. We > got that already thanks to Peter: osdep.h. > > 2. Headers should normally include everything they need beyond osdep.h. > If exceptions are needed for some reason, they must be documented in > the header. If all that's needed from a header is typedefs, put > those into qemu/typedefs.h instead of including the header. > > 3. Cyclic inclusion is forbidden. > > This series fixes violations of rule 2. I may have split patches too > aggressively. Let me know if you want some squashed together. series Reviewed-by: Michael S. Tsirkin feel free to merge. > v4: > * PATCH 01-03: New > * PATCH 04-15: Previous version redone with scripts/clean-includes, > result split up for review > * PATCH 16-19: New > > v3: > * Rebased, old PATCH 1+2+4 are in master as commit > 881e019770..f07ceffdf5 > * PATCH 1: Fix bsd-user > > v2: > * Rebased > * PATCH 3: v1 posted separately > * PATCH 4: New > > [1] Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org> > https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html > > Markus Armbruster (19): > scripts/clean-includes: Fully skip / ignore files > scripts/clean-includes: Don't claim duplicate headers found when not > scripts/clean-includes: Skip symbolic links > bsd-user: Clean up includes > crypto: Clean up includes > hw/cxl: Clean up includes > hw/input: Clean up includes > hw/tricore: Clean up includes > qga: Clean up includes > migration: Clean up includes > net: Clean up includes > target/hexagon: Clean up includes > riscv: Clean up includes > block: Clean up includes > accel: Clean up includes > Fix non-first inclusions of qemu/osdep.h > Don't include headers already included by qemu/osdep.h > 9p: Drop superfluous include of linux/limits.h > Drop duplicate #include > > backends/tpm/tpm_ioctl.h | 2 -- > bsd-user/bsd-proc.h | 4 ---- > bsd-user/qemu.h | 1 - > crypto/block-luks-priv.h | 1 - > fsdev/p9array.h | 2 -- > include/block/graph-lock.h | 1 - > include/block/write-threshold.h | 2 -- > include/hw/arm/fsl-imx6ul.h | 1 - > include/hw/arm/fsl-imx7.h | 1 - > include/hw/cxl/cxl_component.h | 2 -- > include/hw/cxl/cxl_host.h | 1 - > include/hw/cxl/cxl_pci.h | 1 - > include/hw/input/pl050.h | 1 - > include/hw/misc/aspeed_lpc.h | 2 -- > include/hw/pci/pcie_doe.h | 1 - > include/hw/tricore/triboard.h | 1 - > include/qemu/async-teardown.h | 2 -- > include/qemu/dbus.h | 1 - > include/qemu/host-utils.h | 1 - > include/qemu/userfaultfd.h | 1 - > include/sysemu/accel-blocker.h | 1 - > include/sysemu/event-loop-base.h | 1 - > net/vmnet_int.h | 1 - > qga/cutils.h | 2 -- > target/hexagon/hex_arch_types.h | 1 - > target/hexagon/mmvec/macros.h | 1 - > target/riscv/pmu.h | 1 - > accel/tcg/cpu-exec.c | 1 - > audio/sndioaudio.c | 2 +- > backends/hostmem-epc.c | 2 +- > backends/tpm/tpm_emulator.c | 1 - > block/export/vduse-blk.c | 2 +- > block/qapi.c | 1 - > bsd-user/arm/signal.c | 1 + > bsd-user/arm/target_arch_cpu.c | 2 ++ > bsd-user/freebsd/os-sys.c | 1 + > bsd-user/i386/signal.c | 1 + > bsd-user/i386/target_arch_cpu.c | 3 +-- > bsd-user/main.c | 4 +--- > bsd-user/strace.c | 1 - > bsd-user/x86_64/signal.c | 1 + > bsd-user/x86_64/target_arch_cpu.c | 3 +-- > hw/9pfs/9p.c | 5 ----- > hw/acpi/piix4.c | 1 - > hw/alpha/dp264.c | 1 - > hw/arm/virt.c | 1 - > hw/arm/xlnx-versal.c | 1 - > hw/block/pflash_cfi01.c | 1 - > hw/core/machine.c | 1 - > hw/display/virtio-gpu-udmabuf.c | 1 - > hw/hppa/machine.c | 1 - > hw/hyperv/syndbg.c | 2 +- > hw/i2c/pmbus_device.c | 1 - > hw/i386/acpi-build.c | 1 - > hw/input/tsc210x.c | 1 - > hw/loongarch/acpi-build.c | 1 - > hw/misc/macio/cuda.c | 1 - > hw/misc/macio/pmu.c | 1 - > hw/net/xilinx_axienet.c | 1 - > hw/ppc/ppc405_uc.c | 2 -- > hw/ppc/ppc440_bamboo.c | 1 - > hw/ppc/spapr_drc.c | 1 - > hw/rdma/vmw/pvrdma_dev_ring.c | 1 - > hw/remote/machine.c | 1 - > hw/remote/proxy-memory-listener.c | 1 - > hw/remote/remote-obj.c | 1 - > hw/rtc/mc146818rtc.c | 1 - > hw/s390x/virtio-ccw-serial.c | 1 - > hw/sensor/adm1272.c | 1 - > hw/usb/dev-storage-bot.c | 1 - > hw/usb/dev-storage-classic.c | 1 - > migration/postcopy-ram.c | 2 -- > qga/commands-posix.c | 1 - > qga/cutils.c | 3 ++- > softmmu/dirtylimit.c | 1 - > softmmu/runstate.c | 1 - > softmmu/vl.c | 3 --- > target/loongarch/translate.c | 1 - > target/mips/tcg/translate.c | 1 - > target/nios2/translate.c | 2 -- > tcg/tci.c | 1 - > tests/unit/test-cutils.c | 1 - > tests/unit/test-seccomp.c | 1 - > ui/gtk.c | 1 - > ui/udmabuf.c | 1 - > util/async-teardown.c | 12 ++++-------- > util/main-loop.c | 1 - > util/oslib-posix.c | 6 ------ > scripts/clean-includes | 15 ++++++++++----- > 89 files changed, 29 insertions(+), 123 deletions(-) > > -- > 2.39.0 From MAILER-DAEMON Thu Jan 19 06:52:12 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pITSm-0002tl-3f for mharc-qemu-riscv@gnu.org; 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Thu, 19 Jan 2023 03:52:04 -0800 (PST) Message-ID: Date: Thu, 19 Jan 2023 12:52:02 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v4 16/19] Fix non-first inclusions of qemu/osdep.h Content-Language: en-US To: Markus Armbruster Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-17-armbru@redhat.com> <873586u4yj.fsf@pond.sub.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <873586u4yj.fsf@pond.sub.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.094, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 11:52:11 -0000 On 19/1/23 12:41, Markus Armbruster wrote: > Philippe Mathieu-Daudé writes: > >> On 19/1/23 07:59, Markus Armbruster wrote: >>> This commit was created with scripts/clean-includes. >>> Signed-off-by: Markus Armbruster > > [...] > >> Up to here: >> >> Reviewed-by: Philippe Mathieu-Daudé >> >>> diff --git a/util/async-teardown.c b/util/async-teardown.c >>> index 62bfce1b3c..62cdeb0f20 100644 >>> --- a/util/async-teardown.c >>> +++ b/util/async-teardown.c >>> @@ -10,16 +10,12 @@ >>> * option) any later version. See the COPYING file in the top-level directory. >>> * >>> */ >>> -#include >>> -#include >>> -#include >>> -#include >>> -#include >>> -#include >>> -#include >>> -#include >>> >>> #include "qemu/osdep.h" >>> +#include >>> +#include >>> +#include >>> + >>> #include "qemu/async-teardown.h" >> >> This file has more changes. > > I'm not sure I understand. > > The patch does two related things: > > 1. It puts qemu/osdep.h first. The diff makes it look like we leave it > in place and move other stuff across, but that's the same. > > 2. It deletes inclusions of headers qemu/osdep.h already includes: > > > > > > Ah, the other files get this done in the "Drop duplicate #include" patch. From MAILER-DAEMON Thu Jan 19 07:03:12 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pITdL-0006gi-5Y for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 07:03:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pITcc-0006Mx-Ao; Thu, 19 Jan 2023 07:02:35 -0500 Received: from kylie.crudebyte.com ([5.189.157.229]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pITcU-0001Sr-W9; Thu, 19 Jan 2023 07:02:20 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=crudebyte.com; s=kylie; h=Content-Type:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Content-ID:Content-Description; bh=WjF7bL11kEHUmwtj+dctqzKHVoL4fJEuPmXRLjsup0c=; b=nX4+P0JMIHpctmgm+Nnama6bTP zpBHG4Q2xowGKfZQfbsiO/aNE0pr8zFNc8EbPxsDg5Kl7ewa6uYFK3rJ6ZDMOMrl9zzoFF54pPoeD DIElbamtl153IF607J5gkVVDbBwnoXbHjsTIKr9acKO4rW5jGIkLBVD9fz5s823CX2cJYd/GdF/pC 4fy48zhFjG+XegVcIu7hsP1BuHGXw8vPUoC1ZASFyVDc1euHTfLr8Zg09eERH1SZeC/es37VJ+KXV pF72jo+QoTJkNVzmXn406jND06HzWEDT7LO9tL/W+r0Z7ocdAqPCqgsidWM77Sup+e40SaSfShPGk Gm1oxrQMmIA9QwS23UME92QibRkZHkksAnYjwMDCZuwjQaa7jXhQI6VKvmmerE8kbMXgdT9jH4qm0 ymCQU1MSM+RVcAuSnpFDxhJhTRg5P0o8YwioDWAtcQB/9K0GBtHLstYOidS1Cx2luz0vL9Tpc+83N 3KwIj2YUw+1FD2pojJE4/b/+MirZINybTVI57JWk/4W9dsArQXvThUQwqQH54OyoTyX1PWZOeZ5sX 5WHVT8zgEgHSIPYAAXGx7m9KA4OhvOBIXqxTe6GB+SdP5kl2EFyTMSDBQ9M6EsCujLQRPiAPfNNFY CaUhVAFr0tkIseqU/ThzZDsjYJgQEsvkFfyZE4GJk=; From: Christian Schoenebeck To: qemu-devel@nongnu.org Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Markus Armbruster , Markus Armbruster Subject: Re: [PATCH v4 18/19] 9p: Drop superfluous include of linux/limits.h Date: Thu, 19 Jan 2023 13:01:39 +0100 Message-ID: <2538017.PJiUfBrKnX@silver> In-Reply-To: <87ilh2vmib.fsf@pond.sub.org> References: <20230119065959.3104012-1-armbru@redhat.com> <5266030.ICAI56zT51@silver> <87ilh2vmib.fsf@pond.sub.org> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Received-SPF: pass client-ip=5.189.157.229; envelope-from=qemu_oss@crudebyte.com; helo=kylie.crudebyte.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 12:03:01 -0000 On Thursday, January 19, 2023 11:37:00 AM CET Markus Armbruster wrote: > Christian Schoenebeck writes: > > > On Thursday, January 19, 2023 7:59:58 AM CET Markus Armbruster wrote: > >> Signed-off-by: Markus Armbruster > >> --- > >> hw/9pfs/9p.c | 3 --- > >> 1 file changed, 3 deletions(-) > >> > >> diff --git a/hw/9pfs/9p.c b/hw/9pfs/9p.c > >> index 9621ec1341..aa736af380 100644 > >> --- a/hw/9pfs/9p.c > >> +++ b/hw/9pfs/9p.c > >> @@ -17,9 +17,6 @@ > >> */ > >> > >> #include "qemu/osdep.h" > >> -#ifdef CONFIG_LINUX > >> -#include > >> -#endif > >> #include > >> #include "hw/virtio/virtio.h" > >> #include "qapi/error.h" > >> > > > > Where did that base version come from? I don't see it anywhere in history. > > Last relevant change in context was a136d17590a. > > Current master (7ec8aeb6048) has > > #include "qemu/osdep.h" > #ifdef CONFIG_LINUX > #include > #else > #include > #endif > #include > > The previous commit changes it to > > #include "qemu/osdep.h" > #ifdef CONFIG_LINUX > #include > #endif > #include > > because "qemu/osdep.h" already includes . > > Clearer now? Ah, right I missed that in your previous patch. Thanks! Reviewed-by: Christian Schoenebeck Best regards, Christian Schoenebeck From MAILER-DAEMON Thu Jan 19 07:06:55 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pITh1-0002bA-2D for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 07:06:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pITgv-0002Ds-FS; Thu, 19 Jan 2023 07:06:50 -0500 Received: from kylie.crudebyte.com ([5.189.157.229]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pITgt-0002O6-7V; Thu, 19 Jan 2023 07:06:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=crudebyte.com; s=kylie; h=Content-Type:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Content-ID:Content-Description; bh=ohnYTkiG/JEnv7BTDnK67k+U1CDGbji+raBagx15Bhc=; b=ehCBkc+1OZ3ygLgkNvISH0vbQ/ RCKE1D+TmgKfJum6DYs9Vg3NKUr4LOXaKw0x37whdUu3/TH1uKzgqNb2jsTb5oFqLD5IPZeIc/P7i yruP6WpZG2NgFLDJ9gwHQ00Bdql558BQRCvQvlYIChjuoC/kL2hgrgEG76+WSaaammMna+7YkTI+q 6z1bWUaBXOrgWx92VzWAwwbjnAhSXB1bwqYrfvnZ59oHGL8Ooq4t63o94NN8ABHJfpMKxROe+4e6h JtWT5CoorNvT18Edr/GCfwIwNmoiHM3t35PScu3FXMELkAD19J3L+9uzzBN0upQR/i1om4FQjUwiQ rF2cnuA9VYWZgfHltl+O2T3H6cPXegIfIusGokocz9ak+Wq2RN9uCd8SMTU8l8uo2sNQOiav4K5Sl xqoIHluBkVTUeyzdmLEgeBkRTBxGUVcHVEgjX4EuRx1aoyHbDmSTgOm3nMRXcx549B2LYvR63DzMq s/nZgmunrxxXntqG9dcvoldVleRcnlFfeM6fd5su6WZEdnELXkoFR283GV09JNPUWXpKuNtsFdJw2 OIxi8ZPiTfRx8zY+EgLpT4HUaZ+W1IiXp77xgjzmY3gG3e//ZOZWvoy7OFdQLdVVznRK2anBYYsRL CODhpmv/fjurBzuhz1RTHAQq/4sKylTJZIg5XOArA=; From: Christian Schoenebeck To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Markus Armbruster Subject: Re: [PATCH v4 17/19] Don't include headers already included by qemu/osdep.h Date: Thu, 19 Jan 2023 13:06:26 +0100 Message-ID: <12588900.kcvoAOTtsJ@silver> In-Reply-To: <20230119065959.3104012-18-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-18-armbru@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Received-SPF: pass client-ip=5.189.157.229; envelope-from=qemu_oss@crudebyte.com; helo=kylie.crudebyte.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 12:06:53 -0000 On Thursday, January 19, 2023 7:59:57 AM CET Markus Armbruster wrote: > This commit was created with scripts/clean-includes. > > Signed-off-by: Markus Armbruster > --- For 9p changes: Acked-by: Christian Schoenebeck > backends/tpm/tpm_ioctl.h | 2 -- > fsdev/p9array.h | 2 -- > include/hw/misc/aspeed_lpc.h | 2 -- > include/hw/pci/pcie_doe.h | 1 - > include/qemu/async-teardown.h | 2 -- > include/qemu/dbus.h | 1 - > include/qemu/host-utils.h | 1 - > include/sysemu/event-loop-base.h | 1 - > accel/tcg/cpu-exec.c | 1 - > hw/9pfs/9p.c | 2 -- > hw/display/virtio-gpu-udmabuf.c | 1 - > hw/i2c/pmbus_device.c | 1 - > hw/remote/proxy-memory-listener.c | 1 - > hw/sensor/adm1272.c | 1 - > hw/usb/dev-storage-bot.c | 1 - > hw/usb/dev-storage-classic.c | 1 - > softmmu/vl.c | 2 -- > tcg/tci.c | 1 - > tests/unit/test-seccomp.c | 1 - > ui/udmabuf.c | 1 - > util/main-loop.c | 1 - > util/oslib-posix.c | 2 -- > 22 files changed, 29 deletions(-) > > diff --git a/backends/tpm/tpm_ioctl.h b/backends/tpm/tpm_ioctl.h > index e506ef5160..b1d31768a6 100644 > --- a/backends/tpm/tpm_ioctl.h > +++ b/backends/tpm/tpm_ioctl.h > @@ -12,8 +12,6 @@ > # define __USE_LINUX_IOCTL_DEFS > #endif > > -#include > -#include > #ifndef _WIN32 > #include > #include > diff --git a/fsdev/p9array.h b/fsdev/p9array.h > index 90e83a7c7b..50a1b15fe9 100644 > --- a/fsdev/p9array.h > +++ b/fsdev/p9array.h > @@ -27,8 +27,6 @@ > #ifndef QEMU_P9ARRAY_H > #define QEMU_P9ARRAY_H > > -#include "qemu/compiler.h" > - > /** > * P9Array provides a mechanism to access arrays in common C-style (e.g. by > * square bracket [] operator) in conjunction with reference variables that > diff --git a/include/hw/misc/aspeed_lpc.h b/include/hw/misc/aspeed_lpc.h > index fd228731d2..fa398959af 100644 > --- a/include/hw/misc/aspeed_lpc.h > +++ b/include/hw/misc/aspeed_lpc.h > @@ -12,8 +12,6 @@ > > #include "hw/sysbus.h" > > -#include > - > #define TYPE_ASPEED_LPC "aspeed.lpc" > #define ASPEED_LPC(obj) OBJECT_CHECK(AspeedLPCState, (obj), TYPE_ASPEED_LPC) > > diff --git a/include/hw/pci/pcie_doe.h b/include/hw/pci/pcie_doe.h > index ba4d8b03bd..87dc17dcef 100644 > --- a/include/hw/pci/pcie_doe.h > +++ b/include/hw/pci/pcie_doe.h > @@ -11,7 +11,6 @@ > #define PCIE_DOE_H > > #include "qemu/range.h" > -#include "qemu/typedefs.h" > #include "hw/register.h" > > /* > diff --git a/include/qemu/async-teardown.h b/include/qemu/async-teardown.h > index 092e7a37e7..b281da005b 100644 > --- a/include/qemu/async-teardown.h > +++ b/include/qemu/async-teardown.h > @@ -13,8 +13,6 @@ > #ifndef QEMU_ASYNC_TEARDOWN_H > #define QEMU_ASYNC_TEARDOWN_H > > -#include "config-host.h" > - > #ifdef CONFIG_LINUX > void init_async_teardown(void); > #endif > diff --git a/include/qemu/dbus.h b/include/qemu/dbus.h > index 08f00dfd53..81d3de8a5a 100644 > --- a/include/qemu/dbus.h > +++ b/include/qemu/dbus.h > @@ -15,7 +15,6 @@ > #include "qom/object.h" > #include "chardev/char.h" > #include "qemu/notify.h" > -#include "qemu/typedefs.h" > > /* glib/gio 2.68 */ > #define DBUS_METHOD_INVOCATION_HANDLED TRUE > diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h > index 88d476161c..3ce62bf4a5 100644 > --- a/include/qemu/host-utils.h > +++ b/include/qemu/host-utils.h > @@ -30,7 +30,6 @@ > #ifndef HOST_UTILS_H > #define HOST_UTILS_H > > -#include "qemu/compiler.h" > #include "qemu/bswap.h" > #include "qemu/int128.h" > > diff --git a/include/sysemu/event-loop-base.h b/include/sysemu/event-loop-base.h > index 2748bf6ae1..a6c24f1351 100644 > --- a/include/sysemu/event-loop-base.h > +++ b/include/sysemu/event-loop-base.h > @@ -14,7 +14,6 @@ > > #include "qom/object.h" > #include "block/aio.h" > -#include "qemu/typedefs.h" > > #define TYPE_EVENT_LOOP_BASE "event-loop-base" > OBJECT_DECLARE_TYPE(EventLoopBase, EventLoopBaseClass, > diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c > index 8927092537..dd8f54a415 100644 > --- a/accel/tcg/cpu-exec.c > +++ b/accel/tcg/cpu-exec.c > @@ -28,7 +28,6 @@ > #include "exec/exec-all.h" > #include "tcg/tcg.h" > #include "qemu/atomic.h" > -#include "qemu/compiler.h" > #include "qemu/timer.h" > #include "qemu/rcu.h" > #include "exec/log.h" > diff --git a/hw/9pfs/9p.c b/hw/9pfs/9p.c > index 072cf67956..9621ec1341 100644 > --- a/hw/9pfs/9p.c > +++ b/hw/9pfs/9p.c > @@ -19,8 +19,6 @@ > #include "qemu/osdep.h" > #ifdef CONFIG_LINUX > #include > -#else > -#include > #endif > #include > #include "hw/virtio/virtio.h" > diff --git a/hw/display/virtio-gpu-udmabuf.c b/hw/display/virtio-gpu-udmabuf.c > index 8bdf4bac6e..847fa4c0cc 100644 > --- a/hw/display/virtio-gpu-udmabuf.c > +++ b/hw/display/virtio-gpu-udmabuf.c > @@ -21,7 +21,6 @@ > #include "exec/ramblock.h" > #include "sysemu/hostmem.h" > #include > -#include > #include > #include "qemu/memfd.h" > #include "standard-headers/linux/udmabuf.h" > diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c > index 4071a88cfc..c3d6046784 100644 > --- a/hw/i2c/pmbus_device.c > +++ b/hw/i2c/pmbus_device.c > @@ -8,7 +8,6 @@ > > #include "qemu/osdep.h" > #include > -#include > #include "hw/i2c/pmbus_device.h" > #include "migration/vmstate.h" > #include "qemu/module.h" > diff --git a/hw/remote/proxy-memory-listener.c b/hw/remote/proxy-memory-listener.c > index eb9918fe72..18d96a1d04 100644 > --- a/hw/remote/proxy-memory-listener.c > +++ b/hw/remote/proxy-memory-listener.c > @@ -8,7 +8,6 @@ > > #include "qemu/osdep.h" > > -#include "qemu/compiler.h" > #include "qemu/int128.h" > #include "qemu/range.h" > #include "exec/memory.h" > diff --git a/hw/sensor/adm1272.c b/hw/sensor/adm1272.c > index 7310c769be..8f4a1c2cd4 100644 > --- a/hw/sensor/adm1272.c > +++ b/hw/sensor/adm1272.c > @@ -8,7 +8,6 @@ > */ > > #include "qemu/osdep.h" > -#include > #include "hw/i2c/pmbus_device.h" > #include "hw/irq.h" > #include "migration/vmstate.h" > diff --git a/hw/usb/dev-storage-bot.c b/hw/usb/dev-storage-bot.c > index b24b3148c2..1e5c5c711f 100644 > --- a/hw/usb/dev-storage-bot.c > +++ b/hw/usb/dev-storage-bot.c > @@ -8,7 +8,6 @@ > */ > > #include "qemu/osdep.h" > -#include "qemu/typedefs.h" > #include "qapi/error.h" > #include "hw/usb.h" > #include "hw/usb/desc.h" > diff --git a/hw/usb/dev-storage-classic.c b/hw/usb/dev-storage-classic.c > index 00f25bade2..84d19752b5 100644 > --- a/hw/usb/dev-storage-classic.c > +++ b/hw/usb/dev-storage-classic.c > @@ -8,7 +8,6 @@ > */ > > #include "qemu/osdep.h" > -#include "qemu/typedefs.h" > #include "qapi/error.h" > #include "qapi/visitor.h" > #include "hw/usb.h" > diff --git a/softmmu/vl.c b/softmmu/vl.c > index 9177d95d4e..5355a7fe5a 100644 > --- a/softmmu/vl.c > +++ b/softmmu/vl.c > @@ -136,8 +136,6 @@ > #include "qemu/guest-random.h" > #include "qemu/keyval.h" > > -#include "config-host.h" > - > #define MAX_VIRTIO_CONSOLES 1 > > typedef struct BlockdevOptionsQueueEntry { > diff --git a/tcg/tci.c b/tcg/tci.c > index 05a24163d3..e7ac74cab0 100644 > --- a/tcg/tci.c > +++ b/tcg/tci.c > @@ -21,7 +21,6 @@ > #include "exec/cpu_ldst.h" > #include "tcg/tcg-op.h" > #include "tcg/tcg-ldst.h" > -#include "qemu/compiler.h" > #include > > > diff --git a/tests/unit/test-seccomp.c b/tests/unit/test-seccomp.c > index 3d7771e46c..f02c79cafd 100644 > --- a/tests/unit/test-seccomp.c > +++ b/tests/unit/test-seccomp.c > @@ -25,7 +25,6 @@ > #include "qapi/error.h" > #include "qemu/module.h" > > -#include > #include > > static void test_seccomp_helper(const char *args, bool killed, > diff --git a/ui/udmabuf.c b/ui/udmabuf.c > index cebceb2610..cbf4357bb1 100644 > --- a/ui/udmabuf.c > +++ b/ui/udmabuf.c > @@ -8,7 +8,6 @@ > #include "qapi/error.h" > #include "ui/console.h" > > -#include > #include > > int udmabuf_fd(void) > diff --git a/util/main-loop.c b/util/main-loop.c > index 58f776a8c9..3c0f525192 100644 > --- a/util/main-loop.c > +++ b/util/main-loop.c > @@ -33,7 +33,6 @@ > #include "block/thread-pool.h" > #include "qemu/error-report.h" > #include "qemu/queue.h" > -#include "qemu/compiler.h" > #include "qom/object.h" > > #ifndef _WIN32 > diff --git a/util/oslib-posix.c b/util/oslib-posix.c > index 59a891b6a8..fd03fd32c8 100644 > --- a/util/oslib-posix.c > +++ b/util/oslib-posix.c > @@ -40,7 +40,6 @@ > #include "qemu/thread.h" > #include > #include "qemu/cutils.h" > -#include "qemu/compiler.h" > #include "qemu/units.h" > #include "qemu/thread-context.h" > > @@ -50,7 +49,6 @@ > > #ifdef __FreeBSD__ > #include > -#include > #include > #include > #endif > From MAILER-DAEMON Thu Jan 19 07:40:27 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIUDT-0006c0-AA for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 07:40:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with 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mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-58-Kz5evEtGNIGtp1FkSVvq0Q-1; Thu, 19 Jan 2023 07:40:15 -0500 X-MC-Unique: Kz5evEtGNIGtp1FkSVvq0Q-1 Received: from smtp.corp.redhat.com (int-mx09.intmail.prod.int.rdu2.redhat.com [10.11.54.9]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 6CEE53C16EB5; Thu, 19 Jan 2023 12:40:14 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id D67CF492C3E; Thu, 19 Jan 2023 12:40:13 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 6DB4221E6A28; Thu, 19 Jan 2023 13:40:12 +0100 (CET) From: Markus Armbruster To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 16/19] Fix non-first inclusions of qemu/osdep.h References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-17-armbru@redhat.com> <873586u4yj.fsf@pond.sub.org> Date: Thu, 19 Jan 2023 13:40:12 +0100 In-Reply-To: ("Philippe =?utf-8?Q?Mathieu-Daud=C3=A9=22's?= message of "Thu, 19 Jan 2023 12:52:02 +0100") Message-ID: <87cz7asno3.fsf@pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.1 on 10.11.54.9 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 12:40:25 -0000 Philippe Mathieu-Daud=C3=A9 writes: > On 19/1/23 12:41, Markus Armbruster wrote: >> Philippe Mathieu-Daud=C3=A9 writes: >>=20 >>> On 19/1/23 07:59, Markus Armbruster wrote: >>>> This commit was created with scripts/clean-includes. >>>> Signed-off-by: Markus Armbruster >> [...] >>=20 >>> Up to here: >>> >>> Reviewed-by: Philippe Mathieu-Daud=C3=A9 >>> >>>> diff --git a/util/async-teardown.c b/util/async-teardown.c >>>> index 62bfce1b3c..62cdeb0f20 100644 >>>> --- a/util/async-teardown.c >>>> +++ b/util/async-teardown.c >>>> @@ -10,16 +10,12 @@ >>>> * option) any later version. See the COPYING file in the top-leve= l directory. >>>> * >>>> */ >>>> -#include >>>> -#include >>>> -#include >>>> -#include >>>> -#include >>>> -#include >>>> -#include >>>> -#include >>>> #include "qemu/osdep.h" >>>> +#include >>>> +#include >>>> +#include >>>> + >>>> #include "qemu/async-teardown.h" >>> >>> This file has more changes. >> I'm not sure I understand. >> The patch does two related things: >> 1. It puts qemu/osdep.h first. The diff makes it look like we leave it >> in place and move other stuff across, but that's the same. >> 2. It deletes inclusions of headers qemu/osdep.h already includes: >> >> >> >> >> > > Ah, the other files get this done in the "Drop duplicate #include" patch. Right! From MAILER-DAEMON Thu Jan 19 08:00:30 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIUWr-0000bd-S4 for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 08:00:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIUWo-0000aM-Gx for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 08:00:27 -0500 Received: from mail-oa1-x35.google.com ([2001:4860:4864:20::35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIUWm-0003CV-Hw for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 08:00:26 -0500 Received: by mail-oa1-x35.google.com with SMTP id 586e51a60fabf-15ebfdf69adso2492840fac.0 for ; Thu, 19 Jan 2023 05:00:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=GMaoQO0f2teLiXR4j+0EQO0p2xPbhhpWKBDRZJSUv3k=; b=CWmwXcmwOSNBCBCjqe7dCrUlYVx4/sISzOctr7gATjkhmiqRkR8jRrhCKYZkAUWBX/ rhUWLkPF3bDC2yYFSS4gz2+P1kF5nSli+fQKc4c/71h8L2qU37sEPM5tjg4GHzOZgL8b RaVpqH/7Jm5FaA7JsMadZgzf3JmNUaMubNgNafA5JVp85cDZNMp5abbdkW18RKhqnDRT xmxBYIhyDuIdRAZGzhhAR6nUH0ZPxfSFSzvaem/iDl9fH5KczAixPvXJx7Vk8aXqxM0D 171tU5J88bWWkom6GZ+aGUP8VDUqJPHQCDd7CQxyt62GW6pptu/Xe5+2UHtcULJObxj+ U8gQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=GMaoQO0f2teLiXR4j+0EQO0p2xPbhhpWKBDRZJSUv3k=; b=XJc8rW8FVXWndYarlCGVmbyvq1/KwspXRZhPN4yDU3ISXDV1y4lvygOYFXQ/RLyfoi +m/ol9T/XxJHGWqBlE8HAsxQQfRIz3mGsmBhGVyPjOyB9CZdMKcLX9bckoZrCYQBUUT5 uHFCixUgn40PuhwG4k7XJqeiwONKWcBlBfE3hcuGxdv9N3OccegsWuGngYjlixpzpncH DbbchYbWIh0Z6qh79OI97q4TZSvuOMCFodfSSo2LdcteU0H6MZuBL4TVkva7WslCcIca STjCy/5fBwMrEslRL9B3IMV055fjLlq2w2fQPUrBiX3ItWb4k4uyrY7Wsu2/qq4Ggh8C 6ziQ== X-Gm-Message-State: AFqh2konN+R28nF3XdXnNmn6n3wybJlP9pa5nWaIlvCJZaS+hb8B6MwN Ro9OL5Z+guyOgfiquNESI1mgqg== X-Google-Smtp-Source: AMrXdXsL8hNfb3h/wuSfT5GWZ0cHJd8HR6/6kv1FzKU8y3+blx6ElNU47p9o0G4LeeCZt4xCvuybGQ== X-Received: by 2002:a05:6870:4947:b0:144:be2f:bea1 with SMTP id fl7-20020a056870494700b00144be2fbea1mr5379640oab.58.1674133222666; Thu, 19 Jan 2023 05:00:22 -0800 (PST) Received: from [192.168.68.107] ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id bx19-20020a056830601300b006619533d1ddsm13062746otb.76.2023.01.19.05.00.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Jan 2023 05:00:22 -0800 (PST) Message-ID: Date: Thu, 19 Jan 2023 10:00:18 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH v2 3/6] hw/riscv: simplify riscv_compute_fdt_addr() To: Alistair Francis Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, philmd@linaro.org References: <20230116173420.1146808-1-dbarboza@ventanamicro.com> <20230116173420.1146808-4-dbarboza@ventanamicro.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2001:4860:4864:20::35; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x35.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.094, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 13:00:27 -0000 On 1/18/23 23:23, Alistair Francis wrote: > On Tue, Jan 17, 2023 at 3:34 AM Daniel Henrique Barboza > wrote: >> All callers are using attributes from the MachineState object. Use a >> pointer to it instead of passing dram_size (which is always >> machine->ram_size) and fdt (always machine->fdt). >> >> Signed-off-by: Daniel Henrique Barboza >> --- >> hw/riscv/boot.c | 6 +++--- >> hw/riscv/microchip_pfsoc.c | 4 ++-- >> hw/riscv/sifive_u.c | 4 ++-- >> hw/riscv/spike.c | 4 ++-- >> hw/riscv/virt.c | 3 +-- >> include/hw/riscv/boot.h | 2 +- >> 6 files changed, 11 insertions(+), 12 deletions(-) >> >> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c >> index b213a32157..508da3f5c7 100644 >> --- a/hw/riscv/boot.c >> +++ b/hw/riscv/boot.c >> @@ -255,11 +255,11 @@ void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) >> * >> * The FDT is fdt_packed() during the calculation. >> */ >> -uint32_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size, >> - void *fdt) >> +uint32_t riscv_compute_fdt_addr(MachineState *machine, hwaddr dram_base) >> { >> + void *fdt = machine->fdt; >> uint64_t temp; >> - hwaddr dram_end = dram_base + mem_size; >> + hwaddr dram_end = dram_base + machine->ram_size; >> int ret = fdt_pack(fdt); >> int fdtsize; >> >> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c >> index dcdbc2cac3..a53e48e996 100644 >> --- a/hw/riscv/microchip_pfsoc.c >> +++ b/hw/riscv/microchip_pfsoc.c >> @@ -641,8 +641,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) >> } >> >> /* Compute the fdt load address in dram */ >> - fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base, >> - machine->ram_size, machine->fdt); >> + fdt_load_addr = riscv_compute_fdt_addr(machine, >> + memmap[MICROCHIP_PFSOC_DRAM_LO].base); > I don't think this is correct here. > > So, first up I understand we don't correctly handle this today, *but* > I see this change as a step in the wrong direction. > > The problem here is that ram is split over two areas. So if > machine->ram_size is larger then 0x40000000 it is going to overflow > MICROCHIP_PFSOC_DRAM_LO and jump to MICROCHIP_PFSOC_DRAM_HI > (0x1000000000). Yeah .... I'll add a new helper just to handle the microchip_pfsoc case which seems to be the only RISC-V board that has sparse RAM. > > So we really want something like this > > /* Compute the fdt load address in dram */ > if (machine->ram_size > memmap[MICROCHIP_PFSOC_DRAM_LO].size) { > fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_HI].base, > machine->ram_size - > memmap[MICROCHIP_PFSOC_DRAM_LO].size, > machine->fdt); > } else { > fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, > machine->ram_size, > machine->fdt); > } > > to handle overflowing MICROCHIP_PFSOC_DRAM_LO. While this patch is > going in the wrong direction and making that more difficult > > Alistair > > > >> riscv_load_fdt(fdt_load_addr, machine->fdt); >> >> /* Load the reset vector */ >> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c >> index 626d4dc2f3..ebfddf161d 100644 >> --- a/hw/riscv/sifive_u.c >> +++ b/hw/riscv/sifive_u.c >> @@ -616,8 +616,8 @@ static void sifive_u_machine_init(MachineState *machine) >> kernel_entry = 0; >> } >> >> - fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, >> - machine->ram_size, machine->fdt); >> + fdt_load_addr = riscv_compute_fdt_addr(machine, >> + memmap[SIFIVE_U_DEV_DRAM].base); >> riscv_load_fdt(fdt_load_addr, machine->fdt); >> >> if (!riscv_is_32bit(&s->soc.u_cpus)) { >> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c >> index 88b9fdfc36..afd581436b 100644 >> --- a/hw/riscv/spike.c >> +++ b/hw/riscv/spike.c >> @@ -324,8 +324,8 @@ static void spike_board_init(MachineState *machine) >> kernel_entry = 0; >> } >> >> - fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, >> - machine->ram_size, machine->fdt); >> + fdt_load_addr = riscv_compute_fdt_addr(machine, >> + memmap[SPIKE_DRAM].base); >> riscv_load_fdt(fdt_load_addr, machine->fdt); >> >> /* load the reset vector */ >> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c >> index 839dfaa125..cbba0b8930 100644 >> --- a/hw/riscv/virt.c >> +++ b/hw/riscv/virt.c >> @@ -1307,8 +1307,7 @@ static void virt_machine_done(Notifier *notifier, void *data) >> start_addr = virt_memmap[VIRT_FLASH].base; >> } >> >> - fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, >> - machine->ram_size, machine->fdt); >> + fdt_load_addr = riscv_compute_fdt_addr(machine, memmap[VIRT_DRAM].base); >> riscv_load_fdt(fdt_load_addr, machine->fdt); >> >> /* load the reset vector */ >> diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h >> index 9aea7b9c46..f933de88fb 100644 >> --- a/include/hw/riscv/boot.h >> +++ b/include/hw/riscv/boot.h >> @@ -47,7 +47,7 @@ target_ulong riscv_load_kernel(MachineState *machine, >> target_ulong firmware_end_addr, >> symbol_fn_t sym_cb); >> void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); >> -uint32_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, void *fdt); >> +uint32_t riscv_compute_fdt_addr(MachineState *machine, hwaddr dram_start); >> void riscv_load_fdt(uint32_t fdt_addr, void *fdt); >> void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, >> hwaddr saddr, >> -- >> 2.39.0 >> >> From MAILER-DAEMON Thu Jan 19 08:00:49 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIUXB-0000hy-4S for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 08:00:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIUX3-0000ft-T8 for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 08:00:41 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIUX1-0003FY-Rs for qemu-riscv@nongnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x336.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 13:00:42 -0000 Hi Alistair, Andrew, On Thu, Jan 19, 2023 at 1:25 AM Alistair Francis wrote: > > On Wed, Jan 18, 2023 at 10:19 PM Andrew Jones wrote: > > > > On Wed, Jan 18, 2023 at 10:28:46AM +1000, Alistair Francis wrote: > > > On Wed, Jan 18, 2023 at 2:32 AM Andrew Jones wrote: > > > > > > > > On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote: > > ... > > > > > + > > > > > + /* Get rid of 32-bit/64-bit incompatibility */ > > > > > + for (int i = 0; i < 16; ++i) { > > > > > + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > > > > > > > > If we ever define mode=1 for rv64, then 'sv32=on' will be incorrectly > > > > accepted as an alias. I think we should simply not define the sv32 > > > > property for rv64 nor the rv64-only modes for rv32. So, down in > > > > riscv_add_satp_mode_properties() we can add some > > > > > > > > #if defined(TARGET_RISCV32) > > > > ... > > > > #elif defined(TARGET_RISCV64) > > > > ... > > > > #endif > > > > > > Do not add any #if defined(TARGET_RISCV32) to QEMU. > > > > > > We are aiming for the riscv64-softmmu to be able to emulate 32-bit > > > CPUs and compile time macros are the wrong solution here. Instead you > > > can get the xlen of the hart and use that. > > > > > > > Does this mean we want to be able to do the following? > > > > qemu-system-riscv64 -cpu rv32,sv32=on ... > > That's the plan > > > > > If so, then can we move the object_property_add() for sv32 to > > rv32_base_cpu_init() and the rest to rv64_base_cpu_init()? > > Currently, that would be doing the same thing as proposed above, > > since those functions are under TARGET_RISCV* defines, but I guess > > the object_property_add()'s would then be in more or less the right > > places for when the 32-bit emulation support work is started. > > Sounds like a good idea :) What about riscv_any_cpu_init and riscv_host_cpu_init? > > Alistair > > > > > Thanks, > > drew From MAILER-DAEMON Thu Jan 19 09:18:24 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIVkG-0003UB-Dj for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:18:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIVjV-0003G2-BT; Thu, 19 Jan 2023 09:17:44 -0500 Received: from smtpout1.mo529.mail-out.ovh.net ([178.32.125.2]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIVjQ-0001gE-UZ; Thu, 19 Jan 2023 09:17:36 -0500 Received: from mxplan5.mail.ovh.net (unknown [10.109.143.58]) by mo529.mail-out.ovh.net (Postfix) with ESMTPS id 8568B155FAF28; Thu, 19 Jan 2023 15:17:17 +0100 (CET) Received: from kaod.org (37.59.142.110) by DAG8EX2.mxp5.local (172.16.2.72) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.16; Thu, 19 Jan 2023 15:17:15 +0100 Authentication-Results: garm.ovh; auth=pass (GARM-110S004dcc4925c-a362-485b-abf8-43f2d5f70c1c, 24E9BC4E0C08A0C5F41A8E8F02276630B3C3193A) smtp.auth=groug@kaod.org X-OVh-ClientIp: 78.197.208.248 Date: Thu, 19 Jan 2023 15:17:14 +0100 From: Greg Kurz To: Markus Armbruster CC: , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v4 19/19] Drop duplicate #include Message-ID: <20230119151714.30bde826@bahia> In-Reply-To: <20230119065959.3104012-20-armbru@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-20-armbru@redhat.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.35; 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envelope-from=groug@kaod.org; helo=smtpout1.mo529.mail-out.ovh.net X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:18:17 -0000 On Thu, 19 Jan 2023 07:59:59 +0100 Markus Armbruster wrote: > Tracked down with the help of scripts/clean-includes. > > Signed-off-by: Markus Armbruster > --- For ppc changes. Reviewed-by: Greg Kurz > include/hw/arm/fsl-imx6ul.h | 1 - > include/hw/arm/fsl-imx7.h | 1 - > backends/tpm/tpm_emulator.c | 1 - > hw/acpi/piix4.c | 1 - > hw/alpha/dp264.c | 1 - > hw/arm/virt.c | 1 - > hw/arm/xlnx-versal.c | 1 - > hw/block/pflash_cfi01.c | 1 - > hw/core/machine.c | 1 - > hw/hppa/machine.c | 1 - > hw/i386/acpi-build.c | 1 - > hw/loongarch/acpi-build.c | 1 - > hw/misc/macio/cuda.c | 1 - > hw/misc/macio/pmu.c | 1 - > hw/net/xilinx_axienet.c | 1 - > hw/ppc/ppc405_uc.c | 2 -- > hw/ppc/ppc440_bamboo.c | 1 - > hw/ppc/spapr_drc.c | 1 - > hw/rdma/vmw/pvrdma_dev_ring.c | 1 - > hw/remote/machine.c | 1 - > hw/remote/remote-obj.c | 1 - > hw/rtc/mc146818rtc.c | 1 - > hw/s390x/virtio-ccw-serial.c | 1 - > migration/postcopy-ram.c | 2 -- > softmmu/dirtylimit.c | 1 - > softmmu/runstate.c | 1 - > softmmu/vl.c | 1 - > target/loongarch/translate.c | 1 - > target/mips/tcg/translate.c | 1 - > target/nios2/translate.c | 2 -- > tests/unit/test-cutils.c | 1 - > ui/gtk.c | 1 - > util/oslib-posix.c | 4 ---- > 33 files changed, 39 deletions(-) > > diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h > index 7812e516a5..1952cb984d 100644 > --- a/include/hw/arm/fsl-imx6ul.h > +++ b/include/hw/arm/fsl-imx6ul.h > @@ -30,7 +30,6 @@ > #include "hw/timer/imx_gpt.h" > #include "hw/timer/imx_epit.h" > #include "hw/i2c/imx_i2c.h" > -#include "hw/gpio/imx_gpio.h" > #include "hw/sd/sdhci.h" > #include "hw/ssi/imx_spi.h" > #include "hw/net/imx_fec.h" > diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h > index 4e5e071864..355bd8ea83 100644 > --- a/include/hw/arm/fsl-imx7.h > +++ b/include/hw/arm/fsl-imx7.h > @@ -32,7 +32,6 @@ > #include "hw/timer/imx_gpt.h" > #include "hw/timer/imx_epit.h" > #include "hw/i2c/imx_i2c.h" > -#include "hw/gpio/imx_gpio.h" > #include "hw/sd/sdhci.h" > #include "hw/ssi/imx_spi.h" > #include "hw/net/imx_fec.h" > diff --git a/backends/tpm/tpm_emulator.c b/backends/tpm/tpm_emulator.c > index 49cc3d749d..2b440d2c9a 100644 > --- a/backends/tpm/tpm_emulator.c > +++ b/backends/tpm/tpm_emulator.c > @@ -35,7 +35,6 @@ > #include "sysemu/runstate.h" > #include "sysemu/tpm_backend.h" > #include "sysemu/tpm_util.h" > -#include "sysemu/runstate.h" > #include "tpm_int.h" > #include "tpm_ioctl.h" > #include "migration/blocker.h" > diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c > index 0a81f1ad93..df39f91294 100644 > --- a/hw/acpi/piix4.c > +++ b/hw/acpi/piix4.c > @@ -35,7 +35,6 @@ > #include "sysemu/xen.h" > #include "qapi/error.h" > #include "qemu/range.h" > -#include "hw/acpi/pcihp.h" > #include "hw/acpi/cpu_hotplug.h" > #include "hw/acpi/cpu.h" > #include "hw/hotplug.h" > diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c > index c502c8c62a..4161f559a7 100644 > --- a/hw/alpha/dp264.c > +++ b/hw/alpha/dp264.c > @@ -18,7 +18,6 @@ > #include "net/net.h" > #include "qemu/cutils.h" > #include "qemu/datadir.h" > -#include "net/net.h" > > static uint64_t cpu_alpha_superpage_to_phys(void *opaque, uint64_t addr) > { > diff --git a/hw/arm/virt.c b/hw/arm/virt.c > index ea2413a0ba..d3849d7233 100644 > --- a/hw/arm/virt.c > +++ b/hw/arm/virt.c > @@ -33,7 +33,6 @@ > #include "qemu/units.h" > #include "qemu/option.h" > #include "monitor/qdev.h" > -#include "qapi/error.h" > #include "hw/sysbus.h" > #include "hw/arm/boot.h" > #include "hw/arm/primecell.h" > diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c > index 57276e1506..69b1b99e93 100644 > --- a/hw/arm/xlnx-versal.c > +++ b/hw/arm/xlnx-versal.c > @@ -22,7 +22,6 @@ > #include "hw/misc/unimp.h" > #include "hw/arm/xlnx-versal.h" > #include "qemu/log.h" > -#include "hw/sysbus.h" > > #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") > #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") > diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c > index 0cbc2fb4cb..d11406eada 100644 > --- a/hw/block/pflash_cfi01.c > +++ b/hw/block/pflash_cfi01.c > @@ -45,7 +45,6 @@ > #include "qapi/error.h" > #include "qemu/error-report.h" > #include "qemu/bitops.h" > -#include "qemu/error-report.h" > #include "qemu/host-utils.h" > #include "qemu/log.h" > #include "qemu/module.h" > diff --git a/hw/core/machine.c b/hw/core/machine.c > index 616f3a207c..67cf9f9dcd 100644 > --- a/hw/core/machine.c > +++ b/hw/core/machine.c > @@ -39,7 +39,6 @@ > #include "exec/confidential-guest-support.h" > #include "hw/virtio/virtio.h" > #include "hw/virtio/virtio-pci.h" > -#include "qom/object_interfaces.h" > > GlobalProperty hw_compat_7_2[] = {}; > const size_t hw_compat_7_2_len = G_N_ELEMENTS(hw_compat_7_2); > diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c > index de1cc7ab71..7ac68c943f 100644 > --- a/hw/hppa/machine.c > +++ b/hw/hppa/machine.c > @@ -28,7 +28,6 @@ > #include "qapi/error.h" > #include "net/net.h" > #include "qemu/log.h" > -#include "net/net.h" > > #define MIN_SEABIOS_HPPA_VERSION 6 /* require at least this fw version */ > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > index 127c4e2d50..14f6f75454 100644 > --- a/hw/i386/acpi-build.c > +++ b/hw/i386/acpi-build.c > @@ -76,7 +76,6 @@ > > #include "hw/acpi/hmat.h" > #include "hw/acpi/viot.h" > -#include "hw/acpi/cxl.h" > > #include CONFIG_DEVICES > > diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c > index c2b237736d..f551296a0e 100644 > --- a/hw/loongarch/acpi-build.c > +++ b/hw/loongarch/acpi-build.c > @@ -22,7 +22,6 @@ > /* Supported chipsets: */ > #include "hw/pci-host/ls7a.h" > #include "hw/loongarch/virt.h" > -#include "hw/acpi/aml-build.h" > > #include "hw/acpi/utils.h" > #include "hw/acpi/pci.h" > diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c > index 853e88bfed..29a8e5ed19 100644 > --- a/hw/misc/macio/cuda.c > +++ b/hw/misc/macio/cuda.c > @@ -30,7 +30,6 @@ > #include "hw/input/adb.h" > #include "hw/misc/mos6522.h" > #include "hw/misc/macio/cuda.h" > -#include "qapi/error.h" > #include "qemu/timer.h" > #include "sysemu/runstate.h" > #include "sysemu/rtc.h" > diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c > index 97ef8c771b..5a788e595a 100644 > --- a/hw/misc/macio/pmu.c > +++ b/hw/misc/macio/pmu.c > @@ -36,7 +36,6 @@ > #include "hw/misc/mos6522.h" > #include "hw/misc/macio/gpio.h" > #include "hw/misc/macio/pmu.h" > -#include "qapi/error.h" > #include "qemu/timer.h" > #include "sysemu/runstate.h" > #include "sysemu/rtc.h" > diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c > index 990ff3a1c2..673af7da26 100644 > --- a/hw/net/xilinx_axienet.c > +++ b/hw/net/xilinx_axienet.c > @@ -31,7 +31,6 @@ > #include "net/net.h" > #include "net/checksum.h" > > -#include "hw/hw.h" > #include "hw/irq.h" > #include "hw/qdev-properties.h" > #include "hw/stream.h" > diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c > index c973cfb04e..0cc68178ad 100644 > --- a/hw/ppc/ppc405_uc.c > +++ b/hw/ppc/ppc405_uc.c > @@ -38,8 +38,6 @@ > #include "sysemu/sysemu.h" > #include "exec/address-spaces.h" > #include "hw/intc/ppc-uic.h" > -#include "hw/qdev-properties.h" > -#include "qapi/error.h" > #include "trace.h" > > /*****************************************************************************/ > diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c > index 81d71adf34..2880c81cb1 100644 > --- a/hw/ppc/ppc440_bamboo.c > +++ b/hw/ppc/ppc440_bamboo.c > @@ -13,7 +13,6 @@ > > #include "qemu/osdep.h" > #include "qemu/units.h" > -#include "qemu/error-report.h" > #include "qemu/datadir.h" > #include "qemu/error-report.h" > #include "net/net.h" > diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c > index 4923435a8b..b5c400a94d 100644 > --- a/hw/ppc/spapr_drc.c > +++ b/hw/ppc/spapr_drc.c > @@ -17,7 +17,6 @@ > #include "hw/ppc/spapr_drc.h" > #include "qom/object.h" > #include "migration/vmstate.h" > -#include "qapi/error.h" > #include "qapi/qapi-events-qdev.h" > #include "qapi/visitor.h" > #include "qemu/error-report.h" > diff --git a/hw/rdma/vmw/pvrdma_dev_ring.c b/hw/rdma/vmw/pvrdma_dev_ring.c > index 598e6adc5e..30ce22a5be 100644 > --- a/hw/rdma/vmw/pvrdma_dev_ring.c > +++ b/hw/rdma/vmw/pvrdma_dev_ring.c > @@ -14,7 +14,6 @@ > */ > > #include "qemu/osdep.h" > -#include "qemu/cutils.h" > #include "hw/pci/pci.h" > #include "cpu.h" > #include "qemu/cutils.h" > diff --git a/hw/remote/machine.c b/hw/remote/machine.c > index 519f855ec1..fdc6c441bb 100644 > --- a/hw/remote/machine.c > +++ b/hw/remote/machine.c > @@ -22,7 +22,6 @@ > #include "hw/remote/iohub.h" > #include "hw/remote/iommu.h" > #include "hw/qdev-core.h" > -#include "hw/remote/iommu.h" > #include "hw/remote/vfio-user-obj.h" > #include "hw/pci/msi.h" > > diff --git a/hw/remote/remote-obj.c b/hw/remote/remote-obj.c > index 333e5ac443..65b6f7cc86 100644 > --- a/hw/remote/remote-obj.c > +++ b/hw/remote/remote-obj.c > @@ -12,7 +12,6 @@ > #include "qemu/error-report.h" > #include "qemu/notify.h" > #include "qom/object_interfaces.h" > -#include "hw/qdev-core.h" > #include "io/channel.h" > #include "hw/qdev-core.h" > #include "hw/remote/machine.h" > diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c > index bc1192b7ae..ba612a151d 100644 > --- a/hw/rtc/mc146818rtc.c > +++ b/hw/rtc/mc146818rtc.c > @@ -43,7 +43,6 @@ > #include "qapi/error.h" > #include "qapi/qapi-events-misc.h" > #include "qapi/visitor.h" > -#include "hw/rtc/mc146818rtc_regs.h" > > //#define DEBUG_CMOS > //#define DEBUG_COALESCED > diff --git a/hw/s390x/virtio-ccw-serial.c b/hw/s390x/virtio-ccw-serial.c > index bf8057880f..8f8d2302f8 100644 > --- a/hw/s390x/virtio-ccw-serial.c > +++ b/hw/s390x/virtio-ccw-serial.c > @@ -15,7 +15,6 @@ > #include "hw/qdev-properties.h" > #include "hw/virtio/virtio-serial.h" > #include "virtio-ccw.h" > -#include "hw/virtio/virtio-serial.h" > > #define TYPE_VIRTIO_SERIAL_CCW "virtio-serial-ccw" > OBJECT_DECLARE_SIMPLE_TYPE(VirtioSerialCcw, VIRTIO_SERIAL_CCW) > diff --git a/migration/postcopy-ram.c b/migration/postcopy-ram.c > index b9a37ef255..8b7d1af75d 100644 > --- a/migration/postcopy-ram.c > +++ b/migration/postcopy-ram.c > @@ -17,7 +17,6 @@ > */ > > #include "qemu/osdep.h" > -#include "qemu/rcu.h" > #include "qemu/madvise.h" > #include "exec/target_page.h" > #include "migration.h" > @@ -34,7 +33,6 @@ > #include "hw/boards.h" > #include "exec/ramblock.h" > #include "socket.h" > -#include "qemu-file.h" > #include "yank_functions.h" > #include "tls.h" > > diff --git a/softmmu/dirtylimit.c b/softmmu/dirtylimit.c > index 12668555f2..c56f0f58c8 100644 > --- a/softmmu/dirtylimit.c > +++ b/softmmu/dirtylimit.c > @@ -11,7 +11,6 @@ > */ > > #include "qemu/osdep.h" > -#include "qapi/error.h" > #include "qemu/main-loop.h" > #include "qapi/qapi-commands-migration.h" > #include "qapi/qmp/qdict.h" > diff --git a/softmmu/runstate.c b/softmmu/runstate.c > index cab9f6fc07..f9ad88e6a7 100644 > --- a/softmmu/runstate.c > +++ b/softmmu/runstate.c > @@ -41,7 +41,6 @@ > #include "qapi/qapi-commands-run-state.h" > #include "qapi/qapi-events-run-state.h" > #include "qemu/error-report.h" > -#include "qemu/log.h" > #include "qemu/job.h" > #include "qemu/log.h" > #include "qemu/module.h" > diff --git a/softmmu/vl.c b/softmmu/vl.c > index 5355a7fe5a..b2ee3fee3f 100644 > --- a/softmmu/vl.c > +++ b/softmmu/vl.c > @@ -129,7 +129,6 @@ > #include "qapi/qapi-commands-misc.h" > #include "qapi/qapi-visit-qom.h" > #include "qapi/qapi-commands-ui.h" > -#include "qapi/qmp/qdict.h" > #include "block/qdict.h" > #include "qapi/qmp/qerror.h" > #include "sysemu/iothread.h" > diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c > index 38ced69803..72a6275665 100644 > --- a/target/loongarch/translate.c > +++ b/target/loongarch/translate.c > @@ -12,7 +12,6 @@ > #include "exec/helper-proto.h" > #include "exec/helper-gen.h" > > -#include "exec/translator.h" > #include "exec/log.h" > #include "qemu/qemu-print.h" > #include "fpu/softfloat.h" > diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c > index 624e6b7786..aa12bb708a 100644 > --- a/target/mips/tcg/translate.c > +++ b/target/mips/tcg/translate.c > @@ -32,7 +32,6 @@ > #include "semihosting/semihost.h" > > #include "trace.h" > -#include "exec/translator.h" > #include "exec/log.h" > #include "qemu/qemu-print.h" > #include "fpu_helper.h" > diff --git a/target/nios2/translate.c b/target/nios2/translate.c > index 4db8b47744..7aee65a089 100644 > --- a/target/nios2/translate.c > +++ b/target/nios2/translate.c > @@ -938,8 +938,6 @@ static const char * const cr_regnames[NUM_CR_REGS] = { > }; > #endif > > -#include "exec/gen-icount.h" > - > /* generate intermediate code for basic block 'tb'. */ > static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) > { > diff --git a/tests/unit/test-cutils.c b/tests/unit/test-cutils.c > index 2126b46391..3c4f875420 100644 > --- a/tests/unit/test-cutils.c > +++ b/tests/unit/test-cutils.c > @@ -26,7 +26,6 @@ > */ > > #include "qemu/osdep.h" > -#include "qemu/units.h" > #include "qemu/cutils.h" > #include "qemu/units.h" > > diff --git a/ui/gtk.c b/ui/gtk.c > index 4817623c8f..7f752d8b7d 100644 > --- a/ui/gtk.c > +++ b/ui/gtk.c > @@ -53,7 +53,6 @@ > #include > > #include "trace.h" > -#include "qemu/cutils.h" > #include "ui/input.h" > #include "sysemu/runstate.h" > #include "sysemu/sysemu.h" > diff --git a/util/oslib-posix.c b/util/oslib-posix.c > index fd03fd32c8..77d882e681 100644 > --- a/util/oslib-posix.c > +++ b/util/oslib-posix.c > @@ -59,10 +59,6 @@ > > #include "qemu/mmap-alloc.h" > > -#ifdef CONFIG_DEBUG_STACK_USAGE > -#include "qemu/error-report.h" > -#endif > - > #define MAX_MEM_PREALLOC_THREAD_COUNT 16 > > struct MemsetThread; From MAILER-DAEMON Thu Jan 19 09:32:44 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIVy7-0004na-S0 for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:32:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIVxk-0004YJ-QS; Thu, 19 Jan 2023 09:32:22 -0500 Received: from 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([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id g6-20020a4aa706000000b004f9cd1e42d3sm3702525oom.26.2023.01.19.06.32.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Jan 2023 06:32:13 -0800 (PST) Sender: Guenter Roeck Message-ID: <01c6a8f8-881b-66b2-781b-c334e3a9fecc@roeck-us.net> Date: Thu, 19 Jan 2023 06:32:10 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: completion timeouts with pin-based interrupts in QEMU hw/nvme Content-Language: en-US To: Klaus Jensen , Keith Busch Cc: Alistair Francis , Peter Maydell , Jens Axboe , Christoph Hellwig , Sagi Grimberg , linux-nvme@lists.infradead.org, qemu-block@nongnu.org, qemu-devel@nongnu.org, qemu-riscv@nongnu.org, =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= References: <20230117192115.GA2958104@roeck-us.net> From: Guenter Roeck In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c2e; envelope-from=groeck7@gmail.com; helo=mail-oo1-xc2e.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, NICE_REPLY_A=-0.094, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:32:43 -0000 On 1/19/23 00:02, Klaus Jensen wrote: > On Jan 19 08:28, Klaus Jensen wrote: >> On Jan 18 21:03, Keith Busch wrote: >>> On Thu, Jan 19, 2023 at 01:10:57PM +1000, Alistair Francis wrote: >>>> On Thu, Jan 19, 2023 at 12:44 PM Keith Busch wrote: >>>>> >>>>> Further up, it says the "interrupt gateway" is responsible for >>>>> forwarding new interrupt requests while the level remains asserted, but >>>>> it doesn't look like anything is handling that, which essentially turns >>>>> this into an edge interrupt. Am I missing something, or is this really >>>>> not being handled? >>>> >>>> Yeah, that wouldn't be handled. In QEMU the PLIC relies on QEMUs >>>> internal GPIO lines to trigger an interrupt. So with the current setup >>>> we only support edge triggered interrupts. >>> >>> Thanks for confirming! >>> >>> Klaus, >>> I think we can justify introducing a work-around in the emulated device >>> now. My previous proposal with pci_irq_pulse() is no good since it does >>> assert+deassert, but it needs to be the other way around, so please >>> don't considert that one. >>> >>> Also, we ought to revisit the intms/intmc usage in the linux driver for >>> threaded interrupts. >> >> +CC: qemu-riscv >> >> Keith, >> >> Thanks for digging into this! >> >> Yeah, you are probably right that we should only use the intms/intmc >> changes in the use_threaded_interrupts case, not in general. While my >> RFC patch does seem to "fix" this, it is just a workaround as your >> analysis indicate. > > +CC: Philippe, > > I am observing these timeouts/aborts on mips as well, so I guess that > emulation could suffer from the same issue? I suspect it does. In my case, I have an Ethernet controller on the same interrupt line as the NVME controller, and it looks like one of the interrupts gets lost if both controllers raise an interrupt at the same time. The suggested workarounds "fix" the problem, but that doesn't seem to be the correct solution. Guenter From MAILER-DAEMON Thu Jan 19 09:36:31 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW1n-0007N5-KH for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:36:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1R-000798-4r for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:15 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1M-0006zW-LP for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:08 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1F-007gSL-Pz; Thu, 19 Jan 2023 14:35:58 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Nazar Kazakov Subject: [RFC PATCH 09/39] target/riscv: Add vandn.[vv, vx, vi] decoding, translation and execution support Date: Thu, 19 Jan 2023 14:34:58 +0000 Message-Id: <20230119143528.1290950-10-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:16 -0000 From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h | 9 +++++++++ target/riscv/insn32.decode | 3 +++ target/riscv/insn_trans/trans_rvzvkb.c.inc | 5 +++++ target/riscv/vcrypto_helper.c | 19 +++++++++++++++++++ 4 files changed, 36 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c980d52828..5de615ea78 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1171,3 +1171,12 @@ DEF_HELPER_5(vbrev8_v_b, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_w, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_d, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vandn_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vv_d, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 342199abc0..d6f5e4d198 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -904,3 +904,6 @@ vror_vi 010100 . ..... ..... 011 ..... 1010111 @r_vm vror_vi2 010101 . ..... ..... 011 ..... 1010111 @r_vm vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm +vandn_vi 000001 . ..... ..... 011 ..... 1010111 @r_vm +vandn_vv 000001 . ..... ..... 000 ..... 1010111 @r_vm +vandn_vx 000001 . ..... ..... 100 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn_trans/trans_rvzvkb.c.inc index b0c8347ab1..9f75bb3d39 100644 --- a/target/riscv/insn_trans/trans_rvzvkb.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc @@ -147,6 +147,11 @@ static bool trans_##NAME(DisasContext *s, arg_rmr * a) \ return false; \ } + +GEN_OPIVV_TRANS(vandn_vv, zvkb_vv_check) +GEN_OPIVX_TRANS(vandn_vx, zvkb_vx_check) +GEN_OPIVI_TRANS(vandn_vi, IMM_SX, vandn_vx, zvkb_vx_check) + static bool vxrev8_check(DisasContext *s, arg_rmr *a) { return require_rvv(s) && diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index b09fe5fa2a..900e68dfb0 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -135,3 +135,22 @@ GEN_VEXT_V(vrev8_v_b, 1) GEN_VEXT_V(vrev8_v_h, 2) GEN_VEXT_V(vrev8_v_w, 4) GEN_VEXT_V(vrev8_v_d, 8) + +#define DO_ANDN(a, b) ((b) & ~(a)) +RVVCALL(OPIVV2, vandn_vv_b, OP_UUU_B, H1, H1, H1, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_h, OP_UUU_H, H2, H2, H2, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_w, OP_UUU_W, H4, H4, H4, DO_ANDN) +RVVCALL(OPIVV2, vandn_vv_d, OP_UUU_D, H8, H8, H8, DO_ANDN) +GEN_VEXT_VV(vandn_vv_b, 1) +GEN_VEXT_VV(vandn_vv_h, 2) +GEN_VEXT_VV(vandn_vv_w, 4) +GEN_VEXT_VV(vandn_vv_d, 8) + +RVVCALL(OPIVX2, vandn_vx_b, OP_UUU_B, H1, H1, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_h, OP_UUU_H, H2, H2, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_w, OP_UUU_W, H4, H4, DO_ANDN) +RVVCALL(OPIVX2, vandn_vx_d, OP_UUU_D, H8, H8, DO_ANDN) +GEN_VEXT_VX(vandn_vx_b, 1) +GEN_VEXT_VX(vandn_vx_h, 2) +GEN_VEXT_VX(vandn_vx_w, 4) +GEN_VEXT_VX(vandn_vx_d, 8) -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:36:31 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW1n-0007OQ-Qp for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:36:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1M-00074M-Se for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:09 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1F-0006yj-IF for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:02 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1C-007gSL-5g; Thu, 19 Jan 2023 14:35:55 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Nazar Kazakov Subject: [RFC PATCH 01/39] target/riscv: add zvkb cpu property Date: Thu, 19 Jan 2023 14:34:50 +0000 Message-Id: <20230119143528.1290950-2-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:15 -0000 X-List-Received-Date: Thu, 19 Jan 2023 14:36:15 -0000 From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + 2 files changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cc75ca7667..ec1dbd923d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -100,6 +100,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), + ISA_EXT_DATA_ENTRY(zvkb, true, PRIV_VERSION_1_12_0, ext_zvkb), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f5609b62a2..d4824ad0bb 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -461,6 +461,7 @@ struct RISCVCPUConfig { bool ext_zhinxmin; bool ext_zve32f; bool ext_zve64f; + bool ext_zvkb; bool ext_zmmul; bool ext_smaia; bool ext_ssaia; -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:36:40 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW1o-0007Pg-1P for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:36:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1R-000796-3t for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:15 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1J-0006yw-IW for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:08 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1D-007gSL-Ch; Thu, 19 Jan 2023 14:35:56 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence Hunter Subject: [RFC PATCH 04/39] target/riscv: Add vclmulh.vv decoding, translation and execution support Date: Thu, 19 Jan 2023 14:34:53 +0000 Message-Id: <20230119143528.1290950-5-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:16 -0000 Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 + target/riscv/vcrypto_helper.c | 12 ++++++++++++ 4 files changed, 15 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 6c786ef6f3..a155272701 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1140,3 +1140,4 @@ DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) /* Vector crypto functions */ DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4a7421354d..e26ea1df08 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -894,3 +894,4 @@ sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes # *** RV64 Zvkb vector crypto extension *** vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm +vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn_trans/trans_rvzvkb.c.inc index 6e8b81136c..19ce4c7431 100644 --- a/target/riscv/insn_trans/trans_rvzvkb.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc @@ -39,6 +39,7 @@ static bool vclmul_vv_check(DisasContext *s, arg_rmrr *a) } GEN_VV_MASKED_TRANS(vclmul_vv, vclmul_vv_check) +GEN_VV_MASKED_TRANS(vclmulh_vv, vclmul_vv_check) #define GEN_VX_MASKED_TRANS(NAME, CHECK) \ static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index c453d348ad..022b941131 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -31,5 +31,17 @@ static void do_vclmul_vx(void *vd, target_long rs1, void *vs2, int i) ((uint64_t *)vd)[i] = result; } +static void do_vclmulh_vv(void *vd, void *vs1, void *vs2, int i) +{ + __uint128_t result = 0; + for (int j = 63; j >= 0; j--) { + if ((((uint64_t *)vs1)[i] >> j) & 1) { + result ^= (((__uint128_t)(((uint64_t *)vs2)[i])) << j); + } + } + ((uint64_t *)vd)[i] = (result >> 64); +} + GEN_VEXT_VV(vclmul_vv, 8) GEN_VEXT_VX(vclmul_vx, 8) +GEN_VEXT_VV(vclmulh_vv, 8) -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:36:54 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW1w-0007Wr-W4 for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:36:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1Q-000793-EK for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:15 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1J-0006yz-IR for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:07 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1C-007gSL-Hr; Thu, 19 Jan 2023 14:35:55 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence Hunter , Nazar Kazakov , Kiran Ostrolenk , Max Chou Subject: [RFC PATCH 02/39] target/riscv: Add vclmul.vv decoding, translation and execution support Date: Thu, 19 Jan 2023 14:34:51 +0000 Message-Id: <20230119143528.1290950-3-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:16 -0000 Co-authored-by: Nazar Kazakov Co-authored-by: Kiran Ostrolenk Co-authored-by: Max Chou Signed-off-by: Max Chou Signed-off-by: Kiran Ostrolenk Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 3 + target/riscv/insn32.decode | 3 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 41 +++++++ target/riscv/meson.build | 4 +- target/riscv/translate.c | 1 + target/riscv/vcrypto_helper.c | 23 ++++ target/riscv/vector_helper.c | 120 +-------------------- target/riscv/vector_internals.c | 39 +++++++ target/riscv/vector_internals.h | 116 ++++++++++++++++++++ 9 files changed, 230 insertions(+), 120 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvzvkb.c.inc create mode 100644 target/riscv/vcrypto_helper.c create mode 100644 target/riscv/vector_internals.c create mode 100644 target/riscv/vector_internals.h diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 227c7122ef..e9127c9ccb 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1136,3 +1136,6 @@ DEF_HELPER_FLAGS_1(aes64im, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_3(sm4ed, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) + +/* Vector crypto functions */ +DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b7e7613ea2..5ddee69d60 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -890,3 +890,6 @@ sm3p1 00 01000 01001 ..... 001 ..... 0010011 @r2 # *** RV32 Zksed Standard Extension *** sm4ed .. 11000 ..... ..... 000 ..... 0110011 @k_aes sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes + +# *** RV64 Zvkb vector crypto extension *** +vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn_trans/trans_rvzvkb.c.inc new file mode 100644 index 0000000000..fb1995f737 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc @@ -0,0 +1,41 @@ +#define GEN_VV_MASKED_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr * a) \ +{ \ + if (CHECK(s, a)) { \ + uint32_t data = 0; \ + TCGLabel *over = gen_new_label(); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ + \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data = FIELD_DP32(data, VDATA, VTA, s->vta); \ + data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \ + data = FIELD_DP32(data, VDATA, VMA, s->vma); \ + \ + tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs1), \ + vreg_ofs(s, a->rs2), cpu_env, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ + gen_helper_##NAME); \ + \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +static bool zvkb_vv_check(DisasContext *s, arg_rmrr *a) +{ + return opivv_check(s, a) && + s->cfg_ptr->ext_zvkb == true; +} + +static bool vclmul_vv_check(DisasContext *s, arg_rmrr *a) +{ + return zvkb_vv_check(s, a) && s->sew == MO_64; +} + +GEN_VV_MASKED_TRANS(vclmul_vv, vclmul_vv_check) diff --git a/target/riscv/meson.build b/target/riscv/meson.build index ba25164d74..5313b01e5f 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -15,10 +15,12 @@ riscv_ss.add(files( 'gdbstub.c', 'op_helper.c', 'vector_helper.c', + 'vector_internals.c', 'bitmanip_helper.c', 'translate.c', 'm128_helper.c', - 'crypto_helper.c' + 'crypto_helper.c', + 'vcrypto_helper.c' )) riscv_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c'), if_false: files('kvm-stub.c')) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index df38db7553..71684c10f3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1063,6 +1063,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_rvzawrs.c.inc" #include "insn_trans/trans_rvzfh.c.inc" #include "insn_trans/trans_rvk.c.inc" +#include "insn_trans/trans_rvzvkb.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c new file mode 100644 index 0000000000..8a11e56754 --- /dev/null +++ b/target/riscv/vcrypto_helper.c @@ -0,0 +1,23 @@ +#include "qemu/osdep.h" +#include "qemu/host-utils.h" +#include "qemu/bitops.h" +#include "cpu.h" +#include "exec/memop.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "tcg/tcg-gvec-desc.h" +#include "internals.h" +#include "vector_internals.h" + +static void do_vclmul_vv(void *vd, void *vs1, void *vs2, int i) +{ + uint64_t result = 0; + for (int j = 63; j >= 0; j--) { + if ((((uint64_t *)vs1)[i] >> j) & 1) { + result ^= (((uint64_t *)vs2)[i] << j); + } + } + ((uint64_t *)vd)[i] = result; +} + +GEN_VEXT_VV(vclmul_vv, 8) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 00de879787..def1b21414 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -26,6 +26,7 @@ #include "fpu/softfloat.h" #include "tcg/tcg-gvec-desc.h" #include "internals.h" +#include "vector_internals.h" #include target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, @@ -95,48 +96,6 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, #define H8(x) (x) #endif -static inline uint32_t vext_nf(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, NF); -} - -static inline uint32_t vext_vm(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, VM); -} - -/* - * Encode LMUL to lmul as following: - * LMUL vlmul lmul - * 1 000 0 - * 2 001 1 - * 4 010 2 - * 8 011 3 - * - 100 - - * 1/8 101 -3 - * 1/4 110 -2 - * 1/2 111 -1 - */ -static inline int32_t vext_lmul(uint32_t desc) -{ - return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); -} - -static inline uint32_t vext_vta(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, VTA); -} - -static inline uint32_t vext_vma(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, VMA); -} - -static inline uint32_t vext_vta_all_1s(uint32_t desc) -{ - return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S); -} - /* * Get the maximum number of elements can be operated. * @@ -155,21 +114,6 @@ static inline uint32_t vext_max_elems(uint32_t desc, uint32_t log2_esz) return scale < 0 ? vlenb >> -scale : vlenb << scale; } -/* - * Get number of total elements, including prestart, body and tail elements. - * Note that when LMUL < 1, the tail includes the elements past VLMAX that - * are held in the same vector register. - */ -static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc, - uint32_t esz) -{ - uint32_t vlenb = simd_maxsz(desc); - uint32_t sew = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW); - int8_t emul = ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 : - ctzl(esz) - ctzl(sew) + vext_lmul(desc); - return (vlenb << emul) / esz; -} - static inline target_ulong adjust_addr(CPURISCVState *env, target_ulong addr) { return (addr & env->cur_pmmask) | env->cur_pmbase; @@ -202,20 +146,6 @@ static void probe_pages(CPURISCVState *env, target_ulong addr, } } -/* set agnostic elements to 1s */ -static void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt, - uint32_t tot) -{ - if (is_agnostic == 0) { - /* policy undisturbed */ - return; - } - if (tot - cnt == 0) { - return; - } - memset(base + cnt, -1, tot - cnt); -} - static inline void vext_set_elem_mask(void *v0, int index, uint8_t value) { @@ -225,18 +155,6 @@ static inline void vext_set_elem_mask(void *v0, int index, ((uint64_t *)v0)[idx] = deposit64(old, pos, 1, value); } -/* - * Earlier designs (pre-0.9) had a varying number of bits - * per mask value (MLEN). In the 0.9 design, MLEN=1. - * (Section 4.5) - */ -static inline int vext_elem_mask(void *v0, int index) -{ - int idx = index / 64; - int pos = index % 64; - return (((uint64_t *)v0)[idx] >> pos) & 1; -} - /* elements operations for load and store */ typedef void vext_ldst_elem_fn(CPURISCVState *env, target_ulong addr, uint32_t idx, void *vd, uintptr_t retaddr); @@ -800,8 +718,6 @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) #define NOP_UUU_H uint16_t, uint16_t, uint32_t, uint16_t, uint32_t #define NOP_UUU_W uint32_t, uint32_t, uint64_t, uint32_t, uint64_t -/* operation of two vector elements */ -typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); #define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ @@ -822,40 +738,6 @@ RVVCALL(OPIVV2, vsub_vv_h, OP_SSS_H, H2, H2, H2, DO_SUB) RVVCALL(OPIVV2, vsub_vv_w, OP_SSS_W, H4, H4, H4, DO_SUB) RVVCALL(OPIVV2, vsub_vv_d, OP_SSS_D, H8, H8, H8, DO_SUB) -static void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, - CPURISCVState *env, uint32_t desc, - opivv2_fn *fn, uint32_t esz) -{ - uint32_t vm = vext_vm(desc); - uint32_t vl = env->vl; - uint32_t total_elems = vext_get_total_elems(env, desc, esz); - uint32_t vta = vext_vta(desc); - uint32_t vma = vext_vma(desc); - uint32_t i; - - for (i = env->vstart; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, i)) { - /* set masked-off elements to 1s */ - vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); - continue; - } - fn(vd, vs1, vs2, i); - } - env->vstart = 0; - /* set tail elements to 1s */ - vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); -} - -/* generate the helpers for OPIVV */ -#define GEN_VEXT_VV(NAME, ESZ) \ -void HELPER(NAME)(void *vd, void *v0, void *vs1, \ - void *vs2, CPURISCVState *env, \ - uint32_t desc) \ -{ \ - do_vext_vv(vd, v0, vs1, vs2, env, desc, \ - do_##NAME, ESZ); \ -} - GEN_VEXT_VV(vadd_vv_b, 1) GEN_VEXT_VV(vadd_vv_h, 2) GEN_VEXT_VV(vadd_vv_w, 4) diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c new file mode 100644 index 0000000000..a264797882 --- /dev/null +++ b/target/riscv/vector_internals.c @@ -0,0 +1,39 @@ +#include "vector_internals.h" + +/* set agnostic elements to 1s */ +void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt, + uint32_t tot) +{ + if (is_agnostic == 0) { + /* policy undisturbed */ + return; + } + if (tot - cnt == 0) { + return ; + } + memset(base + cnt, -1, tot - cnt); +} + +void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, + CPURISCVState *env, uint32_t desc, + opivv2_fn *fn, uint32_t esz) +{ + uint32_t vm = vext_vm(desc); + uint32_t vl = env->vl; + uint32_t total_elems = vext_get_total_elems(env, desc, esz); + uint32_t vta = vext_vta(desc); + uint32_t vma = vext_vma(desc); + uint32_t i; + + for (i = env->vstart; i < vl; i++) { + if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); + continue; + } + fn(vd, vs1, vs2, i); + } + env->vstart = 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); +} diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h new file mode 100644 index 0000000000..f61803acc0 --- /dev/null +++ b/target/riscv/vector_internals.h @@ -0,0 +1,116 @@ +/* + * RISC-V Vector Extension Internals + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef TARGET_RISCV_VECTOR_INTERNAL_H +#define TARGET_RISCV_VECTOR_INTERNAL_H + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "cpu.h" +#include "tcg/tcg-gvec-desc.h" +#include "internals.h" + +static inline uint32_t vext_nf(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, NF); +} + +/* + * Encode LMUL to lmul as following: + * LMUL vlmul lmul + * 1 000 0 + * 2 001 1 + * 4 010 2 + * 8 011 3 + * - 100 - + * 1/8 101 -3 + * 1/4 110 -2 + * 1/2 111 -1 + */ +static inline int32_t vext_lmul(uint32_t desc) +{ + return sextract32(FIELD_EX32(simd_data(desc), VDATA, LMUL), 0, 3); +} + +static inline uint32_t vext_vm(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VM); +} + +static inline uint32_t vext_vma(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VMA); +} + +static inline uint32_t vext_vta(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VTA); +} + +static inline uint32_t vext_vta_all_1s(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S); +} + +/* + * Earlier designs (pre-0.9) had a varying number of bits + * per mask value (MLEN). In the 0.9 design, MLEN=1. + * (Section 4.5) + */ +static inline int vext_elem_mask(void *v0, int index) +{ + int idx = index / 64; + int pos = index % 64; + return (((uint64_t *)v0)[idx] >> pos) & 1; +} + +/* + * Get number of total elements, including prestart, body and tail elements. + * Note that when LMUL < 1, the tail includes the elements past VLMAX that + * are held in the same vector register. + */ +static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc, + uint32_t esz) +{ + uint32_t vlenb = simd_maxsz(desc); + uint32_t sew = 1 << FIELD_EX64(env->vtype, VTYPE, VSEW); + int8_t emul = ctzl(esz) - ctzl(sew) + vext_lmul(desc) < 0 ? 0 : + ctzl(esz) - ctzl(sew) + vext_lmul(desc); + return (vlenb << emul) / esz; +} + +/* set agnostic elements to 1s */ +void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt, + uint32_t tot); + +/* operation of two vector elements */ +typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); + +void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, + CPURISCVState *env, uint32_t desc, + opivv2_fn *fn, uint32_t esz); + +/* generate the helpers for OPIVV */ +#define GEN_VEXT_VV(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, void *vs1, \ + void *vs2, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + do_vext_vv(vd, v0, vs1, vs2, env, desc, \ + do_##NAME, ESZ); \ +} + +#endif /* TARGET_RISCV_VECTOR_INTERNAL_H */ -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:01 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2A-0007Zp-8k for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1U-0007A6-6i for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:15 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1Q-00070J-4O for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:10 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1J-007gSL-G5; Thu, 19 Jan 2023 14:36:02 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence Hunter Subject: [RFC PATCH 16/39] target/riscv: Add vaesdm.vv decoding, translation and execution support Date: Thu, 19 Jan 2023 14:35:05 +0000 Message-Id: <20230119143528.1290950-17-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:16 -0000 Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 1 + target/riscv/vcrypto_helper.c | 36 +++++++++++++++++++++ 4 files changed, 39 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 020b9861cf..328a026039 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1185,3 +1185,4 @@ DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 33e5883937..e5f3af999d 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -914,3 +914,4 @@ vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1 vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1 vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1 vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1 +vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/insn_trans/trans_rvzvkns.c.inc index 7dd61b879e..21ef836fb2 100644 --- a/target/riscv/insn_trans/trans_rvzvkns.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -60,3 +60,4 @@ GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesdf_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesdf_vs, vaes_check_vs) +GEN_V_UNMASKED_TRANS(vaesdm_vv, vaes_check_vv) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index d3ba5e9cb8..bac21b5623 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -219,6 +219,38 @@ static inline void aes_inv_shift_bytes(uint8_t round_state[4][4]) round_state[3][3] = temp; } +static inline uint8_t xtime(uint8_t x) +{ + return (x << 1) ^ (((x >> 7) & 1) * 0x1b); +} + +static inline uint8_t multiply(uint8_t x, uint8_t y) +{ + return (((y & 1) * x) ^ ((y >> 1 & 1) * xtime(x)) ^ + ((y >> 2 & 1) * xtime(xtime(x))) ^ + ((y >> 3 & 1) * xtime(xtime(xtime(x)))) ^ + ((y >> 4 & 1) * xtime(xtime(xtime(xtime(x)))))); +} + +static inline void aes_inv_mix_cols(uint8_t round_state[4][4]) +{ + uint8_t a, b, c, d; + for (int j = 0; j < 4; ++j) { + a = round_state[j][0]; + b = round_state[j][1]; + c = round_state[j][2]; + d = round_state[j][3]; + round_state[j][0] = multiply(a, 0x0e) ^ multiply(b, 0x0b) ^ + multiply(c, 0x0d) ^ multiply(d, 0x09); + round_state[j][1] = multiply(a, 0x09) ^ multiply(b, 0x0e) ^ + multiply(c, 0x0b) ^ multiply(d, 0x0d); + round_state[j][2] = multiply(a, 0x0d) ^ multiply(b, 0x09) ^ + multiply(c, 0x0e) ^ multiply(d, 0x0b); + round_state[j][3] = multiply(a, 0x0b) ^ multiply(b, 0x0d) ^ + multiply(c, 0x09) ^ multiply(d, 0x0e); + } +} + #define GEN_ZVKNS_HELPER_VV(NAME, ...) \ void HELPER(NAME)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, \ uint32_t desc) \ @@ -301,3 +333,7 @@ GEN_ZVKNS_HELPER_VV(vaesdf_vv, aes_inv_shift_bytes(round_state); GEN_ZVKNS_HELPER_VS(vaesdf_vs, aes_inv_shift_bytes(round_state); aes_inv_sub_bytes(round_state); xor_round_key(round_state, (uint8_t *)round_key);) +GEN_ZVKNS_HELPER_VV(vaesdm_vv, aes_inv_shift_bytes(round_state); + aes_inv_sub_bytes(round_state); + xor_round_key(round_state, (uint8_t *)round_key); + aes_inv_mix_cols(round_state);) -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:03 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2H-0007f7-Dp for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1U-0007A8-7j for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:15 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1P-0006zU-Ui for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:10 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1E-007gSL-J4; Thu, 19 Jan 2023 14:35:57 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, William Salmon , Kiran Ostrolenk Subject: [RFC PATCH 07/39] target/riscv: Add vbrev8.v decoding, translation and execution support Date: Thu, 19 Jan 2023 14:34:56 +0000 Message-Id: <20230119143528.1290950-8-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:17 -0000 From: William Salmon Co-authored-by: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk Signed-off-by: William Salmon --- include/qemu/bitops.h | 32 +++++++++++++++++ target/riscv/helper.h | 5 +++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 41 +++++++++++++++++++++ target/riscv/vcrypto_helper.c | 10 ++++++ target/riscv/vector_helper.c | 41 --------------------- target/riscv/vector_internals.h | 42 ++++++++++++++++++++++ 7 files changed, 131 insertions(+), 41 deletions(-) diff --git a/include/qemu/bitops.h b/include/qemu/bitops.h index 03213ce952..dfce1cb10c 100644 --- a/include/qemu/bitops.h +++ b/include/qemu/bitops.h @@ -618,4 +618,36 @@ static inline uint64_t half_unshuffle64(uint64_t x) return x; } +static inline uint8_t reverse_bits_byte(uint8_t x) +{ + x = (((x & 0b10101010) >> 1) | ((x & 0b01010101) << 1)); + x = (((x & 0b11001100) >> 2) | ((x & 0b00110011) << 2)); + return ((x & 0b11110000) >> 4) | ((x & 0b00001111) << 4); +} + +static inline uint16_t reverse_bits_byte_2(uint16_t x) +{ + return (uint16_t)reverse_bits_byte(x & 0xFF) | \ + (uint16_t)reverse_bits_byte((x >> 8) & 0xFF) << 8; +} + +static inline uint32_t reverse_bits_byte_4(uint32_t x) +{ + return (uint32_t)reverse_bits_byte(x & 0xFF) | \ + (uint32_t)reverse_bits_byte((x >> 8) & 0xFF) << 8 | \ + (uint32_t)reverse_bits_byte((x >> 16) & 0xFF) << 16 | \ + (uint32_t)reverse_bits_byte((x >> 24) & 0xFF) << 24; +} + +static inline uint64_t reverse_bits_byte_8(uint64_t x) +{ + return (uint64_t)reverse_bits_byte(x & 0xFF) | \ + (uint64_t)reverse_bits_byte((x >> 8) & 0xFF) << 8 | \ + (uint64_t)reverse_bits_byte((x >> 16) & 0xFF) << 16 | \ + (uint64_t)reverse_bits_byte((x >> 24) & 0xFF) << 24 | \ + (uint64_t)reverse_bits_byte((x >> 32) & 0xFF) << 32 | \ + (uint64_t)reverse_bits_byte((x >> 40) & 0xFF) << 40 | \ + (uint64_t)reverse_bits_byte((x >> 48) & 0xFF) << 48 | \ + (uint64_t)reverse_bits_byte((x >> 56) & 0xFF) << 56; +} #endif diff --git a/target/riscv/helper.h b/target/riscv/helper.h index e5b6b3360f..c94627d8a4 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1162,3 +1162,8 @@ DEF_HELPER_6(vrol_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrol_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrol_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrol_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_5(vbrev8_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev8_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev8_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vbrev8_v_d, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 725f907ad1..782632a165 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -902,3 +902,4 @@ vror_vv 010100 . ..... ..... 000 ..... 1010111 @r_vm vror_vx 010100 . ..... ..... 100 ..... 1010111 @r_vm vror_vi 010100 . ..... ..... 011 ..... 1010111 @r_vm vror_vi2 010101 . ..... ..... 011 ..... 1010111 @r_vm +vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn_trans/trans_rvzvkb.c.inc index d2a7a92d42..50eee7c0a3 100644 --- a/target/riscv/insn_trans/trans_rvzvkb.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc @@ -115,3 +115,44 @@ static bool trans_vror_vi2(DisasContext *s, arg_rmrr *a) a->rs1 += 32; return trans_vror_vi(s, a); } + +#define GEN_OPIV_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmr * a) \ +{ \ + if (CHECK(s, a)) { \ + uint32_t data = 0; \ + static gen_helper_gvec_3_ptr * const fns[4] = { \ + gen_helper_##NAME##_b, \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d, \ + }; \ + TCGLabel *over = gen_new_label(); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ + \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data = FIELD_DP32(data, VDATA, VTA, s->vta); \ + data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \ + data = FIELD_DP32(data, VDATA, VMA, s->vma); \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), cpu_env, \ + s->cfg_ptr->vlen / 8, s->cfg_ptr->vlen / 8, \ + data, fns[s->sew]); \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +static bool vxrev8_check(DisasContext *s, arg_rmr *a) +{ + return require_rvv(s) && + s->cfg_ptr->ext_zvkb == true && + vext_check_isa_ill(s) && + vext_check_ss(s, a->rd, a->rs2, a->vm); +} + +GEN_OPIV_TRANS(vbrev8_v, vxrev8_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 7ec75c5589..303a656141 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -1,6 +1,7 @@ #include "qemu/osdep.h" #include "qemu/host-utils.h" #include "qemu/bitops.h" +#include "qemu/bswap.h" #include "cpu.h" #include "exec/memop.h" #include "exec/exec-all.h" @@ -115,3 +116,12 @@ GEN_VEXT_VX(vrol_vx_b, 1) GEN_VEXT_VX(vrol_vx_h, 2) GEN_VEXT_VX(vrol_vx_w, 4) GEN_VEXT_VX(vrol_vx_d, 8) + +RVVCALL(OPIVV1, vbrev8_v_b, OP_UU_B, H1, H1, reverse_bits_byte) +RVVCALL(OPIVV1, vbrev8_v_h, OP_UU_H, H2, H2, reverse_bits_byte_2) +RVVCALL(OPIVV1, vbrev8_v_w, OP_UU_W, H4, H4, reverse_bits_byte_4) +RVVCALL(OPIVV1, vbrev8_v_d, OP_UU_D, H8, H8, reverse_bits_byte_8) +GEN_VEXT_V(vbrev8_v_b, 1) +GEN_VEXT_V(vbrev8_v_h, 2) +GEN_VEXT_V(vbrev8_v_w, 4) +GEN_VEXT_V(vbrev8_v_d, 8) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index ff7b03cbe3..07da4b5e16 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -3437,12 +3437,6 @@ RVVCALL(OPFVF3, vfwnmsac_vf_w, WOP_UUU_W, H8, H4, fwnmsac32) GEN_VEXT_VF(vfwnmsac_vf_h, 4) GEN_VEXT_VF(vfwnmsac_vf_w, 8) -/* Vector Floating-Point Square-Root Instruction */ -/* (TD, T2, TX2) */ -#define OP_UU_H uint16_t, uint16_t, uint16_t -#define OP_UU_W uint32_t, uint32_t, uint32_t -#define OP_UU_D uint64_t, uint64_t, uint64_t - #define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ static void do_##NAME(void *vd, void *vs2, int i, \ CPURISCVState *env) \ @@ -4134,41 +4128,6 @@ GEN_VEXT_CMP_VF(vmfge_vf_h, uint16_t, H2, vmfge16) GEN_VEXT_CMP_VF(vmfge_vf_w, uint32_t, H4, vmfge32) GEN_VEXT_CMP_VF(vmfge_vf_d, uint64_t, H8, vmfge64) -/* Vector Floating-Point Classify Instruction */ -#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ -static void do_##NAME(void *vd, void *vs2, int i) \ -{ \ - TX2 s2 = *((T2 *)vs2 + HS2(i)); \ - *((TD *)vd + HD(i)) = OP(s2); \ -} - -#define GEN_VEXT_V(NAME, ESZ) \ -void HELPER(NAME)(void *vd, void *v0, void *vs2, \ - CPURISCVState *env, uint32_t desc) \ -{ \ - uint32_t vm = vext_vm(desc); \ - uint32_t vl = env->vl; \ - uint32_t total_elems = \ - vext_get_total_elems(env, desc, ESZ); \ - uint32_t vta = vext_vta(desc); \ - uint32_t vma = vext_vma(desc); \ - uint32_t i; \ - \ - for (i = env->vstart; i < vl; i++) { \ - if (!vm && !vext_elem_mask(v0, i)) { \ - /* set masked-off elements to 1s */ \ - vext_set_elems_1s(vd, vma, i * ESZ, \ - (i + 1) * ESZ); \ - continue; \ - } \ - do_##NAME(vd, vs2, i); \ - } \ - env->vstart = 0; \ - /* set tail elements to 1s */ \ - vext_set_elems_1s(vd, vta, vl * ESZ, \ - total_elems * ESZ); \ -} - target_ulong fclass_h(uint64_t frs1) { float16 f = frs1; diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h index a0fbac7bf3..f1f16453dc 100644 --- a/target/riscv/vector_internals.h +++ b/target/riscv/vector_internals.h @@ -123,12 +123,54 @@ void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt, /* expand macro args before macro */ #define RVVCALL(macro, ...) macro(__VA_ARGS__) +/* Vector Floating-Point Square-Root Instruction */ +/* (TD, T2, TX2) */ +#define OP_UU_B uint8_t, uint8_t, uint8_t +#define OP_UU_H uint16_t, uint16_t, uint16_t +#define OP_UU_W uint32_t, uint32_t, uint32_t +#define OP_UU_D uint64_t, uint64_t, uint64_t + /* (TD, T1, T2, TX1, TX2) */ #define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t #define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t #define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t #define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t +/* Vector Floating-Point Classify Instruction */ +#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ +static void do_##NAME(void *vd, void *vs2, int i) \ +{ \ + TX2 s2 = *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) = OP(s2); \ +} + +#define GEN_VEXT_V(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vm = vext_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t total_elems = \ + vext_get_total_elems(env, desc, ESZ); \ + uint32_t vta = vext_vta(desc); \ + uint32_t vma = vext_vma(desc); \ + uint32_t i; \ + \ + for (i = env->vstart; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, i)) { \ + /* set masked-off elements to 1s */ \ + vext_set_elems_1s(vd, vma, i * ESZ, \ + (i + 1) * ESZ); \ + continue; \ + } \ + do_##NAME(vd, vs2, i); \ + } \ + env->vstart = 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * ESZ, \ + total_elems * ESZ); \ +} + /* operation of two vector elements */ typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:10 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2J-0007gL-Ee for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1d-0007Da-7s for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:21 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1a-000709-Ba for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:20 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1J-007gSL-0o; Thu, 19 Jan 2023 14:36:02 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence Hunter Subject: [RFC PATCH 15/39] target/riscv: Add vaesdf.vs decoding, translation and execution support Date: Thu, 19 Jan 2023 14:35:04 +0000 Message-Id: <20230119143528.1290950-16-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:27 -0000 Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 1 + target/riscv/vcrypto_helper.c | 3 +++ 4 files changed, 6 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index b7696cb6c4..020b9861cf 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1184,3 +1184,4 @@ DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index ca907dac85..33e5883937 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -913,3 +913,4 @@ vandn_vx 000001 . ..... ..... 100 ..... 1010111 @r_vm vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1 vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1 vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1 +vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/insn_trans/trans_rvzvkns.c.inc index bd1f380a65..7dd61b879e 100644 --- a/target/riscv/insn_trans/trans_rvzvkns.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -59,3 +59,4 @@ static bool vaes_check_vs(DisasContext *s, arg_rmr *a) GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesdf_vv, vaes_check_vv) +GEN_V_UNMASKED_TRANS(vaesdf_vs, vaes_check_vs) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 24b5336fa7..d3ba5e9cb8 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -298,3 +298,6 @@ GEN_ZVKNS_HELPER_VS(vaesef_vs, aes_sub_bytes(round_state); GEN_ZVKNS_HELPER_VV(vaesdf_vv, aes_inv_shift_bytes(round_state); aes_inv_sub_bytes(round_state); xor_round_key(round_state, (uint8_t *)round_key);) +GEN_ZVKNS_HELPER_VS(vaesdf_vs, aes_inv_shift_bytes(round_state); + aes_inv_sub_bytes(round_state); + xor_round_key(round_state, (uint8_t *)round_key);) -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:13 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2T-000806-9m for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1D-000744-NX for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:08 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1B-0006xW-LT for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:35:55 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW13-007gSL-Lb; Thu, 19 Jan 2023 14:35:46 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence Hunter Subject: [RFC PATCH 00/39] Add RISC-V cryptography extensions standardisation Date: Thu, 19 Jan 2023 14:34:49 +0000 Message-Id: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:15 -0000 This RFC introduces an implementation for the six instruction sets of the draft RISC-V cryptography extensions standardisation specification. Once the specification has been ratified we will submit these changes as a pull request email to this mailing list. Would this be prefered by instruction group or unified as in this RFC? This patch set implements the instruction sets as per the 20221202 version of the specification (1). Work performed by Dickon, Lawrence, Nazar, Kiran, and William from Codethink sponsored by SiFive, and Max Chou from SiFive. 1. https://github.com/riscv/riscv-crypto/releases Dickon Hood (1): target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] decoding, translation and execution support Kiran Ostrolenk (4): target/riscv: Add vsha2ms.vv decoding, translation and execution support target/riscv: add zvksh cpu property target/riscv: Add vsm3c.vi decoding, translation and execution support target/riscv: expose zvksh cpu property Lawrence Hunter (16): target/riscv: Add vclmul.vv decoding, translation and execution support target/riscv: Add vclmul.vx decoding, translation and execution support target/riscv: Add vclmulh.vv decoding, translation and execution support target/riscv: Add vclmulh.vx decoding, translation and execution support target/riscv: Add vaesef.vv decoding, translation and execution support target/riscv: Add vaesef.vs decoding, translation and execution support target/riscv: Add vaesdf.vv decoding, translation and execution support target/riscv: Add vaesdf.vs decoding, translation and execution support target/riscv: Add vaesdm.vv decoding, translation and execution support target/riscv: Add vaesdm.vs decoding, translation and execution support target/riscv: Add vaesz.vs decoding, translation and execution support target/riscv: Add vsha2c[hl].vv decoding, translation and execution support target/riscv: Add vsm3me.vv decoding, translation and execution support target/riscv: add zvkg cpu property target/riscv: Add vghmac.vv decoding, translation and execution support target/riscv: expose zvkg cpu property Max Chou (5): crypto: Move SM4_SBOXWORD from target/riscv crypto: Add SM4 constant parameter CK. target/riscv: Add zvksed cfg property target/riscv: Add Zvksed support target/riscv: Expose Zvksed property Nazar Kazakov (10): target/riscv: add zvkb cpu property target/riscv: Add vrev8.v decoding, translation and execution support target/riscv: Add vandn.[vv,vx,vi] decoding, translation and execution support target/riscv: expose zvkb cpu property target/riscv: add zvkns cpu property target/riscv: Add vaeskf1.vi decoding, translation and execution support target/riscv: Add vaeskf2.vi decoding, translation and execution support target/riscv: expose zvkns cpu property target/riscv: add zvknh cpu properties target/riscv: expose zvknh cpu properties William Salmon (3): target/riscv: Add vbrev8.v decoding, translation and execution support target/riscv: Add vaesem.vv decoding, translation and execution support target/riscv: Add vaesem.vs decoding, translation and execution support crypto/sm4.c | 10 + include/crypto/sm4.h | 8 + include/qemu/bitops.h | 32 + target/arm/crypto_helper.c | 10 +- target/riscv/cpu.c | 15 + target/riscv/cpu.h | 7 + target/riscv/crypto_helper.c | 1 + target/riscv/helper.h | 69 ++ target/riscv/insn32.decode | 48 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 164 +++ target/riscv/insn_trans/trans_rvzvkg.c.inc | 8 + target/riscv/insn_trans/trans_rvzvknh.c.inc | 47 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 121 +++ target/riscv/insn_trans/trans_rvzvksed.c.inc | 38 + target/riscv/insn_trans/trans_rvzvksh.c.inc | 20 + target/riscv/meson.build | 4 +- target/riscv/translate.c | 6 + target/riscv/vcrypto_helper.c | 1013 ++++++++++++++++++ target/riscv/vector_helper.c | 242 +---- target/riscv/vector_internals.c | 63 ++ target/riscv/vector_internals.h | 226 ++++ 21 files changed, 1902 insertions(+), 250 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvzvkb.c.inc create mode 100644 target/riscv/insn_trans/trans_rvzvkg.c.inc create mode 100644 target/riscv/insn_trans/trans_rvzvknh.c.inc create mode 100644 target/riscv/insn_trans/trans_rvzvkns.c.inc create mode 100644 target/riscv/insn_trans/trans_rvzvksed.c.inc create mode 100644 target/riscv/insn_trans/trans_rvzvksh.c.inc create mode 100644 target/riscv/vcrypto_helper.c create mode 100644 target/riscv/vector_internals.c create mode 100644 target/riscv/vector_internals.h -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:13 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2T-00080h-Fg for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1b-0007DE-Pn for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:21 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1a-000710-7Q for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:19 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1L-007gSL-DI; Thu, 19 Jan 2023 14:36:04 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, William Salmon Subject: [RFC PATCH 20/39] target/riscv: Add vaesem.vs decoding, translation and execution support Date: Thu, 19 Jan 2023 14:35:09 +0000 Message-Id: <20230119143528.1290950-21-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:27 -0000 From: William Salmon Signed-off-by: William Salmon --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 1 + target/riscv/vcrypto_helper.c | 3 +++ 4 files changed, 6 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 4bfc9a3387..85981f2cad 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1186,6 +1186,7 @@ DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesem_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesem_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index f31414f72c..cc91ca8794 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -915,6 +915,7 @@ vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1 vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1 vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1 vaesem_vv 101000 1 ..... 00010 010 ..... 1110111 @r2_vm_1 +vaesem_vs 101001 1 ..... 00010 010 ..... 1110111 @r2_vm_1 vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1 vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/insn_trans/trans_rvzvkns.c.inc index 2e0523ec62..fae48d63dc 100644 --- a/target/riscv/insn_trans/trans_rvzvkns.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -64,3 +64,4 @@ GEN_V_UNMASKED_TRANS(vaesdm_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesz_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesem_vv, vaes_check_vv) +GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index a1d66a64aa..883739f4ac 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -350,6 +350,9 @@ GEN_ZVKNS_HELPER_VS(vaesdf_vs, aes_inv_shift_bytes(round_state); GEN_ZVKNS_HELPER_VV(vaesem_vv, aes_shift_bytes(round_state); aes_sub_bytes(round_state); aes_mix_cols(round_state); xor_round_key(round_state, (uint8_t *)round_key);) +GEN_ZVKNS_HELPER_VS(vaesem_vs, aes_shift_bytes(round_state); + aes_sub_bytes(round_state); aes_mix_cols(round_state); + xor_round_key(round_state, (uint8_t *)round_key);) GEN_ZVKNS_HELPER_VV(vaesdm_vv, aes_inv_shift_bytes(round_state); aes_inv_sub_bytes(round_state); xor_round_key(round_state, (uint8_t *)round_key); -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:13 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2T-00081K-LQ for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1R-00079C-KE for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:15 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1M-0006zy-Lw for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:09 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1I-007gSL-JA; Thu, 19 Jan 2023 14:36:01 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence Hunter Subject: [RFC PATCH 14/39] target/riscv: Add vaesdf.vv decoding, translation and execution support Date: Thu, 19 Jan 2023 14:35:03 +0000 Message-Id: <20230119143528.1290950-15-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:15 -0000 Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 1 + target/riscv/vcrypto_helper.c | 31 +++++++++++++++++++++ 4 files changed, 34 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 42349837ef..b7696cb6c4 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1183,3 +1183,4 @@ DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 0d65c2ea27..ca907dac85 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -912,3 +912,4 @@ vandn_vx 000001 . ..... ..... 100 ..... 1010111 @r_vm # *** RV64 Zvkns vector crypto extension *** vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1 vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1 +vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/insn_trans/trans_rvzvkns.c.inc index dc4310882d..bd1f380a65 100644 --- a/target/riscv/insn_trans/trans_rvzvkns.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -58,3 +58,4 @@ static bool vaes_check_vs(DisasContext *s, arg_rmr *a) GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs) +GEN_V_UNMASKED_TRANS(vaesdf_vv, vaes_check_vv) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index f59e090c03..24b5336fa7 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -191,6 +191,34 @@ static inline void xor_round_key(uint8_t round_state[4][4], uint8_t *round_key) } } +static inline void aes_inv_sub_bytes(uint8_t round_state[4][4]) +{ + for (int j = 0; j < 16; j++) { + round_state[j / 4][j % 4] = AES_isbox[round_state[j / 4][j % 4]]; + } +} + +static inline void aes_inv_shift_bytes(uint8_t round_state[4][4]) +{ + uint8_t temp; + temp = round_state[3][1]; + round_state[3][1] = round_state[2][1]; + round_state[2][1] = round_state[1][1]; + round_state[1][1] = round_state[0][1]; + round_state[0][1] = temp; + temp = round_state[0][2]; + round_state[0][2] = round_state[2][2]; + round_state[2][2] = temp; + temp = round_state[1][2]; + round_state[1][2] = round_state[3][2]; + round_state[3][2] = temp; + temp = round_state[0][3]; + round_state[0][3] = round_state[1][3]; + round_state[1][3] = round_state[2][3]; + round_state[2][3] = round_state[3][3]; + round_state[3][3] = temp; +} + #define GEN_ZVKNS_HELPER_VV(NAME, ...) \ void HELPER(NAME)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, \ uint32_t desc) \ @@ -267,3 +295,6 @@ GEN_ZVKNS_HELPER_VV(vaesef_vv, aes_sub_bytes(round_state); GEN_ZVKNS_HELPER_VS(vaesef_vs, aes_sub_bytes(round_state); aes_shift_bytes(round_state); xor_round_key(round_state, (uint8_t *)round_key);) +GEN_ZVKNS_HELPER_VV(vaesdf_vv, aes_inv_shift_bytes(round_state); + aes_inv_sub_bytes(round_state); + xor_round_key(round_state, (uint8_t *)round_key);) -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:14 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2T-000825-RO for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1U-0007A7-6o for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:15 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1M-0006zG-KZ for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:10 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1E-007gSL-4N; Thu, 19 Jan 2023 14:35:57 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Kiran Ostrolenk Subject: [RFC PATCH 06/39] target/riscv: Add vrol.[vv, vx] and vror.[vv, vx, vi] decoding, translation and execution support Date: Thu, 19 Jan 2023 14:34:55 +0000 Message-Id: <20230119143528.1290950-7-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:16 -0000 From: Dickon Hood Add an initial implementation of the vrol.* and vror.* instructions, with mappings between the RISC-V instructions and their internal TCG accelerated implmentations. There are some missing ror helpers, so I've bodged it by converting them to rols. Co-authored-by: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk Signed-off-by: Dickon Hood --- target/riscv/helper.h | 20 ++++++++ target/riscv/insn32.decode | 6 +++ target/riscv/insn_trans/trans_rvzvkb.c.inc | 20 ++++++++ target/riscv/vcrypto_helper.c | 58 ++++++++++++++++++++++ target/riscv/vector_helper.c | 45 ----------------- target/riscv/vector_internals.h | 52 +++++++++++++++++++ 6 files changed, 156 insertions(+), 45 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 32f1179e29..e5b6b3360f 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1142,3 +1142,23 @@ DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vror_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vror_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vror_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vror_vv_d, void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vror_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vror_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vror_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vror_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vrol_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrol_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrol_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vrol_vv_d, void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vrol_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vrol_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vrol_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vrol_vx_d, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b4d88dd1cb..725f907ad1 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -896,3 +896,9 @@ vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm +vrol_vv 010101 . ..... ..... 000 ..... 1010111 @r_vm +vrol_vx 010101 . ..... ..... 100 ..... 1010111 @r_vm +vror_vv 010100 . ..... ..... 000 ..... 1010111 @r_vm +vror_vx 010100 . ..... ..... 100 ..... 1010111 @r_vm +vror_vi 010100 . ..... ..... 011 ..... 1010111 @r_vm +vror_vi2 010101 . ..... ..... 011 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn_trans/trans_rvzvkb.c.inc index 533141e559..d2a7a92d42 100644 --- a/target/riscv/insn_trans/trans_rvzvkb.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc @@ -95,3 +95,23 @@ static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a) GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check) GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check) + +GEN_OPIVV_TRANS(vror_vv, zvkb_vv_check) +GEN_OPIVX_TRANS(vror_vx, zvkb_vx_check) +GEN_OPIVV_TRANS(vrol_vv, zvkb_vv_check) +GEN_OPIVX_TRANS(vrol_vx, zvkb_vx_check) + +GEN_OPIVI_TRANS(vror_vi, IMM_TRUNC_SEW, vror_vx, zvkb_vx_check) + +/* + * Immediates are 5b long, and we need six for the rotate-immediate. The + * decision has been taken to remove the vrol.vi instruction -- you can + * emulate it with a ror, after all -- and use the bottom bit of the funct6 + * part of the opcode to encode the extra bit. I've chosen to implement it + * like this because it's easy and reasonably clean. + */ +static bool trans_vror_vi2(DisasContext *s, arg_rmrr *a) +{ + a->rs1 += 32; + return trans_vror_vi(s, a); +} diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 46e2e510c5..7ec75c5589 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -57,3 +57,61 @@ GEN_VEXT_VV(vclmul_vv, 8) GEN_VEXT_VX(vclmul_vx, 8) GEN_VEXT_VV(vclmulh_vv, 8) GEN_VEXT_VX(vclmulh_vx, 8) + +/* + * Looks a mess, but produces reasonable (aarch32) code on clang: + * https://godbolt.org/z/jchjsTda8 + */ +#define DO_ROR(x, n) \ + ((x >> (n & ((sizeof(x) << 3) - 1))) | \ + (x << ((sizeof(x) << 3) - (n & ((sizeof(x) << 3) - 1))))) +#define DO_ROL(x, n) \ + ((x << (n & ((sizeof(x) << 3) - 1))) | \ + (x >> ((sizeof(x) << 3) - (n & ((sizeof(x) << 3) - 1))))) + +RVVCALL(OPIVV2, vror_vv_b, OP_UUU_B, H1, H1, H1, DO_ROR) +RVVCALL(OPIVV2, vror_vv_h, OP_UUU_H, H2, H2, H2, DO_ROR) +RVVCALL(OPIVV2, vror_vv_w, OP_UUU_W, H4, H4, H4, DO_ROR) +RVVCALL(OPIVV2, vror_vv_d, OP_UUU_D, H8, H8, H8, DO_ROR) +GEN_VEXT_VV(vror_vv_b, 1) +GEN_VEXT_VV(vror_vv_h, 2) +GEN_VEXT_VV(vror_vv_w, 4) +GEN_VEXT_VV(vror_vv_d, 8) + +/* + * There's a missing tcg_gen_gvec_rotrs() helper function. + */ +#define GEN_VEXT_VX_RTOL(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + do_vext_vx(vd, v0, (ESZ << 3) - s1, vs2, env, desc, do_##NAME, ESZ); \ +} + +/* DO_ROL because GEN_VEXT_VX_RTOL() converts from R to L */ +RVVCALL(OPIVX2, vror_vx_b, OP_UUU_B, H1, H1, DO_ROL) +RVVCALL(OPIVX2, vror_vx_h, OP_UUU_H, H2, H2, DO_ROL) +RVVCALL(OPIVX2, vror_vx_w, OP_UUU_W, H4, H4, DO_ROL) +RVVCALL(OPIVX2, vror_vx_d, OP_UUU_D, H8, H8, DO_ROL) +GEN_VEXT_VX_RTOL(vror_vx_b, 1) +GEN_VEXT_VX_RTOL(vror_vx_h, 2) +GEN_VEXT_VX_RTOL(vror_vx_w, 4) +GEN_VEXT_VX_RTOL(vror_vx_d, 8) + +RVVCALL(OPIVV2, vrol_vv_b, OP_UUU_B, H1, H1, H1, DO_ROL) +RVVCALL(OPIVV2, vrol_vv_h, OP_UUU_H, H2, H2, H2, DO_ROL) +RVVCALL(OPIVV2, vrol_vv_w, OP_UUU_W, H4, H4, H4, DO_ROL) +RVVCALL(OPIVV2, vrol_vv_d, OP_UUU_D, H8, H8, H8, DO_ROL) +GEN_VEXT_VV(vrol_vv_b, 1) +GEN_VEXT_VV(vrol_vv_h, 2) +GEN_VEXT_VV(vrol_vv_w, 4) +GEN_VEXT_VV(vrol_vv_d, 8) + +RVVCALL(OPIVX2, vrol_vx_b, OP_UUU_B, H1, H1, DO_ROL) +RVVCALL(OPIVX2, vrol_vx_h, OP_UUU_H, H2, H2, DO_ROL) +RVVCALL(OPIVX2, vrol_vx_w, OP_UUU_W, H4, H4, DO_ROL) +RVVCALL(OPIVX2, vrol_vx_d, OP_UUU_D, H8, H8, DO_ROL) +GEN_VEXT_VX(vrol_vx_b, 1) +GEN_VEXT_VX(vrol_vx_h, 2) +GEN_VEXT_VX(vrol_vx_w, 4) +GEN_VEXT_VX(vrol_vx_d, 8) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index ab470092f6..ff7b03cbe3 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -76,26 +76,6 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, return vl; } -/* - * Note that vector data is stored in host-endian 64-bit chunks, - * so addressing units smaller than that needs a host-endian fixup. - */ -#if HOST_BIG_ENDIAN -#define H1(x) ((x) ^ 7) -#define H1_2(x) ((x) ^ 6) -#define H1_4(x) ((x) ^ 4) -#define H2(x) ((x) ^ 3) -#define H4(x) ((x) ^ 1) -#define H8(x) ((x)) -#else -#define H1(x) (x) -#define H1_2(x) (x) -#define H1_4(x) (x) -#define H2(x) (x) -#define H4(x) (x) -#define H8(x) (x) -#endif - /* * Get the maximum number of elements can be operated. * @@ -683,18 +663,11 @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) *** Vector Integer Arithmetic Instructions */ -/* expand macro args before macro */ -#define RVVCALL(macro, ...) macro(__VA_ARGS__) - /* (TD, T1, T2, TX1, TX2) */ #define OP_SSS_B int8_t, int8_t, int8_t, int8_t, int8_t #define OP_SSS_H int16_t, int16_t, int16_t, int16_t, int16_t #define OP_SSS_W int32_t, int32_t, int32_t, int32_t, int32_t #define OP_SSS_D int64_t, int64_t, int64_t, int64_t, int64_t -#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t -#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t -#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t -#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t #define OP_SUS_B int8_t, uint8_t, int8_t, uint8_t, int8_t #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t @@ -718,14 +691,6 @@ GEN_VEXT_ST_WHOLE(vs8r_v, int8_t, ste_b) #define NOP_UUU_H uint16_t, uint16_t, uint32_t, uint16_t, uint32_t #define NOP_UUU_W uint32_t, uint32_t, uint64_t, uint32_t, uint64_t - -#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ -static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ -{ \ - TX1 s1 = *((T1 *)vs1 + HS1(i)); \ - TX2 s2 = *((T2 *)vs2 + HS2(i)); \ - *((TD *)vd + HD(i)) = OP(s2, s1); \ -} #define DO_SUB(N, M) (N - M) #define DO_RSUB(N, M) (M - N) @@ -747,16 +712,6 @@ GEN_VEXT_VV(vsub_vv_h, 2) GEN_VEXT_VV(vsub_vv_w, 4) GEN_VEXT_VV(vsub_vv_d, 8) -/* - * (T1)s1 gives the real operator type. - * (TX1)(T1)s1 expands the operator type of widen or narrow operations. - */ -#define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ -static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \ -{ \ - TX2 s2 = *((T2 *)vs2 + HS2(i)); \ - *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1); \ -} RVVCALL(OPIVX2, vadd_vx_b, OP_SSS_B, H1, H1, DO_ADD) RVVCALL(OPIVX2, vadd_vx_h, OP_SSS_H, H2, H2, DO_ADD) diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h index 49529d2379..a0fbac7bf3 100644 --- a/target/riscv/vector_internals.h +++ b/target/riscv/vector_internals.h @@ -28,6 +28,26 @@ static inline uint32_t vext_nf(uint32_t desc) return FIELD_EX32(simd_data(desc), VDATA, NF); } +/* + * Note that vector data is stored in host-endian 64-bit chunks, + * so addressing units smaller than that needs a host-endian fixup. + */ +#if HOST_BIG_ENDIAN +#define H1(x) ((x) ^ 7) +#define H1_2(x) ((x) ^ 6) +#define H1_4(x) ((x) ^ 4) +#define H2(x) ((x) ^ 3) +#define H4(x) ((x) ^ 1) +#define H8(x) ((x)) +#else +#define H1(x) (x) +#define H1_2(x) (x) +#define H1_4(x) (x) +#define H2(x) (x) +#define H4(x) (x) +#define H8(x) (x) +#endif + /* * Encode LMUL to lmul as following: * LMUL vlmul lmul @@ -96,9 +116,30 @@ static inline uint32_t vext_get_total_elems(CPURISCVState *env, uint32_t desc, void vext_set_elems_1s(void *base, uint32_t is_agnostic, uint32_t cnt, uint32_t tot); +/* + *** Vector Integer Arithmetic Instructions + */ + +/* expand macro args before macro */ +#define RVVCALL(macro, ...) macro(__VA_ARGS__) + +/* (TD, T1, T2, TX1, TX2) */ +#define OP_UUU_B uint8_t, uint8_t, uint8_t, uint8_t, uint8_t +#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t +#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t +#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t + /* operation of two vector elements */ typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); +#define OPIVV2(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ +static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \ +{ \ + TX1 s1 = *((T1 *)vs1 + HS1(i)); \ + TX2 s2 = *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) = OP(s2, s1); \ +} + void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, CPURISCVState *env, uint32_t desc, opivv2_fn *fn, uint32_t esz); @@ -115,6 +156,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i); +/* + * (T1)s1 gives the real operator type. + * (TX1)(T1)s1 expands the operator type of widen or narrow operations. + */ +#define OPIVX2(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ +static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \ +{ \ + TX2 s2 = *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1); \ +} + void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, CPURISCVState *env, uint32_t desc, opivx2_fn fn, uint32_t esz); -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:14 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2U-00082g-2Q for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1b-0007DG-Rg for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:21 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1a-0006z7-8C for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:19 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1D-007gSL-N3; Thu, 19 Jan 2023 14:35:56 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence Hunter Subject: [RFC PATCH 05/39] target/riscv: Add vclmulh.vx decoding, translation and execution support Date: Thu, 19 Jan 2023 14:34:54 +0000 Message-Id: <20230119143528.1290950-6-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:27 -0000 Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 + target/riscv/vcrypto_helper.c | 12 ++++++++++++ 4 files changed, 15 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index a155272701..32f1179e29 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1141,3 +1141,4 @@ DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vclmulh_vv, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vclmulh_vx, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e26ea1df08..b4d88dd1cb 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -895,3 +895,4 @@ sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm vclmulh_vv 001101 . ..... ..... 010 ..... 1010111 @r_vm +vclmulh_vx 001101 . ..... ..... 110 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn_trans/trans_rvzvkb.c.inc index 19ce4c7431..533141e559 100644 --- a/target/riscv/insn_trans/trans_rvzvkb.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc @@ -94,3 +94,4 @@ static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a) } GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check) +GEN_VX_MASKED_TRANS(vclmulh_vx, vclmul_vx_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 022b941131..46e2e510c5 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -42,6 +42,18 @@ static void do_vclmulh_vv(void *vd, void *vs1, void *vs2, int i) ((uint64_t *)vd)[i] = (result >> 64); } +static void do_vclmulh_vx(void *vd, target_long rs1, void *vs2, int i) +{ + __uint128_t result = 0; + for (int j = 63; j >= 0; j--) { + if ((rs1 >> j) & 1) { + result ^= (((__uint128_t)(((uint64_t *)vs2)[i])) << j); + } + } + ((uint64_t *)vd)[i] = (result >> 64); +} + GEN_VEXT_VV(vclmul_vv, 8) GEN_VEXT_VX(vclmul_vx, 8) GEN_VEXT_VV(vclmulh_vv, 8) +GEN_VEXT_VX(vclmulh_vx, 8) -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:23 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2U-000846-ER for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1e-0007EQ-Es for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:27 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1a-0006zo-Lw for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:22 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1H-007gSL-2k; Thu, 19 Jan 2023 14:36:00 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Nazar Kazakov Subject: [RFC PATCH 11/39] target/riscv: add zvkns cpu property Date: Thu, 19 Jan 2023 14:35:00 +0000 Message-Id: <20230119143528.1290950-12-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:28 -0000 From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + 2 files changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a504e68196..fb8bd5c779 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -101,6 +101,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), ISA_EXT_DATA_ENTRY(zvkb, true, PRIV_VERSION_1_12_0, ext_zvkb), + ISA_EXT_DATA_ENTRY(zvkns, true, PRIV_VERSION_1_12_0, ext_zvkns), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d4824ad0bb..56008ef9b9 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -462,6 +462,7 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; bool ext_zvkb; + bool ext_zvkns; bool ext_zmmul; bool ext_smaia; bool ext_ssaia; -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:23 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2d-000881-JH for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1j-0007Es-6N for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:28 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1e-00072d-0z for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:24 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1O-007gSL-Nu; Thu, 19 Jan 2023 14:36:07 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Kiran Ostrolenk Subject: [RFC PATCH 28/39] target/riscv: add zvksh cpu property Date: Thu, 19 Jan 2023 14:35:17 +0000 Message-Id: <20230119143528.1290950-29-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:29 -0000 From: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + 2 files changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 09d9686baf..a21f1d43d4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -104,6 +104,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zvknha, true, PRIV_VERSION_1_12_0, ext_zvknha), ISA_EXT_DATA_ENTRY(zvknhb, true, PRIV_VERSION_1_12_0, ext_zvknhb), ISA_EXT_DATA_ENTRY(zvkns, true, PRIV_VERSION_1_12_0, ext_zvkns), + ISA_EXT_DATA_ENTRY(zvksh, true, PRIV_VERSION_1_12_0, ext_zvksh), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ebee902806..92624bfc57 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -465,6 +465,7 @@ struct RISCVCPUConfig { bool ext_zvknha; bool ext_zvknhb; bool ext_zvkns; + bool ext_zvksh; bool ext_zmmul; bool ext_smaia; bool ext_ssaia; -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:23 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2d-0008AO-Qg for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1j-0007FI-8V for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:28 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1b-00071p-I4 for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:23 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1N-007gSL-GB; Thu, 19 Jan 2023 14:36:06 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Kiran Ostrolenk , Nazar Kazakov Subject: [RFC PATCH 25/39] target/riscv: Add vsha2ms.vv decoding, translation and execution support Date: Thu, 19 Jan 2023 14:35:14 +0000 Message-Id: <20230119143528.1290950-26-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:29 -0000 From: Kiran Ostrolenk Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Kiran Ostrolenk --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 3 + target/riscv/insn_trans/trans_rvzvknh.c.inc | 45 ++++++++++++ target/riscv/translate.c | 1 + target/riscv/vcrypto_helper.c | 80 +++++++++++++++++++++ 5 files changed, 131 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzvknh.c.inc diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 312f59bb38..6e7777c879 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1192,3 +1192,5 @@ DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32) DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32) + +DEF_HELPER_5(vsha2ms_vv, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 1eed0a6b26..57fbd63d91 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -921,3 +921,6 @@ vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1 vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1 + +# *** RV64 Zvknh vector crypto extension *** +vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvknh.c.inc b/target/riscv/insn_trans/trans_rvzvknh.c.inc new file mode 100644 index 0000000000..ff30400100 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzvknh.c.inc @@ -0,0 +1,45 @@ +#define GEN_VV_UNMASKED_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr * a) \ +{ \ + if (CHECK(s, a)) { \ + uint32_t data = 0; \ + TCGLabel *over = gen_new_label(); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ + \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data = FIELD_DP32(data, VDATA, VTA, s->vta); \ + data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \ + data = FIELD_DP32(data, VDATA, VMA, s->vma); \ + \ + tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \ + vreg_ofs(s, a->rs1), \ + vreg_ofs(s, a->rs2), cpu_env, \ + s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data, \ + gen_helper_##NAME); \ + \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +static bool vsha_check_sew(DisasContext *s) +{ + return (s->cfg_ptr->ext_zvknha == true && s->sew == MO_32) || + (s->cfg_ptr->ext_zvknhb == true && + (s->sew == MO_32 || s->sew == MO_64)); +} + +static bool vsha_check(DisasContext *s, arg_rmrr *a) +{ + return opivv_check(s, a) && + vsha_check_sew(s) && + s->vstart % 4 == 0 && + s->lmul >= 0; +} + +GEN_VV_UNMASKED_TRANS(vsha2ms_vv, vsha_check) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 8d39743de2..924a89de9f 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1065,6 +1065,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_rvk.c.inc" #include "insn_trans/trans_rvzvkb.c.inc" #include "insn_trans/trans_rvzvkns.c.inc" +#include "insn_trans/trans_rvzvknh.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 50207b4ff0..af596cce09 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -461,3 +461,83 @@ void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, /* set tail elements to 1s */ vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); } + +static inline uint32_t sig0_sha256(uint32_t x) +{ + return ror32(x, 7) ^ ror32(x, 18) ^ (x >> 3); +} + +static inline uint32_t sig1_sha256(uint32_t x) +{ + return ror32(x, 17) ^ ror32(x, 19) ^ (x >> 10); +} + +static inline uint64_t sig0_sha512(uint64_t x) +{ + return ror64(x, 1) ^ ror64(x, 8) ^ (x >> 7); +} + +static inline uint64_t sig1_sha512(uint64_t x) +{ + return ror64(x, 19) ^ ror64(x, 61) ^ (x >> 6); +} + +static inline void vsha2ms_e32(uint32_t *vd, uint32_t *vs1, uint32_t *vs2) +{ + uint32_t res[4]; + res[0] = sig1_sha256(vs2[H4(2)]) + vs1[H4(1)] + sig0_sha256(vd[H4(1)]) + + vd[H4(0)]; + res[1] = sig1_sha256(vs2[H4(3)]) + vs1[H4(2)] + sig0_sha256(vd[H4(2)]) + + vd[H4(1)]; + res[2] = sig1_sha256(res[0]) + vs1[H4(3)] + sig0_sha256(vd[H4(3)]) + + vd[H4(2)]; + res[3] = sig1_sha256(res[1]) + vs2[H4(0)] + sig0_sha256(vs1[H4(0)]) + + vd[H4(3)]; + vd[H4(3)] = res[3]; + vd[H4(2)] = res[2]; + vd[H4(1)] = res[1]; + vd[H4(0)] = res[0]; +} + +static inline void vsha2ms_e64(uint64_t *vd, uint64_t *vs1, uint64_t *vs2) +{ + uint64_t res[4]; + res[0] = sig1_sha512(vs2[2]) + vs1[1] + sig0_sha512(vd[1]) + vd[0]; + res[1] = sig1_sha512(vs2[3]) + vs1[2] + sig0_sha512(vd[2]) + vd[1]; + res[2] = sig1_sha512(res[0]) + vs1[3] + sig0_sha512(vd[3]) + vd[2]; + res[3] = sig1_sha512(res[1]) + vs2[0] + sig0_sha512(vs1[0]) + vd[3]; + vd[3] = res[3]; + vd[2] = res[2]; + vd[1] = res[1]; + vd[0] = res[0]; +} + +void HELPER(vsha2ms_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, + uint32_t desc) +{ + uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t esz = 0; + uint32_t total_elems; + uint32_t vta = vext_vta(desc); + + if (env->vl % 4 != 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { + if (sew == MO_32) { + esz = 4; + vsha2ms_e32(((uint32_t *)vd) + i * 4, ((uint32_t *)vs1) + i * 4, + ((uint32_t *)vs2) + i * 4); + } else { + /* If not 32 then SEW should be 64 */ + esz = 8; + vsha2ms_e64(((uint64_t *)vd) + i * 4, ((uint64_t *)vs1) + i * 4, + ((uint64_t *)vs2) + i * 4); + } + } + /* set tail elements to 1s */ + total_elems = vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart = 0; +} -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:24 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2e-0008BT-0l for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1j-0007Ej-5Q for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:28 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1e-00072X-1O for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:24 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1O-007gSL-Br; Thu, 19 Jan 2023 14:36:07 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Nazar Kazakov Subject: [RFC PATCH 27/39] target/riscv: expose zvknh cpu properties Date: Thu, 19 Jan 2023 14:35:16 +0000 Message-Id: <20230119143528.1290950-28-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:29 -0000 From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 50bc96be5c..09d9686baf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1075,6 +1075,8 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), DEFINE_PROP_BOOL("zvkb", RISCVCPU, cfg.ext_zvkb, false), + DEFINE_PROP_BOOL("zvknha", RISCVCPU, cfg.ext_zvknha, false), + DEFINE_PROP_BOOL("zvknhb", RISCVCPU, cfg.ext_zvknhb, false), DEFINE_PROP_BOOL("zvkns", RISCVCPU, cfg.ext_zvkns, false), /* Vendor-specific custom extensions */ -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:14 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2U-00083c-8f for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1d-0007DZ-4K for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:21 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1a-00070I-A1 for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:20 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1J-007gSL-Va; Thu, 19 Jan 2023 14:36:02 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence Hunter Subject: [RFC PATCH 17/39] target/riscv: Add vaesdm.vs decoding, translation and execution support Date: Thu, 19 Jan 2023 14:35:06 +0000 Message-Id: <20230119143528.1290950-18-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:27 -0000 Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 1 + target/riscv/vcrypto_helper.c | 4 ++++ 4 files changed, 7 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 328a026039..9895bf5712 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1186,3 +1186,4 @@ DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index e5f3af999d..753039e954 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -915,3 +915,4 @@ vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1 vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1 vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1 vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1 +vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/insn_trans/trans_rvzvkns.c.inc index 21ef836fb2..2c70227f8b 100644 --- a/target/riscv/insn_trans/trans_rvzvkns.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -61,3 +61,4 @@ GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesdf_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesdf_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesdm_vv, vaes_check_vv) +GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index bac21b5623..699bf25bbd 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -337,3 +337,7 @@ GEN_ZVKNS_HELPER_VV(vaesdm_vv, aes_inv_shift_bytes(round_state); aes_inv_sub_bytes(round_state); xor_round_key(round_state, (uint8_t *)round_key); aes_inv_mix_cols(round_state);) +GEN_ZVKNS_HELPER_VS(vaesdm_vs, aes_inv_shift_bytes(round_state); + aes_inv_sub_bytes(round_state); + xor_round_key(round_state, (uint8_t *)round_key); + aes_inv_mix_cols(round_state);) -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:32 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2m-0008J6-D3 for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1c-0007DY-Uy for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:21 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1a-0006zY-At for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:20 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1G-007gSL-F5; Thu, 19 Jan 2023 14:35:59 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Nazar Kazakov Subject: [RFC PATCH 10/39] target/riscv: expose zvkb cpu property Date: Thu, 19 Jan 2023 14:34:59 +0000 Message-Id: <20230119143528.1290950-11-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:27 -0000 From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ec1dbd923d..a504e68196 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1071,6 +1071,8 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), + DEFINE_PROP_BOOL("zvkb", RISCVCPU, cfg.ext_zvkb, false), + /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:35 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2m-0008Jm-JR for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1d-0007Db-85 for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:21 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1a-00070W-Cz for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:20 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1K-007gSL-Dc; Thu, 19 Jan 2023 14:36:03 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence Hunter Subject: [RFC PATCH 18/39] target/riscv: Add vaesz.vs decoding, translation and execution support Date: Thu, 19 Jan 2023 14:35:07 +0000 Message-Id: <20230119143528.1290950-19-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:27 -0000 Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 5 +++-- target/riscv/vcrypto_helper.c | 2 ++ 4 files changed, 7 insertions(+), 2 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 9895bf5712..def126a59b 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1187,3 +1187,4 @@ DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 753039e954..b4ddc2586c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -916,3 +916,4 @@ vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1 vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1 vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1 vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 +vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/insn_trans/trans_rvzvkns.c.inc index 2c70227f8b..145b13bc8c 100644 --- a/target/riscv/insn_trans/trans_rvzvkns.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -43,7 +43,7 @@ static bool vaes_check_vv(DisasContext *s, arg_rmr *a) static bool vaes_check_overlap(DisasContext *s, int vd, int vs2) { int8_t op_size = s->lmul <= 0 ? 1 : 1 << s->lmul; - return !is_overlapped(vd, op_size, vs2, op_size); + return !is_overlapped(vd, op_size, vs2, 1); } static bool vaes_check_vs(DisasContext *s, arg_rmr *a) @@ -52,7 +52,7 @@ static bool vaes_check_vs(DisasContext *s, arg_rmr *a) vaes_check_overlap(s, a->rd, a->rs2) && s->cfg_ptr->ext_zvkns == true && vext_check_isa_ill(s) && - require_align(a->rd, s->lmul) && require_align(a->rs2, s->lmul) && + require_align(a->rd, s->lmul) && s->vstart % 4 == 0 && s->sew == MO_32; } @@ -62,3 +62,4 @@ GEN_V_UNMASKED_TRANS(vaesdf_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesdf_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesdm_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs) +GEN_V_UNMASKED_TRANS(vaesz_vs, vaes_check_vs) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 699bf25bbd..39e2498b7d 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -341,3 +341,5 @@ GEN_ZVKNS_HELPER_VS(vaesdm_vs, aes_inv_shift_bytes(round_state); aes_inv_sub_bytes(round_state); xor_round_key(round_state, (uint8_t *)round_key); aes_inv_mix_cols(round_state);) +GEN_ZVKNS_HELPER_VS(vaesz_vs, + xor_round_key(round_state, (uint8_t *)round_key);) -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:42 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2p-0008NS-5f for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1e-0007ET-Q4 for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:27 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1a-0006zu-KX for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:22 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1H-007gSL-MS; Thu, 19 Jan 2023 14:36:00 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence Hunter , Nazar Kazakov Subject: [RFC PATCH 12/39] target/riscv: Add vaesef.vv decoding, translation and execution support Date: Thu, 19 Jan 2023 14:35:01 +0000 Message-Id: <20230119143528.1290950-13-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:27 -0000 X-List-Received-Date: Thu, 19 Jan 2023 14:36:27 -0000 Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 4 ++ target/riscv/insn_trans/trans_rvzvkns.c.inc | 42 ++++++++++++ target/riscv/translate.c | 1 + target/riscv/vcrypto_helper.c | 75 +++++++++++++++++++++ 5 files changed, 124 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzvkns.c.inc diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 5de615ea78..bdfa63302e 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1180,3 +1180,5 @@ DEF_HELPER_6(vandn_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vandn_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index d6f5e4d198..fdaab9a189 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -74,6 +74,7 @@ @r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd @r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd +@r2_vm_1 ...... . ..... ..... ... ..... ....... &rmr vm=1 %rs2 %rd @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd @r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd @r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd @@ -907,3 +908,6 @@ vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm vandn_vi 000001 . ..... ..... 011 ..... 1010111 @r_vm vandn_vv 000001 . ..... ..... 000 ..... 1010111 @r_vm vandn_vx 000001 . ..... ..... 100 ..... 1010111 @r_vm + +# *** RV64 Zvkns vector crypto extension *** +vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/insn_trans/trans_rvzvkns.c.inc new file mode 100644 index 0000000000..f079425614 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -0,0 +1,42 @@ +#define GEN_V_UNMASKED_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ +{ \ + if (CHECK(s, a)) { \ + TCGv_ptr rd_v, rs2_v; \ + TCGv_i32 desc; \ + uint32_t data = 0; \ + \ + TCGLabel *over = gen_new_label(); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data = FIELD_DP32(data, VDATA, VTA, s->vta); \ + data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \ + data = FIELD_DP32(data, VDATA, VMA, s->vma); \ + rd_v = tcg_temp_new_ptr(); \ + rs2_v = tcg_temp_new_ptr(); \ + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data)); \ + tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); \ + tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); \ + gen_helper_##NAME(rd_v, rs2_v, cpu_env, desc); \ + tcg_temp_free_ptr(rd_v); \ + tcg_temp_free_ptr(rs2_v); \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + + +static bool vaes_check_vv(DisasContext *s, arg_rmr *a) +{ + return require_rvv(s) && + s->cfg_ptr->ext_zvkns == true && + vext_check_isa_ill(s) && + require_align(a->rd, s->lmul) && require_align(a->rs2, s->lmul) && + s->vstart % 4 == 0 && s->sew == MO_32; +} +GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 71684c10f3..8d39743de2 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1064,6 +1064,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_rvzfh.c.inc" #include "insn_trans/trans_rvk.c.inc" #include "insn_trans/trans_rvzvkb.c.inc" +#include "insn_trans/trans_rvzvkns.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 900e68dfb0..59d7d32a05 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -3,6 +3,7 @@ #include "qemu/bitops.h" #include "qemu/bswap.h" #include "cpu.h" +#include "crypto/aes.h" #include "exec/memop.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -154,3 +155,77 @@ GEN_VEXT_VX(vandn_vx_b, 1) GEN_VEXT_VX(vandn_vx_h, 2) GEN_VEXT_VX(vandn_vx_w, 4) GEN_VEXT_VX(vandn_vx_d, 8) + +static inline void aes_sub_bytes(uint8_t round_state[4][4]) +{ + for (int j = 0; j < 16; j++) { + round_state[j / 4][j % 4] = AES_sbox[round_state[j / 4][j % 4]]; + } +} + +static inline void aes_shift_bytes(uint8_t round_state[4][4]) +{ + uint8_t temp; + temp = round_state[0][1]; + round_state[0][1] = round_state[1][1]; + round_state[1][1] = round_state[2][1]; + round_state[2][1] = round_state[3][1]; + round_state[3][1] = temp; + temp = round_state[0][2]; + round_state[0][2] = round_state[2][2]; + round_state[2][2] = temp; + temp = round_state[1][2]; + round_state[1][2] = round_state[3][2]; + round_state[3][2] = temp; + temp = round_state[0][3]; + round_state[0][3] = round_state[3][3]; + round_state[3][3] = round_state[2][3]; + round_state[2][3] = round_state[1][3]; + round_state[1][3] = temp; +} + +static inline void xor_round_key(uint8_t round_state[4][4], uint8_t *round_key) +{ + for (int j = 0; j < 16; j++) { + round_state[j / 4][j % 4] = round_state[j / 4][j % 4] ^ (round_key)[j]; + } +} + +#define GEN_ZVKNS_HELPER_VV(NAME, ...) \ +void HELPER(NAME)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + uint64_t *vd = vd_vptr; \ + uint64_t *vs2 = vs2_vptr; \ + uint32_t vl = env->vl; \ + uint32_t total_elems = vext_get_total_elems(env, desc, 4); \ + uint32_t vta = vext_vta(desc); \ + if (env->vl % 4 != 0) { \ + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); \ + } \ + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { \ + uint64_t round_key[2] = { \ + cpu_to_le64(vs2[i * 2 + 0]), \ + cpu_to_le64(vs2[i * 2 + 1]), \ + }; \ + uint8_t round_state[4][4]; \ + cpu_to_le64s(vd + i * 2 + 0); \ + cpu_to_le64s(vd + i * 2 + 1); \ + for (int j = 0; j < 16; j++) { \ + round_state[j / 4][j % 4] = ((uint8_t *)(vd + i * 2))[j]; \ + } \ + __VA_ARGS__; \ + for (int j = 0; j < 16; j++) { \ + ((uint8_t *)(vd + i * 2))[j] = round_state[j / 4][j % 4]; \ + } \ + le64_to_cpus(vd + i * 2 + 0); \ + le64_to_cpus(vd + i * 2 + 1); \ + } \ + env->vstart = 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \ +} + +GEN_ZVKNS_HELPER_VV(vaesef_vv, aes_sub_bytes(round_state); + aes_shift_bytes(round_state); + xor_round_key(round_state, (uint8_t *)round_key);) -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:43 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2w-0008TF-T9 for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1e-0007ER-Ja for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:27 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1b-00071N-5C for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:22 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1N-007gSL-1H; Thu, 19 Jan 2023 14:36:05 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Nazar Kazakov Subject: [RFC PATCH 24/39] target/riscv: add zvknh cpu properties Date: Thu, 19 Jan 2023 14:35:13 +0000 Message-Id: <20230119143528.1290950-25-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:27 -0000 From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 660af57038..50bc96be5c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -101,6 +101,8 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), ISA_EXT_DATA_ENTRY(zvkb, true, PRIV_VERSION_1_12_0, ext_zvkb), + ISA_EXT_DATA_ENTRY(zvknha, true, PRIV_VERSION_1_12_0, ext_zvknha), + ISA_EXT_DATA_ENTRY(zvknhb, true, PRIV_VERSION_1_12_0, ext_zvknhb), ISA_EXT_DATA_ENTRY(zvkns, true, PRIV_VERSION_1_12_0, ext_zvkns), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 56008ef9b9..ebee902806 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -462,6 +462,8 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; bool ext_zvkb; + bool ext_zvknha; + bool ext_zvknhb; bool ext_zvkns; bool ext_zmmul; bool ext_smaia; -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:43 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2x-0008Uk-32 for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1Q-000790-73 for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:15 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1J-0006z2-Id for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:06 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1D-007gSL-01; Thu, 19 Jan 2023 14:35:55 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence Hunter , Kiran Ostrolenk , Nazar Kazakov Subject: [RFC PATCH 03/39] target/riscv: Add vclmul.vx decoding, translation and execution support Date: Thu, 19 Jan 2023 14:34:52 +0000 Message-Id: <20230119143528.1290950-4-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:16 -0000 X-List-Received-Date: Thu, 19 Jan 2023 14:36:16 -0000 X-List-Received-Date: Thu, 19 Jan 2023 14:36:16 -0000 X-List-Received-Date: Thu, 19 Jan 2023 14:36:16 -0000 Co-authored-by: Kiran Ostrolenk Co-authored-by: Nazar Kazakov Signed-off-by: Kiran Ostrolenk Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 54 ++++++++++++++++++++++ target/riscv/vcrypto_helper.c | 12 +++++ target/riscv/vector_helper.c | 36 --------------- target/riscv/vector_internals.c | 24 ++++++++++ target/riscv/vector_internals.h | 16 +++++++ 7 files changed, 108 insertions(+), 36 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index e9127c9ccb..6c786ef6f3 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1139,3 +1139,4 @@ DEF_HELPER_FLAGS_3(sm4ks, TCG_CALL_NO_RWG_SE, tl, tl, tl, tl) /* Vector crypto functions */ DEF_HELPER_6(vclmul_vv, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vclmul_vx, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 5ddee69d60..4a7421354d 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -893,3 +893,4 @@ sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes # *** RV64 Zvkb vector crypto extension *** vclmul_vv 001100 . ..... ..... 010 ..... 1010111 @r_vm +vclmul_vx 001100 . ..... ..... 110 ..... 1010111 @r_vm diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn_trans/trans_rvzvkb.c.inc index fb1995f737..6e8b81136c 100644 --- a/target/riscv/insn_trans/trans_rvzvkb.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc @@ -39,3 +39,57 @@ static bool vclmul_vv_check(DisasContext *s, arg_rmrr *a) } GEN_VV_MASKED_TRANS(vclmul_vv, vclmul_vv_check) + +#define GEN_VX_MASKED_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \ +{ \ + if (CHECK(s, a)) { \ + TCGv_ptr rd_v, v0_v, rs2_v; \ + TCGv rs1; \ + TCGv_i32 desc; \ + uint32_t data = 0; \ + \ + TCGLabel *over = gen_new_label(); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ + \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data = FIELD_DP32(data, VDATA, VTA, s->vta); \ + data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \ + data = FIELD_DP32(data, VDATA, VMA, s->vma); \ + \ + rd_v = tcg_temp_new_ptr(); \ + v0_v = tcg_temp_new_ptr(); \ + rs1 = get_gpr(s, a->rs1, EXT_ZERO); \ + rs2_v = tcg_temp_new_ptr(); \ + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data)); \ + tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); \ + tcg_gen_addi_ptr(v0_v, cpu_env, vreg_ofs(s, 0)); \ + tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); \ + gen_helper_##NAME(rd_v, v0_v, rs1, rs2_v, cpu_env, desc); \ + tcg_temp_free_ptr(rd_v); \ + tcg_temp_free_ptr(v0_v); \ + tcg_temp_free_ptr(rs2_v); \ + \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +static bool zvkb_vx_check(DisasContext *s, arg_rmrr *a) +{ + return opivx_check(s, a) && + s->cfg_ptr->ext_zvkb == true; +} + +static bool vclmul_vx_check(DisasContext *s, arg_rmrr *a) +{ + return zvkb_vx_check(s, a) && + s->sew == MO_64; +} + +GEN_VX_MASKED_TRANS(vclmul_vx, vclmul_vx_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 8a11e56754..c453d348ad 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -20,4 +20,16 @@ static void do_vclmul_vv(void *vd, void *vs1, void *vs2, int i) ((uint64_t *)vd)[i] = result; } +static void do_vclmul_vx(void *vd, target_long rs1, void *vs2, int i) +{ + uint64_t result = 0; + for (int j = 63; j >= 0; j--) { + if ((rs1 >> j) & 1) { + result ^= (((uint64_t *)vs2)[i] << j); + } + } + ((uint64_t *)vd)[i] = result; +} + GEN_VEXT_VV(vclmul_vv, 8) +GEN_VEXT_VX(vclmul_vx, 8) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index def1b21414..ab470092f6 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -747,8 +747,6 @@ GEN_VEXT_VV(vsub_vv_h, 2) GEN_VEXT_VV(vsub_vv_w, 4) GEN_VEXT_VV(vsub_vv_d, 8) -typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i); - /* * (T1)s1 gives the real operator type. * (TX1)(T1)s1 expands the operator type of widen or narrow operations. @@ -773,40 +771,6 @@ RVVCALL(OPIVX2, vrsub_vx_h, OP_SSS_H, H2, H2, DO_RSUB) RVVCALL(OPIVX2, vrsub_vx_w, OP_SSS_W, H4, H4, DO_RSUB) RVVCALL(OPIVX2, vrsub_vx_d, OP_SSS_D, H8, H8, DO_RSUB) -static void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, - CPURISCVState *env, uint32_t desc, - opivx2_fn fn, uint32_t esz) -{ - uint32_t vm = vext_vm(desc); - uint32_t vl = env->vl; - uint32_t total_elems = vext_get_total_elems(env, desc, esz); - uint32_t vta = vext_vta(desc); - uint32_t vma = vext_vma(desc); - uint32_t i; - - for (i = env->vstart; i < vl; i++) { - if (!vm && !vext_elem_mask(v0, i)) { - /* set masked-off elements to 1s */ - vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); - continue; - } - fn(vd, s1, vs2, i); - } - env->vstart = 0; - /* set tail elements to 1s */ - vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); -} - -/* generate the helpers for OPIVX */ -#define GEN_VEXT_VX(NAME, ESZ) \ -void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ - void *vs2, CPURISCVState *env, \ - uint32_t desc) \ -{ \ - do_vext_vx(vd, v0, s1, vs2, env, desc, \ - do_##NAME, ESZ); \ -} - GEN_VEXT_VX(vadd_vx_b, 1) GEN_VEXT_VX(vadd_vx_h, 2) GEN_VEXT_VX(vadd_vx_w, 4) diff --git a/target/riscv/vector_internals.c b/target/riscv/vector_internals.c index a264797882..b23fa4dd74 100644 --- a/target/riscv/vector_internals.c +++ b/target/riscv/vector_internals.c @@ -37,3 +37,27 @@ void do_vext_vv(void *vd, void *v0, void *vs1, void *vs2, /* set tail elements to 1s */ vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); } + +void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, + CPURISCVState *env, uint32_t desc, + opivx2_fn fn, uint32_t esz) +{ + uint32_t vm = vext_vm(desc); + uint32_t vl = env->vl; + uint32_t total_elems = vext_get_total_elems(env, desc, esz); + uint32_t vta = vext_vta(desc); + uint32_t vma = vext_vma(desc); + uint32_t i; + + for (i = env->vstart; i < vl; i++) { + if (!vm && !vext_elem_mask(v0, i)) { + /* set masked-off elements to 1s */ + vext_set_elems_1s(vd, vma, i * esz, (i + 1) * esz); + continue; + } + fn(vd, s1, vs2, i); + } + env->vstart = 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * esz, total_elems * esz); +} diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h index f61803acc0..49529d2379 100644 --- a/target/riscv/vector_internals.h +++ b/target/riscv/vector_internals.h @@ -113,4 +113,20 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, \ do_##NAME, ESZ); \ } +typedef void opivx2_fn(void *vd, target_long s1, void *vs2, int i); + +void do_vext_vx(void *vd, void *v0, target_long s1, void *vs2, + CPURISCVState *env, uint32_t desc, + opivx2_fn fn, uint32_t esz); + +/* generate the helpers for OPIVX */ +#define GEN_VEXT_VX(NAME, ESZ) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong s1, \ + void *vs2, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + do_vext_vx(vd, v0, s1, vs2, env, desc, \ + do_##NAME, ESZ); \ +} + #endif /* TARGET_RISCV_VECTOR_INTERNAL_H */ -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:43 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2x-00005Z-A0 for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1S-00079q-MR for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:15 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1P-000701-Uh for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:10 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1I-007gSL-53; Thu, 19 Jan 2023 14:36:01 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence Hunter Subject: [RFC PATCH 13/39] target/riscv: Add vaesef.vs decoding, translation and execution support Date: Thu, 19 Jan 2023 14:35:02 +0000 Message-Id: <20230119143528.1290950-14-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:16 -0000 Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 18 ++++++++++ target/riscv/vcrypto_helper.c | 38 +++++++++++++++++++++ 4 files changed, 58 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index bdfa63302e..42349837ef 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1182,3 +1182,4 @@ DEF_HELPER_6(vandn_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vandn_vx_d, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index fdaab9a189..0d65c2ea27 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -911,3 +911,4 @@ vandn_vx 000001 . ..... ..... 100 ..... 1010111 @r_vm # *** RV64 Zvkns vector crypto extension *** vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1 +vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/insn_trans/trans_rvzvkns.c.inc index f079425614..dc4310882d 100644 --- a/target/riscv/insn_trans/trans_rvzvkns.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -39,4 +39,22 @@ static bool vaes_check_vv(DisasContext *s, arg_rmr *a) require_align(a->rd, s->lmul) && require_align(a->rs2, s->lmul) && s->vstart % 4 == 0 && s->sew == MO_32; } + +static bool vaes_check_overlap(DisasContext *s, int vd, int vs2) +{ + int8_t op_size = s->lmul <= 0 ? 1 : 1 << s->lmul; + return !is_overlapped(vd, op_size, vs2, op_size); +} + +static bool vaes_check_vs(DisasContext *s, arg_rmr *a) +{ + return require_rvv(s) && + vaes_check_overlap(s, a->rd, a->rs2) && + s->cfg_ptr->ext_zvkns == true && + vext_check_isa_ill(s) && + require_align(a->rd, s->lmul) && require_align(a->rs2, s->lmul) && + s->vstart % 4 == 0 && s->sew == MO_32; +} + GEN_V_UNMASKED_TRANS(vaesef_vv, vaes_check_vv) +GEN_V_UNMASKED_TRANS(vaesef_vs, vaes_check_vs) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 59d7d32a05..f59e090c03 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -226,6 +226,44 @@ void HELPER(NAME)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, \ vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \ } +#define GEN_ZVKNS_HELPER_VS(NAME, ...) \ +void HELPER(NAME)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, \ + uint32_t desc) \ +{ \ + uint64_t *vd = vd_vptr; \ + uint64_t *vs2 = vs2_vptr; \ + uint32_t vl = env->vl; \ + uint32_t total_elems = vext_get_total_elems(env, desc, 4); \ + uint32_t vta = vext_vta(desc); \ + if (env->vl % 4 != 0) { \ + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); \ + } \ + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { \ + uint64_t round_key[2] = { \ + cpu_to_le64(vs2[0]), \ + cpu_to_le64(vs2[1]), \ + }; \ + uint8_t round_state[4][4]; \ + cpu_to_le64s(vd + i * 2 + 0); \ + cpu_to_le64s(vd + i * 2 + 1); \ + for (int j = 0; j < 16; j++) { \ + round_state[j / 4][j % 4] = ((uint8_t *)(vd + i * 2))[j]; \ + } \ + __VA_ARGS__; \ + for (int j = 0; j < 16; j++) { \ + ((uint8_t *)(vd + i * 2))[j] = round_state[j / 4][j % 4]; \ + } \ + le64_to_cpus(vd + i * 2 + 0); \ + le64_to_cpus(vd + i * 2 + 1); \ + } \ + env->vstart = 0; \ + /* set tail elements to 1s */ \ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); \ +} + GEN_ZVKNS_HELPER_VV(vaesef_vv, aes_sub_bytes(round_state); aes_shift_bytes(round_state); xor_round_key(round_state, (uint8_t *)round_key);) +GEN_ZVKNS_HELPER_VS(vaesef_vs, aes_sub_bytes(round_state); + aes_shift_bytes(round_state); + xor_round_key(round_state, (uint8_t *)round_key);) -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:43 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2x-00007Z-GS for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1d-0007Dc-C0 for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:21 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1a-000718-CE for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:21 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1L-007gSL-PG; Thu, 19 Jan 2023 14:36:04 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Nazar Kazakov Subject: [RFC PATCH 21/39] target/riscv: Add vaeskf1.vi decoding, translation and execution support Date: Thu, 19 Jan 2023 14:35:10 +0000 Message-Id: <20230119143528.1290950-22-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:27 -0000 From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 45 +++++++++++++++++++++ target/riscv/vcrypto_helper.c | 42 +++++++++++++++++++ 4 files changed, 89 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 85981f2cad..2ac02dde01 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1190,3 +1190,4 @@ DEF_HELPER_4(vaesem_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) +DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index cc91ca8794..325e2401c8 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -919,3 +919,4 @@ vaesem_vs 101001 1 ..... 00010 010 ..... 1110111 @r2_vm_1 vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1 vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 +vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/insn_trans/trans_rvzvkns.c.inc index fae48d63dc..62c3cd83e7 100644 --- a/target/riscv/insn_trans/trans_rvzvkns.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -65,3 +65,48 @@ GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesz_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesem_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesem_vs, vaes_check_vs) + +#define GEN_VI_UNMASKED_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ +{ \ + if (CHECK(s, a)) { \ + TCGv_ptr rd_v, rs2_v; \ + TCGv_i32 uimm_v, desc; \ + uint32_t data = 0; \ + \ + TCGLabel *over = gen_new_label(); \ + tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \ + tcg_gen_brcond_tl(TCG_COND_GEU, cpu_vstart, cpu_vl, over); \ + \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + data = FIELD_DP32(data, VDATA, VTA, s->vta); \ + data = FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s); \ + data = FIELD_DP32(data, VDATA, VMA, s->vma); \ + \ + rd_v = tcg_temp_new_ptr(); \ + rs2_v = tcg_temp_new_ptr(); \ + uimm_v = tcg_constant_i32(a->rs1); \ + desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8, \ + s->cfg_ptr->vlen / 8, data)); \ + tcg_gen_addi_ptr(rd_v, cpu_env, vreg_ofs(s, a->rd)); \ + tcg_gen_addi_ptr(rs2_v, cpu_env, vreg_ofs(s, a->rs2)); \ + gen_helper_##NAME(rd_v, rs2_v, uimm_v, cpu_env, desc); \ + tcg_temp_free_ptr(rd_v); \ + tcg_temp_free_ptr(rs2_v); \ + mark_vs_dirty(s); \ + gen_set_label(over); \ + return true; \ + } \ + return false; \ +} + +static bool vaeskf1_check(DisasContext *s, arg_vaeskf1_vi * a) +{ + return require_rvv(s) && s->cfg_ptr->ext_zvkns == true && + vext_check_isa_ill(s) && s->vstart % 4 == 0 && s->sew == MO_32 && + require_align(a->rd, s->lmul) && require_align(a->rs2, s->lmul) && + a->rs1 >= 1 && a->rs1 <= 10; +} + +GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 883739f4ac..13ceb705cd 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -363,3 +363,45 @@ GEN_ZVKNS_HELPER_VS(vaesdm_vs, aes_inv_shift_bytes(round_state); aes_inv_mix_cols(round_state);) GEN_ZVKNS_HELPER_VS(vaesz_vs, xor_round_key(round_state, (uint8_t *)round_key);) + +void HELPER(vaeskf1_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, + CPURISCVState *env, uint32_t desc) +{ + uint32_t *vd = vd_vptr; + uint32_t *vs2 = vs2_vptr; + uint32_t vl = env->vl; + uint32_t total_elems = vext_get_total_elems(env, desc, 4); + uint32_t vta = vext_vta(desc); + if (vl % 4 != 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { + uint32_t rk[8]; + static const uint32_t rcon[] = { + 0x01000000, 0x02000000, 0x04000000, 0x08000000, 0x10000000, + 0x20000000, 0x40000000, 0x80000000, 0x1B000000, 0x36000000, + }; + + rk[0] = bswap32(vs2[i * 4 + H4(0)]); + rk[1] = bswap32(vs2[i * 4 + H4(1)]); + rk[2] = bswap32(vs2[i * 4 + H4(2)]); + rk[3] = bswap32(vs2[i * 4 + H4(3)]); + + rk[4] = rk[0] ^ (AES_Te4[(rk[3] >> 16) & 0xff] & 0xff000000) ^ + (AES_Te4[(rk[3] >> 8) & 0xff] & 0x00ff0000) ^ + (AES_Te4[(rk[3] >> 0) & 0xff] & 0x0000ff00) ^ + (AES_Te4[(rk[3] >> 24) & 0xff] & 0x000000ff) ^ rcon[uimm - 1]; + rk[5] = rk[1] ^ rk[4]; + rk[6] = rk[2] ^ rk[5]; + rk[7] = rk[3] ^ rk[6]; + + vd[i * 4 + H4(0)] = bswap32(rk[4]); + vd[i * 4 + H4(1)] = bswap32(rk[5]); + vd[i * 4 + H4(2)] = bswap32(rk[6]); + vd[i * 4 + H4(3)] = bswap32(rk[7]); + } + env->vstart = 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); +} -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:43 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2x-00008z-O6 for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1e-0007ES-Li for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:27 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1a-000713-TB for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:22 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1K-007gSL-VH; Thu, 19 Jan 2023 14:36:03 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, William Salmon Subject: [RFC PATCH 19/39] target/riscv: Add vaesem.vv decoding, translation and execution support Date: Thu, 19 Jan 2023 14:35:08 +0000 Message-Id: <20230119143528.1290950-20-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:27 -0000 From: William Salmon Signed-off-by: William Salmon --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 1 + target/riscv/vcrypto_helper.c | 17 +++++++++++++++++ 4 files changed, 20 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index def126a59b..4bfc9a3387 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1185,6 +1185,7 @@ DEF_HELPER_4(vaesef_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesef_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdf_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdf_vs, void, ptr, ptr, env, i32) +DEF_HELPER_4(vaesem_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index b4ddc2586c..f31414f72c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -914,6 +914,7 @@ vaesef_vv 101000 1 ..... 00011 010 ..... 1110111 @r2_vm_1 vaesef_vs 101001 1 ..... 00011 010 ..... 1110111 @r2_vm_1 vaesdf_vv 101000 1 ..... 00001 010 ..... 1110111 @r2_vm_1 vaesdf_vs 101001 1 ..... 00001 010 ..... 1110111 @r2_vm_1 +vaesem_vv 101000 1 ..... 00010 010 ..... 1110111 @r2_vm_1 vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1 vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/insn_trans/trans_rvzvkns.c.inc index 145b13bc8c..2e0523ec62 100644 --- a/target/riscv/insn_trans/trans_rvzvkns.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -63,3 +63,4 @@ GEN_V_UNMASKED_TRANS(vaesdf_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesdm_vv, vaes_check_vv) GEN_V_UNMASKED_TRANS(vaesdm_vs, vaes_check_vs) GEN_V_UNMASKED_TRANS(vaesz_vs, vaes_check_vs) +GEN_V_UNMASKED_TRANS(vaesem_vv, vaes_check_vv) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 39e2498b7d..a1d66a64aa 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -251,6 +251,20 @@ static inline void aes_inv_mix_cols(uint8_t round_state[4][4]) } } +static inline void aes_mix_cols(uint8_t round_state[4][4]) +{ + uint8_t a, b; + for (int j = 0; j < 4; ++j) { + a = round_state[j][0]; + b = round_state[j][0] ^ round_state[j][1] ^ round_state[j][2] ^ + round_state[j][3]; + round_state[j][0] ^= xtime(round_state[j][0] ^ round_state[j][1]) ^ b; + round_state[j][1] ^= xtime(round_state[j][1] ^ round_state[j][2]) ^ b; + round_state[j][2] ^= xtime(round_state[j][2] ^ round_state[j][3]) ^ b; + round_state[j][3] ^= xtime(round_state[j][3] ^ a) ^ b; + } +} + #define GEN_ZVKNS_HELPER_VV(NAME, ...) \ void HELPER(NAME)(void *vd_vptr, void *vs2_vptr, CPURISCVState *env, \ uint32_t desc) \ @@ -333,6 +347,9 @@ GEN_ZVKNS_HELPER_VV(vaesdf_vv, aes_inv_shift_bytes(round_state); GEN_ZVKNS_HELPER_VS(vaesdf_vs, aes_inv_shift_bytes(round_state); aes_inv_sub_bytes(round_state); xor_round_key(round_state, (uint8_t *)round_key);) +GEN_ZVKNS_HELPER_VV(vaesem_vv, aes_shift_bytes(round_state); + aes_sub_bytes(round_state); aes_mix_cols(round_state); + xor_round_key(round_state, (uint8_t *)round_key);) GEN_ZVKNS_HELPER_VV(vaesdm_vv, aes_inv_shift_bytes(round_state); aes_inv_sub_bytes(round_state); xor_round_key(round_state, (uint8_t *)round_key); -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:44 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2x-0000Ad-Vc for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1e-0007EP-Cq for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:27 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1a-0006zS-LI for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:22 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1F-007gSL-33; Thu, 19 Jan 2023 14:35:58 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Nazar Kazakov Subject: [RFC PATCH 08/39] target/riscv: Add vrev8.v decoding, translation and execution support Date: Thu, 19 Jan 2023 14:34:57 +0000 Message-Id: <20230119143528.1290950-9-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:27 -0000 From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h | 4 ++++ target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkb.c.inc | 1 + target/riscv/vcrypto_helper.c | 10 ++++++++++ 4 files changed, 16 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index c94627d8a4..c980d52828 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1163,6 +1163,10 @@ DEF_HELPER_6(vrol_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrol_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrol_vx_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_5(vrev8_v_b, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vrev8_v_d, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_b, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vbrev8_v_w, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 782632a165..342199abc0 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -903,3 +903,4 @@ vror_vx 010100 . ..... ..... 100 ..... 1010111 @r_vm vror_vi 010100 . ..... ..... 011 ..... 1010111 @r_vm vror_vi2 010101 . ..... ..... 011 ..... 1010111 @r_vm vbrev8_v 010010 . ..... 01000 010 ..... 1010111 @r2_vm +vrev8_v 010010 . ..... 01001 010 ..... 1010111 @r2_vm diff --git a/target/riscv/insn_trans/trans_rvzvkb.c.inc b/target/riscv/insn_trans/trans_rvzvkb.c.inc index 50eee7c0a3..b0c8347ab1 100644 --- a/target/riscv/insn_trans/trans_rvzvkb.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkb.c.inc @@ -156,3 +156,4 @@ static bool vxrev8_check(DisasContext *s, arg_rmr *a) } GEN_OPIV_TRANS(vbrev8_v, vxrev8_check) +GEN_OPIV_TRANS(vrev8_v, vxrev8_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 303a656141..b09fe5fa2a 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -125,3 +125,13 @@ GEN_VEXT_V(vbrev8_v_b, 1) GEN_VEXT_V(vbrev8_v_h, 2) GEN_VEXT_V(vbrev8_v_w, 4) GEN_VEXT_V(vbrev8_v_d, 8) + +#define DO_VREV8_B(a) (a) +RVVCALL(OPIVV1, vrev8_v_b, OP_UU_B, H1, H1, DO_VREV8_B) +RVVCALL(OPIVV1, vrev8_v_h, OP_UU_H, H2, H2, bswap16) +RVVCALL(OPIVV1, vrev8_v_w, OP_UU_W, H4, H4, bswap32) +RVVCALL(OPIVV1, vrev8_v_d, OP_UU_D, H8, H8, bswap64) +GEN_VEXT_V(vrev8_v_b, 1) +GEN_VEXT_V(vrev8_v_h, 2) +GEN_VEXT_V(vrev8_v_w, 4) +GEN_VEXT_V(vrev8_v_d, 8) -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:45 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2y-0000DM-Bw for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1j-0007Eo-6Y for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:28 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1b-00071M-6g for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:23 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1M-007gSL-L8; Thu, 19 Jan 2023 14:36:05 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Nazar Kazakov Subject: [RFC PATCH 23/39] target/riscv: expose zvkns cpu property Date: Thu, 19 Jan 2023 14:35:12 +0000 Message-Id: <20230119143528.1290950-24-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:29 -0000 From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fb8bd5c779..660af57038 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1073,6 +1073,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), DEFINE_PROP_BOOL("zvkb", RISCVCPU, cfg.ext_zvkb, false), + DEFINE_PROP_BOOL("zvkns", RISCVCPU, cfg.ext_zvkns, false), /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:46 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2z-0000EW-At for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1j-0007Ei-5I for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:28 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1b-00071G-5s for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:23 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1M-007gSL-7S; Thu, 19 Jan 2023 14:36:05 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Nazar Kazakov Subject: [RFC PATCH 22/39] target/riscv: Add vaeskf2.vi decoding, translation and execution support Date: Thu, 19 Jan 2023 14:35:11 +0000 Message-Id: <20230119143528.1290950-23-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:29 -0000 From: Nazar Kazakov Signed-off-by: Nazar Kazakov --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvkns.c.inc | 9 ++++ target/riscv/vcrypto_helper.c | 56 +++++++++++++++++++++ 4 files changed, 67 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 2ac02dde01..312f59bb38 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1191,3 +1191,4 @@ DEF_HELPER_4(vaesdm_vv, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesdm_vs, void, ptr, ptr, env, i32) DEF_HELPER_4(vaesz_vs, void, ptr, ptr, env, i32) DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32) +DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 325e2401c8..1eed0a6b26 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -920,3 +920,4 @@ vaesdm_vv 101000 1 ..... 00000 010 ..... 1110111 @r2_vm_1 vaesdm_vs 101001 1 ..... 00000 010 ..... 1110111 @r2_vm_1 vaesz_vs 101001 1 ..... 00111 010 ..... 1110111 @r2_vm_1 vaeskf1_vi 100010 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkns.c.inc b/target/riscv/insn_trans/trans_rvzvkns.c.inc index 62c3cd83e7..0abb7811b7 100644 --- a/target/riscv/insn_trans/trans_rvzvkns.c.inc +++ b/target/riscv/insn_trans/trans_rvzvkns.c.inc @@ -109,4 +109,13 @@ static bool vaeskf1_check(DisasContext *s, arg_vaeskf1_vi * a) a->rs1 >= 1 && a->rs1 <= 10; } +static bool vaeskf2_check(DisasContext *s, arg_vaeskf2_vi *a) +{ + return require_rvv(s) && s->cfg_ptr->ext_zvkns == true && + vext_check_isa_ill(s) && s->vstart % 4 == 0 && s->sew == MO_32 && + require_align(a->rd, s->lmul) && require_align(a->rs2, s->lmul) && + a->rs1 >= 2 && a->rs1 <= 14; +} + GEN_VI_UNMASKED_TRANS(vaeskf1_vi, vaeskf1_check) +GEN_VI_UNMASKED_TRANS(vaeskf2_vi, vaeskf2_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 13ceb705cd..50207b4ff0 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -405,3 +405,59 @@ void HELPER(vaeskf1_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, /* set tail elements to 1s */ vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); } + +void HELPER(vaeskf2_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, + CPURISCVState *env, uint32_t desc) +{ + uint32_t *vd = vd_vptr; + uint32_t *vs2 = vs2_vptr; + uint32_t vl = env->vl; + uint32_t total_elems = vext_get_total_elems(env, desc, 4); + uint32_t vta = vext_vta(desc); + if (env->vl % 4 != 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { + uint32_t rk[12]; + static const uint32_t rcon[] = { + 0x01000000, 0x02000000, 0x04000000, 0x08000000, 0x10000000, + 0x20000000, 0x40000000, 0x80000000, 0x1B000000, 0x36000000, + }; + + rk[0] = bswap32(vd[i * 4 + H4(0)]); + rk[1] = bswap32(vd[i * 4 + H4(1)]); + rk[2] = bswap32(vd[i * 4 + H4(2)]); + rk[3] = bswap32(vd[i * 4 + H4(3)]); + rk[4] = bswap32(vs2[i * 4 + H4(0)]); + rk[5] = bswap32(vs2[i * 4 + H4(1)]); + rk[6] = bswap32(vs2[i * 4 + H4(2)]); + rk[7] = bswap32(vs2[i * 4 + H4(3)]); + + if (uimm % 2 == 0) { + rk[8] = rk[0] ^ (AES_Te4[(rk[7] >> 16) & 0xff] & 0xff000000) ^ + (AES_Te4[(rk[7] >> 8) & 0xff] & 0x00ff0000) ^ + (AES_Te4[(rk[7] >> 0) & 0xff] & 0x0000ff00) ^ + (AES_Te4[(rk[7] >> 24) & 0xff] & 0x000000ff) ^ + rcon[(uimm - 1) / 2]; + rk[9] = rk[1] ^ rk[8]; + rk[10] = rk[2] ^ rk[9]; + rk[11] = rk[3] ^ rk[10]; + } else { + rk[8] = rk[0] ^ (AES_Te4[(rk[7] >> 24) & 0xff] & 0xff000000) ^ + (AES_Te4[(rk[7] >> 16) & 0xff] & 0x00ff0000) ^ + (AES_Te4[(rk[7] >> 8) & 0xff] & 0x0000ff00) ^ + (AES_Te4[(rk[7] >> 0) & 0xff] & 0x000000ff); + rk[9] = rk[1] ^ rk[8]; + rk[10] = rk[2] ^ rk[9]; + rk[11] = rk[3] ^ rk[10]; + } + + vd[i * 4 + H4(0)] = bswap32(rk[8]); + vd[i * 4 + H4(1)] = bswap32(rk[9]); + vd[i * 4 + H4(2)] = bswap32(rk[10]); + vd[i * 4 + H4(3)] = bswap32(rk[11]); + } + env->vstart = 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, vl * 4, total_elems * 4); +} -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:46 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW30-0000FR-6j for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1j-0007Eh-4W for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:28 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1e-00072V-0c for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:23 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1N-007gSL-UD; Thu, 19 Jan 2023 14:36:06 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence Hunter , Nazar Kazakov Subject: [RFC PATCH 26/39] target/riscv: Add vsha2c[hl].vv decoding, translation and execution support Date: Thu, 19 Jan 2023 14:35:15 +0000 Message-Id: <20230119143528.1290950-27-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:29 -0000 Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvzvknh.c.inc | 2 + target/riscv/vcrypto_helper.c | 153 ++++++++++++++++++++ 4 files changed, 159 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 6e7777c879..911270c387 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1194,3 +1194,5 @@ DEF_HELPER_5(vaeskf1_vi, void, ptr, ptr, i32, env, i32) DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32) DEF_HELPER_5(vsha2ms_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsha2ch_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsha2cl_vv, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 57fbd63d91..2387bc179c 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -924,3 +924,5 @@ vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1 # *** RV64 Zvknh vector crypto extension *** vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvknh.c.inc b/target/riscv/insn_trans/trans_rvzvknh.c.inc index ff30400100..4d4d26eae5 100644 --- a/target/riscv/insn_trans/trans_rvzvknh.c.inc +++ b/target/riscv/insn_trans/trans_rvzvknh.c.inc @@ -43,3 +43,5 @@ static bool vsha_check(DisasContext *s, arg_rmrr *a) } GEN_VV_UNMASKED_TRANS(vsha2ms_vv, vsha_check) +GEN_VV_UNMASKED_TRANS(vsha2cl_vv, vsha_check) +GEN_VV_UNMASKED_TRANS(vsha2ch_vv, vsha_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index af596cce09..b73581641a 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -541,3 +541,156 @@ void HELPER(vsha2ms_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); env->vstart = 0; } + +static inline uint64_t sum0_64(uint64_t x) +{ + return ror64(x, 28) ^ ror64(x, 34) ^ ror64(x, 39); +} + +static inline uint32_t sum0_32(uint32_t x) +{ + return ror32(x, 2) ^ ror32(x, 13) ^ ror32(x, 22); +} + +static inline uint64_t sum1_64(uint64_t x) +{ + return ror64(x, 14) ^ ror64(x, 18) ^ ror64(x, 41); +} + +static inline uint32_t sum1_32(uint32_t x) +{ + return ror32(x, 6) ^ ror32(x, 11) ^ ror32(x, 25); +} + +#define ch(x, y, z) ((x & y) ^ ((~x) & z)) + +#define maj(x, y, z) ((x & y) ^ (x & z) ^ (y & z)) + +static void vsha2c_64(uint64_t *vs2, uint64_t *vd, uint64_t *vs1) +{ + uint64_t a = vs2[3], b = vs2[2], e = vs2[1], f = vs2[0]; + uint64_t c = vd[3], d = vd[2], g = vd[1], h = vd[0]; + uint64_t W0 = vs1[0], W1 = vs1[1]; + uint64_t T1 = h + sum1_64(e) + ch(e, f, g) + W0; + uint64_t T2 = sum0_64(a) + maj(a, b, c); + + h = g; + g = f; + f = e; + e = d + T1; + d = c; + c = b; + b = a; + a = T1 + T2; + + T1 = h + sum1_64(e) + ch(e, f, g) + W1; + T2 = sum0_64(a) + maj(a, b, c); + h = g; + g = f; + f = e; + e = d + T1; + d = c; + c = b; + b = a; + a = T1 + T2; + + vd[0] = f; + vd[1] = e; + vd[2] = b; + vd[3] = a; +} + +static void vsha2c_32(uint32_t *vs2, uint32_t *vd, uint32_t *vs1) +{ + uint32_t a = vs2[H4(3)], b = vs2[H4(2)], e = vs2[H4(1)], f = vs2[H4(0)]; + uint32_t c = vd[H4(3)], d = vd[H4(2)], g = vd[H4(1)], h = vd[H4(0)]; + uint32_t W0 = vs1[H4(0)], W1 = vs1[H4(1)]; + uint32_t T1 = h + sum1_32(e) + ch(e, f, g) + W0; + uint32_t T2 = sum0_32(a) + maj(a, b, c); + + h = g; + g = f; + f = e; + e = d + T1; + d = c; + c = b; + b = a; + a = T1 + T2; + + T1 = h + sum1_32(e) + ch(e, f, g) + W1; + T2 = sum0_32(a) + maj(a, b, c); + h = g; + g = f; + f = e; + e = d + T1; + d = c; + c = b; + b = a; + a = T1 + T2; + + vd[H4(0)] = f; + vd[H4(1)] = e; + vd[H4(2)] = b; + vd[H4(3)] = a; + +} + +void HELPER(vsha2ch_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, + uint32_t desc) +{ + uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t esz = 0; + uint32_t total_elems; + uint32_t vta = vext_vta(desc); + + if (env->vl % 4 != 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { + if (sew == MO_64) { + esz = 8; + vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i, + ((uint64_t *)vs1) + 4 * i + 2); + } else { + esz = 4; + vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i, + ((uint32_t *)vs1) + 4 * i + 2); + } + } + + /* set tail elements to 1s */ + total_elems = vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart = 0; +} + +void HELPER(vsha2cl_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, + uint32_t desc) +{ + uint32_t sew = FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t esz = 0; + uint32_t total_elems; + uint32_t vta = vext_vta(desc); + + if (env->vl % 4 != 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { + if (sew == MO_64) { + esz = 8; + vsha2c_64(((uint64_t *)vs2) + 4 * i, ((uint64_t *)vd) + 4 * i, + (((uint64_t *)vs1) + 4 * i)); + } else { + esz = 4; + vsha2c_32(((uint32_t *)vs2) + 4 * i, ((uint32_t *)vd) + 4 * i, + (((uint32_t *)vs1) + 4 * i)); + } + } + + /* set tail elements to 1s */ + total_elems = vext_get_total_elems(env, desc, esz); + vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); + env->vstart = 0; +} -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:37:44 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW2y-0000Bm-5o for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:37:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1j-0007En-5u for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:28 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW1e-00072o-0y for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:36:23 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1P-007gSL-7l; Thu, 19 Jan 2023 14:36:08 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence Hunter , Kiran Ostrolenk Subject: [RFC PATCH 29/39] target/riscv: Add vsm3me.vv decoding, translation and execution support Date: Thu, 19 Jan 2023 14:35:18 +0000 Message-Id: <20230119143528.1290950-30-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:36:29 -0000 Co-authored-by: Kiran Ostrolenk Signed-off-by: Lawrence Hunter Signed-off-by: Kiran Ostrolenk --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvzvksh.c.inc | 12 ++++++ target/riscv/translate.c | 1 + target/riscv/vcrypto_helper.c | 43 +++++++++++++++++++++ 5 files changed, 61 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzvksh.c.inc diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 911270c387..36e0d8eff3 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1196,3 +1196,5 @@ DEF_HELPER_5(vaeskf2_vi, void, ptr, ptr, i32, env, i32) DEF_HELPER_5(vsha2ms_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsha2ch_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsha2cl_vv, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 2387bc179c..671614e354 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -926,3 +926,6 @@ vaeskf2_vi 101010 1 ..... ..... 010 ..... 1110111 @r_vm_1 vsha2ms_vv 101101 1 ..... ..... 010 ..... 1110111 @r_vm_1 vsha2ch_vv 101110 1 ..... ..... 010 ..... 1110111 @r_vm_1 vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 + +# *** RV64 Zvksh vector crypto extensions *** +vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvksh.c.inc b/target/riscv/insn_trans/trans_rvzvksh.c.inc new file mode 100644 index 0000000000..2956618d7e --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzvksh.c.inc @@ -0,0 +1,12 @@ +static inline bool vsm3_check(DisasContext *s) +{ + return s->cfg_ptr->ext_zvksh == true && require_rvv(s) && + vext_check_isa_ill(s) && s->vstart % 8 == 0 && s->sew == MO_32; +} + +static inline bool vsm3me_check(DisasContext *s, arg_rmrr *a) +{ + return vsm3_check(s) && vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm); +} + +GEN_VV_UNMASKED_TRANS(vsm3me_vv, vsm3me_check) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 924a89de9f..9ca2cec23a 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1066,6 +1066,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_rvzvkb.c.inc" #include "insn_trans/trans_rvzvkns.c.inc" #include "insn_trans/trans_rvzvknh.c.inc" +#include "insn_trans/trans_rvzvksh.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index b73581641a..4dd5920aa4 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -694,3 +694,46 @@ void HELPER(vsha2cl_vv)(void *vd, void *vs1, void *vs2, CPURISCVState *env, vext_set_elems_1s(vd, vta, env->vl * esz, total_elems * esz); env->vstart = 0; } + +static inline uint32_t p1(uint32_t x) +{ + return (x) ^ rol32((x), 15) ^ rol32((x), 23); +} + +static inline uint32_t zvksh_w(uint32_t m16, uint32_t m9, uint32_t m3, + uint32_t m13, uint32_t m6) +{ + return p1(m16 ^ m9 ^ rol32(m3, 15)) ^ rol32(m13, 7) ^ m6; +} + +void HELPER(vsm3me_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr, + CPURISCVState *env, uint32_t desc) +{ + uint32_t esz = memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW)); + uint32_t total_elems = vext_get_total_elems(env, desc, esz); + uint32_t vta = vext_vta(desc); + uint32_t *vd = vd_vptr; + uint32_t *vs1 = vs1_vptr; + uint32_t *vs2 = vs2_vptr; + + if (env->vl % 8 != 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (int i = env->vstart / 8; i < env->vl / 8; i++) { + uint32_t w[24]; + for (int j = 0; j < 8; j++) { + w[j] = bswap32(vs1[H4((i * 8) + j)]); + w[j + 8] = bswap32(vs2[H4((i * 8) + j)]); + } + for (int j = 0; j < 8; j++) { + w[j + 16] = + zvksh_w(w[j], w[j + 7], w[j + 13], w[j + 3], w[j + 10]); + } + for (int j = 0; j < 8; j++) { + vd[(i * 8) + j] = bswap32(w[H4(j + 16)]); + } + } + vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); + env->vstart = 0; +} -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:42:39 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIW7j-0003v0-7Q for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:42:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIW7h-0003ue-TT for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:42:37 -0500 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIW7f-0000BI-Cw for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:42:37 -0500 Received: by mail-ej1-x631.google.com with SMTP id v6so6227130ejg.6 for ; Thu, 19 Jan 2023 06:42:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; 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Thu, 19 Jan 2023 06:42:33 -0800 (PST) MIME-Version: 1.0 References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-5-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-5-armbru@redhat.com> From: Warner Losh Date: Thu, 19 Jan 2023 07:42:46 -0700 Message-ID: Subject: Re: [PATCH v4 04/19] bsd-user: Clean up includes To: Markus Armbruster Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Content-Type: multipart/alternative; boundary="000000000000763fdf05f29ef11f" Received-SPF: none client-ip=2a00:1450:4864:20::631; envelope-from=wlosh@bsdimp.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:42:38 -0000 --000000000000763fdf05f29ef11f Content-Type: text/plain; charset="UTF-8" On Thu, Jan 19, 2023 at 12:00 AM Markus Armbruster wrote: > Clean up includes so that osdep.h is included first and headers > which it implies are not included manually. > > This commit was created with scripts/clean-includes. > > Signed-off-by: Markus Armbruster > --- > bsd-user/bsd-proc.h | 4 ---- > bsd-user/qemu.h | 1 - > bsd-user/arm/signal.c | 1 + > bsd-user/arm/target_arch_cpu.c | 2 ++ > bsd-user/freebsd/os-sys.c | 1 + > bsd-user/i386/signal.c | 1 + > bsd-user/i386/target_arch_cpu.c | 3 +-- > bsd-user/main.c | 4 +--- > bsd-user/strace.c | 1 - > bsd-user/x86_64/signal.c | 1 + > bsd-user/x86_64/target_arch_cpu.c | 3 +-- > 11 files changed, 9 insertions(+), 13 deletions(-) > > diff --git a/bsd-user/bsd-proc.h b/bsd-user/bsd-proc.h > index 68b66e571d..a1061bffb8 100644 > --- a/bsd-user/bsd-proc.h > +++ b/bsd-user/bsd-proc.h > @@ -20,11 +20,7 @@ > #ifndef BSD_PROC_H_ > #define BSD_PROC_H_ > > -#include > -#include > -#include > #include > Did you test this on FreeBSD 12? FreeBSD 13 has started to climb the hill where all includes are independent, but much of that hasn't been merged to 12 yet. sys/types.h, at least, is documented as a prereq for both sys/stat.h and sys/resource.h. I know many of these are in os-dep.h, and I've had trouble in the bsd-user fork with that and the layout of the code which has arguably way too much in the .h files. Also, why didn't you move sys/resource.h and other such files to os-dep.h? I'm struggling to understand the rules around what is or isn't included where? > -#include > > /* exit(2) */ > static inline abi_long do_bsd_exit(void *cpu_env, abi_long arg1) > diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h > index be6105385e..0ceecfb6df 100644 > --- a/bsd-user/qemu.h > +++ b/bsd-user/qemu.h > @@ -17,7 +17,6 @@ > #ifndef QEMU_H > #define QEMU_H > > -#include "qemu/osdep.h" > #include "cpu.h" > #include "qemu/units.h" > #include "exec/cpu_ldst.h" > diff --git a/bsd-user/arm/signal.c b/bsd-user/arm/signal.c > index 2b1dd745d1..9734407543 100644 > --- a/bsd-user/arm/signal.c > +++ b/bsd-user/arm/signal.c > @@ -17,6 +17,7 @@ > * along with this program; if not, see . > */ > > +#include "qemu/osdep.h" > #include "qemu.h" > > /* > diff --git a/bsd-user/arm/target_arch_cpu.c > b/bsd-user/arm/target_arch_cpu.c > index 02bf9149d5..fe38ae2210 100644 > --- a/bsd-user/arm/target_arch_cpu.c > +++ b/bsd-user/arm/target_arch_cpu.c > @@ -16,6 +16,8 @@ > * You should have received a copy of the GNU General Public License > * along with this program; if not, see . > */ > + > +#include "qemu/osdep.h" > #include "target_arch.h" > > void target_cpu_set_tls(CPUARMState *env, target_ulong newtls) > diff --git a/bsd-user/freebsd/os-sys.c b/bsd-user/freebsd/os-sys.c > index 309e27b9d6..1676ec10f8 100644 > --- a/bsd-user/freebsd/os-sys.c > +++ b/bsd-user/freebsd/os-sys.c > @@ -17,6 +17,7 @@ > * along with this program; if not, see . > */ > > +#include "qemu/osdep.h" > #include "qemu.h" > #include "target_arch_sysarch.h" > > diff --git a/bsd-user/i386/signal.c b/bsd-user/i386/signal.c > index 5dd975ce56..a3131047b8 100644 > --- a/bsd-user/i386/signal.c > +++ b/bsd-user/i386/signal.c > @@ -17,6 +17,7 @@ > * along with this program; if not, see . > */ > > +#include "qemu/osdep.h" > #include "qemu.h" > > /* > diff --git a/bsd-user/i386/target_arch_cpu.c > b/bsd-user/i386/target_arch_cpu.c > index d349e45299..2a3af2ddef 100644 > --- a/bsd-user/i386/target_arch_cpu.c > +++ b/bsd-user/i386/target_arch_cpu.c > @@ -17,9 +17,8 @@ > * along with this program; if not, see . > */ > > -#include > - > #include "qemu/osdep.h" > + > #include "cpu.h" > #include "qemu.h" > #include "qemu/timer.h" > diff --git a/bsd-user/main.c b/bsd-user/main.c > index 6f09180d65..41290e16f9 100644 > --- a/bsd-user/main.c > +++ b/bsd-user/main.c > @@ -18,12 +18,10 @@ > * along with this program; if not, see . > */ > > -#include > -#include > +#include "qemu/osdep.h" > #include > #include > > -#include "qemu/osdep.h" > #include "qemu/help-texts.h" > #include "qemu/units.h" > #include "qemu/accel.h" > diff --git a/bsd-user/strace.c b/bsd-user/strace.c > index a77d10dd6b..96499751eb 100644 > --- a/bsd-user/strace.c > +++ b/bsd-user/strace.c > @@ -20,7 +20,6 @@ > #include > #include > #include > -#include > > #include "qemu.h" > > diff --git a/bsd-user/x86_64/signal.c b/bsd-user/x86_64/signal.c > index c3875bc4c6..46cb865180 100644 > --- a/bsd-user/x86_64/signal.c > +++ b/bsd-user/x86_64/signal.c > @@ -16,6 +16,7 @@ > * along with this program; if not, see . > */ > > +#include "qemu/osdep.h" > #include "qemu.h" > > /* > diff --git a/bsd-user/x86_64/target_arch_cpu.c > b/bsd-user/x86_64/target_arch_cpu.c > index be7bd10720..1d32f18907 100644 > --- a/bsd-user/x86_64/target_arch_cpu.c > +++ b/bsd-user/x86_64/target_arch_cpu.c > @@ -17,9 +17,8 @@ > * along with this program; if not, see . > */ > > -#include > - > #include "qemu/osdep.h" > + > #include "cpu.h" > #include "qemu.h" > #include "qemu/timer.h" > I suppose these are fine. How do I run the cleanup script? I have 2x the number of files not upstream in the bsd-user fork that I'd like to cleanup as well and they are likely a bigger mess and I'll just upstream them in the messy state unless I understand how to keep the neat :). Warner --000000000000763fdf05f29ef11f Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Thu, Jan 19, 2023 at 12:00 AM Mark= us Armbruster <armbru@redhat.com> wrote:
Cle= an up includes so that osdep.h is included first and headers
which it implies are not included manually.

This commit was created with scripts/clean-includes.

Signed-off-by: Markus Armbruster <
armbru@redhat.com>
---
=C2=A0bsd-user/bsd-proc.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0| 4 ----
=C2=A0bsd-user/qemu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0| 1 -
=C2=A0bsd-user/arm/signal.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= | 1 +
=C2=A0bsd-user/arm/target_arch_cpu.c=C2=A0 =C2=A0 | 2 ++
=C2=A0bsd-user/freebsd/os-sys.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 1 +
=C2=A0bsd-user/i386/signal.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | 1 +=
=C2=A0bsd-user/i386/target_arch_cpu.c=C2=A0 =C2=A0| 3 +--
=C2=A0bsd-user/main.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0| 4 +---
=C2=A0bsd-user/strace.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0| 1 -
=C2=A0bsd-user/x86_64/signal.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 | 1 +
=C2=A0bsd-user/x86_64/target_arch_cpu.c | 3 +--
=C2=A011 files changed, 9 insertions(+), 13 deletions(-)

diff --git a/bsd-user/bsd-proc.h b/bsd-user/bsd-proc.h
index 68b66e571d..a1061bffb8 100644
--- a/bsd-user/bsd-proc.h
+++ b/bsd-user/bsd-proc.h
@@ -20,11 +20,7 @@
=C2=A0#ifndef BSD_PROC_H_
=C2=A0#define BSD_PROC_H_

-#include <sys/types.h>
-#include <sys/stat.h>
-#include <sys/time.h>
=C2=A0#include <sys/resource.h>

D= id you test this on FreeBSD 12? FreeBSD 13 has started to climb the hill wh= ere all includes are independent, but much of that hasn't been merged t= o 12 yet. sys/types.h, at least, is documented as a prereq for both sys/sta= t.h and sys/resource.h.

I know many of these are i= n os-dep.h, and I've had trouble in the bsd-user fork with that and the= layout of the code which has arguably way too much in the .h files.
<= div>
Also, why didn't you move sys/resource.h and other s= uch files to os-dep.h? I'm struggling to understand the rules around wh= at is or isn't included where?
=C2=A0
-#include <unistd.h>

=C2=A0/* exit(2) */
=C2=A0static inline abi_long do_bsd_exit(void *cpu_env, abi_long arg1)
diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h
index be6105385e..0ceecfb6df 100644
--- a/bsd-user/qemu.h
+++ b/bsd-user/qemu.h
@@ -17,7 +17,6 @@
=C2=A0#ifndef QEMU_H
=C2=A0#define QEMU_H

-#include "qemu/osdep.h"
=C2=A0#include "cpu.h"
=C2=A0#include "qemu/units.h"
=C2=A0#include "exec/cpu_ldst.h"
diff --git a/bsd-user/arm/signal.c b/bsd-user/arm/signal.c
index 2b1dd745d1..9734407543 100644
--- a/bsd-user/arm/signal.c
+++ b/bsd-user/arm/signal.c
@@ -17,6 +17,7 @@
=C2=A0 *=C2=A0 along with this program; if not, see <http://www.gnu.o= rg/licenses/>.
=C2=A0 */

+#include "qemu/osdep.h"
=C2=A0#include "qemu.h"

=C2=A0/*
diff --git a/bsd-user/arm/target_arch_cpu.c b/bsd-user/arm/target_arch_cpu.= c
index 02bf9149d5..fe38ae2210 100644
--- a/bsd-user/arm/target_arch_cpu.c
+++ b/bsd-user/arm/target_arch_cpu.c
@@ -16,6 +16,8 @@
=C2=A0 *=C2=A0 You should have received a copy of the GNU General Public Li= cense
=C2=A0 *=C2=A0 along with this program; if not, see <http://www.gnu.o= rg/licenses/>.
=C2=A0 */
+
+#include "qemu/osdep.h"
=C2=A0#include "target_arch.h"

=C2=A0void target_cpu_set_tls(CPUARMState *env, target_ulong newtls)
diff --git a/bsd-user/freebsd/os-sys.c b/bsd-user/freebsd/os-sys.c
index 309e27b9d6..1676ec10f8 100644
--- a/bsd-user/freebsd/os-sys.c
+++ b/bsd-user/freebsd/os-sys.c
@@ -17,6 +17,7 @@
=C2=A0 *=C2=A0 along with this program; if not, see <http://www.gnu.o= rg/licenses/>.
=C2=A0 */

+#include "qemu/osdep.h"
=C2=A0#include "qemu.h"
=C2=A0#include "target_arch_sysarch.h"

diff --git a/bsd-user/i386/signal.c b/bsd-user/i386/signal.c
index 5dd975ce56..a3131047b8 100644
--- a/bsd-user/i386/signal.c
+++ b/bsd-user/i386/signal.c
@@ -17,6 +17,7 @@
=C2=A0 *=C2=A0 along with this program; if not, see <http://www.gnu.o= rg/licenses/>.
=C2=A0 */

+#include "qemu/osdep.h"
=C2=A0#include "qemu.h"

=C2=A0/*
diff --git a/bsd-user/i386/target_arch_cpu.c b/bsd-user/i386/target_arch_cp= u.c
index d349e45299..2a3af2ddef 100644
--- a/bsd-user/i386/target_arch_cpu.c
+++ b/bsd-user/i386/target_arch_cpu.c
@@ -17,9 +17,8 @@
=C2=A0 *=C2=A0 along with this program; if not, see <http://www.gnu.o= rg/licenses/>.
=C2=A0 */

-#include <sys/types.h>
-
=C2=A0#include "qemu/osdep.h"
+
=C2=A0#include "cpu.h"
=C2=A0#include "qemu.h"
=C2=A0#include "qemu/timer.h"
diff --git a/bsd-user/main.c b/bsd-user/main.c
index 6f09180d65..41290e16f9 100644
--- a/bsd-user/main.c
+++ b/bsd-user/main.c
@@ -18,12 +18,10 @@
=C2=A0 *=C2=A0 along with this program; if not, see <http://www.gnu.o= rg/licenses/>.
=C2=A0 */

-#include <sys/types.h>
-#include <sys/time.h>
+#include "qemu/osdep.h"
=C2=A0#include <sys/resource.h>
=C2=A0#include <sys/sysctl.h>

-#include "qemu/osdep.h"
=C2=A0#include "qemu/help-texts.h"
=C2=A0#include "qemu/units.h"
=C2=A0#include "qemu/accel.h"
diff --git a/bsd-user/strace.c b/bsd-user/strace.c
index a77d10dd6b..96499751eb 100644
--- a/bsd-user/strace.c
+++ b/bsd-user/strace.c
@@ -20,7 +20,6 @@
=C2=A0#include <sys/select.h>
=C2=A0#include <sys/syscall.h>
=C2=A0#include <sys/ioccom.h>
-#include <ctype.h>

=C2=A0#include "qemu.h"

diff --git a/bsd-user/x86_64/signal.c b/bsd-user/x86_64/signal.c
index c3875bc4c6..46cb865180 100644
--- a/bsd-user/x86_64/signal.c
+++ b/bsd-user/x86_64/signal.c
@@ -16,6 +16,7 @@
=C2=A0 *=C2=A0 along with this program; if not, see <http://www.gnu.o= rg/licenses/>.
=C2=A0 */

+#include "qemu/osdep.h"
=C2=A0#include "qemu.h"

=C2=A0/*
diff --git a/bsd-user/x86_64/target_arch_cpu.c b/bsd-user/x86_64/target_arc= h_cpu.c
index be7bd10720..1d32f18907 100644
--- a/bsd-user/x86_64/target_arch_cpu.c
+++ b/bsd-user/x86_64/target_arch_cpu.c
@@ -17,9 +17,8 @@
=C2=A0 *=C2=A0 along with this program; if not, see <http://www.gnu.o= rg/licenses/>.
=C2=A0 */

-#include <sys/types.h>
-
=C2=A0#include "qemu/osdep.h"
+
=C2=A0#include "cpu.h"
=C2=A0#include "qemu.h"
=C2=A0#include "qemu/timer.h"

I suppose these are fine. How do I run the cleanup script? I have 2x the n= umber of files not upstream in the bsd-user fork that I'd like to clean= up as well and they are likely a bigger mess and I'll just upstream the= m in the messy state unless I understand how to keep the neat :).
=

Warner
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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id d9-20020a1709063ec900b007bd9e683639sm16283259ejj.130.2023.01.19.06.49.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 06:49:35 -0800 (PST) Date: Thu, 19 Jan 2023 15:49:34 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Alistair Francis , Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Subject: Re: [PATCH v5 2/2] riscv: Allow user to set the satp mode Message-ID: <20230119144934.ikmij2b7m7yeqwtz@orel> References: <20230113103453.42776-1-alexghiti@rivosinc.com> <20230113103453.42776-3-alexghiti@rivosinc.com> <20230117163138.jze47hjeeuwu2k4j@orel> <20230118121916.6aqj57leen72z5tz@orel> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=ajones@ventanamicro.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:49:40 -0000 On Thu, Jan 19, 2023 at 02:00:27PM +0100, Alexandre Ghiti wrote: > Hi Alistair, Andrew, > > On Thu, Jan 19, 2023 at 1:25 AM Alistair Francis wrote: > > > > On Wed, Jan 18, 2023 at 10:19 PM Andrew Jones wrote: > > > > > > On Wed, Jan 18, 2023 at 10:28:46AM +1000, Alistair Francis wrote: > > > > On Wed, Jan 18, 2023 at 2:32 AM Andrew Jones wrote: > > > > > > > > > > On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote: > > > ... > > > > > > + > > > > > > + /* Get rid of 32-bit/64-bit incompatibility */ > > > > > > + for (int i = 0; i < 16; ++i) { > > > > > > + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > > > > > > > > > > If we ever define mode=1 for rv64, then 'sv32=on' will be incorrectly > > > > > accepted as an alias. I think we should simply not define the sv32 > > > > > property for rv64 nor the rv64-only modes for rv32. So, down in > > > > > riscv_add_satp_mode_properties() we can add some > > > > > > > > > > #if defined(TARGET_RISCV32) > > > > > ... > > > > > #elif defined(TARGET_RISCV64) > > > > > ... > > > > > #endif > > > > > > > > Do not add any #if defined(TARGET_RISCV32) to QEMU. > > > > > > > > We are aiming for the riscv64-softmmu to be able to emulate 32-bit > > > > CPUs and compile time macros are the wrong solution here. Instead you > > > > can get the xlen of the hart and use that. > > > > > > > > > > Does this mean we want to be able to do the following? > > > > > > qemu-system-riscv64 -cpu rv32,sv32=on ... > > > > That's the plan > > > > > > > > If so, then can we move the object_property_add() for sv32 to > > > rv32_base_cpu_init() and the rest to rv64_base_cpu_init()? > > > Currently, that would be doing the same thing as proposed above, > > > since those functions are under TARGET_RISCV* defines, but I guess > > > the object_property_add()'s would then be in more or less the right > > > places for when the 32-bit emulation support work is started. > > > > Sounds like a good idea :) > > What about riscv_any_cpu_init and riscv_host_cpu_init? riscv_host_cpu_init depends on KVM support, so we actually don't need to add the properties in this patch at all. That's later work. I'm not real clear as to what riscv_any_cpu_init is. It looks like a cpu type that tries to enable all supported standard extensions. Maybe we need a patch like below first and then add the sv* properties in the same way we will for the rv*_base_cpu_init functions. Thanks, drew diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cc75ca76677f..a2987205991e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -229,19 +229,15 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) env->vext_ver = vext_ver; } -static void riscv_any_cpu_init(Object *obj) -{ - CPURISCVState *env = &RISCV_CPU(obj)->env; -#if defined(TARGET_RISCV32) - set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); -#elif defined(TARGET_RISCV64) - set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); -#endif - set_priv_version(env, PRIV_VERSION_1_12_0); - register_cpu_props(DEVICE(obj)); -} - #if defined(TARGET_RISCV64) +static void rv64_any_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_priv_version(env, PRIV_VERSION_1_12_0); + register_cpu_props(DEVICE(obj)); +} + static void rv64_base_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; @@ -285,6 +281,14 @@ static void rv128_base_cpu_init(Object *obj) set_priv_version(env, PRIV_VERSION_1_12_0); } #else +static void rv32_any_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_priv_version(env, PRIV_VERSION_1_12_0); + register_cpu_props(DEVICE(obj)); +} + static void rv32_base_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; @@ -1285,17 +1289,18 @@ static const TypeInfo riscv_cpu_type_infos[] = { .class_size = sizeof(RISCVCPUClass), .class_init = riscv_cpu_class_init, }, - DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), #if defined(CONFIG_KVM) DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), #endif #if defined(TARGET_RISCV32) + DEFINE_CPU(TYPE_RISCV_CPU_ANY, rv32_any_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), #elif defined(TARGET_RISCV64) + DEFINE_CPU(TYPE_RISCV_CPU_ANY, rv64_any_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), From MAILER-DAEMON Thu Jan 19 09:54:35 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIWJH-0003eK-1C for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:54:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIWJF-0003e3-Fk for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:54:33 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIWJD-0002cG-Se for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:54:33 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1S-007gSL-Ab; Thu, 19 Jan 2023 14:36:11 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Max Chou Subject: [RFC PATCH 36/39] crypto: Add SM4 constant parameter CK. Date: Thu, 19 Jan 2023 14:35:25 +0000 Message-Id: <20230119143528.1290950-37-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:54:33 -0000 From: Max Chou Signed-off-by: Max Chou Reviewed-by: Frank Chang --- crypto/sm4.c | 10 ++++++++++ include/crypto/sm4.h | 1 + 2 files changed, 11 insertions(+) diff --git a/crypto/sm4.c b/crypto/sm4.c index 9f0cd452c7..2987306cf7 100644 --- a/crypto/sm4.c +++ b/crypto/sm4.c @@ -47,3 +47,13 @@ uint8_t const sm4_sbox[] = { 0x79, 0xee, 0x5f, 0x3e, 0xd7, 0xcb, 0x39, 0x48, }; +uint32_t const sm4_ck[] = { + 0x00070e15, 0x1c232a31, 0x383f464d, 0x545b6269, + 0x70777e85, 0x8c939aa1, 0xa8afb6bd, 0xc4cbd2d9, + 0xe0e7eef5, 0xfc030a11, 0x181f262d, 0x343b4249, + 0x50575e65, 0x6c737a81, 0x888f969d, 0xa4abb2b9, + 0xc0c7ced5, 0xdce3eaf1, 0xf8ff060d, 0x141b2229, + 0x30373e45, 0x4c535a61, 0x686f767d, 0x848b9299, + 0xa0a7aeb5, 0xbcc3cad1, 0xd8dfe6ed, 0xf4fb0209, + 0x10171e25, 0x2c333a41, 0x484f565d, 0x646b7279 +}; diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h index 33478562a4..d0df6e473c 100644 --- a/include/crypto/sm4.h +++ b/include/crypto/sm4.h @@ -9,5 +9,6 @@ ) extern const uint8_t sm4_sbox[256]; +extern const uint32_t sm4_ck[32]; #endif -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:54:40 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIWJM-0003gV-9n for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:54:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIWJK-0003f0-UU for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:54:38 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIWJI-0002f3-HN for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:54:38 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1R-007gSL-P5; Thu, 19 Jan 2023 14:36:10 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence Hunter Subject: [RFC PATCH 34/39] target/riscv: expose zvkg cpu property Date: Thu, 19 Jan 2023 14:35:23 +0000 Message-Id: <20230119143528.1290950-35-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:54:39 -0000 Signed-off-by: Lawrence Hunter --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8045a7cec0..4bd404faa0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1077,6 +1077,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), DEFINE_PROP_BOOL("zvkb", RISCVCPU, cfg.ext_zvkb, false), + DEFINE_PROP_BOOL("zvkg", RISCVCPU, cfg.ext_zvkg, false), DEFINE_PROP_BOOL("zvknha", RISCVCPU, cfg.ext_zvknha, false), DEFINE_PROP_BOOL("zvknhb", RISCVCPU, cfg.ext_zvknhb, false), DEFINE_PROP_BOOL("zvkns", RISCVCPU, cfg.ext_zvkns, false), -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:54:44 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIWJQ-0003iQ-4S for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:54:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIWJP-0003hw-0j for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:54:43 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIWJN-0002g0-AM for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:54:42 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1Q-007gSL-Aw; Thu, 19 Jan 2023 14:36:09 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Kiran Ostrolenk Subject: [RFC PATCH 30/39] target/riscv: Add vsm3c.vi decoding, translation and execution support Date: Thu, 19 Jan 2023 14:35:19 +0000 Message-Id: <20230119143528.1290950-31-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:54:43 -0000 From: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk --- target/riscv/helper.h | 1 + target/riscv/insn32.decode | 1 + target/riscv/insn_trans/trans_rvzvksh.c.inc | 8 ++ target/riscv/vcrypto_helper.c | 90 +++++++++++++++++++++ 4 files changed, 100 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 36e0d8eff3..a82103ead9 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1198,3 +1198,4 @@ DEF_HELPER_5(vsha2ch_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsha2cl_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 671614e354..4a50114e92 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -929,3 +929,4 @@ vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 # *** RV64 Zvksh vector crypto extensions *** vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvksh.c.inc b/target/riscv/insn_trans/trans_rvzvksh.c.inc index 2956618d7e..e9b8f9a23f 100644 --- a/target/riscv/insn_trans/trans_rvzvksh.c.inc +++ b/target/riscv/insn_trans/trans_rvzvksh.c.inc @@ -9,4 +9,12 @@ static inline bool vsm3me_check(DisasContext *s, arg_rmrr *a) return vsm3_check(s) && vext_check_sss(s, a->rd, a->rs1, a->rs2, a->vm); } + +static inline bool vsm3c_check(DisasContext *s, arg_rmrr *a) +{ + return vsm3_check(s) && a->rs1 < 32 && + vext_check_ss(s, a->rd, a->rs2, a->vm); +} + GEN_VV_UNMASKED_TRANS(vsm3me_vv, vsm3me_check) +GEN_VI_UNMASKED_TRANS(vsm3c_vi, vsm3c_check) diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 4dd5920aa4..478e652c9b 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -737,3 +737,93 @@ void HELPER(vsm3me_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr, vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); env->vstart = 0; } + +static inline uint32_t ff1(uint32_t x, uint32_t y, uint32_t z) +{ + return x ^ y ^ z; +}; +static inline uint32_t ff2(uint32_t x, uint32_t y, uint32_t z) +{ + return (x & y) | (x & z) | (y & z); +}; +static inline uint32_t ff_j(uint32_t x, uint32_t y, uint32_t z, uint32_t j) +{ + return (j <= 15) ? ff1(x, y, z) : ff2(x, y, z); +}; +static inline uint32_t gg1(uint32_t x, uint32_t y, uint32_t z) +{ + return x ^ y ^ z; +}; +static inline uint32_t gg2(uint32_t x, uint32_t y, uint32_t z) +{ + return (x & y) | (~x & z); +}; +static inline uint32_t gg_j(uint32_t x, uint32_t y, uint32_t z, uint32_t j) +{ + return (j <= 15) ? gg1(x, y, z) : gg2(x, y, z); +}; +static inline uint32_t t_j(uint32_t j) +{ + return (j <= 15) ? 0x79cc4519 : 0x7a879d8a; +}; +static inline uint32_t p_0(uint32_t x) +{ + return x ^ rol32(x, 9) ^ rol32(x, 17); +}; +static void sm3c(uint32_t *vd, uint32_t *vs1, uint32_t *vs2, uint32_t uimm) +{ + uint32_t x0, x1; + uint32_t j; + uint32_t ss1, ss2, tt1, tt2; + x0 = vs2[0] ^ vs2[4]; + x1 = vs2[1] ^ vs2[5]; + j = 2 * uimm; + ss1 = rol32(rol32(vs1[0], 12) + vs1[4] + rol32(t_j(j), j % 32), 7); + ss2 = ss1 ^ rol32(vs1[0], 12); + tt1 = ff_j(vs1[0], vs1[1], vs1[2], j) + vs1[3] + ss2 + x0; + tt2 = gg_j(vs1[4], vs1[5], vs1[6], j) + vs1[7] + ss1 + vs2[0]; + vs1[3] = vs1[2]; + vd[3] = rol32(vs1[1], 9); + vs1[1] = vs1[0]; + vd[1] = tt1; + vs1[7] = vs1[6]; + vd[7] = rol32(vs1[5], 19); + vs1[5] = vs1[4]; + vd[5] = p_0(tt2); + j = 2 * uimm + 1; + ss1 = rol32(rol32(vd[1], 12) + vd[5] + rol32(t_j(j), j % 32), 7); + ss2 = ss1 ^ rol32(vd[1], 12); + tt1 = ff_j(vd[1], vs1[1], vd[3], j) + vs1[3] + ss2 + x1; + tt2 = gg_j(vd[5], vs1[5], vd[7], j) + vs1[7] + ss1 + vs2[1]; + vd[2] = rol32(vs1[1], 9); + vd[0] = tt1; + vd[6] = rol32(vs1[5], 19); + vd[4] = p_0(tt2); +} +void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, + CPURISCVState *env, uint32_t desc) +{ + uint32_t esz = memop_size(FIELD_EX64(env->vtype, VTYPE, VSEW)); + uint32_t total_elems = vext_get_total_elems(env, desc, esz); + uint32_t vta = vext_vta(desc); + uint32_t *vd = vd_vptr; + uint32_t *vs2 = vs2_vptr; + uint32_t v1[8], v2[8], v3[8]; + + if (env->vl % 8 != 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (int i = env->vstart / 8; i < env->vl / 8; i++) { + for (int k = 0; k < 8; k++) { + v2[k] = bswap32(vd[H4(i * 8 + k)]); + v3[k] = bswap32(vs2[H4(i * 8 + k)]); + } + sm3c(v1, v2, v3, uimm); + for (int k = 0; k < 8; k++) { + vd[i * 8 + k] = bswap32(v1[H4(k)]); + } + } + vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); + env->vstart = 0; +} -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:54:48 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIWJU-0003jP-8t for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:54:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIWJT-0003jA-94 for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:54:47 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIWJR-0002gI-8s for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:54:47 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1S-007gSL-S3; Thu, 19 Jan 2023 14:36:11 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Max Chou Subject: [RFC PATCH 38/39] target/riscv: Add Zvksed support Date: Thu, 19 Jan 2023 14:35:27 +0000 Message-Id: <20230119143528.1290950-39-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:54:47 -0000 From: Max Chou - add vsm4k, vsm4r instructions Signed-off-by: Max Chou Reviewed-by: Frank Chang [lawrence.hunter@codethink.co.uk: Moved SM4 functions from crypto_helper.c to vcrypto_helper.c] [nazar.kazakov@codethink.co.uk: Added alignment checks, refactored code to use macros, and minor style changes] --- target/riscv/crypto_helper.c | 1 + target/riscv/helper.h | 4 + target/riscv/insn32.decode | 5 + target/riscv/insn_trans/trans_rvzvksed.c.inc | 38 +++++ target/riscv/translate.c | 1 + target/riscv/vcrypto_helper.c | 139 +++++++++++++++++++ 6 files changed, 188 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzvksed.c.inc diff --git a/target/riscv/crypto_helper.c b/target/riscv/crypto_helper.c index 2ef30281b1..760ce22570 100644 --- a/target/riscv/crypto_helper.c +++ b/target/riscv/crypto_helper.c @@ -23,6 +23,7 @@ #include "exec/helper-proto.h" #include "crypto/aes.h" #include "crypto/sm4.h" +#include "vector_internals.h" #define AES_XTIME(a) \ ((a << 1) ^ ((a & 0x80) ? 0x1b : 0)) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 6272294d50..07fad2568c 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1201,3 +1201,7 @@ DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32) DEF_HELPER_5(vghmac_vv, void, ptr, ptr, ptr, env, i32) + +DEF_HELPER_5(vsm4k_vi, void, ptr, ptr, i32, env, i32) +DEF_HELPER_4(vsm4r_vv, void, ptr, ptr, env, i32) +DEF_HELPER_4(vsm4r_vs, void, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index ff044f8288..3e83884f43 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -933,3 +933,8 @@ vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1 # *** RV64 Zvkg vector crypto extension *** vghmac_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1 + +# *** RV64 Zvksed Standart Extension *** +vsm4k_vi 100001 1 ..... ..... 010 ..... 1110111 @r_vm_1 +vsm4r_vv 101000 1 ..... 10000 010 ..... 1110111 @r2_vm_1 +vsm4r_vs 101001 1 ..... 10000 010 ..... 1110111 @r2_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvksed.c.inc b/target/riscv/insn_trans/trans_rvzvksed.c.inc new file mode 100644 index 0000000000..1740f57c0a --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzvksed.c.inc @@ -0,0 +1,38 @@ +#define ZVKSED_EGS 4 + +static bool zvksed_check(DisasContext *s) +{ + return require_rvv(s) && + s->cfg_ptr->ext_zvksed == true && + vext_check_isa_ill(s) && + s->vstart % ZVKSED_EGS == 0 && + s->sew == MO_32; +} + +static bool vsm4k_vi_check(DisasContext *s, arg_rmrr *a) +{ + return zvksed_check(s) && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul) && + a->rs1 >= 0 && a->rs1 <= 7; +} + +GEN_VI_UNMASKED_TRANS(vsm4k_vi, vsm4k_vi_check) + +static bool vsm4r_vv_check(DisasContext *s, arg_rmr *a) +{ + return zvksed_check(s) && + require_align(a->rd, s->lmul) && + require_align(a->rs2, s->lmul); +} + +GEN_V_UNMASKED_TRANS(vsm4r_vv, vsm4r_vv_check) + +static bool vsm4r_vs_check(DisasContext *s, arg_rmr *a) +{ + return zvksed_check(s) && + !is_overlapped(a->rd, 1 << MAX(s->lmul, 0), a->rs2, 1) && + require_align(a->rd, s->lmul); +} + +GEN_V_UNMASKED_TRANS(vsm4r_vs, vsm4r_vs_check) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0bc1c9db65..2ffb1827c5 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1068,6 +1068,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_rvzvknh.c.inc" #include "insn_trans/trans_rvzvksh.c.inc" #include "insn_trans/trans_rvzvkg.c.inc" +#include "insn_trans/trans_rvzvksed.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index a309ac3f03..fd9fc3c6d7 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -4,6 +4,7 @@ #include "qemu/bswap.h" #include "cpu.h" #include "crypto/aes.h" +#include "crypto/sm4.h" #include "exec/memop.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -872,3 +873,141 @@ void HELPER(vghmac_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr, vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4); env->vstart = 0; } + +void HELPER(vsm4k_vi)(void *vd, void *vs2, uint32_t uimm5, + CPURISCVState *env, uint32_t desc) +{ + const uint32_t egs = 4; + uint32_t rnd = uimm5; + uint32_t group_start = env->vstart / egs; + uint32_t group_end = env->vl / egs; + uint32_t esz = sizeof(uint32_t); + uint32_t total_elems = vext_get_total_elems(env, desc, esz); + + if (env->vl % egs != 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (uint32_t i = group_start; i < group_end; ++i) { + uint32_t vstart = i * egs; + uint32_t vend = (i + 1) * egs; + uint32_t rk[4] = {0}; + uint32_t tmp[8] = {0}; + + for (uint32_t j = vstart; j < vend; ++j) { + rk[j - vstart] = *((uint32_t *)vs2 + H4(j)); + } + + for (uint32_t j = 0; j < egs; ++j) { + tmp[j] = rk[j]; + } + + for (uint32_t j = 0; j < egs; ++j) { + uint32_t b, s; + b = tmp[j + 1] ^ tmp[j + 2] ^ tmp[j + 3] ^ sm4_ck[rnd * 4 + j]; + + s = SM4_SBOXWORD(b); + + tmp[j + 4] = tmp[j] ^ (s ^ rol32(s, 13) ^ rol32(s, 23)); + } + + for (uint32_t j = vstart; j < vend; ++j) { + *((uint32_t *)vd + H4(j)) = tmp[egs + (j - vstart)]; + } + } + + env->vstart = 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz); +} + +static void do_sm4_round(uint32_t *rk, uint32_t *buf) +{ + const uint32_t egs = 4; + uint32_t s, b; + + for (uint32_t j = egs; j < egs * 2; ++j) { + b = buf[j - 3] ^ buf[j - 2] ^ buf[j - 1] ^ rk[j - 4]; + + s = SM4_SBOXWORD(b); + + buf[j] = buf[j - 4] ^ (s ^ rol32(s, 2) ^ rol32(s, 10) ^ + rol32(s, 18) ^ rol32(s, 24)); + } +} + +void HELPER(vsm4r_vv)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc) +{ + const uint32_t egs = 4; + uint32_t group_start = env->vstart / egs; + uint32_t group_end = env->vl / egs; + uint32_t esz = sizeof(uint32_t); + uint32_t total_elems = vext_get_total_elems(env, desc, esz); + + if (env->vl % egs != 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (uint32_t i = group_start; i < group_end; ++i) { + uint32_t vstart = i * egs; + uint32_t vend = (i + 1) * egs; + uint32_t rk[4] = {0}; + uint32_t tmp[8] = {0}; + + for (uint32_t j = vstart; j < vend; ++j) { + rk[j - vstart] = *((uint32_t *)vs2 + H4(j)); + } + + for (uint32_t j = vstart; j < vend; ++j) { + tmp[j - vstart] = *((uint32_t *)vd + H4(j)); + } + + do_sm4_round(rk, tmp); + + for (uint32_t j = vstart; j < vend; ++j) { + *((uint32_t *)vd + H4(j)) = tmp[egs + (j - vstart)]; + } + } + + env->vstart = 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz); +} + +void HELPER(vsm4r_vs)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc) +{ + const uint32_t egs = 4; + uint32_t group_start = env->vstart / egs; + uint32_t group_end = env->vl / egs; + uint32_t esz = sizeof(uint32_t); + uint32_t total_elems = vext_get_total_elems(env, desc, esz); + + if (env->vl % egs != 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (uint32_t i = group_start; i < group_end; ++i) { + uint32_t vstart = i * egs; + uint32_t vend = (i + 1) * egs; + uint32_t rk[4] = {0}; + uint32_t tmp[8] = {0}; + + for (uint32_t j = 0; j < egs; ++j) { + rk[j] = *((uint32_t *)vs2 + H4(j)); + } + + for (uint32_t j = vstart; j < vend; ++j) { + tmp[j - vstart] = *((uint32_t *)vd + H4(j)); + } + + do_sm4_round(rk, tmp); + + for (uint32_t j = vstart; j < vend; ++j) { + *((uint32_t *)vd + H4(j)) = tmp[egs + (j - vstart)]; + } + } + + env->vstart = 0; + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vext_vta(desc), env->vl * esz, total_elems * esz); +} -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:54:51 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIWJX-0003mD-Eu for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:54:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIWJW-0003lY-LE for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:54:50 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIWJU-0002gu-Um for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:54:50 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1S-007gSL-JO; Thu, 19 Jan 2023 14:36:11 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Max Chou Subject: [RFC PATCH 37/39] target/riscv: Add zvksed cfg property Date: Thu, 19 Jan 2023 14:35:26 +0000 Message-Id: <20230119143528.1290950-38-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:54:50 -0000 From: Max Chou Signed-off-by: Max Chou Reviewed-by: Frank Chang --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + 2 files changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4bd404faa0..d298c9bbfb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -105,6 +105,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zvknha, true, PRIV_VERSION_1_12_0, ext_zvknha), ISA_EXT_DATA_ENTRY(zvknhb, true, PRIV_VERSION_1_12_0, ext_zvknhb), ISA_EXT_DATA_ENTRY(zvkns, true, PRIV_VERSION_1_12_0, ext_zvkns), + ISA_EXT_DATA_ENTRY(zvksed, true, PRIV_VERSION_1_12_0, ext_zvksed), ISA_EXT_DATA_ENTRY(zvksh, true, PRIV_VERSION_1_12_0, ext_zvksh), ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b3b1174d74..89e9fd61da 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -466,6 +466,7 @@ struct RISCVCPUConfig { bool ext_zvknha; bool ext_zvknhb; bool ext_zvkns; + bool ext_zvksed; bool ext_zvksh; bool ext_zmmul; bool ext_smaia; -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:54:54 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIWJa-0003n9-JF for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:54:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIWJZ-0003mv-RI for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:54:53 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIWJY-0002hk-F0 for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:54:53 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1S-007gSL-21; Thu, 19 Jan 2023 14:36:10 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Max Chou Subject: [RFC PATCH 35/39] crypto: Move SM4_SBOXWORD from target/riscv Date: Thu, 19 Jan 2023 14:35:24 +0000 Message-Id: <20230119143528.1290950-36-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:54:54 -0000 From: Max Chou - Share SM4_SBOXWORD between target/riscv and target/arm. Signed-off-by: Max Chou Reviewed-by: Frank Chang --- include/crypto/sm4.h | 7 +++++++ target/arm/crypto_helper.c | 10 ++-------- 2 files changed, 9 insertions(+), 8 deletions(-) diff --git a/include/crypto/sm4.h b/include/crypto/sm4.h index 9bd3ebc62e..33478562a4 100644 --- a/include/crypto/sm4.h +++ b/include/crypto/sm4.h @@ -1,6 +1,13 @@ #ifndef QEMU_SM4_H #define QEMU_SM4_H +#define SM4_SBOXWORD(WORD) ( \ + sm4_sbox[((WORD) >> 24) & 0xff] << 24 | \ + sm4_sbox[((WORD) >> 16) & 0xff] << 16 | \ + sm4_sbox[((WORD) >> 8) & 0xff] << 8 | \ + sm4_sbox[((WORD) >> 0) & 0xff] << 0 \ +) + extern const uint8_t sm4_sbox[256]; #endif diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c index d28690321f..4e97af9879 100644 --- a/target/arm/crypto_helper.c +++ b/target/arm/crypto_helper.c @@ -707,10 +707,7 @@ static void do_crypto_sm4e(uint64_t *rd, uint64_t *rn, uint64_t *rm) CR_ST_WORD(d, (i + 3) % 4) ^ CR_ST_WORD(n, i); - t = sm4_sbox[t & 0xff] | - sm4_sbox[(t >> 8) & 0xff] << 8 | - sm4_sbox[(t >> 16) & 0xff] << 16 | - sm4_sbox[(t >> 24) & 0xff] << 24; + t = SM4_SBOXWORD(t); CR_ST_WORD(d, i) ^= t ^ rol32(t, 2) ^ rol32(t, 10) ^ rol32(t, 18) ^ rol32(t, 24); @@ -744,10 +741,7 @@ static void do_crypto_sm4ekey(uint64_t *rd, uint64_t *rn, uint64_t *rm) CR_ST_WORD(d, (i + 3) % 4) ^ CR_ST_WORD(m, i); - t = sm4_sbox[t & 0xff] | - sm4_sbox[(t >> 8) & 0xff] << 8 | - sm4_sbox[(t >> 16) & 0xff] << 16 | - sm4_sbox[(t >> 24) & 0xff] << 24; + t = SM4_SBOXWORD(t); CR_ST_WORD(d, i) ^= t ^ rol32(t, 13) ^ rol32(t, 23); } -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:55:00 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIWJf-0003oO-Nw for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:55:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIWJd-0003nq-6i for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:54:57 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIWJb-0002hy-Ps for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:54:56 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1T-007gSL-5y; Thu, 19 Jan 2023 14:36:12 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Max Chou Subject: [RFC PATCH 39/39] target/riscv: Expose Zvksed property Date: Thu, 19 Jan 2023 14:35:28 +0000 Message-Id: <20230119143528.1290950-40-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:54:57 -0000 From: Max Chou Signed-off-by: Max Chou Reviewed-by: Frank Chang --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d298c9bbfb..0a707a4415 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1082,6 +1082,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("zvknha", RISCVCPU, cfg.ext_zvknha, false), DEFINE_PROP_BOOL("zvknhb", RISCVCPU, cfg.ext_zvknhb, false), DEFINE_PROP_BOOL("zvkns", RISCVCPU, cfg.ext_zvkns, false), + DEFINE_PROP_BOOL("zvksed", RISCVCPU, cfg.ext_zvksed, false), DEFINE_PROP_BOOL("zvksh", RISCVCPU, cfg.ext_zvksh, false), /* Vendor-specific custom extensions */ -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:55:03 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIWJj-0003s2-6R for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:55:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIWJh-0003oj-BL for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:55:01 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIWJg-0002iV-1t for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:55:01 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1R-007gSL-4q; Thu, 19 Jan 2023 14:36:10 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence Hunter Subject: [RFC PATCH 32/39] target/riscv: add zvkg cpu property Date: Thu, 19 Jan 2023 14:35:21 +0000 Message-Id: <20230119143528.1290950-33-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:55:01 -0000 Signed-off-by: Lawrence Hunter --- target/riscv/cpu.c | 1 + target/riscv/cpu.h | 1 + 2 files changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c0c2d70abf..8045a7cec0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -101,6 +101,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), ISA_EXT_DATA_ENTRY(zvkb, true, PRIV_VERSION_1_12_0, ext_zvkb), + ISA_EXT_DATA_ENTRY(zvkg, true, PRIV_VERSION_1_12_0, ext_zvkg), ISA_EXT_DATA_ENTRY(zvknha, true, PRIV_VERSION_1_12_0, ext_zvknha), ISA_EXT_DATA_ENTRY(zvknhb, true, PRIV_VERSION_1_12_0, ext_zvknhb), ISA_EXT_DATA_ENTRY(zvkns, true, PRIV_VERSION_1_12_0, ext_zvkns), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 92624bfc57..b3b1174d74 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -462,6 +462,7 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; bool ext_zvkb; + bool ext_zvkg; bool ext_zvknha; bool ext_zvknhb; bool ext_zvkns; -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:55:12 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIWJs-00044P-OQ for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:55:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIWJr-000443-CE for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:55:11 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIWJp-0002ix-Mi for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:55:11 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1R-007gSL-FA; Thu, 19 Jan 2023 14:36:10 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence Hunter , Nazar Kazakov Subject: [RFC PATCH 33/39] target/riscv: Add vghmac.vv decoding, translation and execution support Date: Thu, 19 Jan 2023 14:35:22 +0000 Message-Id: <20230119143528.1290950-34-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:55:11 -0000 Co-authored-by: Nazar Kazakov Signed-off-by: Nazar Kazakov Signed-off-by: Lawrence Hunter --- target/riscv/helper.h | 2 + target/riscv/insn32.decode | 3 ++ target/riscv/insn_trans/trans_rvzvkg.c.inc | 8 ++++ target/riscv/translate.c | 1 + target/riscv/vcrypto_helper.c | 45 ++++++++++++++++++++++ 5 files changed, 59 insertions(+) create mode 100644 target/riscv/insn_trans/trans_rvzvkg.c.inc diff --git a/target/riscv/helper.h b/target/riscv/helper.h index a82103ead9..6272294d50 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1199,3 +1199,5 @@ DEF_HELPER_5(vsha2cl_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsm3me_vv, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vsm3c_vi, void, ptr, ptr, i32, env, i32) + +DEF_HELPER_5(vghmac_vv, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 4a50114e92..ff044f8288 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -930,3 +930,6 @@ vsha2cl_vv 101111 1 ..... ..... 010 ..... 1110111 @r_vm_1 # *** RV64 Zvksh vector crypto extensions *** vsm3me_vv 100000 1 ..... ..... 010 ..... 1110111 @r_vm_1 vsm3c_vi 101011 1 ..... ..... 010 ..... 1110111 @r_vm_1 + +# *** RV64 Zvkg vector crypto extension *** +vghmac_vv 101100 1 ..... ..... 010 ..... 1110111 @r_vm_1 diff --git a/target/riscv/insn_trans/trans_rvzvkg.c.inc b/target/riscv/insn_trans/trans_rvzvkg.c.inc new file mode 100644 index 0000000000..576f5d39c4 --- /dev/null +++ b/target/riscv/insn_trans/trans_rvzvkg.c.inc @@ -0,0 +1,8 @@ +static bool vghmac_check(DisasContext *s, arg_rmrr *a) +{ + return opivv_check(s, a) && + s->vstart % 4 == 0 && + s->sew == MO_32; +} + +GEN_VV_UNMASKED_TRANS(vghmac_vv, vghmac_check) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 9ca2cec23a..0bc1c9db65 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1067,6 +1067,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_rvzvkns.c.inc" #include "insn_trans/trans_rvzvknh.c.inc" #include "insn_trans/trans_rvzvksh.c.inc" +#include "insn_trans/trans_rvzvkg.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" diff --git a/target/riscv/vcrypto_helper.c b/target/riscv/vcrypto_helper.c index 478e652c9b..a309ac3f03 100644 --- a/target/riscv/vcrypto_helper.c +++ b/target/riscv/vcrypto_helper.c @@ -827,3 +827,48 @@ void HELPER(vsm3c_vi)(void *vd_vptr, void *vs2_vptr, uint32_t uimm, vext_set_elems_1s(vd_vptr, vta, env->vl * esz, total_elems * esz); env->vstart = 0; } + +void HELPER(vghmac_vv)(void *vd_vptr, void *vs1_vptr, void *vs2_vptr, + CPURISCVState *env, uint32_t desc) +{ + uint64_t *vd = vd_vptr; + uint64_t *vs1 = vs1_vptr; + uint64_t *vs2 = vs2_vptr; + uint32_t vta = vext_vta(desc); + uint32_t total_elems = vext_get_total_elems(env, desc, 4); + + if (env->vl % 4 != 0) { + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + for (uint32_t i = env->vstart / 4; i < env->vl / 4; i++) { + __uint128_t Y = reverse_bits_byte_8(vd[i * 2 + 0]) | + ((__uint128_t)reverse_bits_byte_8(vd[i * 2 + 1]) << 64); + __uint128_t H = reverse_bits_byte_8(vs1[i * 2 + 0]) | + ((__uint128_t)reverse_bits_byte_8(vs1[i * 2 + 1]) << 64); + __uint128_t X = vs2[i * 2 + 0] | ((__uint128_t)vs2[i * 2 + 1] << 64); + __uint128_t Z = 0; + + for (uint j = 0; j < 128; j++) { + if ((Y >> j) & 1) { + Z ^= H; + } + bool reduce = ((H >> 127) & 1); + H = H << 1; + if (reduce) { + H ^= 0x87; + } + } + + Z = reverse_bits_byte_8(Z & UINT64_MAX) | + ((__uint128_t)reverse_bits_byte_8((Z >> 64) & UINT64_MAX) << 64); + + Z = Z ^ X; + + vd[i * 2 + 0] = Z & UINT64_MAX; + vd[i * 2 + 1] = (Z >> 64) & UINT64_MAX; + } + /* set tail elements to 1s */ + vext_set_elems_1s(vd, vta, env->vl * 4, total_elems * 4); + env->vstart = 0; +} -- 2.39.1 From MAILER-DAEMON Thu Jan 19 09:55:16 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIWJv-00047C-Sy for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 09:55:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIWJu-00046t-Nj for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:55:14 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIWJt-0002vU-E4 for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 09:55:14 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad.office.codethink.co.uk) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pIW1Q-007gSL-OU; Thu, 19 Jan 2023 14:36:09 +0000 From: Lawrence Hunter To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Kiran Ostrolenk Subject: [RFC PATCH 31/39] target/riscv: expose zvksh cpu property Date: Thu, 19 Jan 2023 14:35:20 +0000 Message-Id: <20230119143528.1290950-32-lawrence.hunter@codethink.co.uk> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 14:55:14 -0000 From: Kiran Ostrolenk Signed-off-by: Kiran Ostrolenk --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a21f1d43d4..c0c2d70abf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1079,6 +1079,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("zvknha", RISCVCPU, cfg.ext_zvknha, false), DEFINE_PROP_BOOL("zvknhb", RISCVCPU, cfg.ext_zvknhb, false), DEFINE_PROP_BOOL("zvkns", RISCVCPU, cfg.ext_zvkns, false), + DEFINE_PROP_BOOL("zvksh", RISCVCPU, cfg.ext_zvksh, false), /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), -- 2.39.1 From MAILER-DAEMON Thu Jan 19 10:00:42 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIWPC-0002wq-53 for mharc-qemu-riscv@gnu.org; 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boundary="0000000000002a5aa505f299c022" Received-SPF: pass client-ip=170.10.133.124; envelope-from=kkostiuk@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 19 Jan 2023 10:00:16 -0500 X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 08:30:59 -0000 --0000000000002a5aa505f299c022 Content-Type: text/plain; charset="UTF-8" Reviewed-by: Konstantin Kostiuk On Thu, Jan 19, 2023 at 9:00 AM Markus Armbruster wrote: > Clean up includes so that osdep.h is included first and headers > which it implies are not included manually. > > This commit was created with scripts/clean-includes. > > Signed-off-by: Markus Armbruster > --- > qga/cutils.h | 2 -- > qga/commands-posix.c | 1 - > qga/cutils.c | 3 ++- > 3 files changed, 2 insertions(+), 4 deletions(-) > > diff --git a/qga/cutils.h b/qga/cutils.h > index f0f30a7d28..c1f2f4b17a 100644 > --- a/qga/cutils.h > +++ b/qga/cutils.h > @@ -1,8 +1,6 @@ > #ifndef CUTILS_H_ > #define CUTILS_H_ > > -#include "qemu/osdep.h" > - > int qga_open_cloexec(const char *name, int flags, mode_t mode); > > #endif /* CUTILS_H_ */ > diff --git a/qga/commands-posix.c b/qga/commands-posix.c > index ebd33a643c..079689d79a 100644 > --- a/qga/commands-posix.c > +++ b/qga/commands-posix.c > @@ -51,7 +51,6 @@ > #else > #include > #endif > -#include > #ifdef CONFIG_SOLARIS > #include > #endif > diff --git a/qga/cutils.c b/qga/cutils.c > index b8e142ef64..b21bcf3683 100644 > --- a/qga/cutils.c > +++ b/qga/cutils.c > @@ -2,8 +2,9 @@ > * This work is licensed under the terms of the GNU GPL, version 2 or > later. > * See the COPYING file in the top-level directory. > */ > -#include "cutils.h" > > +#include "qemu/osdep.h" > +#include "cutils.h" > #include "qapi/error.h" > > /** > -- > 2.39.0 > > --0000000000002a5aa505f299c022 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Reviewed-by: Konstantin Kostiuk <kkostiuk@redhat.com>



=
On Thu, Jan 19, 2023 at 9:00 AM Marku= s Armbruster <armbru@redhat.com= > wrote:
Clea= n up includes so that osdep.h is included first and headers
which it implies are not included manually.

This commit was created with scripts/clean-includes.

Signed-off-by: Markus Armbruster <armbru@redhat.com>
---
=C2=A0qga/cutils.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 2 --
=C2=A0qga/commands-posix.c | 1 -
=C2=A0qga/cutils.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 3 ++-
=C2=A03 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/qga/cutils.h b/qga/cutils.h
index f0f30a7d28..c1f2f4b17a 100644
--- a/qga/cutils.h
+++ b/qga/cutils.h
@@ -1,8 +1,6 @@
=C2=A0#ifndef CUTILS_H_
=C2=A0#define CUTILS_H_

-#include "qemu/osdep.h"
-
=C2=A0int qga_open_cloexec(const char *name, int flags, mode_t mode);

=C2=A0#endif /* CUTILS_H_ */
diff --git a/qga/commands-posix.c b/qga/commands-posix.c
index ebd33a643c..079689d79a 100644
--- a/qga/commands-posix.c
+++ b/qga/commands-posix.c
@@ -51,7 +51,6 @@
=C2=A0#else
=C2=A0#include <net/ethernet.h>
=C2=A0#endif
-#include <sys/types.h>
=C2=A0#ifdef CONFIG_SOLARIS
=C2=A0#include <sys/sockio.h>
=C2=A0#endif
diff --git a/qga/cutils.c b/qga/cutils.c
index b8e142ef64..b21bcf3683 100644
--- a/qga/cutils.c
+++ b/qga/cutils.c
@@ -2,8 +2,9 @@
=C2=A0 * This work is licensed under the terms of the GNU GPL, version 2 or= later.
=C2=A0 * See the COPYING file in the top-level directory.
=C2=A0 */
-#include "cutils.h"

+#include "qemu/osdep.h"
+#include "cutils.h"
=C2=A0#include "qapi/error.h"

=C2=A0/**
--
2.39.0

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[209.85.167.51]) by smtp.gmail.com with ESMTPSA id bp22-20020a056512159600b004cc800b1f2csm5144524lfb.238.2023.01.19.07.20.27 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Jan 2023 07:20:27 -0800 (PST) Received: by mail-lf1-f51.google.com with SMTP id y25so3685215lfa.9 for ; Thu, 19 Jan 2023 07:20:27 -0800 (PST) X-Received: by 2002:ac2:46e3:0:b0:4b6:e80b:7e44 with SMTP id q3-20020ac246e3000000b004b6e80b7e44mr522698lfo.508.1674141626713; Thu, 19 Jan 2023 07:20:26 -0800 (PST) MIME-Version: 1.0 References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> In-Reply-To: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> From: Frank Chang Date: Thu, 19 Jan 2023 23:20:15 +0800 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [RFC PATCH 00/39] Add RISC-V cryptography extensions standardisation To: Lawrence Hunter Cc: qemu-riscv@nongnu.org, dickon.hood@codethink.co.uk, frank.chang@sifive.com Content-Type: multipart/alternative; boundary="000000000000f6cba305f29f782c" Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=frank.chang@sifive.com; helo=mail-lf1-x133.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 15:20:33 -0000 --000000000000f6cba305f29f782c Content-Type: text/plain; charset="UTF-8" Hi Lawrence, The spec says that: "With the exception of Zvknhb, each of these Vector Crypto Extensions can be build on any base Vector Extension, embedded (Zve*) or application ("V"). Zvknhb requires ELEN=64 and therefore cannot be implemented on a Zve32* base. While the Zvkb extension can be built on an Zve32* base, the vclmul[h] instructions will not be supported in such a case as they require SEW=64." So I guess we also need to add the checks for each Vector Crypto CPU property in riscv_cpu_realize() to check whether either "V" or "Zve*" extension is enabled or disabled, based on the restrictions defined in the spec. Regards, Frank Chang On Thu, Jan 19, 2023 at 10:39 PM Lawrence Hunter < lawrence.hunter@codethink.co.uk> wrote: > This RFC introduces an implementation for the six instruction sets > of the draft RISC-V cryptography extensions standardisation > specification. Once the specification has been ratified we will submit > these changes as a pull request email to this mailing list. Would this > be prefered by instruction group or unified as in this RFC? > > This patch set implements the instruction sets as per the 20221202 > version of the specification (1). > > Work performed by Dickon, Lawrence, Nazar, Kiran, and William from > Codethink > sponsored by SiFive, and Max Chou from SiFive. > > 1. https://github.com/riscv/riscv-crypto/releases > > Dickon Hood (1): > target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] decoding, > translation and execution support > > Kiran Ostrolenk (4): > target/riscv: Add vsha2ms.vv decoding, translation and execution > support > target/riscv: add zvksh cpu property > target/riscv: Add vsm3c.vi decoding, translation and execution support > target/riscv: expose zvksh cpu property > > Lawrence Hunter (16): > target/riscv: Add vclmul.vv decoding, translation and execution > support > target/riscv: Add vclmul.vx decoding, translation and execution > support > target/riscv: Add vclmulh.vv decoding, translation and execution > support > target/riscv: Add vclmulh.vx decoding, translation and execution > support > target/riscv: Add vaesef.vv decoding, translation and execution > support > target/riscv: Add vaesef.vs decoding, translation and execution > support > target/riscv: Add vaesdf.vv decoding, translation and execution > support > target/riscv: Add vaesdf.vs decoding, translation and execution > support > target/riscv: Add vaesdm.vv decoding, translation and execution > support > target/riscv: Add vaesdm.vs decoding, translation and execution > support > target/riscv: Add vaesz.vs decoding, translation and execution support > target/riscv: Add vsha2c[hl].vv decoding, translation and execution > support > target/riscv: Add vsm3me.vv decoding, translation and execution > support > target/riscv: add zvkg cpu property > target/riscv: Add vghmac.vv decoding, translation and execution > support > target/riscv: expose zvkg cpu property > > Max Chou (5): > crypto: Move SM4_SBOXWORD from target/riscv > crypto: Add SM4 constant parameter CK. > target/riscv: Add zvksed cfg property > target/riscv: Add Zvksed support > target/riscv: Expose Zvksed property > > Nazar Kazakov (10): > target/riscv: add zvkb cpu property > target/riscv: Add vrev8.v decoding, translation and execution support > target/riscv: Add vandn.[vv,vx,vi] decoding, translation and execution > support > target/riscv: expose zvkb cpu property > target/riscv: add zvkns cpu property > target/riscv: Add vaeskf1.vi decoding, translation and execution > support > target/riscv: Add vaeskf2.vi decoding, translation and execution > support > target/riscv: expose zvkns cpu property > target/riscv: add zvknh cpu properties > target/riscv: expose zvknh cpu properties > > William Salmon (3): > target/riscv: Add vbrev8.v decoding, translation and execution support > target/riscv: Add vaesem.vv decoding, translation and execution > support > target/riscv: Add vaesem.vs decoding, translation and execution > support > > crypto/sm4.c | 10 + > include/crypto/sm4.h | 8 + > include/qemu/bitops.h | 32 + > target/arm/crypto_helper.c | 10 +- > target/riscv/cpu.c | 15 + > target/riscv/cpu.h | 7 + > target/riscv/crypto_helper.c | 1 + > target/riscv/helper.h | 69 ++ > target/riscv/insn32.decode | 48 + > target/riscv/insn_trans/trans_rvzvkb.c.inc | 164 +++ > target/riscv/insn_trans/trans_rvzvkg.c.inc | 8 + > target/riscv/insn_trans/trans_rvzvknh.c.inc | 47 + > target/riscv/insn_trans/trans_rvzvkns.c.inc | 121 +++ > target/riscv/insn_trans/trans_rvzvksed.c.inc | 38 + > target/riscv/insn_trans/trans_rvzvksh.c.inc | 20 + > target/riscv/meson.build | 4 +- > target/riscv/translate.c | 6 + > target/riscv/vcrypto_helper.c | 1013 ++++++++++++++++++ > target/riscv/vector_helper.c | 242 +---- > target/riscv/vector_internals.c | 63 ++ > target/riscv/vector_internals.h | 226 ++++ > 21 files changed, 1902 insertions(+), 250 deletions(-) > create mode 100644 target/riscv/insn_trans/trans_rvzvkb.c.inc > create mode 100644 target/riscv/insn_trans/trans_rvzvkg.c.inc > create mode 100644 target/riscv/insn_trans/trans_rvzvknh.c.inc > create mode 100644 target/riscv/insn_trans/trans_rvzvkns.c.inc > create mode 100644 target/riscv/insn_trans/trans_rvzvksed.c.inc > create mode 100644 target/riscv/insn_trans/trans_rvzvksh.c.inc > create mode 100644 target/riscv/vcrypto_helper.c > create mode 100644 target/riscv/vector_internals.c > create mode 100644 target/riscv/vector_internals.h > > -- > 2.39.1 > > > --000000000000f6cba305f29f782c Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Lawrence,

The spec says that:<= br>
"With the exception of Zvknhb, each of these Vector Crypto= Extensions can be build on any base
Vector Extension, embedded (Zve*)= or application ("V"). Zvknhb requires ELEN=3D64 and thereforecannot be implemented on a Zve32* base.
While the Zvkb extension can be= built on an Zve32* base, the vclmul[h] instructions will not be
support= ed in such a case as they require SEW=3D64."

So I g= uess we also need to add the checks for each Vector Crypto CPU property in= =C2=A0riscv_cpu_realize()
to check whether either "V" o= r "Zve*" extension is enabled or disabled,
based on the= restrictions defined in the spec.

Regards,
<= div>Frank Chang


On Thu, Jan 19, 2023 at 10:39 PM Lawren= ce Hunter <lawrence.h= unter@codethink.co.uk> wrote:
This RFC introduces an implementation for the six inst= ruction sets
of the draft RISC-V cryptography extensions standardisation
specification. Once the specification has been ratified we will submit
these changes as a pull request email to this mailing list. Would this
be prefered by instruction group or unified as in this RFC?

This patch set implements the instruction sets as per the 20221202
version of the specification (1).

Work performed by Dickon, Lawrence, Nazar, Kiran, and William from Codethin= k
sponsored by SiFive, and Max Chou from SiFive.

1. https://github.com/riscv/riscv-crypto/releases<= br>
Dickon Hood (1):
=C2=A0 target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] decoding,
=C2=A0 =C2=A0 translation and execution support

Kiran Ostrolenk (4):
=C2=A0 target/riscv: Add vsha2ms.vv decoding, translation and execution
=C2=A0 =C2=A0 support
=C2=A0 target/riscv: add zvksh cpu property
=C2=A0 target/riscv: Add vsm3c.vi decoding, translation and execution support
=C2=A0 target/riscv: expose zvksh cpu property

Lawrence Hunter (16):
=C2=A0 target/riscv: Add vclmul.vv decoding, translation and execution
=C2=A0 =C2=A0 support
=C2=A0 target/riscv: Add vclmul.vx decoding, translation and execution
=C2=A0 =C2=A0 support
=C2=A0 target/riscv: Add vclmulh.vv decoding, translation and execution
=C2=A0 =C2=A0 support
=C2=A0 target/riscv: Add vclmulh.vx decoding, translation and execution
=C2=A0 =C2=A0 support
=C2=A0 target/riscv: Add vaesef.vv decoding, translation and execution
=C2=A0 =C2=A0 support
=C2=A0 target/riscv: Add vaesef.vs decoding, translation and execution
=C2=A0 =C2=A0 support
=C2=A0 target/riscv: Add vaesdf.vv decoding, translation and execution
=C2=A0 =C2=A0 support
=C2=A0 target/riscv: Add vaesdf.vs decoding, translation and execution
=C2=A0 =C2=A0 support
=C2=A0 target/riscv: Add vaesdm.vv decoding, translation and execution
=C2=A0 =C2=A0 support
=C2=A0 target/riscv: Add vaesdm.vs decoding, translation and execution
=C2=A0 =C2=A0 support
=C2=A0 target/riscv: Add vaesz.vs decoding, translation and execution suppo= rt
=C2=A0 target/riscv: Add vsha2c[hl].vv decoding, translation and execution<= br> =C2=A0 =C2=A0 support
=C2=A0 target/riscv: Add vsm3me.vv decoding, translation and execution
=C2=A0 =C2=A0 support
=C2=A0 target/riscv: add zvkg cpu property
=C2=A0 target/riscv: Add vghmac.vv decoding, translation and execution
=C2=A0 =C2=A0 support
=C2=A0 target/riscv: expose zvkg cpu property

Max Chou (5):
=C2=A0 crypto: Move SM4_SBOXWORD from target/riscv
=C2=A0 crypto: Add SM4 constant parameter CK.
=C2=A0 target/riscv: Add zvksed cfg property
=C2=A0 target/riscv: Add Zvksed support
=C2=A0 target/riscv: Expose Zvksed property

Nazar Kazakov (10):
=C2=A0 target/riscv: add zvkb cpu property
=C2=A0 target/riscv: Add vrev8.v decoding, translation and execution suppor= t
=C2=A0 target/riscv: Add vandn.[vv,vx,vi] decoding, translation and executi= on
=C2=A0 =C2=A0 support
=C2=A0 target/riscv: expose zvkb cpu property
=C2=A0 target/riscv: add zvkns cpu property
=C2=A0 target/riscv: Add vaeskf1.vi decoding, translation and execution
=C2=A0 =C2=A0 support
=C2=A0 target/riscv: Add vaeskf2.vi decoding, translation and execution
=C2=A0 =C2=A0 support
=C2=A0 target/riscv: expose zvkns cpu property
=C2=A0 target/riscv: add zvknh cpu properties
=C2=A0 target/riscv: expose zvknh cpu properties

William Salmon (3):
=C2=A0 target/riscv: Add vbrev8.v decoding, translation and execution suppo= rt
=C2=A0 target/riscv: Add vaesem.vv decoding, translation and execution
=C2=A0 =C2=A0 support
=C2=A0 target/riscv: Add vaesem.vs decoding, translation and execution
=C2=A0 =C2=A0 support

=C2=A0crypto/sm4.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2= =A010 +
=C2=A0include/crypto/sm4.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A0 8 +
=C2=A0include/qemu/bitops.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A032 +
=C2=A0target/arm/crypto_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A010 +-
=C2=A0target/riscv/cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A015 +
=C2=A0target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A0 7 +
=C2=A0target/riscv/crypto_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A0 1 +
=C2=A0target/riscv/helper.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A069 ++
=C2=A0target/riscv/insn32.decode=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A048 +
=C2=A0target/riscv/insn_trans/trans_rvzvkb.c.inc=C2=A0 =C2=A0|=C2=A0 164 ++= +
=C2=A0target/riscv/insn_trans/trans_rvzvkg.c.inc=C2=A0 =C2=A0|=C2=A0 =C2=A0= 8 +
=C2=A0target/riscv/insn_trans/trans_rvzvknh.c.inc=C2=A0 |=C2=A0 =C2=A047 +<= br> =C2=A0target/riscv/insn_trans/trans_rvzvkns.c.inc=C2=A0 |=C2=A0 121 +++
=C2=A0target/riscv/insn_trans/trans_rvzvksed.c.inc |=C2=A0 =C2=A038 +
=C2=A0target/riscv/insn_trans/trans_rvzvksh.c.inc=C2=A0 |=C2=A0 =C2=A020 +<= br> =C2=A0target/riscv/meson.build=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A0 4 +-
=C2=A0target/riscv/translate.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A0 6 +
=C2=A0target/riscv/vcrypto_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 | 1013 ++++++++++++++++++
=C2=A0target/riscv/vector_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0|=C2=A0 242 +----
=C2=A0target/riscv/vector_internals.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 |=C2=A0 =C2=A063 ++
=C2=A0target/riscv/vector_internals.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 |=C2=A0 226 ++++
=C2=A021 files changed, 1902 insertions(+), 250 deletions(-)
=C2=A0create mode 100644 target/riscv/insn_trans/trans_rvzvkb.c.inc
=C2=A0create mode 100644 target/riscv/insn_trans/trans_rvzvkg.c.inc
=C2=A0create mode 100644 target/riscv/insn_trans/trans_rvzvknh.c.inc
=C2=A0create mode 100644 target/riscv/insn_trans/trans_rvzvkns.c.inc
=C2=A0create mode 100644 target/riscv/insn_trans/trans_rvzvksed.c.inc
=C2=A0create mode 100644 target/riscv/insn_trans/trans_rvzvksh.c.inc
=C2=A0create mode 100644 target/riscv/vcrypto_helper.c
=C2=A0create mode 100644 target/riscv/vector_internals.c
=C2=A0create mode 100644 target/riscv/vector_internals.h

--
2.39.1


--000000000000f6cba305f29f782c-- From MAILER-DAEMON Thu Jan 19 11:42:27 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIXzf-0001Ru-OP for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 11:42:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIXzd-0001RD-Nc for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 11:42:25 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIXza-0007ZK-He for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 11:42:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674146542; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=HEI7l5ms6HIUjyJ+u9iD/hHdz4tVBVNn2Ky4AfTnhHA=; b=enkph6nlx881YFZSBoLQ+suPcG97DSjLPzsefb6PEAWA2RIA6EW7ZJmRryXbi8C8Bs5bxi EgmHkSzQEwRIFaaK15o0wu49PgL/MCnkBb9IVxI6hI0Dd6kPY/nYLxx8qxx13iRCtFCUno rk8NotZaQLPcXWq+h5mHu9XGhC7I6to= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-374-MOhusnXYM--Tflrmc5WuoQ-1; Thu, 19 Jan 2023 11:42:17 -0500 X-MC-Unique: MOhusnXYM--Tflrmc5WuoQ-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id ADE32101A521; Thu, 19 Jan 2023 16:42:16 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 879152026D76; Thu, 19 Jan 2023 16:42:15 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 65E6621E6A28; Thu, 19 Jan 2023 17:42:14 +0100 (CET) From: Markus Armbruster To: Warner Losh Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 04/19] bsd-user: Clean up includes References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-5-armbru@redhat.com> Date: Thu, 19 Jan 2023 17:42:14 +0100 In-Reply-To: (Warner Losh's message of "Thu, 19 Jan 2023 07:42:46 -0700") Message-ID: <87r0vqpjbt.fsf@pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Scanned-By: MIMEDefang 3.1 on 10.11.54.4 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 16:42:25 -0000 Warner Losh writes: > On Thu, Jan 19, 2023 at 12:00 AM Markus Armbruster > wrote: > >> Clean up includes so that osdep.h is included first and headers >> which it implies are not included manually. >> >> This commit was created with scripts/clean-includes. >> >> Signed-off-by: Markus Armbruster >> --- >> bsd-user/bsd-proc.h | 4 ---- >> bsd-user/qemu.h | 1 - >> bsd-user/arm/signal.c | 1 + >> bsd-user/arm/target_arch_cpu.c | 2 ++ >> bsd-user/freebsd/os-sys.c | 1 + >> bsd-user/i386/signal.c | 1 + >> bsd-user/i386/target_arch_cpu.c | 3 +-- >> bsd-user/main.c | 4 +--- >> bsd-user/strace.c | 1 - >> bsd-user/x86_64/signal.c | 1 + >> bsd-user/x86_64/target_arch_cpu.c | 3 +-- >> 11 files changed, 9 insertions(+), 13 deletions(-) >> >> diff --git a/bsd-user/bsd-proc.h b/bsd-user/bsd-proc.h >> index 68b66e571d..a1061bffb8 100644 >> --- a/bsd-user/bsd-proc.h >> +++ b/bsd-user/bsd-proc.h >> @@ -20,11 +20,7 @@ >> #ifndef BSD_PROC_H_ >> #define BSD_PROC_H_ >> >> -#include >> -#include >> -#include >> #include >> > > Did you test this on FreeBSD 12? FreeBSD 13 has started to climb the hill > where all includes are independent, but much of that hasn't been merged to > 12 yet. sys/types.h, at least, is documented as a prereq for both > sys/stat.h and sys/resource.h. > > I know many of these are in os-dep.h, and I've had trouble in the bsd-user > fork with that and the layout of the code which has arguably way too much > in the .h files. No, I didn't test on FreeBSD 12. Any .c must include qemu/osdep.h *first*. Any further inclusions of headers qemu/osdep.h includes already are no-ops unless the headers in question lack multiple inclusion guards. > Also, why didn't you move sys/resource.h and other such files to os-dep.h? > I'm struggling to understand the rules around what is or isn't included > where? This series is "run scripts/clean-includes, split it into reviewable chunks, tidy up blank lines". Moving more includes into qemu/osdep.h is out of scope. I sympathize with your complaint that QEMU does too much in headers in general, and in qemu/osdep.h in particular. >> -#include >> >> /* exit(2) */ >> static inline abi_long do_bsd_exit(void *cpu_env, abi_long arg1) >> diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h >> index be6105385e..0ceecfb6df 100644 >> --- a/bsd-user/qemu.h >> +++ b/bsd-user/qemu.h >> @@ -17,7 +17,6 @@ >> #ifndef QEMU_H >> #define QEMU_H >> >> -#include "qemu/osdep.h" >> #include "cpu.h" >> #include "qemu/units.h" >> #include "exec/cpu_ldst.h" >> diff --git a/bsd-user/arm/signal.c b/bsd-user/arm/signal.c >> index 2b1dd745d1..9734407543 100644 >> --- a/bsd-user/arm/signal.c >> +++ b/bsd-user/arm/signal.c >> @@ -17,6 +17,7 @@ >> * along with this program; if not, see . >> */ >> >> +#include "qemu/osdep.h" >> #include "qemu.h" >> >> /* >> diff --git a/bsd-user/arm/target_arch_cpu.c >> b/bsd-user/arm/target_arch_cpu.c >> index 02bf9149d5..fe38ae2210 100644 >> --- a/bsd-user/arm/target_arch_cpu.c >> +++ b/bsd-user/arm/target_arch_cpu.c >> @@ -16,6 +16,8 @@ >> * You should have received a copy of the GNU General Public License >> * along with this program; if not, see . >> */ >> + >> +#include "qemu/osdep.h" >> #include "target_arch.h" >> >> void target_cpu_set_tls(CPUARMState *env, target_ulong newtls) >> diff --git a/bsd-user/freebsd/os-sys.c b/bsd-user/freebsd/os-sys.c >> index 309e27b9d6..1676ec10f8 100644 >> --- a/bsd-user/freebsd/os-sys.c >> +++ b/bsd-user/freebsd/os-sys.c >> @@ -17,6 +17,7 @@ >> * along with this program; if not, see . >> */ >> >> +#include "qemu/osdep.h" >> #include "qemu.h" >> #include "target_arch_sysarch.h" >> >> diff --git a/bsd-user/i386/signal.c b/bsd-user/i386/signal.c >> index 5dd975ce56..a3131047b8 100644 >> --- a/bsd-user/i386/signal.c >> +++ b/bsd-user/i386/signal.c >> @@ -17,6 +17,7 @@ >> * along with this program; if not, see . >> */ >> >> +#include "qemu/osdep.h" >> #include "qemu.h" >> >> /* >> diff --git a/bsd-user/i386/target_arch_cpu.c >> b/bsd-user/i386/target_arch_cpu.c >> index d349e45299..2a3af2ddef 100644 >> --- a/bsd-user/i386/target_arch_cpu.c >> +++ b/bsd-user/i386/target_arch_cpu.c >> @@ -17,9 +17,8 @@ >> * along with this program; if not, see . >> */ >> >> -#include >> - >> #include "qemu/osdep.h" >> + >> #include "cpu.h" >> #include "qemu.h" >> #include "qemu/timer.h" >> diff --git a/bsd-user/main.c b/bsd-user/main.c >> index 6f09180d65..41290e16f9 100644 >> --- a/bsd-user/main.c >> +++ b/bsd-user/main.c >> @@ -18,12 +18,10 @@ >> * along with this program; if not, see . >> */ >> >> -#include >> -#include >> +#include "qemu/osdep.h" >> #include >> #include >> >> -#include "qemu/osdep.h" >> #include "qemu/help-texts.h" >> #include "qemu/units.h" >> #include "qemu/accel.h" >> diff --git a/bsd-user/strace.c b/bsd-user/strace.c >> index a77d10dd6b..96499751eb 100644 >> --- a/bsd-user/strace.c >> +++ b/bsd-user/strace.c >> @@ -20,7 +20,6 @@ >> #include >> #include >> #include >> -#include >> >> #include "qemu.h" >> >> diff --git a/bsd-user/x86_64/signal.c b/bsd-user/x86_64/signal.c >> index c3875bc4c6..46cb865180 100644 >> --- a/bsd-user/x86_64/signal.c >> +++ b/bsd-user/x86_64/signal.c >> @@ -16,6 +16,7 @@ >> * along with this program; if not, see . >> */ >> >> +#include "qemu/osdep.h" >> #include "qemu.h" >> >> /* >> diff --git a/bsd-user/x86_64/target_arch_cpu.c >> b/bsd-user/x86_64/target_arch_cpu.c >> index be7bd10720..1d32f18907 100644 >> --- a/bsd-user/x86_64/target_arch_cpu.c >> +++ b/bsd-user/x86_64/target_arch_cpu.c >> @@ -17,9 +17,8 @@ >> * along with this program; if not, see . >> */ >> >> -#include >> - >> #include "qemu/osdep.h" >> + >> #include "cpu.h" >> #include "qemu.h" >> #include "qemu/timer.h" >> > > I suppose these are fine. How do I run the cleanup script? I have 2x the > number of files not upstream in the bsd-user fork that I'd like to cleanup > as well and they are likely a bigger mess and I'll just upstream them in > the messy state unless I understand how to keep the neat :). I used $ scripts/clean-includes --check-dup-head --all Which resulted in a big mess I didn't dare to submit for review :) So I split it up. Easiest way was to identify useful sets of files, add files that include headers from the set, transitively, then run $ scripts/clean-includes FILES... --check-dup-head reports possible duplicate inclusions. It is prone to false positives. That's why it merely reports them. You may want to not use it for now. There's a big usage comment at the beginning of the script. Hope this helps! From MAILER-DAEMON Thu Jan 19 11:48:09 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIY5B-0005If-2X for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 11:48:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIY59-0005IE-2H for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 11:48:07 -0500 Received: from mail-oa1-x2d.google.com ([2001:4860:4864:20::2d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIY57-0000Cj-4C for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 11:48:06 -0500 Received: by mail-oa1-x2d.google.com with SMTP id 586e51a60fabf-15f944494ccso3175742fac.8 for ; Thu, 19 Jan 2023 08:48:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=7IjGwceFrorEQWODkaJ+qujMdCxUhiZTDcNwBtO4cCs=; b=liR+LRDsaEnd1dgpaffjlk0rFPNtRChunkKb9Ky95H+e71FLY/Gtw7PHSO3wqCoqXH ca2iytGtcI/F8ol2X1XbVggC0dACOowC2WLyD9aw6tpHFpjdbZlYyaRrFLmiEGwXrWpd JG5kTuOVwzuMgCuM2j0VohoJfhpYn18WSwCzoOgxnS//najb02hkHQnXLVPeGN9OyXf8 CzLdUm/tgawmeSFMe/MRc3ZezV0USlCtj7Zx5Jrf2kE2WJsCwBUWCxbskBa4M3Hjz3M6 kX3CgW9fkrVr4rUqBuciwWcVApz/NwQPnU4wwS/4sgg6+IH/BIOFZOt0wtOKTZLDgK5t Vbiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=7IjGwceFrorEQWODkaJ+qujMdCxUhiZTDcNwBtO4cCs=; b=30NXR/ItX08iyIFKMC213Q6FNxGO7qxOB9fnKk7kzcau0eNbMuF7i2CLL+3ka4tyax clqPLQ8zI09WMZ+aA8KpHX+TOOM7WQoFGN6iaby7L7cvF1kGviDNhBIYu5GkSCDbiqyO O/Yc03SF97OURw+f/CnjVYXyCM1e1VEltGk1QuCqZ8RJ9Q1UxzN+4vBM4T3IUucwrsgJ FN1sYSO8lG0QyOYO1gZJ4tt5+E3GO4R+cma9EkuPWK03yzNWWjFuuYevPbQMyNYSK749 WZ3tAQdlK0WRdROopembclosfUwbqBcIYDouNuuRGCBcKyqG9aj2ZcyNFmaAeeOGqeAf lGyA== X-Gm-Message-State: AFqh2kq/l3XftBg3LA6coiEnNzITa/ox+SMl/Lh6Gzsn6yFpRLvkjs3W E7fwzsdhpmn3WYCZNuENj2XzDw== X-Google-Smtp-Source: AMrXdXtcvxtakR5L5av+htXdmiRmxsBg5Q4zrG5FepI3esNrX0hNbbLSh1i74HRHMKWXRRI/I8tdPw== X-Received: by 2002:a05:6871:42c9:b0:142:83f9:fa0 with SMTP id lt9-20020a05687142c900b0014283f90fa0mr6340206oab.11.1674146883028; Thu, 19 Jan 2023 08:48:03 -0800 (PST) Received: from [192.168.68.107] ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id bd13-20020a056870d78d00b0014fe4867dc7sm20114788oab.56.2023.01.19.08.48.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Jan 2023 08:48:02 -0800 (PST) Message-ID: <253a083d-d31c-7c83-7d78-835d736c27a6@ventanamicro.com> Date: Thu, 19 Jan 2023 13:47:58 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH v2 3/6] hw/riscv: simplify riscv_compute_fdt_addr() Content-Language: en-US To: Alistair Francis Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, philmd@linaro.org References: <20230116173420.1146808-1-dbarboza@ventanamicro.com> <20230116173420.1146808-4-dbarboza@ventanamicro.com> From: Daniel Henrique Barboza In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2d.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.094, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 16:48:07 -0000 On 1/18/23 23:23, Alistair Francis wrote: > On Tue, Jan 17, 2023 at 3:34 AM Daniel Henrique Barboza > wrote: >> All callers are using attributes from the MachineState object. Use a >> pointer to it instead of passing dram_size (which is always >> machine->ram_size) and fdt (always machine->fdt). >> >> Signed-off-by: Daniel Henrique Barboza >> --- >> hw/riscv/boot.c | 6 +++--- >> hw/riscv/microchip_pfsoc.c | 4 ++-- >> hw/riscv/sifive_u.c | 4 ++-- >> hw/riscv/spike.c | 4 ++-- >> hw/riscv/virt.c | 3 +-- >> include/hw/riscv/boot.h | 2 +- >> 6 files changed, 11 insertions(+), 12 deletions(-) >> >> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c >> index b213a32157..508da3f5c7 100644 >> --- a/hw/riscv/boot.c >> +++ b/hw/riscv/boot.c >> @@ -255,11 +255,11 @@ void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) >> * >> * The FDT is fdt_packed() during the calculation. >> */ >> -uint32_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size, >> - void *fdt) >> +uint32_t riscv_compute_fdt_addr(MachineState *machine, hwaddr dram_base) >> { >> + void *fdt = machine->fdt; >> uint64_t temp; >> - hwaddr dram_end = dram_base + mem_size; >> + hwaddr dram_end = dram_base + machine->ram_size; >> int ret = fdt_pack(fdt); >> int fdtsize; >> >> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c >> index dcdbc2cac3..a53e48e996 100644 >> --- a/hw/riscv/microchip_pfsoc.c >> +++ b/hw/riscv/microchip_pfsoc.c >> @@ -641,8 +641,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) >> } >> >> /* Compute the fdt load address in dram */ >> - fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base, >> - machine->ram_size, machine->fdt); >> + fdt_load_addr = riscv_compute_fdt_addr(machine, >> + memmap[MICROCHIP_PFSOC_DRAM_LO].base); > I don't think this is correct here. > > So, first up I understand we don't correctly handle this today, *but* > I see this change as a step in the wrong direction. > > The problem here is that ram is split over two areas. So if > machine->ram_size is larger then 0x40000000 it is going to overflow > MICROCHIP_PFSOC_DRAM_LO and jump to MICROCHIP_PFSOC_DRAM_HI > (0x1000000000). > > So we really want something like this > > /* Compute the fdt load address in dram */ > if (machine->ram_size > memmap[MICROCHIP_PFSOC_DRAM_LO].size) { > fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_HI].base, > machine->ram_size - > memmap[MICROCHIP_PFSOC_DRAM_LO].size, > machine->fdt); > } else { > fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, > machine->ram_size, > machine->fdt); > } Checking the code from microchip-icicle-kit I see that the minimal ram_size is 1.5Gb. In fact the machine would not allow anything less: $ ./qemu-system-riscv64 -M microchip-icicle-kit -m 512M qemu-system-riscv64: Invalid RAM size, should be bigger than 1.5 GiB The reasoning is in its machine_class_init(): ====      * Map 513 MiB high memory, the mimimum required high memory size, because      * HSS will do memory test against the high memory address range regardless      * of physical memory installed. ==== This also means that this machine is putting the FDT in the wrong spot every time, since 1.5Gb is going to hit in the gap between the low and hi memory every time and the start of the hi area is 64Gb away. I believe this is yet another reason to create a specific helper to deal with the FDT of this machine. I'll re-send with this change. Daniel > > to handle overflowing MICROCHIP_PFSOC_DRAM_LO. While this patch is > going in the wrong direction and making that more difficult > > Alistair > > > >> riscv_load_fdt(fdt_load_addr, machine->fdt); >> >> /* Load the reset vector */ >> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c >> index 626d4dc2f3..ebfddf161d 100644 >> --- a/hw/riscv/sifive_u.c >> +++ b/hw/riscv/sifive_u.c >> @@ -616,8 +616,8 @@ static void sifive_u_machine_init(MachineState *machine) >> kernel_entry = 0; >> } >> >> - fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, >> - machine->ram_size, machine->fdt); >> + fdt_load_addr = riscv_compute_fdt_addr(machine, >> + memmap[SIFIVE_U_DEV_DRAM].base); >> riscv_load_fdt(fdt_load_addr, machine->fdt); >> >> if (!riscv_is_32bit(&s->soc.u_cpus)) { >> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c >> index 88b9fdfc36..afd581436b 100644 >> --- a/hw/riscv/spike.c >> +++ b/hw/riscv/spike.c >> @@ -324,8 +324,8 @@ static void spike_board_init(MachineState *machine) >> kernel_entry = 0; >> } >> >> - fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, >> - machine->ram_size, machine->fdt); >> + fdt_load_addr = riscv_compute_fdt_addr(machine, >> + memmap[SPIKE_DRAM].base); >> riscv_load_fdt(fdt_load_addr, machine->fdt); >> >> /* load the reset vector */ >> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c >> index 839dfaa125..cbba0b8930 100644 >> --- a/hw/riscv/virt.c >> +++ b/hw/riscv/virt.c >> @@ -1307,8 +1307,7 @@ static void virt_machine_done(Notifier *notifier, void *data) >> start_addr = virt_memmap[VIRT_FLASH].base; >> } >> >> - fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, >> - machine->ram_size, machine->fdt); >> + fdt_load_addr = riscv_compute_fdt_addr(machine, memmap[VIRT_DRAM].base); >> riscv_load_fdt(fdt_load_addr, machine->fdt); >> >> /* load the reset vector */ >> diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h >> index 9aea7b9c46..f933de88fb 100644 >> --- a/include/hw/riscv/boot.h >> +++ b/include/hw/riscv/boot.h >> @@ -47,7 +47,7 @@ target_ulong riscv_load_kernel(MachineState *machine, >> target_ulong firmware_end_addr, >> symbol_fn_t sym_cb); >> void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); >> -uint32_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, void *fdt); >> +uint32_t riscv_compute_fdt_addr(MachineState *machine, hwaddr dram_start); >> void riscv_load_fdt(uint32_t fdt_addr, void *fdt); >> void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, >> hwaddr saddr, >> -- >> 2.39.0 >> >> From MAILER-DAEMON Thu Jan 19 12:05:19 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIYLn-0005SI-LG for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 12:05:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIYLm-0005Rj-1d for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 12:05:18 -0500 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIYLj-0003EY-5g for qemu-riscv@nongnu.org; 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boundary="000000000000a59ef205f2a0efeb" Received-SPF: none client-ip=2a00:1450:4864:20::62c; envelope-from=wlosh@bsdimp.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 17:05:18 -0000 --000000000000a59ef205f2a0efeb Content-Type: text/plain; charset="UTF-8" On Thu, Jan 19, 2023 at 9:42 AM Markus Armbruster wrote: > Warner Losh writes: > > > On Thu, Jan 19, 2023 at 12:00 AM Markus Armbruster > > wrote: > > > >> Clean up includes so that osdep.h is included first and headers > >> which it implies are not included manually. > >> > >> This commit was created with scripts/clean-includes. > >> > >> Signed-off-by: Markus Armbruster > >> --- > >> bsd-user/bsd-proc.h | 4 ---- > >> bsd-user/qemu.h | 1 - > >> bsd-user/arm/signal.c | 1 + > >> bsd-user/arm/target_arch_cpu.c | 2 ++ > >> bsd-user/freebsd/os-sys.c | 1 + > >> bsd-user/i386/signal.c | 1 + > >> bsd-user/i386/target_arch_cpu.c | 3 +-- > >> bsd-user/main.c | 4 +--- > >> bsd-user/strace.c | 1 - > >> bsd-user/x86_64/signal.c | 1 + > >> bsd-user/x86_64/target_arch_cpu.c | 3 +-- > >> 11 files changed, 9 insertions(+), 13 deletions(-) > >> > >> diff --git a/bsd-user/bsd-proc.h b/bsd-user/bsd-proc.h > >> index 68b66e571d..a1061bffb8 100644 > >> --- a/bsd-user/bsd-proc.h > >> +++ b/bsd-user/bsd-proc.h > >> @@ -20,11 +20,7 @@ > >> #ifndef BSD_PROC_H_ > >> #define BSD_PROC_H_ > >> > >> -#include > >> -#include > >> -#include > >> #include > >> > > > > Did you test this on FreeBSD 12? FreeBSD 13 has started to climb the hill > > where all includes are independent, but much of that hasn't been merged > to > > 12 yet. sys/types.h, at least, is documented as a prereq for both > > sys/stat.h and sys/resource.h. > > > > I know many of these are in os-dep.h, and I've had trouble in the > bsd-user > > fork with that and the layout of the code which has arguably way too much > > in the .h files. > > No, I didn't test on FreeBSD 12. > OK. Fair enough. If it passes the CI tests, then it's likely fine (though if I hit issues, I'll submit patches). > Any .c must include qemu/osdep.h *first*. Any further inclusions of > headers qemu/osdep.h includes already are no-ops unless the headers in > question lack multiple inclusion guards. > OK. > > Also, why didn't you move sys/resource.h and other such files to > os-dep.h? > > I'm struggling to understand the rules around what is or isn't included > > where? > > This series is "run scripts/clean-includes, split it into reviewable > chunks, tidy up blank lines". Moving more includes into qemu/osdep.h is > out of scope. > OK. Fair point. I'm happy with that answer since it tells me I could move things there too, if need be. > I sympathize with your complaint that QEMU does too much in headers in > general, and in qemu/osdep.h in particular. > Yea, I'm not entirely sure it's a complaint, or if it's an observation of difficulties relative to other code bases... I go back and forth on my opinion of it... > >> -#include > >> > >> /* exit(2) */ > >> static inline abi_long do_bsd_exit(void *cpu_env, abi_long arg1) > >> diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h > >> index be6105385e..0ceecfb6df 100644 > >> --- a/bsd-user/qemu.h > >> +++ b/bsd-user/qemu.h > >> @@ -17,7 +17,6 @@ > >> #ifndef QEMU_H > >> #define QEMU_H > >> > >> -#include "qemu/osdep.h" > >> #include "cpu.h" > >> #include "qemu/units.h" > >> #include "exec/cpu_ldst.h" > >> diff --git a/bsd-user/arm/signal.c b/bsd-user/arm/signal.c > >> index 2b1dd745d1..9734407543 100644 > >> --- a/bsd-user/arm/signal.c > >> +++ b/bsd-user/arm/signal.c > >> @@ -17,6 +17,7 @@ > >> * along with this program; if not, see >. > >> */ > >> > >> +#include "qemu/osdep.h" > >> #include "qemu.h" > >> > >> /* > >> diff --git a/bsd-user/arm/target_arch_cpu.c > >> b/bsd-user/arm/target_arch_cpu.c > >> index 02bf9149d5..fe38ae2210 100644 > >> --- a/bsd-user/arm/target_arch_cpu.c > >> +++ b/bsd-user/arm/target_arch_cpu.c > >> @@ -16,6 +16,8 @@ > >> * You should have received a copy of the GNU General Public License > >> * along with this program; if not, see >. > >> */ > >> + > >> +#include "qemu/osdep.h" > >> #include "target_arch.h" > >> > >> void target_cpu_set_tls(CPUARMState *env, target_ulong newtls) > >> diff --git a/bsd-user/freebsd/os-sys.c b/bsd-user/freebsd/os-sys.c > >> index 309e27b9d6..1676ec10f8 100644 > >> --- a/bsd-user/freebsd/os-sys.c > >> +++ b/bsd-user/freebsd/os-sys.c > >> @@ -17,6 +17,7 @@ > >> * along with this program; if not, see >. > >> */ > >> > >> +#include "qemu/osdep.h" > >> #include "qemu.h" > >> #include "target_arch_sysarch.h" > >> > >> diff --git a/bsd-user/i386/signal.c b/bsd-user/i386/signal.c > >> index 5dd975ce56..a3131047b8 100644 > >> --- a/bsd-user/i386/signal.c > >> +++ b/bsd-user/i386/signal.c > >> @@ -17,6 +17,7 @@ > >> * along with this program; if not, see >. > >> */ > >> > >> +#include "qemu/osdep.h" > >> #include "qemu.h" > >> > >> /* > >> diff --git a/bsd-user/i386/target_arch_cpu.c > >> b/bsd-user/i386/target_arch_cpu.c > >> index d349e45299..2a3af2ddef 100644 > >> --- a/bsd-user/i386/target_arch_cpu.c > >> +++ b/bsd-user/i386/target_arch_cpu.c > >> @@ -17,9 +17,8 @@ > >> * along with this program; if not, see >. > >> */ > >> > >> -#include > >> - > >> #include "qemu/osdep.h" > >> + > >> #include "cpu.h" > >> #include "qemu.h" > >> #include "qemu/timer.h" > >> diff --git a/bsd-user/main.c b/bsd-user/main.c > >> index 6f09180d65..41290e16f9 100644 > >> --- a/bsd-user/main.c > >> +++ b/bsd-user/main.c > >> @@ -18,12 +18,10 @@ > >> * along with this program; if not, see >. > >> */ > >> > >> -#include > >> -#include > >> +#include "qemu/osdep.h" > >> #include > >> #include > >> > >> -#include "qemu/osdep.h" > >> #include "qemu/help-texts.h" > >> #include "qemu/units.h" > >> #include "qemu/accel.h" > >> diff --git a/bsd-user/strace.c b/bsd-user/strace.c > >> index a77d10dd6b..96499751eb 100644 > >> --- a/bsd-user/strace.c > >> +++ b/bsd-user/strace.c > >> @@ -20,7 +20,6 @@ > >> #include > >> #include > >> #include > >> -#include > >> > >> #include "qemu.h" > >> > >> diff --git a/bsd-user/x86_64/signal.c b/bsd-user/x86_64/signal.c > >> index c3875bc4c6..46cb865180 100644 > >> --- a/bsd-user/x86_64/signal.c > >> +++ b/bsd-user/x86_64/signal.c > >> @@ -16,6 +16,7 @@ > >> * along with this program; if not, see >. > >> */ > >> > >> +#include "qemu/osdep.h" > >> #include "qemu.h" > >> > >> /* > >> diff --git a/bsd-user/x86_64/target_arch_cpu.c > >> b/bsd-user/x86_64/target_arch_cpu.c > >> index be7bd10720..1d32f18907 100644 > >> --- a/bsd-user/x86_64/target_arch_cpu.c > >> +++ b/bsd-user/x86_64/target_arch_cpu.c > >> @@ -17,9 +17,8 @@ > >> * along with this program; if not, see >. > >> */ > >> > >> -#include > >> - > >> #include "qemu/osdep.h" > >> + > >> #include "cpu.h" > >> #include "qemu.h" > >> #include "qemu/timer.h" > >> > > > > I suppose these are fine. How do I run the cleanup script? I have 2x the > > number of files not upstream in the bsd-user fork that I'd like to > cleanup > > as well and they are likely a bigger mess and I'll just upstream them in > > the messy state unless I understand how to keep the neat :). > > I used > > $ scripts/clean-includes --check-dup-head --all > > Which resulted in a big mess I didn't dare to submit for review :) So I > split it up. Easiest way was to identify useful sets of files, add > files that include headers from the set, transitively, then run > > $ scripts/clean-includes FILES... > > --check-dup-head reports possible duplicate inclusions. It is prone to > false positives. That's why it merely reports them. You may want to > not use it for now. > > There's a big usage comment at the beginning of the script. > > Hope this helps! > It does. After your changes land, I'll merge, and run this on the branch. I have a few changes queued up, and have been contemplating changes to my upstreaming workflow to speed the process along... So I'm happy with it. Thanks for the cleanup and the time to answer my questions. Reviewed-by: Warner Losh Warner --000000000000a59ef205f2a0efeb Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Thu, Jan 19, 2023 at 9:42 AM Marku= s Armbruster <armbru@redhat.com= > wrote:
Warn= er Losh <imp@bsdimp.= com> writes:

> On Thu, Jan 19, 2023 at 12:00 AM Markus Armbruster <armbru@redhat.com>
> wrote:
>
>> Clean up includes so that osdep.h is included first and headers >> which it implies are not included manually.
>>
>> This commit was created with scripts/clean-includes.
>>
>> Signed-off-by: Markus Armbruster <armbru@redhat.com>
>> ---
>>=C2=A0 bsd-user/bsd-proc.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0| 4 ----
>>=C2=A0 bsd-user/qemu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0| 1 -
>>=C2=A0 bsd-user/arm/signal.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0| 1 +
>>=C2=A0 bsd-user/arm/target_arch_cpu.c=C2=A0 =C2=A0 | 2 ++
>>=C2=A0 bsd-user/freebsd/os-sys.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|= 1 +
>>=C2=A0 bsd-user/i386/signal.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 | 1 +
>>=C2=A0 bsd-user/i386/target_arch_cpu.c=C2=A0 =C2=A0| 3 +--
>>=C2=A0 bsd-user/main.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0| 4 +---
>>=C2=A0 bsd-user/strace.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0| 1 -
>>=C2=A0 bsd-user/x86_64/signal.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |= 1 +
>>=C2=A0 bsd-user/x86_64/target_arch_cpu.c | 3 +--
>>=C2=A0 11 files changed, 9 insertions(+), 13 deletions(-)
>>
>> diff --git a/bsd-user/bsd-proc.h b/bsd-user/bsd-proc.h
>> index 68b66e571d..a1061bffb8 100644
>> --- a/bsd-user/bsd-proc.h
>> +++ b/bsd-user/bsd-proc.h
>> @@ -20,11 +20,7 @@
>>=C2=A0 #ifndef BSD_PROC_H_
>>=C2=A0 #define BSD_PROC_H_
>>
>> -#include <sys/types.h>
>> -#include <sys/stat.h>
>> -#include <sys/time.h>
>>=C2=A0 #include <sys/resource.h>
>>
>
> Did you test this on FreeBSD 12? FreeBSD 13 has started to climb the h= ill
> where all includes are independent, but much of that hasn't been m= erged to
> 12 yet. sys/types.h, at least, is documented as a prereq for both
> sys/stat.h and sys/resource.h.
>
> I know many of these are in os-dep.h, and I've had trouble in the = bsd-user
> fork with that and the layout of the code which has arguably way too m= uch
> in the .h files.

No, I didn't test on FreeBSD 12.

OK= . Fair enough. If it passes the CI tests, then it's likely fine (though= if I hit issues, I'll submit patches).
=C2=A0
Any .c must include qemu/osdep.h *first*.=C2=A0 Any further inclusions of headers qemu/osdep.h includes already are no-ops unless the headers in
question lack multiple inclusion guards.

OK.
=C2=A0
> Also, why didn't you move sys/resource.h and other such files to o= s-dep.h?
> I'm struggling to understand the rules around what is or isn't= included
> where?

This series is "run scripts/clean-includes, split it into reviewable chunks, tidy up blank lines".=C2=A0 Moving more includes into qemu/osd= ep.h is
out of scope.

OK. Fair point. I'm h= appy with that answer since it tells me I could move things there too, if n= eed be.
=C2=A0
I sympathize with your complaint that QEMU does too much in headers in
general, and in qemu/osdep.h in particular.

=
Yea, I'm not entirely sure=C2=A0 it's a complaint, or if it= 9;s an observation of difficulties relative to other code bases... I go bac= k and forth on my opinion of it...
=C2=A0
>> -#include <unistd.h>
>>
>>=C2=A0 /* exit(2) */
>>=C2=A0 static inline abi_long do_bsd_exit(void *cpu_env, abi_long a= rg1)
>> diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h
>> index be6105385e..0ceecfb6df 100644
>> --- a/bsd-user/qemu.h
>> +++ b/bsd-user/qemu.h
>> @@ -17,7 +17,6 @@
>>=C2=A0 #ifndef QEMU_H
>>=C2=A0 #define QEMU_H
>>
>> -#include "qemu/osdep.h"
>>=C2=A0 #include "cpu.h"
>>=C2=A0 #include "qemu/units.h"
>>=C2=A0 #include "exec/cpu_ldst.h"
>> diff --git a/bsd-user/arm/signal.c b/bsd-user/arm/signal.c
>> index 2b1dd745d1..9734407543 100644
>> --- a/bsd-user/arm/signal.c
>> +++ b/bsd-user/arm/signal.c
>> @@ -17,6 +17,7 @@
>>=C2=A0 =C2=A0*=C2=A0 along with this program; if not, see <ht= tp://www.gnu.org/licenses/>.
>>=C2=A0 =C2=A0*/
>>
>> +#include "qemu/osdep.h"
>>=C2=A0 #include "qemu.h"
>>
>>=C2=A0 /*
>> diff --git a/bsd-user/arm/target_arch_cpu.c
>> b/bsd-user/arm/target_arch_cpu.c
>> index 02bf9149d5..fe38ae2210 100644
>> --- a/bsd-user/arm/target_arch_cpu.c
>> +++ b/bsd-user/arm/target_arch_cpu.c
>> @@ -16,6 +16,8 @@
>>=C2=A0 =C2=A0*=C2=A0 You should have received a copy of the GNU Gen= eral Public License
>>=C2=A0 =C2=A0*=C2=A0 along with this program; if not, see <ht= tp://www.gnu.org/licenses/>.
>>=C2=A0 =C2=A0*/
>> +
>> +#include "qemu/osdep.h"
>>=C2=A0 #include "target_arch.h"
>>
>>=C2=A0 void target_cpu_set_tls(CPUARMState *env, target_ulong newtl= s)
>> diff --git a/bsd-user/freebsd/os-sys.c b/bsd-user/freebsd/os-sys.c=
>> index 309e27b9d6..1676ec10f8 100644
>> --- a/bsd-user/freebsd/os-sys.c
>> +++ b/bsd-user/freebsd/os-sys.c
>> @@ -17,6 +17,7 @@
>>=C2=A0 =C2=A0*=C2=A0 along with this program; if not, see <ht= tp://www.gnu.org/licenses/>.
>>=C2=A0 =C2=A0*/
>>
>> +#include "qemu/osdep.h"
>>=C2=A0 #include "qemu.h"
>>=C2=A0 #include "target_arch_sysarch.h"
>>
>> diff --git a/bsd-user/i386/signal.c b/bsd-user/i386/signal.c
>> index 5dd975ce56..a3131047b8 100644
>> --- a/bsd-user/i386/signal.c
>> +++ b/bsd-user/i386/signal.c
>> @@ -17,6 +17,7 @@
>>=C2=A0 =C2=A0*=C2=A0 along with this program; if not, see <ht= tp://www.gnu.org/licenses/>.
>>=C2=A0 =C2=A0*/
>>
>> +#include "qemu/osdep.h"
>>=C2=A0 #include "qemu.h"
>>
>>=C2=A0 /*
>> diff --git a/bsd-user/i386/target_arch_cpu.c
>> b/bsd-user/i386/target_arch_cpu.c
>> index d349e45299..2a3af2ddef 100644
>> --- a/bsd-user/i386/target_arch_cpu.c
>> +++ b/bsd-user/i386/target_arch_cpu.c
>> @@ -17,9 +17,8 @@
>>=C2=A0 =C2=A0*=C2=A0 along with this program; if not, see <ht= tp://www.gnu.org/licenses/>.
>>=C2=A0 =C2=A0*/
>>
>> -#include <sys/types.h>
>> -
>>=C2=A0 #include "qemu/osdep.h"
>> +
>>=C2=A0 #include "cpu.h"
>>=C2=A0 #include "qemu.h"
>>=C2=A0 #include "qemu/timer.h"
>> diff --git a/bsd-user/main.c b/bsd-user/main.c
>> index 6f09180d65..41290e16f9 100644
>> --- a/bsd-user/main.c
>> +++ b/bsd-user/main.c
>> @@ -18,12 +18,10 @@
>>=C2=A0 =C2=A0*=C2=A0 along with this program; if not, see <ht= tp://www.gnu.org/licenses/>.
>>=C2=A0 =C2=A0*/
>>
>> -#include <sys/types.h>
>> -#include <sys/time.h>
>> +#include "qemu/osdep.h"
>>=C2=A0 #include <sys/resource.h>
>>=C2=A0 #include <sys/sysctl.h>
>>
>> -#include "qemu/osdep.h"
>>=C2=A0 #include "qemu/help-texts.h"
>>=C2=A0 #include "qemu/units.h"
>>=C2=A0 #include "qemu/accel.h"
>> diff --git a/bsd-user/strace.c b/bsd-user/strace.c
>> index a77d10dd6b..96499751eb 100644
>> --- a/bsd-user/strace.c
>> +++ b/bsd-user/strace.c
>> @@ -20,7 +20,6 @@
>>=C2=A0 #include <sys/select.h>
>>=C2=A0 #include <sys/syscall.h>
>>=C2=A0 #include <sys/ioccom.h>
>> -#include <ctype.h>
>>
>>=C2=A0 #include "qemu.h"
>>
>> diff --git a/bsd-user/x86_64/signal.c b/bsd-user/x86_64/signal.c >> index c3875bc4c6..46cb865180 100644
>> --- a/bsd-user/x86_64/signal.c
>> +++ b/bsd-user/x86_64/signal.c
>> @@ -16,6 +16,7 @@
>>=C2=A0 =C2=A0*=C2=A0 along with this program; if not, see <ht= tp://www.gnu.org/licenses/>.
>>=C2=A0 =C2=A0*/
>>
>> +#include "qemu/osdep.h"
>>=C2=A0 #include "qemu.h"
>>
>>=C2=A0 /*
>> diff --git a/bsd-user/x86_64/target_arch_cpu.c
>> b/bsd-user/x86_64/target_arch_cpu.c
>> index be7bd10720..1d32f18907 100644
>> --- a/bsd-user/x86_64/target_arch_cpu.c
>> +++ b/bsd-user/x86_64/target_arch_cpu.c
>> @@ -17,9 +17,8 @@
>>=C2=A0 =C2=A0*=C2=A0 along with this program; if not, see <ht= tp://www.gnu.org/licenses/>.
>>=C2=A0 =C2=A0*/
>>
>> -#include <sys/types.h>
>> -
>>=C2=A0 #include "qemu/osdep.h"
>> +
>>=C2=A0 #include "cpu.h"
>>=C2=A0 #include "qemu.h"
>>=C2=A0 #include "qemu/timer.h"
>>
>
> I suppose these are fine. How do I run the cleanup script? I have 2x t= he
> number of files not upstream in the bsd-user fork that I'd like to= cleanup
> as well and they are likely a bigger mess and I'll just upstream t= hem in
> the messy state unless I understand how to keep the neat :).

I used

=C2=A0 =C2=A0 $ scripts/clean-includes --check-dup-head --all

Which resulted in a big mess I didn't dare to submit for review :)=C2= =A0 So I
split it up.=C2=A0 Easiest way was to identify useful sets of files, add files that include headers from the set, transitively, then run

=C2=A0 =C2=A0 $ scripts/clean-includes FILES...

--check-dup-head reports possible duplicate inclusions.=C2=A0 It is prone t= o
false positives.=C2=A0 That's why it merely reports them.=C2=A0 You may= want to
not use it for now.

There's a big usage comment at the beginning of the script.

Hope this helps!

It does. After your ch= anges land, I'll merge, and run this on the branch. I have a few change= s queued up, and have been contemplating changes to my upstreaming workflow= to speed the process along...

So I'm happy wi= th it. Thanks for the cleanup and the time to answer my questions.

Reviewed-by: Warner Losh <imp@bsdimp.com>

Warner=C2=A0
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No relevant changes made in the other 6 patches. Patches are based on riscv-to-apply.next. Changes from v2: - patch 3 (new): - add a specific function to retrieve the FDT addr of the Icicle Kit machine - v2 link: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg03366.html Daniel Henrique Barboza (7): hw/riscv/boot.c: calculate fdt size after fdt_pack() hw/riscv: split fdt address calculation from fdt load hw/riscv/microchip_pfsoc.c: add an Icicle Kit fdt address function hw/riscv: simplify riscv_compute_fdt_addr() hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' hw/riscv/boot.c | 42 +++- hw/riscv/microchip_pfsoc.c | 48 +++- hw/riscv/sifive_u.c | 7 +- hw/riscv/spike.c | 24 +- hw/riscv/virt.c | 468 +++++++++++++++++++------------------ include/hw/riscv/boot.h | 3 +- 6 files changed, 331 insertions(+), 261 deletions(-) -- 2.39.0 From MAILER-DAEMON Thu Jan 19 14:20:49 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIaSv-0002Sf-IR for mharc-qemu-riscv@gnu.org; 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Thu, 19 Jan 2023 11:20:32 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v3 2/7] hw/riscv: split fdt address calculation from fdt load Date: Thu, 19 Jan 2023 16:17:23 -0300 Message-Id: <20230119191728.622081-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230119191728.622081-1-dbarboza@ventanamicro.com> References: <20230119191728.622081-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::36; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x36.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 19:20:39 -0000 A common trend in other archs is to calculate the fdt address, which is usually straightforward, and then calling a function that loads the fdt/dtb by using that address. riscv_load_fdt() is doing a bit too much in comparison. It's calculating the fdt address via an elaborated heuristic to put the FDT at the bottom of DRAM, and "bottom of DRAM" will vary across boards and configurations, then it's actually loading the fdt, and finally it's returning the fdt address used to the caller. Reduce the existing complexity of riscv_load_fdt() by splitting its code into a new function, riscv_compute_fdt_addr(), that will take care of all fdt address logic. riscv_load_fdt() can then be a simple function that just loads a fdt at the given fdt address. We're also taken the opportunity to clarify the intentions and assumptions made by these functions. riscv_load_fdt() is receiving a hwaddr as fdt_addr because the Polarfire SoC will have an exclusive compute fdt address function that can return 64 bit addresses. Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 33 +++++++++++++++++++++++++-------- hw/riscv/microchip_pfsoc.c | 6 ++++-- hw/riscv/sifive_u.c | 7 ++++--- hw/riscv/spike.c | 6 +++--- hw/riscv/virt.c | 7 ++++--- include/hw/riscv/boot.h | 3 ++- 6 files changed, 42 insertions(+), 20 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index dc14d8cd14..13b5ce2d49 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -249,9 +249,21 @@ void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) } } -uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) +/* + * The FDT should be put at the farthest point possible to + * avoid overwriting it with the kernel/initrd. + * + * This function makes an assumption that the DRAM is + * contiguous. It also cares about 32-bit systems and + * will limit fdt_addr to be addressable by them even for + * 64-bit CPUs. + * + * The FDT is fdt_packed() during the calculation. + */ +uint32_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size, + void *fdt) { - uint64_t temp, fdt_addr; + uint64_t temp; hwaddr dram_end = dram_base + mem_size; int ret = fdt_pack(fdt); int fdtsize; @@ -272,11 +284,18 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) * end of dram or 3GB whichever is lesser. */ temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; - fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); - ret = fdt_pack(fdt); - /* Should only fail if we've built a corrupted tree */ - g_assert(ret == 0); + return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); +} + +/* + * 'fdt_addr' is received as hwaddr because boards might put + * the FDT beyond 32-bit addressing boundary. + */ +void riscv_load_fdt(hwaddr fdt_addr, void *fdt) +{ + uint32_t fdtsize = fdt_totalsize(fdt); + /* copy in the device tree */ qemu_fdt_dumpdtb(fdt, fdtsize); @@ -284,8 +303,6 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) &address_space_memory); qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize)); - - return fdt_addr; } void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 82ae5e7023..dcdbc2cac3 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -641,8 +641,10 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) } /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base, + machine->ram_size, machine->fdt); + riscv_load_fdt(fdt_load_addr, machine->fdt); + /* Load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr, memmap[MICROCHIP_PFSOC_ENVM_DATA].base, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 2fb6ee231f..626d4dc2f3 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -616,9 +616,10 @@ static void sifive_u_machine_init(MachineState *machine) kernel_entry = 0; } - /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, + machine->ram_size, machine->fdt); + riscv_load_fdt(fdt_load_addr, machine->fdt); + if (!riscv_is_32bit(&s->soc.u_cpus)) { start_addr_hi32 = (uint64_t)start_addr >> 32; } diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index badc11ec43..88b9fdfc36 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -324,9 +324,9 @@ static void spike_board_init(MachineState *machine) kernel_entry = 0; } - /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, + machine->ram_size, machine->fdt); + riscv_load_fdt(fdt_load_addr, machine->fdt); /* load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4a11b4b010..67c8a01e1d 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1300,9 +1300,10 @@ static void virt_machine_done(Notifier *notifier, void *data) start_addr = virt_memmap[VIRT_FLASH].base; } - /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, + machine->ram_size, machine->fdt); + riscv_load_fdt(fdt_load_addr, machine->fdt); + /* load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, virt_memmap[VIRT_MROM].base, diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index f94653a09b..c529ed2129 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -47,7 +47,8 @@ target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, symbol_fn_t sym_cb); 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Thu, 19 Jan 2023 11:20:30 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v3 1/7] hw/riscv/boot.c: calculate fdt size after fdt_pack() Date: Thu, 19 Jan 2023 16:17:22 -0300 Message-Id: <20230119191728.622081-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230119191728.622081-1-dbarboza@ventanamicro.com> References: <20230119191728.622081-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::34; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 19:20:39 -0000 fdt_pack() can change the fdt size, meaning that fdt_totalsize() can contain a now deprecated (bigger) value. Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 2594276223..dc14d8cd14 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -253,8 +253,13 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) { uint64_t temp, fdt_addr; hwaddr dram_end = dram_base + mem_size; - int ret, fdtsize = fdt_totalsize(fdt); + int ret = fdt_pack(fdt); + int fdtsize; + /* Should only fail if we've built a corrupted tree */ + g_assert(ret == 0); + + fdtsize = fdt_totalsize(fdt); if (fdtsize <= 0) { error_report("invalid device-tree"); exit(1); -- 2.39.0 From MAILER-DAEMON Thu Jan 19 14:20:55 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIaSz-0002Ua-QF for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 14:20:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIaSn-0002Md-30 for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 14:20:41 -0500 Received: from mail-oa1-x41.google.com ([2001:4860:4864:20::41]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIaSk-0007Yq-M6 for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 14:20:40 -0500 Received: by mail-oa1-x41.google.com with SMTP id 586e51a60fabf-142b72a728fso3688087fac.9 for ; Thu, 19 Jan 2023 11:20:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VXD8ZPUYsyRTQukgddfHyr53eMY4QsmB4t6z8+0bMqY=; b=ZkVT2pO8y6++jBhPH8xLANQt/wm0qI60fGX9+0pvOfIDamlZGgjOmzjGhe0Bqat93h 7gciBfoqsBQljKZD/RMoIvZINc2ckbzuuqMh/uMj/vZ1pEyg9CHyVVrT/cB2KK5l5OUh bvFx2AbkjKmONHaAtIBn1drW1nr6Z8r8vhJ7s7gVkMC+JUyPemLv5Fr3t2TXRdbrh8A6 QV0J8WHoyCpkit+gKBoPymALjP8ouSwHVtSmXV2mpF/k00BVia81ZhsrBPLf5x/66EQH dOJWzZXVuNiFW3OjWEuQICZLysOSNJlEWKEIje5yDu23ifz7pd/1/usYZOVzx/Z9wDLm I2Kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VXD8ZPUYsyRTQukgddfHyr53eMY4QsmB4t6z8+0bMqY=; b=bLixH7SgpzSI1TVMT+bYGg0ZqXTYD7F1D5hKdnOFb41iIVUznbyxBuj7cOQDy5TMk8 Y5aehVnHEnJ/3r0627uwH131bf1BPPw1c+G1RYyS8xabIiQbYnvCCz6v3Msn4DlXxWA6 C4MBoXwqVfzHpQsr/WRn/CUt4hb4/fq2CKcEieNJBIlT3C/+wHiD3X3jMfZvnKTS8pvh GEmf1S6IgECDhY0kcWbZoyx8xG8OgSZFRkMZZx/3sSiN4WnPLq8qTlmZHWbCGoXTTPqg 3flsIFWzvYEjfe3LDchNCC03w2++PY2LSHTG/6/AFVZVOVUE1+bWkgi4iEAd9awJwHZr JDYA== X-Gm-Message-State: AFqh2krGSfA657KNcocgcSnN1YjmYrWCJcgZZLuHq9SpA9J+5kDB2MSW 3exgnw0EM6mg+VnQOkvvO9m2Bw== X-Google-Smtp-Source: AMrXdXtDLprwWWgQkTCbPkpnVVL0hk9GE/w/pKJhtgWgKa0pIhqmSghviR9mz/5LYffnHNBsqB0e3g== X-Received: by 2002:a05:6870:6c1a:b0:15f:5fd:b91f with SMTP id na26-20020a0568706c1a00b0015f05fdb91fmr6525019oab.50.1674156035052; Thu, 19 Jan 2023 11:20:35 -0800 (PST) Received: from grind.dc1.ventanamicro.com ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id t9-20020a056870f20900b0015f193c86d2sm9001128oao.6.2023.01.19.11.20.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 11:20:34 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v3 3/7] hw/riscv/microchip_pfsoc.c: add an Icicle Kit fdt address function Date: Thu, 19 Jan 2023 16:17:24 -0300 Message-Id: <20230119191728.622081-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230119191728.622081-1-dbarboza@ventanamicro.com> References: <20230119191728.622081-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::41; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x41.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 19:20:49 -0000 The Icicle Kit board works with 2 distinct RAM banks that are separated by a gap. We have a lower bank with 1GiB size, a gap follows, then at 64GiB the high memory starts. MachineClass::default_ram_size is set to 1.5Gb and machine_init() is enforcing it as minimal RAM size, meaning that there we'll always have at least 512 MiB in the Hi RAM area, and that the FDT will be located there all the time. riscv_compute_fdt_addr() can't handle this setup because it assumes that the RAM is always contiguous. It's also returning an uint32_t because it's enforcing that fdt address is sitting on an area that is addressable to 32 bit CPUs, but 32 bits won't be enough to point to the Hi area of the Icicle Kit RAM (and to its FDT itself). Create a new function called microchip_compute_fdt_addr() that is able to deal with all these details that are particular to the Icicle Kit. Ditch riscv_compute_fdt_addr() and use it instead. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/microchip_pfsoc.c | 46 +++++++++++++++++++++++++++++++++++--- 1 file changed, 43 insertions(+), 3 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index dcdbc2cac3..9b829e4d1a 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -54,6 +54,8 @@ #include "sysemu/device_tree.h" #include "sysemu/sysemu.h" +#include + /* * The BIOS image used by this machine is called Hart Software Services (HSS). * See https://github.com/polarfire-soc/hart-software-services @@ -513,6 +515,46 @@ static void microchip_pfsoc_soc_register_types(void) type_init(microchip_pfsoc_soc_register_types) +static hwaddr microchip_compute_fdt_addr(MachineState *ms) +{ + const MemMapEntry *memmap = microchip_pfsoc_memmap; + hwaddr mem_low_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size; + hwaddr mem_high_size, fdt_base; + int ret = fdt_pack(ms->fdt); + int fdtsize; + + /* Should only fail if we've built a corrupted tree */ + g_assert(ret == 0); + + fdtsize = fdt_totalsize(ms->fdt); + if (fdtsize <= 0) { + error_report("invalid device-tree"); + exit(1); + } + + /* + * microchip_icicle_kit_machine_init() does a validation + * that guarantees that ms->ram_size is always greater + * than mem_low_size and that mem_high_size will be + * at least 512MiB. + * + * This also means that our fdt_addr will be based + * on the starting address of the HI DRAM block. + */ + mem_high_size = ms->ram_size - mem_low_size; + fdt_base = memmap[MICROCHIP_PFSOC_DRAM_HI].base; + + /* + * In theory we could copy riscv_compute_fdt_addr() + * and put the FDT capped at maximum 3Gb from fdt_base, + * but fdt_base is set at 0x1000000000 (64GiB). We + * make the assumption here that the OS is ready to + * handle the FDT, 2MB aligned, at the very end of + * the available RAM. + */ + return QEMU_ALIGN_DOWN(fdt_base + mem_high_size - fdtsize, 2 * MiB); +} + static void microchip_icicle_kit_machine_init(MachineState *machine) { MachineClass *mc = MACHINE_GET_CLASS(machine); @@ -640,9 +682,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) "bootargs", machine->kernel_cmdline); } - /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base, - machine->ram_size, machine->fdt); + fdt_load_addr = microchip_compute_fdt_addr(machine); riscv_load_fdt(fdt_load_addr, machine->fdt); /* Load the reset vector */ -- 2.39.0 From MAILER-DAEMON Thu Jan 19 14:20:56 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIaT1-0002VE-Oq for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 14:20:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIaSv-0002S8-Pb for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 14:20:49 -0500 Received: from mail-oa1-x29.google.com ([2001:4860:4864:20::29]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIaSp-0007ef-Do for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 14:20:46 -0500 Received: by mail-oa1-x29.google.com with SMTP id 586e51a60fabf-15bb8ec196aso3748517fac.3 for ; Thu, 19 Jan 2023 11:20:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9RxUOPUtG+Yi/MoUstTaqusMDk90ecIBy4eZX2O9y+I=; b=hTpqlWcFiBFRlsQ+YdZRV5tkeBnTq4N4vbyByhxe2LiUzLYlJBag+CQ1bYeVgf+zHS UXmxTHaIg3JNdIZRVc70DmukiwDN+L8Or8rHxlPVIILD1DZO0QGibHgtwdgsAEDtKXdf 0n1MuDX0TWnmY9ie9tQkVNbntUJuB+1ISEE3tCn4aKoT7TndRg8PMDuT+qTtPnw3ez2E 5Kj54kY4LLkIQw7jYk62XzYbmP1BTMvRUHLI+ouzOg84VXudXoBDEVc8cnpEbaVgiheF +ynqbKfc2wHu/JLvQ1j9htZ+TMrpouhbF55dyFCOBgCrMDVSxKUP1KXauWG6yHn1uThA SbCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9RxUOPUtG+Yi/MoUstTaqusMDk90ecIBy4eZX2O9y+I=; b=sVE0XkmgoXk/p2c1TBwLqnNuxKaArZ7TZUtfNI1hhBjhTr6plptaqu45txmxFBfUAd 25CKzyDOJr6g11MnKNTt5hRbs/49IiZSCX9zQp2EdmdB0SmGTfBh6k8y9hbMK/tbEiLQ OxhPU7AO36SxYHuzHOoCxC/Jxpw7leTJj7FLDEw0bJRYRQ2HY0fGdtpBQ5ykS8xJF0pi zx+s20TKso6RBH8IWErbJWsHAB5vnsTRG/0tHG6OlQn394xehhQcakKhJoS3En6ZfOhW Cc+SNvFJ6qoOLwFZfFnaV7aJLE2cXtdmgVNrY2I/NiqOnLy+qVgQo2HzNllCI/wXMKGu txBA== X-Gm-Message-State: AFqh2ko5OWNJIGAwaPggSMyr0o/6DJDCIaZ+lzLYqughlbcLBqZKJkgn 9hOzRRN3D1Ra90tK+eSIeRT/0A== X-Google-Smtp-Source: AMrXdXsaGKvW67FWZBPQb0p7hMwh0eRRCHyYXdWrlAAaYPj8f73atSBBm9WVsROpDTw4P9TzyJsLcQ== X-Received: by 2002:a05:6870:b14c:b0:15e:d25e:6d18 with SMTP id a12-20020a056870b14c00b0015ed25e6d18mr7639931oal.12.1674156042131; Thu, 19 Jan 2023 11:20:42 -0800 (PST) Received: from grind.dc1.ventanamicro.com ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id t9-20020a056870f20900b0015f193c86d2sm9001128oao.6.2023.01.19.11.20.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 11:20:41 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 6/7] hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' Date: Thu, 19 Jan 2023 16:17:27 -0300 Message-Id: <20230119191728.622081-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230119191728.622081-1-dbarboza@ventanamicro.com> References: <20230119191728.622081-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::29; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 19:20:50 -0000 We have a convention in other QEMU boards/archs to name MachineState pointers as either 'machine' or 'ms'. MachineClass pointers are usually called 'mc'. The 'virt' RISC-V machine has a lot of instances where MachineState pointers are named 'mc'. There is nothing wrong with that, but we gain more compatibility with the rest of the QEMU code base, and easier reviews, if we follow QEMU conventions. Rename all 'mc' MachineState pointers to 'ms'. This is a very tedious and mechanical patch that was produced by doing the following: - find/replace all 'MachineState *mc' to 'MachineState *ms'; - find/replace all 'mc->fdt' to 'ms->fdt'; - find/replace all 'mc->smp.cpus' to 'ms->smp.cpus'; - replace any remaining occurrences of 'mc' that the compiler complained about. Suggested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 434 ++++++++++++++++++++++++------------------------ 1 file changed, 217 insertions(+), 217 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 1119f4ba22..7bb71ace58 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -227,7 +227,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, { int cpu; uint32_t cpu_phandle; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); char *name, *cpu_name, *core_name, *intc_name; bool is_32_bit = riscv_is_32bit(&s->soc[0]); @@ -236,40 +236,40 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); - qemu_fdt_add_subnode(mc->fdt, cpu_name); + qemu_fdt_add_subnode(ms->fdt, cpu_name); if (riscv_feature(&s->soc[socket].harts[cpu].env, RISCV_FEATURE_MMU)) { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", + qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); } else { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", + qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", "riscv,none"); } name = riscv_isa_string(&s->soc[socket].harts[cpu]); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); + qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name); g_free(name); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv"); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay"); - qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", + qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); + qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); + qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", s->soc[socket].hartid_base + cpu); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, cpu_name, socket); - qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); + qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); + riscv_socket_fdt_write_id(ms, cpu_name, socket); + qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); intc_phandles[cpu] = (*phandle)++; intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); - qemu_fdt_add_subnode(mc->fdt, intc_name); - qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", + qemu_fdt_add_subnode(ms->fdt, intc_name); + qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", intc_phandles[cpu]); - qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", + qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", "riscv,cpu-intc"); - qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); + qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); core_name = g_strdup_printf("%s/core%d", clust_name, cpu); - qemu_fdt_add_subnode(mc->fdt, core_name); - qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle); + qemu_fdt_add_subnode(ms->fdt, core_name); + qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); g_free(core_name); g_free(intc_name); @@ -282,16 +282,16 @@ static void create_fdt_socket_memory(RISCVVirtState *s, { char *mem_name; uint64_t addr, size; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); - addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); - size = riscv_socket_mem_size(mc, socket); + addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); + size = riscv_socket_mem_size(ms, socket); mem_name = g_strdup_printf("/memory@%lx", (long)addr); - qemu_fdt_add_subnode(mc->fdt, mem_name); - qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", + qemu_fdt_add_subnode(ms->fdt, mem_name); + qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); - qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, mem_name, socket); + qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); + riscv_socket_fdt_write_id(ms, mem_name, socket); g_free(mem_name); } @@ -303,7 +303,7 @@ static void create_fdt_socket_clint(RISCVVirtState *s, char *clint_name; uint32_t *clint_cells; unsigned long clint_addr; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); static const char * const clint_compat[2] = { "sifive,clint0", "riscv,clint0" }; @@ -319,15 +319,15 @@ static void create_fdt_socket_clint(RISCVVirtState *s, clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); - qemu_fdt_add_subnode(mc->fdt, clint_name); - qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible", + qemu_fdt_add_subnode(ms->fdt, clint_name); + qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", (char **)&clint_compat, ARRAY_SIZE(clint_compat)); - qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); - qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, clint_name, socket); + riscv_socket_fdt_write_id(ms, clint_name, socket); g_free(clint_name); g_free(clint_cells); @@ -344,7 +344,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, uint32_t *aclint_mswi_cells; uint32_t *aclint_sswi_cells; uint32_t *aclint_mtimer_cells; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); @@ -363,16 +363,16 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); name = g_strdup_printf("/soc/mswi@%lx", addr); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-mswi"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", aclint_mswi_cells, aclint_cells_size); - qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, name, socket); + qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); + riscv_socket_fdt_write_id(ms, name, socket); g_free(name); } @@ -386,33 +386,33 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; } name = g_strdup_printf("/soc/mtimer@%lx", addr); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-mtimer"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 0x0, RISCV_ACLINT_DEFAULT_MTIME); - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", aclint_mtimer_cells, aclint_cells_size); - riscv_socket_fdt_write_id(mc, name, socket); + riscv_socket_fdt_write_id(ms, name, socket); g_free(name); if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { addr = memmap[VIRT_ACLINT_SSWI].base + (memmap[VIRT_ACLINT_SSWI].size * socket); name = g_strdup_printf("/soc/sswi@%lx", addr); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-sswi"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", aclint_sswi_cells, aclint_cells_size); - qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, name, socket); + qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); + riscv_socket_fdt_write_id(ms, name, socket); g_free(name); } @@ -430,7 +430,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s, char *plic_name; uint32_t *plic_cells; unsigned long plic_addr; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); static const char * const plic_compat[2] = { "sifive,plic-1.0.0", "riscv,plic0" }; @@ -456,27 +456,27 @@ static void create_fdt_socket_plic(RISCVVirtState *s, plic_phandles[socket] = (*phandle)++; plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); - qemu_fdt_add_subnode(mc->fdt, plic_name); - qemu_fdt_setprop_cell(mc->fdt, plic_name, + qemu_fdt_add_subnode(ms->fdt, plic_name); + qemu_fdt_setprop_cell(ms->fdt, plic_name, "#interrupt-cells", FDT_PLIC_INT_CELLS); - qemu_fdt_setprop_cell(mc->fdt, plic_name, + qemu_fdt_setprop_cell(ms->fdt, plic_name, "#address-cells", FDT_PLIC_ADDR_CELLS); - qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", + qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", (char **)&plic_compat, ARRAY_SIZE(plic_compat)); - qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); - qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", + qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", VIRT_IRQCHIP_NUM_SOURCES - 1); - riscv_socket_fdt_write_id(mc, plic_name, socket); - qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", + riscv_socket_fdt_write_id(ms, plic_name, socket); + qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", plic_phandles[socket]); if (!socket) { - platform_bus_add_all_fdt_nodes(mc->fdt, plic_name, + platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, memmap[VIRT_PLATFORM_BUS].base, memmap[VIRT_PLATFORM_BUS].size, VIRT_PLATFORM_BUS_IRQ); @@ -504,18 +504,18 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, { int cpu, socket; char *imsic_name; - MachineState *mc = MACHINE(s); - int socket_count = riscv_socket_count(mc); + MachineState *ms = MACHINE(s); + int socket_count = riscv_socket_count(ms); uint32_t imsic_max_hart_per_socket, imsic_guest_bits; uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; *msi_m_phandle = (*phandle)++; *msi_s_phandle = (*phandle)++; - imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2); + imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); imsic_regs = g_new0(uint32_t, socket_count * 4); /* M-level IMSIC node */ - for (cpu = 0; cpu < mc->smp.cpus; cpu++) { + for (cpu = 0; cpu < ms->smp.cpus; cpu++) { imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); } @@ -534,35 +534,35 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, } imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)memmap[VIRT_IMSIC_M].base); - qemu_fdt_add_subnode(mc->fdt, imsic_name); - qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", + qemu_fdt_add_subnode(ms->fdt, imsic_name); + qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", FDT_IMSIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", - imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); - qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", + imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); + qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, socket_count * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); if (socket_count > 1) { - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", imsic_num_bits(socket_count)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); } - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle); + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phandle); g_free(imsic_name); /* S-level IMSIC node */ - for (cpu = 0; cpu < mc->smp.cpus; cpu++) { + for (cpu = 0; cpu < ms->smp.cpus; cpu++) { imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); } @@ -583,34 +583,34 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, } imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)memmap[VIRT_IMSIC_S].base); - qemu_fdt_add_subnode(mc->fdt, imsic_name); - qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", + qemu_fdt_add_subnode(ms->fdt, imsic_name); + qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", FDT_IMSIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", - imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); - qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", + imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); + qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, socket_count * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); if (imsic_guest_bits) { - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", imsic_guest_bits); } if (socket_count > 1) { - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", imsic_num_bits(socket_count)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); } - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle); + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_s_phandle); g_free(imsic_name); g_free(imsic_regs); @@ -629,7 +629,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, char *aplic_name; uint32_t *aplic_cells; unsigned long aplic_addr; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); uint32_t aplic_m_phandle, aplic_s_phandle; aplic_m_phandle = (*phandle)++; @@ -644,28 +644,28 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_addr = memmap[VIRT_APLIC_M].base + (memmap[VIRT_APLIC_M].size * socket); aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); - qemu_fdt_add_subnode(mc->fdt, aplic_name); - qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, + qemu_fdt_add_subnode(ms->fdt, aplic_name); + qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#interrupt-cells", FDT_APLIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); if (s->aia_type == VIRT_AIA_TYPE_APLIC) { - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); } else { - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_m_phandle); } - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", VIRT_IRQCHIP_NUM_SOURCES); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", aplic_s_phandle); - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(mc, aplic_name, socket); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); + riscv_socket_fdt_write_id(ms, aplic_name, socket); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phandle); g_free(aplic_name); /* S-level APLIC node */ @@ -676,27 +676,27 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_addr = memmap[VIRT_APLIC_S].base + (memmap[VIRT_APLIC_S].size * socket); aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); - qemu_fdt_add_subnode(mc->fdt, aplic_name); - qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, + qemu_fdt_add_subnode(ms->fdt, aplic_name); + qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#interrupt-cells", FDT_APLIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); if (s->aia_type == VIRT_AIA_TYPE_APLIC) { - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); } else { - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_s_phandle); } - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(mc, aplic_name, socket); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); + riscv_socket_fdt_write_id(ms, aplic_name, socket); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_s_phandle); if (!socket) { - platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name, + platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, memmap[VIRT_PLATFORM_BUS].base, memmap[VIRT_PLATFORM_BUS].size, VIRT_PLATFORM_BUS_IRQ); @@ -711,13 +711,13 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, static void create_fdt_pmu(RISCVVirtState *s) { char *pmu_name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); RISCVCPU hart = s->soc[0].harts[0]; pmu_name = g_strdup_printf("/soc/pmu"); - qemu_fdt_add_subnode(mc->fdt, pmu_name); - qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu"); - riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name); + qemu_fdt_add_subnode(ms->fdt, pmu_name); + qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); + riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name); g_free(pmu_name); } @@ -731,26 +731,26 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, { char *clust_name; int socket, phandle_pos; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); uint32_t msi_m_phandle = 0, msi_s_phandle = 0; uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; - int socket_count = riscv_socket_count(mc); + int socket_count = riscv_socket_count(ms); - qemu_fdt_add_subnode(mc->fdt, "/cpus"); - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", + qemu_fdt_add_subnode(ms->fdt, "/cpus"); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); - qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); + qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); - intc_phandles = g_new0(uint32_t, mc->smp.cpus); + intc_phandles = g_new0(uint32_t, ms->smp.cpus); - phandle_pos = mc->smp.cpus; + phandle_pos = ms->smp.cpus; for (socket = (socket_count - 1); socket >= 0; socket--) { phandle_pos -= s->soc[socket].num_harts; clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); - qemu_fdt_add_subnode(mc->fdt, clust_name); + qemu_fdt_add_subnode(ms->fdt, clust_name); create_fdt_socket_cpus(s, socket, clust_name, phandle, &intc_phandles[phandle_pos]); @@ -776,7 +776,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, *msi_pcie_phandle = msi_s_phandle; } - phandle_pos = mc->smp.cpus; + phandle_pos = ms->smp.cpus; for (socket = (socket_count - 1); socket >= 0; socket--) { phandle_pos -= s->soc[socket].num_harts; @@ -807,7 +807,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, } } - riscv_socket_fdt_write_distance_matrix(mc); + riscv_socket_fdt_write_distance_matrix(ms); } static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, @@ -815,23 +815,23 @@ static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, { int i; char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); for (i = 0; i < VIRTIO_COUNT; i++) { name = g_strdup_printf("/soc/virtio_mmio@%lx", (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 0x0, memmap[VIRT_VIRTIO].size); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_virtio_phandle); if (s->aia_type == VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", VIRTIO_IRQ + i); } else { - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", VIRTIO_IRQ + i, 0x4); } g_free(name); @@ -843,29 +843,29 @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, uint32_t msi_pcie_phandle) { char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); name = g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS); - qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "pci-host-ecam-generic"); - qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci"); - qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0); - qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0, + qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); + qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); + qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); - qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0); + qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { - qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); } - qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0, + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); - qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges", + qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 1, FDT_PCI_RANGE_IOPORT, 2, 0, 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 1, FDT_PCI_RANGE_MMIO, @@ -875,7 +875,7 @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); - create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle); + create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); g_free(name); } @@ -884,39 +884,39 @@ static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, { char *name; uint32_t test_phandle; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); test_phandle = (*phandle)++; name = g_strdup_printf("/soc/test@%lx", (long)memmap[VIRT_TEST].base); - qemu_fdt_add_subnode(mc->fdt, name); + qemu_fdt_add_subnode(ms->fdt, name); { static const char * const compat[3] = { "sifive,test1", "sifive,test0", "syscon" }; - qemu_fdt_setprop_string_array(mc->fdt, name, "compatible", + qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", (char **)&compat, ARRAY_SIZE(compat)); } - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); - qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle); - test_phandle = qemu_fdt_get_phandle(mc->fdt, name); + qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); + test_phandle = qemu_fdt_get_phandle(ms->fdt, name); g_free(name); name = g_strdup_printf("/reboot"); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot"); - qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); - qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); - qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET); + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); + qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); + qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); g_free(name); name = g_strdup_printf("/poweroff"); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff"); - qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); - qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); - qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS); + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); + qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); + qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); g_free(name); } @@ -924,24 +924,24 @@ static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, uint32_t irq_mmio_phandle) { char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_UART0].base, 0x0, memmap[VIRT_UART0].size); - qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); if (s->aia_type == VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); } else { - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4); + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); } - qemu_fdt_add_subnode(mc->fdt, "/chosen"); - qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); + qemu_fdt_add_subnode(ms->fdt, "/chosen"); + qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); g_free(name); } @@ -949,20 +949,20 @@ static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, uint32_t irq_mmio_phandle) { char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "google,goldfish-rtc"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); if (s->aia_type == VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); } else { - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4); + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); } g_free(name); } @@ -970,68 +970,68 @@ static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) { char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; hwaddr flashbase = virt_memmap[VIRT_FLASH].base; name = g_strdup_printf("/flash@%" PRIx64, flashbase); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); - qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); + qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2, flashbase, 2, flashsize, 2, flashbase + flashsize, 2, flashsize); - qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); + qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); g_free(name); } static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) { char *nodename; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); hwaddr base = memmap[VIRT_FW_CFG].base; hwaddr size = memmap[VIRT_FW_CFG].size; nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); - qemu_fdt_add_subnode(mc->fdt, nodename); - qemu_fdt_setprop_string(mc->fdt, nodename, + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "qemu,fw-cfg-mmio"); - qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", + qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); - qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); + qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); g_free(nodename); } static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) { - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; uint8_t rng_seed[32]; - if (mc->dtb) { - mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); - if (!mc->fdt) { + if (ms->dtb) { + ms->fdt = load_device_tree(ms->dtb, &s->fdt_size); + if (!ms->fdt) { error_report("load_device_tree() failed"); exit(1); } } else { - mc->fdt = create_device_tree(&s->fdt_size); - if (!mc->fdt) { + ms->fdt = create_device_tree(&s->fdt_size); + if (!ms->fdt) { error_report("create_device_tree() failed"); exit(1); } } - qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu"); - qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio"); - qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2); - qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2); + qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); + qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); + qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); + qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); - qemu_fdt_add_subnode(mc->fdt, "/soc"); - qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0); - qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus"); - qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); - qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); + qemu_fdt_add_subnode(ms->fdt, "/soc"); + qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); + qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); + qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); + qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, @@ -1053,7 +1053,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) /* Pass seed to RNG */ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); - qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", + qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); } @@ -1106,14 +1106,14 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, return dev; } -static FWCfgState *create_fw_cfg(const MachineState *mc) +static FWCfgState *create_fw_cfg(const MachineState *ms) { hwaddr base = virt_memmap[VIRT_FW_CFG].base; FWCfgState *fw_cfg; fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, &address_space_memory); - fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); + fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); return fw_cfg; } -- 2.39.0 From MAILER-DAEMON Thu Jan 19 14:21:02 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIaT2-0002VW-MC for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 14:21:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIaSo-0002NA-Q5 for qemu-riscv@nongnu.org; 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Thu, 19 Jan 2023 11:20:39 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 5/7] hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() Date: Thu, 19 Jan 2023 16:17:26 -0300 Message-Id: <20230119191728.622081-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230119191728.622081-1-dbarboza@ventanamicro.com> References: <20230119191728.622081-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::31; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x31.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 19:20:49 -0000 riscv_socket_count() returns either ms->numa_state->num_nodes or 1 depending on NUMA support. In any case the value can be retrieved only once and used in the rest of the function. This will also alleviate the rename we're going to do next by reducing the instances of MachineState 'mc' inside hw/riscv/virt.c. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 2688410fc5..1119f4ba22 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -505,13 +505,14 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, int cpu, socket; char *imsic_name; MachineState *mc = MACHINE(s); + int socket_count = riscv_socket_count(mc); uint32_t imsic_max_hart_per_socket, imsic_guest_bits; uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; *msi_m_phandle = (*phandle)++; *msi_s_phandle = (*phandle)++; imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2); - imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4); + imsic_regs = g_new0(uint32_t, socket_count * 4); /* M-level IMSIC node */ for (cpu = 0; cpu < mc->smp.cpus; cpu++) { @@ -519,7 +520,7 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); } imsic_max_hart_per_socket = 0; - for (socket = 0; socket < riscv_socket_count(mc); socket++) { + for (socket = 0; socket < socket_count; socket++) { imsic_addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; @@ -545,14 +546,14 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, - riscv_socket_count(mc) * sizeof(uint32_t) * 4); + socket_count * sizeof(uint32_t) * 4); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); - if (riscv_socket_count(mc) > 1) { + if (socket_count > 1) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", - imsic_num_bits(riscv_socket_count(mc))); + imsic_num_bits(socket_count)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); } @@ -567,7 +568,7 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, } imsic_guest_bits = imsic_num_bits(s->aia_guests + 1); imsic_max_hart_per_socket = 0; - for (socket = 0; socket < riscv_socket_count(mc); socket++) { + for (socket = 0; socket < socket_count; socket++) { imsic_addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * @@ -594,18 +595,18 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, - riscv_socket_count(mc) * sizeof(uint32_t) * 4); + socket_count * sizeof(uint32_t) * 4); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); if (imsic_guest_bits) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits", imsic_guest_bits); } - if (riscv_socket_count(mc) > 1) { + if (socket_count > 1) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", - imsic_num_bits(riscv_socket_count(mc))); + imsic_num_bits(socket_count)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); } @@ -733,6 +734,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, MachineState *mc = MACHINE(s); uint32_t msi_m_phandle = 0, msi_s_phandle = 0; uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; + int socket_count = riscv_socket_count(mc); qemu_fdt_add_subnode(mc->fdt, "/cpus"); qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", @@ -744,7 +746,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, intc_phandles = g_new0(uint32_t, mc->smp.cpus); phandle_pos = mc->smp.cpus; - for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { + for (socket = (socket_count - 1); socket >= 0; socket--) { phandle_pos -= s->soc[socket].num_harts; clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); @@ -775,7 +777,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, } phandle_pos = mc->smp.cpus; - for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { + for (socket = (socket_count - 1); socket >= 0; socket--) { phandle_pos -= s->soc[socket].num_harts; if (s->aia_type == VIRT_AIA_TYPE_NONE) { @@ -790,7 +792,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, g_free(intc_phandles); - for (socket = 0; socket < riscv_socket_count(mc); socket++) { + for (socket = 0; socket < socket_count; socket++) { if (socket == 0) { *irq_mmio_phandle = xplic_phandles[socket]; *irq_virtio_phandle = xplic_phandles[socket]; @@ -1051,7 +1053,8 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) /* Pass seed to RNG */ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); - qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); + qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", + rng_seed, sizeof(rng_seed)); } static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, @@ -1328,9 +1331,10 @@ static void virt_machine_init(MachineState *machine) char *soc_name; DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; int i, base_hartid, hart_count; + int socket_count = riscv_socket_count(machine); /* Check socket count limit */ - if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { + if (VIRT_SOCKETS_MAX < socket_count) { error_report("number of sockets/nodes should be less than %d", VIRT_SOCKETS_MAX); exit(1); @@ -1338,7 +1342,7 @@ static void virt_machine_init(MachineState *machine) /* Initialize sockets */ mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; - for (i = 0; i < riscv_socket_count(machine); i++) { + for (i = 0; i < socket_count; i++) { if (!riscv_socket_check_hartids(machine, i)) { error_report("discontinuous hartids in socket%d", i); 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Thu, 19 Jan 2023 11:20:44 -0800 (PST) Received: from grind.dc1.ventanamicro.com ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id t9-20020a056870f20900b0015f193c86d2sm9001128oao.6.2023.01.19.11.20.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 11:20:44 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v3 7/7] hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' Date: Thu, 19 Jan 2023 16:17:28 -0300 Message-Id: <20230119191728.622081-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230119191728.622081-1-dbarboza@ventanamicro.com> References: <20230119191728.622081-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::2b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 19:20:53 -0000 Follow the QEMU convention of naming MachineState pointers as 'ms' by renaming the instances where we're calling it 'mc'. Suggested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza --- hw/riscv/spike.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index afd581436b..222fde0c5c 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -56,7 +56,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, uint64_t addr, size; unsigned long clint_addr; int cpu, socket; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); uint32_t *clint_cells; uint32_t cpu_phandle, intc_phandle, phandle = 1; char *name, *mem_name, *clint_name, *clust_name; @@ -65,7 +65,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, "sifive,clint0", "riscv,clint0" }; - fdt = mc->fdt = create_device_tree(&fdt_size); + fdt = ms->fdt = create_device_tree(&fdt_size); if (!fdt) { error_report("create_device_tree() failed"); exit(1); @@ -96,7 +96,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); - for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { + for (socket = (riscv_socket_count(ms) - 1); socket >= 0; socket--) { clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); qemu_fdt_add_subnode(fdt, clust_name); @@ -121,7 +121,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, qemu_fdt_setprop_cell(fdt, cpu_name, "reg", s->soc[socket].hartid_base + cpu); qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, cpu_name, socket); + riscv_socket_fdt_write_id(ms, cpu_name, socket); qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); @@ -147,14 +147,14 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, g_free(cpu_name); } - addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket); - size = riscv_socket_mem_size(mc, socket); + addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(ms, socket); + size = riscv_socket_mem_size(ms, socket); mem_name = g_strdup_printf("/memory@%lx", (long)addr); qemu_fdt_add_subnode(fdt, mem_name); qemu_fdt_setprop_cells(fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, mem_name, socket); + riscv_socket_fdt_write_id(ms, mem_name, socket); g_free(mem_name); clint_addr = memmap[SPIKE_CLINT].base + @@ -167,14 +167,14 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, clint_name, socket); + riscv_socket_fdt_write_id(ms, clint_name, socket); g_free(clint_name); g_free(clint_cells); g_free(clust_name); } - riscv_socket_fdt_write_distance_matrix(mc); + riscv_socket_fdt_write_distance_matrix(ms); qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); 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Thu, 19 Jan 2023 11:20:37 -0800 (PST) Received: from grind.dc1.ventanamicro.com ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id t9-20020a056870f20900b0015f193c86d2sm9001128oao.6.2023.01.19.11.20.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 11:20:36 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v3 4/7] hw/riscv: simplify riscv_compute_fdt_addr() Date: Thu, 19 Jan 2023 16:17:25 -0300 Message-Id: <20230119191728.622081-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230119191728.622081-1-dbarboza@ventanamicro.com> References: <20230119191728.622081-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::2c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 19:20:41 -0000 All callers are using attributes from the MachineState object. Use a pointer to it instead of passing dram_size (which is always machine->ram_size) and fdt (always machine->fdt). Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 6 +++--- hw/riscv/sifive_u.c | 4 ++-- hw/riscv/spike.c | 4 ++-- hw/riscv/virt.c | 3 +-- include/hw/riscv/boot.h | 2 +- 5 files changed, 9 insertions(+), 10 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 13b5ce2d49..3027457042 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -260,11 +260,11 @@ void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) * * The FDT is fdt_packed() during the calculation. */ -uint32_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size, - void *fdt) +uint32_t riscv_compute_fdt_addr(MachineState *machine, hwaddr dram_base) { + void *fdt = machine->fdt; uint64_t temp; - hwaddr dram_end = dram_base + mem_size; + hwaddr dram_end = dram_base + machine->ram_size; int ret = fdt_pack(fdt); int fdtsize; diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 626d4dc2f3..ebfddf161d 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -616,8 +616,8 @@ static void sifive_u_machine_init(MachineState *machine) kernel_entry = 0; } - fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(machine, + memmap[SIFIVE_U_DEV_DRAM].base); riscv_load_fdt(fdt_load_addr, machine->fdt); if (!riscv_is_32bit(&s->soc.u_cpus)) { diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 88b9fdfc36..afd581436b 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -324,8 +324,8 @@ static void spike_board_init(MachineState *machine) kernel_entry = 0; } - fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(machine, + memmap[SPIKE_DRAM].base); riscv_load_fdt(fdt_load_addr, machine->fdt); /* load the reset vector */ diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 67c8a01e1d..2688410fc5 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1300,8 +1300,7 @@ static void virt_machine_done(Notifier *notifier, void *data) start_addr = virt_memmap[VIRT_FLASH].base; } - fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(machine, memmap[VIRT_DRAM].base); riscv_load_fdt(fdt_load_addr, machine->fdt); /* load the reset vector */ diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index c529ed2129..79d3bf268b 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -47,7 +47,7 @@ target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, symbol_fn_t sym_cb); void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); -uint32_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, void *fdt); +uint32_t riscv_compute_fdt_addr(MachineState *machine, hwaddr dram_start); void riscv_load_fdt(hwaddr fdt_addr, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr, -- 2.39.0 From MAILER-DAEMON Thu Jan 19 14:39:50 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIalJ-0005uk-Nj for mharc-qemu-riscv@gnu.org; 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Thu, 19 Jan 2023 11:39:41 -0800 (PST) Message-ID: <91833080-784f-06cf-70ae-67936040ab78@linaro.org> Date: Thu, 19 Jan 2023 20:39:40 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v3 4/7] hw/riscv: simplify riscv_compute_fdt_addr() Content-Language: en-US To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com References: <20230119191728.622081-1-dbarboza@ventanamicro.com> <20230119191728.622081-5-dbarboza@ventanamicro.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230119191728.622081-5-dbarboza@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=philmd@linaro.org; helo=mail-ej1-x632.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.094, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 19:39:48 -0000 On 19/1/23 20:17, Daniel Henrique Barboza wrote: > All callers are using attributes from the MachineState object. Use a > pointer to it instead of passing dram_size (which is always > machine->ram_size) and fdt (always machine->fdt). > > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/boot.c | 6 +++--- > hw/riscv/sifive_u.c | 4 ++-- > hw/riscv/spike.c | 4 ++-- > hw/riscv/virt.c | 3 +-- > include/hw/riscv/boot.h | 2 +- > 5 files changed, 9 insertions(+), 10 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Thu Jan 19 14:57:17 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIb2C-00049U-UE for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 14:57:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIb2B-00048v-G5; Thu, 19 Jan 2023 14:57:15 -0500 Received: from ams.source.kernel.org ([2604:1380:4601:e00::1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIb25-0000Th-5H; Thu, 19 Jan 2023 14:57:14 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 21DDDB82699; Thu, 19 Jan 2023 19:56:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CF8D3C433D2; Thu, 19 Jan 2023 19:56:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1674158217; bh=BmWTeRUIusd8OEFXHTJuzYETV+qmAT4J8HYVZub7ViY=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=K8lhsd7alaACglghdd1I9y4yPe7IvAzSXQc8QssGw+5JOfnkzpORBDCy5bC52DQAc 69W0intb65QhW2B/5J7r/jEqnhMwUK6jhTGpjRtWrL4gDkY0tFU52+lymQtyIBx2QI X1v32S/jnwu9qHXpN6mkMtRXpCOdHtoopItBnYTNV1Ogal3Pb85qwKI3uzXIcb/VKB s5FXSd7b0gtvXTsI7ghyBPKQ4jAuK5S0Z3xkl5Y0CfNQ8tN0q2vJ0f4F1sRlAZm+ht d33NOLgp4j+uLVBfAA6WGHDAz+QiwTdsstvyZROwpivhPMRv4Kxzm00wlIfvRW1Z0e z6meFC+wZZqlw== Date: Thu, 19 Jan 2023 19:56:54 +0000 From: Conor Dooley To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Subject: Re: [PATCH v3 3/7] hw/riscv/microchip_pfsoc.c: add an Icicle Kit fdt address function Message-ID: References: <20230119191728.622081-1-dbarboza@ventanamicro.com> <20230119191728.622081-4-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="K/ySGvJLhH//+QXY" Content-Disposition: inline In-Reply-To: <20230119191728.622081-4-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2604:1380:4601:e00::1; envelope-from=conor@kernel.org; helo=ams.source.kernel.org X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 19:57:15 -0000 --K/ySGvJLhH//+QXY Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hey! On Thu, Jan 19, 2023 at 04:17:24PM -0300, Daniel Henrique Barboza wrote: > The Icicle Kit board works with 2 distinct RAM banks that are separated > by a gap. We have a lower bank with 1GiB size, a gap follows, > then at 64GiB the high memory starts. >=20 > MachineClass::default_ram_size is set to 1.5Gb and machine_init() is > enforcing it as minimal RAM size, meaning that there we'll always have > at least 512 MiB in the Hi RAM area, and that the FDT will be located > there all the time. >=20 > riscv_compute_fdt_addr() can't handle this setup because it assumes that > the RAM is always contiguous. It's also returning an uint32_t because > it's enforcing that fdt address is sitting on an area that is addressable > to 32 bit CPUs, but 32 bits won't be enough to point to the Hi area of > the Icicle Kit RAM (and to its FDT itself). >=20 > Create a new function called microchip_compute_fdt_addr() that is able > to deal with all these details that are particular to the Icicle Kit. > Ditch riscv_compute_fdt_addr() and use it instead. Hmm, this breaks boot for me in what is a valid configuration for Icicle/PolarFire SoC which was previously functional in QEMU. I'll try and write another email explaining things in more detail, but in case I do not have time to get that done in the next day or two I figured I should let you know. Thanks, Conor. --K/ySGvJLhH//+QXY Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY8mghgAKCRB4tDGHoIJi 0qEoAP0YFV+8XdaBNd18juhI/NqNzhfVrN0PBsbJ0lsKIEEEpgEAmDvrLApoVrZA hERQ/0xWHHE+1sn/epqZVHWbJPctdgc= =lSRT -----END PGP SIGNATURE----- --K/ySGvJLhH//+QXY-- From MAILER-DAEMON Thu Jan 19 15:17:45 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIbM1-0002KE-2s for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 15:17:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIbLw-0002Jg-A0 for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 15:17:43 -0500 Received: from mail-oa1-x2e.google.com ([2001:4860:4864:20::2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIbLu-0004a1-Ca for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 15:17:39 -0500 Received: by mail-oa1-x2e.google.com with SMTP id 586e51a60fabf-15eec491b40so3847323fac.12 for ; Thu, 19 Jan 2023 12:17:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=lX/f4TRkWE06+NwnzDitUOj/rbGdBPdu3QAKHPVyvhY=; b=DqwAlI9vz84aL0RS7+M3rG6MpGIcPi2jsmESjpAphgpJBqw3+warIw/sfOvij2XC0l iUruRAL0565isjVCc9ncywDTrZH3JxefqmUCeL8hWWrk4r5A6QnmBbdxhRW1yV4bzZpt mprDle4E/lOjSMiHZBwMn7SZ1FFIaUQVbBl4rtiCt5ByvAQFCHi93XY8fWcth6k0cMN0 Oh6bTtzje22uHBmQ/U1y1L5PXxQyP1nA7TC2U4FcrS1cLE/sBT17W8nd0uwsb5uD/GWQ 14HGywH9SLqg+Kahy/QajqcuZ/6rIa4nT0FVNvGdcuhuakM50WN3sVkNItgUSdYX5lUS uXew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=lX/f4TRkWE06+NwnzDitUOj/rbGdBPdu3QAKHPVyvhY=; b=dbgOHAf8AYrf6fa1uVGKcbrQ7n7TigmALvkjBPlYQTewynGasaCKWBpL5Y9/ndwRRq 0ckaX28RI5eDTBp3rFyQuyua2T0Wn9b0JysgBKwMX/3NGjjmGgQ8zS8rrixeeJt5wuKO lcJDSPFdLZwM9yd/Vu1XriHUILDinJaZ2pv/W+SV7+I194PuPxmHKgnnsOgBAnt2wm0l Zc39vpinLARpnUwCdFQ1sOH4WGZlErnSFNzPNluHmhkBDB1/ZduZsE6s2zgrhRzjfSEp Da4fTjZVkjrZJJKxH1XkCz1dXr3zYqNp4CnPwVNn2IyLqA5TQi7lKTQY+1lzqgGrbu5Z 9gug== X-Gm-Message-State: AFqh2krs87vDFZnha4u1FXMu0qX/a+s/NWsDVfr/SeGIMyNttCVcItxD dWZKFJsiP6pNvYdUs5c/ZXm/sg== X-Google-Smtp-Source: AMrXdXtt12V7REAS0RX8kInk0uyyO9YukkuWPNygugVQu1AaV93IVUHCR8keCtbtYaPlXujbfFbf2w== X-Received: by 2002:a05:6870:4985:b0:152:d0dc:2bba with SMTP id ho5-20020a056870498500b00152d0dc2bbamr6572487oab.15.1674159456962; Thu, 19 Jan 2023 12:17:36 -0800 (PST) Received: from [192.168.68.107] ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id e145-20020a4a5597000000b004fd878ef510sm2026322oob.21.2023.01.19.12.17.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Jan 2023 12:17:36 -0800 (PST) Message-ID: Date: Thu, 19 Jan 2023 17:17:33 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH v3 3/7] hw/riscv/microchip_pfsoc.c: add an Icicle Kit fdt address function To: Conor Dooley Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com References: <20230119191728.622081-1-dbarboza@ventanamicro.com> <20230119191728.622081-4-dbarboza@ventanamicro.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2e.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.094, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 20:17:43 -0000 On 1/19/23 16:56, Conor Dooley wrote: > Hey! > > On Thu, Jan 19, 2023 at 04:17:24PM -0300, Daniel Henrique Barboza wrote: >> The Icicle Kit board works with 2 distinct RAM banks that are separated >> by a gap. We have a lower bank with 1GiB size, a gap follows, >> then at 64GiB the high memory starts. >> >> MachineClass::default_ram_size is set to 1.5Gb and machine_init() is >> enforcing it as minimal RAM size, meaning that there we'll always have >> at least 512 MiB in the Hi RAM area, and that the FDT will be located >> there all the time. >> >> riscv_compute_fdt_addr() can't handle this setup because it assumes that >> the RAM is always contiguous. It's also returning an uint32_t because >> it's enforcing that fdt address is sitting on an area that is addressable >> to 32 bit CPUs, but 32 bits won't be enough to point to the Hi area of >> the Icicle Kit RAM (and to its FDT itself). >> >> Create a new function called microchip_compute_fdt_addr() that is able >> to deal with all these details that are particular to the Icicle Kit. >> Ditch riscv_compute_fdt_addr() and use it instead. > Hmm, this breaks boot for me in what is a valid configuration for > Icicle/PolarFire SoC which was previously functional in QEMU. Thanks for letting me know.  Are you testing it by using the command line you mentioned in the "qemu icicle kit es" thread? $(QEMU)/qemu-system-riscv64 \ -M microchip-icicle-kit \ -m 2G -smp 5 \ -kernel $(vmlinux_bin) \ -dtb $(devkit).dtb \ -initrd $(initramfs) \ -display none \ -serial null \ -serial stdio Thanks, Daniel > > I'll try and write another email explaining things in more detail, but > in case I do not have time to get that done in the next day or two I > figured I should let you know. > > Thanks, > Conor. > From MAILER-DAEMON Thu Jan 19 16:37:26 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIcb0-0006Fj-If for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 16:37:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIcay-0006FS-ED for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 16:37:17 -0500 Received: from mail-oi1-x244.google.com ([2607:f8b0:4864:20::244]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIcaw-0001no-08 for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 16:37:16 -0500 Received: by mail-oi1-x244.google.com with SMTP id s66so2838842oib.7 for ; Thu, 19 Jan 2023 13:37:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=uRotMhtHnKBAO6t2X2uPrp0RVjEDypTQfmHvure0DIU=; b=diJp3OKys+kObtFlzg5ZLmw3ZRlmCctSjDOrNUW1RhrxpC6F2RvsvH1jUeJF1zByTz 84OUkgRPX1x1AYsPFQFjpxPRZLu+OnB9VLoGfRLT6Hj/H/D3A8EVva1DLnx7OJkl56h3 8sXOXG0zMb2Qhq7hdsxMAy8BwHZxOmxAa+YFRX5YM18Dysjxw0BuBgHfdcYmq8Sd3YnV ElVZp2Brkz4gzvCXsNLueV8k27S6CyXE+3IrEVYuzOhGOvAbHPKTDYWekEYKmH8o7eJZ vywilixfQ2zC9K7LWADQFmeio/ZhQcPacOUmv2+j7KFBLwA80EUCMMGATFf/EyEjtyoP ulmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=uRotMhtHnKBAO6t2X2uPrp0RVjEDypTQfmHvure0DIU=; b=FeHdv8+9oV5D+yVxAo6ZQz0uPnAd/Qn/3HJO/VJ/zMyFBGt5xz0nyseNt+noh8ZVL9 SOj82AfN5P00701pSt2rJSRbIvlzZ8Pr6bKbAyqKTlbQMzF/n248MPFv2y0MeMGDj593 IRXu5Xu6FRvad84sPoMvbH/I6vZr2Y+tP89DVnxPkvGMFsf4zj4GTpPDMuRALfrC99/d iPpfarugDDw6RyFsUSKt/PXFnkLli6J2e0LuQsDweiA1GcfNQOw4o1Q8JnAfHjlexDCC RRHbimRzNNa1EdnD8bz0ugg8EqwTdgopjIi3T2rjW9N9a26HzYHCXQ1QOtbKUDRrkmIx /FJw== X-Gm-Message-State: AFqh2kq482YrSuGFOxHtpduF/lAHL7o81KBrLUEcN8tJV9mxWtdAD6RN wTa334jLOKyI3/DDxTigoWoVxA== X-Google-Smtp-Source: AMrXdXuUTfclmD9rOdEeDXq5bSZr5NmmZjRG+7Ov4whzmRHGegiuwipzgbAA0Pn6bEccmRV3QO/ulA== X-Received: by 2002:aca:5bc1:0:b0:367:18a6:eb26 with SMTP id p184-20020aca5bc1000000b0036718a6eb26mr4894316oib.42.1674164232001; Thu, 19 Jan 2023 13:37:12 -0800 (PST) Received: from grind.dc1.ventanamicro.com ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id c132-20020aca358a000000b003646062e83bsm13664472oia.29.2023.01.19.13.37.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 13:37:11 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v9 0/3] hw/riscv: clear kernel_entry high bits with 32bit CPUs Date: Thu, 19 Jan 2023 18:37:04 -0300 Message-Id: <20230119213707.651533-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::244; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x244.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 21:37:17 -0000 Hi, In this version I changed the patch order to avoid having a patch that would trigger the 32 bit regression Alistair observed. Patch 3 is now the first patch. I've also addressed the comments from Bin and Phil. Patches based on riscv-to-apply.next. Changes from v8: - patch 1 (former 3): - comment changes - now open code '32' instead of using a macro - v8 link: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg03254.html Daniel Henrique Barboza (3): hw/riscv: clear kernel_entry higher bits from load_elf_ram_sym() hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() hw/riscv/boot.c: make riscv_load_initrd() static hw/riscv/boot.c | 96 ++++++++++++++++++++++++++------------ hw/riscv/microchip_pfsoc.c | 12 +---- hw/riscv/opentitan.c | 4 +- hw/riscv/sifive_e.c | 4 +- hw/riscv/sifive_u.c | 12 +---- hw/riscv/spike.c | 14 ++---- hw/riscv/virt.c | 12 +---- include/hw/riscv/boot.h | 3 +- 8 files changed, 82 insertions(+), 75 deletions(-) -- 2.39.0 From MAILER-DAEMON Thu Jan 19 16:37:29 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIcbA-0006Hc-Ib for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 16:37:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIcb3-0006Fr-H4 for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 16:37:25 -0500 Received: from mail-oa1-x35.google.com ([2001:4860:4864:20::35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIcb0-0001oE-HP for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 16:37:21 -0500 Received: by mail-oa1-x35.google.com with SMTP id 586e51a60fabf-15bb8ec196aso4162639fac.3 for ; Thu, 19 Jan 2023 13:37:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=eBWqTxhea3R6yi0puSYiInuCz6+T6PE/Cqolf5PLF8A=; b=HS6SvkUlRl52/RHSrcQMWB5v+JD6bQA7YCMEs74/QSKTSblBjt5SRg6rK+mmg9G3S3 V+SNebCLoNjm3ddnZ3PMwVRLQBmSFNhgmDKeh2HEKIvFGbkvzrcbRn7I6iVVhDQaIVCz E+MhHm3lsrWHB4rabWKzDTWJZ1LY/NKSfz9NJhZaikLv/hJYfAd5eA4qJOPCEinnmdy9 UTdg/foOkIyAhRM8gHCSuvQWkrTsLAOKAyXBJijVOGdIq9W2c1xNrZppcHgsvNRSamzE SEpqIcOE07HwBZu0ybtsHy6ryGu0jUCXsflaiWYPrRA3TZEg1fY4RiYKn5DZVNM7JvHG CNgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=eBWqTxhea3R6yi0puSYiInuCz6+T6PE/Cqolf5PLF8A=; b=rT7Mv0r/WlzFnMxq+pg7gTiKGditC9D4igQ7j6q7tF6mVOLFcno3HRzNgQtzaQIu7J Orra5hJXy0HVOTurtATHVVscrBsuWXx0435Cu0Lz2wdR4h2GwCLUN8AqJQ8jfq9YGr1v ie4EiiSwABoea16LKWJbb6dBygosOfYsfk5J+UYNAkm4Iy058hpE/8CHINy9XM7EzYdo dPXqF2Bt4GhdTq+H0Y2DnBv0p55AnKUDlajwgnUS27N1munt2r97E6JAJD3kPyUSYwbC HGiYKxxWqsBpQ/CC19bkj6l9FALGvvaXvx/OXP+I+6wPuy2WWyy3pNfMth/VizK+VWMf rhuA== X-Gm-Message-State: AFqh2kq+HgpauW80z+F85qv2nQclk1NB7H27gR0zycX/rX+NKpLkS5j9 oanSe16CMC0agL39XWtVVY0ODA== X-Google-Smtp-Source: AMrXdXvpEG5AXcbWXhF7XYd67lfiJiZxjY1w8gMVRw2ocFdj4iChoIMghgy2ruSjAlEDOHxMnB8tqQ== X-Received: by 2002:a05:6870:670b:b0:15e:ee5d:8696 with SMTP id gb11-20020a056870670b00b0015eee5d8696mr7212513oab.54.1674164236691; Thu, 19 Jan 2023 13:37:16 -0800 (PST) Received: from grind.dc1.ventanamicro.com ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id c132-20020aca358a000000b003646062e83bsm13664472oia.29.2023.01.19.13.37.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 13:37:16 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Palmer Dabbelt , Bin Meng Subject: [PATCH v9 2/3] hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() Date: Thu, 19 Jan 2023 18:37:06 -0300 Message-Id: <20230119213707.651533-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230119213707.651533-1-dbarboza@ventanamicro.com> References: <20230119213707.651533-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::35; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 21:37:26 -0000 The microchip_icicle_kit, sifive_u, spike and virt boards are now doing the same steps when '-kernel' is used: - execute load_kernel() - load init_rd() - write kernel_cmdline Let's fold everything inside riscv_load_kernel() to avoid code repetition. To not change the behavior of boards that aren't calling riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and allow these boards to opt out from initrd loading. Cc: Palmer Dabbelt Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 22 +++++++++++++++++++--- hw/riscv/microchip_pfsoc.c | 11 +---------- hw/riscv/opentitan.c | 3 ++- hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 11 +---------- hw/riscv/spike.c | 11 +---------- hw/riscv/virt.c | 11 +---------- include/hw/riscv/boot.h | 1 + 8 files changed, 28 insertions(+), 45 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 46fc7adccf..29e0c204d3 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -192,10 +192,12 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr) target_ulong riscv_load_kernel(MachineState *machine, RISCVHartArrayState *harts, target_ulong kernel_start_addr, + bool load_initrd, symbol_fn_t sym_cb) { const char *kernel_filename = machine->kernel_filename; uint64_t kernel_load_base, kernel_entry; + void *fdt = machine->fdt; g_assert(kernel_filename != NULL); @@ -210,21 +212,35 @@ target_ulong riscv_load_kernel(MachineState *machine, translate_kernel_address, harts, NULL, &kernel_load_base, NULL, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { - return kernel_load_base; + kernel_entry = kernel_load_base; + goto out; } if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, NULL, NULL, NULL) > 0) { - return kernel_entry; + goto out; } if (load_image_targphys_as(kernel_filename, kernel_start_addr, current_machine->ram_size, NULL) > 0) { - return kernel_start_addr; + kernel_entry = kernel_start_addr; + goto out; } error_report("could not load kernel '%s'", kernel_filename); exit(1); + +out: + if (load_initrd && machine->initrd_filename) { + riscv_load_initrd(machine, kernel_entry); + } + + if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { + qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", + machine->kernel_cmdline); + } + + return kernel_entry; } void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index bdefeb3cbb..b7e171b605 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -630,16 +630,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) firmware_end_addr); kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, - kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", - "bootargs", machine->kernel_cmdline); - } + kernel_start_addr, true, NULL); /* Compute the fdt load address in dram */ fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 2731138c41..3af9bfa52a 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -102,7 +102,8 @@ static void opentitan_board_init(MachineState *machine) if (machine->kernel_filename) { riscv_load_kernel(machine, &s->soc.cpus, - memmap[IBEX_DEV_RAM].base, NULL); + memmap[IBEX_DEV_RAM].base, + false, NULL); } } diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 1a7d381514..04939b60c3 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -115,7 +115,8 @@ static void sifive_e_machine_init(MachineState *machine) if (machine->kernel_filename) { riscv_load_kernel(machine, &s->soc.cpus, - memmap[SIFIVE_E_DEV_DTIM].base, NULL); + memmap[SIFIVE_E_DEV_DTIM].base, + false, NULL); } } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 83dfe09877..b0b3e6f03a 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -599,16 +599,7 @@ static void sifive_u_machine_init(MachineState *machine) firmware_end_addr); kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, - kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + kernel_start_addr, true, NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 2bcc50d90d..483581e05f 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -307,16 +307,7 @@ static void spike_board_init(MachineState *machine) kernel_entry = riscv_load_kernel(machine, &s->soc[0], kernel_start_addr, - htif_symbol_callback); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + true, htif_symbol_callback); } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index ac173a6ed6..48326406fd 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1275,16 +1275,7 @@ static void virt_machine_done(Notifier *notifier, void *data) firmware_end_addr); kernel_entry = riscv_load_kernel(machine, &s->soc[0], - kernel_start_addr, NULL); - - if (machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); - } - - if (machine->kernel_cmdline && *machine->kernel_cmdline) { - qemu_fdt_setprop_string(machine->fdt, "/chosen", "bootargs", - machine->kernel_cmdline); - } + kernel_start_addr, true, NULL); } else { /* * If dynamic firmware is used, it doesn't know where is the next mode diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 105706bf25..e0eab1e01b 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -46,6 +46,7 @@ target_ulong riscv_load_firmware(const char *firmware_filename, target_ulong riscv_load_kernel(MachineState *machine, RISCVHartArrayState *harts, target_ulong firmware_end_addr, + bool load_initrd, symbol_fn_t sym_cb); void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); -- 2.39.0 From MAILER-DAEMON Thu Jan 19 16:37:29 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIcbB-0006IA-7O for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 16:37:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIcb0-0006Fo-Rn for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 16:37:21 -0500 Received: from mail-oi1-x241.google.com ([2607:f8b0:4864:20::241]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIcay-0001nz-4n for qemu-riscv@nongnu.org; Thu, 19 Jan 2023 16:37:18 -0500 Received: by mail-oi1-x241.google.com with SMTP id p133so2830938oig.8 for ; Thu, 19 Jan 2023 13:37:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; 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Thu, 19 Jan 2023 13:37:14 -0800 (PST) Received: from grind.dc1.ventanamicro.com ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id c132-20020aca358a000000b003646062e83bsm13664472oia.29.2023.01.19.13.37.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Jan 2023 13:37:13 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v9 1/3] hw/riscv: clear kernel_entry higher bits from load_elf_ram_sym() Date: Thu, 19 Jan 2023 18:37:05 -0300 Message-Id: <20230119213707.651533-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230119213707.651533-1-dbarboza@ventanamicro.com> References: <20230119213707.651533-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::241; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x241.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 21:37:26 -0000 load_elf_ram_sym() will sign-extend 32 bit addresses. If a 32 bit QEMU guest happens to be running in a hypervisor that are using 64 bits to encode its address, kernel_entry can be padded with '1's and create problems [1]. Use a translate_fn() callback to be called by load_elf_ram_sym() and return only the 32 bits address if we're running a 32 bit CPU. [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html Suggested-by: Philippe Mathieu-Daudé Suggested-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 20 +++++++++++++++++++- hw/riscv/microchip_pfsoc.c | 3 ++- hw/riscv/opentitan.c | 3 ++- hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 3 ++- hw/riscv/spike.c | 3 ++- hw/riscv/virt.c | 3 ++- include/hw/riscv/boot.h | 1 + 8 files changed, 32 insertions(+), 7 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 2594276223..46fc7adccf 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -173,7 +173,24 @@ target_ulong riscv_load_firmware(const char *firmware_filename, exit(1); } +static uint64_t translate_kernel_address(void *opaque, uint64_t addr) +{ + RISCVHartArrayState *harts = opaque; + + if (riscv_is_32bit(harts)) { + /* + * For 32 bit CPUs, kernel_load_base is sign-extended + * (i.e. it can be padded with '1's) by load_elf(). + * Remove the sign extension by truncating to 32-bit. + */ + return extract64(addr, 0, 32); + } + + return addr; +} + target_ulong riscv_load_kernel(MachineState *machine, + RISCVHartArrayState *harts, target_ulong kernel_start_addr, symbol_fn_t sym_cb) { @@ -189,7 +206,8 @@ target_ulong riscv_load_kernel(MachineState *machine, * the (expected) load address load address. This allows kernels to have * separate SBI and ELF entry points (used by FreeBSD, for example). */ - if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, + if (load_elf_ram_sym(kernel_filename, NULL, + translate_kernel_address, harts, NULL, &kernel_load_base, NULL, NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { return kernel_load_base; diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 82ae5e7023..bdefeb3cbb 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -629,7 +629,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); + kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, + kernel_start_addr, NULL); if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 64d5d435b9..2731138c41 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -101,7 +101,8 @@ static void opentitan_board_init(MachineState *machine) } if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); + riscv_load_kernel(machine, &s->soc.cpus, + memmap[IBEX_DEV_RAM].base, NULL); } } diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 3e3f4b0088..1a7d381514 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machine) memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); if (machine->kernel_filename) { - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL); + riscv_load_kernel(machine, &s->soc.cpus, + memmap[SIFIVE_E_DEV_DTIM].base, NULL); } } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 2fb6ee231f..83dfe09877 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -598,7 +598,8 @@ static void sifive_u_machine_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); + kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, + kernel_start_addr, NULL); if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index badc11ec43..2bcc50d90d 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -305,7 +305,8 @@ static void spike_board_init(MachineState *machine) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, + kernel_entry = riscv_load_kernel(machine, &s->soc[0], + kernel_start_addr, htif_symbol_callback); if (machine->initrd_filename) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4a11b4b010..ac173a6ed6 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1274,7 +1274,8 @@ static void virt_machine_done(Notifier *notifier, void *data) kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, kernel_start_addr, NULL); + kernel_entry = riscv_load_kernel(machine, &s->soc[0], + kernel_start_addr, NULL); if (machine->initrd_filename) { riscv_load_initrd(machine, kernel_entry); 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Thu, 19 Jan 2023 13:37:18 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Bin Meng Subject: [PATCH v9 3/3] hw/riscv/boot.c: make riscv_load_initrd() static Date: Thu, 19 Jan 2023 18:37:07 -0300 Message-Id: <20230119213707.651533-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230119213707.651533-1-dbarboza@ventanamicro.com> References: <20230119213707.651533-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 21:37:27 -0000 The only remaining caller is riscv_load_kernel_and_initrd() which belongs to the same file. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/boot.c | 80 ++++++++++++++++++++--------------------- include/hw/riscv/boot.h | 1 - 2 files changed, 40 insertions(+), 41 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 29e0c204d3..62cc816b83 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -189,6 +189,46 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr) return addr; } +static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) +{ + const char *filename = machine->initrd_filename; + uint64_t mem_size = machine->ram_size; + void *fdt = machine->fdt; + hwaddr start, end; + ssize_t size; + + g_assert(filename != NULL); + + /* + * We want to put the initrd far enough into RAM that when the + * kernel is uncompressed it will not clobber the initrd. However + * on boards without much RAM we must ensure that we still leave + * enough room for a decent sized initrd, and on boards with large + * amounts of RAM we must avoid the initrd being so far up in RAM + * that it is outside lowmem and inaccessible to the kernel. + * So for boards with less than 256MB of RAM we put the initrd + * halfway into RAM, and for boards with 256MB of RAM or more we put + * the initrd at 128MB. + */ + start = kernel_entry + MIN(mem_size / 2, 128 * MiB); + + size = load_ramdisk(filename, start, mem_size - start); + if (size == -1) { + size = load_image_targphys(filename, start, mem_size - start); + if (size == -1) { + error_report("could not load ramdisk '%s'", filename); + exit(1); + } + } + + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ + if (fdt) { + end = start + size; + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); + qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); + } +} + target_ulong riscv_load_kernel(MachineState *machine, RISCVHartArrayState *harts, target_ulong kernel_start_addr, @@ -243,46 +283,6 @@ out: return kernel_entry; } -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) -{ - const char *filename = machine->initrd_filename; - uint64_t mem_size = machine->ram_size; - void *fdt = machine->fdt; - hwaddr start, end; - ssize_t size; - - g_assert(filename != NULL); - - /* - * We want to put the initrd far enough into RAM that when the - * kernel is uncompressed it will not clobber the initrd. However - * on boards without much RAM we must ensure that we still leave - * enough room for a decent sized initrd, and on boards with large - * amounts of RAM we must avoid the initrd being so far up in RAM - * that it is outside lowmem and inaccessible to the kernel. - * So for boards with less than 256MB of RAM we put the initrd - * halfway into RAM, and for boards with 256MB of RAM or more we put - * the initrd at 128MB. - */ - start = kernel_entry + MIN(mem_size / 2, 128 * MiB); - - size = load_ramdisk(filename, start, mem_size - start); - if (size == -1) { - size = load_image_targphys(filename, start, mem_size - start); - if (size == -1) { - error_report("could not load ramdisk '%s'", filename); - exit(1); - } - } - - /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ - if (fdt) { - end = start + size; - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", end); - } -} - uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) { uint64_t temp, fdt_addr; diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index e0eab1e01b..bc9faed397 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -48,7 +48,6 @@ target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, bool load_initrd, symbol_fn_t sym_cb); -void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr, -- 2.39.0 From MAILER-DAEMON Thu Jan 19 17:16:34 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIdCz-0007n2-AE for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 17:16:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIdCx-0007ma-Ep; Thu, 19 Jan 2023 17:16:31 -0500 Received: from mx0b-0031df01.pphosted.com ([205.220.180.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIdCv-0000UA-1b; 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envelope-from=tsimpson@quicinc.com; helo=mx0b-0031df01.pphosted.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 22:16:31 -0000 > -----Original Message----- > From: Markus Armbruster > Sent: Thursday, January 19, 2023 1:00 AM > To: qemu-devel@nongnu.org > Cc: richard.henderson@linaro.org; pbonzini@redhat.com; > kwolf@redhat.com; hreitz@redhat.com; imp@bsdimp.com; > kevans@freebsd.org; berrange@redhat.com; groug@kaod.org; > qemu_oss@crudebyte.com; mst@redhat.com; philmd@linaro.org; > peter.maydell@linaro.org; alistair@alistair23.me; jasowang@redhat.com; > jonathan.cameron@huawei.com; kbastian@mail.uni-paderborn.de; > quintela@redhat.com; dgilbert@redhat.com; michael.roth@amd.com; > kkostiuk@redhat.com; Taylor Simpson ; > palmer@dabbelt.com; bin.meng@windriver.com; qemu-block@nongnu.org; > qemu-arm@nongnu.org; qemu-riscv@nongnu.org > Subject: [PATCH v4 12/19] target/hexagon: Clean up includes >=20 > Clean up includes so that osdep.h is included first and headers which it > implies are not included manually. >=20 > This commit was created with scripts/clean-includes. >=20 > Changes to standalone programs dropped, because I can't tell whether them > not using qemu/osdep.h is intentional: >=20 > target/hexagon/gen_dectree_import.c > target/hexagon/gen_semantics.c > target/hexagon/idef-parser/idef-parser.h > target/hexagon/idef-parser/parser-helpers.c > target/hexagon/idef-parser/parser-helpers.h Correct. These are standalone programs not built with the full QEMU contex= t. >=20 > Signed-off-by: Markus Armbruster > --- > target/hexagon/hex_arch_types.h | 1 - > target/hexagon/mmvec/macros.h | 1 - > 2 files changed, 2 deletions(-) Reviewed-by: Taylor Simpson From MAILER-DAEMON Thu Jan 19 17:45:12 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIdei-0006vW-QX for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 17:45:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIdef-0006u8-Rc; Thu, 19 Jan 2023 17:45:09 -0500 Received: from mail-ua1-x936.google.com ([2607:f8b0:4864:20::936]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIded-0005FP-D5; Thu, 19 Jan 2023 17:45:09 -0500 Received: by mail-ua1-x936.google.com with SMTP id g12so947831uae.6; Thu, 19 Jan 2023 14:45:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=9T2LHo4z/skdJ6o1zjhvO2jeAFrlopB/32iHlHs6Amg=; b=TUNNMtahAU4KN1w38tUH9re0LSAGzhLUfOgCz0xcENWF6G6bLtg08Cu3wdmSi1Rgq0 L9bVNIQdBHvuY3qPxga1XM09Ps6/r/ZMGDEnSU5TN2WLEw21mE3dKL3IM6qDgGtTZXe7 FjN7W/NGVKTis55LS8NBhY+c9JNuVKVl6QSLMY2CAq5yp0h3FlekzbrU8rUW9ujJAo5I UrMeBXuXPRv/MbufEs4AZSB/ZEjkblR27rT/QzaO0FC4/gnqyc/8w2rTOBu2anZq2rD8 fnX/kA44ieqSTLd5tgY5JCF4zHHXXdKlNm38Lk8nshfg2EZqa2IzAVXFNxr8/lPMdzGl 1d9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=9T2LHo4z/skdJ6o1zjhvO2jeAFrlopB/32iHlHs6Amg=; b=fTeNQLwdkrP8duRbgRkz0lbT3ddTq0N0vLzYv0IscUj9DqhufwAg03F3sUlPcKgDnC 2Qq6GRE+7rlRrqPBMGBKnA9rG3ChPTlCxQnnPRUQ07S384RPvNRxMGG/izI7kJXshLrL T/4sl1zA5c2OqXQP03yVzh07ZNXrxbrVx3U8jlXXnmiIG8lyFAerV5c3hezEKCJwtFVc 0JWFiU37u2LTKOHl3F5QTrff208M4y4cIe9HO+QOdtuGiHmCcZ24hApB114zv9AmeDKY 1myT3UHbaEJTYAjd5YtGsIi+nVLHeY3zSrtAw/3ZrQiOHlBTBrdWgjGf2rHMdq85kskl 5dpA== X-Gm-Message-State: AFqh2kpiDQtn0Xxj9WqpqK3tQzBdd7RJ9QfQ85ktkA2P69h6DKf5e09z RtUR1ZnnygCVI0cc/de4vo4WKasvUOudx2s4p50= X-Google-Smtp-Source: AMrXdXvCZE8Xh3BZFLtpIRyOJgmdz3oRbYuFffyPfQG5kpF5X4xN+j4cnDqFm7tme9XEV9K4zsMT3xfSs8kC6iQFbhs= X-Received: by 2002:ab0:d89:0:b0:5fe:e440:bec4 with SMTP id i9-20020ab00d89000000b005fee440bec4mr1476002uak.96.1674168304879; Thu, 19 Jan 2023 14:45:04 -0800 (PST) MIME-Version: 1.0 References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-14-armbru@redhat.com> In-Reply-To: <20230119065959.3104012-14-armbru@redhat.com> From: Alistair Francis Date: Fri, 20 Jan 2023 08:44:38 +1000 Message-ID: Subject: Re: [PATCH v4 13/19] riscv: Clean up includes To: Markus Armbruster Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::936; envelope-from=alistair23@gmail.com; helo=mail-ua1-x936.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 22:45:11 -0000 On Thu, Jan 19, 2023 at 5:10 PM Markus Armbruster wrote: > > Clean up includes so that osdep.h is included first and headers > which it implies are not included manually. > > This commit was created with scripts/clean-includes. > > Signed-off-by: Markus Armbruster Reviewed-by: Alistair Francis Alistair > --- > target/riscv/pmu.h | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h > index 3004ce37b6..0c819ca983 100644 > --- a/target/riscv/pmu.h > +++ b/target/riscv/pmu.h > @@ -16,7 +16,6 @@ > * this program. If not, see . > */ > > -#include "qemu/osdep.h" > #include "qemu/log.h" > #include "cpu.h" > #include "qemu/main-loop.h" > -- > 2.39.0 > > From MAILER-DAEMON Thu Jan 19 18:46:47 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIecH-0003Cv-LM for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 18:46:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIecA-00037A-94; Thu, 19 Jan 2023 18:46:41 -0500 Received: from mail-ua1-x935.google.com ([2607:f8b0:4864:20::935]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIec6-0002NA-0h; Thu, 19 Jan 2023 18:46:35 -0500 Received: by mail-ua1-x935.google.com with SMTP id u3so991214uae.0; Thu, 19 Jan 2023 15:46:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=KPqJVJp80N/DeT38pRVWoUhAfRHJVaCGxreCuk0z0lQ=; b=L1Wa+IhLlyW6uZQjQEganUvpaCWpvURHGyHXP/hvz7QjzHmmC/Y7sBp1otKN/UZguM Om12yWN9TTQRytnGqvErPn7lVAh8bFJiC8wKQDI6ALcRPdJRa+AlM7qNFUmsnF7pUSsS ZBsIozRh1OmTS0F7j0oLMExg0juSTHgeo6X14x2d/GhizXv2xVP3COLVuuzbJVLAl7wF r+IvHheOGT2IVXuA0u7fpZCX3YPddn+ILJrGF6kOoOf9Xfe0gRgSovjsqQMUpl7CFASb SMGOEzZEzCRGM5wgbOBxuNWoTUvvD0qBQhAJiFX079Dqtg67r2zgpadPzERTwW9u2eAv 5nSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=KPqJVJp80N/DeT38pRVWoUhAfRHJVaCGxreCuk0z0lQ=; b=uUI8PxNwLYQ3kgmx3sUEwMEnX8pFIxEmGEj43bO7Tzr3Jbsc9HDhYS5Nt+e9cHoEbB j1jM29Gv1udgGz6BtnZzdpBK6/uwCPPZLrJnsvIYwMUjkknX/P91UcOpuAPcj2FwaNWb LBiWHasXgMVyUX5WXqFQJeKLbplGWMM7r0Dv90y9WSeErjifr11poq69CyDCz0oRsQTf Q1zHJSwCUusTVYUOc7cg5KgrQTTlN7bS0j54Gd9GkcsIsfWjFgtYuJqikNtBBjN5vCY0 ncDT/QNCLj3ZEueXG8g1n412vL3QHZJ24rN5Z1I6gKyqlduShnRW+UPevEA+d2+31WtK suZA== X-Gm-Message-State: AFqh2kqZJQBJBm7tHyMHbCT0WzfkqY1PBTJSZLquT4oyD02qeqbLCWr7 PNsQ2HaZnALJa1q0QO91maYpA17dXXuqQ0FCUFg= X-Google-Smtp-Source: AMrXdXumeFp70WmynUNpbw4r3HyocN0em/Mt78DcvpI/jdNUgdZAU9rfcKmdnZKjPtthcOUvjratqDEP88Uu6WfWjKY= X-Received: by 2002:ab0:3b8d:0:b0:419:2865:3ae7 with SMTP id p13-20020ab03b8d000000b0041928653ae7mr1567838uaw.70.1674171991715; Thu, 19 Jan 2023 15:46:31 -0800 (PST) MIME-Version: 1.0 References: <20230113103453.42776-1-alexghiti@rivosinc.com> <20230113103453.42776-3-alexghiti@rivosinc.com> <20230117163138.jze47hjeeuwu2k4j@orel> <20230118121916.6aqj57leen72z5tz@orel> In-Reply-To: From: Alistair Francis Date: Fri, 20 Jan 2023 09:46:05 +1000 Message-ID: Subject: Re: [PATCH v5 2/2] riscv: Allow user to set the satp mode To: Alexandre Ghiti Cc: Andrew Jones , Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::935; envelope-from=alistair23@gmail.com; helo=mail-ua1-x935.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 19 Jan 2023 23:46:42 -0000 On Thu, Jan 19, 2023 at 11:00 PM Alexandre Ghiti wrote: > > Hi Alistair, Andrew, > > On Thu, Jan 19, 2023 at 1:25 AM Alistair Francis wrote: > > > > On Wed, Jan 18, 2023 at 10:19 PM Andrew Jones wrote: > > > > > > On Wed, Jan 18, 2023 at 10:28:46AM +1000, Alistair Francis wrote: > > > > On Wed, Jan 18, 2023 at 2:32 AM Andrew Jones wrote: > > > > > > > > > > On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote: > > > ... > > > > > > + > > > > > > + /* Get rid of 32-bit/64-bit incompatibility */ > > > > > > + for (int i = 0; i < 16; ++i) { > > > > > > + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > > > > > > > > > > If we ever define mode=1 for rv64, then 'sv32=on' will be incorrectly > > > > > accepted as an alias. I think we should simply not define the sv32 > > > > > property for rv64 nor the rv64-only modes for rv32. So, down in > > > > > riscv_add_satp_mode_properties() we can add some > > > > > > > > > > #if defined(TARGET_RISCV32) > > > > > ... > > > > > #elif defined(TARGET_RISCV64) > > > > > ... > > > > > #endif > > > > > > > > Do not add any #if defined(TARGET_RISCV32) to QEMU. > > > > > > > > We are aiming for the riscv64-softmmu to be able to emulate 32-bit > > > > CPUs and compile time macros are the wrong solution here. Instead you > > > > can get the xlen of the hart and use that. > > > > > > > > > > Does this mean we want to be able to do the following? > > > > > > qemu-system-riscv64 -cpu rv32,sv32=on ... > > > > That's the plan > > > > > > > > If so, then can we move the object_property_add() for sv32 to > > > rv32_base_cpu_init() and the rest to rv64_base_cpu_init()? Wait! Sorry I didn't read this carefully enough. No, that is not what we want to do. That then won't support the vendor CPUs. We just want to add the properties to all CPUs. Then if an invalid option is set we should return an error. Note that the 64-bit only configs can be hidden behind a #if defined(TARGET_RISCV64). Alistair > > > Currently, that would be doing the same thing as proposed above, > > > since those functions are under TARGET_RISCV* defines, but I guess > > > the object_property_add()'s would then be in more or less the right > > > places for when the 32-bit emulation support work is started. > > > > Sounds like a good idea :) > > What about riscv_any_cpu_init and riscv_host_cpu_init? > > > > > Alistair > > > > > > > > Thanks, > > > drew From MAILER-DAEMON Thu Jan 19 19:00:34 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIepe-0006Cn-KT for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 19:00:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIepc-00064H-74; Thu, 19 Jan 2023 19:00:32 -0500 Received: from mail-vk1-xa36.google.com ([2607:f8b0:4864:20::a36]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIepa-0005mE-DP; Thu, 19 Jan 2023 19:00:31 -0500 Received: by mail-vk1-xa36.google.com with SMTP id i82so1792301vki.8; Thu, 19 Jan 2023 16:00:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=2L6/cN1y8IcvPVXB8DgZtdsayOsjfkLvj/cekQsNgo4=; b=ba1qp6waQ+PGIXrQwGdUbMcC12jpWRqHk94DuztjfjT8/KyuvBLNFZAyhwaGWU2xo7 cW3+U68uIGXBpfzaJ1+afb0LyYCPBE+Rb1tg7TGqQzXrd+zSJix2wArb6RpoXTU0U5fZ cRFJhdWoRDsyuJ+H0o9mhG/0vv2WTla2uT1ThUo4wZKlsNjH8fug+5FfxWSFgLSI6mtx XPytPn4miM9FtfMVaWp3KZP/Q0jsv6iXZStJeHNGca/TK2Z3KpaWG9148RZA+30g0dbB SKYXXkRlBKgeMnGsRKO+teIcse5t4UceJOhrdnqMWTPXejOg+hqD+YEcxvIHEk/oXBBw FM/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=2L6/cN1y8IcvPVXB8DgZtdsayOsjfkLvj/cekQsNgo4=; b=oFE8pB1S4WUHsTnIdvqjbpfrIpNKvornNLCRR5U2a3459OTZ9RZ7i5hwjLjqGBY0rk FNUgZfZWgda05XwtRaRLAF/x64U34SGD4IPGlwov4ycyr3QjF/h5rg+h/5X/vTyOYtqh Srg4QlnzCo/2giisXYeG3/yYuNHaGvuTj0I3T8x9+kufeW1LFRD/10dIdczK0Jl+G2NK pcvqJL1n8FAjEjj5Ia5ZbJdPoqWfzPFTvLI0Ag9U6hdVsYkhQcHzgtqt1KJN5ftQDQmz 16qVQIzfjvehJqRC4U3dRShxXgcCuylXOgMQKFmev1gKTg/bwcGYwuipdRKpjUELhSYI quVQ== X-Gm-Message-State: AFqh2koImILASqpXDTZ2oGgsZR2tTQQLrTd94gBrlQhU8bmcM7hWp/bt sK69Go1TGgepC/J9xJ4VDNdc3lIs/tTkJTgU7pcECXcOcU8= X-Google-Smtp-Source: AMrXdXua5mO9KZHaUF6Ju1g+rDP0gKREBk/J/pzWeZwQAmfine587Go6Lb4DlKmRjJgIHfjVjBcvOgw4xZgtvCkVM8Q= X-Received: by 2002:a05:6122:924:b0:3d5:5f93:53f with SMTP id j36-20020a056122092400b003d55f93053fmr1728465vka.7.1674172828585; Thu, 19 Jan 2023 16:00:28 -0800 (PST) MIME-Version: 1.0 References: <20221211052745.24738-1-vysakhpillai@embeddedinn.xyz> In-Reply-To: <20221211052745.24738-1-vysakhpillai@embeddedinn.xyz> From: Alistair Francis Date: Fri, 20 Jan 2023 10:00:02 +1000 Message-ID: Subject: Re: [PATCH] hw/riscv: Add support to change default RISCV hart memory region To: Vysakh P Pillai Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::a36; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa36.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Jan 2023 00:00:32 -0000 On Sun, Dec 11, 2022 at 3:29 PM Vysakh P Pillai wrote: > > Add support to optionally specify a memory region container > to be used to override the default system memory used > by the the RISCV harts when they are realized. Additional > memory regions can be added as sub-regions of this container > to dynamically control the memory regions and mappings visible > from the hart. Thanks for the patch. I think it might make more sense to send this with the series adding your board. It's a little difficult to picture how this is going to be used otherwise. > > Signed-off-by: Vysakh P Pillai > --- > hw/riscv/riscv_hart.c | 5 +++++ > include/hw/riscv/riscv_hart.h | 1 + > 2 files changed, 6 insertions(+) > > diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c > index 613ea2aaa0..7a8dcab7e7 100644 > --- a/hw/riscv/riscv_hart.c > +++ b/hw/riscv/riscv_hart.c > @@ -33,6 +33,8 @@ static Property riscv_harts_props[] = { > DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), > DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec, > DEFAULT_RSTVEC), > + DEFINE_PROP_UINT64("cpu-memory", RISCVHartArrayState, > + cpu_memory,NULL), I'm not sure I follow, this is a uint64_t but the default value is NULL? I assume you are using this as a pointer then? Alistair > DEFINE_PROP_END_OF_LIST(), > }; > > @@ -49,6 +51,9 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, int idx, > qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); > s->harts[idx].env.mhartid = s->hartid_base + idx; > qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); > + if (s->cpu_memory) { > + object_property_set_link(OBJECT(&s->harts[idx].parent_obj), "memory",OBJECT(s->cpu_memory), &error_abort); > + } > return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp); > } > > diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h > index bbc21cdc9a..3e5dfeeaae 100644 > --- a/include/hw/riscv/riscv_hart.h > +++ b/include/hw/riscv/riscv_hart.h > @@ -38,6 +38,7 @@ struct RISCVHartArrayState { > uint32_t hartid_base; > char *cpu_type; > uint64_t resetvec; > + uint64_t cpu_memory; > RISCVCPU *harts; > }; > > -- > 2.34.1 > > > From MAILER-DAEMON Thu Jan 19 19:15:48 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIf4M-0001gy-Ka for mharc-qemu-riscv@gnu.org; Thu, 19 Jan 2023 19:15:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIf4H-0001eu-TX; Thu, 19 Jan 2023 19:15:42 -0500 Received: from sin.source.kernel.org ([2604:1380:40e1:4800::1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIf4D-0002y8-1w; Thu, 19 Jan 2023 19:15:41 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sin.source.kernel.org (Postfix) with ESMTPS id ADB0BCE25E5; Fri, 20 Jan 2023 00:15:23 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EA086C433EF; Fri, 20 Jan 2023 00:15:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1674173722; bh=ePFabqVRf4st39leips0qVardbndU2mTd4+n33r+jwg=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=bn8/FCIFNQ+VJaszS3acaCOV3J0H/F1qq+4eQTmsmeeddcQLLwLoC9liQWiypZabg R6/qChbvE4buMa8nVVefDzPKbJqKZ7km96FmVFjXxpAvk85olYXvou06+tWlEaTcJb ZcJgsCd39tMCD3MJC/Px3CuuS7DWfzWmCdNTW5NyuJq8cnSm6OIObcPshj+Y6HgMH9 xCWoE5yOGwJPl96CpZDcb2fE8mMnSQol1HMwkPCJPkdJxg0E5T2i2eGji1A6ThDdgv LSx+I1Vr3Ao7O3KIqgCBdtJIzOmcT3d/CJbEDLL0mkpQqRIY/zkq0cnbUFldEjkbka /w32EXYiCQjww== Date: Fri, 20 Jan 2023 00:15:18 +0000 From: Conor Dooley To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Subject: Re: [PATCH v3 3/7] hw/riscv/microchip_pfsoc.c: add an Icicle Kit fdt address function Message-ID: References: <20230119191728.622081-1-dbarboza@ventanamicro.com> <20230119191728.622081-4-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="wMrXO/i6lGaZKplm" Content-Disposition: inline In-Reply-To: <20230119191728.622081-4-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2604:1380:40e1:4800::1; envelope-from=conor@kernel.org; helo=sin.source.kernel.org X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Jan 2023 00:15:44 -0000 --wMrXO/i6lGaZKplm Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hey Daniel, Got through the stuff I wanted to get done tonight faster than expected... On Thu, Jan 19, 2023 at 05:17:33PM -0300, Daniel Henrique Barboza wrote: > Are you testing it by using the command line > you mentioned in the "qemu icicle kit es" thread? >=20 > $(QEMU)/qemu-system-riscv64 \ > -M microchip-icicle-kit \ > -m 2G -smp 5 \ > -kernel $(vmlinux_bin) \ > -dtb $(devkit).dtb \ > -initrd $(initramfs) \ > -display none \ > -serial null \ > -serial stdio Yah, effectively. It's not quite that, but near enough as makes no real difference: qemu-icicle: $(QEMU)/qemu-system-riscv64 -M microchip-icicle-kit \ -m 2G -smp 5 \ -kernel $(vmlinux_bin) \ -dtb $(wrkdir)/riscvpc.dtb \ -initrd $(initramfs) \ -display none -serial null \ -serial stdio \ -D qemu.log -d unimp I just tried to make things somewhat more intelligible for that thread. Also in case it is not obvious, I do work for Microchip. As I mentioned to Alistair at LPC, I/we don't have the cycles at the moment to do anything with QEMU, so the bits of fixes I have sent are things I fixed while debugging other issues etc, mostly in the evenings. Anways, I'll attempt to explain what the craic is here.. On Thu, Jan 19, 2023 at 04:17:24PM -0300, Daniel Henrique Barboza wrote: > The Icicle Kit board works with 2 distinct RAM banks that are separated Ehh, 2 isn't really true. There are 6 possible "windows" into the DDR on MPFS, list here as with their start addresses. 32-bit cached 0x0080000000 64-bit cached 0x1000000000 32-bit non-cached 0x00c0000000 64-bit non-cached 0x1400000000 32-bit WCB 0x00d0000000 64-bit WCB 0x1800000000 These are the "bus" addresses, where the harts think the memory is, but the memory is not actually connected there. There are some runtime configurable registers which determine what addresses these correspond to in the DDR itself. When the QEMU port for MPFS was written, only two of these were in use, the 32-bit and 64-bit non-cached regions. The config (seg) registers were set up so that the 32-bit cached region pointed to 0x0 in DDR and the 64-bit region pointed to 0x3000_0000 in DDR. =E2=A2=B0=E2=A0=92=E2=A0=92=E2=A0=92=E2=A0=92=E2=A1=96=E2=A0=92=E2=A0=92=E2= =A0=92=E2=A3=B6=E2=A0=920x80000000 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8=E2=A1=96=E2=A0=92=E2=A0=92=E2=A2=B2=E2=A1=87 =E2=A1=87 0x400000= 00 =E2=A2=B8=E2=A1=87 =E2=A2=B8=E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8=E2=A1=87 =E2=A2=B8=E2=A0=93=E2=A0=92=E2=A0=92=E2=A0=92=E2=A0=83 = =E2=A1=87 <-- 64-bit starts here =E2=A2=B8=E2=A1=87 =E2=A2=B8 =E2=A1=87 =20 =E2=A2=B8=E2=A1=87 =E2=A2=B8 =E2=A1=87 =20 =E2=A2=B8=E2=A1=87 =E2=A2=B8 =E2=A1=87 =20 =E2=A2=B8=E2=A1=87 =E2=A2=B8 =E2=A1=87 =20 =E2=A2=B8=E2=A1=87 =E2=A2=B8 =E2=A1=87 <-- 32-bit starts at 0x0 =E2=A0=98=E2=A0=93=E2=A0=920=E2=A0=9A=E2=A0=92=E2=A0=921=E2=A0=92=E2=A0=92= =E2=A0=920x00000000 (These diagrams are a bit crap, I'm copy pasting them from a TUI tool for visualising these I made for myself. The ~s can be ignored. https://github.com/ConchuOD/memory-aperature-configurator) > by a gap. We have a lower bank with 1GiB size, a gap follows, > then at 64GiB the high memory starts. As you correctly pointed out, that lower region is in fact 1 GiB & hence there is actually an overlapping region of 256 MiB. The Devicetree at this point in time looked like: ddrc_cache_lo: memory@80000000 { device_type =3D "memory"; reg =3D <0x0 0x80000000 0x0 0x30000000>; clocks =3D <&clkcfg CLK_DDRC>; status =3D "okay"; }; ddrc_cache_hi: memory@1000000000 { device_type =3D "memory"; reg =3D <0x10 0x0 0x0 0x40000000>; clocks =3D <&clkcfg CLK_DDRC>; status =3D "okay"; }; At some point, it was decided that instead we would use a configuration with ~no memory at 32-bit addresses. I think it was this one here: =E2=A2=B0=E2=A1=96=E2=A0=92=E2=A0=92=E2=A2=B2=E2=A1=96=E2=A0=92=E2=A0=92=E2= =A0=92=E2=A3=B6=E2=A0=920x80000000 =E2=A2=B8=E2=A1=87 =E2=A2=B8=E2=A1=87 =E2=A3=BF =E2=A1=87 =20 =E2=A2=B8=E2=A0=93=E2=A0=92=E2=A0=92=E2=A0=9A=E2=A1=87 =E2=A1=9F =E2=A1= =87 <-- 32-bit starts here =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 0x40000000 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 <-- 64-bit starts at 0x0 =E2=A0=98=E2=A0=92=E2=A0=920=E2=A0=92=E2=A0=93=E2=A0=921=E2=A0=92=E2=A0=93= =E2=A0=920x00000000 Because of how these windows work, the 32-bit cached region was always there, just not used as the Devicetree became: ddrc_cache: memory@1000000000 { device_type =3D "memory"; reg =3D <0x10 0x0 0x0 0x76000000>; status =3D "okay"; }; The remaining bit of memory is being used for some WCB buffers etc & not for the OS itself. This was never upstreamed anywhere AFAIK as it was a workaround. The current Devicetree in Linux & U-Boot corresponds to a configuration like: =E2=A2=B0=E2=A0=92=E2=A0=92=E2=A0=92=E2=A0=92=E2=A1=96=E2=A0=92=E2=A0=92=E2= =A0=92=E2=A3=B6=E2=A0=920x80000000 =E2=A2=B8 =E2=A1=87 =E2=A3=BF =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=9F =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8=E2=A1=96=E2=A0=92=E2=A0=92=E2=A2=B2=E2=A1=87 =E2=A1=87 0x400000= 00 =E2=A2=B8=E2=A1=87 =E2=A2=B8=E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8=E2=A1=87 =E2=A2=B8=E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8=E2=A1=87 =E2=A2=B8=E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8=E2=A1=87 =E2=A2=B8=E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8=E2=A1=87 =E2=A2=B8=E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8=E2=A1=87 =E2=A2=B8=E2=A1=87 =E2=A1=87 =E2=A1=87 =20 =E2=A2=B8=E2=A1=87 =E2=A2=B8=E2=A1=87 =E2=A1=87 =E2=A1=87 <-- 32- & 64-b= it start at 0x0 =E2=A0=98=E2=A0=93=E2=A0=920=E2=A0=9A=E2=A0=93=E2=A0=921=E2=A0=92=E2=A0=93= =E2=A0=920x00000000 That DT looks like: ddrc_cache_lo: memory@80000000 { device_type =3D "memory"; reg =3D <0x0 0x80000000 0x0 0x40000000>; status =3D "okay"; }; ddrc_cache_hi: memory@1040000000 { device_type =3D "memory"; reg =3D <0x10 0x40000000 0x0 0x40000000>; status =3D "okay"; }; Each of these changes came as part of an FPGA reference design change & a corresponding compatible change. I believe rtlv2203 was the second configuration & rtlv2210 the third. I can't boot the current configuration in QEMU, probably due to some of the things you point out below. To get it working, I remove the ddrc_cache_hi from my DT and boot with the 32-bit cached memory only. This is what the current changes have broken for me. IMO it is a perfectly valid thing to boot a system using less than the memory it *can* use. I guess you read the other thread in which I stated that the HSS boot that is documented doesn't work with recent HSSes. Ideally, and I am most certainly _not_ expecting anyone to do this, when the HSS writes the "seg" registers during boot to configure the memory layout as per the FPGA bitstream QEMU would configure the memory layout it is emulating to match. Since direct kernel boot is a thing too, I was thinking that for that mode, the config in the dtb should probably be used. I don't know enough about QEMU to know if this is even possible! The other possibility I was thinking of was just relaxing the DDR limit entirely (and ignoring the overlaying) so that QEMU thinks there is 1 GiB at 0x8000_0000 and 16 GiB at 0x10_0000_0000. Again, I've not had the cycles to look into any of this at all nor am I expecting anyone else to - just while I am already typing about this stuff there's no harm in broadcasting the other thoughts I had. > MachineClass::default_ram_size is set to 1.5Gb and machine_init() is > enforcing it as minimal RAM size, meaning that there we'll always have I don't think that this is=20 > at least 512 MiB in the Hi RAM area, and that the FDT will be located > there all the time. All the time? That's odd. I suppose my kernel then remaps the dtb into the memory range it can access, and therefore things keep ticking. I don't think that machine_init() should be enforcing a minimum ram size of 1.5 GiB - although maybe Bin Meng has a reason for that that I don't understand. > riscv_compute_fdt_addr() can't handle this setup because it assumes that > the RAM is always contiguous. It's also returning an uint32_t because > it's enforcing that fdt address is sitting on an area that is addressable > to 32 bit CPUs, but 32 bits won't be enough to point to the Hi area of > the Icicle Kit RAM (and to its FDT itself). >=20 > Create a new function called microchip_compute_fdt_addr() that is able > to deal with all these details that are particular to the Icicle Kit. > Ditch riscv_compute_fdt_addr() and use it instead. >=20 > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/microchip_pfsoc.c | 46 +++++++++++++++++++++++++++++++++++--- > 1 file changed, 43 insertions(+), 3 deletions(-) >=20 > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index dcdbc2cac3..9b829e4d1a 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -54,6 +54,8 @@ > #include "sysemu/device_tree.h" > #include "sysemu/sysemu.h" > =20 > +#include > + > /* > * The BIOS image used by this machine is called Hart Software Services = (HSS). > * See https://github.com/polarfire-soc/hart-software-services > @@ -513,6 +515,46 @@ static void microchip_pfsoc_soc_register_types(void) > =20 > type_init(microchip_pfsoc_soc_register_types) > =20 > +static hwaddr microchip_compute_fdt_addr(MachineState *ms) > +{ > + const MemMapEntry *memmap =3D microchip_pfsoc_memmap; > + hwaddr mem_low_size =3D memmap[MICROCHIP_PFSOC_DRAM_LO].size; > + hwaddr mem_high_size, fdt_base; > + int ret =3D fdt_pack(ms->fdt); > + int fdtsize; > + > + /* Should only fail if we've built a corrupted tree */ > + g_assert(ret =3D=3D 0); > + > + fdtsize =3D fdt_totalsize(ms->fdt); > + if (fdtsize <=3D 0) { > + error_report("invalid device-tree"); > + exit(1); > + } > + > + /* > + * microchip_icicle_kit_machine_init() does a validation > + * that guarantees that ms->ram_size is always greater > + * than mem_low_size and that mem_high_size will be > + * at least 512MiB. Again, I don't think it should be doing this at all. I see the comment about that size refers to DDR training, but given the overlaying of memory it's entirely possible to train against 64-bit addresses but then boot a kernel using only low memory addresses. Perhaps by default & for booting via the bootloader, but I don't think enforcing this makes sense when the bootloader is not involved. If a dtb is used as the source for the memory layout, requiring memory at high addresses doesn't make sense to me. I have no idea if there is a mechanism for figuring that out though nor am I au fait with how these memory sizes are calculated. It is getting kinda late here, so I am sending this without having investigated any of the detail, sorry. Hopefully that wasn't too deranged and you can at least understand why I have been doing what I have... Thanks, Conor. > + * > + * This also means that our fdt_addr will be based > + * on the starting address of the HI DRAM block. > + */ > + mem_high_size =3D ms->ram_size - mem_low_size; > + fdt_base =3D memmap[MICROCHIP_PFSOC_DRAM_HI].base; > + > + /* > + * In theory we could copy riscv_compute_fdt_addr() > + * and put the FDT capped at maximum 3Gb from fdt_base, > + * but fdt_base is set at 0x1000000000 (64GiB). We > + * make the assumption here that the OS is ready to > + * handle the FDT, 2MB aligned, at the very end of > + * the available RAM. > + */ > + return QEMU_ALIGN_DOWN(fdt_base + mem_high_size - fdtsize, 2 * MiB); > +} > + > static void microchip_icicle_kit_machine_init(MachineState *machine) > { > MachineClass *mc =3D MACHINE_GET_CLASS(machine); > @@ -640,9 +682,7 @@ static void microchip_icicle_kit_machine_init(Machine= State *machine) > "bootargs", machine->kernel_cmdline); > } > =20 > - /* Compute the fdt load address in dram */ > - fdt_load_addr =3D riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_= DRAM_LO].base, > - machine->ram_size, machine= ->fdt); > + fdt_load_addr =3D microchip_compute_fdt_addr(machine); > riscv_load_fdt(fdt_load_addr, machine->fdt); > =20 > /* Load the reset vector */ > --=20 > 2.39.0 >=20 >=20 >=20 --wMrXO/i6lGaZKplm Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY8ndFgAKCRB4tDGHoIJi 0g4GAQC7HlIcorv5FwQjYfzQLi/taDetKgE8WxSKwNQSVWwdfwEA47i98rN/DSAn N8hBItXm3FBdDhl13xv4vpQGc2lKFA0= =HZlu -----END PGP SIGNATURE----- --wMrXO/i6lGaZKplm-- From MAILER-DAEMON Fri Jan 20 02:19:28 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIlgM-0006Je-Ur for mharc-qemu-riscv@gnu.org; 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Fri, 20 Jan 2023 02:19:07 -0500 X-MC-Unique: dYftd6rBM2OUinGqeKSM9Q-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id C14B03802B82; Fri, 20 Jan 2023 07:19:06 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id E696D1415113; Fri, 20 Jan 2023 07:19:05 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id CACB421E6A28; Fri, 20 Jan 2023 08:19:04 +0100 (CET) From: Markus Armbruster To: "Dr. David Alan Gilbert" Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 10/19] migration: Clean up includes References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-11-armbru@redhat.com> <87wn5ivmru.fsf@pond.sub.org> Date: Fri, 20 Jan 2023 08:19:04 +0100 In-Reply-To: (David Alan Gilbert's message of "Thu, 19 Jan 2023 11:45:36 +0000") Message-ID: <87wn5hoeqf.fsf@pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Jan 2023 07:19:22 -0000 "Dr. David Alan Gilbert" writes: > * Markus Armbruster (armbru@redhat.com) wrote: >> "Dr. David Alan Gilbert" writes: >> >> > * Markus Armbruster (armbru@redhat.com) wrote: >> >> Clean up includes so that osdep.h is included first and headers >> >> which it implies are not included manually. >> > >> > That change doesn't seem to match the message; the patch is removing the >> > osdep.h include. >> >> It's the commit message scripts/clean-includes creates :) >> >> I can throw in another patch to the script so it mentions it also >> removes qemu/osdep.h from headers. > > Oh hmm it would be clearer; What about $GITSUBJ: Clean up includes Clean up includes so that osdep.h is included first in .c and not in .h, and headers which it implies are not included manually. This commit was created with scripts/clean-includes. > but OK then, so > > Reviewed-by: Dr. David Alan Gilbert Thanks! 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Fri, 20 Jan 2023 08:21:08 +0100 (CET) From: Markus Armbruster To: Taylor Simpson Cc: "qemu-devel@nongnu.org" , "richard.henderson@linaro.org" , "pbonzini@redhat.com" , "kwolf@redhat.com" , "hreitz@redhat.com" , "imp@bsdimp.com" , "kevans@freebsd.org" , "berrange@redhat.com" , "groug@kaod.org" , "qemu_oss@crudebyte.com" , "mst@redhat.com" , "philmd@linaro.org" , "peter.maydell@linaro.org" , "alistair@alistair23.me" , "jasowang@redhat.com" , "jonathan.cameron@huawei.com" , "kbastian@mail.uni-paderborn.de" , "quintela@redhat.com" , "dgilbert@redhat.com" , "michael.roth@amd.com" , "kkostiuk@redhat.com" , "palmer@dabbelt.com" , "bin.meng@windriver.com" , "qemu-block@nongnu.org" , "qemu-arm@nongnu.org" , "qemu-riscv@nongnu.org" , Alessandro Di Federico Subject: Re: [PATCH v4 12/19] target/hexagon: Clean up includes References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-13-armbru@redhat.com> Date: Fri, 20 Jan 2023 08:21:08 +0100 In-Reply-To: (Taylor Simpson's message of "Thu, 19 Jan 2023 22:15:37 +0000") Message-ID: <87sfg5oemz.fsf@pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Scanned-By: MIMEDefang 3.1 on 10.11.54.6 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Jan 2023 07:21:40 -0000 Taylor Simpson writes: >> -----Original Message----- >> From: Markus Armbruster >> Sent: Thursday, January 19, 2023 1:00 AM >> To: qemu-devel@nongnu.org >> Cc: richard.henderson@linaro.org; pbonzini@redhat.com; >> kwolf@redhat.com; hreitz@redhat.com; imp@bsdimp.com; >> kevans@freebsd.org; berrange@redhat.com; groug@kaod.org; >> qemu_oss@crudebyte.com; mst@redhat.com; philmd@linaro.org; >> peter.maydell@linaro.org; alistair@alistair23.me; jasowang@redhat.com; >> jonathan.cameron@huawei.com; kbastian@mail.uni-paderborn.de; >> quintela@redhat.com; dgilbert@redhat.com; michael.roth@amd.com; >> kkostiuk@redhat.com; Taylor Simpson ; >> palmer@dabbelt.com; bin.meng@windriver.com; qemu-block@nongnu.org; >> qemu-arm@nongnu.org; qemu-riscv@nongnu.org >> Subject: [PATCH v4 12/19] target/hexagon: Clean up includes >> >> Clean up includes so that osdep.h is included first and headers which it >> implies are not included manually. >> >> This commit was created with scripts/clean-includes. >> >> Changes to standalone programs dropped, because I can't tell whether them >> not using qemu/osdep.h is intentional: >> >> target/hexagon/gen_dectree_import.c >> target/hexagon/gen_semantics.c >> target/hexagon/idef-parser/idef-parser.h >> target/hexagon/idef-parser/parser-helpers.c >> target/hexagon/idef-parser/parser-helpers.h > > Correct. These are standalone programs not built with the full QEMU context. I'll tweak the commit message like this: Changes to standalone programs dropped, because these intentionally don't use qemu/osdep.h: >> Signed-off-by: Markus Armbruster >> --- >> target/hexagon/hex_arch_types.h | 1 - >> target/hexagon/mmvec/macros.h | 1 - >> 2 files changed, 2 deletions(-) > > Reviewed-by: Taylor Simpson Thanks! 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[109.43.177.118]) by smtp.gmail.com with ESMTPSA id u12-20020a05620a430c00b006ee949b8051sm25457987qko.51.2023.01.19.23.24.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Jan 2023 23:24:04 -0800 (PST) Message-ID: <9494369d-a498-81f7-0cd8-1cfe31029c2a@redhat.com> Date: Fri, 20 Jan 2023 08:24:01 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-block@nongnu.org References: <20230111083909.42624-1-philmd@linaro.org> From: Thomas Huth Subject: Re: [PATCH v2 0/4] bulk: Replace TARGET_FMT_plx by HWADDR_PRIx In-Reply-To: <20230111083909.42624-1-philmd@linaro.org> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Language: en-US Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.129.124; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: 36 X-Spam_score: 3.6 X-Spam_bar: +++ X-Spam_report: (3.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.094, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Jan 2023 07:24:22 -0000 On 11/01/2023 09.39, Philippe Mathieu-Daudé wrote: > Since v1: > - Fix checkpatch style violations > - Use HWADDR_PRIx instead of HWADDR_FMT_plx (Zoltan) > > Supersedes: <20230110212947.34557-1-philmd@linaro.org> > "bulk: Rename TARGET_FMT_plx -> HWADDR_FMT_plx" > > Philippe Mathieu-Daudé (4): > hw: Remove hardcoded tabs (code style) > bulk: Coding style fixes > bulk: Replace TARGET_FMT_plx -> HWADDR_PRIx > bulk: Prefix '0x' to hex values displayed with HWADDR_PRIx format Big sorry, I picked up v1 for my last pull request before I saw that there is a v2. But IMHO it's ok to have a separate macro with a %016 included, so I'd rather tend to keep HWADDR_FMT_plx. Anyway, if you consider the other changes in your series important enough, please rebase them. Sorry again for the additional work that this might cause. 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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id r28-20020a056402035c00b0049ebbee7134sm340516edw.94.2023.01.20.01.53.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Jan 2023 01:53:07 -0800 (PST) Date: Fri, 20 Jan 2023 10:53:06 +0100 From: Andrew Jones To: Alistair Francis Cc: Alexandre Ghiti , Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Subject: Re: [PATCH v5 2/2] riscv: Allow user to set the satp mode Message-ID: <20230120095306.yyqq36dliabni3h3@orel> References: <20230113103453.42776-1-alexghiti@rivosinc.com> <20230113103453.42776-3-alexghiti@rivosinc.com> <20230117163138.jze47hjeeuwu2k4j@orel> <20230118121916.6aqj57leen72z5tz@orel> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=ajones@ventanamicro.com; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Jan 2023 09:53:12 -0000 On Fri, Jan 20, 2023 at 09:46:05AM +1000, Alistair Francis wrote: > On Thu, Jan 19, 2023 at 11:00 PM Alexandre Ghiti wrote: > > > > Hi Alistair, Andrew, > > > > On Thu, Jan 19, 2023 at 1:25 AM Alistair Francis wrote: > > > > > > On Wed, Jan 18, 2023 at 10:19 PM Andrew Jones wrote: > > > > > > > > On Wed, Jan 18, 2023 at 10:28:46AM +1000, Alistair Francis wrote: > > > > > On Wed, Jan 18, 2023 at 2:32 AM Andrew Jones wrote: > > > > > > > > > > > > On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote: > > > > ... > > > > > > > + > > > > > > > + /* Get rid of 32-bit/64-bit incompatibility */ > > > > > > > + for (int i = 0; i < 16; ++i) { > > > > > > > + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > > > > > > > > > > > > If we ever define mode=1 for rv64, then 'sv32=on' will be incorrectly > > > > > > accepted as an alias. I think we should simply not define the sv32 > > > > > > property for rv64 nor the rv64-only modes for rv32. So, down in > > > > > > riscv_add_satp_mode_properties() we can add some > > > > > > > > > > > > #if defined(TARGET_RISCV32) > > > > > > ... > > > > > > #elif defined(TARGET_RISCV64) > > > > > > ... > > > > > > #endif > > > > > > > > > > Do not add any #if defined(TARGET_RISCV32) to QEMU. > > > > > > > > > > We are aiming for the riscv64-softmmu to be able to emulate 32-bit > > > > > CPUs and compile time macros are the wrong solution here. Instead you > > > > > can get the xlen of the hart and use that. > > > > > > > > > > > > > Does this mean we want to be able to do the following? > > > > > > > > qemu-system-riscv64 -cpu rv32,sv32=on ... > > > > > > That's the plan > > > > > > > > > > > If so, then can we move the object_property_add() for sv32 to > > > > rv32_base_cpu_init() and the rest to rv64_base_cpu_init()? > > Wait! Sorry I didn't read this carefully enough. No, that is not what > we want to do. That then won't support the vendor CPUs. > > We just want to add the properties to all CPUs. Then if an invalid > option is set we should return an error. > > Note that the 64-bit only configs can be hidden behind a #if > defined(TARGET_RISCV64). OK, so we want the original suggestion of putting an 'if defined(TARGET_RISCV64)' in riscv_add_satp_mode_properties(), which is called from register_cpu_props(), for the 64-bit only configs, but to support emulation we can't put sv32 under an 'if defined(TARGET_RISCV32)'. Instead, we need to check the xlen supported by the cpu type. That makes sense to me, and I think it'd be easiest to do in cpu_riscv_set_satp() with something like if (!strncmp(name, "rv32", 4) && RISCV_CPU(obj)->env.misa_mxl != MXL_RV32) { ... fail with error message ... } Thanks, drew From MAILER-DAEMON Fri Jan 20 07:44:58 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIqlO-0008M8-IO for mharc-qemu-riscv@gnu.org; Fri, 20 Jan 2023 07:44:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIqlM-0008LS-QK for qemu-riscv@nongnu.org; Fri, 20 Jan 2023 07:44:56 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIqlK-0003DU-Sy for qemu-riscv@nongnu.org; Fri, 20 Jan 2023 07:44:56 -0500 Received: by mail-wm1-x32d.google.com with SMTP id c4-20020a1c3504000000b003d9e2f72093so5764233wma.1 for ; Fri, 20 Jan 2023 04:44:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=7dKPT7zZeztEVVbtJ/eXlr1NgI/lK4+/GGJyiR1XdRc=; b=GmfIlS3okrg4vEVz5uh9RrKJRsNo91feo2kcYs6+tK0NQXs/ysu4+4/qwWLos1h/7s 4CLIMpr+AStWQEa+3gKYwq3xJXURMsKf4pyv+k2CU2zwYVACaK/8LwB/kyQByqjoW//x oyxn+WHYAYcPXGsDhcxtj5NkLA0VKd/d+5ZNChBdsfzbQRSFbMH2GKsIwLbtVKX5JyhG 0+g6HY7YfpY7u+cTD0fiYg40Jn0UfbYUA0S+U2f6/FvJMCbJ7aNH6ZZJfkDS4k89h3qB dMo6HGKhpNFuO4qJ9b/4rBRMu4H/tY+m2mGgP8FrR5sd1mn/OmqE9oFamiziIRHqakun tp3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=7dKPT7zZeztEVVbtJ/eXlr1NgI/lK4+/GGJyiR1XdRc=; b=7yRXSnes5udWNRVBAJMvMFZPBT2Zac3MGvdb7J8CDXrStdTQCizjdFdbh4Icsw7YCP 4UxCNGZlA/TgAQis1T9Ek7zNj8LaH31Sz9xbP+lk2zB3vZWGiu//qeteZRF/pbx7sOHW /v0UXERWNcceEbV1loggqHDzqoA6LJWGVu+Oi14WWJWOvmih2hz6WKDb4zPzMVxXoSz9 6kLvULHjTWYfGReAZVrMSKp/Z1IuhYR3vXoyutVDIUbJ/T7GcEEjYNq2bwf6QoIwMr+p j7X7tvKxJGSLzAV0GHk+wsbtbgLFl+QJymxkgiUWiOTVUS1Wx4Y4Od6f8D+eocwFItBZ VplA== X-Gm-Message-State: AFqh2kp1737FO54Ss9plSnA4LVhA36LH9oYBFi+e6ZQU0MKjz7pHv2z7 FXf8UHqFyA2qrpLU5iuZbWAsNpRt90jYbz1oqmsHdQ== X-Google-Smtp-Source: AMrXdXtKGvxbVgintkp4tzFlcw8sMiqTjAo0kr4OoBmIVnicUa1zKfuvN5lT0N7pcThp1Ph4MVaBLc07AlrofzXHMKU= X-Received: by 2002:a05:600c:35c6:b0:3d1:e710:9905 with SMTP id r6-20020a05600c35c600b003d1e7109905mr672093wmq.81.1674218692764; Fri, 20 Jan 2023 04:44:52 -0800 (PST) MIME-Version: 1.0 References: <20230113103453.42776-1-alexghiti@rivosinc.com> <20230113103453.42776-3-alexghiti@rivosinc.com> <20230117163138.jze47hjeeuwu2k4j@orel> <20230118121916.6aqj57leen72z5tz@orel> <20230120095306.yyqq36dliabni3h3@orel> In-Reply-To: <20230120095306.yyqq36dliabni3h3@orel> From: Alexandre Ghiti Date: Fri, 20 Jan 2023 13:44:41 +0100 Message-ID: Subject: Re: [PATCH v5 2/2] riscv: Allow user to set the satp mode To: Andrew Jones Cc: Alistair Francis , Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x32d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Jan 2023 12:44:57 -0000 On Fri, Jan 20, 2023 at 10:53 AM Andrew Jones wrote: > > On Fri, Jan 20, 2023 at 09:46:05AM +1000, Alistair Francis wrote: > > On Thu, Jan 19, 2023 at 11:00 PM Alexandre Ghiti wrote: > > > > > > Hi Alistair, Andrew, > > > > > > On Thu, Jan 19, 2023 at 1:25 AM Alistair Francis wrote: > > > > > > > > On Wed, Jan 18, 2023 at 10:19 PM Andrew Jones wrote: > > > > > > > > > > On Wed, Jan 18, 2023 at 10:28:46AM +1000, Alistair Francis wrote: > > > > > > On Wed, Jan 18, 2023 at 2:32 AM Andrew Jones wrote: > > > > > > > > > > > > > > On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote: > > > > > ... > > > > > > > > + > > > > > > > > + /* Get rid of 32-bit/64-bit incompatibility */ > > > > > > > > + for (int i = 0; i < 16; ++i) { > > > > > > > > + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > > > > > > > > > > > > > > If we ever define mode=1 for rv64, then 'sv32=on' will be incorrectly > > > > > > > accepted as an alias. I think we should simply not define the sv32 > > > > > > > property for rv64 nor the rv64-only modes for rv32. So, down in > > > > > > > riscv_add_satp_mode_properties() we can add some > > > > > > > > > > > > > > #if defined(TARGET_RISCV32) > > > > > > > ... > > > > > > > #elif defined(TARGET_RISCV64) > > > > > > > ... > > > > > > > #endif > > > > > > > > > > > > Do not add any #if defined(TARGET_RISCV32) to QEMU. > > > > > > > > > > > > We are aiming for the riscv64-softmmu to be able to emulate 32-bit > > > > > > CPUs and compile time macros are the wrong solution here. Instead you > > > > > > can get the xlen of the hart and use that. > > > > > > > > > > > > > > > > Does this mean we want to be able to do the following? > > > > > > > > > > qemu-system-riscv64 -cpu rv32,sv32=on ... > > > > > > > > That's the plan > > > > > > > > > > > > > > If so, then can we move the object_property_add() for sv32 to > > > > > rv32_base_cpu_init() and the rest to rv64_base_cpu_init()? > > > > Wait! Sorry I didn't read this carefully enough. No, that is not what > > we want to do. That then won't support the vendor CPUs. > > > > We just want to add the properties to all CPUs. Then if an invalid > > option is set we should return an error. Maybe I just don't get this part... > > > > Note that the 64-bit only configs can be hidden behind a #if > > defined(TARGET_RISCV64). > > OK, so we want the original suggestion of putting an > 'if defined(TARGET_RISCV64)' in riscv_add_satp_mode_properties(), > which is called from register_cpu_props(), for the 64-bit only > configs, but to support emulation we can't put sv32 under an > 'if defined(TARGET_RISCV32)'. Instead, we need to check the xlen > supported by the cpu type. That makes sense to me, and I think > it'd be easiest to do in cpu_riscv_set_satp() with something like > > if (!strncmp(name, "rv32", 4) && > RISCV_CPU(obj)->env.misa_mxl != MXL_RV32) { > ... fail with error message ... > } > ...but what about simply using the runtime check when we add the properties? Like this: static void riscv_add_satp_mode_properties(Object *obj) { RISCVCPU *cpu = RISCV_CPU(obj); if (cpu->env.misa_mxl == MXL_RV32) { object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); } else { object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); } } > Thanks, > drew From MAILER-DAEMON Fri Jan 20 08:00:19 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIr07-0007LX-QG for mharc-qemu-riscv@gnu.org; Fri, 20 Jan 2023 08:00:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIr05-0007L0-3m for qemu-riscv@nongnu.org; Fri, 20 Jan 2023 08:00:09 -0500 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIr03-0006FF-Cq for qemu-riscv@nongnu.org; Fri, 20 Jan 2023 08:00:08 -0500 Received: by mail-pj1-x1034.google.com with SMTP id k10-20020a17090a590a00b0022ba875a1a4so1990852pji.3 for ; Fri, 20 Jan 2023 05:00:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=a3DHMQ6hzTLjlt39P1qRoArzmXvZXOpc2fIYrcZ1leU=; b=ecJSeHZTsl0ncMlkCpTbc69ElJ4W75LR+gU2idRc42qZlVWFbS9y9AkTm0kURJNrRo aERj1SZ0O//FzSU5M8k1LnwQK7j/UH0ajqe2Y1ZvdB5tyv8uYS5mJgmg8SwBoOs91ohH 0ro3modS1X17QGD//5H10pWDRnRRmetmjYA5z8/o1YTVSHHM+njQV3w1+Q5ew8BgPZaD 0+PYtcbxWI49ZbNe1OWa7j3lmpz8FJ8ufEMrB1dqjI8smDxjiTieATsgePlxv7wFC5sU YQ6c3VcLpd6eOqRYvYHZUQjBAJXmj4XgadNfrBOuA0SGoURCbn2vrVtEBzsE6uieqTP2 FLag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=a3DHMQ6hzTLjlt39P1qRoArzmXvZXOpc2fIYrcZ1leU=; b=xeN6Td0tzHqikWLaEcJV9SJHaAclOFISBlnhq2LLR9jIrVRmpTiIIQeIfFRwXAe89V movFRqeRzh+xAjy45XkidGoGUyUe2IGjdUqn4S9BKvoo8XvepZNhSaialTeOV4vEjV4G xHNW963KqUbyRrLcM5PDjsUGn5V07upaENnv1DUwbbCsVgdSdij2tfCAFLIlKBOCFA6a lgoCz7IoJDqVpeEzngJGrUOwvCYyp+o822YmNnh/HLydA1DLuxZqN0W/3NtWiRF6FGbR WLMRst3HPhTRF/8Y75bpe6CfqW7jhBhDcKP3Hm6lCaTouFcmcICn/GqY5N5yx8VU8CNq EYTA== X-Gm-Message-State: AFqh2krMYuA7I+lNhL8ZV26Ny3Dx8vCmzgVVTwCzBRa8azBzthSAkv+k DvZaGBuCz1+pj5sOigJGdXKv9A== X-Google-Smtp-Source: AMrXdXvlTy8T+lSISiRXS+xvGooOLpQjzzuim2By6MhwcbbjhTYU9tryrrdfYRtT2jJkOXd5D+vZ3Q== X-Received: by 2002:a17:903:32c8:b0:194:de51:9af with SMTP id i8-20020a17090332c800b00194de5109afmr4206405plr.22.1674219604474; Fri, 20 Jan 2023 05:00:04 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id u7-20020a170902e5c700b0017f72a430adsm7279610plf.71.2023.01.20.05.00.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Jan 2023 05:00:03 -0800 (PST) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Richard Henderson , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH v3 0/4] Nested virtualization fixes for QEMU Date: Fri, 20 Jan 2023 18:29:46 +0530 Message-Id: <20230120125950.2246378-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=apatel@ventanamicro.com; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Jan 2023 13:00:09 -0000 This series mainly includes fixes discovered while developing nested virtualization running on QEMU. These patches can also be found in the riscv_nested_fixes_v3 branch at: https://github.com/avpatel/qemu.git Changes since v2: - Dropped PATCH1 since it is already merged - Rebased on latest riscv-to-apply.next branch of Alistair Changes since v1: - Added Alistair's Reviewed-by tags to appropriate patches - Added detailed comment block in PATCH4 Anup Patel (4): target/riscv: Update VS timer whenever htimedelta changes target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX target/riscv: Ensure opcode is saved for all relevant instructions target/riscv/cpu_helper.c | 2 -- target/riscv/csr.c | 16 +++++++++ target/riscv/insn_trans/trans_rva.c.inc | 10 ++++-- target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvh.c.inc | 3 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ target/riscv/insn_trans/trans_rvzfh.c.inc | 2 ++ target/riscv/insn_trans/trans_svinval.c.inc | 3 ++ target/riscv/time_helper.c | 36 ++++++++++++++++++--- 10 files changed, 69 insertions(+), 9 deletions(-) -- 2.34.1 From MAILER-DAEMON Fri Jan 20 08:00:23 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIr0J-0007NO-Nr for mharc-qemu-riscv@gnu.org; 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Fri, 20 Jan 2023 05:00:08 -0800 (PST) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Richard Henderson , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Alistair Francis Subject: [PATCH v3 1/4] target/riscv: Update VS timer whenever htimedelta changes Date: Fri, 20 Jan 2023 18:29:47 +0530 Message-Id: <20230120125950.2246378-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230120125950.2246378-1-apatel@ventanamicro.com> References: <20230120125950.2246378-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=apatel@ventanamicro.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Jan 2023 13:00:19 -0000 The htimedelta[h] CSR has impact on the VS timer comparison so we should call riscv_timer_write_timecmp() whenever htimedelta changes. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/csr.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 62e6c4acbd..fa17d7770c 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3045,6 +3045,8 @@ static RISCVException read_htimedelta(CPURISCVState *env, int csrno, static RISCVException write_htimedelta(CPURISCVState *env, int csrno, target_ulong val) { + RISCVCPU *cpu = env_archcpu(env); + if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; } @@ -3054,6 +3056,12 @@ static RISCVException write_htimedelta(CPURISCVState *env, int csrno, } else { env->htimedelta = val; } + + if (cpu->cfg.ext_sstc && env->rdtime_fn) { + riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp, + env->htimedelta, MIP_VSTIP); + } + return RISCV_EXCP_NONE; } @@ -3071,11 +3079,19 @@ static RISCVException read_htimedeltah(CPURISCVState *env, int csrno, static RISCVException write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val) { + RISCVCPU *cpu = env_archcpu(env); + if (!env->rdtime_fn) { return RISCV_EXCP_ILLEGAL_INST; } env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val); + + if (cpu->cfg.ext_sstc && env->rdtime_fn) { + riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp, + env->htimedelta, MIP_VSTIP); + } + return RISCV_EXCP_NONE; } -- 2.34.1 From MAILER-DAEMON Fri Jan 20 08:00:24 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIr0J-0007NX-Tm for mharc-qemu-riscv@gnu.org; Fri, 20 Jan 2023 08:00:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIr0G-0007ML-UU for qemu-riscv@nongnu.org; Fri, 20 Jan 2023 08:00:22 -0500 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIr0D-0006HD-ND for qemu-riscv@nongnu.org; Fri, 20 Jan 2023 08:00:20 -0500 Received: by mail-pj1-x1029.google.com with SMTP id z4-20020a17090a170400b00226d331390cso4798564pjd.5 for ; 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Fri, 20 Jan 2023 05:00:14 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id u7-20020a170902e5c700b0017f72a430adsm7279610plf.71.2023.01.20.05.00.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Jan 2023 05:00:13 -0800 (PST) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Richard Henderson , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Alistair Francis Subject: [PATCH v3 2/4] target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP Date: Fri, 20 Jan 2023 18:29:48 +0530 Message-Id: <20230120125950.2246378-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230120125950.2246378-1-apatel@ventanamicro.com> References: <20230120125950.2246378-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=apatel@ventanamicro.com; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Jan 2023 13:00:22 -0000 Instead of clearing mask in riscv_cpu_update_mip() for VSTIP, we should call riscv_cpu_update_mip() with mask == 0 from timer_helper.c for VSTIP. Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor") Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 2 -- target/riscv/time_helper.c | 12 ++++++++---- 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 8ea3442b4a..84f84b2bae 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -621,8 +621,6 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value) vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; } - /* No need to update mip for VSTIP */ - mask = ((mask == MIP_VSTIP) && env->vstime_irq) ? 0 : mask; vstip = env->vstime_irq ? MIP_VSTIP : 0; QEMU_IOTHREAD_LOCK_GUARD(); diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index 8cce667dfd..4fb2a471a9 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -27,7 +27,7 @@ static void riscv_vstimer_cb(void *opaque) RISCVCPU *cpu = opaque; CPURISCVState *env = &cpu->env; env->vstime_irq = 1; - riscv_cpu_update_mip(cpu, MIP_VSTIP, BOOL_TO_MASK(1)); + riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1)); } static void riscv_stimer_cb(void *opaque) @@ -57,16 +57,20 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer, */ if (timer_irq == MIP_VSTIP) { env->vstime_irq = 1; + riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(1)); + } else { + riscv_cpu_update_mip(cpu, MIP_STIP, BOOL_TO_MASK(1)); } - riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(1)); return; } + /* Clear the [VS|S]TIP bit in mip */ if (timer_irq == MIP_VSTIP) { env->vstime_irq = 0; + riscv_cpu_update_mip(cpu, 0, BOOL_TO_MASK(0)); + } else { + riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); } - /* Clear the [V]STIP bit in mip */ - riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); /* otherwise, set up the future timer interrupt */ diff = timecmp - rtc_r; -- 2.34.1 From MAILER-DAEMON Fri Jan 20 08:00:28 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIr0M-0007OU-05 for mharc-qemu-riscv@gnu.org; Fri, 20 Jan 2023 08:00:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIr0I-0007Mh-Qt for qemu-riscv@nongnu.org; Fri, 20 Jan 2023 08:00:22 -0500 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIr0G-0006Hg-UZ for qemu-riscv@nongnu.org; Fri, 20 Jan 2023 08:00:22 -0500 Received: by mail-pj1-x102f.google.com with SMTP id x2-20020a17090a46c200b002295ca9855aso8995430pjg.2 for ; Fri, 20 Jan 2023 05:00:20 -0800 (PST) DKIM-Signature: v=1; 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Fri, 20 Jan 2023 05:00:18 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id u7-20020a170902e5c700b0017f72a430adsm7279610plf.71.2023.01.20.05.00.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Jan 2023 05:00:18 -0800 (PST) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Richard Henderson , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Alistair Francis Subject: [PATCH v3 3/4] target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX Date: Fri, 20 Jan 2023 18:29:49 +0530 Message-Id: <20230120125950.2246378-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230120125950.2246378-1-apatel@ventanamicro.com> References: <20230120125950.2246378-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=apatel@ventanamicro.com; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Jan 2023 13:00:23 -0000 The time CSR will wrap-around immediately after reaching UINT64_MAX so we don't need to re-start QEMU timer when timecmp == UINT64_MAX in riscv_timer_write_timecmp(). Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/time_helper.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index 4fb2a471a9..b654f91af9 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -72,6 +72,30 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer *timer, riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); } + /* + * Sstc specification says the following about timer interrupt: + * "A supervisor timer interrupt becomes pending - as reflected in + * the STIP bit in the mip and sip registers - whenever time contains + * a value greater than or equal to stimecmp, treating the values + * as unsigned integers. Writes to stimecmp are guaranteed to be + * reflected in STIP eventually, but not necessarily immediately. + * The interrupt remains posted until stimecmp becomes greater + * than time - typically as a result of writing stimecmp." + * + * When timecmp = UINT64_MAX, the time CSR will eventually reach + * timecmp value but on next timer tick the time CSR will wrap-around + * and become zero which is less than UINT64_MAX. Now, the timer + * interrupt behaves like a level triggered interrupt so it will + * become 1 when time = timecmp = UINT64_MAX and next timer tick + * it will become 0 again because time = 0 < timecmp = UINT64_MAX. + * + * Based on above, we don't re-start the QEMU timer when timecmp + * equals UINT64_MAX. + */ + if (timecmp == UINT64_MAX) { + return; + } + /* otherwise, set up the future timer interrupt */ diff = timecmp - rtc_r; /* back to ns (note args switched in muldiv64) */ -- 2.34.1 From MAILER-DAEMON Fri Jan 20 08:00:33 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIr0S-0007Rs-2g for mharc-qemu-riscv@gnu.org; Fri, 20 Jan 2023 08:00:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIr0N-0007QQ-KH for qemu-riscv@nongnu.org; Fri, 20 Jan 2023 08:00:28 -0500 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pIr0L-0006Ja-IB for qemu-riscv@nongnu.org; Fri, 20 Jan 2023 08:00:27 -0500 Received: by mail-pj1-x1031.google.com with SMTP id h5-20020a17090a9c0500b0022bb85eb35dso420804pjp.3 for ; Fri, 20 Jan 2023 05:00:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UXFj+TsARYhyAgQ44IDyO3msxHENfQx3g7RXDPoLpl8=; b=fFXzg6IfJFbd54MhU8YS0nZbsBNgGnZasdpbRAVJcLSZKlpnw0MW5/5bQIFg8BblFk 0LEDEyasyRTnF29ZoRxXFI1y+pv/sa7hYn3QiiRJz1uiF035ax6WA2B7IcXyVj6ji/UF 10b1kGoOG54B4k1jY1heu1AW5sqdSfazsRo87S6100nTqxrhUEx6eNBSQ61pwLXrseHc a3CEInwIYki4KGcr7+MB7QsLc1SsnGmXvhE0wN3SR2atz2VfGv+WN54JYqcV8g86+qVE AxSJGnoWj22WrOI1XSb0AdXltXOgisx2XixFffIvG/N8ZLe2q9pgdTMwjRBumz2w9Xea ds1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UXFj+TsARYhyAgQ44IDyO3msxHENfQx3g7RXDPoLpl8=; b=3zOw/3KY2sLXeDpsjYSMxnTpNZbwTyTvCfQHACLCLf91KnR+Ycwyk+xbff+MxYqRm0 zxgzpqB2km8QHowQMFQ4lZyR1gH25R1a6exdoO/9oX/iS4H0RBavNcBo60eJfNLfk7ep oW55+JMcOc2Ele0LgD6QIui/x49ddPqaH5ZZvFDcdQTUYxltduiu4Semdnyh8QRBZB2L WW/ero1gpjq6LmMbPDHIbL8xdWpJVOZLPFl4a3jjsNWskididoHmXc6tCRHtWQMRNX+o ONar635juakOPKBVJifUtftPqOV8RceVTWgS6XDIkIAmp6hUtBClO2MxyhTLkcUoytJe Uweg== X-Gm-Message-State: AFqh2krCLnqvnnWd33z6QWaB2v9Z5OIawAD27ZmdAhxdgvMZemhi+1oP 8/HeWM/J8kGdbx17vRLlahh+1g== X-Google-Smtp-Source: AMrXdXuA2FNidxqpWO+6f8WMO+OiA2gfBsF33p6oUoJb6qofsQmMX0coaat1P5Le6e4xAMMsZJfcVg== X-Received: by 2002:a05:6a21:32a6:b0:a7:9022:5d5e with SMTP id yt38-20020a056a2132a600b000a790225d5emr20327875pzb.2.1674219623704; Fri, 20 Jan 2023 05:00:23 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id u7-20020a170902e5c700b0017f72a430adsm7279610plf.71.2023.01.20.05.00.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Jan 2023 05:00:23 -0800 (PST) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Richard Henderson , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH v3 4/4] target/riscv: Ensure opcode is saved for all relevant instructions Date: Fri, 20 Jan 2023 18:29:50 +0530 Message-Id: <20230120125950.2246378-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230120125950.2246378-1-apatel@ventanamicro.com> References: <20230120125950.2246378-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=apatel@ventanamicro.com; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Jan 2023 13:00:28 -0000 We should call decode_save_opc() for all relevant instructions which can potentially generate a virtual instruction fault or a guest page fault because generating transformed instruction upon guest page fault expects opcode to be available. Without this, hypervisor will see transformed instruction as zero in htinst CSR for guest MMIO emulation which makes MMIO emulation in hypervisor slow and also breaks nested virtualization. Fixes: a9814e3e08d2 ("target/riscv: Minimize the calls to decode_save_opc") Signed-off-by: Anup Patel --- target/riscv/insn_trans/trans_rva.c.inc | 10 +++++++--- target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvh.c.inc | 3 +++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ target/riscv/insn_trans/trans_rvzfh.c.inc | 2 ++ target/riscv/insn_trans/trans_svinval.c.inc | 3 +++ 7 files changed, 21 insertions(+), 3 deletions(-) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc index 45db82c9be..5f194a447b 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -20,8 +20,10 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) { - TCGv src1 = get_address(ctx, a->rs1, 0); + TCGv src1; + decode_save_opc(ctx); + src1 = get_address(ctx, a->rs1, 0); if (a->rl) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } @@ -43,6 +45,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop) TCGLabel *l1 = gen_new_label(); TCGLabel *l2 = gen_new_label(); + decode_save_opc(ctx); src1 = get_address(ctx, a->rs1, 0); tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); @@ -81,9 +84,10 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, MemOp mop) { TCGv dest = dest_gpr(ctx, a->rd); - TCGv src1 = get_address(ctx, a->rs1, 0); - TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); + TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE); + decode_save_opc(ctx); + src1 = get_address(ctx, a->rs1, 0); func(dest, src1, src2, ctx->mem_idx, mop); gen_set_gpr(ctx, a->rd, dest); diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc index 1397c1ce1c..6e3159b797 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -38,6 +38,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + decode_save_opc(ctx); addr = get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEUQ); @@ -52,6 +53,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVD); + decode_save_opc(ctx); addr = get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUQ); return true; diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc index a1d3eb52ad..965e1f8d11 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -38,6 +38,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + decode_save_opc(ctx); addr = get_address(ctx, a->rs1, a->imm); dest = cpu_fpr[a->rd]; tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL); @@ -54,6 +55,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) REQUIRE_FPU; REQUIRE_EXT(ctx, RVF); + decode_save_opc(ctx); addr = get_address(ctx, a->rs1, a->imm); tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL); return true; diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc index 4f8aecddc7..9248b48c36 100644 --- a/target/riscv/insn_trans/trans_rvh.c.inc +++ b/target/riscv/insn_trans/trans_rvh.c.inc @@ -36,6 +36,7 @@ static bool do_hlv(DisasContext *ctx, arg_r2 *a, MemOp mop) #ifdef CONFIG_USER_ONLY return false; #else + decode_save_opc(ctx); if (check_access(ctx)) { TCGv dest = dest_gpr(ctx, a->rd); TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); @@ -82,6 +83,7 @@ static bool do_hsv(DisasContext *ctx, arg_r2_s *a, MemOp mop) #ifdef CONFIG_USER_ONLY return false; #else + decode_save_opc(ctx); if (check_access(ctx)) { TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); TCGv data = get_gpr(ctx, a->rs2, EXT_NONE); @@ -135,6 +137,7 @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) static bool do_hlvx(DisasContext *ctx, arg_r2 *a, void (*func)(TCGv, TCGv_env, TCGv)) { + decode_save_opc(ctx); if (check_access(ctx)) { TCGv dest = dest_gpr(ctx, a->rd); TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index 5c69b88d1e..4496f21266 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -261,6 +261,7 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop) static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) { + decode_save_opc(ctx); if (get_xl(ctx) == MXL_RV128) { return gen_load_i128(ctx, a, memop); } else { @@ -350,6 +351,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop) static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) { + decode_save_opc(ctx); if (get_xl(ctx) == MXL_RV128) { return gen_store_i128(ctx, a, memop); } else { diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc index 5d07150cd0..2ad5716312 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -49,6 +49,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a) REQUIRE_FPU; REQUIRE_ZFH_OR_ZFHMIN(ctx); + decode_save_opc(ctx); t0 = get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { TCGv temp = temp_new(ctx); @@ -71,6 +72,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a) REQUIRE_FPU; REQUIRE_ZFH_OR_ZFHMIN(ctx); + decode_save_opc(ctx); t0 = get_gpr(ctx, a->rs1, EXT_NONE); if (a->imm) { TCGv temp = tcg_temp_new(); diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc index 2682bd969f..f3cd7d5c0b 100644 --- a/target/riscv/insn_trans/trans_svinval.c.inc +++ b/target/riscv/insn_trans/trans_svinval.c.inc @@ -28,6 +28,7 @@ static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a) /* Do the same as sfence.vma currently */ REQUIRE_EXT(ctx, RVS); #ifndef CONFIG_USER_ONLY + decode_save_opc(ctx); gen_helper_tlb_flush(cpu_env); return true; #endif @@ -56,6 +57,7 @@ static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a) /* Do the same as hfence.vvma currently */ REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY + decode_save_opc(ctx); gen_helper_hyp_tlb_flush(cpu_env); return true; #endif @@ -68,6 +70,7 @@ static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a) /* Do the same as hfence.gvma currently */ REQUIRE_EXT(ctx, RVH); #ifndef CONFIG_USER_ONLY + decode_save_opc(ctx); gen_helper_hyp_gvma_tlb_flush(cpu_env); return true; #endif -- 2.34.1 From MAILER-DAEMON Fri Jan 20 08:26:28 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pIrPX-0000Ne-QE for mharc-qemu-riscv@gnu.org; Fri, 20 Jan 2023 08:26:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pIrOl-0008LM-FM for qemu-riscv@nongnu.org; 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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id g8-20020aa7d1c8000000b0049e1f167956sm6416743edp.9.2023.01.20.05.25.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Jan 2023 05:25:33 -0800 (PST) Date: Fri, 20 Jan 2023 14:25:32 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Alistair Francis , Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Subject: Re: [PATCH v5 2/2] riscv: Allow user to set the satp mode Message-ID: <20230120132532.n5inawnb3odhy7ik@orel> References: <20230113103453.42776-1-alexghiti@rivosinc.com> <20230113103453.42776-3-alexghiti@rivosinc.com> <20230117163138.jze47hjeeuwu2k4j@orel> <20230118121916.6aqj57leen72z5tz@orel> <20230120095306.yyqq36dliabni3h3@orel> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=ajones@ventanamicro.com; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Jan 2023 13:26:09 -0000 On Fri, Jan 20, 2023 at 01:44:41PM +0100, Alexandre Ghiti wrote: > On Fri, Jan 20, 2023 at 10:53 AM Andrew Jones wrote: > > > > On Fri, Jan 20, 2023 at 09:46:05AM +1000, Alistair Francis wrote: > > > On Thu, Jan 19, 2023 at 11:00 PM Alexandre Ghiti wrote: > > > > > > > > Hi Alistair, Andrew, > > > > > > > > On Thu, Jan 19, 2023 at 1:25 AM Alistair Francis wrote: > > > > > > > > > > On Wed, Jan 18, 2023 at 10:19 PM Andrew Jones wrote: > > > > > > > > > > > > On Wed, Jan 18, 2023 at 10:28:46AM +1000, Alistair Francis wrote: > > > > > > > On Wed, Jan 18, 2023 at 2:32 AM Andrew Jones wrote: > > > > > > > > > > > > > > > > On Fri, Jan 13, 2023 at 11:34:53AM +0100, Alexandre Ghiti wrote: > > > > > > ... > > > > > > > > > + > > > > > > > > > + /* Get rid of 32-bit/64-bit incompatibility */ > > > > > > > > > + for (int i = 0; i < 16; ++i) { > > > > > > > > > + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > > > > > > > > > > > > > > > > If we ever define mode=1 for rv64, then 'sv32=on' will be incorrectly > > > > > > > > accepted as an alias. I think we should simply not define the sv32 > > > > > > > > property for rv64 nor the rv64-only modes for rv32. So, down in > > > > > > > > riscv_add_satp_mode_properties() we can add some > > > > > > > > > > > > > > > > #if defined(TARGET_RISCV32) > > > > > > > > ... > > > > > > > > #elif defined(TARGET_RISCV64) > > > > > > > > ... > > > > > > > > #endif > > > > > > > > > > > > > > Do not add any #if defined(TARGET_RISCV32) to QEMU. > > > > > > > > > > > > > > We are aiming for the riscv64-softmmu to be able to emulate 32-bit > > > > > > > CPUs and compile time macros are the wrong solution here. Instead you > > > > > > > can get the xlen of the hart and use that. > > > > > > > > > > > > > > > > > > > Does this mean we want to be able to do the following? > > > > > > > > > > > > qemu-system-riscv64 -cpu rv32,sv32=on ... > > > > > > > > > > That's the plan > > > > > > > > > > > > > > > > > If so, then can we move the object_property_add() for sv32 to > > > > > > rv32_base_cpu_init() and the rest to rv64_base_cpu_init()? > > > > > > Wait! Sorry I didn't read this carefully enough. No, that is not what > > > we want to do. That then won't support the vendor CPUs. > > > > > > We just want to add the properties to all CPUs. Then if an invalid > > > option is set we should return an error. > > Maybe I just don't get this part... Indeed, I like not adding the property at all over adding it and then complaining when it's used. Your solution below looks good to me and would be my preference as well. Thanks, drew > > > > > > > Note that the 64-bit only configs can be hidden behind a #if > > > defined(TARGET_RISCV64). > > > > OK, so we want the original suggestion of putting an > > 'if defined(TARGET_RISCV64)' in riscv_add_satp_mode_properties(), > > which is called from register_cpu_props(), for the 64-bit only > > configs, but to support emulation we can't put sv32 under an > > 'if defined(TARGET_RISCV32)'. Instead, we need to check the xlen > > supported by the cpu type. That makes sense to me, and I think > > it'd be easiest to do in cpu_riscv_set_satp() with something like > > > > if (!strncmp(name, "rv32", 4) && > > RISCV_CPU(obj)->env.misa_mxl != MXL_RV32) { > > ... fail with error message ... > > } > > > > ...but what about simply using the runtime check when we add the > properties? Like this: > > static void riscv_add_satp_mode_properties(Object *obj) > { > RISCVCPU *cpu = RISCV_CPU(obj); > > if (cpu->env.misa_mxl == MXL_RV32) { > object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, > cpu_riscv_set_satp, NULL, > &cpu->cfg.satp_mode); > } else { > object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, > cpu_riscv_set_satp, NULL, > &cpu->cfg.satp_mode); > object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, > cpu_riscv_set_satp, NULL, > &cpu->cfg.satp_mode); > object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, > cpu_riscv_set_satp, NULL, > &cpu->cfg.satp_mode); > object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, > cpu_riscv_set_satp, NULL, > &cpu->cfg.satp_mode); > } > } > > > Thanks, > > drew From MAILER-DAEMON Sat Jan 21 14:05:59 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJJBf-0001tr-64 for mharc-qemu-riscv@gnu.org; Sat, 21 Jan 2023 14:05:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJJBd-0001tj-UJ for qemu-riscv@nongnu.org; Sat, 21 Jan 2023 14:05:57 -0500 Received: from mail-qt1-x842.google.com ([2607:f8b0:4864:20::842]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJJBb-00032W-64 for qemu-riscv@nongnu.org; Sat, 21 Jan 2023 14:05:57 -0500 Received: by mail-qt1-x842.google.com with SMTP id h24so2817573qta.12 for ; Sat, 21 Jan 2023 11:05:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=1OIV7/IWjD2Q2PsX3VRFNxg4ZxzK66CWQ/k2Sv1g7nM=; b=fE6do+b5aYr5zzl7KjN64RXBki8SfWQ3XeuXb83wKI/340TZ/a9DGb+Nd6796Nuv5D BUJvEv+jr2wGZObStz+1Ad7ceC4is+fR3YiB0wD2w3miLmqLeVN/y0BVScMwfgRIK3Xh O851nbjIPIC/h1bQyGEZdrV7VWlSa+p+elbgIWHvGEm5gkPs9bRibTis9q26fzTtFZ2R c2PVAtFbuXBXEbWui2abEldXWDENe19u0dRaQRfN6Up4TKLw88TEgN+xHQtYzhPjlZG8 VtaroG/bmSl6Kg5UaLd2HvThtBEBpPCdehGnfURlKDwbGNm3N2PM/52EIhHpS9BTBvnU o9mQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=1OIV7/IWjD2Q2PsX3VRFNxg4ZxzK66CWQ/k2Sv1g7nM=; b=5cB2aEMVlKxthKO33SvpLtwEGgJiEfJ+j0e4bqlEk3q2mzjnKxNAP7HKZNvlHcrec7 8mIi6wD0fbSU+trtTIR7fS8hEDLLOv4/X8sOIL+3ZD2AMFnUa3UZSesBOE7Pg54mQrwj 8wnMM1ogc/D0s9tSJo/6d5U7pW5HaJlwznzBFuZwMcP7AoOUJ1hLSKGAXJxQLBMo2FYQ UByj2QBkrA49HFJXNz3LMQWjK31YBPCBSfoLl/soitFaprNLKApfev/E6v1llpDYNJn5 TLqnwUisFv4pcK1YB61114MnbHp5wbx5KaUYd6zGcRxJuYIQzUt1/hz/strVv2Y7dyiG 2Y9g== X-Gm-Message-State: AFqh2koYLDehiFOFRONmnKzCUik8wPQBQDBTcNxcHfAoBpkVXPKL6HeN uWWQfB6DQBheq4vthTv6Ry56pNalZxyHCOdFOjE= X-Google-Smtp-Source: AMrXdXtYWXZhk9+bUeKXy/7KicnSDVdO2IZae0ds1nYxVjckRDrncZZJuHw2t59/XvfLb61C9AJKKw== X-Received: by 2002:aca:2b13:0:b0:355:1e71:768 with SMTP id i19-20020aca2b13000000b003551e710768mr8593232oik.39.1674323903693; Sat, 21 Jan 2023 09:58:23 -0800 (PST) Received: from [192.168.68.107] ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id l16-20020a9d7a90000000b0068682fc91a1sm3292784otn.39.2023.01.21.09.58.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 21 Jan 2023 09:58:23 -0800 (PST) Message-ID: <385b977b-d15f-6c54-1d05-ab68e122dfe8@ventanamicro.com> Date: Sat, 21 Jan 2023 14:58:19 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH v3 3/7] hw/riscv/microchip_pfsoc.c: add an Icicle Kit fdt address function Content-Language: en-US To: Conor Dooley Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com References: <20230119191728.622081-1-dbarboza@ventanamicro.com> <20230119191728.622081-4-dbarboza@ventanamicro.com> From: Daniel Henrique Barboza In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::842; envelope-from=dbarboza@ventanamicro.com; helo=mail-qt1-x842.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.092, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 21 Jan 2023 19:05:58 -0000 Conor, Thanks for the Icicle-kit walk-through! I'll not claim that I fully understood it, but I understood enough to handle the situation ATM. Without this change, this is where the FDT is being installed in the board when I start it with 8Gb of RAM (retrieved via 'info roms'): addr=00000000bfe00000 size=0x00a720 mem=ram name="fdt" Which surprised me at first because this is almost at the end of the LO area which has 1Gb and I figured it would be in the middle of another RAM area. I took another read at what we're doing in riscv_load_fdt(): ----------- temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); ----------- This code can be read as "if the starting address of the RAM is lower than 3Gb, put the FDT no further than 3Gb (0xc0000000). Otherwise, put it at the end of dram", where "dram_base" is the starting address of the RAM block that the function receives. For icicle-kit, this is being passed as memmap[MICROCHIP_PFSOC_DRAM_LO].base, 0x80000000, which is 2Gb. So, regardless of how much RAM we have (dram_end), the FDT will always be capped at 3Gb. At this moment, this fits exactly at the end of the LO area for the Icicle Kit. Which is funny because this 3Gb restriction was added by commit 1a475d39ef54 to fix 32 bit guest boot and it happened to also work for the Microchip SoC. So yeah, I thought that I was fixing a bug and in the end I caused one. This patch needs to go. Alistair, I believe I should re-send v2, this time explaining why the existing function will not break the Microchip board because we'll never put the FDT out of the LO area of the board. Does this work for you? Conor, one more thing: On 1/19/23 21:15, Conor Dooley wrote: > Hey Daniel, > > Got through the stuff I wanted to get done tonight faster than > expected... > > On Thu, Jan 19, 2023 at 05:17:33PM -0300, Daniel Henrique Barboza wrote: >> Are you testing it by using the command line >> you mentioned in the "qemu icicle kit es" thread? >> >> $(QEMU)/qemu-system-riscv64 \ >> -M microchip-icicle-kit \ >> -m 2G -smp 5 \ >> -kernel $(vmlinux_bin) \ >> -dtb $(devkit).dtb \ >> -initrd $(initramfs) \ >> -display none \ >> -serial null \ >> -serial stdio > > Yah, effectively. It's not quite that, but near enough as makes no real > difference: > qemu-icicle: > $(QEMU)/qemu-system-riscv64 -M microchip-icicle-kit \ > -m 2G -smp 5 \ > -kernel $(vmlinux_bin) \ > -dtb $(wrkdir)/riscvpc.dtb \ > -initrd $(initramfs) \ > -display none -serial null \ > -serial stdio \ > -D qemu.log -d unimp > > I just tried to make things somewhat more intelligible for that thread. I tried it out with kernel v6.0.0 (I saw you mentioning in the other thread that this was the latest kernel you were able to boot this way) and it booted up until the kernel complained about missing initramfs. Any tips on how I can build an initrd disk for the board? Thanks, Daniel > > Also in case it is not obvious, I do work for Microchip. As I mentioned > to Alistair at LPC, I/we don't have the cycles at the moment to do > anything with QEMU, so the bits of fixes I have sent are things I fixed > while debugging other issues etc, mostly in the evenings. > > Anways, I'll attempt to explain what the craic is here.. > > On Thu, Jan 19, 2023 at 04:17:24PM -0300, Daniel Henrique Barboza wrote: >> The Icicle Kit board works with 2 distinct RAM banks that are separated > > Ehh, 2 isn't really true. There are 6 possible "windows" into the DDR on > MPFS, list here as with their start addresses. > > 32-bit cached 0x0080000000 > 64-bit cached 0x1000000000 > 32-bit non-cached 0x00c0000000 > 64-bit non-cached 0x1400000000 > 32-bit WCB 0x00d0000000 > 64-bit WCB 0x1800000000 > > These are the "bus" addresses, where the harts think the memory is, but > the memory is not actually connected there. There are some runtime > configurable registers which determine what addresses these correspond > to in the DDR itself. > > When the QEMU port for MPFS was written, only two of these were in use, > the 32-bit and 64-bit non-cached regions. The config (seg) registers > were set up so that the 32-bit cached region pointed to 0x0 in DDR and > the 64-bit region pointed to 0x3000_0000 in DDR. > ⢰⠒⠒⠒⠒⡖⠒⠒⠒⣶⠒0x80000000 > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ ⡇ > ⢸⡖⠒⠒⢲⡇ ⡇ 0x40000000 > ⢸⡇ ⢸⡇ ⡇ ⡇ > ⢸⡇ ⢸⠓⠒⠒⠒⠃ ⡇ <-- 64-bit starts here > ⢸⡇ ⢸ ⡇ > ⢸⡇ ⢸ ⡇ > ⢸⡇ ⢸ ⡇ > ⢸⡇ ⢸ ⡇ > ⢸⡇ ⢸ ⡇ <-- 32-bit starts at 0x0 > ⠘⠓⠒0⠚⠒⠒1⠒⠒⠒0x00000000 > > (These diagrams are a bit crap, I'm copy pasting them from a TUI tool > for visualising these I made for myself. The ~s can be ignored. > https://github.com/ConchuOD/memory-aperature-configurator) > >> by a gap. We have a lower bank with 1GiB size, a gap follows, >> then at 64GiB the high memory starts. > > As you correctly pointed out, that lower region is in fact 1 GiB & hence > there is actually an overlapping region of 256 MiB. > > The Devicetree at this point in time looked like: > ddrc_cache_lo: memory@80000000 { > device_type = "memory"; > reg = <0x0 0x80000000 0x0 0x30000000>; > clocks = <&clkcfg CLK_DDRC>; > status = "okay"; > }; > > ddrc_cache_hi: memory@1000000000 { > device_type = "memory"; > reg = <0x10 0x0 0x0 0x40000000>; > clocks = <&clkcfg CLK_DDRC>; > status = "okay"; > }; > > At some point, it was decided that instead we would use a configuration > with ~no memory at 32-bit addresses. I think it was this one here: > > ⢰⡖⠒⠒⢲⡖⠒⠒⠒⣶⠒0x80000000 > ⢸⡇ ⢸⡇ ⣿ ⡇ > ⢸⠓⠒⠒⠚⡇ ⡟ ⡇ <-- 32-bit starts here > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ 0x40000000 > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ ⡇ <-- 64-bit starts at 0x0 > ⠘⠒⠒0⠒⠓⠒1⠒⠓⠒0x00000000 > > Because of how these windows work, the 32-bit cached region was always > there, just not used as the Devicetree became: > ddrc_cache: memory@1000000000 { > device_type = "memory"; > reg = <0x10 0x0 0x0 0x76000000>; > status = "okay"; > }; > > The remaining bit of memory is being used for some WCB buffers etc & > not for the OS itself. This was never upstreamed anywhere AFAIK as it > was a workaround. > > The current Devicetree in Linux & U-Boot corresponds to a configuration > like: > ⢰⠒⠒⠒⠒⡖⠒⠒⠒⣶⠒0x80000000 > ⢸ ⡇ ⣿ ⡇ > ⢸ ⡇ ⡟ ⡇ > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ ⡇ > ⢸ ⡇ ⡇ ⡇ > ⢸⡖⠒⠒⢲⡇ ⡇ 0x40000000 > ⢸⡇ ⢸⡇ ⡇ ⡇ > ⢸⡇ ⢸⡇ ⡇ ⡇ > ⢸⡇ ⢸⡇ ⡇ ⡇ > ⢸⡇ ⢸⡇ ⡇ ⡇ > ⢸⡇ ⢸⡇ ⡇ ⡇ > ⢸⡇ ⢸⡇ ⡇ ⡇ > ⢸⡇ ⢸⡇ ⡇ ⡇ <-- 32- & 64-bit start at 0x0 > ⠘⠓⠒0⠚⠓⠒1⠒⠓⠒0x00000000 > > That DT looks like: > ddrc_cache_lo: memory@80000000 { > device_type = "memory"; > reg = <0x0 0x80000000 0x0 0x40000000>; > status = "okay"; > }; > > ddrc_cache_hi: memory@1040000000 { > device_type = "memory"; > reg = <0x10 0x40000000 0x0 0x40000000>; > status = "okay"; > }; > > Each of these changes came as part of an FPGA reference design change & > a corresponding compatible change. I believe rtlv2203 was the second > configuration & rtlv2210 the third. > > I can't boot the current configuration in QEMU, probably due to some of > the things you point out below. > To get it working, I remove the ddrc_cache_hi from my DT and boot with > the 32-bit cached memory only. > This is what the current changes have broken for me. > > IMO it is a perfectly valid thing to boot a system using less than the > memory it *can* use. > > I guess you read the other thread in which I stated that the HSS boot > that is documented doesn't work with recent HSSes. Ideally, and I am > most certainly _not_ expecting anyone to do this, when the HSS writes > the "seg" registers during boot to configure the memory layout as per > the FPGA bitstream QEMU would configure the memory layout it is > emulating to match. > Since direct kernel boot is a thing too, I was thinking that for that > mode, the config in the dtb should probably be used. > I don't know enough about QEMU to know if this is even possible! > > The other possibility I was thinking of was just relaxing the DDR limit > entirely (and ignoring the overlaying) so that QEMU thinks there is 1 > GiB at 0x8000_0000 and 16 GiB at 0x10_0000_0000. > Again, I've not had the cycles to look into any of this at all nor am I > expecting anyone else to - just while I am already typing about this > stuff there's no harm in broadcasting the other thoughts I had. > >> MachineClass::default_ram_size is set to 1.5Gb and machine_init() is >> enforcing it as minimal RAM size, meaning that there we'll always have > > I don't think that this is > >> at least 512 MiB in the Hi RAM area, and that the FDT will be located >> there all the time. > > All the time? That's odd. > I suppose my kernel then remaps the dtb into the memory range it can > access, and therefore things keep ticking. > > I don't think that machine_init() should be enforcing a minimum ram size > of 1.5 GiB - although maybe Bin Meng has a reason for that that I don't > understand. > >> riscv_compute_fdt_addr() can't handle this setup because it assumes that >> the RAM is always contiguous. It's also returning an uint32_t because >> it's enforcing that fdt address is sitting on an area that is addressable >> to 32 bit CPUs, but 32 bits won't be enough to point to the Hi area of >> the Icicle Kit RAM (and to its FDT itself). >> >> Create a new function called microchip_compute_fdt_addr() that is able >> to deal with all these details that are particular to the Icicle Kit. >> Ditch riscv_compute_fdt_addr() and use it instead. >> >> Signed-off-by: Daniel Henrique Barboza >> --- >> hw/riscv/microchip_pfsoc.c | 46 +++++++++++++++++++++++++++++++++++--- >> 1 file changed, 43 insertions(+), 3 deletions(-) >> >> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c >> index dcdbc2cac3..9b829e4d1a 100644 >> --- a/hw/riscv/microchip_pfsoc.c >> +++ b/hw/riscv/microchip_pfsoc.c >> @@ -54,6 +54,8 @@ >> #include "sysemu/device_tree.h" >> #include "sysemu/sysemu.h" >> >> +#include >> + >> /* >> * The BIOS image used by this machine is called Hart Software Services (HSS). >> * See https://github.com/polarfire-soc/hart-software-services >> @@ -513,6 +515,46 @@ static void microchip_pfsoc_soc_register_types(void) >> >> type_init(microchip_pfsoc_soc_register_types) >> >> +static hwaddr microchip_compute_fdt_addr(MachineState *ms) >> +{ >> + const MemMapEntry *memmap = microchip_pfsoc_memmap; >> + hwaddr mem_low_size = memmap[MICROCHIP_PFSOC_DRAM_LO].size; >> + hwaddr mem_high_size, fdt_base; >> + int ret = fdt_pack(ms->fdt); >> + int fdtsize; >> + >> + /* Should only fail if we've built a corrupted tree */ >> + g_assert(ret == 0); >> + >> + fdtsize = fdt_totalsize(ms->fdt); >> + if (fdtsize <= 0) { >> + error_report("invalid device-tree"); >> + exit(1); >> + } >> + >> + /* >> + * microchip_icicle_kit_machine_init() does a validation >> + * that guarantees that ms->ram_size is always greater >> + * than mem_low_size and that mem_high_size will be >> + * at least 512MiB. > > Again, I don't think it should be doing this at all. I see the comment > about that size refers to DDR training, but given the overlaying of > memory it's entirely possible to train against 64-bit addresses but then > boot a kernel using only low memory addresses. > Perhaps by default & for booting via the bootloader, but I don't think > enforcing this makes sense when the bootloader is not involved. > > If a dtb is used as the source for the memory layout, requiring memory > at high addresses doesn't make sense to me. I have no idea if there is a > mechanism for figuring that out though nor am I au fait with how these > memory sizes are calculated. > It is getting kinda late here, so I am sending this without having > investigated any of the detail, sorry. > > Hopefully that wasn't too deranged and you can at least understand why I > have been doing what I have... > > Thanks, > Conor. > >> + * >> + * This also means that our fdt_addr will be based >> + * on the starting address of the HI DRAM block. >> + */ >> + mem_high_size = ms->ram_size - mem_low_size; >> + fdt_base = memmap[MICROCHIP_PFSOC_DRAM_HI].base; >> + >> + /* >> + * In theory we could copy riscv_compute_fdt_addr() >> + * and put the FDT capped at maximum 3Gb from fdt_base, >> + * but fdt_base is set at 0x1000000000 (64GiB). We >> + * make the assumption here that the OS is ready to >> + * handle the FDT, 2MB aligned, at the very end of >> + * the available RAM. >> + */ >> + return QEMU_ALIGN_DOWN(fdt_base + mem_high_size - fdtsize, 2 * MiB); >> +} >> + >> static void microchip_icicle_kit_machine_init(MachineState *machine) >> { >> MachineClass *mc = MACHINE_GET_CLASS(machine); >> @@ -640,9 +682,7 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) >> "bootargs", machine->kernel_cmdline); >> } >> >> - /* Compute the fdt load address in dram */ >> - fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base, >> - machine->ram_size, machine->fdt); >> + fdt_load_addr = microchip_compute_fdt_addr(machine); >> riscv_load_fdt(fdt_load_addr, machine->fdt); >> >> /* Load the reset vector */ >> -- >> 2.39.0 >> >> >> From MAILER-DAEMON Sat Jan 21 14:51:13 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJJtR-0007hW-FP for mharc-qemu-riscv@gnu.org; Sat, 21 Jan 2023 14:51:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJJtQ-0007h6-Mt; Sat, 21 Jan 2023 14:51:12 -0500 Received: from dfw.source.kernel.org ([139.178.84.217]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJJtO-0007Y8-Mv; Sat, 21 Jan 2023 14:51:12 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5E73D60B07; Sat, 21 Jan 2023 19:51:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id C04DCC433D2; Sat, 21 Jan 2023 19:51:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1674330665; bh=5xv3EI3R/s6bgkFlULHWIsu8pYY/Wht1FAiQ/i9EMng=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=ZYz06FYiO6X0AsPHzQsonkLElutrZLAHMwDFiFmv5f5oiHND5KITEr7xqTAjUbzRr Q4StMMVYL0A/7OTIXT5+L6GfIq09HLxwQaO6slZgfyJAQMseX2JvOii8xYp7jWr54V 4fYOJcjA31+KxV1ANOh42Ooomx6tlrp9mRNx8qyPNNJCa1oYLJ6L/gTQwCpiHsa6GL jJsD6Rf2v8yGtFXzK6isyTz2tqdGTGZBK34DNuaLJBex6b/YUgOsvqytGfK5Jf3C+O rDizzmJB+TRBY8lk/cSnfslpzdLIww5ps8G+duIQ6SePt839nRQTc+25vddQQikMNE odvGPKhtqHl5A== Date: Sat, 21 Jan 2023 19:51:02 +0000 From: Conor Dooley To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Subject: Re: [PATCH v3 3/7] hw/riscv/microchip_pfsoc.c: add an Icicle Kit fdt address function Message-ID: References: <20230119191728.622081-1-dbarboza@ventanamicro.com> <20230119191728.622081-4-dbarboza@ventanamicro.com> <385b977b-d15f-6c54-1d05-ab68e122dfe8@ventanamicro.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="7/9P0CDH7AfIHltX" Content-Disposition: inline In-Reply-To: <385b977b-d15f-6c54-1d05-ab68e122dfe8@ventanamicro.com> Received-SPF: pass client-ip=139.178.84.217; envelope-from=conor@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 21 Jan 2023 19:51:13 -0000 --7/9P0CDH7AfIHltX Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sat, Jan 21, 2023 at 02:58:19PM -0300, Daniel Henrique Barboza wrote: > Conor, >=20 > Thanks for the Icicle-kit walk-through! nw chief > I'll not claim that I fully understood it, > but I understood enough to handle the situation ATM. tbf, I struggle to explain/visualise that stuff with the "windows" etc well. I wrote myself a program to visualise it for a good reason! Well it was done in Rust, so there were two good reasons ;) > Without this change, this is where the FDT is being installed in the boar= d when > I start it with 8Gb of RAM (retrieved via 'info roms'): >=20 > addr=3D00000000bfe00000 size=3D0x00a720 mem=3Dram name=3D"fdt" >=20 > Which surprised me at first because this is almost at the end of the LO a= rea which has > 1Gb and I figured it would be in the middle of another RAM area. I took a= nother read > at what we're doing in riscv_load_fdt(): >=20 > ----------- > temp =3D (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; > fdt_addr =3D QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); > ----------- >=20 > This code can be read as "if the starting address of the RAM is lower tha= n 3Gb, put > the FDT no further than 3Gb (0xc0000000). Otherwise, put it at the end of= dram", > where "dram_base" is the starting address of the RAM block that the funct= ion > receives. >=20 > For icicle-kit, this is being passed as memmap[MICROCHIP_PFSOC_DRAM_LO].= base, > 0x80000000, which is 2Gb. >=20 > So, regardless of how much RAM we have (dram_end), the FDT will always be= capped at > 3Gb. At this moment, this fits exactly at the end of the LO area for the = Icicle Kit. > Which is funny because this 3Gb restriction was added by commit 1a475d39e= f54 to fix > 32 bit guest boot and it happened to also work for the Microchip SoC. That's hilariously convenient hahah > So yeah, I thought that I was fixing a bug and in the end I caused one. T= his patch > needs to go. >=20 > Alistair, I believe I should re-send v2, this time explaining why the exi= sting function > will not break the Microchip board because we'll never put the FDT out of= the LO area > of the board. Does this work for you? > Conor, one more thing: >=20 >=20 > On 1/19/23 21:15, Conor Dooley wrote: > > Hey Daniel, > >=20 > > Got through the stuff I wanted to get done tonight faster than > > expected... > >=20 > > On Thu, Jan 19, 2023 at 05:17:33PM -0300, Daniel Henrique Barboza wrote: > > > Are you testing it by using the command line > > > you mentioned in the "qemu icicle kit es" thread? > > >=20 > > > $(QEMU)/qemu-system-riscv64 \ > > > -M microchip-icicle-kit \ > > > -m 2G -smp 5 \ > > > -kernel $(vmlinux_bin) \ > > > -dtb $(devkit).dtb \ > > > -initrd $(initramfs) \ > > > -display none \ > > > -serial null \ > > > -serial stdio > >=20 > > Yah, effectively. It's not quite that, but near enough as makes no real > > difference: > > qemu-icicle: > > $(QEMU)/qemu-system-riscv64 -M microchip-icicle-kit \ > > -m 2G -smp 5 \ > > -kernel $(vmlinux_bin) \ > > -dtb $(wrkdir)/riscvpc.dtb \ > > -initrd $(initramfs) \ > > -display none -serial null \ > > -serial stdio \ > > -D qemu.log -d unimp > >=20 > > I just tried to make things somewhat more intelligible for that thread. >=20 > I tried it out with kernel v6.0.0 (I saw you mentioning in the other thre= ad that > this was the latest kernel you were able to boot this way) Yah, I said that because I didn't want them to have to mess with DT. Later kernels do work, but need DT modifications as things are now configured for the below case. > > The current Devicetree in Linux & U-Boot corresponds to a configuration > > like: > > =E2=A2=B0=E2=A0=92=E2=A0=92=E2=A0=92=E2=A0=92=E2=A1=96=E2=A0=92=E2=A0= =92=E2=A0=92=E2=A3=B6=E2=A0=920x80000000 > > =E2=A2=B8 =E2=A1=87 =E2=A3=BF =E2=A1=87 > > =E2=A2=B8 =E2=A1=87 =E2=A1=9F =E2=A1=87 > > =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 > > =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 > > =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 > > =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 > > =E2=A2=B8 =E2=A1=87 =E2=A1=87 =E2=A1=87 > > =E2=A2=B8=E2=A1=96=E2=A0=92=E2=A0=92=E2=A2=B2=E2=A1=87 =E2=A1=87 0x40= 000000 > > =E2=A2=B8=E2=A1=87 =E2=A2=B8=E2=A1=87 =E2=A1=87 =E2=A1=87 > > =E2=A2=B8=E2=A1=87 =E2=A2=B8=E2=A1=87 =E2=A1=87 =E2=A1=87 > > =E2=A2=B8=E2=A1=87 =E2=A2=B8=E2=A1=87 =E2=A1=87 =E2=A1=87 > > =E2=A2=B8=E2=A1=87 =E2=A2=B8=E2=A1=87 =E2=A1=87 =E2=A1=87 > > =E2=A2=B8=E2=A1=87 =E2=A2=B8=E2=A1=87 =E2=A1=87 =E2=A1=87 > > =E2=A2=B8=E2=A1=87 =E2=A2=B8=E2=A1=87 =E2=A1=87 =E2=A1=87 > > =E2=A2=B8=E2=A1=87 =E2=A2=B8=E2=A1=87 =E2=A1=87 =E2=A1=87 <-- 32- & = 64-bit start at 0x0 > > =E2=A0=98=E2=A0=93=E2=A0=920=E2=A0=9A=E2=A0=93=E2=A0=921=E2=A0=92=E2=A0= =93=E2=A0=920x00000000 > >=20 > > That DT looks like: > > ddrc_cache_lo: memory@80000000 { > > device_type =3D "memory"; > > reg =3D <0x0 0x80000000 0x0 0x40000000>; > > status =3D "okay"; > > }; > >=20 > > ddrc_cache_hi: memory@1040000000 { > > device_type =3D "memory"; > > reg =3D <0x10 0x40000000 0x0 0x40000000>; > > status =3D "okay"; > > }; This one doesn't work in QEMU, so for those kernels I just delete the ddrc_cache_hi node, and v6.2-rcN works in that way. > and it booted up until > the kernel complained about missing initramfs. Any tips on how I can buil= d an > initrd disk for the board? Ehh, any old initramfs for RISC-V should work, right? I suppose passing a normal rootfs does either - I just mostly work w/ hardware & use NFS there, so have nothing scripted to build a rootfs for me, which is why I've been using initramfs. I build one using buildroot, with a config like: https://raw.githubusercontent.com/ConchuOD/riscv-env/dev/conf/lowmem/buildr= oot_initramfs_config I then do (ripped from my makefile rule): $(linux_srcdir)/usr/gen_initramfs.sh \ -o initramfs.cpio -u $(shell id -u) -g $(shell id -g) \ initramfs.txt \ $(path_to_buildroot_sysroot) I'm lazy and CBA finding somewhere else to host this, so I put one here: https://github.com/ConchuOD/riscv-env/releases/download/v2022.03/initramfs.= cpio.gz Thanks, Conor. --7/9P0CDH7AfIHltX Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY8xCJgAKCRB4tDGHoIJi 0qSNAP4lhmtV5x7uyEuDWom4NMNJGCxrcpB0Kfms8h9NqiB0VwD+PESebJpDpN0f u1pYuD8j9MgvbSsHzDwGLt7vV6eTUAo= =vZg/ -----END PGP SIGNATURE----- --7/9P0CDH7AfIHltX-- From MAILER-DAEMON Sun Jan 22 17:54:30 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJjEM-0006Lc-Ad for mharc-qemu-riscv@gnu.org; Sun, 22 Jan 2023 17:54:30 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJjEI-0006L2-UK; Sun, 22 Jan 2023 17:54:26 -0500 Received: from mail-vs1-xe2c.google.com ([2607:f8b0:4864:20::e2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJjEG-0006eS-I0; Sun, 22 Jan 2023 17:54:25 -0500 Received: by mail-vs1-xe2c.google.com with SMTP id l125so11189891vsc.2; Sun, 22 Jan 2023 14:54:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=4I40+AVbej6AAPnbz8AePv5s3N9ys0uSGtrAZHOJVn8=; b=fRm07AMhS+gbkHHOpiRPX+lL70vhaVxTI2dpRNeiUDe5Pah0157z3yY5Te/WzPQ9xc dw2u076lW4fpYhZ6uELmbbhBP0CRoz8YXHq0q3NCASw0aYOueRqSFDdIeRyB30+GE5lL TsTZyzR+0F8zM/D4doT3EUXhM3YOohGfZij6heND+5Xlg3nG+WQ8E/CU/ArZ7nQ2w76I DTMcPnp0E4IICJJTpiDDx/me9aLtp81lGbhxSr0kU0HbjpXC4acl2VLvxeC9nSvLewif T5zJeh/TmQ9QGFjNQ0uvVu994TjaT1pzjpi74/n77hzxS8HhwtJiV5xlZ746pvSM9Qil rHhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=4I40+AVbej6AAPnbz8AePv5s3N9ys0uSGtrAZHOJVn8=; b=XHS/KVfvbd/55vemQL43vqQwezok7YvRmhdtlr2orzfhXqiMsBS9kDXjtb8lLrkYB4 fdb4mAEByv9vKBJthWxLuXsku3FEOuTBLOmXiSb+FHemHpY1SEjFw35j/GyrhBM6Pn3F 4lDeK8KGIaFw3luHwrA798lZWkLTCp4yOp49qy7+00pLeTcwIozOrLla172ducOivUb/ yBL5CrdHyE4z+Y/aQahjM4lp4VZIB9TpA9wNbnrzHC6JpYlOE6We7TFuBohsDRbu6OXE cyDI83Gx8aMqqqNGKJrd3SF+UXPdyCtOWU1WTrJaWUHSatNJHr8QBuMfZTfMbFbiVXYU CETA== X-Gm-Message-State: AFqh2kqQHlUtZy42f04n/RyM+bDTgX2cNKbZFIYBSyKuseuQT99LuW2T jo2jh992qNh2hyQia3/DwbvNFnwGPJQ0x2UWcso= X-Google-Smtp-Source: AMrXdXvMP6iQg7byFJnOocAZ9jS1FnPaN/15bOui+N4iv58hyZ6iI1bD0n9y4bskBPHsVaa+RVHyoPeZcHGwA6tJLpk= X-Received: by 2002:a05:6102:f98:b0:3d3:c7d9:7b62 with SMTP id e24-20020a0561020f9800b003d3c7d97b62mr2701722vsv.72.1674428062864; Sun, 22 Jan 2023 14:54:22 -0800 (PST) MIME-Version: 1.0 References: <20230119191728.622081-1-dbarboza@ventanamicro.com> <20230119191728.622081-4-dbarboza@ventanamicro.com> <385b977b-d15f-6c54-1d05-ab68e122dfe8@ventanamicro.com> In-Reply-To: <385b977b-d15f-6c54-1d05-ab68e122dfe8@ventanamicro.com> From: Alistair Francis Date: Mon, 23 Jan 2023 08:53:56 +1000 Message-ID: Subject: Re: [PATCH v3 3/7] hw/riscv/microchip_pfsoc.c: add an Icicle Kit fdt address function To: Daniel Henrique Barboza Cc: Conor Dooley , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e2c; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 22 Jan 2023 22:54:27 -0000 On Sun, Jan 22, 2023 at 5:16 AM Daniel Henrique Barboza wrote: > > Conor, > > Thanks for the Icicle-kit walk-through! I'll not claim that I fully understood it, > but I understood enough to handle the situation ATM. > > Without this change, this is where the FDT is being installed in the board when > I start it with 8Gb of RAM (retrieved via 'info roms'): > > addr=00000000bfe00000 size=0x00a720 mem=ram name="fdt" > > Which surprised me at first because this is almost at the end of the LO area which has > 1Gb and I figured it would be in the middle of another RAM area. I took another read > at what we're doing in riscv_load_fdt(): > > ----------- > temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; > fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); > ----------- > > This code can be read as "if the starting address of the RAM is lower than 3Gb, put > the FDT no further than 3Gb (0xc0000000). Otherwise, put it at the end of dram", > where "dram_base" is the starting address of the RAM block that the function > receives. > > For icicle-kit, this is being passed as memmap[MICROCHIP_PFSOC_DRAM_LO].base, > 0x80000000, which is 2Gb. > > So, regardless of how much RAM we have (dram_end), the FDT will always be capped at > 3Gb. At this moment, this fits exactly at the end of the LO area for the Icicle Kit. > Which is funny because this 3Gb restriction was added by commit 1a475d39ef54 to fix > 32 bit guest boot and it happened to also work for the Microchip SoC. > > So yeah, I thought that I was fixing a bug and in the end I caused one. This patch > needs to go. > > > Alistair, I believe I should re-send v2, this time explaining why the existing function > will not break the Microchip board because we'll never put the FDT out of the LO area > of the board. Does this work for you? I think that's fine. My only worry is that we are losing some flexibility that some future board might want. Alistair From MAILER-DAEMON Sun Jan 22 19:01:49 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJkHV-0007uN-Gi for mharc-qemu-riscv@gnu.org; Sun, 22 Jan 2023 19:01:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJkHT-0007tu-VN; Sun, 22 Jan 2023 19:01:47 -0500 Received: from mail-vk1-xa2b.google.com ([2607:f8b0:4864:20::a2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJkHR-0006mP-RO; Sun, 22 Jan 2023 19:01:47 -0500 Received: by mail-vk1-xa2b.google.com with SMTP id q21so5226631vka.3; Sun, 22 Jan 2023 16:01:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=2NBcqqjcEF0dc5fWct4sV6OKuKM5spyiDbli2Qgd4Ow=; b=JJ8V89sGhdj5qNJkNNpRwykGvSyUULXVv7IJJOuiBA0/aTw26k7cMutyJxl7lQBxO5 091NyHgocD/6u+gFtxEL9GvVOMijUPFmVVNYzvu2GrGl6Ki98w8eL7OozPJkVPAD+Q7N AHxCTjRDoSBtp1HSJ9H20ojoW+ngAZjSeJ28mSCHMy5lvoJ9vQK8/FRIpmd78UmlapV9 8QCFSTGch8cxle21kWCjU6AdID3/6JxFx0xzEZVdg9D/4/5lIiHURAMd6I+/g1IBWd25 pbytGPZfwWOy6TSjXxrP+x4T7qkj2JixHCtlnXpmrM/iUTi0TR4gl+xw/dbGF0+WKN9I bHfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2NBcqqjcEF0dc5fWct4sV6OKuKM5spyiDbli2Qgd4Ow=; b=KG+Zj/n5jjNzVpmj7sekEJVmmyVvR+R5U8O74R0aX7bVKUE6uggAlb7LHJpCodMIP0 0/NKOy8wG9fEw4q8EhldgLGpKorMQf0L2b1iFrUaOOnaN8jjKqx4SLpgYtFpA7V9/6EQ cxnq/mgwmCHirVOtc3DU1EbTWuHbCcPrAl/knh0DJC0Nyft9MQRS8NOCFGFaWQg8Edcj GBt9w6hWohw4kG0r/qk/aJRXs/Fr+XM8odKF9p+NkhoErFplX1a/fL7utm4NukTeerjP OGqS4IlggpKyyxk6UvhQ9iEhMuxUu06NWgCdKqT3em48ulvCPfsvzlu2DEr0PvBOC7uG D52w== X-Gm-Message-State: AFqh2kq/USzqIo1TbgtmGvdnclaJ6wlRcebqpLcaUDLELQcL6NSX9U+c 4BiMBekrZw2IjTKrTZOgRUUshC6xZBxE/GcQVHs= X-Google-Smtp-Source: AMrXdXse0v/P04PggFKeZOl8SgzuHXzgx8pftcoqT5cBcIAcJCNBL3nL1eKcqd2NoKP5194p21b/G+YIt13zZxV6LMk= X-Received: by 2002:a1f:2c0c:0:b0:3e1:7e08:a117 with SMTP id s12-20020a1f2c0c000000b003e17e08a117mr2969781vks.34.1674432104307; Sun, 22 Jan 2023 16:01:44 -0800 (PST) MIME-Version: 1.0 References: <20230119213707.651533-1-dbarboza@ventanamicro.com> <20230119213707.651533-2-dbarboza@ventanamicro.com> In-Reply-To: <20230119213707.651533-2-dbarboza@ventanamicro.com> From: Alistair Francis Date: Mon, 23 Jan 2023 10:01:18 +1000 Message-ID: Subject: Re: [PATCH v9 1/3] hw/riscv: clear kernel_entry higher bits from load_elf_ram_sym() To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= , Bin Meng Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a2b; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 00:01:48 -0000 On Fri, Jan 20, 2023 at 7:38 AM Daniel Henrique Barboza wrote: > > load_elf_ram_sym() will sign-extend 32 bit addresses. If a 32 bit > QEMU guest happens to be running in a hypervisor that are using 64 > bits to encode its address, kernel_entry can be padded with '1's > and create problems [1]. > > Use a translate_fn() callback to be called by load_elf_ram_sym() and > return only the 32 bits address if we're running a 32 bit CPU. > > [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html > > Suggested-by: Philippe Mathieu-Daud=C3=A9 > Suggested-by: Bin Meng > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Signed-off-by: Daniel Henrique Barboza Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/boot.c | 20 +++++++++++++++++++- > hw/riscv/microchip_pfsoc.c | 3 ++- > hw/riscv/opentitan.c | 3 ++- > hw/riscv/sifive_e.c | 3 ++- > hw/riscv/sifive_u.c | 3 ++- > hw/riscv/spike.c | 3 ++- > hw/riscv/virt.c | 3 ++- > include/hw/riscv/boot.h | 1 + > 8 files changed, 32 insertions(+), 7 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 2594276223..46fc7adccf 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -173,7 +173,24 @@ target_ulong riscv_load_firmware(const char *firmwar= e_filename, > exit(1); > } > > +static uint64_t translate_kernel_address(void *opaque, uint64_t addr) > +{ > + RISCVHartArrayState *harts =3D opaque; > + > + if (riscv_is_32bit(harts)) { > + /* > + * For 32 bit CPUs, kernel_load_base is sign-extended > + * (i.e. it can be padded with '1's) by load_elf(). > + * Remove the sign extension by truncating to 32-bit. > + */ > + return extract64(addr, 0, 32); > + } > + > + return addr; > +} > + > target_ulong riscv_load_kernel(MachineState *machine, > + RISCVHartArrayState *harts, > target_ulong kernel_start_addr, > symbol_fn_t sym_cb) > { > @@ -189,7 +206,8 @@ target_ulong riscv_load_kernel(MachineState *machine, > * the (expected) load address load address. This allows kernels to = have > * separate SBI and ELF entry points (used by FreeBSD, for example). > */ > - if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, > + if (load_elf_ram_sym(kernel_filename, NULL, > + translate_kernel_address, harts, > NULL, &kernel_load_base, NULL, NULL, 0, > EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { > return kernel_load_base; > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index 82ae5e7023..bdefeb3cbb 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -629,7 +629,8 @@ static void microchip_icicle_kit_machine_init(Machine= State *machine) > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpu= s, > firmware_end_ad= dr); > > - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, N= ULL); > + kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, > + kernel_start_addr, NULL); > > if (machine->initrd_filename) { > riscv_load_initrd(machine, kernel_entry); > diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c > index 64d5d435b9..2731138c41 100644 > --- a/hw/riscv/opentitan.c > +++ b/hw/riscv/opentitan.c > @@ -101,7 +101,8 @@ static void opentitan_board_init(MachineState *machin= e) > } > > if (machine->kernel_filename) { > - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); > + riscv_load_kernel(machine, &s->soc.cpus, > + memmap[IBEX_DEV_RAM].base, NULL); > } > } > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > index 3e3f4b0088..1a7d381514 100644 > --- a/hw/riscv/sifive_e.c > +++ b/hw/riscv/sifive_e.c > @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machi= ne) > memmap[SIFIVE_E_DEV_MROM].base, &address_space= _memory); > > if (machine->kernel_filename) { > - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL)= ; > + riscv_load_kernel(machine, &s->soc.cpus, > + memmap[SIFIVE_E_DEV_DTIM].base, NULL); > } > } > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 2fb6ee231f..83dfe09877 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -598,7 +598,8 @@ static void sifive_u_machine_init(MachineState *machi= ne) > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpu= s, > firmware_end_ad= dr); > > - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, N= ULL); > + kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, > + kernel_start_addr, NULL); > > if (machine->initrd_filename) { > riscv_load_initrd(machine, kernel_entry); > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index badc11ec43..2bcc50d90d 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -305,7 +305,8 @@ static void spike_board_init(MachineState *machine) > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], > firmware_end_ad= dr); > > - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, > + kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], > + kernel_start_addr, > htif_symbol_callback); > > if (machine->initrd_filename) { > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 4a11b4b010..ac173a6ed6 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -1274,7 +1274,8 @@ static void virt_machine_done(Notifier *notifier, v= oid *data) > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], > firmware_end_ad= dr); > > - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, N= ULL); > + kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], > + kernel_start_addr, NULL); > > if (machine->initrd_filename) { > riscv_load_initrd(machine, kernel_entry); > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h > index f94653a09b..105706bf25 100644 > --- a/include/hw/riscv/boot.h > +++ b/include/hw/riscv/boot.h > @@ -44,6 +44,7 @@ target_ulong riscv_load_firmware(const char *firmware_f= ilename, > hwaddr firmware_load_addr, > symbol_fn_t sym_cb); > target_ulong riscv_load_kernel(MachineState *machine, > + RISCVHartArrayState *harts, > target_ulong firmware_end_addr, > symbol_fn_t sym_cb); > void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); > -- > 2.39.0 > > From MAILER-DAEMON Sun Jan 22 19:06:15 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJkLn-00011Z-9f for mharc-qemu-riscv@gnu.org; Sun, 22 Jan 2023 19:06:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJkLl-000119-Sj for qemu-riscv@nongnu.org; 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Sun, 22 Jan 2023 16:06:00 -0800 (PST) Received: from localhost.localdomain (unknown [10.225.165.30]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4P0VkG1vffz1RvLy; Sun, 22 Jan 2023 16:05:57 -0800 (PST) From: Wilfred Mallawa To: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-riscv@nongnu.org Cc: qemu-devel@nongnu.org, Wilfred Mallawa Subject: [PATCH] include/hw/riscv/opentitan: update opentitan IRQs Date: Mon, 23 Jan 2023 10:05:41 +1000 Message-Id: <20230123000540.58351-1-wilfred.mallawa@opensource.wdc.com> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=380668d3b=wilfred.mallawa@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 00:06:14 -0000 From: Wilfred Mallawa Updates the opentitan IRQs to match the latest supported commit of Opentitan from TockOS. OPENTITAN_SUPPORTED_SHA :=3D 565e4af39760a123c59a184aa2f5812a961fde47 Signed-off-by: Wilfred Mallawa --- include/hw/riscv/opentitan.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index 7659d1bc5b..235728b9cc 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -108,11 +108,11 @@ enum { IBEX_UART0_RX_BREAK_ERR_IRQ =3D 6, IBEX_UART0_RX_TIMEOUT_IRQ =3D 7, IBEX_UART0_RX_PARITY_ERR_IRQ =3D 8, - IBEX_TIMER_TIMEREXPIRED0_0 =3D 127, - IBEX_SPI_HOST0_ERR_IRQ =3D 134, - IBEX_SPI_HOST0_SPI_EVENT_IRQ =3D 135, - IBEX_SPI_HOST1_ERR_IRQ =3D 136, - IBEX_SPI_HOST1_SPI_EVENT_IRQ =3D 137, + IBEX_TIMER_TIMEREXPIRED0_0 =3D 124, + IBEX_SPI_HOST0_ERR_IRQ =3D 131, + IBEX_SPI_HOST0_SPI_EVENT_IRQ =3D 132, + IBEX_SPI_HOST1_ERR_IRQ =3D 133, + IBEX_SPI_HOST1_SPI_EVENT_IRQ =3D 134, }; =20 #endif --=20 2.39.0 From MAILER-DAEMON Sun Jan 22 19:24:48 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJkdk-0003vy-0K for mharc-qemu-riscv@gnu.org; Sun, 22 Jan 2023 19:24:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJkdb-0003vQ-58; Sun, 22 Jan 2023 19:24:39 -0500 Received: from mail-vs1-xe34.google.com ([2607:f8b0:4864:20::e34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJkdY-0003Ek-Fc; Sun, 22 Jan 2023 19:24:38 -0500 Received: by mail-vs1-xe34.google.com with SMTP id q125so11369528vsb.0; Sun, 22 Jan 2023 16:24:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=8fZqZuTkE+WjJG7EHXyNeyFw6GlZLWGaAGuhBGJ4LdQ=; b=QMK/MAMBMvYJiGXeeX98pckLE0Z6OzQzARKzsKk7TXkzqE+xKi90y7i/J8SN/CPbQt Fq33cSvbqP8h4RBxC0PTVTVVkk8sJW1+Dy2wx9MnZoO1ZJDgUdDCYCWJos5ANGhWVdjr 4scGTnYKeolXMl6lqOyB9BMWCnKAhvAAZeR5lqe7XnCWOSs2FtvcsUnsPwK8uhWCLL4l xynfV2+tA12rDbawD2cOh6L1axKW+TlSPqwYGlGFZkfe7AhvfRbOieBwiDgbh0hK+eVj b1eiPDRS1uu1i+LCZK1uzPKtyFtyStMBK10BB5jfRf69FxBXe8iigiom3Qy2E1CPY4XF 85Tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=8fZqZuTkE+WjJG7EHXyNeyFw6GlZLWGaAGuhBGJ4LdQ=; b=iRd+to8HxQ989PcFU7/sdYYGtgVyRttKeCkcFh4Bx6pse+p+jPhYj4s7xxR1AVmlec a54g29Lxpkh2FYpjTCb3RjBY38MCie0KUs4CHjmILW1mykh3PG4X4+5sP808mkao9T1I UIvaF0iWVVhhXyFE5l0lC/6FnyhLn+YpRXclu9yZtl8qra2PST7ooiah4fmWhd8/jDA5 b/qhOWIgFeYA9xDSBl5tM5wfG0OSZQARi+164ls0ZjEVxpDjEU9cnORxTy9vGD9AOT49 d+pzljqIDvCXZWhTG/Y7R3E8MobG/OmFIYnAHDpuZXKGExfpKtxuAOUl0DwDFg2YX2hv dN0w== X-Gm-Message-State: AFqh2kphf1eQ+Hhg4q4APyjxfMGTVd249dxA1i+FtRB7bhwIP9LOByR+ XXFfwKYc44e6nVbpmqTi+IkqRcQ4MwWytjBshtuWwQZ4Qt4= X-Google-Smtp-Source: AMrXdXtIXWCIR/tqdeTZojbxIs4jgf7z7eNX8xPSjUSRXdjSMIOYSi8hd6LXbNxCEELtv9vVc1d3wosEXTKboXVhYJE= X-Received: by 2002:a67:eb10:0:b0:3c9:8cc2:dd04 with SMTP id a16-20020a67eb10000000b003c98cc2dd04mr3192007vso.73.1674433474431; Sun, 22 Jan 2023 16:24:34 -0800 (PST) MIME-Version: 1.0 References: <20230119213707.651533-1-dbarboza@ventanamicro.com> In-Reply-To: <20230119213707.651533-1-dbarboza@ventanamicro.com> From: Alistair Francis Date: Mon, 23 Jan 2023 10:24:08 +1000 Message-ID: Subject: Re: [PATCH v9 0/3] hw/riscv: clear kernel_entry high bits with 32bit CPUs To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e34; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe34.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 00:24:41 -0000 On Fri, Jan 20, 2023 at 7:38 AM Daniel Henrique Barboza wrote: > > Hi, > > In this version I changed the patch order to avoid having a patch that > would trigger the 32 bit regression Alistair observed. Patch 3 is now > the first patch. > > I've also addressed the comments from Bin and Phil. > > Patches based on riscv-to-apply.next. > > Changes from v8: > - patch 1 (former 3): > - comment changes > - now open code '32' instead of using a macro > - v8 link: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg03254.html > > Daniel Henrique Barboza (3): > hw/riscv: clear kernel_entry higher bits from load_elf_ram_sym() > hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() > hw/riscv/boot.c: make riscv_load_initrd() static Thanks! Applied to riscv-to-apply.next Alistair > > hw/riscv/boot.c | 96 ++++++++++++++++++++++++++------------ > hw/riscv/microchip_pfsoc.c | 12 +---- > hw/riscv/opentitan.c | 4 +- > hw/riscv/sifive_e.c | 4 +- > hw/riscv/sifive_u.c | 12 +---- > hw/riscv/spike.c | 14 ++---- > hw/riscv/virt.c | 12 +---- > include/hw/riscv/boot.h | 3 +- > 8 files changed, 82 insertions(+), 75 deletions(-) > > -- > 2.39.0 > > From MAILER-DAEMON Sun Jan 22 21:53:42 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJmxq-0007CH-2Z for mharc-qemu-riscv@gnu.org; Sun, 22 Jan 2023 21:53:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJmxo-0007By-Gd; Sun, 22 Jan 2023 21:53:40 -0500 Received: from mail-vk1-xa33.google.com ([2607:f8b0:4864:20::a33]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJmxn-0000lg-27; Sun, 22 Jan 2023 21:53:40 -0500 Received: by mail-vk1-xa33.google.com with SMTP id 12so5331291vkj.12; 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Sun, 22 Jan 2023 18:53:37 -0800 (PST) MIME-Version: 1.0 References: <20230123000540.58351-1-wilfred.mallawa@opensource.wdc.com> In-Reply-To: <20230123000540.58351-1-wilfred.mallawa@opensource.wdc.com> From: Alistair Francis Date: Mon, 23 Jan 2023 12:53:11 +1000 Message-ID: Subject: Re: [PATCH] include/hw/riscv/opentitan: update opentitan IRQs To: Wilfred Mallawa Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Wilfred Mallawa Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::a33; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa33.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 02:53:40 -0000 On Mon, Jan 23, 2023 at 10:06 AM Wilfred Mallawa wrote: > > From: Wilfred Mallawa > > Updates the opentitan IRQs to match the latest supported commit of > Opentitan from TockOS. > > OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47 > > Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis Alistair > --- > include/hw/riscv/opentitan.h | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h > index 7659d1bc5b..235728b9cc 100644 > --- a/include/hw/riscv/opentitan.h > +++ b/include/hw/riscv/opentitan.h > @@ -108,11 +108,11 @@ enum { > IBEX_UART0_RX_BREAK_ERR_IRQ = 6, > IBEX_UART0_RX_TIMEOUT_IRQ = 7, > IBEX_UART0_RX_PARITY_ERR_IRQ = 8, > - IBEX_TIMER_TIMEREXPIRED0_0 = 127, > - IBEX_SPI_HOST0_ERR_IRQ = 134, > - IBEX_SPI_HOST0_SPI_EVENT_IRQ = 135, > - IBEX_SPI_HOST1_ERR_IRQ = 136, > - IBEX_SPI_HOST1_SPI_EVENT_IRQ = 137, > + IBEX_TIMER_TIMEREXPIRED0_0 = 124, > + IBEX_SPI_HOST0_ERR_IRQ = 131, > + IBEX_SPI_HOST0_SPI_EVENT_IRQ = 132, > + IBEX_SPI_HOST1_ERR_IRQ = 133, > + IBEX_SPI_HOST1_SPI_EVENT_IRQ = 134, > }; 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Sun, 22 Jan 2023 19:57:59 -0800 (PST) Received: from toolbox.alistair23.me (unknown [10.225.167.8]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4P0bsx0BLQz1RvLy; Sun, 22 Jan 2023 19:57:56 -0800 (PST) From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, Bin Meng , alistair23@gmail.com, bmeng.cn@gmail.com Subject: [PATCH] hw/riscv: boot: Don't use CSRs if they are disabled Date: Mon, 23 Jan 2023 13:57:54 +1000 Message-Id: <20230123035754.75553-1-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=380dee0ef=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 03:58:12 -0000 From: Alistair Francis If the CSRs and CSR instructions are disabled because the Zicsr extension isn't enabled then we want to make sure we don't run any CSR instructions in the boot ROM. This patches removes the CSR instructions from the reset-vec if the extension isn't enabled. We replace the instruction with a NOP instead. Note that we don't do this for the SiFive U machine, as we are modelling the hardware in that case. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1447 Signed-off-by: Alistair Francis --- hw/riscv/boot.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 2594276223..cb27798a25 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -356,6 +356,15 @@ void riscv_setup_rom_reset_vec(MachineState *machine= , RISCVHartArrayState *harts reset_vec[4] =3D 0x0182b283; /* ld t0, 24(t0) */ } =20 + if (!harts->harts[0].cfg.ext_icsr) { + /* + * The Zicsr extension has been disabled, so let's ensure we don= 't + * run the CSR instruction. Let's fill the address with a non + * compressed nop. + */ + reset_vec[2] =3D 0x00000013; /* addi x0, x0, 0 */ + } + /* copy in the reset vector in little_endian byte order */ for (i =3D 0; i < ARRAY_SIZE(reset_vec); i++) { reset_vec[i] =3D cpu_to_le32(reset_vec[i]); --=20 2.39.0 From MAILER-DAEMON Mon Jan 23 01:39:24 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJqUG-0004Hp-Ip for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 01:39:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJqU7-0004HG-Ko for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 01:39:19 -0500 Received: from esa1.hgst.iphmx.com ([68.232.141.245]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJqU3-0006va-RE for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 01:39:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; 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envelope-from=prvs=380668d3b=wilfred.mallawa@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 06:39:22 -0000 From: Wilfred Mallawa Updates the opentitan IRQs to match the latest supported commit of Opentitan from TockOS. OPENTITAN_SUPPORTED_SHA :=3D 565e4af39760a123c59a184aa2f5812a961fde47 Memory layout as per [1] [1] https://github.com/lowRISC/opentitan/blob/565e4af39760a123c59a184aa2f= 5812a961fde47/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h Signed-off-by: Wilfred Mallawa --- Changes in v2: - Updated the MMIO register layout/size - Bumped the supported commit sha - Added link to OT register layout for reference in the commit msg hw/riscv/opentitan.c | 80 ++++++++++++++++++------------------ include/hw/riscv/opentitan.h | 14 +++---- 2 files changed, 47 insertions(+), 47 deletions(-) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 64d5d435b9..353f030d80 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -31,47 +31,47 @@ /* * This version of the OpenTitan machine currently supports * OpenTitan RTL version: - * + * * * MMIO mapping as per (specified commit): * lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h */ static const MemMapEntry ibex_memmap[] =3D { - [IBEX_DEV_ROM] =3D { 0x00008000, 0x8000 }, - [IBEX_DEV_RAM] =3D { 0x10000000, 0x20000 }, - [IBEX_DEV_FLASH] =3D { 0x20000000, 0x100000 }, - [IBEX_DEV_UART] =3D { 0x40000000, 0x1000 }, - [IBEX_DEV_GPIO] =3D { 0x40040000, 0x1000 }, - [IBEX_DEV_SPI_DEVICE] =3D { 0x40050000, 0x1000 }, - [IBEX_DEV_I2C] =3D { 0x40080000, 0x1000 }, - [IBEX_DEV_PATTGEN] =3D { 0x400e0000, 0x1000 }, - [IBEX_DEV_TIMER] =3D { 0x40100000, 0x1000 }, - [IBEX_DEV_OTP_CTRL] =3D { 0x40130000, 0x4000 }, - [IBEX_DEV_LC_CTRL] =3D { 0x40140000, 0x1000 }, - [IBEX_DEV_ALERT_HANDLER] =3D { 0x40150000, 0x1000 }, - [IBEX_DEV_SPI_HOST0] =3D { 0x40300000, 0x1000 }, - [IBEX_DEV_SPI_HOST1] =3D { 0x40310000, 0x1000 }, - [IBEX_DEV_USBDEV] =3D { 0x40320000, 0x1000 }, - [IBEX_DEV_PWRMGR] =3D { 0x40400000, 0x1000 }, - [IBEX_DEV_RSTMGR] =3D { 0x40410000, 0x1000 }, - [IBEX_DEV_CLKMGR] =3D { 0x40420000, 0x1000 }, - [IBEX_DEV_PINMUX] =3D { 0x40460000, 0x1000 }, - [IBEX_DEV_AON_TIMER] =3D { 0x40470000, 0x1000 }, - [IBEX_DEV_SENSOR_CTRL] =3D { 0x40490000, 0x1000 }, - [IBEX_DEV_FLASH_CTRL] =3D { 0x41000000, 0x1000 }, - [IBEX_DEV_AES] =3D { 0x41100000, 0x1000 }, - [IBEX_DEV_HMAC] =3D { 0x41110000, 0x1000 }, - [IBEX_DEV_KMAC] =3D { 0x41120000, 0x1000 }, - [IBEX_DEV_OTBN] =3D { 0x41130000, 0x10000 }, - [IBEX_DEV_KEYMGR] =3D { 0x41140000, 0x1000 }, - [IBEX_DEV_CSRNG] =3D { 0x41150000, 0x1000 }, - [IBEX_DEV_ENTROPY] =3D { 0x41160000, 0x1000 }, - [IBEX_DEV_EDNO] =3D { 0x41170000, 0x1000 }, - [IBEX_DEV_EDN1] =3D { 0x41180000, 0x1000 }, - [IBEX_DEV_NMI_GEN] =3D { 0x411c0000, 0x1000 }, - [IBEX_DEV_PERI] =3D { 0x411f0000, 0x10000 }, - [IBEX_DEV_PLIC] =3D { 0x48000000, 0x4005000 }, - [IBEX_DEV_FLASH_VIRTUAL] =3D { 0x80000000, 0x80000 }, + [IBEX_DEV_ROM] =3D { 0x00008000, 0x8000 }, + [IBEX_DEV_RAM] =3D { 0x10000000, 0x20000 }, + [IBEX_DEV_FLASH] =3D { 0x20000000, 0x100000 }, + [IBEX_DEV_UART] =3D { 0x40000000, 0x40 }, + [IBEX_DEV_GPIO] =3D { 0x40040000, 0x40 }, + [IBEX_DEV_SPI_DEVICE] =3D { 0x40050000, 0x2000 }, + [IBEX_DEV_I2C] =3D { 0x40080000, 0x80 }, + [IBEX_DEV_PATTGEN] =3D { 0x400e0000, 0x40 }, + [IBEX_DEV_TIMER] =3D { 0x40100000, 0x200 }, + [IBEX_DEV_OTP_CTRL] =3D { 0x40130000, 0x2000 }, + [IBEX_DEV_LC_CTRL] =3D { 0x40140000, 0x100 }, + [IBEX_DEV_ALERT_HANDLER] =3D { 0x40150000, 0x800 }, + [IBEX_DEV_SPI_HOST0] =3D { 0x40300000, 0x40 }, + [IBEX_DEV_SPI_HOST1] =3D { 0x40310000, 0x40 }, + [IBEX_DEV_USBDEV] =3D { 0x40320000, 0x1000 }, + [IBEX_DEV_PWRMGR] =3D { 0x40400000, 0x80 }, + [IBEX_DEV_RSTMGR] =3D { 0x40410000, 0x80 }, + [IBEX_DEV_CLKMGR] =3D { 0x40420000, 0x80 }, + [IBEX_DEV_PINMUX] =3D { 0x40460000, 0x1000 }, + [IBEX_DEV_AON_TIMER] =3D { 0x40470000, 0x40 }, + [IBEX_DEV_SENSOR_CTRL] =3D { 0x40490000, 0x40 }, + [IBEX_DEV_FLASH_CTRL] =3D { 0x41000000, 0x200 }, + [IBEX_DEV_AES] =3D { 0x41100000, 0x100 }, + [IBEX_DEV_HMAC] =3D { 0x41110000, 0x1000 }, + [IBEX_DEV_KMAC] =3D { 0x41120000, 0x1000 }, + [IBEX_DEV_OTBN] =3D { 0x41130000, 0x10000 }, + [IBEX_DEV_KEYMGR] =3D { 0x41140000, 0x100 }, + [IBEX_DEV_CSRNG] =3D { 0x41150000, 0x80 }, + [IBEX_DEV_ENTROPY] =3D { 0x41160000, 0x100 }, + [IBEX_DEV_EDNO] =3D { 0x41170000, 0x80 }, + [IBEX_DEV_EDN1] =3D { 0x41180000, 0x80 }, + [IBEX_DEV_SRAM_CTRL] =3D { 0x411c0000, 0x20 }, + [IBEX_DEV_IBEX_CFG] =3D { 0x411f0000, 0x100 }, + [IBEX_DEV_PLIC] =3D { 0x48000000, 0x8000000 }, + [IBEX_DEV_FLASH_VIRTUAL] =3D { 0x80000000, 0x80000 }, }; =20 static void opentitan_board_init(MachineState *machine) @@ -294,12 +294,12 @@ static void lowrisc_ibex_soc_realize(DeviceState *d= ev_soc, Error **errp) memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size); create_unimplemented_device("riscv.lowrisc.ibex.alert_handler", memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDL= ER].size); - create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen", - memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size); + create_unimplemented_device("riscv.lowrisc.ibex.sram_ctrl", + memmap[IBEX_DEV_SRAM_CTRL].base, memmap[IBEX_DEV_SRAM_CTRL].size= ); create_unimplemented_device("riscv.lowrisc.ibex.otbn", memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size); - create_unimplemented_device("riscv.lowrisc.ibex.peri", - memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size); + create_unimplemented_device("riscv.lowrisc.ibex.ibex_cfg", + memmap[IBEX_DEV_IBEX_CFG].base, memmap[IBEX_DEV_IBEX_CFG].size); } =20 static Property lowrisc_ibex_soc_props[] =3D { diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index 7659d1bc5b..c40b05052a 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -94,9 +94,9 @@ enum { IBEX_DEV_EDNO, IBEX_DEV_EDN1, IBEX_DEV_ALERT_HANDLER, - IBEX_DEV_NMI_GEN, + IBEX_DEV_SRAM_CTRL, IBEX_DEV_OTBN, - IBEX_DEV_PERI, + IBEX_DEV_IBEX_CFG, }; =20 enum { @@ -108,11 +108,11 @@ enum { IBEX_UART0_RX_BREAK_ERR_IRQ =3D 6, IBEX_UART0_RX_TIMEOUT_IRQ =3D 7, IBEX_UART0_RX_PARITY_ERR_IRQ =3D 8, - IBEX_TIMER_TIMEREXPIRED0_0 =3D 127, - IBEX_SPI_HOST0_ERR_IRQ =3D 134, - IBEX_SPI_HOST0_SPI_EVENT_IRQ =3D 135, - IBEX_SPI_HOST1_ERR_IRQ =3D 136, - IBEX_SPI_HOST1_SPI_EVENT_IRQ =3D 137, + IBEX_TIMER_TIMEREXPIRED0_0 =3D 124, + IBEX_SPI_HOST0_ERR_IRQ =3D 131, + IBEX_SPI_HOST0_SPI_EVENT_IRQ =3D 132, + IBEX_SPI_HOST1_ERR_IRQ =3D 133, + IBEX_SPI_HOST1_SPI_EVENT_IRQ =3D 134, }; =20 #endif --=20 2.39.1 From MAILER-DAEMON Mon Jan 23 04:03:33 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJsjk-00088r-Ue for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 04:03:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJsji-00088Z-Fs for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 04:03:30 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJsjg-0003PN-Ki for qemu-riscv@nongnu.org; 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[2.7.42.160]) by smtp.gmail.com with ESMTPSA id e17-20020adfe7d1000000b0024cb961b6aesm4313537wrn.104.2023.01.23.01.03.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 01:03:26 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v6 0/5] riscv: Allow user to set the satp mode Date: Mon, 23 Jan 2023 10:03:19 +0100 Message-Id: <20230123090324.732681-1-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x436.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 09:03:30 -0000 This introduces new properties to allow the user to set the satp mode, see patch 3 for full syntax. In addition, it prevents cpus to boot in a satp mode they do not support (see patch 5). v6: - Remove the valid_vm check in validate_vm and add it to the finalize function so that map already contains the constraint, Alex - Add forgotten mbare to satp_mode_from_str, Alex - Move satp mode properties handling to riscv_cpu_satp_mode_finalize, Andrew - Only add satp mode properties corresponding to the cpu, and then remove the check against valid_vm_1_10_32/64 in riscv_cpu_satp_mode_finalize, Andrew/Alistair/Alex - Move mmu-type setting to its own patch, Andrew - patch 5 is new and is a fix, Alex v5: - Simplify v4 implementation by leveraging valid_vm_1_10_32/64, as suggested by Andrew - Split the v4 patch into 2 patches as suggested by Andrew - Lot of other minor corrections, from Andrew - Set the satp mode N by disabling the satp mode N + 1 - Add a helper to set satp mode from a string, as suggested by Frank v4: - Use custom boolean properties instead of OnOffAuto properties, based on ARMVQMap, as suggested by Andrew v3: - Free sv_name as pointed by Bin - Replace satp-mode with boolean properties as suggested by Andrew - Removed RB from Atish as the patch considerably changed v2: - Use error_setg + return as suggested by Alistair - Add RB from Atish - Fixed checkpatch issues missed in v1 - Replaced Ludovic email address with the rivos one Alexandre Ghiti (5): riscv: Pass Object to register_cpu_props instead of DeviceState riscv: Change type of valid_vm_1_10_[32|64] to bool riscv: Allow user to set the satp mode riscv: Correctly set the device-tree entry 'mmu-type' riscv: Introduce satp mode hw capabilities hw/riscv/virt.c | 19 ++-- target/riscv/cpu.c | 247 +++++++++++++++++++++++++++++++++++++++++++-- target/riscv/cpu.h | 23 +++++ target/riscv/csr.c | 29 +++--- 4 files changed, 287 insertions(+), 31 deletions(-) -- 2.37.2 From MAILER-DAEMON Mon Jan 23 04:04:33 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJskj-0000PY-3j for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 04:04:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJskh-0000OQ-5n for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 04:04:31 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJskf-0003Ui-0u for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 04:04:30 -0500 Received: by mail-wr1-x432.google.com with SMTP id r9so10090443wrw.4 for ; Mon, 23 Jan 2023 01:04:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=duFDaakbwIRfk/K0lg2ZD1Dq5YvZUrqFJqMDHNa4J+A=; b=7Ojuk0BmAvuxJMGbL2anNJZNnYslIJnYQsJtPkHXcBf5gjGFLDyF2gEHWIDeoVNsuA GPNQECBgXkGIAyJLc97Klf0zNZP0a7tYsurIYdP/EGlX4MwsH4RFDh1SaLnkfKFGO0/z kDAgO0uuS9AyNWF3CpcrEsLyrex/eLlEX7fku+pcm+R7VfGSujKMytW0iDCBuLVW72fX oLu6QU9m2M+aO13TycK/dXaG50R0B9iBHFkUPn02dnSiUNdTsFNIuRXUBOLUZr+n4v82 cMxKaAvUpBDhi4i9b0rGA/sQ0dw7u/SfF29F8crxWWXrNJc7P/dN8eIOdvYPzMcsJIHs q7rA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=duFDaakbwIRfk/K0lg2ZD1Dq5YvZUrqFJqMDHNa4J+A=; b=QNrlEw/oP67pfvppGHuT2/ygvwfa1hFXSAcwp8iiiBt2qlGP2SKpBabkrkArLHZ47Q u5n+xV0On2eiJQoazjNK4HRLkAyzCE3DpDKRJUOX1UD3m8fuLbBLqtBA2XK2acwpdmfY vqaHqI1V4j4Ns5J+KtvR63mcRjhT9LIsWsM+wBCAqZj2o0h9WodEFzWrS0PE3IAIVwQZ CDXNsZ7V/TO+tnRR+pGRo8C5XE3ndqNHXuVH78tR+MQkR7emnCBEtboCUocVn8t2CUg8 /n+xQvvy7eiNYjJqAvWX0UWQB5aYRrax82rSg6cyS9dHcSmRYUCqQ7Kjr0id/Ax47KvR fPMQ== X-Gm-Message-State: AFqh2koZcX194yi5cU5IZU7dwIZyKCsG927mFkE397yw1z5juX0H4zjK OXOVnjtZdhv61lp6KQBb9qNA3Q== X-Google-Smtp-Source: AMrXdXtno35GXuCPP2kgqufW+ivWpz6mZ4yJP632wtY1BW1CBowyAAY3RLue1YuiNbfph6dswyLOYQ== X-Received: by 2002:adf:ec88:0:b0:256:ff7d:2346 with SMTP id z8-20020adfec88000000b00256ff7d2346mr21082578wrn.51.1674464667283; Mon, 23 Jan 2023 01:04:27 -0800 (PST) Received: from alex-rivos.ba.rivosinc.com (lfbn-lyo-1-450-160.w2-7.abo.wanadoo.fr. [2.7.42.160]) by smtp.gmail.com with ESMTPSA id h9-20020a5d4fc9000000b002bbb2d43f65sm2572714wrw.14.2023.01.23.01.04.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 01:04:27 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v6 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState Date: Mon, 23 Jan 2023 10:03:20 +0100 Message-Id: <20230123090324.732681-2-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230123090324.732681-1-alexghiti@rivosinc.com> References: <20230123090324.732681-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 09:04:31 -0000 One can extract the DeviceState pointer from the Object pointer, so pass the Object for future commits to access other fields of Object. No functional changes intended. Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Reviewed-by: Andrew Jones Signed-off-by: Alexandre Ghiti --- target/riscv/cpu.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cc75ca7667..7181b34f86 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -200,7 +200,7 @@ static const char * const riscv_intr_names[] = { "reserved" }; -static void register_cpu_props(DeviceState *dev); +static void register_cpu_props(Object *obj); const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { @@ -238,7 +238,7 @@ static void riscv_any_cpu_init(Object *obj) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif set_priv_version(env, PRIV_VERSION_1_12_0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); } #if defined(TARGET_RISCV64) @@ -247,7 +247,7 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -280,7 +280,7 @@ static void rv128_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -290,7 +290,7 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -343,7 +343,7 @@ static void riscv_host_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, 0); #endif - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); } #endif @@ -1083,9 +1083,10 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_END_OF_LIST(), }; -static void register_cpu_props(DeviceState *dev) +static void register_cpu_props(Object *obj) { Property *prop; + DeviceState *dev = DEVICE(obj); for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); -- 2.37.2 From MAILER-DAEMON Mon Jan 23 04:05:36 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJslk-00017m-7m for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 04:05:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJslh-00017K-7h for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 04:05:34 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJsld-0003q3-Iq for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 04:05:31 -0500 Received: by mail-wr1-x434.google.com with SMTP id b7so10102615wrt.3 for ; Mon, 23 Jan 2023 01:05:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8spMprAsa6MCDDlueScecGJZmjzYC45CUjlzeSiGbvw=; b=Me8RZhnnAW/q1wRaMAqB2blaKMubDBwL49QrlR/hfuFrOGw/KnuYha9Y2E1QuMW8eY kK9+G9P2doFJst10IHfE/jJ9GRASt29FgAy+A7bN04TKHxLgOKV+P3nXP92vPpwNP8gp 9l9QtfWQBgwI5MO7ncJYhAdc0K2f1r6o2GXDYoTw64QEPBmf0xogUQ5rvcUZHL1aLR3p jxVXGuNO9/2FtXT88F7s34t1RKkFTxaMsAvdnFlKZAsKEZ1yxaPIoAkrgq4Ya7vwlyWU 4lPxpB7RWD4PtGHDqb6xbXAwPwnWakxv6sQ+9ZOlAmWHztjHXu8/PWIpgMuaQsB3clpv VIvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8spMprAsa6MCDDlueScecGJZmjzYC45CUjlzeSiGbvw=; b=SJjgFxuSEDryzLgxxGyMlsxeT7RuMiAEQ7cKEasus7Z5qpNSkwy+uojeyUrY2g6OMO p8NmX5PDrUm4Xdl4nQU4TML1ZDTzG41cW7nhzm/Y2fxIyJ6sk91N6+fX3mcC5qWcq+2d OQPZeQbscETjArCuefQMAC0ZAU+dnNCcDMmYPNORIGeuN1TsWojdKCWkIpufLmcYZ3f0 +HxEP0q+8lKA68rXrC3zbITgvMqzr9OQeZXpb5HSbREC/K6DLnJP9m1okYk31F9aZa4+ kUa+8syd7MGoSIMwZgzMgv+rm8CKdgN5sxk3U/HGF22PkXinr+9PT69/sR3uskbpUNqP +KnQ== X-Gm-Message-State: AFqh2koBuMXgxD/v7zOXJytqf2bPcVEi90Y7IQ/RAnk/4XDcVbJpdQwh xEL++xSrJ7eh5RchEoyLwj8WEg== X-Google-Smtp-Source: AMrXdXvtHyd1eUX/ehqKeFeoqQUSVyfsytqHWT11mpw4NqyEkE4/4E925rGFx3FrDKtqRnz2queV5w== X-Received: by 2002:adf:f501:0:b0:2ba:dce5:ee28 with SMTP id q1-20020adff501000000b002badce5ee28mr20090467wro.18.1674464728211; Mon, 23 Jan 2023 01:05:28 -0800 (PST) Received: from alex-rivos.ba.rivosinc.com (lfbn-lyo-1-450-160.w2-7.abo.wanadoo.fr. [2.7.42.160]) by smtp.gmail.com with ESMTPSA id t13-20020adfe10d000000b002b6bcc0b64dsm29827405wrz.4.2023.01.23.01.05.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 01:05:27 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v6 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool Date: Mon, 23 Jan 2023 10:03:21 +0100 Message-Id: <20230123090324.732681-3-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230123090324.732681-1-alexghiti@rivosinc.com> References: <20230123090324.732681-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 09:05:34 -0000 This array is actually used as a boolean so swap its current char type to a boolean and at the same time, change the type of validate_vm to bool since it returns valid_vm_1_10_[32|64]. Signed-off-by: Alexandre Ghiti --- target/riscv/csr.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0db2c233e5..6b157806a5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1117,16 +1117,16 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; static const target_ulong vsip_writable_mask = MIP_VSSIP; -static const char valid_vm_1_10_32[16] = { - [VM_1_10_MBARE] = 1, - [VM_1_10_SV32] = 1 +static const bool valid_vm_1_10_32[16] = { + [VM_1_10_MBARE] = true, + [VM_1_10_SV32] = true }; -static const char valid_vm_1_10_64[16] = { - [VM_1_10_MBARE] = 1, - [VM_1_10_SV39] = 1, - [VM_1_10_SV48] = 1, - [VM_1_10_SV57] = 1 +static const bool valid_vm_1_10_64[16] = { + [VM_1_10_MBARE] = true, + [VM_1_10_SV39] = true, + [VM_1_10_SV48] = true, + [VM_1_10_SV57] = true }; /* Machine Information Registers */ @@ -1209,7 +1209,7 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static int validate_vm(CPURISCVState *env, target_ulong vm) +static bool validate_vm(CPURISCVState *env, target_ulong vm) { if (riscv_cpu_mxl(env) == MXL_RV32) { return valid_vm_1_10_32[vm & 0xf]; @@ -2648,7 +2648,8 @@ static RISCVException read_satp(CPURISCVState *env, int csrno, static RISCVException write_satp(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong vm, mask; + target_ulong mask; + bool vm; if (!riscv_feature(env, RISCV_FEATURE_MMU)) { return RISCV_EXCP_NONE; -- 2.37.2 From MAILER-DAEMON Mon Jan 23 04:06:33 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJsmf-0002MW-B7 for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 04:06:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJsme-0002Ij-Ku for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 04:06:32 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJsmc-0003ye-Dn for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 04:06:32 -0500 Received: by mail-wr1-x432.google.com with SMTP id r9so10095412wrw.4 for ; Mon, 23 Jan 2023 01:06:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5y1u+iA0lffnBWequUWRNtiLHQ5dabBRmqn3ZAdpew4=; b=ZpnK95I9vUfEC+zLL72nsUf9FYHDen2W/NkmJcM8E4tuMm00OYhsswog2i90M/qQG7 vdUPZnt65e/lyizGGyKY9eURXahliXFsr1taFnuw4PDTgddfZq0RQV2wf6FFDRf4umIF y4eY7O0JZuPl7DXGMzfe98qxdUEB2UbcZkBWW1Epz07LfDOFFFbwyMNRtE9cbbPKgDOF 76bE6qlX9vzgHfjstPs13KgZt3RMst2di5kMO8u/bfxwYtarnP36Zt7uK/5Y+E+30VVr KE3PPOutbMKT3OT5RjSAQM5pxwkBVPY2wVDHOP7MuFNyppYbr1AbrP3Bet1mnut3IKur gr4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5y1u+iA0lffnBWequUWRNtiLHQ5dabBRmqn3ZAdpew4=; b=Co9ssMJNCd7oeC/m7KzM7hweKfQY+NJne+SO1RLFuan3AS6AP6/l1ypp6P+55DXZDd l7wi2/CsoEAD/JaLmpmIZcEVN1iWCMZlSECCWzoM4ue7jTAj9qB/K9YUrS8/o9dRgPod 6oq52jMCj9+XDtIiZOeQbgN+BizXv5BupFKFZkP1x/Q4x3KvMFMqhcHjyB7DpIx64tMs 4Cs+JW4hZSSKzyojApuv05dpSoTo2Zt9yvrEZtV6XAMq73GK0nBrrnk57ezmMDcjF9yq 7yd1lHLV8YI4WsPkC/+KBJLaz6ZlMUIITZU+lA8zlaADN1M5OGea6D7zXxfyAJ9izzsX 4QQA== X-Gm-Message-State: AFqh2kpSrmFrwMy5aB891xBstAIG5aTxLdYRUm9hQwAlvrOKLqA7Lpyq zcuo+pD2RhELsgh115WqisaufA== X-Google-Smtp-Source: AMrXdXv3uZk/GWuxqnhqPLPeJsyJOarwyQ7v+bRV8pAXRutiqnNEbtE5qixi2Z8EbDi1rQgjhMSImw== X-Received: by 2002:a05:6000:a16:b0:2b1:c393:cbe with SMTP id co22-20020a0560000a1600b002b1c3930cbemr16151925wrb.11.1674464789102; Mon, 23 Jan 2023 01:06:29 -0800 (PST) Received: from alex-rivos.ba.rivosinc.com (lfbn-lyo-1-450-160.w2-7.abo.wanadoo.fr. [2.7.42.160]) by smtp.gmail.com with ESMTPSA id u24-20020adfa198000000b002bc84c55758sm41286539wru.63.2023.01.23.01.06.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 01:06:28 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Ludovic Henry Subject: [PATCH v6 3/5] riscv: Allow user to set the satp mode Date: Mon, 23 Jan 2023 10:03:22 +0100 Message-Id: <20230123090324.732681-4-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230123090324.732681-1-alexghiti@rivosinc.com> References: <20230123090324.732681-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 09:06:32 -0000 RISC-V specifies multiple sizes for addressable memory and Linux probes for the machine's support at startup via the satp CSR register (done in csr.c:validate_vm). As per the specification, sv64 must support sv57, which in turn must support sv48...etc. So we can restrict machine support by simply setting the "highest" supported mode and the bare mode is always supported. You can set the satp mode using the new properties "sv32", "sv39", "sv48", "sv57" and "sv64" as follows: -cpu rv64,sv57=on # Linux will boot using sv57 scheme -cpu rv64,sv39=on # Linux will boot using sv39 scheme -cpu rv64,sv57=off # Linux will boot using sv48 scheme -cpu rv64 # Linux will boot using sv57 scheme by default We take the highest level set by the user: -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme We make sure that invalid configurations are rejected: -cpu rv64,sv32=on # Can't enable 32-bit satp mode in 64-bit -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are # enabled We accept "redundant" configurations: -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme And contradictory configurations: -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme In addition, we now correctly set the device-tree entry 'mmu-type' using those new properties. Co-Developed-by: Ludovic Henry Signed-off-by: Ludovic Henry Signed-off-by: Alexandre Ghiti --- target/riscv/cpu.c | 204 +++++++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 19 +++++ target/riscv/csr.c | 12 ++- 3 files changed, 228 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7181b34f86..e409e6ab64 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -27,6 +27,7 @@ #include "time_helper.h" #include "exec/exec-all.h" #include "qapi/error.h" +#include "qapi/visitor.h" #include "qemu/error-report.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" @@ -229,6 +230,79 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) env->vext_ver = vext_ver; } +static uint8_t satp_mode_from_str(const char *satp_mode_str) +{ + if (!strncmp(satp_mode_str, "mbare", 5)) { + return VM_1_10_MBARE; + } + + if (!strncmp(satp_mode_str, "sv32", 4)) { + return VM_1_10_SV32; + } + + if (!strncmp(satp_mode_str, "sv39", 4)) { + return VM_1_10_SV39; + } + + if (!strncmp(satp_mode_str, "sv48", 4)) { + return VM_1_10_SV48; + } + + if (!strncmp(satp_mode_str, "sv57", 4)) { + return VM_1_10_SV57; + } + + if (!strncmp(satp_mode_str, "sv64", 4)) { + return VM_1_10_SV64; + } + + g_assert_not_reached(); +} + +uint8_t satp_mode_max_from_map(uint32_t map) +{ + /* map here has at least one bit set, so no problem with clz */ + return 31 - __builtin_clz(map); +} + +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) +{ + if (is_32_bit) { + switch (satp_mode) { + case VM_1_10_SV32: + return "sv32"; + case VM_1_10_MBARE: + return "none"; + } + } else { + switch (satp_mode) { + case VM_1_10_SV64: + return "sv64"; + case VM_1_10_SV57: + return "sv57"; + case VM_1_10_SV48: + return "sv48"; + case VM_1_10_SV39: + return "sv39"; + case VM_1_10_MBARE: + return "none"; + } + } + + g_assert_not_reached(); +} + +/* Sets the satp mode to the max supported */ +static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit) +{ + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { + cpu->cfg.satp_mode.map |= + (1 << satp_mode_from_str(is_32_bit ? "sv32" : "sv57")); + } else { + cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); + } +} + static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; @@ -619,6 +693,82 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) } } +static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) +{ + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; + + if (cpu->cfg.satp_mode.map == 0) { + /* + * If unset by both the user and the cpu, we fallback to the default + * satp mode. + */ + if (cpu->cfg.satp_mode.init == 0) { + set_satp_mode_default(cpu, rv32); + } else { + /* + * Find the lowest level that was disabled and then enable the + * first valid level below which can be found in + * valid_vm_1_10_32/64. + */ + for (int i = 1; i < 16; ++i) { + if (!(cpu->cfg.satp_mode.map & (1 << i)) && + (cpu->cfg.satp_mode.init & (1 << i)) && + valid_vm[i]) { + for (int j = i - 1; j >= 0; --j) { + if (valid_vm[j]) { + cpu->cfg.satp_mode.map |= (1 << j); + break; + } + } + break; + } + } + } + } + + /* Make sure the configuration asked is supported by qemu */ + for (int i = 0; i < 16; ++i) { + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { + error_setg(errp, "satp_mode %s is not valid", + satp_mode_str(i, rv32)); + return; + } + } + + /* + * Make sure the user did not ask for an invalid configuration as per + * the specification. + */ + if (!rv32) { + uint8_t satp_mode_max; + + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); + + for (int i = satp_mode_max - 1; i >= 0; --i) { + if (!(cpu->cfg.satp_mode.map & (1 << i)) && + (cpu->cfg.satp_mode.init & (1 << i)) && + valid_vm[i]) { + error_setg(errp, "cannot disable %s satp mode if %s " + "is enabled", satp_mode_str(i, false), + satp_mode_str(satp_mode_max, false)); + return; + } + } + } +} + +static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) +{ + Error *local_err = NULL; + + riscv_cpu_satp_mode_finalize(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } +} + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -919,6 +1069,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } #endif + riscv_cpu_finalize_features(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + riscv_cpu_register_gdb_regs_for_features(cs); qemu_init_vcpu(cs); @@ -927,6 +1083,52 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) mcc->parent_realize(dev, errp); } +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVSATPMap *satp_map = opaque; + uint8_t satp = satp_mode_from_str(name); + bool value; + + value = (satp_map->map & (1 << satp)); + + visit_type_bool(v, name, &value, errp); +} + +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVSATPMap *satp_map = opaque; + uint8_t satp = satp_mode_from_str(name); + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + satp_map->map = deposit32(satp_map->map, satp, 1, value); + satp_map->init |= 1 << satp; +} + +static void riscv_add_satp_mode_properties(Object *obj) +{ + RISCVCPU *cpu = RISCV_CPU(obj); + + if (cpu->env.misa_mxl == MXL_RV32) { + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + } else { + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + } +} + #ifndef CONFIG_USER_ONLY static void riscv_cpu_set_irq(void *opaque, int irq, int level) { @@ -1091,6 +1293,8 @@ static void register_cpu_props(Object *obj) for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } + + riscv_add_satp_mode_properties(obj); } static Property riscv_cpu_properties[] = { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f5609b62a2..e37177db5c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -27,6 +27,7 @@ #include "qom/object.h" #include "qemu/int128.h" #include "cpu_bits.h" +#include "qapi/qapi-types-common.h" #define TCG_GUEST_DEFAULT_MO 0 @@ -413,6 +414,17 @@ struct RISCVCPUClass { ResettablePhases parent_phases; }; +/* + * map is a 16-bit bitmap: the most significant set bit in map is the maximum + * satp mode that is supported. + * + * init is a 16-bit bitmap used to make sure the user selected a correct + * configuration as per the specification. + */ +typedef struct { + uint16_t map, init; +} RISCVSATPMap; + struct RISCVCPUConfig { bool ext_i; bool ext_e; @@ -488,6 +500,8 @@ struct RISCVCPUConfig { bool debug; bool short_isa_string; + + RISCVSATPMap satp_mode; }; typedef struct RISCVCPUConfig RISCVCPUConfig; @@ -794,9 +808,14 @@ enum riscv_pmu_event_idx { /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; +extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; + void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); +uint8_t satp_mode_max_from_map(uint32_t map); +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); + #endif /* RISCV_CPU_H */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6b157806a5..3c02055825 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1117,12 +1117,12 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; static const target_ulong vsip_writable_mask = MIP_VSSIP; -static const bool valid_vm_1_10_32[16] = { +const bool valid_vm_1_10_32[16] = { [VM_1_10_MBARE] = true, [VM_1_10_SV32] = true }; -static const bool valid_vm_1_10_64[16] = { +const bool valid_vm_1_10_64[16] = { [VM_1_10_MBARE] = true, [VM_1_10_SV39] = true, [VM_1_10_SV48] = true, @@ -1211,11 +1211,9 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, static bool validate_vm(CPURISCVState *env, target_ulong vm) { - if (riscv_cpu_mxl(env) == MXL_RV32) { - return valid_vm_1_10_32[vm & 0xf]; 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[2.7.42.160]) by smtp.gmail.com with ESMTPSA id n35-20020a05600c3ba300b003db12112fcfsm11356682wms.4.2023.01.23.01.07.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 01:07:29 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v6 4/5] riscv: Correctly set the device-tree entry 'mmu-type' Date: Mon, 23 Jan 2023 10:03:23 +0100 Message-Id: <20230123090324.732681-5-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230123090324.732681-1-alexghiti@rivosinc.com> References: <20230123090324.732681-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 09:07:33 -0000 The 'mmu-type' should reflect what the hardware is capable of so use the new satp_mode field in RISCVCPUConfig to do that. Signed-off-by: Alexandre Ghiti --- hw/riscv/virt.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 94ff2a1584..48d034a5f7 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -228,7 +228,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, int cpu; uint32_t cpu_phandle; MachineState *mc = MACHINE(s); - char *name, *cpu_name, *core_name, *intc_name; + uint8_t satp_mode_max; + char *name, *cpu_name, *core_name, *intc_name, *sv_name; for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { cpu_phandle = (*phandle)++; @@ -236,14 +237,14 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(mc->fdt, cpu_name); - if (riscv_feature(&s->soc[socket].harts[cpu].env, - RISCV_FEATURE_MMU)) { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", - (is_32_bit) ? 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[2.7.42.160]) by smtp.gmail.com with ESMTPSA id f14-20020a05600c154e00b003daff80f16esm13908803wmg.27.2023.01.23.01.08.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 01:08:30 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities Date: Mon, 23 Jan 2023 10:03:24 +0100 Message-Id: <20230123090324.732681-6-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230123090324.732681-1-alexghiti@rivosinc.com> References: <20230123090324.732681-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x32f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 09:08:36 -0000 Currently, the max satp mode is set with the only constraint that it must be implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. But we actually need to add another level of constraint: what the hw is actually capable of, because currently, a linux booting on a sifive-u54 boots in sv57 mode which is incompatible with the cpu's sv39 max capability. So add a new bitmap to RISCVSATPMap which contains this capability and initialize it in every XXX_cpu_init. Finally, we have the following chain of constraints: Qemu capability > HW capability > User choice > Software capability Signed-off-by: Alexandre Ghiti --- target/riscv/cpu.c | 78 +++++++++++++++++++++++++++++++--------------- target/riscv/cpu.h | 8 +++-- 2 files changed, 59 insertions(+), 27 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e409e6ab64..19a37fee2b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -292,24 +292,39 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) g_assert_not_reached(); } -/* Sets the satp mode to the max supported */ -static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit) +static void set_satp_mode_max_supported(RISCVCPU *cpu, + const char *satp_mode_str, + bool is_32_bit) { - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { - cpu->cfg.satp_mode.map |= - (1 << satp_mode_from_str(is_32_bit ? "sv32" : "sv57")); - } else { - cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); + uint8_t satp_mode = satp_mode_from_str(satp_mode_str); + const bool *valid_vm = is_32_bit ? valid_vm_1_10_32 : valid_vm_1_10_64; + + for (int i = 0; i <= satp_mode; ++i) { + if (valid_vm[i]) { + cpu->cfg.satp_mode.supported |= (1 << i); + } } } +/* Sets the satp mode to the max supported */ +static void set_satp_mode_default(RISCVCPU *cpu) +{ + uint8_t satp_mode = satp_mode_max_from_map(cpu->cfg.satp_mode.supported); + + cpu->cfg.satp_mode.map |= (1 << satp_mode); +} + static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + #if defined(TARGET_RISCV32) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_satp_mode_max_supported(cpu, "sv32", true); #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_satp_mode_max_supported(cpu, "sv57", false); #endif set_priv_version(env, PRIV_VERSION_1_12_0); register_cpu_props(obj); @@ -319,18 +334,24 @@ static void riscv_any_cpu_init(Object *obj) static void rv64_base_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); + set_satp_mode_max_supported(cpu, "sv57", false); } static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); + set_satp_mode_max_supported(cpu, "sv39", false); } static void rv64_sifive_e_cpu_init(Object *obj) @@ -341,6 +362,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; + set_satp_mode_max_supported(cpu, "mbare", false); } static void rv128_base_cpu_init(Object *obj) @@ -352,11 +374,13 @@ static void rv128_base_cpu_init(Object *obj) exit(EXIT_FAILURE); } CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); + set_satp_mode_max_supported(cpu, "sv57", false); } #else static void rv32_base_cpu_init(Object *obj) @@ -367,13 +391,17 @@ static void rv32_base_cpu_init(Object *obj) register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); + set_satp_mode_max_supported(cpu, "sv32", true); } static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); + set_satp_mode_max_supported(cpu, "sv32", true); } static void rv32_sifive_e_cpu_init(Object *obj) @@ -384,6 +412,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; + set_satp_mode_max_supported(cpu, "mbare", true); } static void rv32_ibex_cpu_init(Object *obj) @@ -394,6 +423,7 @@ static void rv32_ibex_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.mmu = false; + set_satp_mode_max_supported(cpu, "mbare", true); cpu->cfg.epmp = true; } @@ -405,6 +435,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; + set_satp_mode_max_supported(cpu, "mbare", true); } #endif @@ -696,7 +727,9 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) { bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; - const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; + uint8_t satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); + uint8_t satp_mode_supported_max = + satp_mode_max_from_map(cpu->cfg.satp_mode.supported); if (cpu->cfg.satp_mode.map == 0) { /* @@ -704,7 +737,7 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) * satp mode. */ if (cpu->cfg.satp_mode.init == 0) { - set_satp_mode_default(cpu, rv32); + set_satp_mode_default(cpu); } else { /* * Find the lowest level that was disabled and then enable the @@ -714,9 +747,9 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) for (int i = 1; i < 16; ++i) { if (!(cpu->cfg.satp_mode.map & (1 << i)) && (cpu->cfg.satp_mode.init & (1 << i)) && - valid_vm[i]) { + (cpu->cfg.satp_mode.supported & (1 << i))) { for (int j = i - 1; j >= 0; --j) { - if (valid_vm[j]) { + if (cpu->cfg.satp_mode.supported & (1 << j)) { cpu->cfg.satp_mode.map |= (1 << j); break; } @@ -727,13 +760,12 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) } } - /* Make sure the configuration asked is supported by qemu */ - for (int i = 0; i < 16; ++i) { - if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { - error_setg(errp, "satp_mode %s is not valid", - satp_mode_str(i, rv32)); - return; - } + /* Make sure the user asked for a supported configuration (HW and qemu) */ + if (satp_mode_map_max > satp_mode_supported_max) { + error_setg(errp, "satp_mode %s is higher than hw max capability %s", + satp_mode_str(satp_mode_map_max, rv32), + satp_mode_str(satp_mode_supported_max, rv32)); + return; } /* @@ -741,17 +773,13 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) * the specification. */ if (!rv32) { - uint8_t satp_mode_max; - - satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); - - for (int i = satp_mode_max - 1; i >= 0; --i) { + for (int i = satp_mode_map_max - 1; i >= 0; --i) { if (!(cpu->cfg.satp_mode.map & (1 << i)) && (cpu->cfg.satp_mode.init & (1 << i)) && - valid_vm[i]) { + (cpu->cfg.satp_mode.supported & (1 << i))) { error_setg(errp, "cannot disable %s satp mode if %s " "is enabled", satp_mode_str(i, false), - satp_mode_str(satp_mode_max, false)); + satp_mode_str(satp_mode_map_max, false)); return; } } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e37177db5c..b591122099 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -416,13 +416,17 @@ struct RISCVCPUClass { /* * map is a 16-bit bitmap: the most significant set bit in map is the maximum - * satp mode that is supported. + * satp mode that is supported. It may be chosen by the user and must respect + * what qemu implements (valid_1_10_32/64) and what the hw is capable of + * (supported bitmap below). * * init is a 16-bit bitmap used to make sure the user selected a correct * configuration as per the specification. + * + * supported is a 16-bit bitmap used to reflect the hw capabilities. */ typedef struct { - uint16_t map, init; + uint16_t map, init, supported; } RISCVSATPMap; struct RISCVCPUConfig { -- 2.37.2 From MAILER-DAEMON Mon Jan 23 04:48:39 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJtRK-0005KN-Sc for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 04:48:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJtRI-0005Jz-Ea for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 04:48:32 -0500 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJtRG-0003KE-HK for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 04:48:31 -0500 Received: by mail-ed1-x52a.google.com with SMTP id g11so8379113eda.12 for ; Mon, 23 Jan 2023 01:48:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=SBM/C96GofxGllCvWI14+I+kD6WGsHTa+H4lr4tmoDw=; b=UG4vLTwSCPcHB/cOw72FHVeFgRHyj1XQ3+kjqVzsNBOlFuWpDPLM205aN9KBnEf13d u3SM3L30Gl+Hy14BNmXeEM+DCTVHbwj9bHrslykNpWFYYeoVOtv+RrFhEgCMyNxJKiSN aBDUwErX1N0z/SFQMp6JQXhve/WT2c1Sd9+jbfbDcsHGYODHWpCxaq39zDsVOR5hDm7o tJvNMNLVTZfXYks/bHBNi4T7VWi71ezzoSAn1OWi00yP0aEqWlSpszR/OoqqFcFKq0IX xtIxwgD4fBneg7FMbdaQ/6JQNwKRU4sFfzXs3JjQrEH/4sHY15WGPwpJb30L8iqctMeC LvjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=SBM/C96GofxGllCvWI14+I+kD6WGsHTa+H4lr4tmoDw=; b=ME3KNkeXz8GSdcbFep8mwG1y3DNvcHSe0GUM+aXXpPVEdt11UKeXJWpBrJBRu5eAVq FQnZrtgZxjTKB67iBPC2dkzLe3/19y/B1lN7Z/VmTrQzXB3Iz8hl4Am/h+aGcICZMdgo sSE3ezGcM0TTMR44GL1XfQiUzMIx28AOKBXqbsQ8/P9/k2AxC71thXV0S8DbmQsEYzxX AaBabFjyxZ9nxusMjIQUNW+JAuz1cpcszv3aYPQyTlMNEgi0baSbrKef/vrnInfH5UdH od43EYfsJrWJnkWwIGG+VqAebtxw0plBSRdX7TBRxpf8sXQ448+P1k29X1hXQ3narf3b 6hKw== X-Gm-Message-State: AFqh2kpGL+3qYpU5zC4N5CkVx7+5U6lNpO4CjTa618Ivz3oCyobt45jZ PifCzZbOcY8KksZ07+M0kLNaGw== X-Google-Smtp-Source: AMrXdXv1TPLvJaenhJn6oLD9uBeAbR0XmFvttWTso0dGT1n1s95PceQsuof0UDfo0LHR8E65oIZNRA== X-Received: by 2002:a05:6402:5110:b0:49d:32d0:126 with SMTP id m16-20020a056402511000b0049d32d00126mr30578288edd.20.1674467307887; Mon, 23 Jan 2023 01:48:27 -0800 (PST) Received: from localhost (cst2-173-16.cust.vodafone.cz. [31.30.173.16]) by smtp.gmail.com with ESMTPSA id r8-20020a05640251c800b0049df0f91b78sm12578154edd.78.2023.01.23.01.48.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 01:48:27 -0800 (PST) Date: Mon, 23 Jan 2023 10:48:26 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: Re: [PATCH v6 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool Message-ID: <20230123094826.sszyj5lq3ol3zoqy@orel> References: <20230123090324.732681-1-alexghiti@rivosinc.com> <20230123090324.732681-3-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230123090324.732681-3-alexghiti@rivosinc.com> Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=ajones@ventanamicro.com; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 09:48:32 -0000 On Mon, Jan 23, 2023 at 10:03:21AM +0100, Alexandre Ghiti wrote: > This array is actually used as a boolean so swap its current char type > to a boolean and at the same time, change the type of validate_vm to > bool since it returns valid_vm_1_10_[32|64]. > > Signed-off-by: Alexandre Ghiti Suggested-by: Andrew Jones Reviewed-by: Andrew Jones > --- > target/riscv/csr.c | 21 +++++++++++---------- > 1 file changed, 11 insertions(+), 10 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 0db2c233e5..6b157806a5 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1117,16 +1117,16 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; > static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; > static const target_ulong vsip_writable_mask = MIP_VSSIP; > > -static const char valid_vm_1_10_32[16] = { > - [VM_1_10_MBARE] = 1, > - [VM_1_10_SV32] = 1 > +static const bool valid_vm_1_10_32[16] = { > + [VM_1_10_MBARE] = true, > + [VM_1_10_SV32] = true > }; > > -static const char valid_vm_1_10_64[16] = { > - [VM_1_10_MBARE] = 1, > - [VM_1_10_SV39] = 1, > - [VM_1_10_SV48] = 1, > - [VM_1_10_SV57] = 1 > +static const bool valid_vm_1_10_64[16] = { > + [VM_1_10_MBARE] = true, > + [VM_1_10_SV39] = true, > + [VM_1_10_SV48] = true, > + [VM_1_10_SV57] = true > }; > > /* Machine Information Registers */ > @@ -1209,7 +1209,7 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, > return RISCV_EXCP_NONE; > } > > -static int validate_vm(CPURISCVState *env, target_ulong vm) > +static bool validate_vm(CPURISCVState *env, target_ulong vm) > { > if (riscv_cpu_mxl(env) == MXL_RV32) { > return valid_vm_1_10_32[vm & 0xf]; > @@ -2648,7 +2648,8 @@ static RISCVException read_satp(CPURISCVState *env, int csrno, > static RISCVException write_satp(CPURISCVState *env, int csrno, > target_ulong val) > { > - target_ulong vm, mask; > + target_ulong mask; > + bool vm; > > if (!riscv_feature(env, RISCV_FEATURE_MMU)) { > return RISCV_EXCP_NONE; > -- > 2.37.2 > From MAILER-DAEMON Mon Jan 23 05:11:21 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJtnN-0002Bh-EH for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 05:11:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJtnM-0002BK-1A for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 05:11:20 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJtnJ-00072Z-4s for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 05:11:19 -0500 Received: by mail-ej1-x62f.google.com with SMTP id v6so29075399ejg.6 for ; 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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id hq15-20020a1709073f0f00b0084c7029b24dsm22057708ejc.151.2023.01.23.02.11.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 02:11:15 -0800 (PST) Date: Mon, 23 Jan 2023 11:11:13 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Subject: Re: [PATCH v6 3/5] riscv: Allow user to set the satp mode Message-ID: <20230123101113.rqxi5dh7dawp6b4s@orel> References: <20230123090324.732681-1-alexghiti@rivosinc.com> <20230123090324.732681-4-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230123090324.732681-4-alexghiti@rivosinc.com> Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=ajones@ventanamicro.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 10:11:20 -0000 On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote: > RISC-V specifies multiple sizes for addressable memory and Linux probes for > the machine's support at startup via the satp CSR register (done in > csr.c:validate_vm). > > As per the specification, sv64 must support sv57, which in turn must > support sv48...etc. So we can restrict machine support by simply setting the > "highest" supported mode and the bare mode is always supported. > > You can set the satp mode using the new properties "sv32", "sv39", "sv48", > "sv57" and "sv64" as follows: > -cpu rv64,sv57=on # Linux will boot using sv57 scheme > -cpu rv64,sv39=on # Linux will boot using sv39 scheme > -cpu rv64,sv57=off # Linux will boot using sv48 scheme > -cpu rv64 # Linux will boot using sv57 scheme by default > > We take the highest level set by the user: > -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme > > We make sure that invalid configurations are rejected: > -cpu rv64,sv32=on # Can't enable 32-bit satp mode in 64-bit The property doesn't exist for rv64 anymore, so I'm not sure we need this info in the commit message. > -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are > # enabled > > We accept "redundant" configurations: > -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme > > And contradictory configurations: > -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme > > In addition, we now correctly set the device-tree entry 'mmu-type' using > those new properties. > > Co-Developed-by: Ludovic Henry > Signed-off-by: Ludovic Henry > Signed-off-by: Alexandre Ghiti > --- > target/riscv/cpu.c | 204 +++++++++++++++++++++++++++++++++++++++++++++ > target/riscv/cpu.h | 19 +++++ > target/riscv/csr.c | 12 ++- > 3 files changed, 228 insertions(+), 7 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 7181b34f86..e409e6ab64 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -27,6 +27,7 @@ > #include "time_helper.h" > #include "exec/exec-all.h" > #include "qapi/error.h" > +#include "qapi/visitor.h" > #include "qemu/error-report.h" > #include "hw/qdev-properties.h" > #include "migration/vmstate.h" > @@ -229,6 +230,79 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) > env->vext_ver = vext_ver; > } > > +static uint8_t satp_mode_from_str(const char *satp_mode_str) > +{ > + if (!strncmp(satp_mode_str, "mbare", 5)) { > + return VM_1_10_MBARE; > + } > + > + if (!strncmp(satp_mode_str, "sv32", 4)) { > + return VM_1_10_SV32; > + } > + > + if (!strncmp(satp_mode_str, "sv39", 4)) { > + return VM_1_10_SV39; > + } > + > + if (!strncmp(satp_mode_str, "sv48", 4)) { > + return VM_1_10_SV48; > + } > + > + if (!strncmp(satp_mode_str, "sv57", 4)) { > + return VM_1_10_SV57; > + } > + > + if (!strncmp(satp_mode_str, "sv64", 4)) { > + return VM_1_10_SV64; > + } > + > + g_assert_not_reached(); > +} > + > +uint8_t satp_mode_max_from_map(uint32_t map) > +{ > + /* map here has at least one bit set, so no problem with clz */ > + return 31 - __builtin_clz(map); > +} > + > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > +{ > + if (is_32_bit) { > + switch (satp_mode) { > + case VM_1_10_SV32: > + return "sv32"; > + case VM_1_10_MBARE: > + return "none"; > + } > + } else { > + switch (satp_mode) { > + case VM_1_10_SV64: > + return "sv64"; > + case VM_1_10_SV57: > + return "sv57"; > + case VM_1_10_SV48: > + return "sv48"; > + case VM_1_10_SV39: > + return "sv39"; > + case VM_1_10_MBARE: > + return "none"; > + } > + } > + > + g_assert_not_reached(); > +} > + > +/* Sets the satp mode to the max supported */ > +static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit) > +{ > + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > + cpu->cfg.satp_mode.map |= > + (1 << satp_mode_from_str(is_32_bit ? "sv32" : "sv57")); > + } else { > + cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > + } > +} > + > static void riscv_any_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > @@ -619,6 +693,82 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > } > } > > +static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > +{ > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > + > + if (cpu->cfg.satp_mode.map == 0) { > + /* > + * If unset by both the user and the cpu, we fallback to the default > + * satp mode. > + */ nit: I'd put the above comment under the if init == 0 below. > + if (cpu->cfg.satp_mode.init == 0) { > + set_satp_mode_default(cpu, rv32); > + } else { > + /* > + * Find the lowest level that was disabled and then enable the > + * first valid level below which can be found in > + * valid_vm_1_10_32/64. > + */ > + for (int i = 1; i < 16; ++i) { > + if (!(cpu->cfg.satp_mode.map & (1 << i)) && > + (cpu->cfg.satp_mode.init & (1 << i)) && > + valid_vm[i]) { > + for (int j = i - 1; j >= 0; --j) { > + if (valid_vm[j]) { > + cpu->cfg.satp_mode.map |= (1 << j); > + break; We don't want to break here, we want fully populate the map. Otherwise the future coming qmp_query_cpu_model_expansion() is going to produce results like rv39=off,rv48=off,rv57=on,rv64=off for the default because it gets its info from cpu_riscv_get_satp(), which only checks the map. > + } > + } > + break; > + } > + } > + } > + } > + > + /* Make sure the configuration asked is supported by qemu */ > + for (int i = 0; i < 16; ++i) { > + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > + error_setg(errp, "satp_mode %s is not valid", > + satp_mode_str(i, rv32)); > + return; > + } > + } > + > + /* > + * Make sure the user did not ask for an invalid configuration as per > + * the specification. > + */ > + if (!rv32) { > + uint8_t satp_mode_max; > + > + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > + > + for (int i = satp_mode_max - 1; i >= 0; --i) { > + if (!(cpu->cfg.satp_mode.map & (1 << i)) && > + (cpu->cfg.satp_mode.init & (1 << i)) && > + valid_vm[i]) { > + error_setg(errp, "cannot disable %s satp mode if %s " > + "is enabled", satp_mode_str(i, false), > + satp_mode_str(satp_mode_max, false)); > + return; > + } > + } > + } > +} > + > +static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > +{ > + Error *local_err = NULL; > + > + riscv_cpu_satp_mode_finalize(cpu, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > + } > +} > + > static void riscv_cpu_realize(DeviceState *dev, Error **errp) > { > CPUState *cs = CPU(dev); > @@ -919,6 +1069,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > #endif > > + riscv_cpu_finalize_features(cpu, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > + } > + > riscv_cpu_register_gdb_regs_for_features(cs); > > qemu_init_vcpu(cs); > @@ -927,6 +1083,52 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > mcc->parent_realize(dev, errp); > } > > +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + RISCVSATPMap *satp_map = opaque; > + uint8_t satp = satp_mode_from_str(name); > + bool value; > + > + value = (satp_map->map & (1 << satp)); > + > + visit_type_bool(v, name, &value, errp); > +} > + > +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + RISCVSATPMap *satp_map = opaque; > + uint8_t satp = satp_mode_from_str(name); > + bool value; > + > + if (!visit_type_bool(v, name, &value, errp)) { > + return; > + } > + > + satp_map->map = deposit32(satp_map->map, satp, 1, value); > + satp_map->init |= 1 << satp; > +} > + > +static void riscv_add_satp_mode_properties(Object *obj) > +{ > + RISCVCPU *cpu = RISCV_CPU(obj); > + > + if (cpu->env.misa_mxl == MXL_RV32) { > + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + } else { > + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + } > +} > + > #ifndef CONFIG_USER_ONLY > static void riscv_cpu_set_irq(void *opaque, int irq, int level) > { > @@ -1091,6 +1293,8 @@ static void register_cpu_props(Object *obj) > for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > qdev_property_add_static(dev, prop); > } > + > + riscv_add_satp_mode_properties(obj); > } > > static Property riscv_cpu_properties[] = { > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index f5609b62a2..e37177db5c 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -27,6 +27,7 @@ > #include "qom/object.h" > #include "qemu/int128.h" > #include "cpu_bits.h" > +#include "qapi/qapi-types-common.h" > > #define TCG_GUEST_DEFAULT_MO 0 > > @@ -413,6 +414,17 @@ struct RISCVCPUClass { > ResettablePhases parent_phases; > }; > > +/* > + * map is a 16-bit bitmap: the most significant set bit in map is the maximum > + * satp mode that is supported. > + * > + * init is a 16-bit bitmap used to make sure the user selected a correct > + * configuration as per the specification. > + */ > +typedef struct { > + uint16_t map, init; > +} RISCVSATPMap; > + > struct RISCVCPUConfig { > bool ext_i; > bool ext_e; > @@ -488,6 +500,8 @@ struct RISCVCPUConfig { > bool debug; > > bool short_isa_string; > + > + RISCVSATPMap satp_mode; > }; > > typedef struct RISCVCPUConfig RISCVCPUConfig; > @@ -794,9 +808,14 @@ enum riscv_pmu_event_idx { > /* CSR function table */ > extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; > > +extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; > + > void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); > void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); > > void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); > > +uint8_t satp_mode_max_from_map(uint32_t map); > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); > + > #endif /* RISCV_CPU_H */ > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 6b157806a5..3c02055825 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1117,12 +1117,12 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; > static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; > static const target_ulong vsip_writable_mask = MIP_VSSIP; > > -static const bool valid_vm_1_10_32[16] = { > +const bool valid_vm_1_10_32[16] = { > [VM_1_10_MBARE] = true, > [VM_1_10_SV32] = true > }; > > -static const bool valid_vm_1_10_64[16] = { > +const bool valid_vm_1_10_64[16] = { > [VM_1_10_MBARE] = true, > [VM_1_10_SV39] = true, > [VM_1_10_SV48] = true, > @@ -1211,11 +1211,9 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, > > static bool validate_vm(CPURISCVState *env, target_ulong vm) > { > - if (riscv_cpu_mxl(env) == MXL_RV32) { > - return valid_vm_1_10_32[vm & 0xf]; > - } else { > - return valid_vm_1_10_64[vm & 0xf]; > - } > + RISCVCPU *cpu = RISCV_CPU(env_cpu(env)); > + > + return ((vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map)); > } > > static RISCVException write_mstatus(CPURISCVState *env, int csrno, > -- > 2.37.2 > Thanks, drew From MAILER-DAEMON Mon Jan 23 05:12:38 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJtoc-0002tj-QV for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 05:12:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJtoX-0002t8-Mh for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 05:12:35 -0500 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJtoW-0007Bt-6e for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 05:12:33 -0500 Received: by mail-ej1-x632.google.com with SMTP id qx13so28980920ejb.13 for ; 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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id 21-20020a170906319500b0086faa5b06d4sm11843926ejy.181.2023.01.23.02.12.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 02:12:30 -0800 (PST) Date: Mon, 23 Jan 2023 11:12:29 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: Re: [PATCH v6 4/5] riscv: Correctly set the device-tree entry 'mmu-type' Message-ID: <20230123101229.okef2kaqubwvybfh@orel> References: <20230123090324.732681-1-alexghiti@rivosinc.com> <20230123090324.732681-5-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230123090324.732681-5-alexghiti@rivosinc.com> Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=ajones@ventanamicro.com; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 10:12:35 -0000 On Mon, Jan 23, 2023 at 10:03:23AM +0100, Alexandre Ghiti wrote: > The 'mmu-type' should reflect what the hardware is capable of so use the > new satp_mode field in RISCVCPUConfig to do that. > > Signed-off-by: Alexandre Ghiti > --- > hw/riscv/virt.c | 19 ++++++++++--------- > 1 file changed, 10 insertions(+), 9 deletions(-) Reviewed-by: Andrew Jones From MAILER-DAEMON Mon Jan 23 05:14:46 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJtqf-0003nJ-56 for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 05:14:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJtqY-0003mK-Nm for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 05:14:39 -0500 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJtqU-0007XO-9r for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 05:14:37 -0500 Received: by mail-ed1-x52b.google.com with SMTP id y19so13964627edc.2 for ; Mon, 23 Jan 2023 02:14:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=AVFBKQZNyUoBTGsEwYpP77CZQH4iE/9OohcF2Hi3Hu0=; b=nFXAPqS0Z1SStpmN6xTsiZn3GJ0Lks2zl3C2EnYcRd9y4AIS05u32WvlI4pAIRhyn9 C1886DRGCglmdtV612xA5sJU+++8VtkveIZkBO08c+gJD7ocmCIlp4fXluWXdRIgGWJc MLMXOsc7l7C8vqpc8FHYAvLTw+bdHzoACF3tAtkch2R+lmgignJcYFgl+jSlYWXkmXET L0Vy4F5xZ8LhwzDYC5S/RmH3szJsJOp1Bhjc1EY/m+Z4VMqwWFrSm2mqBD0fEEfhMsGL pjL5v3+f/RPecfFIAf42WbBMqw6feU7zdrWgv8JDEma4dDpBEt2FK82WHo7DZWY770SH lZuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=AVFBKQZNyUoBTGsEwYpP77CZQH4iE/9OohcF2Hi3Hu0=; b=YNeg6sjpWIDwpb7dWH5hH2kcqslGCLjqy933q/6pcSIqRYZ/to6fkXewOlRCaTOBOQ Dyyrv0J24JRtL6n3m+KMOlzIxXZeCKG1Ty8YP5/svk0Z4HzuzNeG5K/ili0QqAuQ/KUX SaSzvj4tr3/YhU5g2YzeLU0VVQEQyip0MI6AkkC0UCfa7MlBL1wyB3X5nGrx3xwfuyM/ 3jmiDF5mUyUHGPBSc7RBmAyTAqJjtvwwyP/sHsUoigcjiBtjCXdTMeRLMTyeNkSNcV/8 2JCDiaReHAv1BwXEIHv02pKrU+EpZpjs5R73jieR1oSQyF14x7Du2p5Ky9Q4HFmNuXFi NAUQ== X-Gm-Message-State: AFqh2kpPKUh/D5wUvIzhe/VeePF0vgHzdTq7G759TXRVjb5QVoi+r4o0 GfmmfOwSbsx1sj3jl1tdkD2/pQ== X-Google-Smtp-Source: AMrXdXsIDPrcvL3hCUVVHe4C6TfaLDz3s3OnVQokxY/2Mw+PdqzgZDmdNRsKbrGaAaDPM0v5AN1veQ== X-Received: by 2002:a50:fa94:0:b0:493:597e:2193 with SMTP id w20-20020a50fa94000000b00493597e2193mr25646246edr.37.1674468871218; Mon, 23 Jan 2023 02:14:31 -0800 (PST) Received: from localhost (cst2-173-16.cust.vodafone.cz. [31.30.173.16]) by smtp.gmail.com with ESMTPSA id f3-20020aa7d843000000b0049ef04ad502sm4295237eds.40.2023.01.23.02.14.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 02:14:30 -0800 (PST) Date: Mon, 23 Jan 2023 11:14:29 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Subject: Re: [PATCH v6 3/5] riscv: Allow user to set the satp mode Message-ID: <20230123101429.a3x6vlatbvbp7kox@orel> References: <20230123090324.732681-1-alexghiti@rivosinc.com> <20230123090324.732681-4-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230123090324.732681-4-alexghiti@rivosinc.com> Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=ajones@ventanamicro.com; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 10:14:40 -0000 On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote: > RISC-V specifies multiple sizes for addressable memory and Linux probes for > the machine's support at startup via the satp CSR register (done in > csr.c:validate_vm). > > As per the specification, sv64 must support sv57, which in turn must > support sv48...etc. So we can restrict machine support by simply setting the > "highest" supported mode and the bare mode is always supported. > > You can set the satp mode using the new properties "sv32", "sv39", "sv48", > "sv57" and "sv64" as follows: > -cpu rv64,sv57=on # Linux will boot using sv57 scheme > -cpu rv64,sv39=on # Linux will boot using sv39 scheme > -cpu rv64,sv57=off # Linux will boot using sv48 scheme > -cpu rv64 # Linux will boot using sv57 scheme by default > > We take the highest level set by the user: > -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme > > We make sure that invalid configurations are rejected: > -cpu rv64,sv32=on # Can't enable 32-bit satp mode in 64-bit > -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are > # enabled > > We accept "redundant" configurations: > -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme > > And contradictory configurations: > -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme > > In addition, we now correctly set the device-tree entry 'mmu-type' using > those new properties. This sentence no longer applies to this patch. Thanks, drew From MAILER-DAEMON Mon Jan 23 05:20:03 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJtvn-0006KL-CT for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 05:20:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJtvk-0006Hz-9p for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 05:20:02 -0500 Received: from mail-oo1-xc2d.google.com ([2607:f8b0:4864:20::c2d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJtvi-0008Ls-Kj for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 05:20:00 -0500 Received: by mail-oo1-xc2d.google.com with SMTP id u13-20020a4aa34d000000b004f5219f9424so2033045ool.5 for ; Mon, 23 Jan 2023 02:19:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=3cqjTjRrNXVcRyacZlC+0sgKMvwpwq01NpDqAzLPsHA=; b=KF9XgTm4Ky7kV6wjenflewrzevdYU5UJNOtHoYIr4E2o1dkeeqMXqrCjqGyXh3DCJV 1nybxQPkiEGgfwIJD7NNsa0GHLXL1OB+S4y2ZSVs/Ap5HELlGL47Du9/MeNiX4ZRqyb+ GxFTHoYv4GMBUDY3uj1zya/c53bmGalvmuhY0a13dh3wNX6tssggy3RaGaBtx1+1jrtO wl01CrO9X2fvHrgAZnVA3wDt6VQNh9U8Kd0rX7HyBhbO2PKiYVSB37vROFniYkPgXwqR B+pMjlyQ13xZBs5mto/YrLzjwnOyec8CDlnFNRYY1TxLh+yHj2lOIovdsvqd7yNFpg8c /mwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=3cqjTjRrNXVcRyacZlC+0sgKMvwpwq01NpDqAzLPsHA=; b=cAnuFpw1nlh2/LElnGPifX7R/kTDTwf78PgZiUQxWj0eH9sibiAQuKlkHfLuNAVmRW fERXxwzgtv/Yo8V6a9JgsJh+o/EKNDB9sG3bbMtwxqASDtWfT1bBU0EfmgpWpu39TsCA b2dhkx4ztV/m8b4oHjgVP3mT6CiZemAozJCfxVqAAdlVMRjC16h2ani/WyaNwXIXRKwr DHyd0pGvvPZKmEniPvhaLTlbrkX+LHyLw2e+BHlbGw/ASAYgxALHM/hPR//OlBxnlI3y fRUGcM6VL3oj0A5DQEOI6Yhb8iDKq2tKlWCJfxo4c4Eee+Gu87LpZLstTtveSwNB6uCw ci1A== X-Gm-Message-State: AFqh2krOG1TwEavRKIBCYn+TJVNFU51ELXhisMgKt3BAX7TmCZ+S2sev 1PR1FY53EA5J2emXeXD8gAzJMA== X-Google-Smtp-Source: AMrXdXvsmRNRqy4J19ztiYSTCE9CtIwRUNLt1q/GfrtMPSZslOhYTGBIusDH05oloC0t0NdMyPYlOw== X-Received: by 2002:a4a:acc4:0:b0:4f2:a1c1:4dfc with SMTP id c4-20020a4aacc4000000b004f2a1c14dfcmr10863397oon.6.1674469196573; Mon, 23 Jan 2023 02:19:56 -0800 (PST) Received: from [192.168.68.107] ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id x6-20020a4aaa06000000b004f11e1ce173sm22785260oom.5.2023.01.23.02.19.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 Jan 2023 02:19:56 -0800 (PST) Message-ID: <14efb6ee-4de0-ce26-569b-3a7ec6647e7d@ventanamicro.com> Date: Mon, 23 Jan 2023 07:19:52 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH v3 3/7] hw/riscv/microchip_pfsoc.c: add an Icicle Kit fdt address function To: Alistair Francis Cc: Conor Dooley , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com References: <20230119191728.622081-1-dbarboza@ventanamicro.com> <20230119191728.622081-4-dbarboza@ventanamicro.com> <385b977b-d15f-6c54-1d05-ab68e122dfe8@ventanamicro.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::c2d; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2d.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.149, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 10:20:02 -0000 On 1/22/23 19:53, Alistair Francis wrote: > On Sun, Jan 22, 2023 at 5:16 AM Daniel Henrique Barboza > wrote: >> >> Conor, >> >> Thanks for the Icicle-kit walk-through! I'll not claim that I fully understood it, >> but I understood enough to handle the situation ATM. >> >> Without this change, this is where the FDT is being installed in the board when >> I start it with 8Gb of RAM (retrieved via 'info roms'): >> >> addr=00000000bfe00000 size=0x00a720 mem=ram name="fdt" >> >> Which surprised me at first because this is almost at the end of the LO area which has >> 1Gb and I figured it would be in the middle of another RAM area. I took another read >> at what we're doing in riscv_load_fdt(): >> >> ----------- >> temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; >> fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); >> ----------- >> >> This code can be read as "if the starting address of the RAM is lower than 3Gb, put >> the FDT no further than 3Gb (0xc0000000). Otherwise, put it at the end of dram", >> where "dram_base" is the starting address of the RAM block that the function >> receives. >> >> For icicle-kit, this is being passed as memmap[MICROCHIP_PFSOC_DRAM_LO].base, >> 0x80000000, which is 2Gb. >> >> So, regardless of how much RAM we have (dram_end), the FDT will always be capped at >> 3Gb. At this moment, this fits exactly at the end of the LO area for the Icicle Kit. >> Which is funny because this 3Gb restriction was added by commit 1a475d39ef54 to fix >> 32 bit guest boot and it happened to also work for the Microchip SoC. >> >> So yeah, I thought that I was fixing a bug and in the end I caused one. This patch >> needs to go. >> >> >> Alistair, I believe I should re-send v2, this time explaining why the existing function >> will not break the Microchip board because we'll never put the FDT out of the LO area >> of the board. Does this work for you? > > I think that's fine. My only worry is that we are losing some > flexibility that some future board might want. What if we change riscv_load_fdt() parameters to pass a MemoryRegion/MemMapEntry instead of just dram_base? Instead of this: uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) We would have this: uint64_t riscv_load_fdt(MemMapEntry mem, uint64_t mem_size, void *fdt) Or even this: uint64_t riscv_load_fdt(hwaddr dram_base, hwaddr dram_size, uint64_t mem_size, void *fdt) And then we can make assumptions based on the actual memory region that the fdt is going to fit into, instead of having a starting address and a total memory size and have to deal with issues such as sparse memory. We can keep all the assumptions already made today (e.g. the 3Gb maximum addr) while also having a guarantee that the fdt isn't going to be put in the wrong memory region/spot if we decide to change the assumptions later on. Thanks, Daniel > > Alistair From MAILER-DAEMON Mon Jan 23 05:25:07 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJu0f-0007VR-KA for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 05:25:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJu0e-0007V5-8U for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 05:25:04 -0500 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJu0c-0000kR-Fy for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 05:25:03 -0500 Received: by mail-oi1-x243.google.com with SMTP id d188so9938214oia.3 for ; Mon, 23 Jan 2023 02:25:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=rgdj8fTeRua4k7SIhwr99XATVMtPD7r3q1liZ2lLMpw=; b=UFtwbk3jOsQy6erve0jY7+gOcu119i0eXbDW14ABYjNhnkiqfqwpRRNuV683WgFjL7 KLBjhuT0uSyQukUXNejdTGsehIygKETKeaKBJ7ki8cYZfXP1lgdC4wYkVAzFx1KacjHI uH2o8WDWCIXyKQzb8UmI0NbiLXe+cWj0ZrjjQ4ep/A/JjWQJrxsUJc9yffqLXm4S2CjT kLcvD3c7J8g9kA2jOSvKS2QIxgGX3WWvcDYbjfoQVCtfIzjWEs27oSjaVoKcFr/ee0br BdHE6MTxmp1XPAZTSben6y4D5gLVsk/Hv4IfO55w4gw+z7pMZk4rZllNWW0TFtn7OrVI WcZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=rgdj8fTeRua4k7SIhwr99XATVMtPD7r3q1liZ2lLMpw=; b=G9skmjyzVDoiBHo88FqS3wUKWd/5FEwbdKaSoU7T04hLZFQEDZxsutemdAIRM8+kSZ fAUNLowcSVA9QdZ+xN+P6yFvoQlcqya/jEFtNawil6lJAajA/ijz0ZSrr8UYn30Z8rLC tl1cm4cfOzylXbotPOjIjPHdWJ1xCqsCSwmP7ovYp4ZUJoy0lc5LyLl7KPPdK3Eo8/IG KQg+r0JFGW312md7B3rtWhPHI/vGehaplUSErGNIj7jcu9yJOn7ySgU0vYEV3JVitl41 PQe/AuNYwQK9EWjcdsQzo/6jLyx8Fkrg5YruYUJNz9k1+VOuaNu2/hvxE2GBkdPpJdT8 YxZw== X-Gm-Message-State: AFqh2kriC9BtR8hA776lTo/KXTPAUaGFsT01LfaBErtxB/MuC2VSwF0l 4J+R+lpSqCriNHIPIHmq8Enryw== X-Google-Smtp-Source: AMrXdXvzKXZ4WzRNWRgXIqW4fNhGqGR84SmcOhi6fcukUoiw/xx6IVwh1nN4H2Pwl0bCmwm75vpqwg== X-Received: by 2002:aca:5b02:0:b0:35a:54df:638b with SMTP id p2-20020aca5b02000000b0035a54df638bmr9904897oib.4.1674469501028; Mon, 23 Jan 2023 02:25:01 -0800 (PST) Received: from [192.168.68.107] ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id du23-20020a056808629700b0036acbbf9fbasm8206437oib.46.2023.01.23.02.24.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 Jan 2023 02:25:00 -0800 (PST) Message-ID: <084f9a13-c74f-fa5e-19a7-e6b437f34cce@ventanamicro.com> Date: Mon, 23 Jan 2023 07:24:57 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH] hw/riscv: boot: Don't use CSRs if they are disabled Content-Language: en-US To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, Bin Meng , alistair23@gmail.com, bmeng.cn@gmail.com References: <20230123035754.75553-1-alistair.francis@opensource.wdc.com> From: Daniel Henrique Barboza In-Reply-To: <20230123035754.75553-1-alistair.francis@opensource.wdc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::243; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x243.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.149, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 10:25:04 -0000 On 1/23/23 00:57, Alistair Francis wrote: > From: Alistair Francis > > If the CSRs and CSR instructions are disabled because the Zicsr > extension isn't enabled then we want to make sure we don't run any CSR > instructions in the boot ROM. > > This patches removes the CSR instructions from the reset-vec if the > extension isn't enabled. We replace the instruction with a NOP instead. > > Note that we don't do this for the SiFive U machine, as we are modelling > the hardware in that case. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1447 > Signed-off-by: Alistair Francis > --- Shouldn't we also handle the sifive_u/sifive_e boards? Their reset vectors aren't being covered by riscv_set_rom_reset_vec() (it's on my TODO, didn't send it yet because sifive uses an extra MSEL pin at the start of the vector). Daniel > hw/riscv/boot.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 2594276223..cb27798a25 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -356,6 +356,15 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts > reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ > } > > + if (!harts->harts[0].cfg.ext_icsr) { > + /* > + * The Zicsr extension has been disabled, so let's ensure we don't > + * run the CSR instruction. Let's fill the address with a non > + * compressed nop. > + */ > + reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */ > + } > + > /* copy in the reset vector in little_endian byte order */ > for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { > reset_vec[i] = cpu_to_le32(reset_vec[i]); From MAILER-DAEMON Mon Jan 23 05:29:21 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJu4n-0000sT-CL for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 05:29:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJu4m-0000sC-6V for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 05:29:20 -0500 Received: from mail-ej1-x629.google.com ([2a00:1450:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJu4j-0001MM-GJ for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 05:29:19 -0500 Received: by mail-ej1-x629.google.com with SMTP id v6so29200225ejg.6 for ; Mon, 23 Jan 2023 02:29:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=b0oXK1SdRy74tLtiMX3fYKJ2HnHYK6rsSmwH4fzUscU=; b=ahfiun4Tijo6PquHjRJjf6KlQrrIdB8XKm69mCw5oJvxKuzeGShObomjrnu4KngRlw 8pVznH9uGVp+xab01oRTOiVBN0voMbxJ31Pt1IeZ6aPaW30FqUcMnHbW97DEpJfrgh5C g5Xpe3307g0ExkRIRPsSDAinCbne9l5xew/GkCPy4fHeBLD2gkM5siOfWFTQdQvcqkz2 qnt7VsWbqpiYCk/xLPLk0KXIHvUoSLbJZP5KVphH8AY97U+p8C3wY5waAc6olyvMPNcp Kv+F3CmfnOjfYpIxgZeAEFAmYub3zmsN6P2jAXT5xUs+F9fQqgqmdqWrqGJQcCopp3DY e8IQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=b0oXK1SdRy74tLtiMX3fYKJ2HnHYK6rsSmwH4fzUscU=; b=73VDsjmAGYK+QXLyNpwXC/s/aL3OlH81GsVbcMRpr2kecBIdPpjwYGdYJD+Vu6CY6p kavvyeH6mfB0MGwBG5ObktylUtKX1vtOWnMYzMlX1R4ElndJ85Tfoz1TphkP6qn+t307 VO4rKoUf4rpdYebL7TnW6rEF/tkiWHq25U1nuhoIV1YsQ3QyNcyiiNIqVnooO4G9iE6e /8kgjL8wWxCFJeFD6hA/EzAfOIhduSRnNzeIr4cH84V/CAkXQC706AHfU+9nRfbdDTwe 4JUJEy6/vz/RVIlawkpDaJoBBWmCxMykyEWr/VWU7q0u+hAfUWhtmErZ0WCprf5IQfsO 4Hsw== X-Gm-Message-State: AFqh2kqk2MobaiWtQKolP0kR9hSTqBWSr5xgbXTnQydXjaNQi1iFAOTG BQY0LBeYTMf3MtPBKNChm9kZMg== X-Google-Smtp-Source: AMrXdXsJVlJ6kY47pB1tE2A7cm4P8SwWyJPuWSvJnu8u4XKLHbAvyMOxrg6Yy8ofddTFs4JqqGS2Aw== X-Received: by 2002:a17:907:2a07:b0:86f:4a4e:4853 with SMTP id fd7-20020a1709072a0700b0086f4a4e4853mr22048541ejc.49.1674469754206; Mon, 23 Jan 2023 02:29:14 -0800 (PST) Received: from localhost (cst2-173-16.cust.vodafone.cz. [31.30.173.16]) by smtp.gmail.com with ESMTPSA id ti3-20020a170907c20300b0087190b46ab0sm10616325ejc.76.2023.01.23.02.29.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 02:29:13 -0800 (PST) Date: Mon, 23 Jan 2023 11:29:12 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Subject: Re: [PATCH v6 3/5] riscv: Allow user to set the satp mode Message-ID: <20230123102912.kq5c47nzeg7ufkma@orel> References: <20230123090324.732681-1-alexghiti@rivosinc.com> <20230123090324.732681-4-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230123090324.732681-4-alexghiti@rivosinc.com> Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=ajones@ventanamicro.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 10:29:20 -0000 On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote: ... > +/* Sets the satp mode to the max supported */ > +static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit) > +{ nit: When passing in the cpu object pointer there's no need to also pass is_32_bit, we can just use it from the pointer, cpu->env.misa_mxl == MXL_RV32 Thanks, drew From MAILER-DAEMON Mon Jan 23 05:51:23 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJuQ6-0006hw-3Q for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 05:51:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJuQ2-0006ha-2p for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 05:51:19 -0500 Received: from mail-ed1-x52e.google.com ([2a00:1450:4864:20::52e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJuPz-0005G8-KW for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 05:51:17 -0500 Received: by mail-ed1-x52e.google.com with SMTP id y19so14072162edc.2 for ; Mon, 23 Jan 2023 02:51:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=miSzRVihC966WmBKDzYaDj+suthG1DiOvuoQ8KvQmwY=; b=X4/LDyEUNDhvkVho+MySA0RPrClLon30CLeVTmIe6be7WOiFeG8Nw7hJVRwx9WZQTY z0I7ANe6S1QWy73IlHdaFfTJ1dVywhcjNrUXEvuB7Gj7CAWjJueQfsstAfI7cB+ehf8e yLX6xFU0Sr/SeGX294OJ3UDWsySPV10thU2BqciWKXaIGmmZTGszPAaWyXLMxY5lbC5k BKy5d0hbnhWzLS5abfaqCYZQMkAadCymnFH3M1iPysgmQY/T967vF9uIQ6pEdauu+wYF MVI8D3rvGs+0niapZTYc9F7wQU7GXoEofSV3Ya5PDyw7OM8vvuMfx2IwEemyC+Pw4Zx4 3qHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=miSzRVihC966WmBKDzYaDj+suthG1DiOvuoQ8KvQmwY=; b=1S3sNpYUkrqAkVOTG7O+pq8yljJ35/Aeyluss2NV56i6hRnzUCP/ZyTSq4D2XDozBn k3su6ac7o2GSKSb/FtTeulgExliSUAKhQU6UzciGN0iemYx+K0/5qBbLENw4CYs4p0wJ nz6FU/KuO4Gt1et/ScA/LMSiJL//8s3iHn21iY4kK772xWtU87u6edoSbHUo+G8XDs/o SxGPWL0onb6h/uzd+XRIKWPsCnEHGkPIrLp6OVROMTVGcmkSNjURQaePn/5rSa/8Dh2q nKNxCRpKA4gtAJjRjIUmF6pso3hDn6kV1qy0jkJAjKXN41gCeilVw+2mhCOINU2YOQqN DHnA== X-Gm-Message-State: AFqh2ko3TO807fx5B4wSCHITwvHMDUCj4/s32XgQE2Ku3eExB2FEySwu 5rAGt7U2OAa/AEJHUWOZ+nTsQg== X-Google-Smtp-Source: AMrXdXvXULPuOZ9+/WhCEd/NURJSFRmBDg5ypj6ZY5rAasW7wvoDoVAoN2lrgPdvQ1dkNGJn7HV04Q== X-Received: by 2002:a05:6402:27d3:b0:499:b3db:6aa3 with SMTP id c19-20020a05640227d300b00499b3db6aa3mr31394664ede.1.1674471073772; Mon, 23 Jan 2023 02:51:13 -0800 (PST) Received: from localhost (cst2-173-16.cust.vodafone.cz. [31.30.173.16]) by smtp.gmail.com with ESMTPSA id h29-20020a50cddd000000b0049ea1214087sm4076981edj.73.2023.01.23.02.51.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 02:51:13 -0800 (PST) Date: Mon, 23 Jan 2023 11:51:12 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities Message-ID: <20230123105112.zidabgiswkpnzo5r@orel> References: <20230123090324.732681-1-alexghiti@rivosinc.com> <20230123090324.732681-6-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230123090324.732681-6-alexghiti@rivosinc.com> Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=ajones@ventanamicro.com; helo=mail-ed1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 10:51:20 -0000 On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote: > Currently, the max satp mode is set with the only constraint that it must be > implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. > > But we actually need to add another level of constraint: what the hw is > actually capable of, because currently, a linux booting on a sifive-u54 > boots in sv57 mode which is incompatible with the cpu's sv39 max > capability. > > So add a new bitmap to RISCVSATPMap which contains this capability and > initialize it in every XXX_cpu_init. > > Finally, we have the following chain of constraints: > > Qemu capability > HW capability > User choice > Software capability ^ What software is this? I'd think the user's choice would always be last. > > Signed-off-by: Alexandre Ghiti > --- > target/riscv/cpu.c | 78 +++++++++++++++++++++++++++++++--------------- > target/riscv/cpu.h | 8 +++-- > 2 files changed, 59 insertions(+), 27 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index e409e6ab64..19a37fee2b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -292,24 +292,39 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > g_assert_not_reached(); > } > > -/* Sets the satp mode to the max supported */ > -static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit) > +static void set_satp_mode_max_supported(RISCVCPU *cpu, > + const char *satp_mode_str, > + bool is_32_bit) > { > - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > - cpu->cfg.satp_mode.map |= > - (1 << satp_mode_from_str(is_32_bit ? "sv32" : "sv57")); > - } else { > - cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > + uint8_t satp_mode = satp_mode_from_str(satp_mode_str); > + const bool *valid_vm = is_32_bit ? valid_vm_1_10_32 : valid_vm_1_10_64; > + > + for (int i = 0; i <= satp_mode; ++i) { > + if (valid_vm[i]) { > + cpu->cfg.satp_mode.supported |= (1 << i); I don't think we need a new 'supported' bitmap, I think each board that needs to further constrain va-bits from what QEMU supports should just set valid_vm_1_10_32/64. I.e. drop const from the arrays and add an init function something like #define QEMU_SATP_MODE_MAX VM_1_10_SV64 void riscv_cpu_set_satp_mode_max(RISCVCPU *cpu, uint8_t satp_mode_max) { bool is_32_bit = cpu->env.misa_mxl == MXL_RV32; bool *valid_vm = is_32_bit ? valid_vm_1_10_32 : valid_vm_1_10_64; g_assert(satp_mode_max <= QEMU_SATP_MODE_MAX); g_assert(!is_32_bit || satp_mode_max < 2); memset(valid_vm, 0, sizeof(*valid_vm)); for (int i = 0; i <= satp_mode_max; i++) { valid_vm[i] = true; } } The valid_vm[] checks already in finalize should then manage the validation needed to constrain boards. Only boards that care about this need to call this function, otherwise they'll get the default. Also, this patch should come before the patch that changes the default for all boards to sv57 in order to avoid breaking bisection. Thanks, drew From MAILER-DAEMON Mon Jan 23 06:15:29 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJunP-0006UR-Pv for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 06:15:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJunM-0006SK-2o for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 06:15:25 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJunJ-0000eB-Si for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 06:15:23 -0500 Received: by mail-wr1-x42f.google.com with SMTP id bk16so10418326wrb.11 for ; Mon, 23 Jan 2023 03:15:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=I4iyZij1GOgkgv+ODM4VNeORqp8b+qBDsCSiugb6yB0=; b=IAS5ye4RabLcbLlnu1oaQ+h9Kfm9uxcrBXk2h9+DweOcB3stiyzQsvO6PvVxne0BqX lFEVxeLav4kCf98wC6hUzH22jPgSmLb+DCzIQTXjbYSUxEbT6Z+BQJTiwvLWH2R3oW0J 5OPNqC9iF3jKy1emlrM+moW4NOiix7DRppMg+ILQ3btSnKXXKIzAZAzO9jGvO1YZL8MC MDp5OB+5z01PQf69K1B7nK/cuesC1AGSTJXn/JuEUSb35IllJkKcHZ2h/cA4l07dTWbF qimOhDCVK/TNAKg8LfBvrALpUoHVp528vErxhswA3Vi1grYg72AfSYMTZDTy9ajvtLmg 262g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=I4iyZij1GOgkgv+ODM4VNeORqp8b+qBDsCSiugb6yB0=; b=njLT0VQhVuP+e0wkAygw1E2Fa2jUWy4v6OsSU1POldqZVFDaEffS2cNAKFkQVGYROh lY9dKtEi4Q5ezcw9498ai6Fo2Oir8NMAz/XunX7Sa4Y0k4sql4LmKEzHqjwOxSVs8G8K 3yh8r7Dto7PIVLJOGRrNu+mbc+46n10XpMTGRfJVIaOivy737yEpue3k/R3qpg3op62F V+sdLdcGzrnfPyARKylqpdDTJs6eajKAGALYX3sFDywDEHr8Lrf5WLYvdJT+SHjIGpY/ zq1qXw/2lDT6/mmOFFDvZg4WaY4hc4+S7IPOM2v/FNl1YC58PPfebroLKFHMczXWvhm8 z+Gg== X-Gm-Message-State: AFqh2kpx+DR5lhO6nfNct/Q0FjSRw8926clo3JFCecNIGAVNL+FnHVvH +5ZKW8oGPeyYAM4qLucLIuHZvemb2YWsG3jSno44ig== X-Google-Smtp-Source: AMrXdXuAxty8SYB9+X0IEXIu2ZtUdFqJWlLycRWIGphwVqP+xm7UiqT6w8GeSlXJIkkCpRKzt8rLFh9wQpSq70KgdbY= X-Received: by 2002:a5d:5190:0:b0:2bd:d6bc:e35c with SMTP id k16-20020a5d5190000000b002bdd6bce35cmr1056204wrv.144.1674472519667; Mon, 23 Jan 2023 03:15:19 -0800 (PST) MIME-Version: 1.0 References: <20230123090324.732681-1-alexghiti@rivosinc.com> <20230123090324.732681-6-alexghiti@rivosinc.com> <20230123105112.zidabgiswkpnzo5r@orel> In-Reply-To: <20230123105112.zidabgiswkpnzo5r@orel> From: Alexandre Ghiti Date: Mon, 23 Jan 2023 12:15:08 +0100 Message-ID: Subject: Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities To: Andrew Jones Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 11:15:25 -0000 On Mon, Jan 23, 2023 at 11:51 AM Andrew Jones wrote: > > On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote: > > Currently, the max satp mode is set with the only constraint that it must be > > implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. > > > > But we actually need to add another level of constraint: what the hw is > > actually capable of, because currently, a linux booting on a sifive-u54 > > boots in sv57 mode which is incompatible with the cpu's sv39 max > > capability. > > > > So add a new bitmap to RISCVSATPMap which contains this capability and > > initialize it in every XXX_cpu_init. > > > > Finally, we have the following chain of constraints: > > > > Qemu capability > HW capability > User choice > Software capability > > ^ What software is this? > I'd think the user's choice would always be last. > > > > > Signed-off-by: Alexandre Ghiti > > --- > > target/riscv/cpu.c | 78 +++++++++++++++++++++++++++++++--------------- > > target/riscv/cpu.h | 8 +++-- > > 2 files changed, 59 insertions(+), 27 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index e409e6ab64..19a37fee2b 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -292,24 +292,39 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > > g_assert_not_reached(); > > } > > > > -/* Sets the satp mode to the max supported */ > > -static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit) > > +static void set_satp_mode_max_supported(RISCVCPU *cpu, > > + const char *satp_mode_str, > > + bool is_32_bit) > > { > > - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > > - cpu->cfg.satp_mode.map |= > > - (1 << satp_mode_from_str(is_32_bit ? "sv32" : "sv57")); > > - } else { > > - cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > > + uint8_t satp_mode = satp_mode_from_str(satp_mode_str); > > + const bool *valid_vm = is_32_bit ? valid_vm_1_10_32 : valid_vm_1_10_64; > > + > > + for (int i = 0; i <= satp_mode; ++i) { > > + if (valid_vm[i]) { > > + cpu->cfg.satp_mode.supported |= (1 << i); > > I don't think we need a new 'supported' bitmap, I think each board that > needs to further constrain va-bits from what QEMU supports should just set > valid_vm_1_10_32/64. I.e. drop const from the arrays and add an init > function something like This was my first idea too, but those arrays are global and I have to admit that I thought it was possible to emulate a cpu with different cores. Anyway, isn't it a bit weird to store this into some global array whereas it is intimately linked to the CPU? To me, it makes sense to keep those variables as a way to know what qemu is able to emulate and have a CPU specific map like in this patch for the hw capabilities. Does it make sense to you? > > #define QEMU_SATP_MODE_MAX VM_1_10_SV64 > > void riscv_cpu_set_satp_mode_max(RISCVCPU *cpu, uint8_t satp_mode_max) > { > bool is_32_bit = cpu->env.misa_mxl == MXL_RV32; > bool *valid_vm = is_32_bit ? valid_vm_1_10_32 : valid_vm_1_10_64; > > g_assert(satp_mode_max <= QEMU_SATP_MODE_MAX); > g_assert(!is_32_bit || satp_mode_max < 2); > > memset(valid_vm, 0, sizeof(*valid_vm)); > > for (int i = 0; i <= satp_mode_max; i++) { > valid_vm[i] = true; > } > } > > The valid_vm[] checks already in finalize should then manage the > validation needed to constrain boards. Only boards that care about > this need to call this function, otherwise they'll get the default. > > Also, this patch should come before the patch that changes the default > for all boards to sv57 in order to avoid breaking bisection. As I explained earlier, I didn't change the default to sv57! Just fixed what was passed via the device tree, which should not be used anyway :) Alex > > Thanks, > drew From MAILER-DAEMON Mon Jan 23 06:49:42 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJvKY-00058H-Jr for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 06:49:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJvKW-00057k-Ev; Mon, 23 Jan 2023 06:49:40 -0500 Received: from mail-vk1-xa34.google.com ([2607:f8b0:4864:20::a34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJvKU-0006UT-Px; Mon, 23 Jan 2023 06:49:40 -0500 Received: by mail-vk1-xa34.google.com with SMTP id b81so5803403vkf.1; Mon, 23 Jan 2023 03:49:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=fe3wQWfTwAwJBdmmp+ksAlwmOP05eh7YvVMspuYv9SU=; b=WD6hp6ZGeyxDd+b55aCySRjVrV++x6XVzUhe9IpgpsjL5l93ymW1bEW22sLiMMlFSc TifVsjrh/I9TKo5oZgx0q742YTKdTVHXFQ0Hhx8gZ+4FgzGu/cPfuwk+SECey+H6Mrn0 Mh+Kr5lqtc83v57NdhCNaQy2c4gDf4Wbnybk1lTNuerAIEMOf1vIlrNHyRaOjaDcIJ5A OFzfTGSy7Z/v6tQdLn9X3CHRcb8dl/OXh6JBXQA/TOad/J3pGmgZKW09tgQu1e0iaNky kRlzuoTBgGt5tpEAxXupE70HTamiHCnvHpDcCG9mWPLehwAB0fVBv7JVnYYtfqR4UK/e 20NQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=fe3wQWfTwAwJBdmmp+ksAlwmOP05eh7YvVMspuYv9SU=; b=qgOQHl9jqsehq3jaEB/D7AT4dcmJ6SztBFb/LP7HS5MxlyCBwErxGjvmFu4E29MSkY KwBCpuEfQpJnaOPcpykwsoCzDgR3/m1YldKfbCC5JHoilBKnunpRDqNUM0fHuttf5EwL 8j98gmFD7UyF6IOeodxKTpjlNrqjrRxHvsWRqVXsDIho6AmeNaAHv8yxuo535Zv8qQYr toVC55rvXjQNfEAPdPASWkh2drelTRAS6iBsy7gZ4ufriJ2kCG5Tye0/oPiCUgJXmdVZ W3Dem16UIkH+uuZWhGddWGVnPWQpE4PfIa6kzLr7ziBUnQyhUogL4nvM5hTVFz9lyMMt IrAw== X-Gm-Message-State: AFqh2koTz5vPnJ9LkQmKNNj6C4ErwXLl3fpsm9h5Cv3dIDMFYBb8G7zZ LamYXHLgCiw0Ra3oKGo8AeUyY5vNLHcirF+kJpQ= X-Google-Smtp-Source: AMrXdXuFVhIA+WFT1MWZq/dZSa407zky4j2y4alVMDLgfhzhClAvivZHlBAwa91KOFQEPefkmkBGpWaVcbLzOM/I7UY= X-Received: by 2002:a1f:b681:0:b0:3dd:fc42:994d with SMTP id g123-20020a1fb681000000b003ddfc42994dmr3231523vkf.25.1674474577415; Mon, 23 Jan 2023 03:49:37 -0800 (PST) MIME-Version: 1.0 References: <20230119191728.622081-1-dbarboza@ventanamicro.com> <20230119191728.622081-4-dbarboza@ventanamicro.com> <385b977b-d15f-6c54-1d05-ab68e122dfe8@ventanamicro.com> <14efb6ee-4de0-ce26-569b-3a7ec6647e7d@ventanamicro.com> In-Reply-To: <14efb6ee-4de0-ce26-569b-3a7ec6647e7d@ventanamicro.com> From: Alistair Francis Date: Mon, 23 Jan 2023 21:49:11 +1000 Message-ID: Subject: Re: [PATCH v3 3/7] hw/riscv/microchip_pfsoc.c: add an Icicle Kit fdt address function To: Daniel Henrique Barboza Cc: Conor Dooley , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::a34; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa34.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 11:49:40 -0000 On Mon, Jan 23, 2023 at 8:19 PM Daniel Henrique Barboza wrote: > > > > On 1/22/23 19:53, Alistair Francis wrote: > > On Sun, Jan 22, 2023 at 5:16 AM Daniel Henrique Barboza > > wrote: > >> > >> Conor, > >> > >> Thanks for the Icicle-kit walk-through! I'll not claim that I fully understood it, > >> but I understood enough to handle the situation ATM. > >> > >> Without this change, this is where the FDT is being installed in the board when > >> I start it with 8Gb of RAM (retrieved via 'info roms'): > >> > >> addr=00000000bfe00000 size=0x00a720 mem=ram name="fdt" > >> > >> Which surprised me at first because this is almost at the end of the LO area which has > >> 1Gb and I figured it would be in the middle of another RAM area. I took another read > >> at what we're doing in riscv_load_fdt(): > >> > >> ----------- > >> temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; > >> fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); > >> ----------- > >> > >> This code can be read as "if the starting address of the RAM is lower than 3Gb, put > >> the FDT no further than 3Gb (0xc0000000). Otherwise, put it at the end of dram", > >> where "dram_base" is the starting address of the RAM block that the function > >> receives. > >> > >> For icicle-kit, this is being passed as memmap[MICROCHIP_PFSOC_DRAM_LO].base, > >> 0x80000000, which is 2Gb. > >> > >> So, regardless of how much RAM we have (dram_end), the FDT will always be capped at > >> 3Gb. At this moment, this fits exactly at the end of the LO area for the Icicle Kit. > >> Which is funny because this 3Gb restriction was added by commit 1a475d39ef54 to fix > >> 32 bit guest boot and it happened to also work for the Microchip SoC. > >> > >> So yeah, I thought that I was fixing a bug and in the end I caused one. This patch > >> needs to go. > >> > >> > >> Alistair, I believe I should re-send v2, this time explaining why the existing function > >> will not break the Microchip board because we'll never put the FDT out of the LO area > >> of the board. Does this work for you? > > > > I think that's fine. My only worry is that we are losing some > > flexibility that some future board might want. > > What if we change riscv_load_fdt() parameters to pass a MemoryRegion/MemMapEntry > instead of just dram_base? > > Instead of this: > > uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) > > We would have this: > > uint64_t riscv_load_fdt(MemMapEntry mem, uint64_t mem_size, void *fdt) > > Or even this: > > uint64_t riscv_load_fdt(hwaddr dram_base, hwaddr dram_size, > uint64_t mem_size, void *fdt) > > > And then we can make assumptions based on the actual memory region that the fdt > is going to fit into, instead of having a starting address and a total memory > size and have to deal with issues such as sparse memory. > > We can keep all the assumptions already made today (e.g. the 3Gb maximum addr) > while also having a guarantee that the fdt isn't going to be put in the wrong > memory region/spot if we decide to change the assumptions later on. That seems like a good direction. We currently don't need this though, so don't feel like it needs to be done today. Alistair > > > Thanks, > > Daniel > > > > > > > Alistair From MAILER-DAEMON Mon Jan 23 06:51:55 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJvMh-0005x8-8u for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 06:51:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJvMf-0005vY-GW; Mon, 23 Jan 2023 06:51:53 -0500 Received: from mail-vs1-xe34.google.com ([2607:f8b0:4864:20::e34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJvMd-00077U-LT; Mon, 23 Jan 2023 06:51:53 -0500 Received: by mail-vs1-xe34.google.com with SMTP id t10so12560312vsr.3; Mon, 23 Jan 2023 03:51:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=WXRZjU2/+Ku0v/DLnU6CS6vf7K9zE8FigBzKnXdHAcg=; b=grQETtIq1FnrngqPTPy5/gc41dmt1TqL2SCCZzrDvuyVSHF4DdWLWr6aBMJ4vJImz2 j65xK+IeMlEitVRKVlP2NcQWw8EsjbYFV//J0jV53os+tTYoIQ2x9Qh8TTt4qFrlan9b HW+2ybIajIUbk4RhUJEHK/vwzHbMHNCRsIhlkx1bpdAfnkdMtzv9NeMqRSqYA8/IJYYF WCt5cF1FQqOu93jmd73/XAKn93lVWKsNcXXTZ8TB1Zgw64mFR2ECuH8OZINnHkY7c79N RPuGklN60pIkUe19rh/m83FNPl/PMilnQPz7YiW1A3F570aPa6ZDgtf4+EqtsZTc3D0q MucA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=WXRZjU2/+Ku0v/DLnU6CS6vf7K9zE8FigBzKnXdHAcg=; b=S+eit5sksC+T6UCMyGOodFyUJ6f+3Hei2sXV/+QDu43z2q5Kzj83BdbC0w645Uoqxa Wb8tuP2vTyDJBCRyqj9a70Gc5nW3cpYcDcoeVHXJByAEaZZ8LC8KApF/xMUutyolHpu3 Xx6zt40Ps2+BDoDWM8GTt/Kzsq0JmVqEhnPoW3eS6fOG1pb1DunjZu2mDg010itS8ddz IKdK5Bp1ncU+R3akvhHaiQn6A2CE4DxYN8d0SMQgTQAyRI0OElx88NT+zl4x9sGpHxXg 8dNEzvbEcO6lJ+esSbXK2YDQij4g9hT92gghPP/iDOofEFY2GX0Uo2Uy9KnUANWLUxAy Hqcw== X-Gm-Message-State: AFqh2ko4bByraz5zNPqyOILff9XbiCU+Hrn/6Y2QiNOCrWVVIx/FGUIX sN2I/9QoTC1+XbJkGfT9buvoo2i1yWMDuoquQfo= X-Google-Smtp-Source: AMrXdXsGHYmmdRCIvMnxYjfrj9IoekuWTLro7RvT5UtjKe2gbtCRQEk3CQgcNWLX2U9BmIkHbnxhf40DIUFHrj1tZVY= X-Received: by 2002:a67:ba0c:0:b0:3ce:f2da:96a with SMTP id l12-20020a67ba0c000000b003cef2da096amr2769691vsn.64.1674474710082; Mon, 23 Jan 2023 03:51:50 -0800 (PST) MIME-Version: 1.0 References: <20230123035754.75553-1-alistair.francis@opensource.wdc.com> <084f9a13-c74f-fa5e-19a7-e6b437f34cce@ventanamicro.com> In-Reply-To: <084f9a13-c74f-fa5e-19a7-e6b437f34cce@ventanamicro.com> From: Alistair Francis Date: Mon, 23 Jan 2023 21:51:23 +1000 Message-ID: Subject: Re: [PATCH] hw/riscv: boot: Don't use CSRs if they are disabled To: Daniel Henrique Barboza Cc: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, Bin Meng , bmeng.cn@gmail.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e34; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe34.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 11:51:54 -0000 On Mon, Jan 23, 2023 at 8:25 PM Daniel Henrique Barboza wrote: > > > > On 1/23/23 00:57, Alistair Francis wrote: > > From: Alistair Francis > > > > If the CSRs and CSR instructions are disabled because the Zicsr > > extension isn't enabled then we want to make sure we don't run any CSR > > instructions in the boot ROM. > > > > This patches removes the CSR instructions from the reset-vec if the > > extension isn't enabled. We replace the instruction with a NOP instead. > > > > Note that we don't do this for the SiFive U machine, as we are modelling > > the hardware in that case. > > > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1447 > > Signed-off-by: Alistair Francis > > --- > > Shouldn't we also handle the sifive_u/sifive_e boards? Their reset vectors > aren't being covered by riscv_set_rom_reset_vec() (it's on my TODO, didn't > send it yet because sifive uses an extra MSEL pin at the start of the vector). I feel that those boards are modelling hardware, so in this case we should model what the hardware does. I don't even think that a user could disable the CSR extension on those boards. Alistair > > > > Daniel > > > > > hw/riscv/boot.c | 9 +++++++++ > > 1 file changed, 9 insertions(+) > > > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > > index 2594276223..cb27798a25 100644 > > --- a/hw/riscv/boot.c > > +++ b/hw/riscv/boot.c > > @@ -356,6 +356,15 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts > > reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ > > } > > > > + if (!harts->harts[0].cfg.ext_icsr) { > > + /* > > + * The Zicsr extension has been disabled, so let's ensure we don't > > + * run the CSR instruction. Let's fill the address with a non > > + * compressed nop. > > + */ > > + reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */ > > + } > > + > > /* copy in the reset vector in little_endian byte order */ > > for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { > > reset_vec[i] = cpu_to_le32(reset_vec[i]); From MAILER-DAEMON Mon Jan 23 07:03:08 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJvXY-0000KV-K9 for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 07:03:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJvXW-0000KD-Vj for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 07:03:07 -0500 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJvXU-00012x-Uj for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 07:03:06 -0500 Received: by mail-oi1-x243.google.com with SMTP id r9so10099090oig.12 for ; Mon, 23 Jan 2023 04:03:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=lRsg1eHSy6dXcK398HZhrx7k4aUwyZw1FnC/dc/O1jg=; b=aKzrHYalwWa1VbDiCChcbh261PQV1drdWnJkKh4SnAhJZ0eeQRUAUro1nWdQpCCs7E ccwJXtCeMT94KpwjW4w8DZYz0Yvl7dyQR+klqgqynsoMTQhFHmb6OB6NXnrnKV5nkEwY Iw2+xQlWY4CsUfKv/0X0pVWOO2V4CszjjzWNsRC+j8QQriuYAic+OLSB9pii+83O87No h9h2QZ+Xlr8XCz+LRu8yWObOjxCvGVzehxNQ7LPHUKKsFL70+GUExyKOPBULDvluDk10 RCvIcjNwWIUmf8yQMF0A0e2+l9iupj+O1wdZ7mwASP+s96wHEuck/iYXJk6l3NCWod04 n55g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=lRsg1eHSy6dXcK398HZhrx7k4aUwyZw1FnC/dc/O1jg=; b=0FeCX1VC4HDyM5cxNO7XG8IchWy1awXwokLvQ98Gsm0RaQ9XE1SMzEtYzN+F2CGPcY rr61DzDoxO2yxJcqD3HDPSDYmOMGzgMWuXAYxjppy5FevUskaX3XwceNiTjPNplt4y8c yjAPPA2bwXXMMY08R2hvHg9oT/fAykIASMSHqMFVi21QCXwgq2t8qoXBFEnsJyeLqJ1n L2Ubm0nOd6jGP5W4V57OJX/fDvI862smw3XdPfDUdoPteS63OIplgwRifE6Lm8qxMH7M 4eg+sX5wM4WpQl6b26M6xd9g7TpFUMYAJBd7uMgTa/key8RfQp6wAXGloMD44c37OHLx qIlA== X-Gm-Message-State: AFqh2kp+lb1XXgaWRDgd8fGsY6nsVVy2YCMRQiWwBOZdtrD8KKprrh6G tF+CEk70pAmKEH4wESZ80Eb8qg== X-Google-Smtp-Source: AMrXdXs1X7TEP3kOBrJnSohAwRGgt0phthWfbeevxj0yg0NY+51BY+HQHf1xcTMY2gxuaOktdPwC1g== X-Received: by 2002:aca:5a86:0:b0:364:e913:3a9 with SMTP id o128-20020aca5a86000000b00364e91303a9mr9945010oib.49.1674475383364; Mon, 23 Jan 2023 04:03:03 -0800 (PST) Received: from [192.168.68.107] ([191.17.222.2]) by smtp.gmail.com with ESMTPSA id s38-20020a05680820a600b0036eafb8eee9sm5326331oiw.22.2023.01.23.04.03.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 Jan 2023 04:03:02 -0800 (PST) Message-ID: <9ab1e3af-db52-4d55-03e7-263a2f7ae965@ventanamicro.com> Date: Mon, 23 Jan 2023 09:02:59 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH] hw/riscv: boot: Don't use CSRs if they are disabled Content-Language: en-US To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: palmer@dabbelt.com, alistair.francis@wdc.com, Bin Meng , alistair23@gmail.com, bmeng.cn@gmail.com References: <20230123035754.75553-1-alistair.francis@opensource.wdc.com> From: Daniel Henrique Barboza In-Reply-To: <20230123035754.75553-1-alistair.francis@opensource.wdc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::243; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x243.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.147, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 12:03:07 -0000 On 1/23/23 00:57, Alistair Francis wrote: > From: Alistair Francis > > If the CSRs and CSR instructions are disabled because the Zicsr > extension isn't enabled then we want to make sure we don't run any CSR > instructions in the boot ROM. > > This patches removes the CSR instructions from the reset-vec if the > extension isn't enabled. We replace the instruction with a NOP instead. > > Note that we don't do this for the SiFive U machine, as we are modelling > the hardware in that case. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1447 > Signed-off-by: Alistair Francis > --- Reviewed-by: Daniel Henrique Barboza > hw/riscv/boot.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 2594276223..cb27798a25 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -356,6 +356,15 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts > reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ > } > > + if (!harts->harts[0].cfg.ext_icsr) { > + /* > + * The Zicsr extension has been disabled, so let's ensure we don't > + * run the CSR instruction. Let's fill the address with a non > + * compressed nop. > + */ > + reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */ > + } > + > /* copy in the reset vector in little_endian byte order */ > for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { > reset_vec[i] = cpu_to_le32(reset_vec[i]); From MAILER-DAEMON Mon Jan 23 08:32:29 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJwvt-0001fD-W2 for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 08:32:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJwva-0001bh-7V for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 08:32:11 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJwvN-0001AU-U7 for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 08:31:55 -0500 Received: by mail-wm1-x32b.google.com with SMTP id d4-20020a05600c3ac400b003db1de2aef0so8564939wms.2 for ; Mon, 23 Jan 2023 05:31:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=mBD5y8cfI6GMwahAw4KyuJkxWK4yyvM9tjn4dxB1/vk=; b=gKnnmDA7IXowzA524+ovhlLeVCltdsaZnzPaNV+xZPY2Dv+x6Guxo+DQbmQfKTetHS 0+BahoM/KESIalrOeTLg4TYFigyGMKF/GjFuk6NQwBPsrTU4SNjiUcqxKbJQ9LNhYmlb ZqD5FqqAbGtBo6DO3AE6DyM5Bx/9Xbe/gwcXZ8CPhkBd7EK+yKzRQL4Ujrm6IcSYaaPu zw8B0RMDkr+sH3HKH+BCVKR7ykiJTTRtxHyRWDwrTg6qesBE+Lpm32Pgx0x1jNOi4f/B aKcW3IJyMW+bdXg9oZ4Di0sw1HFudTD5fdisvheelPLYFsfhdP827zAwYA95fT24M8/C eh1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=mBD5y8cfI6GMwahAw4KyuJkxWK4yyvM9tjn4dxB1/vk=; b=UV8tApDpR0Srrfxjd2HmCNEcZppjk6g/AN/qE7sdi9VpXfYI+R1MUJ/g26bp9ed7qY AccE3q+yQdpLY4JqJTLitEVqlIkcHRxQxVStVkXvo2PTmtQyxVVNGEK4zfjlkkfQozJm OpJOTsnLwyRxSEVCfCAbKBDEaDKrk5fieGqkLYsnxBZBg1Vgd9zLCfShf3V0f4LYQH1/ 4tSDLUtXMACEfRK9CFB5RsFQGZ+4rJdZWX+QF/5v2z/CDih+606VLY0ilsPDVCmk+l7k bcHGcqNpMZ8ISfVobTt2IUQazOF0yYVG4Z9LqBa+4QAvn3xCyUsd+Fyzed+ypnTQ1kik HshA== X-Gm-Message-State: AFqh2kpCJOFdLhJTAO9mHg0yPf/K7BElcrAMLePom/JkY8fdoVzeGPFn auBo9+xP8guTiGvXYdkc8FxnLw== X-Google-Smtp-Source: AMrXdXtCJQH+shuT8TM2DWLcDW3vfAmXySSIts6bimE43JL+BXwiojejXuGvVjmMtUyKFdP+LZnqtA== X-Received: by 2002:a05:600c:a4e:b0:3db:14d0:65be with SMTP id c14-20020a05600c0a4e00b003db14d065bemr19426771wmq.34.1674480688621; Mon, 23 Jan 2023 05:31:28 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id 17-20020a05600c021100b003dafb0c8dfbsm12169287wmi.14.2023.01.23.05.31.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 05:31:28 -0800 (PST) Date: Mon, 23 Jan 2023 14:31:27 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities Message-ID: <20230123133127.7dyqhdryrbp27o46@orel> References: <20230123090324.732681-1-alexghiti@rivosinc.com> <20230123090324.732681-6-alexghiti@rivosinc.com> <20230123105112.zidabgiswkpnzo5r@orel> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 13:32:15 -0000 On Mon, Jan 23, 2023 at 12:15:08PM +0100, Alexandre Ghiti wrote: > On Mon, Jan 23, 2023 at 11:51 AM Andrew Jones wrote: > > > > On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote: > > > Currently, the max satp mode is set with the only constraint that it must be > > > implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. > > > > > > But we actually need to add another level of constraint: what the hw is > > > actually capable of, because currently, a linux booting on a sifive-u54 > > > boots in sv57 mode which is incompatible with the cpu's sv39 max > > > capability. > > > > > > So add a new bitmap to RISCVSATPMap which contains this capability and > > > initialize it in every XXX_cpu_init. > > > > > > Finally, we have the following chain of constraints: > > > > > > Qemu capability > HW capability > User choice > Software capability > > > > ^ What software is this? > > I'd think the user's choice would always be last. > > > > > > > > Signed-off-by: Alexandre Ghiti > > > --- > > > target/riscv/cpu.c | 78 +++++++++++++++++++++++++++++++--------------- > > > target/riscv/cpu.h | 8 +++-- > > > 2 files changed, 59 insertions(+), 27 deletions(-) > > > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > > index e409e6ab64..19a37fee2b 100644 > > > --- a/target/riscv/cpu.c > > > +++ b/target/riscv/cpu.c > > > @@ -292,24 +292,39 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > > > g_assert_not_reached(); > > > } > > > > > > -/* Sets the satp mode to the max supported */ > > > -static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit) > > > +static void set_satp_mode_max_supported(RISCVCPU *cpu, > > > + const char *satp_mode_str, > > > + bool is_32_bit) > > > { > > > - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > > > - cpu->cfg.satp_mode.map |= > > > - (1 << satp_mode_from_str(is_32_bit ? "sv32" : "sv57")); > > > - } else { > > > - cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > > > + uint8_t satp_mode = satp_mode_from_str(satp_mode_str); > > > + const bool *valid_vm = is_32_bit ? valid_vm_1_10_32 : valid_vm_1_10_64; > > > + > > > + for (int i = 0; i <= satp_mode; ++i) { > > > + if (valid_vm[i]) { > > > + cpu->cfg.satp_mode.supported |= (1 << i); > > > > I don't think we need a new 'supported' bitmap, I think each board that > > needs to further constrain va-bits from what QEMU supports should just set > > valid_vm_1_10_32/64. I.e. drop const from the arrays and add an init > > function something like > > This was my first idea too, but those arrays are global and I have to > admit that I thought it was possible to emulate a cpu with different > cores. Anyway, isn't it a bit weird to store this into some global > array whereas it is intimately linked to the CPU? To me, it makes > sense to keep those variables as a way to know what qemu is able to > emulate and have a CPU specific map like in this patch for the hw > capabilities. Does it make sense to you? Ah, yes, to support heterogeneous configs it's best to keep this information per-cpu. I'll take another look at the patch. > > > > > #define QEMU_SATP_MODE_MAX VM_1_10_SV64 > > > > void riscv_cpu_set_satp_mode_max(RISCVCPU *cpu, uint8_t satp_mode_max) > > { > > bool is_32_bit = cpu->env.misa_mxl == MXL_RV32; > > bool *valid_vm = is_32_bit ? valid_vm_1_10_32 : valid_vm_1_10_64; > > > > g_assert(satp_mode_max <= QEMU_SATP_MODE_MAX); > > g_assert(!is_32_bit || satp_mode_max < 2); > > > > memset(valid_vm, 0, sizeof(*valid_vm)); > > > > for (int i = 0; i <= satp_mode_max; i++) { > > valid_vm[i] = true; > > } > > } > > > > The valid_vm[] checks already in finalize should then manage the > > validation needed to constrain boards. Only boards that care about > > this need to call this function, otherwise they'll get the default. > > > > Also, this patch should come before the patch that changes the default > > for all boards to sv57 in order to avoid breaking bisection. > > As I explained earlier, I didn't change the default to sv57! Just > fixed what was passed via the device tree, which should not be used > anyway :) OK, I keep misunderstanding how we're "fixing" something which is is wrong, but apparently doesn't exhibit any symptoms. So, assuming it doesn't matter, then I guess it can come anywhere in the series. Thanks, drew From MAILER-DAEMON Mon Jan 23 08:51:34 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJxEU-00073x-PB for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 08:51:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJxES-000734-N1 for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 08:51:33 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pJxEP-0006cV-FC for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 08:51:32 -0500 Received: by mail-wm1-x331.google.com with SMTP id f25-20020a1c6a19000000b003da221fbf48so8603098wmc.1 for ; Mon, 23 Jan 2023 05:51:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=pB5HH4yHacuaSXFeR4M3fVfhrIi2ZrUbS9tHIQedDyY=; b=hqEyUlwrz6/ZSup9Kg3UazdylCajo70cGs6Zdo9AJApoeQRH94vuYLmNYbHmmFzxDu rSHCnwra7K6WfuzaG8F1lt5fgRPLE9+ucCctKwZ5XsVUWGRP2ecWzugxQryklf/ZMKr9 d3MPVGhebjfRSJCJ2S3a3AXcvhOYLMbAvB+dpgzQStBS50SJ78pIuhIwwPRuXJ7PH29l z+Lvb55v0wu9pQtJCwDNZxcLlBDSlJ3PGuBMW7mBCeeJOj3lgq1pHgsT4+PLcJ2hUrOn aAjsEm2LtiBNh76Ngc3KnT1jm0J/0fRa8HqFHHOXooZTzDg4mJLl8GIkcRreXi83Rv+m ZMGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=pB5HH4yHacuaSXFeR4M3fVfhrIi2ZrUbS9tHIQedDyY=; b=s/zD18js6o0eZAh3t5RaaT7PMoaUlTYaEHQ0Ao/CEcM+VNDMsm0I3xgfn5FDGU75Ug 2P8ZNTJxFkeH2UCV/yMbLPnkBjiqWyJ1xSFlOJJB+eslKSJljjeWbs7umgZftvyjmCla PkvftoqYCcXbu+fFlqJTYuwhXKlWP1egNrw6Zhzsm3y64iLK22a3coFmitjy+RSdadVu 80Ri4mN1x26UpITmAhegBtI3Pc6whIdk5aIdkXjzSiGNGUUpCs2JVX1+aLMgyE8R4pYe 2fJm9CeXpA60NgKdfDFypnWbuucHhg0rwtY1CpnxJv2qwAh+H+nRtM8IUPWPJhp/NSMB PRWQ== X-Gm-Message-State: AFqh2kriXUvko1mESJlDS5Zk79G1aSp3/5dVwms4XfIxAZ3Dffn2Ca99 gwyQDd4s6Pj4JtB/lDbbpiXQJA== X-Google-Smtp-Source: AMrXdXtY/up1ISH8T/bWSHKAXhpqxyBBgFi7ie3BPW3YsxYaW+39tGXqkrnqRVEDhuDtk3WyZQXFsg== X-Received: by 2002:a05:600c:3ba5:b0:3cf:7925:7a3 with SMTP id n37-20020a05600c3ba500b003cf792507a3mr24301013wms.24.1674481887474; Mon, 23 Jan 2023 05:51:27 -0800 (PST) Received: from localhost (2001-1ae9-1c2-4c00-20f-c6b4-1e57-7965.ip6.tmcz.cz. [2001:1ae9:1c2:4c00:20f:c6b4:1e57:7965]) by smtp.gmail.com with ESMTPSA id q7-20020a05600c46c700b003db11dfc687sm11290922wmo.36.2023.01.23.05.51.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 23 Jan 2023 05:51:27 -0800 (PST) Date: Mon, 23 Jan 2023 14:51:26 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities Message-ID: <20230123135126.koxdvloakhwk2gcy@orel> References: <20230123090324.732681-1-alexghiti@rivosinc.com> <20230123090324.732681-6-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230123090324.732681-6-alexghiti@rivosinc.com> Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=ajones@ventanamicro.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 13:51:33 -0000 On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote: > Currently, the max satp mode is set with the only constraint that it must be > implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. > > But we actually need to add another level of constraint: what the hw is > actually capable of, because currently, a linux booting on a sifive-u54 > boots in sv57 mode which is incompatible with the cpu's sv39 max > capability. > > So add a new bitmap to RISCVSATPMap which contains this capability and > initialize it in every XXX_cpu_init. > > Finally, we have the following chain of constraints: > > Qemu capability > HW capability > User choice > Software capability > > Signed-off-by: Alexandre Ghiti > --- > target/riscv/cpu.c | 78 +++++++++++++++++++++++++++++++--------------- > target/riscv/cpu.h | 8 +++-- > 2 files changed, 59 insertions(+), 27 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index e409e6ab64..19a37fee2b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -292,24 +292,39 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > g_assert_not_reached(); > } > > -/* Sets the satp mode to the max supported */ > -static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit) > +static void set_satp_mode_max_supported(RISCVCPU *cpu, > + const char *satp_mode_str, > + bool is_32_bit) I'd drop 'is_32_bit' and get it from 'cpu', which would "clean up" all the callsites by getting rid of all the true/false stuff. Also, why take the string instead of the VM_1_10_SV* define? > { > - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > - cpu->cfg.satp_mode.map |= > - (1 << satp_mode_from_str(is_32_bit ? "sv32" : "sv57")); > - } else { > - cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > + uint8_t satp_mode = satp_mode_from_str(satp_mode_str); > + const bool *valid_vm = is_32_bit ? valid_vm_1_10_32 : valid_vm_1_10_64; > + > + for (int i = 0; i <= satp_mode; ++i) { > + if (valid_vm[i]) { > + cpu->cfg.satp_mode.supported |= (1 << i); > + } > } > } > > +/* Sets the satp mode to the max supported */ > +static void set_satp_mode_default(RISCVCPU *cpu) > +{ > + uint8_t satp_mode = satp_mode_max_from_map(cpu->cfg.satp_mode.supported); > + > + cpu->cfg.satp_mode.map |= (1 << satp_mode); Let's do 'cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported' to make sure 'map' has all supported bits set for property probing. > +} > + > static void riscv_any_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > #if defined(TARGET_RISCV32) > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > + set_satp_mode_max_supported(cpu, "sv32", true); > #elif defined(TARGET_RISCV64) > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > + set_satp_mode_max_supported(cpu, "sv57", false); > #endif > set_priv_version(env, PRIV_VERSION_1_12_0); > register_cpu_props(obj); > @@ -319,18 +334,24 @@ static void riscv_any_cpu_init(Object *obj) > static void rv64_base_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > /* We set this in the realise function */ > set_misa(env, MXL_RV64, 0); > register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > + set_satp_mode_max_supported(cpu, "sv57", false); > } > > static void rv64_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > + set_satp_mode_max_supported(cpu, "sv39", false); > } > > static void rv64_sifive_e_cpu_init(Object *obj) > @@ -341,6 +362,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > + set_satp_mode_max_supported(cpu, "mbare", false); > } > > static void rv128_base_cpu_init(Object *obj) > @@ -352,11 +374,13 @@ static void rv128_base_cpu_init(Object *obj) > exit(EXIT_FAILURE); > } > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > /* We set this in the realise function */ > set_misa(env, MXL_RV128, 0); > register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > + set_satp_mode_max_supported(cpu, "sv57", false); > } > #else > static void rv32_base_cpu_init(Object *obj) > @@ -367,13 +391,17 @@ static void rv32_base_cpu_init(Object *obj) > register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > + set_satp_mode_max_supported(cpu, "sv32", true); > } > > static void rv32_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > + set_satp_mode_max_supported(cpu, "sv32", true); > } > > static void rv32_sifive_e_cpu_init(Object *obj) > @@ -384,6 +412,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > + set_satp_mode_max_supported(cpu, "mbare", true); > } > > static void rv32_ibex_cpu_init(Object *obj) > @@ -394,6 +423,7 @@ static void rv32_ibex_cpu_init(Object *obj) > set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_11_0); > cpu->cfg.mmu = false; > + set_satp_mode_max_supported(cpu, "mbare", true); > cpu->cfg.epmp = true; > } > > @@ -405,6 +435,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > + set_satp_mode_max_supported(cpu, "mbare", true); > } > #endif > > @@ -696,7 +727,9 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > { > bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > - const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > + uint8_t satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > + uint8_t satp_mode_supported_max = > + satp_mode_max_from_map(cpu->cfg.satp_mode.supported); > > if (cpu->cfg.satp_mode.map == 0) { > /* > @@ -704,7 +737,7 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > * satp mode. > */ > if (cpu->cfg.satp_mode.init == 0) { > - set_satp_mode_default(cpu, rv32); > + set_satp_mode_default(cpu); > } else { > /* > * Find the lowest level that was disabled and then enable the > @@ -714,9 +747,9 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > for (int i = 1; i < 16; ++i) { > if (!(cpu->cfg.satp_mode.map & (1 << i)) && > (cpu->cfg.satp_mode.init & (1 << i)) && > - valid_vm[i]) { > + (cpu->cfg.satp_mode.supported & (1 << i))) { > for (int j = i - 1; j >= 0; --j) { > - if (valid_vm[j]) { > + if (cpu->cfg.satp_mode.supported & (1 << j)) { > cpu->cfg.satp_mode.map |= (1 << j); > break; > } > @@ -727,13 +760,12 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > } > } > > - /* Make sure the configuration asked is supported by qemu */ > - for (int i = 0; i < 16; ++i) { > - if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > - error_setg(errp, "satp_mode %s is not valid", > - satp_mode_str(i, rv32)); > - return; > - } > + /* Make sure the user asked for a supported configuration (HW and qemu) */ > + if (satp_mode_map_max > satp_mode_supported_max) { > + error_setg(errp, "satp_mode %s is higher than hw max capability %s", > + satp_mode_str(satp_mode_map_max, rv32), > + satp_mode_str(satp_mode_supported_max, rv32)); > + return; > } > > /* > @@ -741,17 +773,13 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > * the specification. > */ > if (!rv32) { > - uint8_t satp_mode_max; > - > - satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > - > - for (int i = satp_mode_max - 1; i >= 0; --i) { > + for (int i = satp_mode_map_max - 1; i >= 0; --i) { > if (!(cpu->cfg.satp_mode.map & (1 << i)) && > (cpu->cfg.satp_mode.init & (1 << i)) && > - valid_vm[i]) { > + (cpu->cfg.satp_mode.supported & (1 << i))) { > error_setg(errp, "cannot disable %s satp mode if %s " > "is enabled", satp_mode_str(i, false), > - satp_mode_str(satp_mode_max, false)); > + satp_mode_str(satp_mode_map_max, false)); > return; > } > } > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index e37177db5c..b591122099 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -416,13 +416,17 @@ struct RISCVCPUClass { > > /* > * map is a 16-bit bitmap: the most significant set bit in map is the maximum > - * satp mode that is supported. > + * satp mode that is supported. It may be chosen by the user and must respect > + * what qemu implements (valid_1_10_32/64) and what the hw is capable of > + * (supported bitmap below). > * > * init is a 16-bit bitmap used to make sure the user selected a correct > * configuration as per the specification. > + * > + * supported is a 16-bit bitmap used to reflect the hw capabilities. > */ > typedef struct { > - uint16_t map, init; > + uint16_t map, init, supported; > } RISCVSATPMap; > > struct RISCVCPUConfig { > -- > 2.37.2 > Thanks, drew From MAILER-DAEMON Mon Jan 23 09:26:25 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pJxmD-0007PA-8h for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 09:26:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJvQZ-0007iO-CK for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 06:55:55 -0500 Received: from imap4.hz.codethink.co.uk ([188.40.203.114]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pJvQX-0007t3-MB for qemu-riscv@nongnu.org; Mon, 23 Jan 2023 06:55:55 -0500 Received: from [167.98.27.226] (helo=rainbowdash) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pJvQO-009V47-IO; Mon, 23 Jan 2023 11:55:45 +0000 Received: from ben by rainbowdash with local (Exim 4.96) (envelope-from ) id 1pJvQP-000hSe-08; Mon, 23 Jan 2023 11:55:45 +0000 From: Ben Dooks To: qemu-riscv@nongnu.org Cc: frank.chang@sifive.com, jude.onyenegecha@sifive.com, sudip.mukherjee@sifive.com, Ben Dooks Subject: [RFC] riscv: add config for asid size Date: Mon, 23 Jan 2023 11:55:37 +0000 Message-Id: <20230123115537.167054-1-ben.dooks@sifive.com> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=188.40.203.114; envelope-from=ben@codethink.co.uk; helo=imap4.hz.codethink.co.uk X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Mon, 23 Jan 2023 09:26:24 -0500 X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 11:55:55 -0000 Add a config to the cpu state to control the size of the ASID area in the SATP CSR to enable testing with smaller than the default (which is currently maximum for both rv32 and rv64) or 0 to disable the ASID altogether. For example, an rv64 with only 8 asid bits: -cpu rv64,asid-bits=8 or no asids -cpu rv64,asid-bits=0 Signed-off-by: Ben Dooks --- There are still a question of do we update the config if we use the default, and do we need to have any way of runtime changing this? --- target/riscv/cpu.c | 33 +++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 2 ++ target/riscv/cpu_bits.h | 6 ++++-- target/riscv/csr.c | 5 +++-- 4 files changed, 42 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cc75ca7667..a752b60251 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -917,6 +917,38 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) riscv_pmu_timer_cb, cpu); } } + + if (cpu->cfg.mmu) { + target_ulong asid_mask, asid_shift; + + if (riscv_cpu_mxl(&cpu->env) == MXL_RV32) { + asid_mask = SATP32_ASID_MASK; + asid_shift = SATP32_ASID_SHIFT; + } else { + asid_mask = SATP64_ASID_MASK; + asid_shift = SATP64_ASID_SHIFT; + } + + if (cpu->cfg.asid_bits < 0) { + // todo - do we update cpu->cfg.asid_bits here? + env->asid_clear = 0x0; + } else { + target_ulong calc_mask; + + calc_mask = ((target_ulong)1 << cpu->cfg.asid_bits) - 1; + calc_mask <<= asid_shift; + + if (calc_mask > asid_mask) { + error_setg(errp, "too many ASID bits [-1 %d]", + __builtin_clz(asid_mask >> asid_shift)); + return; + } else { + env->asid_clear = calc_mask ^ asid_mask; + } + } + printf("calc_mask = %lx, normal %lx, diff %lx\n", + env->asid_clear, asid_mask, asid_mask ^ env->asid_clear); + } #endif riscv_cpu_register_gdb_regs_for_features(cs); @@ -1022,6 +1054,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), + DEFINE_PROP_INT32("asid-bits", RISCVCPU, cfg.asid_bits, -1), DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f5609b62a2..a756d5be32 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -215,6 +215,7 @@ struct CPUArchState { uint64_t mideleg; target_ulong satp; /* since: priv-1.10.0 */ + target_ulong asid_clear; /* clear these asid bits in satp */ target_ulong stval; target_ulong medeleg; @@ -475,6 +476,7 @@ struct RISCVCPUConfig { /* Vendor-specific custom extensions */ bool ext_XVentanaCondOps; + int32_t asid_bits; uint8_t pmu_num; char *priv_spec; char *user_spec; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 8b0d7e20ea..173616aedc 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -612,12 +612,14 @@ typedef enum { /* RV32 satp CSR field masks */ #define SATP32_MODE 0x80000000 -#define SATP32_ASID 0x7fc00000 +#define SATP32_ASID_MASK 0x7fc00000 +#define SATP32_ASID_SHIFT 22 #define SATP32_PPN 0x003fffff /* RV64 satp CSR field masks */ #define SATP64_MODE 0xF000000000000000ULL -#define SATP64_ASID 0x0FFFF00000000000ULL +#define SATP64_ASID_MASK 0x0FFFF00000000000ULL +#define SATP64_ASID_SHIFT 44 #define SATP64_PPN 0x00000FFFFFFFFFFFULL /* VM modes (satp.mode) privileged ISA 1.10 */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0db2c233e5..8313cd3b43 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2654,12 +2654,13 @@ static RISCVException write_satp(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } + val &= ~env->asid_clear; if (riscv_cpu_mxl(env) == MXL_RV32) { vm = validate_vm(env, get_field(val, SATP32_MODE)); - mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID | SATP32_PPN); + mask = (val ^ env->satp) & (SATP32_MODE | SATP32_ASID_MASK | SATP32_PPN); } else { vm = validate_vm(env, get_field(val, SATP64_MODE)); - mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID | SATP64_PPN); + mask = (val ^ env->satp) & (SATP64_MODE | SATP64_ASID_MASK | SATP64_PPN); } if (vm && mask) { -- 2.39.0 From MAILER-DAEMON Mon Jan 23 17:40:07 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK5Tz-00062z-Hs for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 17:40:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK5Tx-00062H-0V; Mon, 23 Jan 2023 17:40:05 -0500 Received: from mail-vk1-xa2b.google.com ([2607:f8b0:4864:20::a2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK5Tu-0004p2-GK; Mon, 23 Jan 2023 17:40:04 -0500 Received: by mail-vk1-xa2b.google.com with SMTP id i82so6753060vki.8; Mon, 23 Jan 2023 14:40:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=R6qDaSB1eZAp6e7Eb1wnVLWxQEGT7OzrisF9ZhbUIdo=; b=Tjzze3o+3HUwFv+2hrI7HyO1d79LkWUeB72AeZ/bBVJoh1fiqiGs8kVgYE2L//kkXF QYsYhemaFlZGj+nCazl9z/rQSg55to2pPh2idmRGJ+sem4LYFWh+H2KwCeJ74rVZH7bS PYfOI4Hiv3b/V0VU64vL9ae85HdCZaPr6L8jwUC9vGpzR3JnAz8hZ/OJy5+eZogCyvF9 yNHyrAdIxhqlgaBaqWQpO7u3pC6YxWrfl7rx3IBeERWDCtbuf2N4hn/J56Y19uWNrWWb Y5aNyS1L5Hx6M9BzdNlqTsUc2CESjERhVWHISU15GaEl61xk6ZsNUf2EJ/cIONM1mMQy x6cg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=R6qDaSB1eZAp6e7Eb1wnVLWxQEGT7OzrisF9ZhbUIdo=; b=ZAl12DFNsxxiW0fQgnL5edJtzuxMKVnIEAU734Pxh1w1a0S+ttywDJ3debi4gFWsLN 3IrEKVkIB9OUWKAN9cY7Pk8Zxs1L+mtQuZ+KvWJpkUpZvbqgMc4gaAx3vLT4+sQudcmJ S9jjFnXNDHk7RL/qMOC5dkwjhRHshPmhlyOUTotKU5HMxkoIIBQCKj/UhcyC9qKqZR6a KC7Im0ffJ9DMZyaF7A/IbFJk1/0X94lhbM3m93aVXOnXOYR2W0+osa4J2pQNWo8JJ/3R ttYmoFmKAQkxFqUeJeiMYAEKH2lMGr0S4/74ZM9jPcElp6p+sHAs3VsL6ahaP/n5T/eQ d0kQ== X-Gm-Message-State: AFqh2kqG78j2G45yOvWN+wNeIJhbfiJAgke4YMyY3f2HgsjmmYav3yR9 PRHOTwS1/K53cbkyIDDc4z4REpNlEGK03vAkzYc= X-Google-Smtp-Source: AMrXdXtva2IT59FPFTe1UiSjnsp1P4KDi+yzH/6SI7RUQwN3f3ta3/UVVQljpHk8kgSvxm3qEz2of/a7rGl7j55Y6hU= X-Received: by 2002:a05:6122:924:b0:3d5:5f93:53f with SMTP id j36-20020a056122092400b003d55f93053fmr3391315vka.7.1674513599622; Mon, 23 Jan 2023 14:39:59 -0800 (PST) MIME-Version: 1.0 References: <20230123063619.222459-1-wilfred.mallawa@opensource.wdc.com> In-Reply-To: <20230123063619.222459-1-wilfred.mallawa@opensource.wdc.com> From: Alistair Francis Date: Tue, 24 Jan 2023 08:39:33 +1000 Message-ID: Subject: Re: [PATCH v2] include/hw/riscv/opentitan: update opentitan IRQs To: Wilfred Mallawa Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Wilfred Mallawa Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::a2b; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 22:40:05 -0000 On Mon, Jan 23, 2023 at 4:40 PM Wilfred Mallawa wrote: > > From: Wilfred Mallawa > > Updates the opentitan IRQs to match the latest supported commit of > Opentitan from TockOS. > > OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47 > > Memory layout as per [1] > > [1] https://github.com/lowRISC/opentitan/blob/565e4af39760a123c59a184aa2f5812a961fde47/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h > > Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis Alistair > --- > Changes in v2: > - Updated the MMIO register layout/size > - Bumped the supported commit sha > - Added link to OT register layout for reference in the commit > msg > > hw/riscv/opentitan.c | 80 ++++++++++++++++++------------------ > include/hw/riscv/opentitan.h | 14 +++---- > 2 files changed, 47 insertions(+), 47 deletions(-) > > diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c > index 64d5d435b9..353f030d80 100644 > --- a/hw/riscv/opentitan.c > +++ b/hw/riscv/opentitan.c > @@ -31,47 +31,47 @@ > /* > * This version of the OpenTitan machine currently supports > * OpenTitan RTL version: > - * > + * > * > * MMIO mapping as per (specified commit): > * lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h > */ > static const MemMapEntry ibex_memmap[] = { > - [IBEX_DEV_ROM] = { 0x00008000, 0x8000 }, > - [IBEX_DEV_RAM] = { 0x10000000, 0x20000 }, > - [IBEX_DEV_FLASH] = { 0x20000000, 0x100000 }, > - [IBEX_DEV_UART] = { 0x40000000, 0x1000 }, > - [IBEX_DEV_GPIO] = { 0x40040000, 0x1000 }, > - [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x1000 }, > - [IBEX_DEV_I2C] = { 0x40080000, 0x1000 }, > - [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 }, > - [IBEX_DEV_TIMER] = { 0x40100000, 0x1000 }, > - [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 }, > - [IBEX_DEV_LC_CTRL] = { 0x40140000, 0x1000 }, > - [IBEX_DEV_ALERT_HANDLER] = { 0x40150000, 0x1000 }, > - [IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x1000 }, > - [IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x1000 }, > - [IBEX_DEV_USBDEV] = { 0x40320000, 0x1000 }, > - [IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 }, > - [IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 }, > - [IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 }, > - [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 }, > - [IBEX_DEV_AON_TIMER] = { 0x40470000, 0x1000 }, > - [IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x1000 }, > - [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 }, > - [IBEX_DEV_AES] = { 0x41100000, 0x1000 }, > - [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 }, > - [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 }, > - [IBEX_DEV_OTBN] = { 0x41130000, 0x10000 }, > - [IBEX_DEV_KEYMGR] = { 0x41140000, 0x1000 }, > - [IBEX_DEV_CSRNG] = { 0x41150000, 0x1000 }, > - [IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 }, > - [IBEX_DEV_EDNO] = { 0x41170000, 0x1000 }, > - [IBEX_DEV_EDN1] = { 0x41180000, 0x1000 }, > - [IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 }, > - [IBEX_DEV_PERI] = { 0x411f0000, 0x10000 }, > - [IBEX_DEV_PLIC] = { 0x48000000, 0x4005000 }, > - [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 }, > + [IBEX_DEV_ROM] = { 0x00008000, 0x8000 }, > + [IBEX_DEV_RAM] = { 0x10000000, 0x20000 }, > + [IBEX_DEV_FLASH] = { 0x20000000, 0x100000 }, > + [IBEX_DEV_UART] = { 0x40000000, 0x40 }, > + [IBEX_DEV_GPIO] = { 0x40040000, 0x40 }, > + [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x2000 }, > + [IBEX_DEV_I2C] = { 0x40080000, 0x80 }, > + [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x40 }, > + [IBEX_DEV_TIMER] = { 0x40100000, 0x200 }, > + [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x2000 }, > + [IBEX_DEV_LC_CTRL] = { 0x40140000, 0x100 }, > + [IBEX_DEV_ALERT_HANDLER] = { 0x40150000, 0x800 }, > + [IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x40 }, > + [IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x40 }, > + [IBEX_DEV_USBDEV] = { 0x40320000, 0x1000 }, > + [IBEX_DEV_PWRMGR] = { 0x40400000, 0x80 }, > + [IBEX_DEV_RSTMGR] = { 0x40410000, 0x80 }, > + [IBEX_DEV_CLKMGR] = { 0x40420000, 0x80 }, > + [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 }, > + [IBEX_DEV_AON_TIMER] = { 0x40470000, 0x40 }, > + [IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x40 }, > + [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x200 }, > + [IBEX_DEV_AES] = { 0x41100000, 0x100 }, > + [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 }, > + [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 }, > + [IBEX_DEV_OTBN] = { 0x41130000, 0x10000 }, > + [IBEX_DEV_KEYMGR] = { 0x41140000, 0x100 }, > + [IBEX_DEV_CSRNG] = { 0x41150000, 0x80 }, > + [IBEX_DEV_ENTROPY] = { 0x41160000, 0x100 }, > + [IBEX_DEV_EDNO] = { 0x41170000, 0x80 }, > + [IBEX_DEV_EDN1] = { 0x41180000, 0x80 }, > + [IBEX_DEV_SRAM_CTRL] = { 0x411c0000, 0x20 }, > + [IBEX_DEV_IBEX_CFG] = { 0x411f0000, 0x100 }, > + [IBEX_DEV_PLIC] = { 0x48000000, 0x8000000 }, > + [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 }, > }; > > static void opentitan_board_init(MachineState *machine) > @@ -294,12 +294,12 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) > memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size); > create_unimplemented_device("riscv.lowrisc.ibex.alert_handler", > memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size); > - create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen", > - memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size); > + create_unimplemented_device("riscv.lowrisc.ibex.sram_ctrl", > + memmap[IBEX_DEV_SRAM_CTRL].base, memmap[IBEX_DEV_SRAM_CTRL].size); > create_unimplemented_device("riscv.lowrisc.ibex.otbn", > memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size); > - create_unimplemented_device("riscv.lowrisc.ibex.peri", > - memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size); > + create_unimplemented_device("riscv.lowrisc.ibex.ibex_cfg", > + memmap[IBEX_DEV_IBEX_CFG].base, memmap[IBEX_DEV_IBEX_CFG].size); > } > > static Property lowrisc_ibex_soc_props[] = { > diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h > index 7659d1bc5b..c40b05052a 100644 > --- a/include/hw/riscv/opentitan.h > +++ b/include/hw/riscv/opentitan.h > @@ -94,9 +94,9 @@ enum { > IBEX_DEV_EDNO, > IBEX_DEV_EDN1, > IBEX_DEV_ALERT_HANDLER, > - IBEX_DEV_NMI_GEN, > + IBEX_DEV_SRAM_CTRL, > IBEX_DEV_OTBN, > - IBEX_DEV_PERI, > + IBEX_DEV_IBEX_CFG, > }; > > enum { > @@ -108,11 +108,11 @@ enum { > IBEX_UART0_RX_BREAK_ERR_IRQ = 6, > IBEX_UART0_RX_TIMEOUT_IRQ = 7, > IBEX_UART0_RX_PARITY_ERR_IRQ = 8, > - IBEX_TIMER_TIMEREXPIRED0_0 = 127, > - IBEX_SPI_HOST0_ERR_IRQ = 134, > - IBEX_SPI_HOST0_SPI_EVENT_IRQ = 135, > - IBEX_SPI_HOST1_ERR_IRQ = 136, > - IBEX_SPI_HOST1_SPI_EVENT_IRQ = 137, > + IBEX_TIMER_TIMEREXPIRED0_0 = 124, > + IBEX_SPI_HOST0_ERR_IRQ = 131, > + IBEX_SPI_HOST0_SPI_EVENT_IRQ = 132, > + IBEX_SPI_HOST1_ERR_IRQ = 133, > + IBEX_SPI_HOST1_SPI_EVENT_IRQ = 134, > }; > > #endif > -- > 2.39.1 > > From MAILER-DAEMON Mon Jan 23 17:50:26 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK5dv-00085O-L6 for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 17:50:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK5dt-000856-8G; Mon, 23 Jan 2023 17:50:21 -0500 Received: from mail-vk1-xa2c.google.com ([2607:f8b0:4864:20::a2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK5dq-0006Tp-0S; Mon, 23 Jan 2023 17:50:21 -0500 Received: by mail-vk1-xa2c.google.com with SMTP id t2so6767820vkk.9; Mon, 23 Jan 2023 14:50:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=OrHEM6IxsY3EE6MKnYDaPOHYvQiIofAFFhu0Ipm5UI8=; b=XFM9dK5EpT7dhghnl3vh+xEuAXvHQn27oceBv/RIHJWrpTozt8JPXIxe2XGC8oFwct akYY479zPIrwWIegQoyU2FUnBSabEgEQ3J945k0RBgZmyb24Gv5xgL/+si0qsSHlWOya 4Gg6WhDvVVveAswUtXP49IKwK1fIUmFqtPVOozd/dfUiBwWL+996K2MY+yMA9Txrn9jy 0ecMsH8SV1XMx2exX66/w2/vSB2LZf+wWxcHozX6eym6MF8OQnRl5zVsKRXJZ8Vsu+4f bx4xuOsXsS3zRqeoSVXoYLgz/sPtCkLQBsV6lCka+gHYCcqyIq4tNshTHCo7FDeD1ihD ESww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OrHEM6IxsY3EE6MKnYDaPOHYvQiIofAFFhu0Ipm5UI8=; b=GIfRxRtufnFgOK1M8qdit2Hdyp8xSeNvOJCZGv4SPRx8K/Qh2nn2EbFpACz6/GUflc zcMrQTeFsK7KZYVgDld3i6qjWWGmQjXBKnmQYK1W4PFnx8P0qRXyKtzCzxPa3cBSa6dA 3yzXLuP5k98ZRNy6O0FNaLWVbl+KTgMgzFsPzo1TpwSG1buTMf8bMX1NtUMz9y9T/92f y9cASTAEFYC+OeslrS6+JbmOsq6Gun1xfXc4tC/z4A33RGwPSVR2zccOKDGtj89CWjfG iLyGtWqTRO2GWps4vgcZ42cl9efvLC8nicz5w/1TPxaWuU6y6VL/V/v55xeFQB1ITKcD EFhA== X-Gm-Message-State: AFqh2krPVHRvHhWy4G+zdKpKKcjBWCk5jn/xmMydQ7V4mXax7XFS3924 LIK67ZhGJRGxCBGOexhJpSlEDWuW1uyIx06+YCg= X-Google-Smtp-Source: AMrXdXuIIfCxC8fmfRjyfkm0UPYfiVkTG74B8fyf0NpfPVIxOo4+pCNtkiKeQvwhlbbzaILARZeb7F8qktOLqXj6HB0= X-Received: by 2002:a1f:b681:0:b0:3dd:fc42:994d with SMTP id g123-20020a1fb681000000b003ddfc42994dmr3515028vkf.25.1674514216393; Mon, 23 Jan 2023 14:50:16 -0800 (PST) MIME-Version: 1.0 References: <20221223180016.2068508-1-christoph.muellner@vrull.eu> <20221223180016.2068508-2-christoph.muellner@vrull.eu> In-Reply-To: <20221223180016.2068508-2-christoph.muellner@vrull.eu> From: Alistair Francis Date: Tue, 24 Jan 2023 08:49:50 +1000 Message-ID: Subject: Re: [PATCH v2 01/15] RISC-V: Adding XTheadCmo ISA extension To: Christoph Muellner Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a2c; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 22:50:21 -0000 On Sat, Dec 24, 2022 at 4:09 AM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > This patch adds support for the XTheadCmo ISA extension. > To avoid interfering with standard extensions, decoder and translation > are in its own xthead* specific files. > Future patches should be able to easily add additional T-Head extension. > > The implementation does not have much functionality (besides accepting > the instructions and not qualifying them as illegal instructions if > the hart executes in the required privilege level for the instruction), > as QEMU does not model CPU caches and instructions are documented > to not raise any exceptions. > > Changes in v2: > - Add ISA_EXT_DATA_ENTRY() > - Explicit test for PRV_U > - Encapsule access to env-priv in inline function > - Use single decoder for XThead extensions > > Co-developed-by: LIU Zhiwei > Signed-off-by: Christoph M=C3=BCllner > --- > target/riscv/cpu.c | 2 + > target/riscv/cpu.h | 1 + > target/riscv/insn_trans/trans_xthead.c.inc | 89 ++++++++++++++++++++++ > target/riscv/meson.build | 1 + > target/riscv/translate.c | 15 +++- > target/riscv/xthead.decode | 38 +++++++++ > 6 files changed, 143 insertions(+), 3 deletions(-) > create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc > create mode 100644 target/riscv/xthead.decode > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6fe176e483..a90b82c5c5 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -108,6 +108,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D = { > ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), > ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), > ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), > + ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadc= mo), > ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_X= VentanaCondOps), > }; > > @@ -1060,6 +1061,7 @@ static Property riscv_cpu_extensions[] =3D { > DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), > > /* Vendor-specific custom extensions */ > + DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), > DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOp= s, false), > > /* These are experimental so mark with 'x-' */ > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 443d15a47c..ad1c19f870 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -465,6 +465,7 @@ struct RISCVCPUConfig { > uint64_t mimpid; > > /* Vendor-specific custom extensions */ > + bool ext_xtheadcmo; > bool ext_XVentanaCondOps; > > uint8_t pmu_num; > diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/in= sn_trans/trans_xthead.c.inc > new file mode 100644 > index 0000000000..00e75c7dca > --- /dev/null > +++ b/target/riscv/insn_trans/trans_xthead.c.inc > @@ -0,0 +1,89 @@ > +/* > + * RISC-V translation routines for the T-Head vendor extensions (xthead*= ). > + * > + * Copyright (c) 2022 VRULL GmbH. > + * > + * This program is free software; you can redistribute it and/or modify = it > + * under the terms and conditions of the GNU General Public License, > + * version 2 or later, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOU= T > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License= for > + * more details. > + * > + * You should have received a copy of the GNU General Public License alo= ng with > + * this program. If not, see . > + */ > + > +#define REQUIRE_XTHEADCMO(ctx) do { \ > + if (!ctx->cfg_ptr->ext_xtheadcmo) { \ > + return false; \ > + } \ > +} while (0) > + > +/* XTheadCmo */ > + > +static inline int priv_level(DisasContext *ctx) > +{ > +#ifdef CONFIG_USER_ONLY > + return PRV_U; > +#else > + /* Priv level equals mem_idx -- see cpu_mmu_index. */ > + return ctx->mem_idx; This should be ANDed with TB_FLAGS_PRIV_MMU_MASK as sometimes this can include hypervisor priv access information > +#endif > +} > + > +#define REQUIRE_PRIV_MHSU(ctx) \ > +do { \ > + int priv =3D priv_level(ctx); \ > + if (!(priv =3D=3D PRV_M || \ > + priv =3D=3D PRV_H || \ PRV_H isn't used > + priv =3D=3D PRV_S || \ > + priv =3D=3D PRV_U)) { \ > + return false; \ When would this not be the case? > + } \ > +} while (0) > + > +#define REQUIRE_PRIV_MHS(ctx) \ > +do { \ > + int priv =3D priv_level(ctx); \ > + if (!(priv =3D=3D PRV_M || \ > + priv =3D=3D PRV_H || \ Also not used > + priv =3D=3D PRV_S)) { \ > + return false; \ > + } \ > +} while (0) > + > +#define NOP_PRIVCHECK(insn, extcheck, privcheck) \ > +static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn * a) \ > +{ \ > + (void) a; \ > + extcheck(ctx); \ > + privcheck(ctx); \ > + return true; \ > +} > + > +NOP_PRIVCHECK(th_dcache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_cpa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_cipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_cva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) > +NOP_PRIVCHECK(th_dcache_civa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) > +NOP_PRIVCHECK(th_dcache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) > +NOP_PRIVCHECK(th_dcache_csw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_cisw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_isw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_cpal1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_cval1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > + > +NOP_PRIVCHECK(th_icache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_icache_ialls, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_icache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) > + > +NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > diff --git a/target/riscv/meson.build b/target/riscv/meson.build > index ba25164d74..5dee37a242 100644 > --- a/target/riscv/meson.build > +++ b/target/riscv/meson.build > @@ -2,6 +2,7 @@ > gen =3D [ > decodetree.process('insn16.decode', extra_args: ['--static-decode=3Dde= code_insn16', '--insnwidth=3D16']), > decodetree.process('insn32.decode', extra_args: '--static-decode=3Ddec= ode_insn32'), > + decodetree.process('xthead.decode', extra_args: '--static-decode=3Ddec= ode_xthead'), > decodetree.process('XVentanaCondOps.decode', extra_args: '--static-dec= ode=3Ddecode_XVentanaCodeOps'), > ] > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index db123da5ec..14d9116975 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -125,13 +125,18 @@ static bool always_true_p(DisasContext *ctx __attr= ibute__((__unused__))) > return true; > } > > +static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) > +{ > + return ctx->cfg_ptr->ext_xtheadcmo; > +} > + > #define MATERIALISE_EXT_PREDICATE(ext) \ > static bool has_ ## ext ## _p(DisasContext *ctx) \ > { \ > return ctx->cfg_ptr->ext_ ## ext ; \ > } > > -MATERIALISE_EXT_PREDICATE(XVentanaCondOps); > +MATERIALISE_EXT_PREDICATE(XVentanaCondOps) Do we need this change? > > #ifdef TARGET_RISCV32 > #define get_xl(ctx) MXL_RV32 > @@ -732,6 +737,10 @@ static int ex_rvc_shiftri(DisasContext *ctx, int imm= ) > /* Include the auto-generated decoder for 32 bit insn */ > #include "decode-insn32.c.inc" > > +/* Include decoders for factored-out extensions */ > +#include "decode-xthead.c.inc" > +#include "decode-XVentanaCondOps.c.inc" > + > static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, > void (*func)(TCGv, TCGv, target_long)) > { > @@ -1033,12 +1042,11 @@ static uint32_t opcode_at(DisasContextBase *dcbas= e, target_ulong pc) > #include "insn_trans/trans_rvk.c.inc" > #include "insn_trans/trans_privileged.c.inc" > #include "insn_trans/trans_svinval.c.inc" > +#include "insn_trans/trans_xthead.c.inc" > #include "insn_trans/trans_xventanacondops.c.inc" > > /* Include the auto-generated decoder for 16 bit insn */ > #include "decode-insn16.c.inc" > -/* Include decoders for factored-out extensions */ > -#include "decode-XVentanaCondOps.c.inc" Can we not leave these at the bottom? Alistair > > /* The specification allows for longer insns, but not supported by qemu.= */ > #define MAX_INSN_LEN 4 > @@ -1059,6 +1067,7 @@ static void decode_opc(CPURISCVState *env, DisasCon= text *ctx, uint16_t opcode) > bool (*decode_func)(DisasContext *, uint32_t); > } decoders[] =3D { > { always_true_p, decode_insn32 }, > + { has_xthead_p, decode_xthead }, > { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, > }; > > diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode > new file mode 100644 > index 0000000000..30533a66f5 > --- /dev/null > +++ b/target/riscv/xthead.decode > @@ -0,0 +1,38 @@ > +# > +# Translation routines for the instructions of the XThead* ISA extension= s > +# > +# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu > +# > +# SPDX-License-Identifier: LGPL-2.1-or-later > +# > +# The documentation of the ISA extensions can be found here: > +# https://github.com/T-head-Semi/thead-extension-spec/releases/latest > + > +# Fields: > +%rs1 15:5 > + > +# Formats > +@sfence_vm ....... ..... ..... ... ..... ....... %rs1 > + > +# XTheadCmo > +th_dcache_call 0000000 00001 00000 000 00000 0001011 > +th_dcache_ciall 0000000 00011 00000 000 00000 0001011 > +th_dcache_iall 0000000 00010 00000 000 00000 0001011 > +th_dcache_cpa 0000001 01001 ..... 000 00000 0001011 @sfence_vm > +th_dcache_cipa 0000001 01011 ..... 000 00000 0001011 @sfence_vm > +th_dcache_ipa 0000001 01010 ..... 000 00000 0001011 @sfence_vm > +th_dcache_cva 0000001 00101 ..... 000 00000 0001011 @sfence_vm > +th_dcache_civa 0000001 00111 ..... 000 00000 0001011 @sfence_vm > +th_dcache_iva 0000001 00110 ..... 000 00000 0001011 @sfence_vm > +th_dcache_csw 0000001 00001 ..... 000 00000 0001011 @sfence_vm > +th_dcache_cisw 0000001 00011 ..... 000 00000 0001011 @sfence_vm > +th_dcache_isw 0000001 00010 ..... 000 00000 0001011 @sfence_vm > +th_dcache_cpal1 0000001 01000 ..... 000 00000 0001011 @sfence_vm > +th_dcache_cval1 0000001 00100 ..... 000 00000 0001011 @sfence_vm > +th_icache_iall 0000000 10000 00000 000 00000 0001011 > +th_icache_ialls 0000000 10001 00000 000 00000 0001011 > +th_icache_ipa 0000001 11000 ..... 000 00000 0001011 @sfence_vm > +th_icache_iva 0000001 10000 ..... 000 00000 0001011 @sfence_vm > +th_l2cache_call 0000000 10101 00000 000 00000 0001011 > +th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 > +th_l2cache_iall 0000000 10110 00000 000 00000 0001011 > -- > 2.38.1 > > From MAILER-DAEMON Mon Jan 23 17:55:13 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK5ib-0000xA-DQ for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 17:55:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK5ia-0000w6-Dw; Mon, 23 Jan 2023 17:55:12 -0500 Received: from mail-vs1-xe33.google.com ([2607:f8b0:4864:20::e33]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK5iX-0007AN-Et; Mon, 23 Jan 2023 17:55:12 -0500 Received: by mail-vs1-xe33.google.com with SMTP id k4so14711555vsc.4; Mon, 23 Jan 2023 14:55:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=vZxUgZ9RAv5GrC0ichKh+1Lei8+P35Lb20jNbBf0cX8=; b=WeSwMEFlxakt49RG+IJCECjV/R6/+VSQj7mv+8Af/b2yIXT4V7Cy/qTzT64WJ8sioD HI77n2P7W6RPqz5NswgJsH+F+KEyPOpwb8Cj4zCGey7gHfAainwtkoKm12Ue83esE5JG DaA85y86e6/PaQBvclJ1dnHIy++FcVMqwy+sdPQAXoNSDMjiI/1mdf9Wr0Rn0KsSuvtb AqwbH+4OzYMRL308QebPAD+jdHUVSUXaeExpA6K75EEF71nwVuhm8H8ZX2oisztLK5LT 43HkoqY8rMSoWCsrLD1a897aiRIvSHGby2tslUOJUTmQlhyYiiBbF8S3X92JyNo+NqVE FnrA== X-Google-DKIM-Signature: v=1; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e33; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe33.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 22:55:12 -0000 On Sat, Dec 24, 2022 at 4:04 AM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > This patch adds support for the XTheadSync ISA extension. > The patch uses the T-Head specific decoder and translation. > > The implementation introduces a helper to execute synchronization tasks: > helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs. > > Changes in v2: > - Add ISA_EXT_DATA_ENTRY() > - Use helper to synchronize CPUs and perform TLB flushes > - Change implemenation to follow latest spec update > - Use single decoder for XThead extensions > > Co-developed-by: LIU Zhiwei > Signed-off-by: Christoph M=C3=BCllner Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 2 + > target/riscv/cpu.h | 1 + > target/riscv/helper.h | 1 + > target/riscv/insn_trans/trans_xthead.c.inc | 86 ++++++++++++++++++++++ > target/riscv/op_helper.c | 6 ++ > target/riscv/translate.c | 2 +- > target/riscv/xthead.decode | 9 +++ > 7 files changed, 106 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index a90b82c5c5..a848836d2e 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -109,6 +109,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D = { > ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), > ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), > ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadc= mo), > + ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xthead= sync), > ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_X= VentanaCondOps), > }; > > @@ -1062,6 +1063,7 @@ static Property riscv_cpu_extensions[] =3D { > > /* Vendor-specific custom extensions */ > DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), > + DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), > DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOp= s, false), > > /* These are experimental so mark with 'x-' */ > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index ad1c19f870..4d3da2acfa 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -466,6 +466,7 @@ struct RISCVCPUConfig { > > /* Vendor-specific custom extensions */ > bool ext_xtheadcmo; > + bool ext_xtheadsync; > bool ext_XVentanaCondOps; > > uint8_t pmu_num; > diff --git a/target/riscv/helper.h b/target/riscv/helper.h > index a03014fe67..ecfb8c280f 100644 > --- a/target/riscv/helper.h > +++ b/target/riscv/helper.h > @@ -109,6 +109,7 @@ DEF_HELPER_1(sret, tl, env) > DEF_HELPER_1(mret, tl, env) > DEF_HELPER_1(wfi, void, env) > DEF_HELPER_1(tlb_flush, void, env) > +DEF_HELPER_1(tlb_flush_all, void, env) > #endif > > /* Hypervisor functions */ > diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/in= sn_trans/trans_xthead.c.inc > index 00e75c7dca..6009d61c81 100644 > --- a/target/riscv/insn_trans/trans_xthead.c.inc > +++ b/target/riscv/insn_trans/trans_xthead.c.inc > @@ -22,6 +22,12 @@ > } \ > } while (0) > > +#define REQUIRE_XTHEADSYNC(ctx) do { \ > + if (!ctx->cfg_ptr->ext_xtheadsync) { \ > + return false; \ > + } \ > +} while (0) > + > /* XTheadCmo */ > > static inline int priv_level(DisasContext *ctx) > @@ -87,3 +93,83 @@ NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIR= E_PRIV_MHSU) > NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > + > +/* XTheadSync */ > + > +static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *= a) > +{ > + (void) a; > + REQUIRE_XTHEADSYNC(ctx); > + > +#ifndef CONFIG_USER_ONLY > + REQUIRE_PRIV_MHS(ctx); > + decode_save_opc(ctx); > + gen_helper_tlb_flush_all(cpu_env); > + return true; > +#else > + return false; > +#endif > +} > + > +#ifndef CONFIG_USER_ONLY > +static void gen_th_sync_local(DisasContext *ctx) > +{ > + /* > + * Emulate out-of-order barriers with pipeline flush > + * by exiting the translation block. > + */ > + gen_set_pc_imm(ctx, ctx->pc_succ_insn); > + tcg_gen_exit_tb(NULL, 0); > + ctx->base.is_jmp =3D DISAS_NORETURN; > +} > +#endif > + > +static bool trans_th_sync(DisasContext *ctx, arg_th_sync *a) > +{ > + (void) a; > + REQUIRE_XTHEADSYNC(ctx); > + > +#ifndef CONFIG_USER_ONLY > + REQUIRE_PRIV_MHSU(ctx); > + > + /* > + * th.sync is an out-of-order barrier. > + */ > + gen_th_sync_local(ctx); > + > + return true; > +#else > + return false; > +#endif > +} > + > +static bool trans_th_sync_i(DisasContext *ctx, arg_th_sync_i *a) > +{ > + (void) a; > + REQUIRE_XTHEADSYNC(ctx); > + > +#ifndef CONFIG_USER_ONLY > + REQUIRE_PRIV_MHSU(ctx); > + > + /* > + * th.sync.i is th.sync plus pipeline flush. > + */ > + gen_th_sync_local(ctx); > + > + return true; > +#else > + return false; > +#endif > +} > + > +static bool trans_th_sync_is(DisasContext *ctx, arg_th_sync_is *a) > +{ > + /* This instruction has the same behaviour like th.sync.i. */ > + return trans_th_sync_i(ctx, a); > +} > + > +static bool trans_th_sync_s(DisasContext *ctx, arg_th_sync_s *a) > +{ > + /* This instruction has the same behaviour like th.sync. */ > + return trans_th_sync(ctx, a); > +} > diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c > index 09f1f5185d..9e3c3f6bf1 100644 > --- a/target/riscv/op_helper.c > +++ b/target/riscv/op_helper.c > @@ -260,6 +260,12 @@ void helper_tlb_flush(CPURISCVState *env) > } > } > > +void helper_tlb_flush_all(CPURISCVState *env) > +{ > + CPUState *cs =3D env_cpu(env); > + tlb_flush_all_cpus_synced(cs); > +} > + > void helper_hyp_tlb_flush(CPURISCVState *env) > { > CPUState *cs =3D env_cpu(env); > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 14d9116975..c40617662a 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -127,7 +127,7 @@ static bool always_true_p(DisasContext *ctx __attrib= ute__((__unused__))) > > static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) > { > - return ctx->cfg_ptr->ext_xtheadcmo; > + return ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; > } > > #define MATERIALISE_EXT_PREDICATE(ext) \ > diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode > index 30533a66f5..1d86f3a012 100644 > --- a/target/riscv/xthead.decode > +++ b/target/riscv/xthead.decode > @@ -10,9 +10,11 @@ > > # Fields: > %rs1 15:5 > +%rs2 20:5 > > # Formats > @sfence_vm ....... ..... ..... ... ..... ....... %rs1 > +@rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 > > # XTheadCmo > th_dcache_call 0000000 00001 00000 000 00000 0001011 > @@ -36,3 +38,10 @@ th_icache_iva 0000001 10000 ..... 000 00000 0001011= @sfence_vm > th_l2cache_call 0000000 10101 00000 000 00000 0001011 > th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 > th_l2cache_iall 0000000 10110 00000 000 00000 0001011 > + > +# XTheadSync > +th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s > +th_sync 0000000 11000 00000 000 00000 0001011 > +th_sync_i 0000000 11010 00000 000 00000 0001011 > +th_sync_is 0000000 11011 00000 000 00000 0001011 > +th_sync_s 0000000 11001 00000 000 00000 0001011 > -- > 2.38.1 > > From MAILER-DAEMON Mon Jan 23 17:56:12 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK5jY-0001i8-Oq for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 17:56:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK5jX-0001hd-9T; Mon, 23 Jan 2023 17:56:11 -0500 Received: from mail-vs1-xe34.google.com ([2607:f8b0:4864:20::e34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK5jU-0007Me-8F; Mon, 23 Jan 2023 17:56:10 -0500 Received: by mail-vs1-xe34.google.com with SMTP id t10so14733415vsr.3; Mon, 23 Jan 2023 14:56:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=N06NnhVaUdYbKzeB4vHXnuqqpbV1u/Omrk1hGgWoqyM=; b=aOntVV81Vw+x134/OxQyOS+NhJ9tpZ9iqTef7L7KZ50V7YjQq/J3KXGt4U0OamlIS5 eFToU7IB5MgNa1N5QXb20YkOAKEgA3075XI3UM8vfrVTQgyRiFL0DFCCzDqMo6VIuiMl GrRaipxKfdbJJ99N/rZuhmhKJvGM4Izw3n85pB5KsXK2G9cjid3DbUBjMQfn/wJtLFAN PEC4X6etXrjwn52kcUYz47TMDQFf14TQ0P3ijgjof8MbS4qYFQEXv/kuORSKPIOA+ZgP lQM7+lUJHopzjU/zusBr8yYvEm48/kdit253JtWt4/hYcxORXYQ0DvTElxAPr15L5KR3 bGjw== X-Google-DKIM-Signature: v=1; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e34; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe34.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 22:56:11 -0000 On Sat, Dec 24, 2022 at 4:10 AM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > This patch adds support for the XTheadBa ISA extension. > The patch uses the T-Head specific decoder and translation. > > Changes in v2: > - Add ISA_EXT_DATA_ENTRY() > - Split XtheadB* extension into individual commits > - Use single decoder for XThead extensions > > Co-developed-by: Philipp Tomsich > Co-developed-by: LIU Zhiwei > Signed-off-by: Christoph M=C3=BCllner Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 2 ++ > target/riscv/cpu.h | 1 + > target/riscv/insn_trans/trans_xthead.c.inc | 39 ++++++++++++++++++++++ > target/riscv/translate.c | 3 +- > target/riscv/xthead.decode | 22 ++++++++++++ > 5 files changed, 66 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index a848836d2e..809b6eb4ed 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -108,6 +108,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D = { > ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), > ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), > ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), > + ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba= ), > ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadc= mo), > ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xthead= sync), > ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_X= VentanaCondOps), > @@ -1062,6 +1063,7 @@ static Property riscv_cpu_extensions[] =3D { > DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), > > /* Vendor-specific custom extensions */ > + DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), > DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), > DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), > DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOp= s, false), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 4d3da2acfa..ec2588a0f0 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -465,6 +465,7 @@ struct RISCVCPUConfig { > uint64_t mimpid; > > /* Vendor-specific custom extensions */ > + bool ext_xtheadba; > bool ext_xtheadcmo; > bool ext_xtheadsync; > bool ext_XVentanaCondOps; > diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/in= sn_trans/trans_xthead.c.inc > index 6009d61c81..79e1f5bde9 100644 > --- a/target/riscv/insn_trans/trans_xthead.c.inc > +++ b/target/riscv/insn_trans/trans_xthead.c.inc > @@ -16,6 +16,12 @@ > * this program. If not, see . > */ > > +#define REQUIRE_XTHEADBA(ctx) do { \ > + if (!ctx->cfg_ptr->ext_xtheadba) { \ > + return false; \ > + } \ > +} while (0) > + > #define REQUIRE_XTHEADCMO(ctx) do { \ > if (!ctx->cfg_ptr->ext_xtheadcmo) { \ > return false; \ > @@ -28,6 +34,39 @@ > } \ > } while (0) > > +/* XTheadBa */ > + > +/* > + * th.addsl is similar to sh[123]add (from Zba), but not an > + * alternative encoding: while sh[123] applies the shift to rs1, > + * th.addsl shifts rs2. > + */ > + > +#define GEN_TH_ADDSL(SHAMT) \ > +static void gen_th_addsl##SHAMT(TCGv ret, TCGv arg1, TCGv arg2) \ > +{ \ > + TCGv t =3D tcg_temp_new(); \ > + tcg_gen_shli_tl(t, arg2, SHAMT); \ > + tcg_gen_add_tl(ret, t, arg1); \ > + tcg_temp_free(t); \ > +} > + > +GEN_TH_ADDSL(1) > +GEN_TH_ADDSL(2) > +GEN_TH_ADDSL(3) > + > +#define GEN_TRANS_TH_ADDSL(SHAMT) = \ > +static bool trans_th_addsl##SHAMT(DisasContext *ctx, = \ > + arg_th_addsl##SHAMT * a) = \ > +{ = \ > + REQUIRE_XTHEADBA(ctx); = \ > + return gen_arith(ctx, a, EXT_NONE, gen_th_addsl##SHAMT, NULL); = \ > +} > + > +GEN_TRANS_TH_ADDSL(1) > +GEN_TRANS_TH_ADDSL(2) > +GEN_TRANS_TH_ADDSL(3) > + > /* XTheadCmo */ > > static inline int priv_level(DisasContext *ctx) > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index c40617662a..7b35f1d71b 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -127,7 +127,8 @@ static bool always_true_p(DisasContext *ctx __attrib= ute__((__unused__))) > > static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) > { > - return ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; > + return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadcmo || > + ctx->cfg_ptr->ext_xtheadsync; > } > > #define MATERIALISE_EXT_PREDICATE(ext) \ > diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode > index 1d86f3a012..b149f13018 100644 > --- a/target/riscv/xthead.decode > +++ b/target/riscv/xthead.decode > @@ -2,6 +2,7 @@ > # Translation routines for the instructions of the XThead* ISA extension= s > # > # Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu > +# Dr. Philipp Tomsich, philipp.tomsich@vrull.eu > # > # SPDX-License-Identifier: LGPL-2.1-or-later > # > @@ -9,12 +10,33 @@ > # https://github.com/T-head-Semi/thead-extension-spec/releases/latest > > # Fields: > +%rd 7:5 > %rs1 15:5 > %rs2 20:5 > > +# Argument sets > +&r rd rs1 rs2 !extern > + > # Formats > @sfence_vm ....... ..... ..... ... ..... ....... %rs1 > @rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 > +@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd > + > +# XTheadBa > +# Instead of defining a new encoding, we simply use the decoder to > +# extract the imm[0:1] field and dispatch to separate translation > +# functions (mirroring the `sh[123]add` instructions from Zba and > +# the regular RVI `add` instruction. > +# > +# The only difference between sh[123]add and addsl is that the shift > +# is applied to rs1 (for addsl) instead of rs2 (for sh[123]add). > +# > +# Note that shift-by-0 is a valid operation according to the manual. > +# This will be equivalent to a regular add. > +add 0000000 ..... ..... 001 ..... 0001011 @r > +th_addsl1 0000001 ..... ..... 001 ..... 0001011 @r > +th_addsl2 0000010 ..... ..... 001 ..... 0001011 @r > +th_addsl3 0000011 ..... ..... 001 ..... 0001011 @r > > # XTheadCmo > th_dcache_call 0000000 00001 00000 000 00000 0001011 > -- > 2.38.1 > > From MAILER-DAEMON Mon Jan 23 17:58:07 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK5lP-0002g0-3j for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 17:58:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK5lN-0002fm-Op; Mon, 23 Jan 2023 17:58:05 -0500 Received: from mail-vk1-xa2c.google.com ([2607:f8b0:4864:20::a2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) 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<20221223180016.2068508-5-christoph.muellner@vrull.eu> In-Reply-To: <20221223180016.2068508-5-christoph.muellner@vrull.eu> From: Alistair Francis Date: Tue, 24 Jan 2023 08:57:35 +1000 Message-ID: Subject: Re: [PATCH v2 04/15] RISC-V: Adding XTheadBb ISA extension To: Christoph Muellner Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a2c; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 22:58:06 -0000 On Sat, Dec 24, 2022 at 4:02 AM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > This patch adds support for the XTheadBb ISA extension. > The patch uses the T-Head specific decoder and translation. > > Changes in v2: > - Add ISA_EXT_DATA_ENTRY() > - Split XtheadB* extension into individual commits > - Make implementation compatible with RV32. > - Use single decoder for XThead extensions > > Co-developed-by: Philipp Tomsich > Co-developed-by: LIU Zhiwei > Signed-off-by: Christoph M=C3=BCllner Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 2 + > target/riscv/cpu.h | 1 + > target/riscv/insn_trans/trans_xthead.c.inc | 124 +++++++++++++++++++++ > target/riscv/translate.c | 4 +- > target/riscv/xthead.decode | 20 ++++ > 5 files changed, 149 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 809b6eb4ed..b5285fb7a7 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -109,6 +109,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D = { > ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), > ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), > ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba= ), > + ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb= ), > ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadc= mo), > ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xthead= sync), > ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_X= VentanaCondOps), > @@ -1064,6 +1065,7 @@ static Property riscv_cpu_extensions[] =3D { > > /* Vendor-specific custom extensions */ > DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), > + DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), > DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), > DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), > DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOp= s, false), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index ec2588a0f0..0ac1d3f5ef 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -466,6 +466,7 @@ struct RISCVCPUConfig { > > /* Vendor-specific custom extensions */ > bool ext_xtheadba; > + bool ext_xtheadbb; > bool ext_xtheadcmo; > bool ext_xtheadsync; > bool ext_XVentanaCondOps; > diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/in= sn_trans/trans_xthead.c.inc > index 79e1f5bde9..a55d1491fa 100644 > --- a/target/riscv/insn_trans/trans_xthead.c.inc > +++ b/target/riscv/insn_trans/trans_xthead.c.inc > @@ -22,6 +22,12 @@ > } \ > } while (0) > > +#define REQUIRE_XTHEADBB(ctx) do { \ > + if (!ctx->cfg_ptr->ext_xtheadbb) { \ > + return false; \ > + } \ > +} while (0) > + > #define REQUIRE_XTHEADCMO(ctx) do { \ > if (!ctx->cfg_ptr->ext_xtheadcmo) { \ > return false; \ > @@ -67,6 +73,124 @@ GEN_TRANS_TH_ADDSL(1) > GEN_TRANS_TH_ADDSL(2) > GEN_TRANS_TH_ADDSL(3) > > +/* XTheadBb */ > + > +/* th.srri is an alternate encoding for rori (from Zbb) */ > +static bool trans_th_srri(DisasContext *ctx, arg_th_srri * a) > +{ > + REQUIRE_XTHEADBB(ctx); > + return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE, > + tcg_gen_rotri_tl, gen_roriw, NULL); > +} > + > +/* th.srriw is an alternate encoding for roriw (from Zbb) */ > +static bool trans_th_srriw(DisasContext *ctx, arg_th_srriw *a) > +{ > + REQUIRE_XTHEADBB(ctx); > + REQUIRE_64BIT(ctx); > + ctx->ol =3D MXL_RV32; > + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL); > +} > + > +/* th.ext and th.extu perform signed/unsigned bitfield extraction */ > +static bool gen_th_bfextract(DisasContext *ctx, arg_th_bfext *a, > + void (*f)(TCGv, TCGv, unsigned int, unsigne= d int)) > +{ > + TCGv dest =3D dest_gpr(ctx, a->rd); > + TCGv source =3D get_gpr(ctx, a->rs1, EXT_ZERO); > + > + if (a->lsb <=3D a->msb) { > + f(dest, source, a->lsb, a->msb - a->lsb + 1); > + gen_set_gpr(ctx, a->rd, dest); > + } > + return true; > +} > + > +static bool trans_th_ext(DisasContext *ctx, arg_th_ext *a) > +{ > + REQUIRE_XTHEADBB(ctx); > + return gen_th_bfextract(ctx, a, tcg_gen_sextract_tl); > +} > + > +static bool trans_th_extu(DisasContext *ctx, arg_th_extu *a) > +{ > + REQUIRE_XTHEADBB(ctx); > + return gen_th_bfextract(ctx, a, tcg_gen_extract_tl); > +} > + > +/* th.ff0: find first zero (clz on an inverted input) */ > +static bool gen_th_ff0(DisasContext *ctx, arg_th_ff0 *a, DisasExtend ext= ) > +{ > + TCGv dest =3D dest_gpr(ctx, a->rd); > + TCGv src1 =3D get_gpr(ctx, a->rs1, ext); > + > + int olen =3D get_olen(ctx); > + TCGv t =3D tcg_temp_new(); > + > + tcg_gen_not_tl(t, src1); > + if (olen !=3D TARGET_LONG_BITS) { > + if (olen =3D=3D 32) { > + gen_clzw(dest, t); > + } else { > + g_assert_not_reached(); > + } > + } else { > + gen_clz(dest, t); > + } > + > + tcg_temp_free(t); > + gen_set_gpr(ctx, a->rd, dest); > + > + return true; > +} > + > +static bool trans_th_ff0(DisasContext *ctx, arg_th_ff0 *a) > +{ > + REQUIRE_XTHEADBB(ctx); > + return gen_th_ff0(ctx, a, EXT_NONE); > +} > + > +/* th.ff1 is an alternate encoding for clz (from Zbb) */ > +static bool trans_th_ff1(DisasContext *ctx, arg_th_ff1 *a) > +{ > + REQUIRE_XTHEADBB(ctx); > + return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw); > +} > + > +static void gen_th_revw(TCGv ret, TCGv arg1) > +{ > + tcg_gen_bswap32_tl(ret, arg1, TCG_BSWAP_OS); > +} > + > +/* th.rev is an alternate encoding for the RV64 rev8 (from Zbb) */ > +static bool trans_th_rev(DisasContext *ctx, arg_th_rev *a) > +{ > + REQUIRE_XTHEADBB(ctx); > + > + return gen_unary_per_ol(ctx, a, EXT_NONE, tcg_gen_bswap_tl, gen_th_r= evw); > +} > + > +/* th.revw is a sign-extended byte-swap of the lower word */ > +static bool trans_th_revw(DisasContext *ctx, arg_th_revw *a) > +{ > + REQUIRE_XTHEADBB(ctx); > + REQUIRE_64BIT(ctx); > + return gen_unary(ctx, a, EXT_NONE, gen_th_revw); > +} > + > +/* th.tstnbz is equivalent to an orc.b (from Zbb) with inverted result *= / > +static void gen_th_tstnbz(TCGv ret, TCGv source1) > +{ > + gen_orc_b(ret, source1); > + tcg_gen_not_tl(ret, ret); > +} > + > +static bool trans_th_tstnbz(DisasContext *ctx, arg_th_tstnbz *a) > +{ > + REQUIRE_XTHEADBB(ctx); > + return gen_unary(ctx, a, EXT_ZERO, gen_th_tstnbz); > +} > + > /* XTheadCmo */ > > static inline int priv_level(DisasContext *ctx) > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 7b35f1d71b..8439ff0bf4 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -127,8 +127,8 @@ static bool always_true_p(DisasContext *ctx __attrib= ute__((__unused__))) > > static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) > { > - return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadcmo || > - ctx->cfg_ptr->ext_xtheadsync; > + return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || > + ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; > } > > #define MATERIALISE_EXT_PREDICATE(ext) \ > diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode > index b149f13018..8cd140891b 100644 > --- a/target/riscv/xthead.decode > +++ b/target/riscv/xthead.decode > @@ -13,14 +13,23 @@ > %rd 7:5 > %rs1 15:5 > %rs2 20:5 > +%sh5 20:5 > +%sh6 20:6 > > # Argument sets > &r rd rs1 rs2 !extern > +&r2 rd rs1 !extern > +&shift shamt rs1 rd !extern > +&th_bfext msb lsb rs1 rd > > # Formats > @sfence_vm ....... ..... ..... ... ..... ....... %rs1 > @rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 > @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd > +@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd > +@th_bfext msb:6 lsb:6 ..... ... ..... ....... &th_bfext %rs1 %rd > +@sh5 ....... ..... ..... ... ..... ....... &shift shamt=3D%sh5= %rs1 %rd > +@sh6 ...... ...... ..... ... ..... ....... &shift shamt=3D%sh6 = %rs1 %rd > > # XTheadBa > # Instead of defining a new encoding, we simply use the decoder to > @@ -38,6 +47,17 @@ th_addsl1 0000001 ..... ..... 001 ..... 0001011= @r > th_addsl2 0000010 ..... ..... 001 ..... 0001011 @r > th_addsl3 0000011 ..... ..... 001 ..... 0001011 @r > > +# XTheadBb > +th_ext ...... ...... ..... 010 ..... 0001011 @th_bfext > +th_extu ...... ...... ..... 011 ..... 0001011 @th_bfext > +th_ff0 1000010 00000 ..... 001 ..... 0001011 @r2 > +th_ff1 1000011 00000 ..... 001 ..... 0001011 @r2 > +th_srri 000100 ...... ..... 001 ..... 0001011 @sh6 > +th_srriw 0001010 ..... ..... 001 ..... 0001011 @sh5 > +th_rev 1000001 00000 ..... 001 ..... 0001011 @r2 > +th_revw 1001000 00000 ..... 001 ..... 0001011 @r2 > +th_tstnbz 1000000 00000 ..... 001 ..... 0001011 @r2 > + > # XTheadCmo > th_dcache_call 0000000 00001 00000 000 00000 0001011 > th_dcache_ciall 0000000 00011 00000 000 00000 0001011 > -- > 2.38.1 > > From MAILER-DAEMON Mon Jan 23 17:58:50 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK5m4-0003Kj-FZ for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 17:58:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK5m2-0003I2-DN; Mon, 23 Jan 2023 17:58:46 -0500 Received: from mail-vs1-xe2c.google.com ([2607:f8b0:4864:20::e2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK5ly-0007x4-SA; Mon, 23 Jan 2023 17:58:45 -0500 Received: by mail-vs1-xe2c.google.com with SMTP id q125so14796928vsb.0; Mon, 23 Jan 2023 14:58:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; 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qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e2c; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 22:58:46 -0000 On Sat, Dec 24, 2022 at 4:01 AM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > This patch adds support for the XTheadBs ISA extension. > The patch uses the T-Head specific decoder and translation. > > Changes in v2: > - Add ISA_EXT_DATA_ENTRY() > - Split XtheadB* extension into individual commits > - Use single decoder for XThead extensions > > Co-developed-by: Philipp Tomsich > Co-developed-by: LIU Zhiwei > Signed-off-by: Christoph M=C3=BCllner Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 2 ++ > target/riscv/cpu.h | 1 + > target/riscv/insn_trans/trans_xthead.c.inc | 15 +++++++++++++++ > target/riscv/translate.c | 3 ++- > target/riscv/xthead.decode | 3 +++ > 5 files changed, 23 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index b5285fb7a7..17273425a8 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -110,6 +110,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D = { > ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), > ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba= ), > ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb= ), > + ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs= ), > ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadc= mo), > ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xthead= sync), > ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_X= VentanaCondOps), > @@ -1066,6 +1067,7 @@ static Property riscv_cpu_extensions[] =3D { > /* Vendor-specific custom extensions */ > DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), > DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), > + DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), > DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), > DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), > DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOp= s, false), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 0ac1d3f5ef..5f68cb1e1e 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -467,6 +467,7 @@ struct RISCVCPUConfig { > /* Vendor-specific custom extensions */ > bool ext_xtheadba; > bool ext_xtheadbb; > + bool ext_xtheadbs; > bool ext_xtheadcmo; > bool ext_xtheadsync; > bool ext_XVentanaCondOps; > diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/in= sn_trans/trans_xthead.c.inc > index a55d1491fa..fb1f2c5731 100644 > --- a/target/riscv/insn_trans/trans_xthead.c.inc > +++ b/target/riscv/insn_trans/trans_xthead.c.inc > @@ -28,6 +28,12 @@ > } \ > } while (0) > > +#define REQUIRE_XTHEADBS(ctx) do { \ > + if (!ctx->cfg_ptr->ext_xtheadbs) { \ > + return false; \ > + } \ > +} while (0) > + > #define REQUIRE_XTHEADCMO(ctx) do { \ > if (!ctx->cfg_ptr->ext_xtheadcmo) { \ > return false; \ > @@ -191,6 +197,15 @@ static bool trans_th_tstnbz(DisasContext *ctx, arg_t= h_tstnbz *a) > return gen_unary(ctx, a, EXT_ZERO, gen_th_tstnbz); > } > > +/* XTheadBs */ > + > +/* th.tst is an alternate encoding for bexti (from Zbs) */ > +static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a) > +{ > + REQUIRE_XTHEADBS(ctx); > + return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext); > +} > + > /* XTheadCmo */ > > static inline int priv_level(DisasContext *ctx) > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 8439ff0bf4..fc326e0a79 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -128,7 +128,8 @@ static bool always_true_p(DisasContext *ctx __attrib= ute__((__unused__))) > static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) > { > return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || > - ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; > + ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || > + ctx->cfg_ptr->ext_xtheadsync; > } > > #define MATERIALISE_EXT_PREDICATE(ext) \ > diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode > index 8cd140891b..8494805611 100644 > --- a/target/riscv/xthead.decode > +++ b/target/riscv/xthead.decode > @@ -58,6 +58,9 @@ th_rev 1000001 00000 ..... 001 ..... 0001011 = @r2 > th_revw 1001000 00000 ..... 001 ..... 0001011 @r2 > th_tstnbz 1000000 00000 ..... 001 ..... 0001011 @r2 > > +# XTheadBs > +th_tst 100010 ...... ..... 001 ..... 0001011 @sh6 > + > # XTheadCmo > th_dcache_call 0000000 00001 00000 000 00000 0001011 > th_dcache_ciall 0000000 00011 00000 000 00000 0001011 > -- > 2.38.1 > > From MAILER-DAEMON Mon Jan 23 17:59:37 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK5mr-00042P-9d for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 17:59:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 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j36-20020a056122092400b003d55f93053fmr3397568vka.7.1674514772479; Mon, 23 Jan 2023 14:59:32 -0800 (PST) MIME-Version: 1.0 References: <20221223180016.2068508-1-christoph.muellner@vrull.eu> <20221223180016.2068508-7-christoph.muellner@vrull.eu> In-Reply-To: <20221223180016.2068508-7-christoph.muellner@vrull.eu> From: Alistair Francis Date: Tue, 24 Jan 2023 08:59:06 +1000 Message-ID: Subject: Re: [PATCH v2 06/15] RISC-V: Adding XTheadCondMov ISA extension To: Christoph Muellner Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a2c; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 22:59:36 -0000 On Sat, Dec 24, 2022 at 4:08 AM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > This patch adds support for the XTheadCondMov ISA extension. > The patch uses the T-Head specific decoder and translation. > > Changes in v2: > - Add ISA_EXT_DATA_ENTRY() > - Fix invalid use of register from dest_gpr() > - Use single decoder for XThead extensions > > Co-developed-by: LIU Zhiwei > Signed-off-by: Christoph M=C3=BCllner Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 2 ++ > target/riscv/cpu.h | 1 + > target/riscv/insn_trans/trans_xthead.c.inc | 35 ++++++++++++++++++++++ > target/riscv/translate.c | 2 +- > target/riscv/xthead.decode | 4 +++ > 5 files changed, 43 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 17273425a8..36a53784dd 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -112,6 +112,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D = { > ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb= ), > ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs= ), > ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadc= mo), > + ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xth= eadcondmov), > ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xthead= sync), > ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_X= VentanaCondOps), > }; > @@ -1069,6 +1070,7 @@ static Property riscv_cpu_extensions[] =3D { > DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), > DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), > DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), > + DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, f= alse), > DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), > DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOp= s, false), > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 5f68cb1e1e..01f035d8e9 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -469,6 +469,7 @@ struct RISCVCPUConfig { > bool ext_xtheadbb; > bool ext_xtheadbs; > bool ext_xtheadcmo; > + bool ext_xtheadcondmov; > bool ext_xtheadsync; > bool ext_XVentanaCondOps; > > diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/in= sn_trans/trans_xthead.c.inc > index fb1f2c5731..bf549bbd74 100644 > --- a/target/riscv/insn_trans/trans_xthead.c.inc > +++ b/target/riscv/insn_trans/trans_xthead.c.inc > @@ -40,6 +40,12 @@ > } \ > } while (0) > > +#define REQUIRE_XTHEADCONDMOV(ctx) do { \ > + if (!ctx->cfg_ptr->ext_xtheadcondmov) { \ > + return false; \ > + } \ > +} while (0) > + > #define REQUIRE_XTHEADSYNC(ctx) do { \ > if (!ctx->cfg_ptr->ext_xtheadsync) { \ > return false; \ > @@ -272,6 +278,35 @@ NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, RE= QUIRE_PRIV_MHS) > NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > > +/* XTheadCondMov */ > + > +static bool gen_th_condmove(DisasContext *ctx, arg_r *a, TCGCond cond) > +{ > + TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_NONE); > + TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); > + TCGv old =3D get_gpr(ctx, a->rd, EXT_NONE); > + TCGv dest =3D dest_gpr(ctx, a->rd); > + > + tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, old); > + > + gen_set_gpr(ctx, a->rd, dest); > + return true; > +} > + > +/* th.mveqz: "if (rs2 =3D=3D 0) rd =3D rs1;" */ > +static bool trans_th_mveqz(DisasContext *ctx, arg_th_mveqz *a) > +{ > + REQUIRE_XTHEADCONDMOV(ctx); > + return gen_th_condmove(ctx, a, TCG_COND_EQ); > +} > + > +/* th.mvnez: "if (rs2 !=3D 0) rd =3D rs1;" */ > +static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a) > +{ > + REQUIRE_XTHEADCONDMOV(ctx); > + return gen_th_condmove(ctx, a, TCG_COND_NE); > +} > + > /* XTheadSync */ > > static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *= a) > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index fc326e0a79..f15883b16b 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -129,7 +129,7 @@ static bool has_xthead_p(DisasContext *ctx __attribu= te__((__unused__))) > { > return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || > ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || > - ctx->cfg_ptr->ext_xtheadsync; > + ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadsy= nc; > } > > #define MATERIALISE_EXT_PREDICATE(ext) \ > diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode > index 8494805611..a8ebd8a18b 100644 > --- a/target/riscv/xthead.decode > +++ b/target/riscv/xthead.decode > @@ -84,6 +84,10 @@ th_l2cache_call 0000000 10101 00000 000 00000 0001011 > th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 > th_l2cache_iall 0000000 10110 00000 000 00000 0001011 > > +# XTheadCondMov > +th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r > +th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r > + > # XTheadSync > th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s > th_sync 0000000 11000 00000 000 00000 0001011 > -- > 2.38.1 > > From MAILER-DAEMON Mon Jan 23 18:00:48 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK5nw-0004n8-MY for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 18:00:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps 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AMrXdXtxpbDMsv2wAgnyZMGI80W9OsZD0/h0DlEMTMArTmdPxvMugViOlASm4sEScZuLA/IRAzVoq4dXE5x49pT+OOc= X-Received: by 2002:a67:ba0c:0:b0:3ce:f2da:96a with SMTP id l12-20020a67ba0c000000b003cef2da096amr3058899vsn.64.1674514831651; Mon, 23 Jan 2023 15:00:31 -0800 (PST) MIME-Version: 1.0 References: <20221223180016.2068508-1-christoph.muellner@vrull.eu> <20221223180016.2068508-8-christoph.muellner@vrull.eu> In-Reply-To: <20221223180016.2068508-8-christoph.muellner@vrull.eu> From: Alistair Francis Date: Tue, 24 Jan 2023 09:00:05 +1000 Message-ID: Subject: Re: [PATCH v2 07/15] RISC-V: Adding T-Head multiply-accumulate instructions To: Christoph Muellner Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e2d; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2d.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 23:00:43 -0000 On Sat, Dec 24, 2022 at 4:04 AM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > This patch adds support for the T-Head MAC instructions. > The patch uses the T-Head specific decoder and translation. > > Changes in v2: > - Add ISA_EXT_DATA_ENTRY() > - Use single decoder for XThead extensions > > Co-developed-by: LIU Zhiwei > Signed-off-by: Christoph M=C3=BCllner Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 2 + > target/riscv/cpu.h | 1 + > target/riscv/insn_trans/trans_xthead.c.inc | 83 ++++++++++++++++++++++ > target/riscv/translate.c | 3 +- > target/riscv/xthead.decode | 8 +++ > 5 files changed, 96 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 36a53784dd..88ad2138db 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -113,6 +113,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D = { > ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs= ), > ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadc= mo), > ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xth= eadcondmov), > + ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadm= ac), > ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xthead= sync), > ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_X= VentanaCondOps), > }; > @@ -1071,6 +1072,7 @@ static Property riscv_cpu_extensions[] =3D { > DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), > DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), > DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, f= alse), > + DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), > DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), > DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOp= s, false), > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 01f035d8e9..92198be9d8 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -470,6 +470,7 @@ struct RISCVCPUConfig { > bool ext_xtheadbs; > bool ext_xtheadcmo; > bool ext_xtheadcondmov; > + bool ext_xtheadmac; > bool ext_xtheadsync; > bool ext_XVentanaCondOps; > > diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/in= sn_trans/trans_xthead.c.inc > index bf549bbd74..109be58c9b 100644 > --- a/target/riscv/insn_trans/trans_xthead.c.inc > +++ b/target/riscv/insn_trans/trans_xthead.c.inc > @@ -46,6 +46,12 @@ > } \ > } while (0) > > +#define REQUIRE_XTHEADMAC(ctx) do { \ > + if (!ctx->cfg_ptr->ext_xtheadmac) { \ > + return false; \ > + } \ > +} while (0) > + > #define REQUIRE_XTHEADSYNC(ctx) do { \ > if (!ctx->cfg_ptr->ext_xtheadsync) { \ > return false; \ > @@ -307,6 +313,83 @@ static bool trans_th_mvnez(DisasContext *ctx, arg_th= _mveqz *a) > return gen_th_condmove(ctx, a, TCG_COND_NE); > } > > +/* XTheadMac */ > + > +static bool gen_th_mac(DisasContext *ctx, arg_r *a, > + void (*accumulate_func)(TCGv, TCGv, TCGv), > + void (*extend_operand_func)(TCGv, TCGv)) > +{ > + TCGv dest =3D dest_gpr(ctx, a->rd); > + TCGv src0 =3D get_gpr(ctx, a->rd, EXT_NONE); > + TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_NONE); > + TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); > + TCGv tmp =3D tcg_temp_new(); > + > + if (extend_operand_func) { > + TCGv tmp2 =3D tcg_temp_new(); > + extend_operand_func(tmp, src1); > + extend_operand_func(tmp2, src2); > + tcg_gen_mul_tl(tmp, tmp, tmp2); > + tcg_temp_free(tmp2); > + } else { > + tcg_gen_mul_tl(tmp, src1, src2); > + } > + > + accumulate_func(dest, src0, tmp); > + gen_set_gpr(ctx, a->rd, dest); > + tcg_temp_free(tmp); > + > + return true; > +} > + > +/* th.mula: "rd =3D rd + rs1 * rs2" */ > +static bool trans_th_mula(DisasContext *ctx, arg_th_mula *a) > +{ > + REQUIRE_XTHEADMAC(ctx); > + return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL); > +} > + > +/* th.mulah: "rd =3D sext.w(rd + sext.w(rs1[15:0]) * sext.w(rs2[15:0]))"= */ > +static bool trans_th_mulah(DisasContext *ctx, arg_th_mulah *a) > +{ > + REQUIRE_XTHEADMAC(ctx); > + ctx->ol =3D MXL_RV32; > + return gen_th_mac(ctx, a, tcg_gen_add_tl, tcg_gen_ext16s_tl); > +} > + > +/* th.mulaw: "rd =3D sext.w(rd + rs1 * rs2)" */ > +static bool trans_th_mulaw(DisasContext *ctx, arg_th_mulaw *a) > +{ > + REQUIRE_XTHEADMAC(ctx); > + REQUIRE_64BIT(ctx); > + ctx->ol =3D MXL_RV32; > + return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL); > +} > + > +/* th.muls: "rd =3D rd - rs1 * rs2" */ > +static bool trans_th_muls(DisasContext *ctx, arg_th_muls *a) > +{ > + REQUIRE_XTHEADMAC(ctx); > + return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); > +} > + > +/* th.mulsh: "rd =3D sext.w(rd - sext.w(rs1[15:0]) * sext.w(rs2[15:0]))"= */ > +static bool trans_th_mulsh(DisasContext *ctx, arg_th_mulsh *a) > +{ > + REQUIRE_XTHEADMAC(ctx); > + ctx->ol =3D MXL_RV32; > + return gen_th_mac(ctx, a, tcg_gen_sub_tl, tcg_gen_ext16s_tl); > +} > + > +/* th.mulsw: "rd =3D sext.w(rd - rs1 * rs2)" */ > +static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a) > +{ > + REQUIRE_XTHEADMAC(ctx); > + REQUIRE_64BIT(ctx); > + ctx->ol =3D MXL_RV32; > + return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); > +} > + > /* XTheadSync */ > > static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *= a) > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index f15883b16b..36f512baa8 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -129,7 +129,8 @@ static bool has_xthead_p(DisasContext *ctx __attribu= te__((__unused__))) > { > return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || > ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || > - ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadsy= nc; > + ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadma= c || > + ctx->cfg_ptr->ext_xtheadsync; > } > > #define MATERIALISE_EXT_PREDICATE(ext) \ > diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode > index a8ebd8a18b..696de6cecf 100644 > --- a/target/riscv/xthead.decode > +++ b/target/riscv/xthead.decode > @@ -88,6 +88,14 @@ th_l2cache_iall 0000000 10110 00000 000 00000 0001011 > th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r > th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r > > +# XTheadMac > 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<20221223180016.2068508-9-christoph.muellner@vrull.eu> In-Reply-To: <20221223180016.2068508-9-christoph.muellner@vrull.eu> From: Alistair Francis Date: Tue, 24 Jan 2023 09:03:12 +1000 Message-ID: Subject: Re: [PATCH v2 08/15] RISC-V: Adding T-Head MemPair extension To: Christoph Muellner Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a31; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa31.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 23:03:46 -0000 On Sat, Dec 24, 2022 at 4:01 AM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > This patch adds support for the T-Head MemPair instructions. > The patch uses the T-Head specific decoder and translation. > > Changes in v2: > - Add ISA_EXT_DATA_ENTRY() > - Use single decoder for XThead extensions > - Use get_address() to calculate addresses > > Co-developed-by: LIU Zhiwei > Signed-off-by: Christoph M=C3=BCllner Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 2 + > target/riscv/cpu.h | 1 + > target/riscv/insn_trans/trans_xthead.c.inc | 88 ++++++++++++++++++++++ > target/riscv/translate.c | 2 +- > target/riscv/xthead.decode | 13 ++++ > 5 files changed, 105 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 88ad2138db..de00f69710 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D = { > ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadc= mo), > ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xth= eadcondmov), > ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadm= ac), > + ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xth= eadmempair), > ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xthead= sync), > ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_X= VentanaCondOps), > }; > @@ -1073,6 +1074,7 @@ static Property riscv_cpu_extensions[] =3D { > DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), > DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, f= alse), > DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), > + DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, f= alse), > DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), > DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOp= s, false), > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 92198be9d8..836445115e 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -471,6 +471,7 @@ struct RISCVCPUConfig { > bool ext_xtheadcmo; > bool ext_xtheadcondmov; > bool ext_xtheadmac; > + bool ext_xtheadmempair; > bool ext_xtheadsync; > bool ext_XVentanaCondOps; > > diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/in= sn_trans/trans_xthead.c.inc > index 109be58c9b..49314306eb 100644 > --- a/target/riscv/insn_trans/trans_xthead.c.inc > +++ b/target/riscv/insn_trans/trans_xthead.c.inc > @@ -52,6 +52,12 @@ > } \ > } while (0) > > +#define REQUIRE_XTHEADMEMPAIR(ctx) do { \ > + if (!ctx->cfg_ptr->ext_xtheadmempair) { \ > + return false; \ > + } \ > +} while (0) > + > #define REQUIRE_XTHEADSYNC(ctx) do { \ > if (!ctx->cfg_ptr->ext_xtheadsync) { \ > return false; \ > @@ -390,6 +396,88 @@ static bool trans_th_mulsw(DisasContext *ctx, arg_th= _mulsw *a) > return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); > } > > +/* XTheadMemPair */ > + > +static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp mem= op, > + int shamt) > +{ > + TCGv rd1 =3D dest_gpr(ctx, a->rd1); > + TCGv rd2 =3D dest_gpr(ctx, a->rd2); > + TCGv addr1 =3D tcg_temp_new(); > + TCGv addr2 =3D tcg_temp_new(); > + > + addr1 =3D get_address(ctx, a->rs, a->sh2 << shamt); > + if ((memop & MO_SIZE) =3D=3D MO_64) { > + addr2 =3D get_address(ctx, a->rs, 8 + (a->sh2 << shamt)); > + } else { > + addr2 =3D get_address(ctx, a->rs, 4 + (a->sh2 << shamt)); > + } > + > + tcg_gen_qemu_ld_tl(rd1, addr1, ctx->mem_idx, memop); > + tcg_gen_qemu_ld_tl(rd2, addr2, ctx->mem_idx, memop); > + gen_set_gpr(ctx, a->rd1, rd1); > + gen_set_gpr(ctx, a->rd2, rd2); > + > + tcg_temp_free(addr1); > + tcg_temp_free(addr2); > + return true; > +} > + > +static bool trans_th_ldd(DisasContext *ctx, arg_th_pair *a) > +{ > + REQUIRE_XTHEADMEMPAIR(ctx); > + REQUIRE_64BIT(ctx); > + return gen_loadpair_tl(ctx, a, MO_TESQ, 4); > +} > + > +static bool trans_th_lwd(DisasContext *ctx, arg_th_pair *a) > +{ > + REQUIRE_XTHEADMEMPAIR(ctx); > + return gen_loadpair_tl(ctx, a, MO_TESL, 3); > +} > + > +static bool trans_th_lwud(DisasContext *ctx, arg_th_pair *a) > +{ > + REQUIRE_XTHEADMEMPAIR(ctx); > + return gen_loadpair_tl(ctx, a, MO_TEUL, 3); > +} > + > +static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp me= mop, > + int shamt) > +{ > + TCGv data1 =3D get_gpr(ctx, a->rd1, EXT_NONE); > + TCGv data2 =3D get_gpr(ctx, a->rd2, EXT_NONE); > + TCGv addr1 =3D tcg_temp_new(); > + TCGv addr2 =3D tcg_temp_new(); > + > + addr1 =3D get_address(ctx, a->rs, a->sh2 << shamt); > + if ((memop & MO_SIZE) =3D=3D MO_64) { > + addr2 =3D get_address(ctx, a->rs, 8 + (a->sh2 << shamt)); > + } else { > + addr2 =3D get_address(ctx, a->rs, 4 + (a->sh2 << shamt)); > + } > + > + tcg_gen_qemu_st_tl(data1, addr1, ctx->mem_idx, memop); > + tcg_gen_qemu_st_tl(data2, addr2, ctx->mem_idx, memop); > + > + tcg_temp_free(addr1); > + tcg_temp_free(addr2); > + return true; > +} > + > +static bool trans_th_sdd(DisasContext *ctx, arg_th_pair *a) > +{ > + REQUIRE_XTHEADMEMPAIR(ctx); > + REQUIRE_64BIT(ctx); > + return gen_storepair_tl(ctx, a, MO_TESQ, 4); > +} > + > +static bool trans_th_swd(DisasContext *ctx, arg_th_pair *a) > +{ > + REQUIRE_XTHEADMEMPAIR(ctx); > + return gen_storepair_tl(ctx, a, MO_TESL, 3); > +} > + > /* XTheadSync */ > > static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *= a) > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 36f512baa8..348fe511e1 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -130,7 +130,7 @@ static bool has_xthead_p(DisasContext *ctx __attribu= te__((__unused__))) > return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || > ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || > ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadma= c || > - ctx->cfg_ptr->ext_xtheadsync; > + ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsy= nc; > } > > #define MATERIALISE_EXT_PREDICATE(ext) \ > diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode > index 696de6cecf..ff2a83b56d 100644 > --- a/target/riscv/xthead.decode > +++ b/target/riscv/xthead.decode > @@ -11,16 +11,21 @@ > > # Fields: > %rd 7:5 > +%rd1 7:5 > +%rs 15:5 > %rs1 15:5 > +%rd2 20:5 > %rs2 20:5 > %sh5 20:5 > %sh6 20:6 > +%sh2 25:2 > > # Argument sets > &r rd rs1 rs2 !extern > &r2 rd rs1 !extern > &shift shamt rs1 rd !extern > &th_bfext msb lsb rs1 rd > +&th_pair rd1 rs rd2 sh2 > > # Formats > @sfence_vm ....... ..... ..... ... ..... ....... %rs1 > @@ -30,6 +35,7 @@ > @th_bfext msb:6 lsb:6 ..... ... ..... ....... &th_bfext %rs1 %rd > @sh5 ....... ..... ..... ... ..... ....... &shift shamt=3D%sh5= %rs1 %rd > @sh6 ...... ...... ..... ... ..... ....... &shift shamt=3D%sh6 = %rs1 %rd > +@th_pair ..... .. ..... ..... ... ..... ....... &th_pair %rd1 %rs %r= d2 %sh2 > > # XTheadBa > # Instead of defining a new encoding, we simply use the decoder to > @@ -96,6 +102,13 @@ th_muls 00100 01 ..... ..... 001 ..... 00010= 11 @r > th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r > th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r > > +# XTheadMemPair > +th_ldd 11111 .. ..... ..... 100 ..... 0001011 @th_pair > +th_lwd 11100 .. ..... ..... 100 ..... 0001011 @th_pair > +th_lwud 11110 .. ..... ..... 100 ..... 0001011 @th_pair > +th_sdd 11111 .. ..... ..... 101 ..... 0001011 @th_pair > +th_swd 11100 .. ..... ..... 101 ..... 0001011 @th_pair > + > # XTheadSync > th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s > th_sync 0000000 11000 00000 000 00000 0001011 > -- > 2.38.1 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Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e32; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe32.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 23:04:58 -0000 On Sat, Dec 24, 2022 at 4:04 AM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > This patch adds support for the T-Head MemIdx instructions. > The patch uses the T-Head specific decoder and translation. > > Changes in v2: > - Add ISA_EXT_DATA_ENTRY() > - Use single decoder for XThead extensions > - Avoid signed-bitfield-extraction by using signed immediate field imm5 > - Use get_address() to calculate addresses > - Introduce helper get_th_address_indexed for rs1+(rs2< - Introduce get_address_indexed() for register offsets (like get_address(= )) > > Co-developed-by: LIU Zhiwei > Signed-off-by: Christoph M=C3=BCllner Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 2 + > target/riscv/cpu.h | 1 + > target/riscv/insn_trans/trans_xthead.c.inc | 377 +++++++++++++++++++++ > target/riscv/translate.c | 21 +- > target/riscv/xthead.decode | 54 +++ > 5 files changed, 454 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index de00f69710..1fbfb7ccc3 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D = { > ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadc= mo), > ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xth= eadcondmov), > ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadm= ac), > + ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xthe= admemidx), > ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xth= eadmempair), > ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xthead= sync), > ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_X= VentanaCondOps), > @@ -1074,6 +1075,7 @@ static Property riscv_cpu_extensions[] =3D { > DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), > DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, f= alse), > DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), > + DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, fal= se), > DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, f= alse), > DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), > DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOp= s, false), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 836445115e..965dc46591 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -471,6 +471,7 @@ struct RISCVCPUConfig { > bool ext_xtheadcmo; > bool ext_xtheadcondmov; > bool ext_xtheadmac; > + bool ext_xtheadmemidx; > bool ext_xtheadmempair; > bool ext_xtheadsync; > bool ext_XVentanaCondOps; > diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/in= sn_trans/trans_xthead.c.inc > index 49314306eb..02b82ac327 100644 > --- a/target/riscv/insn_trans/trans_xthead.c.inc > +++ b/target/riscv/insn_trans/trans_xthead.c.inc > @@ -52,6 +52,12 @@ > } \ > } while (0) > > +#define REQUIRE_XTHEADMEMIDX(ctx) do { \ > + if (!ctx->cfg_ptr->ext_xtheadmemidx) { \ > + return false; \ > + } \ > +} while (0) > + > #define REQUIRE_XTHEADMEMPAIR(ctx) do { \ > if (!ctx->cfg_ptr->ext_xtheadmempair) { \ > return false; \ > @@ -64,6 +70,30 @@ > } \ > } while (0) > > +/* > + * Calculate and return the address for indexed mem operations: > + * If !zext_offs, then the address is rs1 + (rs2 << imm2). > + * If zext_offs, then the address is rs1 + (zext(rs2[31:0]) << imm2). > + */ > +static TCGv get_th_address_indexed(DisasContext *ctx, int rs1, int rs2, > + int imm2, bool zext_offs) > +{ > + TCGv src2 =3D get_gpr(ctx, rs2, EXT_NONE); > + TCGv offs =3D tcg_temp_new(); > + > + if (zext_offs) { > + tcg_gen_extract_tl(offs, src2, 0, 32); > + tcg_gen_shli_tl(offs, offs, imm2); > + } else { > + tcg_gen_shli_tl(offs, src2, imm2); > + } > + > + TCGv addr =3D get_address_indexed(ctx, rs1, offs); > + > + tcg_temp_free(offs); > + return addr; > +} > + > /* XTheadBa */ > > /* > @@ -396,6 +426,353 @@ static bool trans_th_mulsw(DisasContext *ctx, arg_t= h_mulsw *a) > return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); > } > > +/* XTheadMemIdx */ > + > +/* > + * Load with memop from indexed address and add (imm5 << imm2) to rs1. > + * If !preinc, then the load address is rs1. > + * If preinc, then the load address is rs1 + (imm5) << imm2). > + */ > +static bool gen_load_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memo= p, > + bool preinc) > +{ > + TCGv rd =3D dest_gpr(ctx, a->rd); > + TCGv addr =3D get_address(ctx, a->rs1, preinc ? a->imm5 << a->imm2 := 0); > + > + tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); > + addr =3D get_address(ctx, a->rs1, !preinc ? a->imm5 << a->imm2 : 0); > + gen_set_gpr(ctx, a->rd, rd); > + gen_set_gpr(ctx, a->rs1, addr); > + > + return true; > +} > + > +/* > + * Store with memop to indexed address and add (imm5 << imm2) to rs1. > + * If !preinc, then the store address is rs1. > + * If preinc, then the store address is rs1 + (imm5) << imm2). > + */ > +static bool gen_store_inc(DisasContext *ctx, arg_th_meminc *a, MemOp mem= op, > + bool preinc) > +{ > + TCGv data =3D get_gpr(ctx, a->rd, EXT_NONE); > + TCGv addr =3D get_address(ctx, a->rs1, preinc ? a->imm5 << a->imm2 := 0); > + > + tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); > + addr =3D get_address(ctx, a->rs1, !preinc ? a->imm5 << a->imm2 : 0); > + gen_set_gpr(ctx, a->rs1, addr); > + > + return true; > +} > + > +static bool trans_th_ldia(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + REQUIRE_64BIT(ctx); > + return gen_load_inc(ctx, a, MO_TESQ, false); > +} > + > +static bool trans_th_ldib(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + REQUIRE_64BIT(ctx); > + return gen_load_inc(ctx, a, MO_TESQ, true); > +} > + > +static bool trans_th_lwia(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_load_inc(ctx, a, MO_TESL, false); > +} > + > +static bool trans_th_lwib(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_load_inc(ctx, a, MO_TESL, true); > +} > + > +static bool trans_th_lwuia(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + REQUIRE_64BIT(ctx); > + return gen_load_inc(ctx, a, MO_TEUL, false); > +} > + > +static bool trans_th_lwuib(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + REQUIRE_64BIT(ctx); > + return gen_load_inc(ctx, a, MO_TEUL, true); > +} > + > +static bool trans_th_lhia(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_load_inc(ctx, a, MO_TESW, false); > +} > + > +static bool trans_th_lhib(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_load_inc(ctx, a, MO_TESW, true); > +} > + > +static bool trans_th_lhuia(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_load_inc(ctx, a, MO_TEUW, false); > +} > + > +static bool trans_th_lhuib(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_load_inc(ctx, a, MO_TEUW, true); > +} > + > +static bool trans_th_lbia(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_load_inc(ctx, a, MO_SB, false); > +} > + > +static bool trans_th_lbib(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_load_inc(ctx, a, MO_SB, true); > +} > + > +static bool trans_th_lbuia(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_load_inc(ctx, a, MO_UB, false); > +} > + > +static bool trans_th_lbuib(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_load_inc(ctx, a, MO_UB, true); > +} > + > +static bool trans_th_sdia(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + REQUIRE_64BIT(ctx); > + return gen_store_inc(ctx, a, MO_TESQ, false); > +} > + > +static bool trans_th_sdib(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + REQUIRE_64BIT(ctx); > + return gen_store_inc(ctx, a, MO_TESQ, true); > +} > + > +static bool trans_th_swia(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_store_inc(ctx, a, MO_TESL, false); > +} > + > +static bool trans_th_swib(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_store_inc(ctx, a, MO_TESL, true); > +} > + > +static bool trans_th_shia(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_store_inc(ctx, a, MO_TESW, false); > +} > + > +static bool trans_th_shib(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_store_inc(ctx, a, MO_TESW, true); > +} > + > +static bool trans_th_sbia(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_store_inc(ctx, a, MO_SB, false); > +} > + > +static bool trans_th_sbib(DisasContext *ctx, arg_th_meminc *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_store_inc(ctx, a, MO_SB, true); > +} > + > +/* > + * Load with memop from indexed address. > + * If !zext_offs, then address is rs1 + (rs2 << imm2). > + * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2). > + */ > +static bool gen_load_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memo= p, > + bool zext_offs) > +{ > + TCGv rd =3D dest_gpr(ctx, a->rd); > + TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, z= ext_offs); > + > + tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); > + gen_set_gpr(ctx, a->rd, rd); > + > + return true; > +} > + > +/* > + * Store with memop to indexed address. > + * If !zext_offs, then address is rs1 + (rs2 << imm2). > + * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2). > + */ > +static bool gen_store_idx(DisasContext *ctx, arg_th_memidx *a, MemOp mem= op, > + bool zext_offs) > +{ > + TCGv data =3D get_gpr(ctx, a->rd, EXT_NONE); > + TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, z= ext_offs); > + > + tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); > + > + return true; > +} > + > +static bool trans_th_lrd(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + REQUIRE_64BIT(ctx); > + return gen_load_idx(ctx, a, MO_TESQ, false); > +} > + > +static bool trans_th_lrw(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_load_idx(ctx, a, MO_TESL, false); > +} > + > +static bool trans_th_lrwu(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + REQUIRE_64BIT(ctx); > + return gen_load_idx(ctx, a, MO_TEUL, false); > +} > + > +static bool trans_th_lrh(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_load_idx(ctx, a, MO_TESW, false); > +} > + > +static bool trans_th_lrhu(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_load_idx(ctx, a, MO_TEUW, false); > +} > + > +static bool trans_th_lrb(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_load_idx(ctx, a, MO_SB, false); > +} > + > +static bool trans_th_lrbu(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_load_idx(ctx, a, MO_UB, false); > +} > + > +static bool trans_th_srd(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + REQUIRE_64BIT(ctx); > + return gen_store_idx(ctx, a, MO_TESQ, false); > +} > + > +static bool trans_th_srw(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_store_idx(ctx, a, MO_TESL, false); > +} > + > +static bool trans_th_srh(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_store_idx(ctx, a, MO_TESW, false); > +} > + > +static bool trans_th_srb(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_store_idx(ctx, a, MO_SB, false); > +} > +static bool trans_th_lurd(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + REQUIRE_64BIT(ctx); > + return gen_load_idx(ctx, a, MO_TESQ, true); > +} > + > +static bool trans_th_lurw(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_load_idx(ctx, a, MO_TESL, true); > +} > + > +static bool trans_th_lurwu(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + REQUIRE_64BIT(ctx); > + return gen_load_idx(ctx, a, MO_TEUL, true); > +} > + > +static bool trans_th_lurh(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_load_idx(ctx, a, MO_TESW, true); > +} > + > +static bool trans_th_lurhu(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_load_idx(ctx, a, MO_TEUW, true); > +} > + > +static bool trans_th_lurb(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_load_idx(ctx, a, MO_SB, true); > +} > + > +static bool trans_th_lurbu(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_load_idx(ctx, a, MO_UB, true); > +} > + > +static bool trans_th_surd(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + REQUIRE_64BIT(ctx); > + return gen_store_idx(ctx, a, MO_TESQ, true); > +} > + > +static bool trans_th_surw(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_store_idx(ctx, a, MO_TESL, true); > +} > + > +static bool trans_th_surh(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_store_idx(ctx, a, MO_TESW, true); > +} > + > +static bool trans_th_surb(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADMEMIDX(ctx); > + return gen_store_idx(ctx, a, MO_SB, true); > +} > + > /* XTheadMemPair */ > > static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp mem= op, > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index 348fe511e1..f5a870a2ac 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -130,7 +130,8 @@ static bool has_xthead_p(DisasContext *ctx __attribu= te__((__unused__))) > return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || > ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || > ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadma= c || > - ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsy= nc; > + ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmem= pair || > + ctx->cfg_ptr->ext_xtheadsync; > } > > #define MATERIALISE_EXT_PREDICATE(ext) \ > @@ -564,6 +565,24 @@ static TCGv get_address(DisasContext *ctx, int rs1, = int imm) > return addr; > } > > +/* Compute a canonical address from a register plus reg offset. */ > +static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) > +{ > + TCGv addr =3D temp_new(ctx); > + TCGv src1 =3D get_gpr(ctx, rs1, EXT_NONE); > + > + tcg_gen_add_tl(addr, src1, offs); > + if (ctx->pm_mask_enabled) { > + tcg_gen_andc_tl(addr, addr, pm_mask); > + } else if (get_xl(ctx) =3D=3D MXL_RV32) { > + tcg_gen_ext32u_tl(addr, addr); > + } > + if (ctx->pm_base_enabled) { > + tcg_gen_or_tl(addr, addr, pm_base); > + } > + return addr; > +} > + > #ifndef CONFIG_USER_ONLY > /* The states of mstatus_fs are: > * 0 =3D disabled, 1 =3D initial, 2 =3D clean, 3 =3D dirty > diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode > index ff2a83b56d..69e40f22dc 100644 > --- a/target/riscv/xthead.decode > +++ b/target/riscv/xthead.decode > @@ -17,8 +17,10 @@ > %rd2 20:5 > %rs2 20:5 > %sh5 20:5 > +%imm5 20:s5 > %sh6 20:6 > %sh2 25:2 > +%imm2 25:2 > > # Argument sets > &r rd rs1 rs2 !extern > @@ -26,6 +28,8 @@ > &shift shamt rs1 rd !extern > &th_bfext msb lsb rs1 rd > &th_pair rd1 rs rd2 sh2 > +&th_memidx rd rs1 rs2 imm2 > +&th_meminc rd rs1 imm5 imm2 > > # Formats > @sfence_vm ....... ..... ..... ... ..... ....... %rs1 > @@ -36,6 +40,8 @@ > @sh5 ....... ..... ..... ... ..... ....... &shift shamt=3D%sh5= %rs1 %rd > @sh6 ...... ...... ..... ... ..... ....... &shift shamt=3D%sh6 = %rs1 %rd > @th_pair ..... .. ..... ..... ... ..... ....... &th_pair %rd1 %rs %r= d2 %sh2 > +@th_memidx ..... .. ..... ..... ... ..... ....... &th_memidx %rd %rs1 = %rs2 %imm2 > +@th_meminc ..... .. ..... ..... ... ..... ....... &th_meminc %rd %rs1 = %imm5 %imm2 > > # XTheadBa > # Instead of defining a new encoding, we simply use the decoder to > @@ -102,6 +108,54 @@ th_muls 00100 01 ..... ..... 001 ..... 0001= 011 @r > th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r > th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r > > +# XTheadMemIdx > +th_ldia 01111 .. ..... ..... 100 ..... 0001011 @th_meminc > +th_ldib 01101 .. ..... ..... 100 ..... 0001011 @th_meminc > +th_lwia 01011 .. ..... ..... 100 ..... 0001011 @th_meminc > +th_lwib 01001 .. ..... ..... 100 ..... 0001011 @th_meminc > +th_lwuia 11011 .. ..... ..... 100 ..... 0001011 @th_meminc > +th_lwuib 11001 .. ..... ..... 100 ..... 0001011 @th_meminc > +th_lhia 00111 .. ..... ..... 100 ..... 0001011 @th_meminc > +th_lhib 00101 .. ..... ..... 100 ..... 0001011 @th_meminc > +th_lhuia 10111 .. ..... ..... 100 ..... 0001011 @th_meminc > +th_lhuib 10101 .. ..... ..... 100 ..... 0001011 @th_meminc > +th_lbia 00011 .. ..... ..... 100 ..... 0001011 @th_meminc > +th_lbib 00001 .. ..... ..... 100 ..... 0001011 @th_meminc > +th_lbuia 10011 .. ..... ..... 100 ..... 0001011 @th_meminc > +th_lbuib 10001 .. ..... ..... 100 ..... 0001011 @th_meminc > +th_sdia 01111 .. ..... ..... 101 ..... 0001011 @th_meminc > +th_sdib 01101 .. ..... ..... 101 ..... 0001011 @th_meminc > +th_swia 01011 .. ..... ..... 101 ..... 0001011 @th_meminc > +th_swib 01001 .. ..... ..... 101 ..... 0001011 @th_meminc > +th_shia 00111 .. ..... ..... 101 ..... 0001011 @th_meminc > +th_shib 00101 .. ..... ..... 101 ..... 0001011 @th_meminc > +th_sbia 00011 .. ..... ..... 101 ..... 0001011 @th_meminc > +th_sbib 00001 .. ..... ..... 101 ..... 0001011 @th_meminc > + > +th_lrd 01100 .. ..... ..... 100 ..... 0001011 @th_memidx > +th_lrw 01000 .. ..... ..... 100 ..... 0001011 @th_memidx > +th_lrwu 11000 .. ..... ..... 100 ..... 0001011 @th_memidx > +th_lrh 00100 .. ..... ..... 100 ..... 0001011 @th_memidx > +th_lrhu 10100 .. ..... ..... 100 ..... 0001011 @th_memidx > +th_lrb 00000 .. ..... ..... 100 ..... 0001011 @th_memidx > +th_lrbu 10000 .. ..... ..... 100 ..... 0001011 @th_memidx > +th_srd 01100 .. ..... ..... 101 ..... 0001011 @th_memidx > +th_srw 01000 .. ..... ..... 101 ..... 0001011 @th_memidx > +th_srh 00100 .. ..... ..... 101 ..... 0001011 @th_memidx > +th_srb 00000 .. ..... ..... 101 ..... 0001011 @th_memidx > + > +th_lurd 01110 .. ..... ..... 100 ..... 0001011 @th_memidx > +th_lurw 01010 .. ..... ..... 100 ..... 0001011 @th_memidx > +th_lurwu 11010 .. ..... ..... 100 ..... 0001011 @th_memidx > +th_lurh 00110 .. ..... ..... 100 ..... 0001011 @th_memidx > +th_lurhu 10110 .. ..... ..... 100 ..... 0001011 @th_memidx > +th_lurb 00010 .. ..... ..... 100 ..... 0001011 @th_memidx > +th_lurbu 10010 .. ..... ..... 100 ..... 0001011 @th_memidx > +th_surd 01110 .. ..... ..... 101 ..... 0001011 @th_memidx > +th_surw 01010 .. ..... ..... 101 ..... 0001011 @th_memidx > +th_surh 00110 .. ..... ..... 101 ..... 0001011 @th_memidx > +th_surb 00010 .. ..... ..... 101 ..... 0001011 @th_memidx > + > # XTheadMemPair > th_ldd 11111 .. ..... ..... 100 ..... 0001011 @th_pair > th_lwd 11100 .. ..... ..... 100 ..... 0001011 @th_pair > -- > 2.38.1 > > From MAILER-DAEMON Mon Jan 23 18:31:02 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK6H9-00043h-Mx for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 18:30:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK6H7-00043E-OF; Mon, 23 Jan 2023 18:30:53 -0500 Received: from mail-vs1-xe29.google.com ([2607:f8b0:4864:20::e29]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) 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Date: Tue, 24 Jan 2023 09:30:18 +1000 Message-ID: Subject: Re: [PATCH v2] include/hw/riscv/opentitan: update opentitan IRQs To: Wilfred Mallawa Cc: Alistair.Francis@wdc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Wilfred Mallawa Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e29; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe29.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 23:30:54 -0000 On Mon, Jan 23, 2023 at 4:40 PM Wilfred Mallawa wrote: > > From: Wilfred Mallawa > > Updates the opentitan IRQs to match the latest supported commit of > Opentitan from TockOS. > > OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47 > > Memory layout as per [1] > > [1] https://github.com/lowRISC/opentitan/blob/565e4af39760a123c59a184aa2f5812a961fde47/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h > > Signed-off-by: Wilfred Mallawa Thanks! Applied to riscv-to-apply.next Alistair > --- > Changes in v2: > - Updated the MMIO register layout/size > - Bumped the supported commit sha > - Added link to OT register layout for reference in the commit > msg > > hw/riscv/opentitan.c | 80 ++++++++++++++++++------------------ > include/hw/riscv/opentitan.h | 14 +++---- > 2 files changed, 47 insertions(+), 47 deletions(-) > > diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c > index 64d5d435b9..353f030d80 100644 > --- a/hw/riscv/opentitan.c > +++ b/hw/riscv/opentitan.c > @@ -31,47 +31,47 @@ > /* > * This version of the OpenTitan machine currently supports > * OpenTitan RTL version: > - * > + * > * > * MMIO mapping as per (specified commit): > * lowRISC/opentitan: hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h > */ > static const MemMapEntry ibex_memmap[] = { > - [IBEX_DEV_ROM] = { 0x00008000, 0x8000 }, > - [IBEX_DEV_RAM] = { 0x10000000, 0x20000 }, > - [IBEX_DEV_FLASH] = { 0x20000000, 0x100000 }, > - [IBEX_DEV_UART] = { 0x40000000, 0x1000 }, > - [IBEX_DEV_GPIO] = { 0x40040000, 0x1000 }, > - [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x1000 }, > - [IBEX_DEV_I2C] = { 0x40080000, 0x1000 }, > - [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 }, > - [IBEX_DEV_TIMER] = { 0x40100000, 0x1000 }, > - [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 }, > - [IBEX_DEV_LC_CTRL] = { 0x40140000, 0x1000 }, > - [IBEX_DEV_ALERT_HANDLER] = { 0x40150000, 0x1000 }, > - [IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x1000 }, > - [IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x1000 }, > - [IBEX_DEV_USBDEV] = { 0x40320000, 0x1000 }, > - [IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 }, > - [IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 }, > - [IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 }, > - [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 }, > - [IBEX_DEV_AON_TIMER] = { 0x40470000, 0x1000 }, > - [IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x1000 }, > - [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x1000 }, > - [IBEX_DEV_AES] = { 0x41100000, 0x1000 }, > - [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 }, > - [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 }, > - [IBEX_DEV_OTBN] = { 0x41130000, 0x10000 }, > - [IBEX_DEV_KEYMGR] = { 0x41140000, 0x1000 }, > - [IBEX_DEV_CSRNG] = { 0x41150000, 0x1000 }, > - [IBEX_DEV_ENTROPY] = { 0x41160000, 0x1000 }, > - [IBEX_DEV_EDNO] = { 0x41170000, 0x1000 }, > - [IBEX_DEV_EDN1] = { 0x41180000, 0x1000 }, > - [IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 }, > - [IBEX_DEV_PERI] = { 0x411f0000, 0x10000 }, > - [IBEX_DEV_PLIC] = { 0x48000000, 0x4005000 }, > - [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 }, > + [IBEX_DEV_ROM] = { 0x00008000, 0x8000 }, > + [IBEX_DEV_RAM] = { 0x10000000, 0x20000 }, > + [IBEX_DEV_FLASH] = { 0x20000000, 0x100000 }, > + [IBEX_DEV_UART] = { 0x40000000, 0x40 }, > + [IBEX_DEV_GPIO] = { 0x40040000, 0x40 }, > + [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x2000 }, > + [IBEX_DEV_I2C] = { 0x40080000, 0x80 }, > + [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x40 }, > + [IBEX_DEV_TIMER] = { 0x40100000, 0x200 }, > + [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x2000 }, > + [IBEX_DEV_LC_CTRL] = { 0x40140000, 0x100 }, > + [IBEX_DEV_ALERT_HANDLER] = { 0x40150000, 0x800 }, > + [IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x40 }, > + [IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x40 }, > + [IBEX_DEV_USBDEV] = { 0x40320000, 0x1000 }, > + [IBEX_DEV_PWRMGR] = { 0x40400000, 0x80 }, > + [IBEX_DEV_RSTMGR] = { 0x40410000, 0x80 }, > + [IBEX_DEV_CLKMGR] = { 0x40420000, 0x80 }, > + [IBEX_DEV_PINMUX] = { 0x40460000, 0x1000 }, > + [IBEX_DEV_AON_TIMER] = { 0x40470000, 0x40 }, > + [IBEX_DEV_SENSOR_CTRL] = { 0x40490000, 0x40 }, > + [IBEX_DEV_FLASH_CTRL] = { 0x41000000, 0x200 }, > + [IBEX_DEV_AES] = { 0x41100000, 0x100 }, > + [IBEX_DEV_HMAC] = { 0x41110000, 0x1000 }, > + [IBEX_DEV_KMAC] = { 0x41120000, 0x1000 }, > + [IBEX_DEV_OTBN] = { 0x41130000, 0x10000 }, > + [IBEX_DEV_KEYMGR] = { 0x41140000, 0x100 }, > + [IBEX_DEV_CSRNG] = { 0x41150000, 0x80 }, > + [IBEX_DEV_ENTROPY] = { 0x41160000, 0x100 }, > + [IBEX_DEV_EDNO] = { 0x41170000, 0x80 }, > + [IBEX_DEV_EDN1] = { 0x41180000, 0x80 }, > + [IBEX_DEV_SRAM_CTRL] = { 0x411c0000, 0x20 }, > + [IBEX_DEV_IBEX_CFG] = { 0x411f0000, 0x100 }, > + [IBEX_DEV_PLIC] = { 0x48000000, 0x8000000 }, > + [IBEX_DEV_FLASH_VIRTUAL] = { 0x80000000, 0x80000 }, > }; > > static void opentitan_board_init(MachineState *machine) > @@ -294,12 +294,12 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) > memmap[IBEX_DEV_EDN1].base, memmap[IBEX_DEV_EDN1].size); > create_unimplemented_device("riscv.lowrisc.ibex.alert_handler", > memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size); > - create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen", > - memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size); > + create_unimplemented_device("riscv.lowrisc.ibex.sram_ctrl", > + memmap[IBEX_DEV_SRAM_CTRL].base, memmap[IBEX_DEV_SRAM_CTRL].size); > create_unimplemented_device("riscv.lowrisc.ibex.otbn", > memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size); > - create_unimplemented_device("riscv.lowrisc.ibex.peri", > - memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size); > + create_unimplemented_device("riscv.lowrisc.ibex.ibex_cfg", > + memmap[IBEX_DEV_IBEX_CFG].base, memmap[IBEX_DEV_IBEX_CFG].size); > } > > static Property lowrisc_ibex_soc_props[] = { > diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h > index 7659d1bc5b..c40b05052a 100644 > --- a/include/hw/riscv/opentitan.h > +++ b/include/hw/riscv/opentitan.h > @@ -94,9 +94,9 @@ enum { > IBEX_DEV_EDNO, > IBEX_DEV_EDN1, > IBEX_DEV_ALERT_HANDLER, > - IBEX_DEV_NMI_GEN, > + IBEX_DEV_SRAM_CTRL, > IBEX_DEV_OTBN, > - IBEX_DEV_PERI, > + IBEX_DEV_IBEX_CFG, > }; > > enum { > @@ -108,11 +108,11 @@ enum { > IBEX_UART0_RX_BREAK_ERR_IRQ = 6, > IBEX_UART0_RX_TIMEOUT_IRQ = 7, > IBEX_UART0_RX_PARITY_ERR_IRQ = 8, > - IBEX_TIMER_TIMEREXPIRED0_0 = 127, > - IBEX_SPI_HOST0_ERR_IRQ = 134, > - IBEX_SPI_HOST0_SPI_EVENT_IRQ = 135, > - IBEX_SPI_HOST1_ERR_IRQ = 136, > - IBEX_SPI_HOST1_SPI_EVENT_IRQ = 137, > + IBEX_TIMER_TIMEREXPIRED0_0 = 124, > + IBEX_SPI_HOST0_ERR_IRQ = 131, > + IBEX_SPI_HOST0_SPI_EVENT_IRQ = 132, > + IBEX_SPI_HOST1_ERR_IRQ = 133, > + IBEX_SPI_HOST1_SPI_EVENT_IRQ = 134, > }; > > #endif > -- > 2.39.1 > > From MAILER-DAEMON Mon Jan 23 18:39:09 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK6P7-0006bJ-Mw for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 18:39:09 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK6P5-0006ax-BY; Mon, 23 Jan 2023 18:39:07 -0500 Received: from mail-vk1-xa29.google.com ([2607:f8b0:4864:20::a29]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK6P3-00067B-87; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a29; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa29.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 23:39:07 -0000 On Sat, Dec 24, 2022 at 4:09 AM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > This patch adds support for the T-Head FMemIdx instructions. > The patch uses the T-Head specific decoder and translation. > > Changes in v2: > - Add ISA_EXT_DATA_ENTRY() > - Use single decoder for XThead extensions > - Use get_th_address_indexed for address calculations > > Co-developed-by: LIU Zhiwei > Signed-off-by: Christoph M=C3=BCllner Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 2 + > target/riscv/cpu.h | 1 + > target/riscv/insn_trans/trans_xthead.c.inc | 108 +++++++++++++++++++++ > target/riscv/translate.c | 3 +- > target/riscv/xthead.decode | 10 ++ > 5 files changed, 123 insertions(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 1fbfb7ccc3..9c31a50e90 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -113,6 +113,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D = { > ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs= ), > ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadc= mo), > ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xth= eadcondmov), > + ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xth= eadfmemidx), > ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadm= ac), > ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xthe= admemidx), > ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xth= eadmempair), > @@ -1074,6 +1075,7 @@ static Property riscv_cpu_extensions[] =3D { > DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), > DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), > DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, f= alse), > + DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, f= alse), > DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), > DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, fal= se), > DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, f= alse), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 965dc46591..c97c1c0af0 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -470,6 +470,7 @@ struct RISCVCPUConfig { > bool ext_xtheadbs; > bool ext_xtheadcmo; > bool ext_xtheadcondmov; > + bool ext_xtheadfmemidx; > bool ext_xtheadmac; > bool ext_xtheadmemidx; > bool ext_xtheadmempair; > diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/in= sn_trans/trans_xthead.c.inc > index 02b82ac327..dc1a11070e 100644 > --- a/target/riscv/insn_trans/trans_xthead.c.inc > +++ b/target/riscv/insn_trans/trans_xthead.c.inc > @@ -46,6 +46,12 @@ > } \ > } while (0) > > +#define REQUIRE_XTHEADFMEMIDX(ctx) do { \ > + if (!ctx->cfg_ptr->ext_xtheadfmemidx) { \ > + return false; \ > + } \ > +} while (0) > + > #define REQUIRE_XTHEADMAC(ctx) do { \ > if (!ctx->cfg_ptr->ext_xtheadmac) { \ > return false; \ > @@ -349,6 +355,108 @@ static bool trans_th_mvnez(DisasContext *ctx, arg_t= h_mveqz *a) > return gen_th_condmove(ctx, a, TCG_COND_NE); > } > > +/* XTheadFMem */ > + > +/* > + * Load 64-bit float from indexed address. > + * If !zext_offs, then address is rs1 + (rs2 << imm2). > + * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2). > + */ > +static bool gen_fload_idx(DisasContext *ctx, arg_th_memidx *a, MemOp mem= op, > + bool zext_offs) > +{ > + TCGv_i64 rd =3D cpu_fpr[a->rd]; > + TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, z= ext_offs); > + > + tcg_gen_qemu_ld_i64(rd, addr, ctx->mem_idx, memop); > + if ((memop & MO_SIZE) =3D=3D MO_32) { > + gen_nanbox_s(rd, rd); > + } > + > + mark_fs_dirty(ctx); > + return true; > +} > + > +/* > + * Store 64-bit float to indexed address. > + * If !zext_offs, then address is rs1 + (rs2 << imm2). > + * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2). > + */ > +static bool gen_fstore_idx(DisasContext *ctx, arg_th_memidx *a, MemOp me= mop, > + bool zext_offs) > +{ > + TCGv_i64 rd =3D cpu_fpr[a->rd]; > + TCGv addr =3D get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, z= ext_offs); > + > + tcg_gen_qemu_st_i64(rd, addr, ctx->mem_idx, memop); > + > + return true; > +} > + > +static bool trans_th_flrd(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADFMEMIDX(ctx); > + REQUIRE_FPU; > + REQUIRE_EXT(ctx, RVD); > + return gen_fload_idx(ctx, a, MO_TEUQ, false); > +} > + > +static bool trans_th_flrw(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADFMEMIDX(ctx); > + REQUIRE_FPU; > + REQUIRE_EXT(ctx, RVF); > + return gen_fload_idx(ctx, a, MO_TEUL, false); > +} > + > +static bool trans_th_flurd(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADFMEMIDX(ctx); > + REQUIRE_FPU; > + REQUIRE_EXT(ctx, RVD); > + return gen_fload_idx(ctx, a, MO_TEUQ, true); > +} > + > +static bool trans_th_flurw(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADFMEMIDX(ctx); > + REQUIRE_FPU; > + REQUIRE_EXT(ctx, RVF); > + return gen_fload_idx(ctx, a, MO_TEUL, true); > +} > + > +static bool trans_th_fsrd(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADFMEMIDX(ctx); > + REQUIRE_FPU; > + REQUIRE_EXT(ctx, RVD); > + return gen_fstore_idx(ctx, a, MO_TEUQ, false); > +} > + > +static bool trans_th_fsrw(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADFMEMIDX(ctx); > + REQUIRE_FPU; > + REQUIRE_EXT(ctx, RVF); > + return gen_fstore_idx(ctx, a, MO_TEUL, false); > +} > + > +static bool trans_th_fsurd(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADFMEMIDX(ctx); > + REQUIRE_FPU; > + REQUIRE_EXT(ctx, RVD); > + return gen_fstore_idx(ctx, a, MO_TEUQ, true); > +} > + > +static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a) > +{ > + REQUIRE_XTHEADFMEMIDX(ctx); > + REQUIRE_FPU; > + REQUIRE_EXT(ctx, RVF); > + return gen_fstore_idx(ctx, a, MO_TEUL, true); > +} > + > /* XTheadMac */ > > static bool gen_th_mac(DisasContext *ctx, arg_r *a, > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index f5a870a2ac..fb77df721e 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -129,7 +129,8 @@ static bool has_xthead_p(DisasContext *ctx __attribu= te__((__unused__))) > { > return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || > ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || > - ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadma= c || > + ctx->cfg_ptr->ext_xtheadcondmov || > + ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadma= c || > ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmem= pair || > ctx->cfg_ptr->ext_xtheadsync; > } > diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode > index 69e40f22dc..81daf1d694 100644 > --- a/target/riscv/xthead.decode > +++ b/target/riscv/xthead.decode > @@ -100,6 +100,16 @@ th_l2cache_iall 0000000 10110 00000 000 00000 00010= 11 > th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r > th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r > > +# XTheadFMemIdx > +th_flrd 01100 .. ..... ..... 110 ..... 0001011 @th_memidx > +th_flrw 01000 .. ..... ..... 110 ..... 0001011 @th_memidx > +th_flurd 01110 .. ..... ..... 110 ..... 0001011 @th_memidx > +th_flurw 01010 .. ..... ..... 110 ..... 0001011 @th_memidx > +th_fsrd 01100 .. ..... ..... 111 ..... 0001011 @th_memidx > +th_fsrw 01000 .. ..... ..... 111 ..... 0001011 @th_memidx > +th_fsurd 01110 .. ..... ..... 111 ..... 0001011 @th_memidx > +th_fsurw 01010 .. ..... ..... 111 ..... 0001011 @th_memidx > + > # XTheadMac > th_mula 00100 00 ..... ..... 001 ..... 0001011 @r > th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r > -- > 2.38.1 > > From MAILER-DAEMON Mon Jan 23 18:40:24 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK6QK-0007dd-0A for mharc-qemu-riscv@gnu.org; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e31; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe31.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 23:40:22 -0000 On Sat, Dec 24, 2022 at 4:07 AM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > There are no differences for floating point instructions in priv version = 1.11 > and 1.12. There is also no dependency for Zfh to priv version 1.12. > Therefore allow Zfh to be enabled for priv version 1.11. > > Signed-off-by: Christoph M=C3=BCllner Acked-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index bb310755b1..a38127365e 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -76,7 +76,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D { > ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), > ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei)= , > ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihin= tpause), > - ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), > + ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh), > ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), > ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), > ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), > -- > 2.38.1 > > From MAILER-DAEMON Mon Jan 23 18:40:55 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK6Qp-00081H-B0 for mharc-qemu-riscv@gnu.org; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e31; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe31.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 23:40:54 -0000 On Sat, Dec 24, 2022 at 4:09 AM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > The XThead* extensions are maintained by T-Head and VRULL. > Adding a point of contact from both companies. > > Signed-off-by: LIU Zhiwei > Signed-off-by: Christoph M=C3=BCllner Reviewed-by: Alistair Francis Alistair > --- > MAINTAINERS | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/MAINTAINERS b/MAINTAINERS > index b270eb8e5b..38f3ab3772 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -294,6 +294,14 @@ F: include/hw/riscv/ > F: linux-user/host/riscv32/ > F: linux-user/host/riscv64/ > > +RISC-V XThead* extensions > +M: Christoph Muellner > +M: LIU Zhiwei > +L: qemu-riscv@nongnu.org > +S: Supported > +F: target/riscv/insn_trans/trans_xthead.c.inc > +F: target/riscv/xthead*.decode > + > RISC-V XVentanaCondOps extension > M: Philipp Tomsich > L: qemu-riscv@nongnu.org > -- > 2.38.1 > > From MAILER-DAEMON Mon Jan 23 18:43:38 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK6TS-00010T-Lr for mharc-qemu-riscv@gnu.org; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e33; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe33.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 23:43:37 -0000 On Sat, Dec 24, 2022 at 4:07 AM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > This patch adds the T-Head C906 to the list of known CPUs. > Selecting this CPUs will automatically enable the available > ISA extensions of the CPUs (incl. vendor extensions). > > Co-developed-by: LIU Zhiwei > Signed-off-by: Christoph M=C3=BCllner > > Changes in v2: > - Drop C910 as it does not differ from C906 > - Set priv version to 1.11 (new fmin/fmax behaviour) This should be below the line Otherwise: Reviewed-by: Alistair Francis Alistair > > Signed-off-by: Christoph M=C3=BCllner > --- > target/riscv/cpu.c | 31 +++++++++++++++++++++++++++++++ > target/riscv/cpu.h | 2 ++ > target/riscv/cpu_vendorid.h | 6 ++++++ > 3 files changed, 39 insertions(+) > create mode 100644 target/riscv/cpu_vendorid.h > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index a38127365e..d3d8587710 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -279,6 +279,36 @@ static void rv64_sifive_e_cpu_init(Object *obj) > cpu->cfg.mmu =3D false; > } > > +static void rv64_thead_c906_cpu_init(Object *obj) > +{ > + CPURISCVState *env =3D &RISCV_CPU(obj)->env; > + RISCVCPU *cpu =3D RISCV_CPU(obj); > + > + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RV= U); > + set_priv_version(env, PRIV_VERSION_1_11_0); > + > + cpu->cfg.ext_g =3D true; > + cpu->cfg.ext_c =3D true; > + cpu->cfg.ext_u =3D true; > + cpu->cfg.ext_s =3D true; > + cpu->cfg.ext_icsr =3D true; > + cpu->cfg.ext_zfh =3D true; > + cpu->cfg.mmu =3D true; > + cpu->cfg.ext_xtheadba =3D true; > + cpu->cfg.ext_xtheadbb =3D true; > + cpu->cfg.ext_xtheadbs =3D true; > + cpu->cfg.ext_xtheadcmo =3D true; > + cpu->cfg.ext_xtheadcondmov =3D true; > + cpu->cfg.ext_xtheadfmemidx =3D true; > + cpu->cfg.ext_xtheadmac =3D true; > + cpu->cfg.ext_xtheadmemidx =3D true; > + cpu->cfg.ext_xtheadmempair =3D true; > + cpu->cfg.ext_xtheadsync =3D true; > + cpu->cfg.ext_xtheadxmae =3D true; > + > + cpu->cfg.mvendorid =3D THEAD_VENDOR_ID; > +} > + > static void rv128_base_cpu_init(Object *obj) > { > if (qemu_tcg_mttcg_enabled()) { > @@ -1311,6 +1341,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), > DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), > + DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init= ), > DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), > #endif > }; > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 897962f107..28184bbe40 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -27,6 +27,7 @@ > #include "qom/object.h" > #include "qemu/int128.h" > #include "cpu_bits.h" > +#include "cpu_vendorid.h" > > #define TCG_GUEST_DEFAULT_MO 0 > > @@ -53,6 +54,7 @@ > #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51"= ) > #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34"= ) > #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54"= ) > +#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906"= ) > #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") > > #if defined(TARGET_RISCV32) > diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h > new file mode 100644 > index 0000000000..a5aa249bc9 > --- /dev/null > +++ b/target/riscv/cpu_vendorid.h > @@ -0,0 +1,6 @@ > +#ifndef TARGET_RISCV_CPU_VENDORID_H > +#define TARGET_RISCV_CPU_VENDORID_H > + > +#define THEAD_VENDOR_ID 0x5b7 > + > +#endif /* TARGET_RISCV_CPU_VENDORID_H */ > -- > 2.38.1 > > From MAILER-DAEMON Mon Jan 23 18:44:30 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK6UI-0001jK-NH for mharc-qemu-riscv@gnu.org; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a2c; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 23:44:29 -0000 On Sat, Dec 24, 2022 at 4:07 AM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > This patch adds support for the XTheadFmv ISA extension. > The patch uses the T-Head specific decoder and translation. > > Signed-off-by: LIU Zhiwei > Signed-off-by: Christoph M=C3=BCllner Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu.c | 2 + > target/riscv/cpu.h | 1 + > target/riscv/insn_trans/trans_xthead.c.inc | 45 ++++++++++++++++++++++ > target/riscv/translate.c | 6 +-- > target/riscv/xthead.decode | 4 ++ > 5 files changed, 55 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index d3d8587710..d3f711cc41 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D = { > ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadc= mo), > ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xth= eadcondmov), > ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xth= eadfmemidx), > + ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadf= mv), > ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadm= ac), > ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xthe= admemidx), > ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xth= eadmempair), > @@ -1107,6 +1108,7 @@ static Property riscv_cpu_extensions[] =3D { > DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), > DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, f= alse), > DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, f= alse), > + DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), > DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), > DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, fal= se), > DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, f= alse), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 28184bbe40..154c16208a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -473,6 +473,7 @@ struct RISCVCPUConfig { > bool ext_xtheadcmo; > bool ext_xtheadcondmov; > bool ext_xtheadfmemidx; > + bool ext_xtheadfmv; > bool ext_xtheadmac; > bool ext_xtheadmemidx; > bool ext_xtheadmempair; > diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/in= sn_trans/trans_xthead.c.inc > index dc1a11070e..12d5af4f75 100644 > --- a/target/riscv/insn_trans/trans_xthead.c.inc > +++ b/target/riscv/insn_trans/trans_xthead.c.inc > @@ -52,6 +52,12 @@ > } \ > } while (0) > > +#define REQUIRE_XTHEADFMV(ctx) do { \ > + if (!ctx->cfg_ptr->ext_xtheadfmv) { \ > + return false; \ > + } \ > +} while (0) > + > #define REQUIRE_XTHEADMAC(ctx) do { \ > if (!ctx->cfg_ptr->ext_xtheadmac) { \ > return false; \ > @@ -457,6 +463,45 @@ static bool trans_th_fsurw(DisasContext *ctx, arg_th= _memidx *a) > return gen_fstore_idx(ctx, a, MO_TEUL, true); > } > > +/* XTheadFmv */ > + > +static bool trans_th_fmv_hw_x(DisasContext *ctx, arg_th_fmv_hw_x *a) > +{ > + REQUIRE_XTHEADFMV(ctx); > + REQUIRE_32BIT(ctx); > + REQUIRE_FPU; > + REQUIRE_EXT(ctx, RVD); > + > + TCGv src1 =3D get_gpr(ctx, a->rs1, EXT_ZERO); > + TCGv_i64 t1 =3D tcg_temp_new_i64(); > + > + tcg_gen_extu_tl_i64(t1, src1); > + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], t1, 32, 32); > + tcg_temp_free_i64(t1); > + mark_fs_dirty(ctx); > + return true; > +} > + > +static bool trans_th_fmv_x_hw(DisasContext *ctx, arg_th_fmv_x_hw *a) > +{ > + REQUIRE_XTHEADFMV(ctx); > + REQUIRE_32BIT(ctx); > + REQUIRE_FPU; > + REQUIRE_EXT(ctx, RVD); > + TCGv dst; > + TCGv_i64 t1; > + > + dst =3D dest_gpr(ctx, a->rd); > + t1 =3D tcg_temp_new_i64(); > + > + tcg_gen_extract_i64(t1, cpu_fpr[a->rs1], 32, 32); > + tcg_gen_trunc_i64_tl(dst, t1); > + gen_set_gpr(ctx, a->rd, dst); > + tcg_temp_free_i64(t1); > + mark_fs_dirty(ctx); > + return true; > +} > + > /* XTheadMac */ > > static bool gen_th_mac(DisasContext *ctx, arg_r *a, > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > index fb77df721e..1c54c3c67d 100644 > --- a/target/riscv/translate.c > +++ b/target/riscv/translate.c > @@ -130,9 +130,9 @@ static bool has_xthead_p(DisasContext *ctx __attribu= te__((__unused__))) > return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || > ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || > ctx->cfg_ptr->ext_xtheadcondmov || > - ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadma= c || > - ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmem= pair || > - ctx->cfg_ptr->ext_xtheadsync; > + ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfm= v || > + ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx= || > + ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsy= nc; > } > > #define MATERIALISE_EXT_PREDICATE(ext) \ > diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode > index 81daf1d694..d1d104bcf2 100644 > --- a/target/riscv/xthead.decode > +++ b/target/riscv/xthead.decode > @@ -110,6 +110,10 @@ th_fsrw 01000 .. ..... ..... 111 ..... 0001= 011 @th_memidx > th_fsurd 01110 .. ..... ..... 111 ..... 0001011 @th_memidx > th_fsurw 01010 .. ..... ..... 111 ..... 0001011 @th_memidx > > +# XTheadFmv > +th_fmv_hw_x 1010000 00000 ..... 001 ..... 0001011 @r2 > +th_fmv_x_hw 1100000 00000 ..... 001 ..... 0001011 @r2 > + > # XTheadMac > th_mula 00100 00 ..... ..... 001 ..... 0001011 @r > th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r > -- > 2.38.1 > > From MAILER-DAEMON Mon Jan 23 18:50:02 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK6Ze-0003eJ-Bc for mharc-qemu-riscv@gnu.org; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e29; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe29.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 23:50:01 -0000 On Sat, Dec 24, 2022 at 4:04 AM Christoph Muellner wrote: > > From: Christoph M=C3=BCllner > > This patch adds support for the T-Head specific extended memory > attributes. Similar like Svpbmt, this support does not have much effect > as most behaviour is not modelled in QEMU. > > We also don't set any EDATA information, because XMAE discovery is done > using the vendor ID in the Linux kernel. > > Changes in v2: > - Add ISA_EXT_DATA_ENTRY() > > Co-developed-by: LIU Zhiwei > Signed-off-by: Christoph M=C3=BCllner > --- > target/riscv/cpu.c | 2 ++ > target/riscv/cpu.h | 1 + > target/riscv/cpu_helper.c | 6 ++++-- > 3 files changed, 7 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 9c31a50e90..bb310755b1 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -118,6 +118,7 @@ static const struct isa_ext_data isa_edata_arr[] =3D = { > ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xthe= admemidx), > ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xth= eadmempair), > ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xthead= sync), > + ISA_EXT_DATA_ENTRY(xtheadxmae, true, PRIV_VERSION_1_11_0, ext_xthead= xmae), > ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_X= VentanaCondOps), > }; > > @@ -1080,6 +1081,7 @@ static Property riscv_cpu_extensions[] =3D { > DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, fal= se), > DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, f= alse), > DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), > + DEFINE_PROP_BOOL("xtheadxmae", RISCVCPU, cfg.ext_xtheadxmae, false), > DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOp= s, false), > > /* These are experimental so mark with 'x-' */ > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index c97c1c0af0..897962f107 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -475,6 +475,7 @@ struct RISCVCPUConfig { > bool ext_xtheadmemidx; > bool ext_xtheadmempair; > bool ext_xtheadsync; > + bool ext_xtheadxmae; > bool ext_XVentanaCondOps; > > uint8_t pmu_num; > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 278d163803..345bb69b79 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -938,7 +938,8 @@ restart: > > if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { > ppn =3D pte >> PTE_PPN_SHIFT; > - } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) { > + } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot || > + cpu->cfg.ext_xtheadxmae) { I don't like this. This is some pretty core code that is now getting vendor extensions. I know this is very simple, but I'm worried we are opening the doors to other vendors adding their MMU changes. Can we just set ext_svpbmt instead? Alistair > ppn =3D (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT; > } else { > ppn =3D pte >> PTE_PPN_SHIFT; > @@ -950,7 +951,8 @@ restart: > if (!(pte & PTE_V)) { > /* Invalid PTE */ > return TRANSLATE_FAIL; > - } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) { > + } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT) && > + !cpu->cfg.ext_xtheadxmae) { > return TRANSLATE_FAIL; > } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { > /* Inner PTE, continue walking */ > -- > 2.38.1 > > From MAILER-DAEMON Mon Jan 23 18:59:55 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK6jD-00073K-Ao for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 18:59:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK6jA-00072x-Q2; Mon, 23 Jan 2023 18:59:52 -0500 Received: from mail-vs1-xe2f.google.com ([2607:f8b0:4864:20::e2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK6j7-0001SI-42; Mon, 23 Jan 2023 18:59:51 -0500 Received: by mail-vs1-xe2f.google.com with SMTP id t10so14860984vsr.3; Mon, 23 Jan 2023 15:59:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=PFWOPvOnxnFt1nZS/xroCnvkkHE6ZU3CpyTkzzQJIf0=; b=O+4VsXDAaQB/2VR18qjEXjgDPYpfoQll8zFMi1RbLfFbcMpGj/qXJ9gDRg4dLLb70u zgcCSrm77ema8nl+DbukjGNxoY5qQcCQdE8aPHjtBE9Dzx642eWSkWUSJXIQALyA1uxW pcaqJENCmBHib5QozkqwkshbbUxtQsK7KOFh+Teg4MHDJyJJ/4JOLvn+QOUTyz03ZiNf SYjG9uE6g1+Rbbr5RJlPUZdTztonkz/O7KfrvX3ElekhiU6SX9UtpzCCSkZnPNTq8GFo uTCSp5X4e2iVWegSW9Hho4r0CJ3CNCPuh384A0q9nceGhQNqSAHio1+fbpJowjF60VrP elSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=PFWOPvOnxnFt1nZS/xroCnvkkHE6ZU3CpyTkzzQJIf0=; b=AbGRFN37qHqvd+9Q7TqMo16MATXmMtl7O5gs+pzpNGnmNO2jdnXSEecWZjF0WCUA3o nSDFS2+Z1davxg6bspi/Aj5+gxuu1/h+7jphA/oePKdhoHfa7pR2k7ywtWPNe2JAkni+ NzteHcaWbz7u2C8njXiR2RKjMyHpBVH89IrOgC9HaAJBQLUb8RiNYo4T37Q6adjgK5GL PBJ5AFiTqKn0jkOWi6zkktiYeV7IKu78Gj53oEKFo2w90bLZ9woLWidQzI+jzLCxVk79 uudnmE2mAEbALsgseBy5tyxDzbzd6ZPzd+mHZ5weG6lDO+Os1UUsM0wBS9C6JrsB5Mvh YPNw== X-Gm-Message-State: AFqh2kp1m9Jfx6VRk0gE41AqJuXw9t1e9IUUDHMtv4fNMb5x9klVwbKw 7mmS+HHPh5GDN+AuLmqa3+llSN7HmEVsU6wCa0w= X-Google-Smtp-Source: AMrXdXskhhOeOpy3YKC0fGtsYfuGJKqPh72FvPiYw8B5xJvi/WtELek3SqpDrQrlmt1nerirUh89wcCdJW+oDeikL4s= X-Received: by 2002:a05:6102:cd4:b0:3d0:c2e9:cb77 with SMTP id g20-20020a0561020cd400b003d0c2e9cb77mr3386149vst.54.1674518387689; Mon, 23 Jan 2023 15:59:47 -0800 (PST) MIME-Version: 1.0 References: <20230123035754.75553-1-alistair.francis@opensource.wdc.com> In-Reply-To: <20230123035754.75553-1-alistair.francis@opensource.wdc.com> From: Alistair Francis Date: Tue, 24 Jan 2023 09:59:21 +1000 Message-ID: Subject: Re: [PATCH] hw/riscv: boot: Don't use CSRs if they are disabled To: Alistair Francis Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, Bin Meng , bmeng.cn@gmail.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e2f; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 Jan 2023 23:59:53 -0000 On Mon, Jan 23, 2023 at 1:58 PM Alistair Francis wrote: > > From: Alistair Francis > > If the CSRs and CSR instructions are disabled because the Zicsr > extension isn't enabled then we want to make sure we don't run any CSR > instructions in the boot ROM. > > This patches removes the CSR instructions from the reset-vec if the > extension isn't enabled. We replace the instruction with a NOP instead. > > Note that we don't do this for the SiFive U machine, as we are modelling > the hardware in that case. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1447 > Signed-off-by: Alistair Francis Thanks! Applied to riscv-to-apply.next Alistair > --- > hw/riscv/boot.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 2594276223..cb27798a25 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -356,6 +356,15 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts > reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ > } > > + if (!harts->harts[0].cfg.ext_icsr) { > + /* > + * The Zicsr extension has been disabled, so let's ensure we don't > + * run the CSR instruction. Let's fill the address with a non > + * compressed nop. > + */ > + reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */ > + } > + > /* copy in the reset vector in little_endian byte order */ > for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { > reset_vec[i] = cpu_to_le32(reset_vec[i]); > -- > 2.39.0 > From MAILER-DAEMON Mon Jan 23 19:01:26 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK6kg-0001US-Dk for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 19:01:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK6kd-0001Je-Ri; Mon, 23 Jan 2023 19:01:23 -0500 Received: from mail-vs1-xe2b.google.com ([2607:f8b0:4864:20::e2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK6ka-0001zT-S3; Mon, 23 Jan 2023 19:01:23 -0500 Received: by mail-vs1-xe2b.google.com with SMTP id t10so14864071vsr.3; Mon, 23 Jan 2023 16:01:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=TB0rFcpVUqF55lX6TOWsh0ljmpLe+RRZeSmlCLBHshc=; b=kDkBaDtZ1spYzejh9g2dGJXiu0AwD8KDTcAhILpnCPbHc4aJw4Jf2iFkZvRgg7+ReZ TX0wICnvy2OauyHk+f0TlaQg6guqmfQJi2cikZrC+d9qx1Ip6F+uzKEFl1QlXDKld4AZ 59V+wghuAMTjajxUdQUOogsPBsdjF81hhr+mcuOW+oVc0hoaOEqz1fXioBw7Lj97gppd yRxdYmMc6ZPITlG/IP/68tmkAHTn76Ew2BsztnQyRd03dt2sIY+hmZT78OMQsN9pDrqM 8ePqCjY64q2TtjeBPXS5elSPbKCFyBKYE5NODI2BvfS8ibkTMuWZvkafCcGkgOU68IYq 0RtQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=TB0rFcpVUqF55lX6TOWsh0ljmpLe+RRZeSmlCLBHshc=; b=QswSaKoo0XA5VQy3FNRbRFoaTPML6RlpA+nEZ/KeWi4OOyd1/gK7SAFpJrlbJ4fQaa VSCuuCQSM2UnqO+vXjPF9yMatPZhmQVcppt1ean1Tls6B/8nTe27D4A9mZnCYNEmeHIT AI776cW2QYAC0H1m6GT/WeqoD46M/h5MDIOn121U/G/5EZPUrr1dlQTQkJlDEg2+wr22 8UCTGnxFSzhfBM7P87/02u56zHODVksei6he4D4pJbvrR03XYcUKqGV8vpFy53mO4KYL 0Yxb99d/sNlvnsG9I6fsBteLSuSG+82NatJI9rErgdqBfhSLX6Vx/MupqFh1FcFjY9WG 8Kyg== X-Gm-Message-State: AFqh2kpo66DWgKekOVLUkOv5wXOP/Tz/CPvcG4nXIqqkmTMOI10FqyIL fjUdotqAgUSfx7Vn8adihOhKvW7vrpzMeJTaPlA= X-Google-Smtp-Source: AMrXdXvzUzVExgdyxAPjjxKCJIFb9u+T0Eg0Mr8n67JS9qDmusn3PppDmK0B4HbYy/6MdKEZTarMwX9BadeJmEORmUM= X-Received: by 2002:a05:6102:cd4:b0:3d0:c2e9:cb77 with SMTP id g20-20020a0561020cd400b003d0c2e9cb77mr3386711vst.54.1674518479282; Mon, 23 Jan 2023 16:01:19 -0800 (PST) MIME-Version: 1.0 References: <20230120125950.2246378-1-apatel@ventanamicro.com> <20230120125950.2246378-5-apatel@ventanamicro.com> In-Reply-To: <20230120125950.2246378-5-apatel@ventanamicro.com> From: Alistair Francis Date: Tue, 24 Jan 2023 10:00:53 +1000 Message-ID: Subject: Re: [PATCH v3 4/4] target/riscv: Ensure opcode is saved for all relevant instructions To: Anup Patel Cc: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Atish Patra , Richard Henderson , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e2b; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2b.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 00:01:24 -0000 On Fri, Jan 20, 2023 at 11:01 PM Anup Patel wrote: > > We should call decode_save_opc() for all relevant instructions which > can potentially generate a virtual instruction fault or a guest page > fault because generating transformed instruction upon guest page fault > expects opcode to be available. Without this, hypervisor will see > transformed instruction as zero in htinst CSR for guest MMIO emulation > which makes MMIO emulation in hypervisor slow and also breaks nested > virtualization. > > Fixes: a9814e3e08d2 ("target/riscv: Minimize the calls to decode_save_opc") > Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Alistair > --- > target/riscv/insn_trans/trans_rva.c.inc | 10 +++++++--- > target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ > target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ > target/riscv/insn_trans/trans_rvh.c.inc | 3 +++ > target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ > target/riscv/insn_trans/trans_rvzfh.c.inc | 2 ++ > target/riscv/insn_trans/trans_svinval.c.inc | 3 +++ > 7 files changed, 21 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_trans/trans_rva.c.inc > index 45db82c9be..5f194a447b 100644 > --- a/target/riscv/insn_trans/trans_rva.c.inc > +++ b/target/riscv/insn_trans/trans_rva.c.inc > @@ -20,8 +20,10 @@ > > static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop) > { > - TCGv src1 = get_address(ctx, a->rs1, 0); > + TCGv src1; > > + decode_save_opc(ctx); > + src1 = get_address(ctx, a->rs1, 0); > if (a->rl) { > tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); > } > @@ -43,6 +45,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop) > TCGLabel *l1 = gen_new_label(); > TCGLabel *l2 = gen_new_label(); > > + decode_save_opc(ctx); > src1 = get_address(ctx, a->rs1, 0); > tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1); > > @@ -81,9 +84,10 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, > MemOp mop) > { > TCGv dest = dest_gpr(ctx, a->rd); > - TCGv src1 = get_address(ctx, a->rs1, 0); > - TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); > + TCGv src1, src2 = get_gpr(ctx, a->rs2, EXT_NONE); > > + decode_save_opc(ctx); > + src1 = get_address(ctx, a->rs1, 0); > func(dest, src1, src2, ctx->mem_idx, mop); > > gen_set_gpr(ctx, a->rd, dest); > diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_trans/trans_rvd.c.inc > index 1397c1ce1c..6e3159b797 100644 > --- a/target/riscv/insn_trans/trans_rvd.c.inc > +++ b/target/riscv/insn_trans/trans_rvd.c.inc > @@ -38,6 +38,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a) > REQUIRE_FPU; > REQUIRE_EXT(ctx, RVD); > > + decode_save_opc(ctx); > addr = get_address(ctx, a->rs1, a->imm); > tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEUQ); > > @@ -52,6 +53,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) > REQUIRE_FPU; > REQUIRE_EXT(ctx, RVD); > > + decode_save_opc(ctx); > addr = get_address(ctx, a->rs1, a->imm); > tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUQ); > return true; > diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_trans/trans_rvf.c.inc > index a1d3eb52ad..965e1f8d11 100644 > --- a/target/riscv/insn_trans/trans_rvf.c.inc > +++ b/target/riscv/insn_trans/trans_rvf.c.inc > @@ -38,6 +38,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a) > REQUIRE_FPU; > REQUIRE_EXT(ctx, RVF); > > + decode_save_opc(ctx); > addr = get_address(ctx, a->rs1, a->imm); > dest = cpu_fpr[a->rd]; > tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL); > @@ -54,6 +55,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) > REQUIRE_FPU; > REQUIRE_EXT(ctx, RVF); > > + decode_save_opc(ctx); > addr = get_address(ctx, a->rs1, a->imm); > tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL); > return true; > diff --git a/target/riscv/insn_trans/trans_rvh.c.inc b/target/riscv/insn_trans/trans_rvh.c.inc > index 4f8aecddc7..9248b48c36 100644 > --- a/target/riscv/insn_trans/trans_rvh.c.inc > +++ b/target/riscv/insn_trans/trans_rvh.c.inc > @@ -36,6 +36,7 @@ static bool do_hlv(DisasContext *ctx, arg_r2 *a, MemOp mop) > #ifdef CONFIG_USER_ONLY > return false; > #else > + decode_save_opc(ctx); > if (check_access(ctx)) { > TCGv dest = dest_gpr(ctx, a->rd); > TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); > @@ -82,6 +83,7 @@ static bool do_hsv(DisasContext *ctx, arg_r2_s *a, MemOp mop) > #ifdef CONFIG_USER_ONLY > return false; > #else > + decode_save_opc(ctx); > if (check_access(ctx)) { > TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); > TCGv data = get_gpr(ctx, a->rs2, EXT_NONE); > @@ -135,6 +137,7 @@ static bool trans_hsv_d(DisasContext *ctx, arg_hsv_d *a) > static bool do_hlvx(DisasContext *ctx, arg_r2 *a, > void (*func)(TCGv, TCGv_env, TCGv)) > { > + decode_save_opc(ctx); > if (check_access(ctx)) { > TCGv dest = dest_gpr(ctx, a->rd); > TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE); > diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc > index 5c69b88d1e..4496f21266 100644 > --- a/target/riscv/insn_trans/trans_rvi.c.inc > +++ b/target/riscv/insn_trans/trans_rvi.c.inc > @@ -261,6 +261,7 @@ static bool gen_load_i128(DisasContext *ctx, arg_lb *a, MemOp memop) > > static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop) > { > + decode_save_opc(ctx); > if (get_xl(ctx) == MXL_RV128) { > return gen_load_i128(ctx, a, memop); > } else { > @@ -350,6 +351,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop) > > static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop) > { > + decode_save_opc(ctx); > if (get_xl(ctx) == MXL_RV128) { > return gen_store_i128(ctx, a, memop); > } else { > diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc > index 5d07150cd0..2ad5716312 100644 > --- a/target/riscv/insn_trans/trans_rvzfh.c.inc > +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc > @@ -49,6 +49,7 @@ static bool trans_flh(DisasContext *ctx, arg_flh *a) > REQUIRE_FPU; > REQUIRE_ZFH_OR_ZFHMIN(ctx); > > + decode_save_opc(ctx); > t0 = get_gpr(ctx, a->rs1, EXT_NONE); > if (a->imm) { > TCGv temp = temp_new(ctx); > @@ -71,6 +72,7 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a) > REQUIRE_FPU; > REQUIRE_ZFH_OR_ZFHMIN(ctx); > > + decode_save_opc(ctx); > t0 = get_gpr(ctx, a->rs1, EXT_NONE); > if (a->imm) { > TCGv temp = tcg_temp_new(); > diff --git a/target/riscv/insn_trans/trans_svinval.c.inc b/target/riscv/insn_trans/trans_svinval.c.inc > index 2682bd969f..f3cd7d5c0b 100644 > --- a/target/riscv/insn_trans/trans_svinval.c.inc > +++ b/target/riscv/insn_trans/trans_svinval.c.inc > @@ -28,6 +28,7 @@ static bool trans_sinval_vma(DisasContext *ctx, arg_sinval_vma *a) > /* Do the same as sfence.vma currently */ > REQUIRE_EXT(ctx, RVS); > #ifndef CONFIG_USER_ONLY > + decode_save_opc(ctx); > gen_helper_tlb_flush(cpu_env); > return true; > #endif > @@ -56,6 +57,7 @@ static bool trans_hinval_vvma(DisasContext *ctx, arg_hinval_vvma *a) > /* Do the same as hfence.vvma currently */ > REQUIRE_EXT(ctx, RVH); > #ifndef CONFIG_USER_ONLY > + decode_save_opc(ctx); > gen_helper_hyp_tlb_flush(cpu_env); > return true; > #endif > @@ -68,6 +70,7 @@ static bool trans_hinval_gvma(DisasContext *ctx, arg_hinval_gvma *a) > /* Do the same as hfence.gvma currently */ > REQUIRE_EXT(ctx, RVH); > #ifndef CONFIG_USER_ONLY > + decode_save_opc(ctx); > gen_helper_hyp_gvma_tlb_flush(cpu_env); > return true; > #endif > -- > 2.34.1 > > From MAILER-DAEMON Mon Jan 23 19:04:00 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK6n7-0008Kp-TW for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 19:03:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK6mI-0007up-0f; Mon, 23 Jan 2023 19:03:06 -0500 Received: from mail-vk1-xa2c.google.com ([2607:f8b0:4864:20::a2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK6m9-00028v-1L; Mon, 23 Jan 2023 19:02:59 -0500 Received: by mail-vk1-xa2c.google.com with SMTP id q21so6847222vka.3; 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Mon, 23 Jan 2023 16:02:55 -0800 (PST) MIME-Version: 1.0 References: <20230123090324.732681-1-alexghiti@rivosinc.com> <20230123090324.732681-3-alexghiti@rivosinc.com> In-Reply-To: <20230123090324.732681-3-alexghiti@rivosinc.com> From: Alistair Francis Date: Tue, 24 Jan 2023 10:02:29 +1000 Message-ID: Subject: Re: [PATCH v6 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::a2c; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 00:03:55 -0000 On Mon, Jan 23, 2023 at 7:06 PM Alexandre Ghiti wrote: > > This array is actually used as a boolean so swap its current char type > to a boolean and at the same time, change the type of validate_vm to > bool since it returns valid_vm_1_10_[32|64]. > > Signed-off-by: Alexandre Ghiti Reviewed-by: Alistair Francis Alistair > --- > target/riscv/csr.c | 21 +++++++++++---------- > 1 file changed, 11 insertions(+), 10 deletions(-) > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 0db2c233e5..6b157806a5 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1117,16 +1117,16 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; > static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; > static const target_ulong vsip_writable_mask = MIP_VSSIP; > > -static const char valid_vm_1_10_32[16] = { > - [VM_1_10_MBARE] = 1, > - [VM_1_10_SV32] = 1 > +static const bool valid_vm_1_10_32[16] = { > + [VM_1_10_MBARE] = true, > + [VM_1_10_SV32] = true > }; > > -static const char valid_vm_1_10_64[16] = { > - [VM_1_10_MBARE] = 1, > - [VM_1_10_SV39] = 1, > - [VM_1_10_SV48] = 1, > - [VM_1_10_SV57] = 1 > +static const bool valid_vm_1_10_64[16] = { > + [VM_1_10_MBARE] = true, > + [VM_1_10_SV39] = true, > + [VM_1_10_SV48] = true, > + [VM_1_10_SV57] = true > }; > > /* Machine Information Registers */ > @@ -1209,7 +1209,7 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, > return RISCV_EXCP_NONE; > } > > -static int validate_vm(CPURISCVState *env, target_ulong vm) > +static bool validate_vm(CPURISCVState *env, target_ulong vm) > { > if (riscv_cpu_mxl(env) == MXL_RV32) { > return valid_vm_1_10_32[vm & 0xf]; > @@ -2648,7 +2648,8 @@ static RISCVException read_satp(CPURISCVState *env, int csrno, > static RISCVException write_satp(CPURISCVState *env, int csrno, > target_ulong val) > { > - target_ulong vm, mask; > + target_ulong mask; > + bool vm; > > if (!riscv_feature(env, RISCV_FEATURE_MMU)) { > return RISCV_EXCP_NONE; > -- > 2.37.2 > > From MAILER-DAEMON Mon Jan 23 19:35:57 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK7I4-0007OY-L6 for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 19:35:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK7I2-0007Nj-Or; Mon, 23 Jan 2023 19:35:54 -0500 Received: from mail-ua1-x935.google.com ([2607:f8b0:4864:20::935]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK7I1-0007Jd-6S; Mon, 23 Jan 2023 19:35:54 -0500 Received: by mail-ua1-x935.google.com with SMTP id u29so2396766uaa.8; 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Mon, 23 Jan 2023 16:35:51 -0800 (PST) MIME-Version: 1.0 References: <20230123090324.732681-1-alexghiti@rivosinc.com> <20230123090324.732681-5-alexghiti@rivosinc.com> In-Reply-To: <20230123090324.732681-5-alexghiti@rivosinc.com> From: Alistair Francis Date: Tue, 24 Jan 2023 10:35:25 +1000 Message-ID: Subject: Re: [PATCH v6 4/5] riscv: Correctly set the device-tree entry 'mmu-type' To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::935; envelope-from=alistair23@gmail.com; helo=mail-ua1-x935.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 00:35:55 -0000 On Mon, Jan 23, 2023 at 7:08 PM Alexandre Ghiti wrote: > > The 'mmu-type' should reflect what the hardware is capable of so use the > new satp_mode field in RISCVCPUConfig to do that. > > Signed-off-by: Alexandre Ghiti Reviewed-by: Alistair Francis Alistair > --- > hw/riscv/virt.c | 19 ++++++++++--------- > 1 file changed, 10 insertions(+), 9 deletions(-) > > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 94ff2a1584..48d034a5f7 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -228,7 +228,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > int cpu; > uint32_t cpu_phandle; > MachineState *mc = MACHINE(s); > - char *name, *cpu_name, *core_name, *intc_name; > + uint8_t satp_mode_max; > + char *name, *cpu_name, *core_name, *intc_name, *sv_name; > > for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { > cpu_phandle = (*phandle)++; > @@ -236,14 +237,14 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, > cpu_name = g_strdup_printf("/cpus/cpu@%d", > s->soc[socket].hartid_base + cpu); > qemu_fdt_add_subnode(mc->fdt, cpu_name); > - if (riscv_feature(&s->soc[socket].harts[cpu].env, > - RISCV_FEATURE_MMU)) { > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > - (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); > - } else { > - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", > - "riscv,none"); > - } > + > + satp_mode_max = satp_mode_max_from_map( > + s->soc[socket].harts[cpu].cfg.satp_mode.map); > + sv_name = g_strdup_printf("riscv,%s", > + satp_mode_str(satp_mode_max, is_32_bit)); > + qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", sv_name); > + g_free(sv_name); > + > name = riscv_isa_string(&s->soc[socket].harts[cpu]); > qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); > g_free(name); > -- > 2.37.2 > > From MAILER-DAEMON Mon Jan 23 19:41:36 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK7NY-0001Hw-Fa for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 19:41:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK7NX-0001Hf-Pk; Mon, 23 Jan 2023 19:41:35 -0500 Received: from mail-vs1-xe30.google.com ([2607:f8b0:4864:20::e30]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK7NV-0007vQ-EJ; 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charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e30; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe30.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 00:41:36 -0000 On Mon, Jan 23, 2023 at 7:09 PM Alexandre Ghiti wrote: > > Currently, the max satp mode is set with the only constraint that it must be > implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. > > But we actually need to add another level of constraint: what the hw is > actually capable of, because currently, a linux booting on a sifive-u54 > boots in sv57 mode which is incompatible with the cpu's sv39 max > capability. > > So add a new bitmap to RISCVSATPMap which contains this capability and > initialize it in every XXX_cpu_init. > > Finally, we have the following chain of constraints: > > Qemu capability > HW capability > User choice > Software capability > > Signed-off-by: Alexandre Ghiti > --- > target/riscv/cpu.c | 78 +++++++++++++++++++++++++++++++--------------- > target/riscv/cpu.h | 8 +++-- > 2 files changed, 59 insertions(+), 27 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index e409e6ab64..19a37fee2b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -292,24 +292,39 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > g_assert_not_reached(); > } > > -/* Sets the satp mode to the max supported */ > -static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit) > +static void set_satp_mode_max_supported(RISCVCPU *cpu, > + const char *satp_mode_str, > + bool is_32_bit) > { > - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > - cpu->cfg.satp_mode.map |= > - (1 << satp_mode_from_str(is_32_bit ? "sv32" : "sv57")); > - } else { > - cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > + uint8_t satp_mode = satp_mode_from_str(satp_mode_str); > + const bool *valid_vm = is_32_bit ? valid_vm_1_10_32 : valid_vm_1_10_64; > + > + for (int i = 0; i <= satp_mode; ++i) { > + if (valid_vm[i]) { > + cpu->cfg.satp_mode.supported |= (1 << i); > + } > } > } > > +/* Sets the satp mode to the max supported */ > +static void set_satp_mode_default(RISCVCPU *cpu) > +{ > + uint8_t satp_mode = satp_mode_max_from_map(cpu->cfg.satp_mode.supported); > + > + cpu->cfg.satp_mode.map |= (1 << satp_mode); > +} > + > static void riscv_any_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > #if defined(TARGET_RISCV32) > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > + set_satp_mode_max_supported(cpu, "sv32", true); > #elif defined(TARGET_RISCV64) > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > + set_satp_mode_max_supported(cpu, "sv57", false); > #endif > set_priv_version(env, PRIV_VERSION_1_12_0); > register_cpu_props(obj); > @@ -319,18 +334,24 @@ static void riscv_any_cpu_init(Object *obj) > static void rv64_base_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > /* We set this in the realise function */ > set_misa(env, MXL_RV64, 0); > register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > + set_satp_mode_max_supported(cpu, "sv57", false); > } > > static void rv64_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > + set_satp_mode_max_supported(cpu, "sv39", false); Can we just not expose the properties on these vendor CPUs and then not worry about setting maximums? Alistair > } > > static void rv64_sifive_e_cpu_init(Object *obj) > @@ -341,6 +362,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > + set_satp_mode_max_supported(cpu, "mbare", false); > } > > static void rv128_base_cpu_init(Object *obj) > @@ -352,11 +374,13 @@ static void rv128_base_cpu_init(Object *obj) > exit(EXIT_FAILURE); > } > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > /* We set this in the realise function */ > set_misa(env, MXL_RV128, 0); > register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > + set_satp_mode_max_supported(cpu, "sv57", false); > } > #else > static void rv32_base_cpu_init(Object *obj) > @@ -367,13 +391,17 @@ static void rv32_base_cpu_init(Object *obj) > register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > + set_satp_mode_max_supported(cpu, "sv32", true); > } > > static void rv32_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > + set_satp_mode_max_supported(cpu, "sv32", true); > } > > static void rv32_sifive_e_cpu_init(Object *obj) > @@ -384,6 +412,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > + set_satp_mode_max_supported(cpu, "mbare", true); > } > > static void rv32_ibex_cpu_init(Object *obj) > @@ -394,6 +423,7 @@ static void rv32_ibex_cpu_init(Object *obj) > set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_11_0); > cpu->cfg.mmu = false; > + set_satp_mode_max_supported(cpu, "mbare", true); > cpu->cfg.epmp = true; > } > > @@ -405,6 +435,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > + set_satp_mode_max_supported(cpu, "mbare", true); > } > #endif > > @@ -696,7 +727,9 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > { > bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > - const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > + uint8_t satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > + uint8_t satp_mode_supported_max = > + satp_mode_max_from_map(cpu->cfg.satp_mode.supported); > > if (cpu->cfg.satp_mode.map == 0) { > /* > @@ -704,7 +737,7 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > * satp mode. > */ > if (cpu->cfg.satp_mode.init == 0) { > - set_satp_mode_default(cpu, rv32); > + set_satp_mode_default(cpu); > } else { > /* > * Find the lowest level that was disabled and then enable the > @@ -714,9 +747,9 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > for (int i = 1; i < 16; ++i) { > if (!(cpu->cfg.satp_mode.map & (1 << i)) && > (cpu->cfg.satp_mode.init & (1 << i)) && > - valid_vm[i]) { > + (cpu->cfg.satp_mode.supported & (1 << i))) { > for (int j = i - 1; j >= 0; --j) { > - if (valid_vm[j]) { > + if (cpu->cfg.satp_mode.supported & (1 << j)) { > cpu->cfg.satp_mode.map |= (1 << j); > break; > } > @@ -727,13 +760,12 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > } > } > > - /* Make sure the configuration asked is supported by qemu */ > - for (int i = 0; i < 16; ++i) { > - if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > - error_setg(errp, "satp_mode %s is not valid", > - satp_mode_str(i, rv32)); > - return; > - } > + /* Make sure the user asked for a supported configuration (HW and qemu) */ > + if (satp_mode_map_max > satp_mode_supported_max) { > + error_setg(errp, "satp_mode %s is higher than hw max capability %s", > + satp_mode_str(satp_mode_map_max, rv32), > + satp_mode_str(satp_mode_supported_max, rv32)); > + return; > } > > /* > @@ -741,17 +773,13 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > * the specification. > */ > if (!rv32) { > - uint8_t satp_mode_max; > - > - satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > - > - for (int i = satp_mode_max - 1; i >= 0; --i) { > + for (int i = satp_mode_map_max - 1; i >= 0; --i) { > if (!(cpu->cfg.satp_mode.map & (1 << i)) && > (cpu->cfg.satp_mode.init & (1 << i)) && > - valid_vm[i]) { > + (cpu->cfg.satp_mode.supported & (1 << i))) { > error_setg(errp, "cannot disable %s satp mode if %s " > "is enabled", satp_mode_str(i, false), > - satp_mode_str(satp_mode_max, false)); > + satp_mode_str(satp_mode_map_max, false)); > return; > } > } > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index e37177db5c..b591122099 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -416,13 +416,17 @@ struct RISCVCPUClass { > > /* > * map is a 16-bit bitmap: the most significant set bit in map is the maximum > - * satp mode that is supported. > + * satp mode that is supported. It may be chosen by the user and must respect > + * what qemu implements (valid_1_10_32/64) and what the hw is capable of > + * (supported bitmap below). > * > * init is a 16-bit bitmap used to make sure the user selected a correct > * configuration as per the specification. > + * > + * supported is a 16-bit bitmap used to reflect the hw capabilities. > */ > typedef struct { > - uint16_t map, init; > + uint16_t map, init, supported; > } RISCVSATPMap; > > struct RISCVCPUConfig { > -- > 2.37.2 > > From MAILER-DAEMON Mon Jan 23 19:58:52 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK7eG-0004VW-QR for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 19:58:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK7eF-0004VC-CY; Mon, 23 Jan 2023 19:58:51 -0500 Received: from mail-vs1-xe30.google.com ([2607:f8b0:4864:20::e30]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK7eC-00026y-B3; Mon, 23 Jan 2023 19:58:50 -0500 Received: by mail-vs1-xe30.google.com with SMTP id 187so14927284vsv.10; Mon, 23 Jan 2023 16:58:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=nlkX6SH/ooIVPtU9j9xk3s0ijI5Nl4gadVZnzHW31P8=; b=eFKelf/WRftVyBD8nFOoyE7GmBEhRGo+RR0j6qSe57UTRvzAFxO3/dXDDambmDPivH wN6Nw556/vMdtzTdEUHI0BCwNGTVExiYDVLz4u0CLOjImsdWIChYar0Prtb42eatE+h+ MQMvgzQGTvGhibCy6HWDgSqZ1KJIuErT0LoDprqtmKslPDnmg75Y6S7C+kzvuri5UohZ eEYN5/e1n8Kl6v190piS4w8uopHXVh+Mxxd+jkwRLTWQRIZvUFyWT5+E4xboK+KEWScw md1phN/9Bz3U+qpoIBBTB/88LMOwlWvT4Ge9oxhTFC6FQLl0yls8OXJujSsh4pD+FmHO rkyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=nlkX6SH/ooIVPtU9j9xk3s0ijI5Nl4gadVZnzHW31P8=; b=P3HIGDZmIY52RClBTRhLGL/+4p9izMvt8nycemkIV15OslsM6GlgxAEqRfTCswOHw4 w2n/r2Ndl17UMLA2p+bDtnEc+scWk8hmvLeTD5otR4HDb/7UR+j8EMeN292cqhl9trUk gCu6K/pzLQ+uVM0Jt0PuqCTXzJ/97wwYFSzoSDD0VCDSD/nKQ+9TkEeK/Jw9O0RbHVD3 fmkqddMN0u1JwUpnw6KgGUfvP7bYK2V0lktZVNsaqTRobx4SvoTGza8h6hAke36Gjsb7 GW1fL0J70AH+AHS93ACfubtCO5gKZEVIPj12MycqFrdQXl9wyytxsDPfPnjlGyIqb8F7 GAXA== X-Gm-Message-State: AFqh2krJ8K8OsIGSXWgC2a4JbHbzbeKjtpyjcjX2gjOaoxZygPCikeU8 /PZo5EOUqDONGAJRN32MWFVlvOGlJkMyv7PgPp8= X-Google-Smtp-Source: AMrXdXv7UCtkzCti10or3ZcorrUk5marVsWNRimkWJ4RjhSnH69Jy7TacLrbTiqZONNitk+irQFu4pvmCbxL0y7bCNI= X-Received: by 2002:a67:e14a:0:b0:3d3:f10a:4f56 with SMTP id o10-20020a67e14a000000b003d3f10a4f56mr3523586vsl.10.1674521926763; Mon, 23 Jan 2023 16:58:46 -0800 (PST) MIME-Version: 1.0 References: <20230120125950.2246378-1-apatel@ventanamicro.com> In-Reply-To: <20230120125950.2246378-1-apatel@ventanamicro.com> From: Alistair Francis Date: Tue, 24 Jan 2023 10:58:20 +1000 Message-ID: Subject: Re: [PATCH v3 0/4] Nested virtualization fixes for QEMU To: Anup Patel Cc: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar , Atish Patra , Richard Henderson , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e30; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe30.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 00:58:51 -0000 On Fri, Jan 20, 2023 at 11:01 PM Anup Patel wrote: > > This series mainly includes fixes discovered while developing nested > virtualization running on QEMU. > > These patches can also be found in the riscv_nested_fixes_v3 branch at: > https://github.com/avpatel/qemu.git > > Changes since v2: > - Dropped PATCH1 since it is already merged > - Rebased on latest riscv-to-apply.next branch of Alistair > > Changes since v1: > - Added Alistair's Reviewed-by tags to appropriate patches > - Added detailed comment block in PATCH4 > > Anup Patel (4): > target/riscv: Update VS timer whenever htimedelta changes > target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP > target/riscv: No need to re-start QEMU timer when timecmp == > UINT64_MAX > target/riscv: Ensure opcode is saved for all relevant instructions Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu_helper.c | 2 -- > target/riscv/csr.c | 16 +++++++++ > target/riscv/insn_trans/trans_rva.c.inc | 10 ++++-- > target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ > target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ > target/riscv/insn_trans/trans_rvh.c.inc | 3 ++ > target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ > target/riscv/insn_trans/trans_rvzfh.c.inc | 2 ++ > target/riscv/insn_trans/trans_svinval.c.inc | 3 ++ > target/riscv/time_helper.c | 36 ++++++++++++++++++--- > 10 files changed, 69 insertions(+), 9 deletions(-) > > -- > 2.34.1 > > From MAILER-DAEMON Mon Jan 23 20:24:29 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK833-0008B2-Av for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 20:24:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK830-0008Ae-Ce; Mon, 23 Jan 2023 20:24:26 -0500 Received: from mail-ej1-x633.google.com ([2a00:1450:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK82y-0005kP-Hn; Mon, 23 Jan 2023 20:24:26 -0500 Received: by mail-ej1-x633.google.com with SMTP id az20so35265295ejc.1; Mon, 23 Jan 2023 17:24:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=0ZIuz7MMINQls+Wp5fdZcpUvEDFsnJfZ+7hA5iQJwcw=; b=Klfz1n5KJAEbA0Xn90MH7U2B8sz6cx0p+5j8Cm7BEsffvuAChuIfBidxV+/sFH0fCu P2mvefIcztw18jW5VCGCniVlEVhmWZAsu8Xf7OecHOOcuKin/70x14esHq0UanIBTagm lO26LHGwD7HSUQ75jq/O+//sLJVLVMwh4F4ViQXYtrpar60ZeH4jyRWxk4dv9l9kD/6C p5NxPFckAOP/27+JTI5JYonntdrUSBTUN/0MCI31N2E9UsHr0pkscexgm/ga2GhtL+9G BrAk3oNuAC1+xzyzwR1A8PPTNxER3Hoc35AfS07BLuen5VY3cLwPb8YvafvZLyNSCEMS 5xEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=0ZIuz7MMINQls+Wp5fdZcpUvEDFsnJfZ+7hA5iQJwcw=; b=DeH6q1VrmJua5fqlokrk/TOZIeAvDFMifFgVHR7IF5JmBdtvoL7bdqUkPM26gLbVhs ECO0QFmiQmcCS+6kSjXsEiTjDWH09Y2OUWwOTXSOfAbmRR+tXMhO8EAG9z8WXmGS+OUB NTK1FswzwO1Rhr/lWBV+IPOe3GcSojn47E8JPJEzGW0ugf1iIae7v5Zbbv7XUvDKPtpP aXRARXXvplF59C7gqSRXkwoHQcny6mtiMVAfDKiktoSpM0FvuS/mIrxeibT8prqy8vLw ho2c4kZx7s8i1De23/+h8EpginQI+BPnklOwOAfIPlhbTskxWwyvXBs9505aZofW5DeZ usPQ== X-Gm-Message-State: AFqh2kqMTQxAtS45D+QgY8qNRdZb+NHEZ7K8kDvWSba9AbCnYas4246z YDBkNRv8EjyA9bAqZx+MhL+1dnG92UPqu7byN4Q= X-Google-Smtp-Source: AMrXdXuJs1/tHs4qfRjLfOjfmyc9sGOv9fyxctdD5YanFZ0OaZ6Nri6jyjl9D5BevZj3UWKtPlfi469Zsazf6nw/Y2I= X-Received: by 2002:a17:906:555:b0:85f:5ff0:3cb0 with SMTP id k21-20020a170906055500b0085f5ff03cb0mr3274651eja.341.1674523462044; Mon, 23 Jan 2023 17:24:22 -0800 (PST) MIME-Version: 1.0 References: <20230123035754.75553-1-alistair.francis@opensource.wdc.com> In-Reply-To: <20230123035754.75553-1-alistair.francis@opensource.wdc.com> From: Bin Meng Date: Tue, 24 Jan 2023 09:24:10 +0800 Message-ID: Subject: Re: [PATCH] hw/riscv: boot: Don't use CSRs if they are disabled To: Alistair Francis Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, Bin Meng , alistair23@gmail.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 01:24:27 -0000 On Mon, Jan 23, 2023 at 11:58 AM Alistair Francis wrote: > > From: Alistair Francis > > If the CSRs and CSR instructions are disabled because the Zicsr > extension isn't enabled then we want to make sure we don't run any CSR > instructions in the boot ROM. > > This patches removes the CSR instructions from the reset-vec if the > extension isn't enabled. We replace the instruction with a NOP instead. > > Note that we don't do this for the SiFive U machine, as we are modelling > the hardware in that case. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1447 > Signed-off-by: Alistair Francis > --- > hw/riscv/boot.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 2594276223..cb27798a25 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -356,6 +356,15 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts > reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ > } > > + if (!harts->harts[0].cfg.ext_icsr) { > + /* > + * The Zicsr extension has been disabled, so let's ensure we don't > + * run the CSR instruction. Let's fill the address with a non > + * compressed nop. > + */ > + reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */ > + } This is fine for a UP system. I am not sure how SMP can be supported without Zicsr as we need to assign hartid in a0. > + > /* copy in the reset vector in little_endian byte order */ > for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { > reset_vec[i] = cpu_to_le32(reset_vec[i]); > -- Regards, Bin From MAILER-DAEMON Mon Jan 23 20:42:41 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pK8Ke-0003tS-BR for mharc-qemu-riscv@gnu.org; Mon, 23 Jan 2023 20:42:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pK8KY-0003t3-17; Mon, 23 Jan 2023 20:42:34 -0500 Received: from mail-vs1-xe2e.google.com ([2607:f8b0:4864:20::e2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pK8KW-0008I3-BT; Mon, 23 Jan 2023 20:42:33 -0500 Received: by mail-vs1-xe2e.google.com with SMTP id 187so14999963vsv.10; Mon, 23 Jan 2023 17:42:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=FU7jGxZFLK8s7TG/kSqqFuKrnDJwir6nsjwswJ5QelI=; b=GZMyRraVmiRzabG8i9WBS4OP9CqvOSNRtx0K3Cjjlddm/yecDY6EDiZXh3awdD80hA Nw2S4RhO6V+NWgLCIk/Y4hRqASqO7E8nVqOP2Gc5nJoCCDwlq0OHWJWgaBSomUIEhfij 1Je4jVzwK+5b22VJk1nYEK69Gz6t+pTkNmslYklDk3CF+a5/WMRbillFOfi/GkyoRqxX utUuTeZwY01rrD+ihRjjoMth1kUQDtqO75kc/0VMsJBDMUrPPS1QS5uFPzQXovCJANsG AW/eK3b3ZW66GdOcFO8ROn1rKcQx9SimjpPLcw8Cn5eXDNJi2T7GOlBZ5+ah4PsqKgbQ HmzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=FU7jGxZFLK8s7TG/kSqqFuKrnDJwir6nsjwswJ5QelI=; b=poRdSArpu+uaI2NrXZJQqw2mj2rMWcp57jVlGH3+aTUkERwMgCtCg0nhn5Hr+L3ArM TJKnI/0ipNKpH23M/LC1/tcDS8V7LJh8LldBINafgyZ+iWvJktdIVJc7QPyQy6IfJHZi bcoS8Ym6zopadWDkNIiijGf6Q31CTpqc7Lpv0AlFTfqt8VDr+FePCgAkIsgmjOOfxRPn fNgYnf+B7vo92yo8qMyUeP8elFmxGsU7w7+u25MsPxA25fHozmcxF0yh2491MThaOwbQ TBdRZhYZvOy8SYDAquvAHknWDHEDpclfC96ZzNqEFa9XMi8uDulpJf8a7QJhlAAdhclY 5k5Q== X-Gm-Message-State: AFqh2krkWHYD0V24EC1exqDq412IDyyjLSIx/8vtlrfR/ZzESDG4pS9J TrTq0Q9kBEryCK7CqR/GsF40CqnFe6AOoPM6xcA= X-Google-Smtp-Source: AMrXdXv+aaxL1/fqoVmUs9V+DeKmgBy8c3N2VEAV/aH4WdUNteY3U8V/qoRGnmk8sERJWM7vMraGuFOEJwBV90uMJsc= X-Received: by 2002:a67:e14a:0:b0:3d3:f10a:4f56 with SMTP id o10-20020a67e14a000000b003d3f10a4f56mr3535517vsl.10.1674524548266; Mon, 23 Jan 2023 17:42:28 -0800 (PST) MIME-Version: 1.0 References: <20230123035754.75553-1-alistair.francis@opensource.wdc.com> In-Reply-To: From: Alistair Francis Date: Tue, 24 Jan 2023 11:42:01 +1000 Message-ID: Subject: Re: [PATCH] hw/riscv: boot: Don't use CSRs if they are disabled To: Bin Meng Cc: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e2e; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 01:42:38 -0000 On Tue, Jan 24, 2023 at 11:24 AM Bin Meng wrote: > > On Mon, Jan 23, 2023 at 11:58 AM Alistair Francis > wrote: > > > > From: Alistair Francis > > > > If the CSRs and CSR instructions are disabled because the Zicsr > > extension isn't enabled then we want to make sure we don't run any CSR > > instructions in the boot ROM. > > > > This patches removes the CSR instructions from the reset-vec if the > > extension isn't enabled. We replace the instruction with a NOP instead. > > > > Note that we don't do this for the SiFive U machine, as we are modelling > > the hardware in that case. > > > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1447 > > Signed-off-by: Alistair Francis > > --- > > hw/riscv/boot.c | 9 +++++++++ > > 1 file changed, 9 insertions(+) > > > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > > index 2594276223..cb27798a25 100644 > > --- a/hw/riscv/boot.c > > +++ b/hw/riscv/boot.c > > @@ -356,6 +356,15 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts > > reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ > > } > > > > + if (!harts->harts[0].cfg.ext_icsr) { > > + /* > > + * The Zicsr extension has been disabled, so let's ensure we don't > > + * run the CSR instruction. Let's fill the address with a non > > + * compressed nop. > > + */ > > + reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */ > > + } > > This is fine for a UP system. I am not sure how SMP can be supported > without Zicsr as we need to assign hartid in a0. Yeah. My thinking was that no one would be using a multicore system without Zicsr as it's such a core extension. If they are running without Zicsr they have probably hard coded a lot of things anyway and don't expect this to work. In general I think it's pretty rare to even run a RISC-V core without Zicsr at all. Alistair > > > + > > /* copy in the reset vector in little_endian byte order */ > > for (i = 0; i < ARRAY_SIZE(reset_vec); i++) { > > reset_vec[i] = cpu_to_le32(reset_vec[i]); > > -- > > Regards, > Bin From MAILER-DAEMON Tue Jan 24 04:13:21 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKFMm-0007EK-Sz for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 04:13:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKFMk-0007Dp-5N for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 04:13:18 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKFMf-0006oc-SS for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 04:13:17 -0500 Received: by mail-wm1-x32a.google.com with SMTP id fl11-20020a05600c0b8b00b003daf72fc844so12353983wmb.0 for ; Tue, 24 Jan 2023 01:13:12 -0800 (PST) DKIM-Signature: v=1; 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Tue, 24 Jan 2023 01:13:11 -0800 (PST) MIME-Version: 1.0 References: <20230123090324.732681-1-alexghiti@rivosinc.com> <20230123090324.732681-6-alexghiti@rivosinc.com> In-Reply-To: From: Alexandre Ghiti Date: Tue, 24 Jan 2023 10:13:00 +0100 Message-ID: Subject: Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities To: Alistair Francis Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 09:13:18 -0000 Hi Alistair, On Tue, Jan 24, 2023 at 1:41 AM Alistair Francis wrote: > > On Mon, Jan 23, 2023 at 7:09 PM Alexandre Ghiti wrote: > > > > Currently, the max satp mode is set with the only constraint that it must be > > implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. > > > > But we actually need to add another level of constraint: what the hw is > > actually capable of, because currently, a linux booting on a sifive-u54 > > boots in sv57 mode which is incompatible with the cpu's sv39 max > > capability. > > > > So add a new bitmap to RISCVSATPMap which contains this capability and > > initialize it in every XXX_cpu_init. > > > > Finally, we have the following chain of constraints: > > > > Qemu capability > HW capability > User choice > Software capability > > > > Signed-off-by: Alexandre Ghiti > > --- > > target/riscv/cpu.c | 78 +++++++++++++++++++++++++++++++--------------- > > target/riscv/cpu.h | 8 +++-- > > 2 files changed, 59 insertions(+), 27 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index e409e6ab64..19a37fee2b 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -292,24 +292,39 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > > g_assert_not_reached(); > > } > > > > -/* Sets the satp mode to the max supported */ > > -static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit) > > +static void set_satp_mode_max_supported(RISCVCPU *cpu, > > + const char *satp_mode_str, > > + bool is_32_bit) > > { > > - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > > - cpu->cfg.satp_mode.map |= > > - (1 << satp_mode_from_str(is_32_bit ? "sv32" : "sv57")); > > - } else { > > - cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > > + uint8_t satp_mode = satp_mode_from_str(satp_mode_str); > > + const bool *valid_vm = is_32_bit ? valid_vm_1_10_32 : valid_vm_1_10_64; > > + > > + for (int i = 0; i <= satp_mode; ++i) { > > + if (valid_vm[i]) { > > + cpu->cfg.satp_mode.supported |= (1 << i); > > + } > > } > > } > > > > +/* Sets the satp mode to the max supported */ > > +static void set_satp_mode_default(RISCVCPU *cpu) > > +{ > > + uint8_t satp_mode = satp_mode_max_from_map(cpu->cfg.satp_mode.supported); > > + > > + cpu->cfg.satp_mode.map |= (1 << satp_mode); > > +} > > + > > static void riscv_any_cpu_init(Object *obj) > > { > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > + RISCVCPU *cpu = RISCV_CPU(obj); > > + > > #if defined(TARGET_RISCV32) > > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > > + set_satp_mode_max_supported(cpu, "sv32", true); > > #elif defined(TARGET_RISCV64) > > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > > + set_satp_mode_max_supported(cpu, "sv57", false); > > #endif > > set_priv_version(env, PRIV_VERSION_1_12_0); > > register_cpu_props(obj); > > @@ -319,18 +334,24 @@ static void riscv_any_cpu_init(Object *obj) > > static void rv64_base_cpu_init(Object *obj) > > { > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > + RISCVCPU *cpu = RISCV_CPU(obj); > > + > > /* We set this in the realise function */ > > set_misa(env, MXL_RV64, 0); > > register_cpu_props(obj); > > /* Set latest version of privileged specification */ > > set_priv_version(env, PRIV_VERSION_1_12_0); > > + set_satp_mode_max_supported(cpu, "sv57", false); > > } > > > > static void rv64_sifive_u_cpu_init(Object *obj) > > { > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > + RISCVCPU *cpu = RISCV_CPU(obj); > > + > > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > > set_priv_version(env, PRIV_VERSION_1_10_0); > > + set_satp_mode_max_supported(cpu, "sv39", false); > > Can we just not expose the properties on these vendor CPUs and then > not worry about setting maximums? > I'm not sure I understand: the properties are actually not exposed to the vendor cpus from what I see (no calls to register_cpu_props). The problem this patch fixes is that the only constraint on satp is valid_vm_1_10_32/64, which reflects the qemu capabilities: as said in the commit log, a sifive-u54 will allow a kernel to boot in sv57, and not sv39 as it should. This patch only takes advantage of the newly introduced RISCVSATPMap structure to fix this issue, I should maybe emphasize in the commit description that this is a fix. Alex > Alistair > > > } > > > > static void rv64_sifive_e_cpu_init(Object *obj) > > @@ -341,6 +362,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) > > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); > > set_priv_version(env, PRIV_VERSION_1_10_0); > > cpu->cfg.mmu = false; > > + set_satp_mode_max_supported(cpu, "mbare", false); > > } > > > > static void rv128_base_cpu_init(Object *obj) > > @@ -352,11 +374,13 @@ static void rv128_base_cpu_init(Object *obj) > > exit(EXIT_FAILURE); > > } > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > + RISCVCPU *cpu = RISCV_CPU(obj); > > /* We set this in the realise function */ > > set_misa(env, MXL_RV128, 0); > > register_cpu_props(obj); > > /* Set latest version of privileged specification */ > > set_priv_version(env, PRIV_VERSION_1_12_0); > > + set_satp_mode_max_supported(cpu, "sv57", false); > > } > > #else > > static void rv32_base_cpu_init(Object *obj) > > @@ -367,13 +391,17 @@ static void rv32_base_cpu_init(Object *obj) > > register_cpu_props(obj); > > /* Set latest version of privileged specification */ > > set_priv_version(env, PRIV_VERSION_1_12_0); > > + set_satp_mode_max_supported(cpu, "sv32", true); > > } > > > > static void rv32_sifive_u_cpu_init(Object *obj) > > { > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > + RISCVCPU *cpu = RISCV_CPU(obj); > > + > > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > > set_priv_version(env, PRIV_VERSION_1_10_0); > > + set_satp_mode_max_supported(cpu, "sv32", true); > > } > > > > static void rv32_sifive_e_cpu_init(Object *obj) > > @@ -384,6 +412,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) > > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); > > set_priv_version(env, PRIV_VERSION_1_10_0); > > cpu->cfg.mmu = false; > > + set_satp_mode_max_supported(cpu, "mbare", true); > > } > > > > static void rv32_ibex_cpu_init(Object *obj) > > @@ -394,6 +423,7 @@ static void rv32_ibex_cpu_init(Object *obj) > > set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); > > set_priv_version(env, PRIV_VERSION_1_11_0); > > cpu->cfg.mmu = false; > > + set_satp_mode_max_supported(cpu, "mbare", true); > > cpu->cfg.epmp = true; > > } > > > > @@ -405,6 +435,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); > > set_priv_version(env, PRIV_VERSION_1_10_0); > > cpu->cfg.mmu = false; > > + set_satp_mode_max_supported(cpu, "mbare", true); > > } > > #endif > > > > @@ -696,7 +727,9 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > > static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > > { > > bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > > - const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > > + uint8_t satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > > + uint8_t satp_mode_supported_max = > > + satp_mode_max_from_map(cpu->cfg.satp_mode.supported); > > > > if (cpu->cfg.satp_mode.map == 0) { > > /* > > @@ -704,7 +737,7 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > > * satp mode. > > */ > > if (cpu->cfg.satp_mode.init == 0) { > > - set_satp_mode_default(cpu, rv32); > > + set_satp_mode_default(cpu); > > } else { > > /* > > * Find the lowest level that was disabled and then enable the > > @@ -714,9 +747,9 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > > for (int i = 1; i < 16; ++i) { > > if (!(cpu->cfg.satp_mode.map & (1 << i)) && > > (cpu->cfg.satp_mode.init & (1 << i)) && > > - valid_vm[i]) { > > + (cpu->cfg.satp_mode.supported & (1 << i))) { > > for (int j = i - 1; j >= 0; --j) { > > - if (valid_vm[j]) { > > + if (cpu->cfg.satp_mode.supported & (1 << j)) { > > cpu->cfg.satp_mode.map |= (1 << j); > > break; > > } > > @@ -727,13 +760,12 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > > } > > } > > > > - /* Make sure the configuration asked is supported by qemu */ > > - for (int i = 0; i < 16; ++i) { > > - if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > > - error_setg(errp, "satp_mode %s is not valid", > > - satp_mode_str(i, rv32)); > > - return; > > - } > > + /* Make sure the user asked for a supported configuration (HW and qemu) */ > > + if (satp_mode_map_max > satp_mode_supported_max) { > > + error_setg(errp, "satp_mode %s is higher than hw max capability %s", > > + satp_mode_str(satp_mode_map_max, rv32), > > + satp_mode_str(satp_mode_supported_max, rv32)); > > + return; > > } > > > > /* > > @@ -741,17 +773,13 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > > * the specification. > > */ > > if (!rv32) { > > - uint8_t satp_mode_max; > > - > > - satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > > - > > - for (int i = satp_mode_max - 1; i >= 0; --i) { > > + for (int i = satp_mode_map_max - 1; i >= 0; --i) { > > if (!(cpu->cfg.satp_mode.map & (1 << i)) && > > (cpu->cfg.satp_mode.init & (1 << i)) && > > - valid_vm[i]) { > > + (cpu->cfg.satp_mode.supported & (1 << i))) { > > error_setg(errp, "cannot disable %s satp mode if %s " > > "is enabled", satp_mode_str(i, false), > > - satp_mode_str(satp_mode_max, false)); > > + satp_mode_str(satp_mode_map_max, false)); > > return; > > } > > } > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index e37177db5c..b591122099 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -416,13 +416,17 @@ struct RISCVCPUClass { > > > > /* > > * map is a 16-bit bitmap: the most significant set bit in map is the maximum > > - * satp mode that is supported. > > + * satp mode that is supported. It may be chosen by the user and must respect > > + * what qemu implements (valid_1_10_32/64) and what the hw is capable of > > + * (supported bitmap below). > > * > > * init is a 16-bit bitmap used to make sure the user selected a correct > > * configuration as per the specification. > > + * > > + * supported is a 16-bit bitmap used to reflect the hw capabilities. > > */ > > typedef struct { > > - uint16_t map, init; > > + uint16_t map, init, supported; > > } RISCVSATPMap; > > > > struct RISCVCPUConfig { > > -- > > 2.37.2 > > > > From MAILER-DAEMON Tue Jan 24 04:56:46 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKG2m-0002KC-JR for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 04:56:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKG2g-0002Jd-9s for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 04:56:39 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKG2R-0005zb-RW for qemu-riscv@nongnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 09:56:40 -0000 Hi Andrew, On Mon, Jan 23, 2023 at 11:11 AM Andrew Jones wrote: > > On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote: > > RISC-V specifies multiple sizes for addressable memory and Linux probes for > > the machine's support at startup via the satp CSR register (done in > > csr.c:validate_vm). > > > > As per the specification, sv64 must support sv57, which in turn must > > support sv48...etc. So we can restrict machine support by simply setting the > > "highest" supported mode and the bare mode is always supported. > > > > You can set the satp mode using the new properties "sv32", "sv39", "sv48", > > "sv57" and "sv64" as follows: > > -cpu rv64,sv57=on # Linux will boot using sv57 scheme > > -cpu rv64,sv39=on # Linux will boot using sv39 scheme > > -cpu rv64,sv57=off # Linux will boot using sv48 scheme > > -cpu rv64 # Linux will boot using sv57 scheme by default > > > > We take the highest level set by the user: > > -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme > > > > We make sure that invalid configurations are rejected: > > -cpu rv64,sv32=on # Can't enable 32-bit satp mode in 64-bit > > The property doesn't exist for rv64 anymore, so I'm not sure we need > this info in the commit message. Sorry about that... > > > -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are > > # enabled > > > > We accept "redundant" configurations: > > -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme > > > > And contradictory configurations: > > -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme > > > > In addition, we now correctly set the device-tree entry 'mmu-type' using > > those new properties. > > > > Co-Developed-by: Ludovic Henry > > Signed-off-by: Ludovic Henry > > Signed-off-by: Alexandre Ghiti > > --- > > target/riscv/cpu.c | 204 +++++++++++++++++++++++++++++++++++++++++++++ > > target/riscv/cpu.h | 19 +++++ > > target/riscv/csr.c | 12 ++- > > 3 files changed, 228 insertions(+), 7 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 7181b34f86..e409e6ab64 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -27,6 +27,7 @@ > > #include "time_helper.h" > > #include "exec/exec-all.h" > > #include "qapi/error.h" > > +#include "qapi/visitor.h" > > #include "qemu/error-report.h" > > #include "hw/qdev-properties.h" > > #include "migration/vmstate.h" > > @@ -229,6 +230,79 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) > > env->vext_ver = vext_ver; > > } > > > > +static uint8_t satp_mode_from_str(const char *satp_mode_str) > > +{ > > + if (!strncmp(satp_mode_str, "mbare", 5)) { > > + return VM_1_10_MBARE; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv32", 4)) { > > + return VM_1_10_SV32; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv39", 4)) { > > + return VM_1_10_SV39; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv48", 4)) { > > + return VM_1_10_SV48; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv57", 4)) { > > + return VM_1_10_SV57; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv64", 4)) { > > + return VM_1_10_SV64; > > + } > > + > > + g_assert_not_reached(); > > +} > > + > > +uint8_t satp_mode_max_from_map(uint32_t map) > > +{ > > + /* map here has at least one bit set, so no problem with clz */ > > + return 31 - __builtin_clz(map); > > +} > > + > > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > > +{ > > + if (is_32_bit) { > > + switch (satp_mode) { > > + case VM_1_10_SV32: > > + return "sv32"; > > + case VM_1_10_MBARE: > > + return "none"; > > + } > > + } else { > > + switch (satp_mode) { > > + case VM_1_10_SV64: > > + return "sv64"; > > + case VM_1_10_SV57: > > + return "sv57"; > > + case VM_1_10_SV48: > > + return "sv48"; > > + case VM_1_10_SV39: > > + return "sv39"; > > + case VM_1_10_MBARE: > > + return "none"; > > + } > > + } > > + > > + g_assert_not_reached(); > > +} > > + > > +/* Sets the satp mode to the max supported */ > > +static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit) > > +{ > > + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > > + cpu->cfg.satp_mode.map |= > > + (1 << satp_mode_from_str(is_32_bit ? "sv32" : "sv57")); > > + } else { > > + cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > > + } > > +} > > + > > static void riscv_any_cpu_init(Object *obj) > > { > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > @@ -619,6 +693,82 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > > } > > } > > > > +static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > > +{ > > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > > + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > > + > > + if (cpu->cfg.satp_mode.map == 0) { > > + /* > > + * If unset by both the user and the cpu, we fallback to the default > > + * satp mode. > > + */ > > nit: I'd put the above comment under the if init == 0 below. Ok, and I fixed the comment as the cpu does not set map at all, we set map in set_satp_mode_default using qemu/hw capabilities, thanks. > > > + if (cpu->cfg.satp_mode.init == 0) { > > + set_satp_mode_default(cpu, rv32); > > + } else { > > + /* > > + * Find the lowest level that was disabled and then enable the > > + * first valid level below which can be found in > > + * valid_vm_1_10_32/64. > > + */ > > + for (int i = 1; i < 16; ++i) { > > + if (!(cpu->cfg.satp_mode.map & (1 << i)) && > > + (cpu->cfg.satp_mode.init & (1 << i)) && > > + valid_vm[i]) { > > + for (int j = i - 1; j >= 0; --j) { > > + if (valid_vm[j]) { > > + cpu->cfg.satp_mode.map |= (1 << j); > > + break; > > We don't want to break here, we want fully populate the map. Otherwise the > future coming qmp_query_cpu_model_expansion() is going to produce results > like rv39=off,rv48=off,rv57=on,rv64=off for the default because it gets > its info from cpu_riscv_get_satp(), which only checks the map. Ok then I'll "expand" the map too in case map != 0. > > > + } > > + } > > + break; > > + } > > + } > > + } > > + } > > + > > + /* Make sure the configuration asked is supported by qemu */ > > + for (int i = 0; i < 16; ++i) { > > + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > > + error_setg(errp, "satp_mode %s is not valid", > > + satp_mode_str(i, rv32)); > > + return; > > + } > > + } > > + > > + /* > > + * Make sure the user did not ask for an invalid configuration as per > > + * the specification. > > + */ > > + if (!rv32) { > > + uint8_t satp_mode_max; > > + > > + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > > + > > + for (int i = satp_mode_max - 1; i >= 0; --i) { > > + if (!(cpu->cfg.satp_mode.map & (1 << i)) && > > + (cpu->cfg.satp_mode.init & (1 << i)) && > > + valid_vm[i]) { > > + error_setg(errp, "cannot disable %s satp mode if %s " > > + "is enabled", satp_mode_str(i, false), > > + satp_mode_str(satp_mode_max, false)); > > + return; > > + } > > + } > > + } > > +} > > + > > +static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > > +{ > > + Error *local_err = NULL; > > + > > + riscv_cpu_satp_mode_finalize(cpu, &local_err); > > + if (local_err != NULL) { > > + error_propagate(errp, local_err); > > + return; > > + } > > +} > > + > > static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > { > > CPUState *cs = CPU(dev); > > @@ -919,6 +1069,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > } > > #endif > > > > + riscv_cpu_finalize_features(cpu, &local_err); > > + if (local_err != NULL) { > > + error_propagate(errp, local_err); > > + return; > > + } > > + > > riscv_cpu_register_gdb_regs_for_features(cs); > > > > qemu_init_vcpu(cs); > > @@ -927,6 +1083,52 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > mcc->parent_realize(dev, errp); > > } > > > > +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, > > + void *opaque, Error **errp) > > +{ > > + RISCVSATPMap *satp_map = opaque; > > + uint8_t satp = satp_mode_from_str(name); > > + bool value; > > + > > + value = (satp_map->map & (1 << satp)); > > + > > + visit_type_bool(v, name, &value, errp); > > +} > > + > > +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, > > + void *opaque, Error **errp) > > +{ > > + RISCVSATPMap *satp_map = opaque; > > + uint8_t satp = satp_mode_from_str(name); > > + bool value; > > + > > + if (!visit_type_bool(v, name, &value, errp)) { > > + return; > > + } > > + > > + satp_map->map = deposit32(satp_map->map, satp, 1, value); > > + satp_map->init |= 1 << satp; > > +} > > + > > +static void riscv_add_satp_mode_properties(Object *obj) > > +{ > > + RISCVCPU *cpu = RISCV_CPU(obj); > > + > > + if (cpu->env.misa_mxl == MXL_RV32) { > > + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + } else { > > + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + } > > +} > > + > > #ifndef CONFIG_USER_ONLY > > static void riscv_cpu_set_irq(void *opaque, int irq, int level) > > { > > @@ -1091,6 +1293,8 @@ static void register_cpu_props(Object *obj) > > for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > > qdev_property_add_static(dev, prop); > > } > > + > > + riscv_add_satp_mode_properties(obj); > > } > > > > static Property riscv_cpu_properties[] = { > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index f5609b62a2..e37177db5c 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -27,6 +27,7 @@ > > #include "qom/object.h" > > #include "qemu/int128.h" > > #include "cpu_bits.h" > > +#include "qapi/qapi-types-common.h" > > > > #define TCG_GUEST_DEFAULT_MO 0 > > > > @@ -413,6 +414,17 @@ struct RISCVCPUClass { > > ResettablePhases parent_phases; > > }; > > > > +/* > > + * map is a 16-bit bitmap: the most significant set bit in map is the maximum > > + * satp mode that is supported. > > + * > > + * init is a 16-bit bitmap used to make sure the user selected a correct > > + * configuration as per the specification. > > + */ > > +typedef struct { > > + uint16_t map, init; > > +} RISCVSATPMap; > > + > > struct RISCVCPUConfig { > > bool ext_i; > > bool ext_e; > > @@ -488,6 +500,8 @@ struct RISCVCPUConfig { > > bool debug; > > > > bool short_isa_string; > > + > > + RISCVSATPMap satp_mode; > > }; > > > > typedef struct RISCVCPUConfig RISCVCPUConfig; > > @@ -794,9 +808,14 @@ enum riscv_pmu_event_idx { > > /* CSR function table */ > > extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; > > > > +extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; > > + > > void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); > > void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); > > > > void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); > > > > +uint8_t satp_mode_max_from_map(uint32_t map); > > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); > > + > > #endif /* RISCV_CPU_H */ > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 6b157806a5..3c02055825 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -1117,12 +1117,12 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; > > static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; > > static const target_ulong vsip_writable_mask = MIP_VSSIP; > > > > -static const bool valid_vm_1_10_32[16] = { > > +const bool valid_vm_1_10_32[16] = { > > [VM_1_10_MBARE] = true, > > [VM_1_10_SV32] = true > > }; > > > > -static const bool valid_vm_1_10_64[16] = { > > +const bool valid_vm_1_10_64[16] = { > > [VM_1_10_MBARE] = true, > > [VM_1_10_SV39] = true, > > [VM_1_10_SV48] = true, > > @@ -1211,11 +1211,9 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, > > > > static bool validate_vm(CPURISCVState *env, target_ulong vm) > > { > > - if (riscv_cpu_mxl(env) == MXL_RV32) { > > - return valid_vm_1_10_32[vm & 0xf]; > > - } else { > > - return valid_vm_1_10_64[vm & 0xf]; > > - } > > + RISCVCPU *cpu = RISCV_CPU(env_cpu(env)); > > + > > + return ((vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map)); > > } > > > > static RISCVException write_mstatus(CPURISCVState *env, int csrno, > > -- > > 2.37.2 > > > > Thanks, > drew From MAILER-DAEMON Tue Jan 24 04:56:52 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKG2u-0002LC-7h for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 04:56:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKG2t-0002Kw-BM for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 04:56:51 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKG2r-00065C-8I for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 04:56:51 -0500 Received: by mail-wm1-x334.google.com with SMTP id f25-20020a1c6a19000000b003da221fbf48so10491374wmc.1 for ; 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Tue, 24 Jan 2023 01:56:47 -0800 (PST) MIME-Version: 1.0 References: <20230123090324.732681-1-alexghiti@rivosinc.com> <20230123090324.732681-4-alexghiti@rivosinc.com> <20230123101429.a3x6vlatbvbp7kox@orel> In-Reply-To: <20230123101429.a3x6vlatbvbp7kox@orel> From: Alexandre Ghiti Date: Tue, 24 Jan 2023 10:56:37 +0100 Message-ID: Subject: Re: [PATCH v6 3/5] riscv: Allow user to set the satp mode To: Andrew Jones Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x334.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 09:56:51 -0000 On Mon, Jan 23, 2023 at 11:14 AM Andrew Jones wrote: > > On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote: > > RISC-V specifies multiple sizes for addressable memory and Linux probes for > > the machine's support at startup via the satp CSR register (done in > > csr.c:validate_vm). > > > > As per the specification, sv64 must support sv57, which in turn must > > support sv48...etc. So we can restrict machine support by simply setting the > > "highest" supported mode and the bare mode is always supported. > > > > You can set the satp mode using the new properties "sv32", "sv39", "sv48", > > "sv57" and "sv64" as follows: > > -cpu rv64,sv57=on # Linux will boot using sv57 scheme > > -cpu rv64,sv39=on # Linux will boot using sv39 scheme > > -cpu rv64,sv57=off # Linux will boot using sv48 scheme > > -cpu rv64 # Linux will boot using sv57 scheme by default > > > > We take the highest level set by the user: > > -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme > > > > We make sure that invalid configurations are rejected: > > -cpu rv64,sv32=on # Can't enable 32-bit satp mode in 64-bit > > -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are > > # enabled > > > > We accept "redundant" configurations: > > -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme > > > > And contradictory configurations: > > -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme > > > > In addition, we now correctly set the device-tree entry 'mmu-type' using > > those new properties. > > This sentence no longer applies to this patch. Sorry about that and thanks for noticing. Alex > > Thanks, > drew From MAILER-DAEMON Tue Jan 24 05:00:38 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKG6X-0004Ne-0o for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 05:00:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKG6Q-0004Mo-BB for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 05:00:32 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKG6M-00070D-V1 for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 05:00:30 -0500 Received: by mail-wr1-x430.google.com with SMTP id d14so9628266wrr.9 for ; Tue, 24 Jan 2023 02:00:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; 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Tue, 24 Jan 2023 02:00:25 -0800 (PST) MIME-Version: 1.0 References: <20230123090324.732681-1-alexghiti@rivosinc.com> <20230123090324.732681-4-alexghiti@rivosinc.com> <20230123102912.kq5c47nzeg7ufkma@orel> In-Reply-To: <20230123102912.kq5c47nzeg7ufkma@orel> From: Alexandre Ghiti Date: Tue, 24 Jan 2023 11:00:14 +0100 Message-ID: Subject: Re: [PATCH v6 3/5] riscv: Allow user to set the satp mode To: Andrew Jones Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 10:00:32 -0000 On Mon, Jan 23, 2023 at 11:29 AM Andrew Jones wrote: > > On Mon, Jan 23, 2023 at 10:03:22AM +0100, Alexandre Ghiti wrote: > ... > > +/* Sets the satp mode to the max supported */ > > +static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit) > > +{ > > nit: When passing in the cpu object pointer there's no need to also pass > is_32_bit, we can just use it from the pointer, cpu->env.misa_mxl == MXL_RV32 Ok Thanks, Alex > > Thanks, > drew From MAILER-DAEMON Tue Jan 24 05:08:34 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKGED-0006dS-QC for mharc-qemu-riscv@gnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=/SF36r8i+Z8W4TYL8FvIHMioH37dqgLJBRI+fSQpfWc=; b=GtJsPuynvZmLbXTAsORfFnK8iW5xXdI6OUmF7tRXPGy5VwfmZ36iJtuzHaO+Ycd7BA f6GSjy9ZIdnC+6lw45ftt/QNpIHuqgAiYwuDyGmwUY0e3/M3kRFGDStVaAOPmiqLOZUB anx98psdoq9IPl86NDuuZ4Az2z8aTE4PDODeqJRKjXrLxycdzGW9cvefcZ7jFm+G6emK X01K3+F5dDxUeaGsgGcohYeILAigYJsAi1TKhWDicQBWQz/K81KgoeBg25HU5nHADv1M XhReprGSlfXFaOpx65oq9zEEYKO8HzrgbKjZUEFYvV6857Yef8As40OwAGpnx9a91190 Z9aA== X-Gm-Message-State: AFqh2kpBSAo/rSg+oD+3PraSDqSrYgdkvZzUdjBrEHPkY3JcJQFCDGmy /6iHCCLfjdLp04Vqp/5tYDRkJyb1WtAPi72bsLJV7Q== X-Google-Smtp-Source: AMrXdXukbsxDm0D742UTfUIfaGrcBxOjXzH/zL+8iaHBAQQzA5pF1sw9AxggkFl7XJyiAERl4MqjjXNU/KqsnuAQTCc= X-Received: by 2002:a05:600c:35c6:b0:3d1:e710:9905 with SMTP id r6-20020a05600c35c600b003d1e7109905mr1236227wmq.81.1674554884271; Tue, 24 Jan 2023 02:08:04 -0800 (PST) MIME-Version: 1.0 References: <20230123090324.732681-1-alexghiti@rivosinc.com> <20230123090324.732681-6-alexghiti@rivosinc.com> <20230123105112.zidabgiswkpnzo5r@orel> In-Reply-To: <20230123105112.zidabgiswkpnzo5r@orel> From: Alexandre Ghiti Date: Tue, 24 Jan 2023 11:07:53 +0100 Message-ID: Subject: Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities To: Andrew Jones Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 10:08:17 -0000 On Mon, Jan 23, 2023 at 11:51 AM Andrew Jones wrote: > > On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote: > > Currently, the max satp mode is set with the only constraint that it must be > > implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. > > > > But we actually need to add another level of constraint: what the hw is > > actually capable of, because currently, a linux booting on a sifive-u54 > > boots in sv57 mode which is incompatible with the cpu's sv39 max > > capability. > > > > So add a new bitmap to RISCVSATPMap which contains this capability and > > initialize it in every XXX_cpu_init. > > > > Finally, we have the following chain of constraints: > > > > Qemu capability > HW capability > User choice > Software capability > > ^ What software is this? > I'd think the user's choice would always be last. Hmm maybe that's not clear, but I meant that the last constraint was what the emulated software is capable of handling. > > > > > Signed-off-by: Alexandre Ghiti > > --- > > target/riscv/cpu.c | 78 +++++++++++++++++++++++++++++++--------------- > > target/riscv/cpu.h | 8 +++-- > > 2 files changed, 59 insertions(+), 27 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index e409e6ab64..19a37fee2b 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -292,24 +292,39 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > > g_assert_not_reached(); > > } > > > > -/* Sets the satp mode to the max supported */ > > -static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit) > > +static void set_satp_mode_max_supported(RISCVCPU *cpu, > > + const char *satp_mode_str, > > + bool is_32_bit) > > { > > - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > > - cpu->cfg.satp_mode.map |= > > - (1 << satp_mode_from_str(is_32_bit ? "sv32" : "sv57")); > > - } else { > > - cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > > + uint8_t satp_mode = satp_mode_from_str(satp_mode_str); > > + const bool *valid_vm = is_32_bit ? valid_vm_1_10_32 : valid_vm_1_10_64; > > + > > + for (int i = 0; i <= satp_mode; ++i) { > > + if (valid_vm[i]) { > > + cpu->cfg.satp_mode.supported |= (1 << i); > > I don't think we need a new 'supported' bitmap, I think each board that > needs to further constrain va-bits from what QEMU supports should just set > valid_vm_1_10_32/64. I.e. drop const from the arrays and add an init > function something like > > #define QEMU_SATP_MODE_MAX VM_1_10_SV64 > > void riscv_cpu_set_satp_mode_max(RISCVCPU *cpu, uint8_t satp_mode_max) > { > bool is_32_bit = cpu->env.misa_mxl == MXL_RV32; > bool *valid_vm = is_32_bit ? valid_vm_1_10_32 : valid_vm_1_10_64; > > g_assert(satp_mode_max <= QEMU_SATP_MODE_MAX); > g_assert(!is_32_bit || satp_mode_max < 2); > > memset(valid_vm, 0, sizeof(*valid_vm)); > > for (int i = 0; i <= satp_mode_max; i++) { > valid_vm[i] = true; > } > } > > The valid_vm[] checks already in finalize should then manage the > validation needed to constrain boards. Only boards that care about > this need to call this function, otherwise they'll get the default. > > Also, this patch should come before the patch that changes the default > for all boards to sv57 in order to avoid breaking bisection. > > Thanks, > drew From MAILER-DAEMON Tue Jan 24 08:13:52 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKJ7X-000106-SH for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 08:13:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKJ7W-0000zo-Bh for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 08:13:50 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKJ7U-0003QE-7S for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 08:13:50 -0500 Received: by mail-wr1-x433.google.com with SMTP id b7so13848192wrt.3 for ; Tue, 24 Jan 2023 05:13:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=63gUpz/DHEnLeNiJ2GufmxcXpmtP/k4mWXKdkbg54Jo=; b=5tZ2gRVjKdIpaE1srPCHAfpE/km4KUEU28InTrpWz89n3rCI9kGt78lK8z9Znehbn8 zmSITicK8BJlTCTZiQn/oK8dnD5R6KFFtR1XmJ7t5EyWzjR6FtCa/DgMaWv+xYXv/luA 9OpBS7Ct1hmDARlWnxUwuHgKrzsElJwLEVbIueT+CCnpIGxi+QprIKA5is2W8ChoaFC+ zHmL9vgkvWhP4Fp0gqdxzRBSG54wZ+tP7Ca7SisAtGzW2TYUDI8wOKdQFmSzcMMu/VSb zPVtU0Jo7QeyerOngJvt46dk8c+tcxcgnA8ilYYdQrsYfIP2MVojBeqh+KLlK8+nXBCv godQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=63gUpz/DHEnLeNiJ2GufmxcXpmtP/k4mWXKdkbg54Jo=; b=fGihovRxJMbi+A8MwZ8pWL/RO6sEkph4uxhXS7HDsujsAuLhvuB5BAv/IV6PrCCWhm naJRC+Kj1uMWeVo/OcUXz8Mq4vdED/dBja4TJNxO9j6/SrcHGBoMAlWdg3ijrQwmyqQ5 KdoeUeVbvLDxI9W3zDjmD6SXvGk1Bh1mfM36fVw2nAs1jljxFD7FbcFIN/A3WLnokOfF tiGeySyevKG8oh3nVk3cwDR4AVWbgAA0/z4zjEv4iQr8FV3LV+YwrbSTrbJbCQuacOEE E/rXF7A121k+l4MFm3oitrdlsoq0jRaGGBe6dWfdreo/6WQm5pfOMuzLDWcS++rAaxlI 2UdA== X-Gm-Message-State: AFqh2krSyxbWyv7VggzXhXS3CRWJCjKbe0qfVPsU1dWmI620kf0hxYPV EOcyTj94vfVooQGs+hFEyF33Wu5LkU+Q2NjL9AbTEA== X-Google-Smtp-Source: AMrXdXtW3SScwMi6JvNxjKjZuOJHimsaVevjttlxkPykqFVV0pSrkbZpTDoONZgHfOLgGrEGi3QQp5BBYJomcIFe0Rg= X-Received: by 2002:a5d:5190:0:b0:2bd:d6bc:e35c with SMTP id k16-20020a5d5190000000b002bdd6bce35cmr1265377wrv.144.1674566025934; Tue, 24 Jan 2023 05:13:45 -0800 (PST) MIME-Version: 1.0 References: <20230123090324.732681-1-alexghiti@rivosinc.com> <20230123090324.732681-6-alexghiti@rivosinc.com> <20230123105112.zidabgiswkpnzo5r@orel> <20230123133127.7dyqhdryrbp27o46@orel> In-Reply-To: <20230123133127.7dyqhdryrbp27o46@orel> From: Alexandre Ghiti Date: Tue, 24 Jan 2023 14:13:35 +0100 Message-ID: Subject: Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities To: Andrew Jones Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 13:13:50 -0000 On Mon, Jan 23, 2023 at 2:31 PM Andrew Jones wrote: > > On Mon, Jan 23, 2023 at 12:15:08PM +0100, Alexandre Ghiti wrote: > > On Mon, Jan 23, 2023 at 11:51 AM Andrew Jones wrote: > > > > > > On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote: > > > > Currently, the max satp mode is set with the only constraint that it must be > > > > implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. > > > > > > > > But we actually need to add another level of constraint: what the hw is > > > > actually capable of, because currently, a linux booting on a sifive-u54 > > > > boots in sv57 mode which is incompatible with the cpu's sv39 max > > > > capability. > > > > > > > > So add a new bitmap to RISCVSATPMap which contains this capability and > > > > initialize it in every XXX_cpu_init. > > > > > > > > Finally, we have the following chain of constraints: > > > > > > > > Qemu capability > HW capability > User choice > Software capability > > > > > > ^ What software is this? > > > I'd think the user's choice would always be last. > > > > > > > > > > > Signed-off-by: Alexandre Ghiti > > > > --- > > > > target/riscv/cpu.c | 78 +++++++++++++++++++++++++++++++--------------- > > > > target/riscv/cpu.h | 8 +++-- > > > > 2 files changed, 59 insertions(+), 27 deletions(-) > > > > > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > > > index e409e6ab64..19a37fee2b 100644 > > > > --- a/target/riscv/cpu.c > > > > +++ b/target/riscv/cpu.c > > > > @@ -292,24 +292,39 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > > > > g_assert_not_reached(); > > > > } > > > > > > > > -/* Sets the satp mode to the max supported */ > > > > -static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit) > > > > +static void set_satp_mode_max_supported(RISCVCPU *cpu, > > > > + const char *satp_mode_str, > > > > + bool is_32_bit) > > > > { > > > > - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > > > > - cpu->cfg.satp_mode.map |= > > > > - (1 << satp_mode_from_str(is_32_bit ? "sv32" : "sv57")); > > > > - } else { > > > > - cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > > > > + uint8_t satp_mode = satp_mode_from_str(satp_mode_str); > > > > + const bool *valid_vm = is_32_bit ? valid_vm_1_10_32 : valid_vm_1_10_64; > > > > + > > > > + for (int i = 0; i <= satp_mode; ++i) { > > > > + if (valid_vm[i]) { > > > > + cpu->cfg.satp_mode.supported |= (1 << i); > > > > > > I don't think we need a new 'supported' bitmap, I think each board that > > > needs to further constrain va-bits from what QEMU supports should just set > > > valid_vm_1_10_32/64. I.e. drop const from the arrays and add an init > > > function something like > > > > This was my first idea too, but those arrays are global and I have to > > admit that I thought it was possible to emulate a cpu with different > > cores. Anyway, isn't it a bit weird to store this into some global > > array whereas it is intimately linked to the CPU? To me, it makes > > sense to keep those variables as a way to know what qemu is able to > > emulate and have a CPU specific map like in this patch for the hw > > capabilities. Does it make sense to you? > > Ah, yes, to support heterogeneous configs it's best to keep this > information per-cpu. I'll take another look at the patch. > > > > > > > > > #define QEMU_SATP_MODE_MAX VM_1_10_SV64 > > > > > > void riscv_cpu_set_satp_mode_max(RISCVCPU *cpu, uint8_t satp_mode_max) > > > { > > > bool is_32_bit = cpu->env.misa_mxl == MXL_RV32; > > > bool *valid_vm = is_32_bit ? valid_vm_1_10_32 : valid_vm_1_10_64; > > > > > > g_assert(satp_mode_max <= QEMU_SATP_MODE_MAX); > > > g_assert(!is_32_bit || satp_mode_max < 2); > > > > > > memset(valid_vm, 0, sizeof(*valid_vm)); > > > > > > for (int i = 0; i <= satp_mode_max; i++) { > > > valid_vm[i] = true; > > > } > > > } > > > > > > The valid_vm[] checks already in finalize should then manage the > > > validation needed to constrain boards. Only boards that care about > > > this need to call this function, otherwise they'll get the default. > > > > > > Also, this patch should come before the patch that changes the default > > > for all boards to sv57 in order to avoid breaking bisection. > > > > As I explained earlier, I didn't change the default to sv57! Just > > fixed what was passed via the device tree, which should not be used > > anyway :) > > OK, I keep misunderstanding how we're "fixing" something which is > is wrong, but apparently doesn't exhibit any symptoms. So, assuming > it doesn't matter, then I guess it can come anywhere in the series. Actually *I* think it should not matter, but I can't be sure so I'll do what you ask. > > Thanks, > drew From MAILER-DAEMON Tue Jan 24 08:24:34 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKJHu-0004Su-QN for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 08:24:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKJHs-0004RZ-Im for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 08:24:32 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKJHq-0006IL-0w for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 08:24:32 -0500 Received: by mail-wm1-x333.google.com with SMTP id c4-20020a1c3504000000b003d9e2f72093so12822006wma.1 for ; Tue, 24 Jan 2023 05:24:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; 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Tue, 24 Jan 2023 05:24:28 -0800 (PST) MIME-Version: 1.0 References: <20230123090324.732681-1-alexghiti@rivosinc.com> <20230123090324.732681-6-alexghiti@rivosinc.com> <20230123135126.koxdvloakhwk2gcy@orel> In-Reply-To: <20230123135126.koxdvloakhwk2gcy@orel> From: Alexandre Ghiti Date: Tue, 24 Jan 2023 14:24:17 +0100 Message-ID: Subject: Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities To: Andrew Jones Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x333.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 13:24:32 -0000 On Mon, Jan 23, 2023 at 2:51 PM Andrew Jones wrote: > > On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote: > > Currently, the max satp mode is set with the only constraint that it must be > > implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. > > > > But we actually need to add another level of constraint: what the hw is > > actually capable of, because currently, a linux booting on a sifive-u54 > > boots in sv57 mode which is incompatible with the cpu's sv39 max > > capability. > > > > So add a new bitmap to RISCVSATPMap which contains this capability and > > initialize it in every XXX_cpu_init. > > > > Finally, we have the following chain of constraints: > > > > Qemu capability > HW capability > User choice > Software capability > > > > Signed-off-by: Alexandre Ghiti > > --- > > target/riscv/cpu.c | 78 +++++++++++++++++++++++++++++++--------------- > > target/riscv/cpu.h | 8 +++-- > > 2 files changed, 59 insertions(+), 27 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index e409e6ab64..19a37fee2b 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -292,24 +292,39 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > > g_assert_not_reached(); > > } > > > > -/* Sets the satp mode to the max supported */ > > -static void set_satp_mode_default(RISCVCPU *cpu, bool is_32_bit) > > +static void set_satp_mode_max_supported(RISCVCPU *cpu, > > + const char *satp_mode_str, > > + bool is_32_bit) > > I'd drop 'is_32_bit' and get it from 'cpu', which would "clean up" all the > callsites by getting rid of all the true/false stuff. Indeed, better this way > Also, why take the string instead of the VM_1_10_SV* define? No particular reason, but I changed it to VM_1_10_SV*, thanks > > > { > > - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > > - cpu->cfg.satp_mode.map |= > > - (1 << satp_mode_from_str(is_32_bit ? "sv32" : "sv57")); > > - } else { > > - cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > > + uint8_t satp_mode = satp_mode_from_str(satp_mode_str); > > + const bool *valid_vm = is_32_bit ? valid_vm_1_10_32 : valid_vm_1_10_64; > > + > > + for (int i = 0; i <= satp_mode; ++i) { > > + if (valid_vm[i]) { > > + cpu->cfg.satp_mode.supported |= (1 << i); > > + } > > } > > } > > > > +/* Sets the satp mode to the max supported */ > > +static void set_satp_mode_default(RISCVCPU *cpu) > > +{ > > + uint8_t satp_mode = satp_mode_max_from_map(cpu->cfg.satp_mode.supported); > > + > > + cpu->cfg.satp_mode.map |= (1 << satp_mode); > > Let's do 'cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported' to make > sure 'map' has all supported bits set for property probing. Indeed now the map is fully set. > > > +} > > + > > static void riscv_any_cpu_init(Object *obj) > > { > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > + RISCVCPU *cpu = RISCV_CPU(obj); > > + > > #if defined(TARGET_RISCV32) > > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > > + set_satp_mode_max_supported(cpu, "sv32", true); > > #elif defined(TARGET_RISCV64) > > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > > + set_satp_mode_max_supported(cpu, "sv57", false); > > #endif > > set_priv_version(env, PRIV_VERSION_1_12_0); > > register_cpu_props(obj); > > @@ -319,18 +334,24 @@ static void riscv_any_cpu_init(Object *obj) > > static void rv64_base_cpu_init(Object *obj) > > { > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > + RISCVCPU *cpu = RISCV_CPU(obj); > > + > > /* We set this in the realise function */ > > set_misa(env, MXL_RV64, 0); > > register_cpu_props(obj); > > /* Set latest version of privileged specification */ > > set_priv_version(env, PRIV_VERSION_1_12_0); > > + set_satp_mode_max_supported(cpu, "sv57", false); > > } > > > > static void rv64_sifive_u_cpu_init(Object *obj) > > { > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > + RISCVCPU *cpu = RISCV_CPU(obj); > > + > > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > > set_priv_version(env, PRIV_VERSION_1_10_0); > > + set_satp_mode_max_supported(cpu, "sv39", false); > > } > > > > static void rv64_sifive_e_cpu_init(Object *obj) > > @@ -341,6 +362,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) > > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); > > set_priv_version(env, PRIV_VERSION_1_10_0); > > cpu->cfg.mmu = false; > > + set_satp_mode_max_supported(cpu, "mbare", false); > > } > > > > static void rv128_base_cpu_init(Object *obj) > > @@ -352,11 +374,13 @@ static void rv128_base_cpu_init(Object *obj) > > exit(EXIT_FAILURE); > > } > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > + RISCVCPU *cpu = RISCV_CPU(obj); > > /* We set this in the realise function */ > > set_misa(env, MXL_RV128, 0); > > register_cpu_props(obj); > > /* Set latest version of privileged specification */ > > set_priv_version(env, PRIV_VERSION_1_12_0); > > + set_satp_mode_max_supported(cpu, "sv57", false); > > } > > #else > > static void rv32_base_cpu_init(Object *obj) > > @@ -367,13 +391,17 @@ static void rv32_base_cpu_init(Object *obj) > > register_cpu_props(obj); > > /* Set latest version of privileged specification */ > > set_priv_version(env, PRIV_VERSION_1_12_0); > > + set_satp_mode_max_supported(cpu, "sv32", true); > > } > > > > static void rv32_sifive_u_cpu_init(Object *obj) > > { > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > + RISCVCPU *cpu = RISCV_CPU(obj); > > + > > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > > set_priv_version(env, PRIV_VERSION_1_10_0); > > + set_satp_mode_max_supported(cpu, "sv32", true); > > } > > > > static void rv32_sifive_e_cpu_init(Object *obj) > > @@ -384,6 +412,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) > > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); > > set_priv_version(env, PRIV_VERSION_1_10_0); > > cpu->cfg.mmu = false; > > + set_satp_mode_max_supported(cpu, "mbare", true); > > } > > > > static void rv32_ibex_cpu_init(Object *obj) > > @@ -394,6 +423,7 @@ static void rv32_ibex_cpu_init(Object *obj) > > set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); > > set_priv_version(env, PRIV_VERSION_1_11_0); > > cpu->cfg.mmu = false; > > + set_satp_mode_max_supported(cpu, "mbare", true); > > cpu->cfg.epmp = true; > > } > > > > @@ -405,6 +435,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); > > set_priv_version(env, PRIV_VERSION_1_10_0); > > cpu->cfg.mmu = false; > > + set_satp_mode_max_supported(cpu, "mbare", true); > > } > > #endif > > > > @@ -696,7 +727,9 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > > static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > > { > > bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > > - const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > > + uint8_t satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > > + uint8_t satp_mode_supported_max = > > + satp_mode_max_from_map(cpu->cfg.satp_mode.supported); > > > > if (cpu->cfg.satp_mode.map == 0) { > > /* > > @@ -704,7 +737,7 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > > * satp mode. > > */ > > if (cpu->cfg.satp_mode.init == 0) { > > - set_satp_mode_default(cpu, rv32); > > + set_satp_mode_default(cpu); > > } else { > > /* > > * Find the lowest level that was disabled and then enable the > > @@ -714,9 +747,9 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > > for (int i = 1; i < 16; ++i) { > > if (!(cpu->cfg.satp_mode.map & (1 << i)) && > > (cpu->cfg.satp_mode.init & (1 << i)) && > > - valid_vm[i]) { > > + (cpu->cfg.satp_mode.supported & (1 << i))) { > > for (int j = i - 1; j >= 0; --j) { > > - if (valid_vm[j]) { > > + if (cpu->cfg.satp_mode.supported & (1 << j)) { > > cpu->cfg.satp_mode.map |= (1 << j); > > break; > > } > > @@ -727,13 +760,12 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > > } > > } > > > > - /* Make sure the configuration asked is supported by qemu */ > > - for (int i = 0; i < 16; ++i) { > > - if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > > - error_setg(errp, "satp_mode %s is not valid", > > - satp_mode_str(i, rv32)); > > - return; > > - } > > + /* Make sure the user asked for a supported configuration (HW and qemu) */ > > + if (satp_mode_map_max > satp_mode_supported_max) { > > + error_setg(errp, "satp_mode %s is higher than hw max capability %s", > > + satp_mode_str(satp_mode_map_max, rv32), > > + satp_mode_str(satp_mode_supported_max, rv32)); > > + return; > > } > > > > /* > > @@ -741,17 +773,13 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > > * the specification. > > */ > > if (!rv32) { > > - uint8_t satp_mode_max; > > - > > - satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > > - > > - for (int i = satp_mode_max - 1; i >= 0; --i) { > > + for (int i = satp_mode_map_max - 1; i >= 0; --i) { > > if (!(cpu->cfg.satp_mode.map & (1 << i)) && > > (cpu->cfg.satp_mode.init & (1 << i)) && > > - valid_vm[i]) { > > + (cpu->cfg.satp_mode.supported & (1 << i))) { > > error_setg(errp, "cannot disable %s satp mode if %s " > > "is enabled", satp_mode_str(i, false), > > - satp_mode_str(satp_mode_max, false)); > > + satp_mode_str(satp_mode_map_max, false)); > > return; > > } > > } > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index e37177db5c..b591122099 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -416,13 +416,17 @@ struct RISCVCPUClass { > > > > /* > > * map is a 16-bit bitmap: the most significant set bit in map is the maximum > > - * satp mode that is supported. > > + * satp mode that is supported. It may be chosen by the user and must respect > > + * what qemu implements (valid_1_10_32/64) and what the hw is capable of > > + * (supported bitmap below). > > * > > * init is a 16-bit bitmap used to make sure the user selected a correct > > * configuration as per the specification. > > + * > > + * supported is a 16-bit bitmap used to reflect the hw capabilities. > > */ > > typedef struct { > > - uint16_t map, init; > > + uint16_t map, init, supported; > > } RISCVSATPMap; > > > > struct RISCVCPUConfig { > > -- > > 2.37.2 > > > > Thanks, > drew From MAILER-DAEMON Tue Jan 24 10:32:02 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKLHF-0007Sh-NQ for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 10:32:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKLHE-0007SI-8G for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 10:32:00 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKLHC-0005qT-3q for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 10:31:59 -0500 Received: by mail-ej1-x62f.google.com with SMTP id mg12so40010563ejc.5 for ; Tue, 24 Jan 2023 07:31:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=5ontTpgHnhGGx/x0+gbQVZARerX19A7cazWXxmOfuwE=; b=hB/+otqWBol4G4X00uCQK/kRO8q9ANhBV9p1tL4L2r/BS4fi2uAXRE35+kp3ihZxvs jhoSaV6Q8p2JUVXRfI6Nwa8/6zpLl/K8Q4apigZkiYFdEi3rgLHl9HO5E8xk4QOpJkw8 +VR4U/fe3kyiP8nB0eA+lwZDCJcyNyUQdURATl5tS6Squd+LUJ2bBE9XJ5Y7hh9FoiSZ dbQ/fxB8lKi6sIRtANhM9bj55J6kH7PIDMlXXBCQqSXnCjh8HZe2nZMEnW6aerkU5w16 GxBntCnW877fcMHsrxIE00OyASj+2pnoVOUWVGPB+k5yOToZGjNp6g5QFeBXUVHa1sVg 8n9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=5ontTpgHnhGGx/x0+gbQVZARerX19A7cazWXxmOfuwE=; b=gBwFiXbPc3d435OBaDxQzlNi9FaekeQb8RSh6RuWXkfK83xRZV56vXxOdUS6KvjFh9 SBmkISLwfYRl/jo/BsYsYoRszLwZj6Daut1vxpdld4DnO+R7dGzchWm9oqlnIDAExeD+ d5PwXN3G5VNSGYG659QurQQpgcXxf826qX+ZEsCs5C2pYf0x/nyuE61fIbjj4vE46HGB o2iFmLy4drth/LOXStDPYHod65EJv/L7V2M5z/DL92splQT+IrWpnOCwLUNJtZsApoNq KuDizefLW34S9XAaXZr7mRaxUKaBL3yE8gt0PAGa39b5BKUULcIQyWLuRpriHDIDXLRm 6PWQ== X-Gm-Message-State: AFqh2krdQyPAlRcQJiL1/Lq43VyamPnNQFO6Yjgpu1Rru7EFOVAVjCRD bQ2sjRCG1dUZZBTi5cR2zfF90Q== X-Google-Smtp-Source: AMrXdXt+qcSc5sKYx2vlV0k1/3Holy755ocQIc+2zxEFsLo5Y1uxBDCCTL54OJiOxEcjQe8W3KFFFQ== X-Received: by 2002:a17:906:a84f:b0:84d:465f:d2f9 with SMTP id dx15-20020a170906a84f00b0084d465fd2f9mr30748060ejb.67.1674574316224; Tue, 24 Jan 2023 07:31:56 -0800 (PST) Received: from localhost (cst2-173-16.cust.vodafone.cz. [31.30.173.16]) by smtp.gmail.com with ESMTPSA id u4-20020a17090617c400b0081bfc79beaesm1026873eje.75.2023.01.24.07.31.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 07:31:55 -0800 (PST) Date: Tue, 24 Jan 2023 16:31:54 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: Re: [PATCH v6 5/5] riscv: Introduce satp mode hw capabilities Message-ID: <20230124153154.rtffytklzyeidd6b@orel> References: <20230123090324.732681-1-alexghiti@rivosinc.com> <20230123090324.732681-6-alexghiti@rivosinc.com> <20230123105112.zidabgiswkpnzo5r@orel> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=ajones@ventanamicro.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 15:32:00 -0000 On Tue, Jan 24, 2023 at 11:07:53AM +0100, Alexandre Ghiti wrote: > On Mon, Jan 23, 2023 at 11:51 AM Andrew Jones wrote: > > > > On Mon, Jan 23, 2023 at 10:03:24AM +0100, Alexandre Ghiti wrote: > > > Currently, the max satp mode is set with the only constraint that it must be > > > implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. > > > > > > But we actually need to add another level of constraint: what the hw is > > > actually capable of, because currently, a linux booting on a sifive-u54 > > > boots in sv57 mode which is incompatible with the cpu's sv39 max > > > capability. > > > > > > So add a new bitmap to RISCVSATPMap which contains this capability and > > > initialize it in every XXX_cpu_init. > > > > > > Finally, we have the following chain of constraints: > > > > > > Qemu capability > HW capability > User choice > Software capability > > > > ^ What software is this? > > I'd think the user's choice would always be last. > > Hmm maybe that's not clear, but I meant that the last constraint was > what the emulated software is capable of handling. Assuming "emulated software" is the guest OS, then OK. How about rewording as target/riscv's general satp mode support constrains what the boards support and the boards constrain what the user may select. The user's selection will then constrain what's available to the guest OS. Thanks, drew From MAILER-DAEMON Tue Jan 24 12:31:33 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKN8s-0008D1-G8 for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 12:31:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKN8o-0008Bd-QE for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 12:31:27 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKN8l-0000XL-5W for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 12:31:26 -0500 Received: by mail-wr1-x430.google.com with SMTP id r2so14609572wrv.7 for ; Tue, 24 Jan 2023 09:31:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=PEPPswYpVZqmIbYwQ20mzxoBoeCcQE7N6u1dOy8x9B4=; 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Tue, 24 Jan 2023 09:31:20 -0800 (PST) MIME-Version: 1.0 References: <20221223180016.2068508-1-christoph.muellner@vrull.eu> <20221223180016.2068508-2-christoph.muellner@vrull.eu> In-Reply-To: From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Tue, 24 Jan 2023 18:31:07 +0100 Message-ID: Subject: Re: [PATCH v2 01/15] RISC-V: Adding XTheadCmo ISA extension To: Alistair Francis Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: multipart/alternative; boundary="00000000000045669a05f305e209" Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 17:31:28 -0000 --00000000000045669a05f305e209 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, Jan 23, 2023 at 11:50 PM Alistair Francis wrote: > On Sat, Dec 24, 2022 at 4:09 AM Christoph Muellner > wrote: > > > > From: Christoph M=C3=BCllner > > > > This patch adds support for the XTheadCmo ISA extension. > > To avoid interfering with standard extensions, decoder and translation > > are in its own xthead* specific files. > > Future patches should be able to easily add additional T-Head extension= . > > > > The implementation does not have much functionality (besides accepting > > the instructions and not qualifying them as illegal instructions if > > the hart executes in the required privilege level for the instruction), > > as QEMU does not model CPU caches and instructions are documented > > to not raise any exceptions. > > > > Changes in v2: > > - Add ISA_EXT_DATA_ENTRY() > > - Explicit test for PRV_U > > - Encapsule access to env-priv in inline function > > - Use single decoder for XThead extensions > > > > Co-developed-by: LIU Zhiwei > > Signed-off-by: Christoph M=C3=BCllner > > --- > > target/riscv/cpu.c | 2 + > > target/riscv/cpu.h | 1 + > > target/riscv/insn_trans/trans_xthead.c.inc | 89 ++++++++++++++++++++++ > > target/riscv/meson.build | 1 + > > target/riscv/translate.c | 15 +++- > > target/riscv/xthead.decode | 38 +++++++++ > > 6 files changed, 143 insertions(+), 3 deletions(-) > > create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc > > create mode 100644 target/riscv/xthead.decode > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 6fe176e483..a90b82c5c5 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -108,6 +108,7 @@ static const struct isa_ext_data isa_edata_arr[] = =3D { > > ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval= ), > > ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot= ), > > ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), > > + ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, > ext_xtheadcmo), > > ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, > ext_XVentanaCondOps), > > }; > > > > @@ -1060,6 +1061,7 @@ static Property riscv_cpu_extensions[] =3D { > > DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), > > > > /* Vendor-specific custom extensions */ > > + DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), > > DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, > cfg.ext_XVentanaCondOps, false), > > > > /* These are experimental so mark with 'x-' */ > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index 443d15a47c..ad1c19f870 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -465,6 +465,7 @@ struct RISCVCPUConfig { > > uint64_t mimpid; > > > > /* Vendor-specific custom extensions */ > > + bool ext_xtheadcmo; > > bool ext_XVentanaCondOps; > > > > uint8_t pmu_num; > > diff --git a/target/riscv/insn_trans/trans_xthead.c.inc > b/target/riscv/insn_trans/trans_xthead.c.inc > > new file mode 100644 > > index 0000000000..00e75c7dca > > --- /dev/null > > +++ b/target/riscv/insn_trans/trans_xthead.c.inc > > @@ -0,0 +1,89 @@ > > +/* > > + * RISC-V translation routines for the T-Head vendor extensions > (xthead*). > > + * > > + * Copyright (c) 2022 VRULL GmbH. > > + * > > + * This program is free software; you can redistribute it and/or modif= y > it > > + * under the terms and conditions of the GNU General Public License, > > + * version 2 or later, as published by the Free Software Foundation. > > + * > > + * This program is distributed in the hope it will be useful, but > WITHOUT > > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY = or > > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public > License for > > + * more details. > > + * > > + * You should have received a copy of the GNU General Public License > along with > > + * this program. If not, see . > > + */ > > + > > +#define REQUIRE_XTHEADCMO(ctx) do { \ > > + if (!ctx->cfg_ptr->ext_xtheadcmo) { \ > > + return false; \ > > + } \ > > +} while (0) > > + > > +/* XTheadCmo */ > > + > > +static inline int priv_level(DisasContext *ctx) > > +{ > > +#ifdef CONFIG_USER_ONLY > > + return PRV_U; > > +#else > > + /* Priv level equals mem_idx -- see cpu_mmu_index. */ > > + return ctx->mem_idx; > > This should be ANDed with TB_FLAGS_PRIV_MMU_MASK as sometimes this can > include hypervisor priv access information > Ok. > > > +#endif > > +} > > + > > +#define REQUIRE_PRIV_MHSU(ctx) \ > > +do { \ > > + int priv =3D priv_level(ctx); \ > > + if (!(priv =3D=3D PRV_M || \ > > + priv =3D=3D PRV_H || \ > > PRV_H isn't used > > > + priv =3D=3D PRV_S || \ > > + priv =3D=3D PRV_U)) { \ > > + return false; \ > > When would this not be the case? > Ok, I will make this a macro that expands to nothing (and a comment). > > > + } \ > > +} while (0) > > + > > +#define REQUIRE_PRIV_MHS(ctx) \ > > +do { \ > > + int priv =3D priv_level(ctx); \ > > + if (!(priv =3D=3D PRV_M || \ > > + priv =3D=3D PRV_H || \ > > Also not used > Ok, I will remove the PRV_H. > > > + priv =3D=3D PRV_S)) { \ > > + return false; \ > > + } \ > > +} while (0) > > + > > +#define NOP_PRIVCHECK(insn, extcheck, privcheck) \ > > +static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn * a) \ > > +{ \ > > + (void) a; \ > > + extcheck(ctx); \ > > + privcheck(ctx); \ > > + return true; \ > > +} > > + > > +NOP_PRIVCHECK(th_dcache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > > +NOP_PRIVCHECK(th_dcache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > > +NOP_PRIVCHECK(th_dcache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > > +NOP_PRIVCHECK(th_dcache_cpa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > > +NOP_PRIVCHECK(th_dcache_cipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > > +NOP_PRIVCHECK(th_dcache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > > +NOP_PRIVCHECK(th_dcache_cva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) > > +NOP_PRIVCHECK(th_dcache_civa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) > > +NOP_PRIVCHECK(th_dcache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) > > +NOP_PRIVCHECK(th_dcache_csw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > > +NOP_PRIVCHECK(th_dcache_cisw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > > +NOP_PRIVCHECK(th_dcache_isw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > > +NOP_PRIVCHECK(th_dcache_cpal1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > > +NOP_PRIVCHECK(th_dcache_cval1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > > + > > +NOP_PRIVCHECK(th_icache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > > +NOP_PRIVCHECK(th_icache_ialls, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > > +NOP_PRIVCHECK(th_icache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > > +NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) > > + > > +NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > > +NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > > +NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > > diff --git a/target/riscv/meson.build b/target/riscv/meson.build > > index ba25164d74..5dee37a242 100644 > > --- a/target/riscv/meson.build > > +++ b/target/riscv/meson.build > > @@ -2,6 +2,7 @@ > > gen =3D [ > > decodetree.process('insn16.decode', extra_args: > ['--static-decode=3Ddecode_insn16', '--insnwidth=3D16']), > > decodetree.process('insn32.decode', extra_args: > '--static-decode=3Ddecode_insn32'), > > + decodetree.process('xthead.decode', extra_args: > '--static-decode=3Ddecode_xthead'), > > decodetree.process('XVentanaCondOps.decode', extra_args: > '--static-decode=3Ddecode_XVentanaCodeOps'), > > ] > > > > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > > index db123da5ec..14d9116975 100644 > > --- a/target/riscv/translate.c > > +++ b/target/riscv/translate.c > > @@ -125,13 +125,18 @@ static bool always_true_p(DisasContext *ctx > __attribute__((__unused__))) > > return true; > > } > > > > +static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__)= )) > > +{ > > + return ctx->cfg_ptr->ext_xtheadcmo; > > +} > > + > > #define MATERIALISE_EXT_PREDICATE(ext) \ > > static bool has_ ## ext ## _p(DisasContext *ctx) \ > > { \ > > return ctx->cfg_ptr->ext_ ## ext ; \ > > } > > > > -MATERIALISE_EXT_PREDICATE(XVentanaCondOps); > > +MATERIALISE_EXT_PREDICATE(XVentanaCondOps) > > Do we need this change? > It is indeed a drive-by cleanup, that is not necessary. In v1 we were using this macro, therefore it made sense back then. Will be dropped. > > > > > #ifdef TARGET_RISCV32 > > #define get_xl(ctx) MXL_RV32 > > @@ -732,6 +737,10 @@ static int ex_rvc_shiftri(DisasContext *ctx, int > imm) > > /* Include the auto-generated decoder for 32 bit insn */ > > #include "decode-insn32.c.inc" > > > > +/* Include decoders for factored-out extensions */ > > +#include "decode-xthead.c.inc" > > +#include "decode-XVentanaCondOps.c.inc" > > + > > static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, > > void (*func)(TCGv, TCGv, target_long)) > > { > > @@ -1033,12 +1042,11 @@ static uint32_t opcode_at(DisasContextBase > *dcbase, target_ulong pc) > > #include "insn_trans/trans_rvk.c.inc" > > #include "insn_trans/trans_privileged.c.inc" > > #include "insn_trans/trans_svinval.c.inc" > > +#include "insn_trans/trans_xthead.c.inc" > > #include "insn_trans/trans_xventanacondops.c.inc" > > > > /* Include the auto-generated decoder for 16 bit insn */ > > #include "decode-insn16.c.inc" > > -/* Include decoders for factored-out extensions */ > > -#include "decode-XVentanaCondOps.c.inc" > > Can we not leave these at the bottom? > Ok. > Alistair > > > > > /* The specification allows for longer insns, but not supported by > qemu. */ > > #define MAX_INSN_LEN 4 > > @@ -1059,6 +1067,7 @@ static void decode_opc(CPURISCVState *env, > DisasContext *ctx, uint16_t opcode) > > bool (*decode_func)(DisasContext *, uint32_t); > > } decoders[] =3D { > > { always_true_p, decode_insn32 }, > > + { has_xthead_p, decode_xthead }, > > { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, > > }; > > > > diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode > > new file mode 100644 > > index 0000000000..30533a66f5 > > --- /dev/null > > +++ b/target/riscv/xthead.decode > > @@ -0,0 +1,38 @@ > > +# > > +# Translation routines for the instructions of the XThead* ISA > extensions > > +# > > +# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu > > +# > > +# SPDX-License-Identifier: LGPL-2.1-or-later > > +# > > +# The documentation of the ISA extensions can be found here: > > +# https://github.com/T-head-Semi/thead-extension-spec/releases/lates= t > > + > > +# Fields: > > +%rs1 15:5 > > + > > +# Formats > > +@sfence_vm ....... ..... ..... ... ..... ....... %rs1 > > + > > +# XTheadCmo > > +th_dcache_call 0000000 00001 00000 000 00000 0001011 > > +th_dcache_ciall 0000000 00011 00000 000 00000 0001011 > > +th_dcache_iall 0000000 00010 00000 000 00000 0001011 > > +th_dcache_cpa 0000001 01001 ..... 000 00000 0001011 @sfence_vm > > +th_dcache_cipa 0000001 01011 ..... 000 00000 0001011 @sfence_vm > > +th_dcache_ipa 0000001 01010 ..... 000 00000 0001011 @sfence_vm > > +th_dcache_cva 0000001 00101 ..... 000 00000 0001011 @sfence_vm > > +th_dcache_civa 0000001 00111 ..... 000 00000 0001011 @sfence_vm > > +th_dcache_iva 0000001 00110 ..... 000 00000 0001011 @sfence_vm > > +th_dcache_csw 0000001 00001 ..... 000 00000 0001011 @sfence_vm > > +th_dcache_cisw 0000001 00011 ..... 000 00000 0001011 @sfence_vm > > +th_dcache_isw 0000001 00010 ..... 000 00000 0001011 @sfence_vm > > +th_dcache_cpal1 0000001 01000 ..... 000 00000 0001011 @sfence_vm > > +th_dcache_cval1 0000001 00100 ..... 000 00000 0001011 @sfence_vm > > +th_icache_iall 0000000 10000 00000 000 00000 0001011 > > +th_icache_ialls 0000000 10001 00000 000 00000 0001011 > > +th_icache_ipa 0000001 11000 ..... 000 00000 0001011 @sfence_vm > > +th_icache_iva 0000001 10000 ..... 000 00000 0001011 @sfence_vm > > +th_l2cache_call 0000000 10101 00000 000 00000 0001011 > > +th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 > > +th_l2cache_iall 0000000 10110 00000 000 00000 0001011 > > -- > > 2.38.1 > > > > > --00000000000045669a05f305e209 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Mon, Jan 23, 2023 at 11:50 PM Alis= tair Francis <alistair23@gmail.c= om> wrote:
christ= oph.muellner@vrull.eu> wrote:
>
> From: Christoph M=C3=BCllner <christoph.muellner@vrull.eu>
>
> This patch adds support for the XTheadCmo ISA extension.
> To avoid interfering with standard extensions, decoder and translation=
> are in its own xthead* specific files.
> Future patches should be able to easily add additional T-Head extensio= n.
>
> The implementation does not have much functionality (besides accepting=
> the instructions and not qualifying them as illegal instructions if > the hart executes in the required privilege level for the instruction)= ,
> as QEMU does not model CPU caches and instructions are documented
> to not raise any exceptions.
>
> Changes in v2:
> - Add ISA_EXT_DATA_ENTRY()
> - Explicit test for PRV_U
> - Encapsule access to env-priv in inline function
> - Use single decoder for XThead extensions
>
> Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Signed-off-by: Christoph M=C3=BCllner <christoph.muellner@vrull.eu> > ---
>=C2=A0 target/riscv/cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 2 +
>=C2=A0 target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 1 +
>=C2=A0 target/riscv/insn_trans/trans_xthead.c.inc | 89 ++++++++++++++++= ++++++
>=C2=A0 target/riscv/meson.build=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 1 +
>=C2=A0 target/riscv/translate.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 15 +++-
>=C2=A0 target/riscv/xthead.decode=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0| 38 +++++++++
>=C2=A0 6 files changed, 143 insertions(+), 3 deletions(-)
>=C2=A0 create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc >=C2=A0 create mode 100644 target/riscv/xthead.decode
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6fe176e483..a90b82c5c5 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -108,6 +108,7 @@ static const struct isa_ext_data isa_edata_arr[] = =3D {
>=C2=A0 =C2=A0 =C2=A0 ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_1= 2_0, ext_svinval),
>=C2=A0 =C2=A0 =C2=A0 ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_1= 2_0, ext_svnapot),
>=C2=A0 =C2=A0 =C2=A0 ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12= _0, ext_svpbmt),
> +=C2=A0 =C2=A0 ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0= , ext_xtheadcmo),
>=C2=A0 =C2=A0 =C2=A0 ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VER= SION_1_12_0, ext_XVentanaCondOps),
>=C2=A0 };
>
> @@ -1060,6 +1061,7 @@ static Property riscv_cpu_extensions[] =3D {
>=C2=A0 =C2=A0 =C2=A0 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.= ext_zmmul, false),
>
>=C2=A0 =C2=A0 =C2=A0 /* Vendor-specific custom extensions */
> +=C2=A0 =C2=A0 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.e= xt_xtheadcmo, false),
>=C2=A0 =C2=A0 =C2=A0 DEFINE_PROP_BOOL("xventanacondops", RISC= VCPU, cfg.ext_XVentanaCondOps, false),
>
>=C2=A0 =C2=A0 =C2=A0 /* These are experimental so mark with 'x-'= ; */
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 443d15a47c..ad1c19f870 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -465,6 +465,7 @@ struct RISCVCPUConfig {
>=C2=A0 =C2=A0 =C2=A0 uint64_t mimpid;
>
>=C2=A0 =C2=A0 =C2=A0 /* Vendor-specific custom extensions */
> +=C2=A0 =C2=A0 bool ext_xtheadcmo;
>=C2=A0 =C2=A0 =C2=A0 bool ext_XVentanaCondOps;
>
>=C2=A0 =C2=A0 =C2=A0 uint8_t pmu_num;
> diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv= /insn_trans/trans_xthead.c.inc
> new file mode 100644
> index 0000000000..00e75c7dca
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_xthead.c.inc
> @@ -0,0 +1,89 @@
> +/*
> + * RISC-V translation routines for the T-Head vendor extensions (xthe= ad*).
> + *
> + * Copyright (c) 2022 VRULL GmbH.
> + *
> + * This program is free software; you can redistribute it and/or modi= fy it
> + * under the terms and conditions of the GNU General Public License,<= br> > + * version 2 or later, as published by the Free Software Foundation.<= br> > + *
> + * This program is distributed in the hope it will be useful, but WIT= HOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY= or
> + * FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the GNU General Public= License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License = along with
> + * this program.=C2=A0 If not, see <http://www.gnu.org/licenses= />.
> + */
> +
> +#define REQUIRE_XTHEADCMO(ctx) do {=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 \
> +=C2=A0 =C2=A0 if (!ctx->cfg_ptr->ext_xtheadcmo) {=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 \
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return false;=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \
> +=C2=A0 =C2=A0 }=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 \
> +} while (0)
> +
> +/* XTheadCmo */
> +
> +static inline int priv_level(DisasContext *ctx)
> +{
> +#ifdef CONFIG_USER_ONLY
> +=C2=A0 =C2=A0 return PRV_U;
> +#else
> +=C2=A0 =C2=A0 =C2=A0/* Priv level equals mem_idx -- see cpu_mmu_index= . */
> +=C2=A0 =C2=A0 return ctx->mem_idx;

This should be ANDed with TB_FLAGS_PRIV_MMU_MASK as sometimes this can
include hypervisor priv access information

<= div>Ok.
=C2=A0

> +#endif
> +}
> +
> +#define REQUIRE_PRIV_MHSU(ctx)=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 \
> +do {=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \=
> +=C2=A0 =C2=A0 int priv =3D priv_level(ctx);=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0\
> +=C2=A0 =C2=A0 if (!(priv =3D=3D PRV_M ||=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 priv =3D=3D PRV_H ||=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \

PRV_H isn't used

> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 priv =3D=3D PRV_S ||=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 priv =3D=3D PRV_U)) {=C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0\
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return false;=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0\

When would this not be the case?

Ok, I = will make this a macro that expands to nothing (and a comment).
= =C2=A0

> +=C2=A0 =C2=A0 }=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0\
> +} while (0)
> +
> +#define REQUIRE_PRIV_MHS(ctx)=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0\
> +do {=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \=
> +=C2=A0 =C2=A0 int priv =3D priv_level(ctx);=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0\
> +=C2=A0 =C2=A0 if (!(priv =3D=3D PRV_M ||=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 priv =3D=3D PRV_H ||=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \

Also not used

Ok, I will remove the PRV= _H.
=C2=A0

> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 priv =3D=3D PRV_S)) {=C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0\
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return false;=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0\
> +=C2=A0 =C2=A0 }=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0\
> +} while (0)
> +
> +#define NOP_PRIVCHECK(insn, extcheck, privcheck)=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \
> +static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn * a) \
> +{=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0\
> +=C2=A0 =C2=A0 (void) a;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0\
> +=C2=A0 =C2=A0 extcheck(ctx);=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \
> +=C2=A0 =C2=A0 privcheck(ctx);=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0\
> +=C2=A0 =C2=A0 return true;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \
> +}
> +
> +NOP_PRIVCHECK(th_dcache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_cpa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS)
> +NOP_PRIVCHECK(th_dcache_cipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS)
> +NOP_PRIVCHECK(th_dcache_cva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) > +NOP_PRIVCHECK(th_dcache_civa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) > +NOP_PRIVCHECK(th_dcache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) > +NOP_PRIVCHECK(th_dcache_csw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS)
> +NOP_PRIVCHECK(th_dcache_cisw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_isw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS)
> +NOP_PRIVCHECK(th_dcache_cpal1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_cval1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +
> +NOP_PRIVCHECK(th_icache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_icache_ialls, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_icache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS)
> +NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) > +
> +NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS)<= br> > +NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > diff --git a/target/riscv/meson.build b/target/riscv/meson.build
> index ba25164d74..5dee37a242 100644
> --- a/target/riscv/meson.build
> +++ b/target/riscv/meson.build
> @@ -2,6 +2,7 @@
>=C2=A0 gen =3D [
>=C2=A0 =C2=A0 decodetree.process('insn16.decode', extra_args: [= '--static-decode=3Ddecode_insn16', '--insnwidth=3D16']), >=C2=A0 =C2=A0 decodetree.process('insn32.decode', extra_args: &= #39;--static-decode=3Ddecode_insn32'),
> +=C2=A0 decodetree.process('xthead.decode', extra_args: '-= -static-decode=3Ddecode_xthead'),
>=C2=A0 =C2=A0 decodetree.process('XVentanaCondOps.decode', extr= a_args: '--static-decode=3Ddecode_XVentanaCodeOps'),
>=C2=A0 ]
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index db123da5ec..14d9116975 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -125,13 +125,18 @@ static bool always_true_p(DisasContext *ctx=C2= =A0 __attribute__((__unused__)))
>=C2=A0 =C2=A0 =C2=A0 return true;
>=C2=A0 }
>
> +static bool has_xthead_p(DisasContext *ctx=C2=A0 __attribute__((__unu= sed__)))
> +{
> +=C2=A0 =C2=A0 return ctx->cfg_ptr->ext_xtheadcmo;
> +}
> +
>=C2=A0 #define MATERIALISE_EXT_PREDICATE(ext)=C2=A0 \
>=C2=A0 =C2=A0 =C2=A0 static bool has_ ## ext ## _p(DisasContext *ctx)= =C2=A0 =C2=A0 \
>=C2=A0 =C2=A0 =C2=A0 { \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return ctx->cfg_ptr->ext_ ## e= xt ; \
>=C2=A0 =C2=A0 =C2=A0 }
>
> -MATERIALISE_EXT_PREDICATE(XVentanaCondOps);
> +MATERIALISE_EXT_PREDICATE(XVentanaCondOps)

Do we need this change?

It is indeed a = drive-by cleanup, that is not necessary.
In v1 we were using this= macro, therefore it made sense back then.
Will be dropped.
=
=C2=A0

>
>=C2=A0 #ifdef TARGET_RISCV32
>=C2=A0 #define get_xl(ctx)=C2=A0 =C2=A0 MXL_RV32
> @@ -732,6 +737,10 @@ static int ex_rvc_shiftri(DisasContext *ctx, int = imm)
>=C2=A0 /* Include the auto-generated decoder for 32 bit insn */
>=C2=A0 #include "decode-insn32.c.inc"
>
> +/* Include decoders for factored-out extensions */
> +#include "decode-xthead.c.inc"
> +#include "decode-XVentanaCondOps.c.inc"
> +
>=C2=A0 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0void (*func)(TCGv, TCGv, target_lo= ng))
>=C2=A0 {
> @@ -1033,12 +1042,11 @@ static uint32_t opcode_at(DisasContextBase *dc= base, target_ulong pc)
>=C2=A0 #include "insn_trans/trans_rvk.c.inc"
>=C2=A0 #include "insn_trans/trans_privileged.c.inc"
>=C2=A0 #include "insn_trans/trans_svinval.c.inc"
> +#include "insn_trans/trans_xthead.c.inc"
>=C2=A0 #include "insn_trans/trans_xventanacondops.c.inc"
>
>=C2=A0 /* Include the auto-generated decoder for 16 bit insn */
>=C2=A0 #include "decode-insn16.c.inc"
> -/* Include decoders for factored-out extensions */
> -#include "decode-XVentanaCondOps.c.inc"

Can we not leave these at the bottom?

O= k.


Alistair

>
>=C2=A0 /* The specification allows for longer insns, but not supported = by qemu. */
>=C2=A0 #define MAX_INSN_LEN=C2=A0 4
> @@ -1059,6 +1067,7 @@ static void decode_opc(CPURISCVState *env, Disas= Context *ctx, uint16_t opcode)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bool (*decode_func)(DisasContext *, = uint32_t);
>=C2=A0 =C2=A0 =C2=A0 } decoders[] =3D {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 { always_true_p,=C2=A0 decode_insn32= },
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 { has_xthead_p, decode_xthead },
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 { has_XVentanaCondOps_p,=C2=A0 decod= e_XVentanaCodeOps },
>=C2=A0 =C2=A0 =C2=A0 };
>
> diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode > new file mode 100644
> index 0000000000..30533a66f5
> --- /dev/null
> +++ b/target/riscv/xthead.decode
> @@ -0,0 +1,38 @@
> +#
> +# Translation routines for the instructions of the XThead* ISA extens= ions
> +#
> +# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu
> +#
> +# SPDX-License-Identifier: LGPL-2.1-or-later
> +#
> +# The documentation of the ISA extensions can be found here:
> +#=C2=A0 =C2=A0https://githu= b.com/T-head-Semi/thead-extension-spec/releases/latest
> +
> +# Fields:
> +%rs1=C2=A0 =C2=A0 =C2=A0 =C2=A015:5
> +
> +# Formats
> +@sfence_vm=C2=A0 ....... ..... .....=C2=A0 =C2=A0... ..... ....... %r= s1
> +
> +# XTheadCmo
> +th_dcache_call=C2=A0 =C2=A00000000 00001 00000 000 00000 0001011
> +th_dcache_ciall=C2=A0 0000000 00011 00000 000 00000 0001011
> +th_dcache_iall=C2=A0 =C2=A00000000 00010 00000 000 00000 0001011
> +th_dcache_cpa=C2=A0 =C2=A0 0000001 01001 ..... 000 00000 0001011 @sfe= nce_vm
> +th_dcache_cipa=C2=A0 =C2=A00000001 01011 ..... 000 00000 0001011 @sfe= nce_vm
> +th_dcache_ipa=C2=A0 =C2=A0 0000001 01010 ..... 000 00000 0001011 @sfe= nce_vm
> +th_dcache_cva=C2=A0 =C2=A0 0000001 00101 ..... 000 00000 0001011 @sfe= nce_vm
> +th_dcache_civa=C2=A0 =C2=A00000001 00111 ..... 000 00000 0001011 @sfe= nce_vm
> +th_dcache_iva=C2=A0 =C2=A0 0000001 00110 ..... 000 00000 0001011 @sfe= nce_vm
> +th_dcache_csw=C2=A0 =C2=A0 0000001 00001 ..... 000 00000 0001011 @sfe= nce_vm
> +th_dcache_cisw=C2=A0 =C2=A00000001 00011 ..... 000 00000 0001011 @sfe= nce_vm
> +th_dcache_isw=C2=A0 =C2=A0 0000001 00010 ..... 000 00000 0001011 @sfe= nce_vm
> +th_dcache_cpal1=C2=A0 0000001 01000 ..... 000 00000 0001011 @sfence_v= m
> +th_dcache_cval1=C2=A0 0000001 00100 ..... 000 00000 0001011 @sfence_v= m
> +th_icache_iall=C2=A0 =C2=A00000000 10000 00000 000 00000 0001011
> +th_icache_ialls=C2=A0 0000000 10001 00000 000 00000 0001011
> +th_icache_ipa=C2=A0 =C2=A0 0000001 11000 ..... 000 00000 0001011 @sfe= nce_vm
> +th_icache_iva=C2=A0 =C2=A0 0000001 10000 ..... 000 00000 0001011 @sfe= nce_vm
> +th_l2cache_call=C2=A0 0000000 10101 00000 000 00000 0001011
> +th_l2cache_ciall 0000000 10111 00000 000 00000 0001011
> +th_l2cache_iall=C2=A0 0000000 10110 00000 000 00000 0001011
> --
> 2.38.1
>
>
--00000000000045669a05f305e209-- From MAILER-DAEMON Tue Jan 24 12:31:34 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKN8w-0008Di-If for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 12:31:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKN8r-0008CZ-KA for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 12:31:29 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKN8p-0000Xm-Jr for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 12:31:29 -0500 Received: by mail-wr1-x42b.google.com with SMTP id e3so14597887wru.13 for ; Tue, 24 Jan 2023 09:31:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=Pd4xwn7t+vRql5ciugXSa/3ZzrfRriKwhEgYAHyx0/A=; b=MdzmTHeg9bop+z5ks5sfVCDk63KLmKgfPcHmRCvCnbQxAVIqg8iWTPpLwUzJAN59tx /joDAPy8fsAVb0ogKjaMaaUM0ExeBj6bcKQyk36feXnQMBRq51MlcaJdoL9XfPHMRYTO peTqnrNBJDWFjxuBj+lnFMf1nRnc13k5jTr/2qjC9hTBUGiGqMI8kvIVo37KE4bzLYFx rQuTdtJEkKHXaEQTYeAVW8Uo6Cb3+R7A4b16p4QthX4lR6dG60qVdL0DbYbVX4OJbehC QsfSZyNaucZad6G3Rb4otn5PRjJHUsFbcO7VcWiQ1RbeSWHKKuHOrCYXK7EHg9UIMqa/ H2Ww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=Pd4xwn7t+vRql5ciugXSa/3ZzrfRriKwhEgYAHyx0/A=; b=p5W58YC1+4yE2bfd4YLpi5l3CrwSbMsEw6CB3dj1mB1F2WPZtnch6u9ephFtYZZ79D MzVIiB0jcZaOZso6tzji9srV4H+y5TSBSoxbAv6Fxr9YvCdFwLi6Z2JlKBtSZaOMYRBP pj3J0q+jSwcHM6M964yhgoX3WY84X8HZKrCfMDlcUqY4+p0vPPfxT4EnVAB2v7zMx8/d QAhztN8oOmMhLK7NeApaMXdj+B5HczW/LJfM/IZpP+KWerLdF329M1wnj9ZVksBAxSsu Q4CXlIdhp2aRwzTE1HjjBULoVZML/CO8wRWh21qeMVe2Aho2vKPSVYuEeVG8ybK9+v6M 3jUQ== X-Gm-Message-State: AFqh2koE+Es7NVQK6VnWUCQApHhXLnhZjObMNrFrmNO8fEJBl46eVvou zr1pzKgzzGW7fKp/rXuv/+A9TTv3krLcqp0X1+0bVQ== X-Google-Smtp-Source: AMrXdXvP+N8FxA4uuFUzQfxJjPi9Fa/WsUEjH5sv8MoiCBJVemtre0HZhLBD/QsHBbHASl7yjoFSQ5KG19U6K0J3gDU= X-Received: by 2002:adf:e64c:0:b0:2bc:8399:f994 with SMTP id b12-20020adfe64c000000b002bc8399f994mr874945wrn.674.1674581486422; Tue, 24 Jan 2023 09:31:26 -0800 (PST) MIME-Version: 1.0 References: <20221223180016.2068508-1-christoph.muellner@vrull.eu> <20221223180016.2068508-12-christoph.muellner@vrull.eu> In-Reply-To: From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Tue, 24 Jan 2023 18:31:14 +0100 Message-ID: Subject: Re: [PATCH v2 11/15] RISC-V: Adding T-Head XMAE support To: Alistair Francis Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: multipart/alternative; boundary="000000000000a55f4805f305e2f0" Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 17:31:29 -0000 --000000000000a55f4805f305e2f0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Jan 24, 2023 at 12:49 AM Alistair Francis wrote: > On Sat, Dec 24, 2022 at 4:04 AM Christoph Muellner > wrote: > > > > From: Christoph M=C3=BCllner > > > > This patch adds support for the T-Head specific extended memory > > attributes. Similar like Svpbmt, this support does not have much effect > > as most behaviour is not modelled in QEMU. > > > > We also don't set any EDATA information, because XMAE discovery is done > > using the vendor ID in the Linux kernel. > > > > Changes in v2: > > - Add ISA_EXT_DATA_ENTRY() > > > > Co-developed-by: LIU Zhiwei > > Signed-off-by: Christoph M=C3=BCllner > > --- > > target/riscv/cpu.c | 2 ++ > > target/riscv/cpu.h | 1 + > > target/riscv/cpu_helper.c | 6 ++++-- > > 3 files changed, 7 insertions(+), 2 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 9c31a50e90..bb310755b1 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -118,6 +118,7 @@ static const struct isa_ext_data isa_edata_arr[] = =3D { > > ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, > ext_xtheadmemidx), > > ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, > ext_xtheadmempair), > > ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, > ext_xtheadsync), > > + ISA_EXT_DATA_ENTRY(xtheadxmae, true, PRIV_VERSION_1_11_0, > ext_xtheadxmae), > > ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, > ext_XVentanaCondOps), > > }; > > > > @@ -1080,6 +1081,7 @@ static Property riscv_cpu_extensions[] =3D { > > DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, > false), > > DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, > false), > > DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false= ), > > + DEFINE_PROP_BOOL("xtheadxmae", RISCVCPU, cfg.ext_xtheadxmae, false= ), > > DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, > cfg.ext_XVentanaCondOps, false), > > > > /* These are experimental so mark with 'x-' */ > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index c97c1c0af0..897962f107 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -475,6 +475,7 @@ struct RISCVCPUConfig { > > bool ext_xtheadmemidx; > > bool ext_xtheadmempair; > > bool ext_xtheadsync; > > + bool ext_xtheadxmae; > > bool ext_XVentanaCondOps; > > > > uint8_t pmu_num; > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > > index 278d163803..345bb69b79 100644 > > --- a/target/riscv/cpu_helper.c > > +++ b/target/riscv/cpu_helper.c > > @@ -938,7 +938,8 @@ restart: > > > > if (riscv_cpu_sxl(env) =3D=3D MXL_RV32) { > > ppn =3D pte >> PTE_PPN_SHIFT; > > - } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot) { > > + } else if (cpu->cfg.ext_svpbmt || cpu->cfg.ext_svnapot || > > + cpu->cfg.ext_xtheadxmae) { > > I don't like this. This is some pretty core code that is now getting > vendor extensions. I know this is very simple, but I'm worried we are > opening the doors to other vendors adding their MMU changes. > > Can we just set ext_svpbmt instead? > Ok. I will drop this patch. > > Alistair > > > ppn =3D (pte & (target_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIF= T; > > } else { > > ppn =3D pte >> PTE_PPN_SHIFT; > > @@ -950,7 +951,8 @@ restart: > > if (!(pte & PTE_V)) { > > /* Invalid PTE */ > > return TRANSLATE_FAIL; > > - } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT)) { > > + } else if (!cpu->cfg.ext_svpbmt && (pte & PTE_PBMT) && > > + !cpu->cfg.ext_xtheadxmae) { > > return TRANSLATE_FAIL; > > } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { > > /* Inner PTE, continue walking */ > > -- > > 2.38.1 > > > > > --000000000000a55f4805f305e2f0 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Tue, Jan 24, 2023 at 12:49 AM Alis= tair Francis <alistair23@gmail.c= om> wrote:
christ= oph.muellner@vrull.eu> wrote:
>
> From: Christoph M=C3=BCllner <christoph.muellner@vrull.eu>
>
> This patch adds support for the T-Head specific extended memory
> attributes. Similar like Svpbmt, this support does not have much effec= t
> as most behaviour is not modelled in QEMU.
>
> We also don't set any EDATA information, because XMAE discovery is= done
> using the vendor ID in the Linux kernel.
>
> Changes in v2:
> - Add ISA_EXT_DATA_ENTRY()
>
> Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Signed-off-by: Christoph M=C3=BCllner <christoph.muellner@vrull.eu> > ---
>=C2=A0 target/riscv/cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 | 2 ++
>=C2=A0 target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 | 1 +
>=C2=A0 target/riscv/cpu_helper.c | 6 ++++--
>=C2=A0 3 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 9c31a50e90..bb310755b1 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -118,6 +118,7 @@ static const struct isa_ext_data isa_edata_arr[] = =3D {
>=C2=A0 =C2=A0 =C2=A0 ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSIO= N_1_11_0, ext_xtheadmemidx),
>=C2=A0 =C2=A0 =C2=A0 ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSI= ON_1_11_0, ext_xtheadmempair),
>=C2=A0 =C2=A0 =C2=A0 ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_= 1_11_0, ext_xtheadsync),
> +=C2=A0 =C2=A0 ISA_EXT_DATA_ENTRY(xtheadxmae, true, PRIV_VERSION_1_11_= 0, ext_xtheadxmae),
>=C2=A0 =C2=A0 =C2=A0 ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VER= SION_1_12_0, ext_XVentanaCondOps),
>=C2=A0 };
>
> @@ -1080,6 +1081,7 @@ static Property riscv_cpu_extensions[] =3D {
>=C2=A0 =C2=A0 =C2=A0 DEFINE_PROP_BOOL("xtheadmemidx", RISCVCP= U, cfg.ext_xtheadmemidx, false),
>=C2=A0 =C2=A0 =C2=A0 DEFINE_PROP_BOOL("xtheadmempair", RISCVC= PU, cfg.ext_xtheadmempair, false),
>=C2=A0 =C2=A0 =C2=A0 DEFINE_PROP_BOOL("xtheadsync", RISCVCPU,= cfg.ext_xtheadsync, false),
> +=C2=A0 =C2=A0 DEFINE_PROP_BOOL("xtheadxmae", RISCVCPU, cfg.= ext_xtheadxmae, false),
>=C2=A0 =C2=A0 =C2=A0 DEFINE_PROP_BOOL("xventanacondops", RISC= VCPU, cfg.ext_XVentanaCondOps, false),
>
>=C2=A0 =C2=A0 =C2=A0 /* These are experimental so mark with 'x-'= ; */
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index c97c1c0af0..897962f107 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -475,6 +475,7 @@ struct RISCVCPUConfig {
>=C2=A0 =C2=A0 =C2=A0 bool ext_xtheadmemidx;
>=C2=A0 =C2=A0 =C2=A0 bool ext_xtheadmempair;
>=C2=A0 =C2=A0 =C2=A0 bool ext_xtheadsync;
> +=C2=A0 =C2=A0 bool ext_xtheadxmae;
>=C2=A0 =C2=A0 =C2=A0 bool ext_XVentanaCondOps;
>
>=C2=A0 =C2=A0 =C2=A0 uint8_t pmu_num;
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index 278d163803..345bb69b79 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -938,7 +938,8 @@ restart:
>
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (riscv_cpu_sxl(env) =3D=3D MXL_RV= 32) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ppn =3D pte >> P= TE_PPN_SHIFT;
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else if (cpu->cfg.ext_svpbmt || cpu-= >cfg.ext_svnapot) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else if (cpu->cfg.ext_svpbmt || cpu-= >cfg.ext_svnapot ||
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= cpu->cfg.ext_xtheadxmae) {

I don't like this. This is some pretty core code that is now getting vendor extensions. I know this is very simple, but I'm worried we are opening the doors to other vendors adding their MMU changes.

Can we just set ext_svpbmt instead?

Ok.=
I will drop this patch.
=C2=A0

Alistair

>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ppn =3D (pte & (ta= rget_ulong)PTE_PPN_MASK) >> PTE_PPN_SHIFT;
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 } else {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 ppn =3D pte >> P= TE_PPN_SHIFT;
> @@ -950,7 +951,8 @@ restart:
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 if (!(pte & PTE_V)) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Invalid PTE */
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return TRANSLATE_FAIL;=
> -=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else if (!cpu->cfg.ext_svpbmt &&= amp; (pte & PTE_PBMT)) {
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 } else if (!cpu->cfg.ext_svpbmt &&= amp; (pte & PTE_PBMT) &&
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= !cpu->cfg.ext_xtheadxmae) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return TRANSLATE_FAIL;=
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 } else if (!(pte & (PTE_R | PTE_= W | PTE_X))) {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* Inner PTE, continue= walking */
> --
> 2.38.1
>
>
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Tue, 24 Jan 2023 11:51:39 -0800 (PST) MIME-Version: 1.0 References: <20221223180016.2068508-1-christoph.muellner@vrull.eu> <20221223180016.2068508-2-christoph.muellner@vrull.eu> In-Reply-To: From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Tue, 24 Jan 2023 20:51:26 +0100 Message-ID: Subject: Re: [PATCH v2 01/15] RISC-V: Adding XTheadCmo ISA extension To: Alistair Francis Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: multipart/alternative; boundary="0000000000001432e805f307d81a" Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=christoph.muellner@vrull.eu; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 19:51:45 -0000 --0000000000001432e805f307d81a Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Tue, Jan 24, 2023 at 6:31 PM Christoph M=C3=BCllner < christoph.muellner@vrull.eu> wrote: > > > On Mon, Jan 23, 2023 at 11:50 PM Alistair Francis > wrote: > >> On Sat, Dec 24, 2022 at 4:09 AM Christoph Muellner >> wrote: >> > >> > From: Christoph M=C3=BCllner >> > >> > This patch adds support for the XTheadCmo ISA extension. >> > To avoid interfering with standard extensions, decoder and translation >> > are in its own xthead* specific files. >> > Future patches should be able to easily add additional T-Head extensio= n. >> > >> > The implementation does not have much functionality (besides accepting >> > the instructions and not qualifying them as illegal instructions if >> > the hart executes in the required privilege level for the instruction)= , >> > as QEMU does not model CPU caches and instructions are documented >> > to not raise any exceptions. >> > >> > Changes in v2: >> > - Add ISA_EXT_DATA_ENTRY() >> > - Explicit test for PRV_U >> > - Encapsule access to env-priv in inline function >> > - Use single decoder for XThead extensions >> > >> > Co-developed-by: LIU Zhiwei >> > Signed-off-by: Christoph M=C3=BCllner >> > --- >> > target/riscv/cpu.c | 2 + >> > target/riscv/cpu.h | 1 + >> > target/riscv/insn_trans/trans_xthead.c.inc | 89 +++++++++++++++++++++= + >> > target/riscv/meson.build | 1 + >> > target/riscv/translate.c | 15 +++- >> > target/riscv/xthead.decode | 38 +++++++++ >> > 6 files changed, 143 insertions(+), 3 deletions(-) >> > create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc >> > create mode 100644 target/riscv/xthead.decode >> > >> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> > index 6fe176e483..a90b82c5c5 100644 >> > --- a/target/riscv/cpu.c >> > +++ b/target/riscv/cpu.c >> > @@ -108,6 +108,7 @@ static const struct isa_ext_data isa_edata_arr[] = =3D { >> > ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, >> ext_svinval), >> > ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, >> ext_svnapot), >> > ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt)= , >> > + ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, >> ext_xtheadcmo), >> > ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, >> ext_XVentanaCondOps), >> > }; >> > >> > @@ -1060,6 +1061,7 @@ static Property riscv_cpu_extensions[] =3D { >> > DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), >> > >> > /* Vendor-specific custom extensions */ >> > + DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false)= , >> > DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, >> cfg.ext_XVentanaCondOps, false), >> > >> > /* These are experimental so mark with 'x-' */ >> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >> > index 443d15a47c..ad1c19f870 100644 >> > --- a/target/riscv/cpu.h >> > +++ b/target/riscv/cpu.h >> > @@ -465,6 +465,7 @@ struct RISCVCPUConfig { >> > uint64_t mimpid; >> > >> > /* Vendor-specific custom extensions */ >> > + bool ext_xtheadcmo; >> > bool ext_XVentanaCondOps; >> > >> > uint8_t pmu_num; >> > diff --git a/target/riscv/insn_trans/trans_xthead.c.inc >> b/target/riscv/insn_trans/trans_xthead.c.inc >> > new file mode 100644 >> > index 0000000000..00e75c7dca >> > --- /dev/null >> > +++ b/target/riscv/insn_trans/trans_xthead.c.inc >> > @@ -0,0 +1,89 @@ >> > +/* >> > + * RISC-V translation routines for the T-Head vendor extensions >> (xthead*). >> > + * >> > + * Copyright (c) 2022 VRULL GmbH. >> > + * >> > + * This program is free software; you can redistribute it and/or >> modify it >> > + * under the terms and conditions of the GNU General Public License, >> > + * version 2 or later, as published by the Free Software Foundation. >> > + * >> > + * This program is distributed in the hope it will be useful, but >> WITHOUT >> > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY >> or >> > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public >> License for >> > + * more details. >> > + * >> > + * You should have received a copy of the GNU General Public License >> along with >> > + * this program. If not, see . >> > + */ >> > + >> > +#define REQUIRE_XTHEADCMO(ctx) do { \ >> > + if (!ctx->cfg_ptr->ext_xtheadcmo) { \ >> > + return false; \ >> > + } \ >> > +} while (0) >> > + >> > +/* XTheadCmo */ >> > + >> > +static inline int priv_level(DisasContext *ctx) >> > +{ >> > +#ifdef CONFIG_USER_ONLY >> > + return PRV_U; >> > +#else >> > + /* Priv level equals mem_idx -- see cpu_mmu_index. */ >> > + return ctx->mem_idx; >> >> This should be ANDed with TB_FLAGS_PRIV_MMU_MASK as sometimes this can >> include hypervisor priv access information >> > > Ok. > > >> >> > +#endif >> > +} >> > + >> > +#define REQUIRE_PRIV_MHSU(ctx) \ >> > +do { \ >> > + int priv =3D priv_level(ctx); \ >> > + if (!(priv =3D=3D PRV_M || \ >> > + priv =3D=3D PRV_H || \ >> >> PRV_H isn't used >> >> > + priv =3D=3D PRV_S || \ >> > + priv =3D=3D PRV_U)) { \ >> > + return false; \ >> >> When would this not be the case? >> > > Ok, I will make this a macro that expands to nothing (and a comment). > > >> >> > + } \ >> > +} while (0) >> > + >> > +#define REQUIRE_PRIV_MHS(ctx) \ >> > +do { \ >> > + int priv =3D priv_level(ctx); \ >> > + if (!(priv =3D=3D PRV_M || \ >> > + priv =3D=3D PRV_H || \ >> >> Also not used >> > > Ok, I will remove the PRV_H. > > >> >> > + priv =3D=3D PRV_S)) { \ >> > + return false; \ >> > + } \ >> > +} while (0) >> > + >> > +#define NOP_PRIVCHECK(insn, extcheck, privcheck) \ >> > +static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn * a) \ >> > +{ \ >> > + (void) a; \ >> > + extcheck(ctx); \ >> > + privcheck(ctx); \ >> > + return true; \ >> > +} >> > + >> > +NOP_PRIVCHECK(th_dcache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >> > +NOP_PRIVCHECK(th_dcache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >> > +NOP_PRIVCHECK(th_dcache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >> > +NOP_PRIVCHECK(th_dcache_cpa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >> > +NOP_PRIVCHECK(th_dcache_cipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >> > +NOP_PRIVCHECK(th_dcache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >> > +NOP_PRIVCHECK(th_dcache_cva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) >> > +NOP_PRIVCHECK(th_dcache_civa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) >> > +NOP_PRIVCHECK(th_dcache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) >> > +NOP_PRIVCHECK(th_dcache_csw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >> > +NOP_PRIVCHECK(th_dcache_cisw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >> > +NOP_PRIVCHECK(th_dcache_isw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >> > +NOP_PRIVCHECK(th_dcache_cpal1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >> > +NOP_PRIVCHECK(th_dcache_cval1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >> > + >> > +NOP_PRIVCHECK(th_icache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >> > +NOP_PRIVCHECK(th_icache_ialls, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >> > +NOP_PRIVCHECK(th_icache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >> > +NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) >> > + >> > +NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >> > +NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >> > +NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >> > diff --git a/target/riscv/meson.build b/target/riscv/meson.build >> > index ba25164d74..5dee37a242 100644 >> > --- a/target/riscv/meson.build >> > +++ b/target/riscv/meson.build >> > @@ -2,6 +2,7 @@ >> > gen =3D [ >> > decodetree.process('insn16.decode', extra_args: >> ['--static-decode=3Ddecode_insn16', '--insnwidth=3D16']), >> > decodetree.process('insn32.decode', extra_args: >> '--static-decode=3Ddecode_insn32'), >> > + decodetree.process('xthead.decode', extra_args: >> '--static-decode=3Ddecode_xthead'), >> > decodetree.process('XVentanaCondOps.decode', extra_args: >> '--static-decode=3Ddecode_XVentanaCodeOps'), >> > ] >> > >> > diff --git a/target/riscv/translate.c b/target/riscv/translate.c >> > index db123da5ec..14d9116975 100644 >> > --- a/target/riscv/translate.c >> > +++ b/target/riscv/translate.c >> > @@ -125,13 +125,18 @@ static bool always_true_p(DisasContext *ctx >> __attribute__((__unused__))) >> > return true; >> > } >> > >> > +static bool has_xthead_p(DisasContext *ctx >> __attribute__((__unused__))) >> > +{ >> > + return ctx->cfg_ptr->ext_xtheadcmo; >> > +} >> > + >> > #define MATERIALISE_EXT_PREDICATE(ext) \ >> > static bool has_ ## ext ## _p(DisasContext *ctx) \ >> > { \ >> > return ctx->cfg_ptr->ext_ ## ext ; \ >> > } >> > >> > -MATERIALISE_EXT_PREDICATE(XVentanaCondOps); >> > +MATERIALISE_EXT_PREDICATE(XVentanaCondOps) >> >> Do we need this change? >> > > It is indeed a drive-by cleanup, that is not necessary. > In v1 we were using this macro, therefore it made sense back then. > Will be dropped. > > >> >> > >> > #ifdef TARGET_RISCV32 >> > #define get_xl(ctx) MXL_RV32 >> > @@ -732,6 +737,10 @@ static int ex_rvc_shiftri(DisasContext *ctx, int >> imm) >> > /* Include the auto-generated decoder for 32 bit insn */ >> > #include "decode-insn32.c.inc" >> > >> > +/* Include decoders for factored-out extensions */ >> > +#include "decode-xthead.c.inc" >> > +#include "decode-XVentanaCondOps.c.inc" >> > + >> > static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, >> > void (*func)(TCGv, TCGv, target_long)) >> > { >> > @@ -1033,12 +1042,11 @@ static uint32_t opcode_at(DisasContextBase >> *dcbase, target_ulong pc) >> > #include "insn_trans/trans_rvk.c.inc" >> > #include "insn_trans/trans_privileged.c.inc" >> > #include "insn_trans/trans_svinval.c.inc" >> > +#include "insn_trans/trans_xthead.c.inc" >> > #include "insn_trans/trans_xventanacondops.c.inc" >> > >> > /* Include the auto-generated decoder for 16 bit insn */ >> > #include "decode-insn16.c.inc" >> > -/* Include decoders for factored-out extensions */ >> > -#include "decode-XVentanaCondOps.c.inc" >> >> Can we not leave these at the bottom? >> > > Ok. > I got reminded again, why this is like it is: The decoder code needs to be included before the translation functions, because the translation functions use types that are defined in the generated decoder code. And I wanted to keep all vendor extensions together. I think your concern is about touching other code. Therefore, I will not touch the VT decoder position in the v3. Let me know if you prefer another solution. BR Christoph > > >> Alistair >> >> > >> > /* The specification allows for longer insns, but not supported by >> qemu. */ >> > #define MAX_INSN_LEN 4 >> > @@ -1059,6 +1067,7 @@ static void decode_opc(CPURISCVState *env, >> DisasContext *ctx, uint16_t opcode) >> > bool (*decode_func)(DisasContext *, uint32_t); >> > } decoders[] =3D { >> > { always_true_p, decode_insn32 }, >> > + { has_xthead_p, decode_xthead }, >> > { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, >> > }; >> > >> > diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode >> > new file mode 100644 >> > index 0000000000..30533a66f5 >> > --- /dev/null >> > +++ b/target/riscv/xthead.decode >> > @@ -0,0 +1,38 @@ >> > +# >> > +# Translation routines for the instructions of the XThead* ISA >> extensions >> > +# >> > +# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu >> > +# >> > +# SPDX-License-Identifier: LGPL-2.1-or-later >> > +# >> > +# The documentation of the ISA extensions can be found here: >> > +# >> https://github.com/T-head-Semi/thead-extension-spec/releases/latest >> > + >> > +# Fields: >> > +%rs1 15:5 >> > + >> > +# Formats >> > +@sfence_vm ....... ..... ..... ... ..... ....... %rs1 >> > + >> > +# XTheadCmo >> > +th_dcache_call 0000000 00001 00000 000 00000 0001011 >> > +th_dcache_ciall 0000000 00011 00000 000 00000 0001011 >> > +th_dcache_iall 0000000 00010 00000 000 00000 0001011 >> > +th_dcache_cpa 0000001 01001 ..... 000 00000 0001011 @sfence_vm >> > +th_dcache_cipa 0000001 01011 ..... 000 00000 0001011 @sfence_vm >> > +th_dcache_ipa 0000001 01010 ..... 000 00000 0001011 @sfence_vm >> > +th_dcache_cva 0000001 00101 ..... 000 00000 0001011 @sfence_vm >> > +th_dcache_civa 0000001 00111 ..... 000 00000 0001011 @sfence_vm >> > +th_dcache_iva 0000001 00110 ..... 000 00000 0001011 @sfence_vm >> > +th_dcache_csw 0000001 00001 ..... 000 00000 0001011 @sfence_vm >> > +th_dcache_cisw 0000001 00011 ..... 000 00000 0001011 @sfence_vm >> > +th_dcache_isw 0000001 00010 ..... 000 00000 0001011 @sfence_vm >> > +th_dcache_cpal1 0000001 01000 ..... 000 00000 0001011 @sfence_vm >> > +th_dcache_cval1 0000001 00100 ..... 000 00000 0001011 @sfence_vm >> > +th_icache_iall 0000000 10000 00000 000 00000 0001011 >> > +th_icache_ialls 0000000 10001 00000 000 00000 0001011 >> > +th_icache_ipa 0000001 11000 ..... 000 00000 0001011 @sfence_vm >> > +th_icache_iva 0000001 10000 ..... 000 00000 0001011 @sfence_vm >> > +th_l2cache_call 0000000 10101 00000 000 00000 0001011 >> > +th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 >> > +th_l2cache_iall 0000000 10110 00000 000 00000 0001011 >> > -- >> > 2.38.1 >> > >> > >> > --0000000000001432e805f307d81a Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Tue, Jan 24, 2023 at 6:31 PM Chris= toph M=C3=BCllner <christ= oph.muellner@vrull.eu> wrote:


On Mon, Jan 23, = 2023 at 11:50 PM Alistair Francis <alistair23@gmail.com> wrote:
On Sat, Dec 24, 2022 at 4:09 AM Ch= ristoph Muellner
<christ= oph.muellner@vrull.eu> wrote:
>
> From: Christoph M=C3=BCllner <christoph.muellner@vrull.eu>
>
> This patch adds support for the XTheadCmo ISA extension.
> To avoid interfering with standard extensions, decoder and translation=
> are in its own xthead* specific files.
> Future patches should be able to easily add additional T-Head extensio= n.
>
> The implementation does not have much functionality (besides accepting=
> the instructions and not qualifying them as illegal instructions if > the hart executes in the required privilege level for the instruction)= ,
> as QEMU does not model CPU caches and instructions are documented
> to not raise any exceptions.
>
> Changes in v2:
> - Add ISA_EXT_DATA_ENTRY()
> - Explicit test for PRV_U
> - Encapsule access to env-priv in inline function
> - Use single decoder for XThead extensions
>
> Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
> Signed-off-by: Christoph M=C3=BCllner <christoph.muellner@vrull.eu> > ---
>=C2=A0 target/riscv/cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 2 +
>=C2=A0 target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 1 +
>=C2=A0 target/riscv/insn_trans/trans_xthead.c.inc | 89 ++++++++++++++++= ++++++
>=C2=A0 target/riscv/meson.build=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 1 +
>=C2=A0 target/riscv/translate.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0| 15 +++-
>=C2=A0 target/riscv/xthead.decode=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0| 38 +++++++++
>=C2=A0 6 files changed, 143 insertions(+), 3 deletions(-)
>=C2=A0 create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc >=C2=A0 create mode 100644 target/riscv/xthead.decode
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 6fe176e483..a90b82c5c5 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -108,6 +108,7 @@ static const struct isa_ext_data isa_edata_arr[] = =3D {
>=C2=A0 =C2=A0 =C2=A0 ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_1= 2_0, ext_svinval),
>=C2=A0 =C2=A0 =C2=A0 ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_1= 2_0, ext_svnapot),
>=C2=A0 =C2=A0 =C2=A0 ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12= _0, ext_svpbmt),
> +=C2=A0 =C2=A0 ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0= , ext_xtheadcmo),
>=C2=A0 =C2=A0 =C2=A0 ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VER= SION_1_12_0, ext_XVentanaCondOps),
>=C2=A0 };
>
> @@ -1060,6 +1061,7 @@ static Property riscv_cpu_extensions[] =3D {
>=C2=A0 =C2=A0 =C2=A0 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.= ext_zmmul, false),
>
>=C2=A0 =C2=A0 =C2=A0 /* Vendor-specific custom extensions */
> +=C2=A0 =C2=A0 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.e= xt_xtheadcmo, false),
>=C2=A0 =C2=A0 =C2=A0 DEFINE_PROP_BOOL("xventanacondops", RISC= VCPU, cfg.ext_XVentanaCondOps, false),
>
>=C2=A0 =C2=A0 =C2=A0 /* These are experimental so mark with 'x-'= ; */
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 443d15a47c..ad1c19f870 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -465,6 +465,7 @@ struct RISCVCPUConfig {
>=C2=A0 =C2=A0 =C2=A0 uint64_t mimpid;
>
>=C2=A0 =C2=A0 =C2=A0 /* Vendor-specific custom extensions */
> +=C2=A0 =C2=A0 bool ext_xtheadcmo;
>=C2=A0 =C2=A0 =C2=A0 bool ext_XVentanaCondOps;
>
>=C2=A0 =C2=A0 =C2=A0 uint8_t pmu_num;
> diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv= /insn_trans/trans_xthead.c.inc
> new file mode 100644
> index 0000000000..00e75c7dca
> --- /dev/null
> +++ b/target/riscv/insn_trans/trans_xthead.c.inc
> @@ -0,0 +1,89 @@
> +/*
> + * RISC-V translation routines for the T-Head vendor extensions (xthe= ad*).
> + *
> + * Copyright (c) 2022 VRULL GmbH.
> + *
> + * This program is free software; you can redistribute it and/or modi= fy it
> + * under the terms and conditions of the GNU General Public License,<= br> > + * version 2 or later, as published by the Free Software Foundation.<= br> > + *
> + * This program is distributed in the hope it will be useful, but WIT= HOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY= or
> + * FITNESS FOR A PARTICULAR PURPOSE.=C2=A0 See the GNU General Public= License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License = along with
> + * this program.=C2=A0 If not, see <http://www.gnu.org/licenses= />.
> + */
> +
> +#define REQUIRE_XTHEADCMO(ctx) do {=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 \
> +=C2=A0 =C2=A0 if (!ctx->cfg_ptr->ext_xtheadcmo) {=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 \
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return false;=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \
> +=C2=A0 =C2=A0 }=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 \
> +} while (0)
> +
> +/* XTheadCmo */
> +
> +static inline int priv_level(DisasContext *ctx)
> +{
> +#ifdef CONFIG_USER_ONLY
> +=C2=A0 =C2=A0 return PRV_U;
> +#else
> +=C2=A0 =C2=A0 =C2=A0/* Priv level equals mem_idx -- see cpu_mmu_index= . */
> +=C2=A0 =C2=A0 return ctx->mem_idx;

This should be ANDed with TB_FLAGS_PRIV_MMU_MASK as sometimes this can
include hypervisor priv access information

<= div>Ok.
=C2=A0

> +#endif
> +}
> +
> +#define REQUIRE_PRIV_MHSU(ctx)=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 \
> +do {=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \=
> +=C2=A0 =C2=A0 int priv =3D priv_level(ctx);=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0\
> +=C2=A0 =C2=A0 if (!(priv =3D=3D PRV_M ||=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 priv =3D=3D PRV_H ||=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \

PRV_H isn't used

> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 priv =3D=3D PRV_S ||=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 priv =3D=3D PRV_U)) {=C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0\
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return false;=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0\

When would this not be the case?

Ok, I = will make this a macro that expands to nothing (and a comment).
= =C2=A0

> +=C2=A0 =C2=A0 }=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0\
> +} while (0)
> +
> +#define REQUIRE_PRIV_MHS(ctx)=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0\
> +do {=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \=
> +=C2=A0 =C2=A0 int priv =3D priv_level(ctx);=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0\
> +=C2=A0 =C2=A0 if (!(priv =3D=3D PRV_M ||=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 priv =3D=3D PRV_H ||=C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \

Also not used

Ok, I will remove the PRV= _H.
=C2=A0

> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 priv =3D=3D PRV_S)) {=C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0\
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 return false;=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0\
> +=C2=A0 =C2=A0 }=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0\
> +} while (0)
> +
> +#define NOP_PRIVCHECK(insn, extcheck, privcheck)=C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \
> +static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn * a) \
> +{=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0\
> +=C2=A0 =C2=A0 (void) a;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0\
> +=C2=A0 =C2=A0 extcheck(ctx);=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \
> +=C2=A0 =C2=A0 privcheck(ctx);=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0\
> +=C2=A0 =C2=A0 return true;=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 \
> +}
> +
> +NOP_PRIVCHECK(th_dcache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_cpa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS)
> +NOP_PRIVCHECK(th_dcache_cipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS)
> +NOP_PRIVCHECK(th_dcache_cva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) > +NOP_PRIVCHECK(th_dcache_civa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) > +NOP_PRIVCHECK(th_dcache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) > +NOP_PRIVCHECK(th_dcache_csw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS)
> +NOP_PRIVCHECK(th_dcache_cisw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_isw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS)
> +NOP_PRIVCHECK(th_dcache_cpal1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_dcache_cval1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +
> +NOP_PRIVCHECK(th_icache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_icache_ialls, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_icache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS)
> +NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) > +
> +NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > +NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS)<= br> > +NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > diff --git a/target/riscv/meson.build b/target/riscv/meson.build
> index ba25164d74..5dee37a242 100644
> --- a/target/riscv/meson.build
> +++ b/target/riscv/meson.build
> @@ -2,6 +2,7 @@
>=C2=A0 gen =3D [
>=C2=A0 =C2=A0 decodetree.process('insn16.decode', extra_args: [= '--static-decode=3Ddecode_insn16', '--insnwidth=3D16']), >=C2=A0 =C2=A0 decodetree.process('insn32.decode', extra_args: &= #39;--static-decode=3Ddecode_insn32'),
> +=C2=A0 decodetree.process('xthead.decode', extra_args: '-= -static-decode=3Ddecode_xthead'),
>=C2=A0 =C2=A0 decodetree.process('XVentanaCondOps.decode', extr= a_args: '--static-decode=3Ddecode_XVentanaCodeOps'),
>=C2=A0 ]
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index db123da5ec..14d9116975 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -125,13 +125,18 @@ static bool always_true_p(DisasContext *ctx=C2= =A0 __attribute__((__unused__)))
>=C2=A0 =C2=A0 =C2=A0 return true;
>=C2=A0 }
>
> +static bool has_xthead_p(DisasContext *ctx=C2=A0 __attribute__((__unu= sed__)))
> +{
> +=C2=A0 =C2=A0 return ctx->cfg_ptr->ext_xtheadcmo;
> +}
> +
>=C2=A0 #define MATERIALISE_EXT_PREDICATE(ext)=C2=A0 \
>=C2=A0 =C2=A0 =C2=A0 static bool has_ ## ext ## _p(DisasContext *ctx)= =C2=A0 =C2=A0 \
>=C2=A0 =C2=A0 =C2=A0 { \
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 return ctx->cfg_ptr->ext_ ## e= xt ; \
>=C2=A0 =C2=A0 =C2=A0 }
>
> -MATERIALISE_EXT_PREDICATE(XVentanaCondOps);
> +MATERIALISE_EXT_PREDICATE(XVentanaCondOps)

Do we need this change?

It is indeed a = drive-by cleanup, that is not necessary.
In v1 we were using this= macro, therefore it made sense back then.
Will be dropped.
=
=C2=A0

>
>=C2=A0 #ifdef TARGET_RISCV32
>=C2=A0 #define get_xl(ctx)=C2=A0 =C2=A0 MXL_RV32
> @@ -732,6 +737,10 @@ static int ex_rvc_shiftri(DisasContext *ctx, int = imm)
>=C2=A0 /* Include the auto-generated decoder for 32 bit insn */
>=C2=A0 #include "decode-insn32.c.inc"
>
> +/* Include decoders for factored-out extensions */
> +#include "decode-xthead.c.inc"
> +#include "decode-XVentanaCondOps.c.inc"
> +
>=C2=A0 static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a,
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0void (*func)(TCGv, TCGv, target_lo= ng))
>=C2=A0 {
> @@ -1033,12 +1042,11 @@ static uint32_t opcode_at(DisasContextBase *dc= base, target_ulong pc)
>=C2=A0 #include "insn_trans/trans_rvk.c.inc"
>=C2=A0 #include "insn_trans/trans_privileged.c.inc"
>=C2=A0 #include "insn_trans/trans_svinval.c.inc"
> +#include "insn_trans/trans_xthead.c.inc"
>=C2=A0 #include "insn_trans/trans_xventanacondops.c.inc"
>
>=C2=A0 /* Include the auto-generated decoder for 16 bit insn */
>=C2=A0 #include "decode-insn16.c.inc"
> -/* Include decoders for factored-out extensions */
> -#include "decode-XVentanaCondOps.c.inc"

Can we not leave these at the bottom?

O= k.

I got reminded again, = why this is like it is:
The decoder code needs to be included bef= ore the translation functions,
because the translation functions = use types that are defined in the generated decoder code.
And I w= anted=C2=A0to keep all vendor extensions together.
I think your c= oncern is about touching other code. Therefore, I will not touch the VT dec= oder position in the v3.
Let me know if you prefer another soluti= on.

BR
Christoph

=C2=A0


Alistair

>
>=C2=A0 /* The specification allows for longer insns, but not supported = by qemu. */
>=C2=A0 #define MAX_INSN_LEN=C2=A0 4
> @@ -1059,6 +1067,7 @@ static void decode_opc(CPURISCVState *env, Disas= Context *ctx, uint16_t opcode)
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 bool (*decode_func)(DisasContext *, = uint32_t);
>=C2=A0 =C2=A0 =C2=A0 } decoders[] =3D {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 { always_true_p,=C2=A0 decode_insn32= },
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 { has_xthead_p, decode_xthead },
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 { has_XVentanaCondOps_p,=C2=A0 decod= e_XVentanaCodeOps },
>=C2=A0 =C2=A0 =C2=A0 };
>
> diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode > new file mode 100644
> index 0000000000..30533a66f5
> --- /dev/null
> +++ b/target/riscv/xthead.decode
> @@ -0,0 +1,38 @@
> +#
> +# Translation routines for the instructions of the XThead* ISA extens= ions
> +#
> +# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu
> +#
> +# SPDX-License-Identifier: LGPL-2.1-or-later
> +#
> +# The documentation of the ISA extensions can be found here:
> +#=C2=A0 =C2=A0https://githu= b.com/T-head-Semi/thead-extension-spec/releases/latest
> +
> +# Fields:
> +%rs1=C2=A0 =C2=A0 =C2=A0 =C2=A015:5
> +
> +# Formats
> +@sfence_vm=C2=A0 ....... ..... .....=C2=A0 =C2=A0... ..... ....... %r= s1
> +
> +# XTheadCmo
> +th_dcache_call=C2=A0 =C2=A00000000 00001 00000 000 00000 0001011
> +th_dcache_ciall=C2=A0 0000000 00011 00000 000 00000 0001011
> +th_dcache_iall=C2=A0 =C2=A00000000 00010 00000 000 00000 0001011
> +th_dcache_cpa=C2=A0 =C2=A0 0000001 01001 ..... 000 00000 0001011 @sfe= nce_vm
> +th_dcache_cipa=C2=A0 =C2=A00000001 01011 ..... 000 00000 0001011 @sfe= nce_vm
> +th_dcache_ipa=C2=A0 =C2=A0 0000001 01010 ..... 000 00000 0001011 @sfe= nce_vm
> +th_dcache_cva=C2=A0 =C2=A0 0000001 00101 ..... 000 00000 0001011 @sfe= nce_vm
> +th_dcache_civa=C2=A0 =C2=A00000001 00111 ..... 000 00000 0001011 @sfe= nce_vm
> +th_dcache_iva=C2=A0 =C2=A0 0000001 00110 ..... 000 00000 0001011 @sfe= nce_vm
> +th_dcache_csw=C2=A0 =C2=A0 0000001 00001 ..... 000 00000 0001011 @sfe= nce_vm
> +th_dcache_cisw=C2=A0 =C2=A00000001 00011 ..... 000 00000 0001011 @sfe= nce_vm
> +th_dcache_isw=C2=A0 =C2=A0 0000001 00010 ..... 000 00000 0001011 @sfe= nce_vm
> +th_dcache_cpal1=C2=A0 0000001 01000 ..... 000 00000 0001011 @sfence_v= m
> +th_dcache_cval1=C2=A0 0000001 00100 ..... 000 00000 0001011 @sfence_v= m
> +th_icache_iall=C2=A0 =C2=A00000000 10000 00000 000 00000 0001011
> +th_icache_ialls=C2=A0 0000000 10001 00000 000 00000 0001011
> +th_icache_ipa=C2=A0 =C2=A0 0000001 11000 ..... 000 00000 0001011 @sfe= nce_vm
> +th_icache_iva=C2=A0 =C2=A0 0000001 10000 ..... 000 00000 0001011 @sfe= nce_vm
> +th_l2cache_call=C2=A0 0000000 10101 00000 000 00000 0001011
> +th_l2cache_ciall 0000000 10111 00000 000 00000 0001011
> +th_l2cache_iall=C2=A0 0000000 10110 00000 000 00000 0001011
> --
> 2.38.1
>
>
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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id j26-20020a5d453a000000b002bdf3809f59sm2607005wra.38.2023.01.24.11.59.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 11:59:49 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v3 00/14] Add support for the T-Head vendor extensions Date: Tue, 24 Jan 2023 20:59:31 +0100 Message-Id: <20230124195945.181842-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 19:59:55 -0000 From: Christoph Müllner This series introduces support for the T-Head vendor extensions, which are implemented e.g. in the XuanTie C906 and XuanTie C910: * XTheadBa * XTheadBb * XTheadBs * XTheadCmo * XTheadCondMov * XTheadFMemIdx * XTheadFmv * XTheadMac * XTheadMemIdx * XTheadMemPair * XTheadSync The xthead* extensions are documented here: https://github.com/T-head-Semi/thead-extension-spec/releases/latest The "th." instruction prefix prevents future conflicts with standard extensions and has been documentented in the RISC-V toolchain conventions: https://github.com/riscv-non-isa/riscv-toolchain-conventions Note, that the T-Head vendor extensions do not contain all vendor-specific functionality of the T-Head SoCs (e.g. no vendor-specific CSRs are included). Instead the extensions cover coherent functionality, that is exposed to S and U mode. To enable the extensions above, the following two methods are possible: * add the extension to the arch string E.g. QEMU_CPU="any,xtheadcmo=true,xtheadsync=true" * implicitly select the extensions via CPU selection E.g. QEMU_CPU="thead-c906" Major changes in v2: - Add ISA_EXT_DATA_ENTRY()s - Use single decoder for XThead extensions - Simplify a lot of translation functions - Fix RV32 behaviour - Added XTheadFmv - Addressed all comments of v1 Major changes in v3: - Drop XMAE patch - Rename priv level test macros Christoph Müllner (14): RISC-V: Adding XTheadCmo ISA extension RISC-V: Adding XTheadSync ISA extension RISC-V: Adding XTheadBa ISA extension RISC-V: Adding XTheadBb ISA extension RISC-V: Adding XTheadBs ISA extension RISC-V: Adding XTheadCondMov ISA extension RISC-V: Adding T-Head multiply-accumulate instructions RISC-V: Adding T-Head MemPair extension RISC-V: Adding T-Head MemIdx extension RISC-V: Adding T-Head FMemIdx extension RISC-V: Set minimum priv version for Zfh to 1.11 RISC-V: Add initial support for T-Head C906 RISC-V: Adding XTheadFmv ISA extension target/riscv: add a MAINTAINERS entry for XThead* extension support MAINTAINERS | 8 + target/riscv/cpu.c | 54 +- target/riscv/cpu.h | 13 + target/riscv/cpu_vendorid.h | 6 + target/riscv/helper.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 1081 ++++++++++++++++++++ target/riscv/meson.build | 1 + target/riscv/op_helper.c | 6 + target/riscv/translate.c | 31 + target/riscv/xthead.decode | 185 ++++ 10 files changed, 1385 insertions(+), 1 deletion(-) create mode 100644 target/riscv/cpu_vendorid.h create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc create mode 100644 target/riscv/xthead.decode -- 2.39.0 From MAILER-DAEMON Tue Jan 24 14:59:58 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKPSY-0006yh-CZ for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 14:59:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKPSW-0006y3-Ey for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 14:59:56 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKPST-0002PC-N2 for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 14:59:56 -0500 Received: by mail-wm1-x334.google.com with SMTP id f12-20020a7bc8cc000000b003daf6b2f9b9so13599205wml.3 for ; Tue, 24 Jan 2023 11:59:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tfcUFJHqkQVFEoe5n9Ls7hJAnJVusqbORm+LT2ix5zI=; b=kz7TVVtGtaG5KqjrwqKss28GR4XxH4fOOQUfJXE/AlO0Iac21I7af7Ju5GkQBczHeu sEqq7ocsIm+Dp0DveoT++D9Jw7R6sjUYXh6HnfJ72r7qIsBW008BXQFT/odIlpT7vbUu EF33XqXEjhELzrRCOB166EjRfUthN1+L/4O5tdexhYAPzFIMtzRGHjQeeIIX0AAibeD+ JQj+JDMG+NXpSFNC9TozCBz0bdQ0S3eaBt5mvMj7Lh02ay1THFifIEPtpRgIU1eIJN6w rrzpA5xwGl2N+sDXCLKTb1g7KLWQjZMI/frAGYY+5OjNFIKia55oSU9o/cvZnKilpl/0 xL2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tfcUFJHqkQVFEoe5n9Ls7hJAnJVusqbORm+LT2ix5zI=; b=EphlaTr7G6d3x84FnY0fFJ7P/uK9xQ9yFlx5LxPSPhCiLZ8kwIRE3x2ikQ7ekwng4+ sEa8dl83SayLhTkmV7gUH5313HqD8MUiI7ASe8kqtbqZy6ooqCiD0FEJQqccm4aIggVr TdxusGrDaD2honzuSLbPi4UY96rXS3XqxLHzZc9pX5NTU0eEnnxZ7M9/TwLsGTOXDPZQ m8UzU2moUmLkhMCsBeOf+PZnDxog7fICSJzxfxRQmwJB1+F0LTytDPZdaRWXg5DoG/QD sBNReBXj1oKPRj1axQdJ/fjWk4DMNS4BBpTIhYmo/vaHvG0xa5TYCNV5yItnaNBW1/Rh wcyg== X-Gm-Message-State: AFqh2kphOxEB4OguKk3CuEMeJQPHaiypz2hEjeWFR/y8FJs3H0vJYM23 L22H+/pvtfiZR3dgXseo4iW4sZnBmM8BPM4I X-Google-Smtp-Source: AMrXdXs03UqiusUJDJb+kGEPlZ5PjzLjgLPbkJg+cl9YMGPdzY8tnOLB9n4CVIMQbMoXU/TKqREpMw== X-Received: by 2002:a05:600c:468f:b0:3dc:c5c:b94f with SMTP id p15-20020a05600c468f00b003dc0c5cb94fmr4627708wmo.39.1674590391834; Tue, 24 Jan 2023 11:59:51 -0800 (PST) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id j26-20020a5d453a000000b002bdf3809f59sm2607005wra.38.2023.01.24.11.59.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 11:59:51 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v3 01/14] RISC-V: Adding XTheadCmo ISA extension Date: Tue, 24 Jan 2023 20:59:32 +0100 Message-Id: <20230124195945.181842-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230124195945.181842-1-christoph.muellner@vrull.eu> References: <20230124195945.181842-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=christoph.muellner@vrull.eu; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 19:59:56 -0000 From: Christoph Müllner This patch adds support for the XTheadCmo ISA extension. To avoid interfering with standard extensions, decoder and translation are in its own xthead* specific files. Future patches should be able to easily add additional T-Head extension. The implementation does not have much functionality (besides accepting the instructions and not qualifying them as illegal instructions if the hart executes in the required privilege level for the instruction), as QEMU does not model CPU caches and instructions are documented to not raise any exceptions. Co-developed-by: LIU Zhiwei Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Explicit test for PRV_U - Encapsule access to env-priv in inline function - Use single decoder for XThead extensions Changes in v3: - Appling mask TB_FLAGS_PRIV_MMU_MASK to use of ctx->mem_idx - Removing code from test macro REQUIRE_PRIV_MSU() - Removing PRV_H from test macro REQUIRE_PRIV_MS() - Remove unrelated clean-up - Reorder decoder includes target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 81 ++++++++++++++++++++++ target/riscv/meson.build | 1 + target/riscv/translate.c | 8 +++ target/riscv/xthead.decode | 38 ++++++++++ 6 files changed, 131 insertions(+) create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc create mode 100644 target/riscv/xthead.decode diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cc75ca7667..43a3b9218f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -109,6 +109,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), }; @@ -1071,6 +1072,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), /* Vendor-specific custom extensions */ + DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), /* These are experimental so mark with 'x-' */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f5609b62a2..680dd3dfbd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -473,6 +473,7 @@ struct RISCVCPUConfig { uint64_t mimpid; /* Vendor-specific custom extensions */ + bool ext_xtheadcmo; bool ext_XVentanaCondOps; uint8_t pmu_num; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc new file mode 100644 index 0000000000..24acaf188c --- /dev/null +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -0,0 +1,81 @@ +/* + * RISC-V translation routines for the T-Head vendor extensions (xthead*). + * + * Copyright (c) 2022 VRULL GmbH. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#define REQUIRE_XTHEADCMO(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadcmo) { \ + return false; \ + } \ +} while (0) + +/* XTheadCmo */ + +static inline int priv_level(DisasContext *ctx) +{ +#ifdef CONFIG_USER_ONLY + return PRV_U; +#else + /* Priv level is part of mem_idx. */ + return ctx->mem_idx & TB_FLAGS_PRIV_MMU_MASK; +#endif +} + +/* Test if priv level is M, S, or U (cannot fail). */ +#define REQUIRE_PRIV_MSU(ctx) + +/* Test if priv level is M or S. */ +#define REQUIRE_PRIV_MS(ctx) \ +do { \ + int priv = priv_level(ctx); \ + if (!(priv == PRV_M || \ + priv == PRV_S)) { \ + return false; \ + } \ +} while (0) + +#define NOP_PRIVCHECK(insn, extcheck, privcheck) \ +static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn * a) \ +{ \ + (void) a; \ + extcheck(ctx); \ + privcheck(ctx); \ + return true; \ +} + +NOP_PRIVCHECK(th_dcache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cpa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU) +NOP_PRIVCHECK(th_dcache_civa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU) +NOP_PRIVCHECK(th_dcache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU) +NOP_PRIVCHECK(th_dcache_csw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cisw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_isw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cpal1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cval1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) + +NOP_PRIVCHECK(th_icache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_icache_ialls, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_icache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU) + +NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) diff --git a/target/riscv/meson.build b/target/riscv/meson.build index ba25164d74..5dee37a242 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -2,6 +2,7 @@ gen = [ decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']), decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'), + decodetree.process('xthead.decode', extra_args: '--static-decode=decode_xthead'), decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'), ] diff --git a/target/riscv/translate.c b/target/riscv/translate.c index df38db7553..37763e0502 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -128,6 +128,11 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) return true; } +static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) +{ + return ctx->cfg_ptr->ext_xtheadcmo; +} + #define MATERIALISE_EXT_PREDICATE(ext) \ static bool has_ ## ext ## _p(DisasContext *ctx) \ { \ @@ -762,6 +767,7 @@ static int ex_rvc_shiftri(DisasContext *ctx, int imm) /* Include the auto-generated decoder for 32 bit insn */ #include "decode-insn32.c.inc" +#include "decode-xthead.c.inc" static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, void (*func)(TCGv, TCGv, target_long)) @@ -1065,6 +1071,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_rvk.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" +#include "insn_trans/trans_xthead.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" /* Include the auto-generated decoder for 16 bit insn */ @@ -1091,6 +1098,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) bool (*decode_func)(DisasContext *, uint32_t); } decoders[] = { { always_true_p, decode_insn32 }, + { has_xthead_p, decode_xthead }, { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, }; diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode new file mode 100644 index 0000000000..30533a66f5 --- /dev/null +++ b/target/riscv/xthead.decode @@ -0,0 +1,38 @@ +# +# Translation routines for the instructions of the XThead* ISA extensions +# +# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# The documentation of the ISA extensions can be found here: +# https://github.com/T-head-Semi/thead-extension-spec/releases/latest + +# Fields: +%rs1 15:5 + +# Formats +@sfence_vm ....... ..... ..... ... ..... ....... %rs1 + +# XTheadCmo +th_dcache_call 0000000 00001 00000 000 00000 0001011 +th_dcache_ciall 0000000 00011 00000 000 00000 0001011 +th_dcache_iall 0000000 00010 00000 000 00000 0001011 +th_dcache_cpa 0000001 01001 ..... 000 00000 0001011 @sfence_vm +th_dcache_cipa 0000001 01011 ..... 000 00000 0001011 @sfence_vm +th_dcache_ipa 0000001 01010 ..... 000 00000 0001011 @sfence_vm +th_dcache_cva 0000001 00101 ..... 000 00000 0001011 @sfence_vm +th_dcache_civa 0000001 00111 ..... 000 00000 0001011 @sfence_vm +th_dcache_iva 0000001 00110 ..... 000 00000 0001011 @sfence_vm +th_dcache_csw 0000001 00001 ..... 000 00000 0001011 @sfence_vm +th_dcache_cisw 0000001 00011 ..... 000 00000 0001011 @sfence_vm +th_dcache_isw 0000001 00010 ..... 000 00000 0001011 @sfence_vm +th_dcache_cpal1 0000001 01000 ..... 000 00000 0001011 @sfence_vm +th_dcache_cval1 0000001 00100 ..... 000 00000 0001011 @sfence_vm +th_icache_iall 0000000 10000 00000 000 00000 0001011 +th_icache_ialls 0000000 10001 00000 000 00000 0001011 +th_icache_ipa 0000001 11000 ..... 000 00000 0001011 @sfence_vm +th_icache_iva 0000001 10000 ..... 000 00000 0001011 @sfence_vm +th_l2cache_call 0000000 10101 00000 000 00000 0001011 +th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 +th_l2cache_iall 0000000 10110 00000 000 00000 0001011 -- 2.39.0 From MAILER-DAEMON Tue Jan 24 14:59:58 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKPSY-0006yv-H3 for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id j26-20020a5d453a000000b002bdf3809f59sm2607005wra.38.2023.01.24.11.59.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 11:59:52 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v3 02/14] RISC-V: Adding XTheadSync ISA extension Date: Tue, 24 Jan 2023 20:59:33 +0100 Message-Id: <20230124195945.181842-3-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230124195945.181842-1-christoph.muellner@vrull.eu> References: <20230124195945.181842-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 19:59:57 -0000 From: Christoph Müllner This patch adds support for the XTheadSync ISA extension. The patch uses the T-Head specific decoder and translation. The implementation introduces a helper to execute synchronization tasks: helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use helper to synchronize CPUs and perform TLB flushes - Change implemenation to follow latest spec update - Use single decoder for XThead extensions Changes in v3: - Adjust for renamed REQUIRE_PRIV_* test macros target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/helper.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 86 ++++++++++++++++++++++ target/riscv/op_helper.c | 6 ++ target/riscv/translate.c | 2 +- target/riscv/xthead.decode | 9 +++ 7 files changed, 106 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 43a3b9218f..ae2009e89c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -110,6 +110,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), + ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), }; @@ -1073,6 +1074,7 @@ static Property riscv_cpu_extensions[] = { /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), + DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), /* These are experimental so mark with 'x-' */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 680dd3dfbd..d0ab5c7bb0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -474,6 +474,7 @@ struct RISCVCPUConfig { /* Vendor-specific custom extensions */ bool ext_xtheadcmo; + bool ext_xtheadsync; bool ext_XVentanaCondOps; uint8_t pmu_num; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 227c7122ef..d22656698a 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -109,6 +109,7 @@ DEF_HELPER_1(sret, tl, env) DEF_HELPER_1(mret, tl, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(tlb_flush, void, env) +DEF_HELPER_1(tlb_flush_all, void, env) /* Native Debug */ DEF_HELPER_1(itrigger_match, void, env) #endif diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index 24acaf188c..bf5b39c749 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -22,6 +22,12 @@ } \ } while (0) +#define REQUIRE_XTHEADSYNC(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadsync) { \ + return false; \ + } \ +} while (0) + /* XTheadCmo */ static inline int priv_level(DisasContext *ctx) @@ -79,3 +85,83 @@ NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU) NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) + +/* XTheadSync */ + +static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a) +{ + (void) a; + REQUIRE_XTHEADSYNC(ctx); + +#ifndef CONFIG_USER_ONLY + REQUIRE_PRIV_MS(ctx); + decode_save_opc(ctx); + gen_helper_tlb_flush_all(cpu_env); + return true; +#else + return false; +#endif +} + +#ifndef CONFIG_USER_ONLY +static void gen_th_sync_local(DisasContext *ctx) +{ + /* + * Emulate out-of-order barriers with pipeline flush + * by exiting the translation block. + */ + gen_set_pc_imm(ctx, ctx->pc_succ_insn); + tcg_gen_exit_tb(NULL, 0); + ctx->base.is_jmp = DISAS_NORETURN; +} +#endif + +static bool trans_th_sync(DisasContext *ctx, arg_th_sync *a) +{ + (void) a; + REQUIRE_XTHEADSYNC(ctx); + +#ifndef CONFIG_USER_ONLY + REQUIRE_PRIV_MSU(ctx); + + /* + * th.sync is an out-of-order barrier. + */ + gen_th_sync_local(ctx); + + return true; +#else + return false; +#endif +} + +static bool trans_th_sync_i(DisasContext *ctx, arg_th_sync_i *a) +{ + (void) a; + REQUIRE_XTHEADSYNC(ctx); + +#ifndef CONFIG_USER_ONLY + REQUIRE_PRIV_MSU(ctx); + + /* + * th.sync.i is th.sync plus pipeline flush. + */ + gen_th_sync_local(ctx); + + return true; +#else + return false; +#endif +} + +static bool trans_th_sync_is(DisasContext *ctx, arg_th_sync_is *a) +{ + /* This instruction has the same behaviour like th.sync.i. */ + return trans_th_sync_i(ctx, a); +} + +static bool trans_th_sync_s(DisasContext *ctx, arg_th_sync_s *a) +{ + /* This instruction has the same behaviour like th.sync. */ + return trans_th_sync(ctx, a); +} diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 878bcb03b8..48f918b71b 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -258,6 +258,12 @@ void helper_tlb_flush(CPURISCVState *env) } } +void helper_tlb_flush_all(CPURISCVState *env) +{ + CPUState *cs = env_cpu(env); + tlb_flush_all_cpus_synced(cs); +} + void helper_hyp_tlb_flush(CPURISCVState *env) { CPUState *cs = env_cpu(env); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 37763e0502..dcda7cfd22 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -130,7 +130,7 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { - return ctx->cfg_ptr->ext_xtheadcmo; + return ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 30533a66f5..1d86f3a012 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -10,9 +10,11 @@ # Fields: %rs1 15:5 +%rs2 20:5 # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 +@rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 # XTheadCmo th_dcache_call 0000000 00001 00000 000 00000 0001011 @@ -36,3 +38,10 @@ th_icache_iva 0000001 10000 ..... 000 00000 0001011 @sfence_vm th_l2cache_call 0000000 10101 00000 000 00000 0001011 th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 th_l2cache_iall 0000000 10110 00000 000 00000 0001011 + +# XTheadSync +th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s +th_sync 0000000 11000 00000 000 00000 0001011 +th_sync_i 0000000 11010 00000 000 00000 0001011 +th_sync_is 0000000 11011 00000 000 00000 0001011 +th_sync_s 0000000 11001 00000 000 00000 0001011 -- 2.39.0 From MAILER-DAEMON Tue Jan 24 14:59:59 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKPSZ-00070E-SF for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id j26-20020a5d453a000000b002bdf3809f59sm2607005wra.38.2023.01.24.11.59.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 11:59:54 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v3 03/14] RISC-V: Adding XTheadBa ISA extension Date: Tue, 24 Jan 2023 20:59:34 +0100 Message-Id: <20230124195945.181842-4-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230124195945.181842-1-christoph.muellner@vrull.eu> References: <20230124195945.181842-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=christoph.muellner@vrull.eu; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 19:59:58 -0000 From: Christoph Müllner This patch adds support for the XTheadBa ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Split XtheadB* extension into individual commits - Use single decoder for XThead extensions target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 39 ++++++++++++++++++++++ target/riscv/translate.c | 3 +- target/riscv/xthead.decode | 22 ++++++++++++ 5 files changed, 66 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ae2009e89c..4b46130c5b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -109,6 +109,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), @@ -1073,6 +1074,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), /* Vendor-specific custom extensions */ + DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d0ab5c7bb0..d3191bf27b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -473,6 +473,7 @@ struct RISCVCPUConfig { uint64_t mimpid; /* Vendor-specific custom extensions */ + bool ext_xtheadba; bool ext_xtheadcmo; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index bf5b39c749..a7da156869 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -16,6 +16,12 @@ * this program. If not, see . */ +#define REQUIRE_XTHEADBA(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadba) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADCMO(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadcmo) { \ return false; \ @@ -28,6 +34,39 @@ } \ } while (0) +/* XTheadBa */ + +/* + * th.addsl is similar to sh[123]add (from Zba), but not an + * alternative encoding: while sh[123] applies the shift to rs1, + * th.addsl shifts rs2. + */ + +#define GEN_TH_ADDSL(SHAMT) \ +static void gen_th_addsl##SHAMT(TCGv ret, TCGv arg1, TCGv arg2) \ +{ \ + TCGv t = tcg_temp_new(); \ + tcg_gen_shli_tl(t, arg2, SHAMT); \ + tcg_gen_add_tl(ret, t, arg1); \ + tcg_temp_free(t); \ +} + +GEN_TH_ADDSL(1) +GEN_TH_ADDSL(2) +GEN_TH_ADDSL(3) + +#define GEN_TRANS_TH_ADDSL(SHAMT) \ +static bool trans_th_addsl##SHAMT(DisasContext *ctx, \ + arg_th_addsl##SHAMT * a) \ +{ \ + REQUIRE_XTHEADBA(ctx); \ + return gen_arith(ctx, a, EXT_NONE, gen_th_addsl##SHAMT, NULL); \ +} + +GEN_TRANS_TH_ADDSL(1) +GEN_TRANS_TH_ADDSL(2) +GEN_TRANS_TH_ADDSL(3) + /* XTheadCmo */ static inline int priv_level(DisasContext *ctx) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index dcda7cfd22..68baf84807 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -130,7 +130,8 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { - return ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; + return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadcmo || + ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 1d86f3a012..b149f13018 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -2,6 +2,7 @@ # Translation routines for the instructions of the XThead* ISA extensions # # Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu +# Dr. Philipp Tomsich, philipp.tomsich@vrull.eu # # SPDX-License-Identifier: LGPL-2.1-or-later # @@ -9,12 +10,33 @@ # https://github.com/T-head-Semi/thead-extension-spec/releases/latest # Fields: +%rd 7:5 %rs1 15:5 %rs2 20:5 +# Argument sets +&r rd rs1 rs2 !extern + # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 +@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd + +# XTheadBa +# Instead of defining a new encoding, we simply use the decoder to +# extract the imm[0:1] field and dispatch to separate translation +# functions (mirroring the `sh[123]add` instructions from Zba and +# the regular RVI `add` instruction. +# +# The only difference between sh[123]add and addsl is that the shift +# is applied to rs1 (for addsl) instead of rs2 (for sh[123]add). +# +# Note that shift-by-0 is a valid operation according to the manual. +# This will be equivalent to a regular add. +add 0000000 ..... ..... 001 ..... 0001011 @r +th_addsl1 0000001 ..... ..... 001 ..... 0001011 @r +th_addsl2 0000010 ..... ..... 001 ..... 0001011 @r +th_addsl3 0000011 ..... ..... 001 ..... 0001011 @r # XTheadCmo th_dcache_call 0000000 00001 00000 000 00000 0001011 -- 2.39.0 From MAILER-DAEMON Tue Jan 24 15:00:04 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKPSd-00072M-Ti for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id j26-20020a5d453a000000b002bdf3809f59sm2607005wra.38.2023.01.24.11.59.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 11:59:55 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v3 04/14] RISC-V: Adding XTheadBb ISA extension Date: Tue, 24 Jan 2023 20:59:35 +0100 Message-Id: <20230124195945.181842-5-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230124195945.181842-1-christoph.muellner@vrull.eu> References: <20230124195945.181842-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 20:00:00 -0000 From: Christoph Müllner This patch adds support for the XTheadBb ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Split XtheadB* extension into individual commits - Make implementation compatible with RV32. - Use single decoder for XThead extensions target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 124 +++++++++++++++++++++ target/riscv/translate.c | 4 +- target/riscv/xthead.decode | 20 ++++ 5 files changed, 149 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4b46130c5b..b995470dd6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -110,6 +110,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), + ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), @@ -1075,6 +1076,7 @@ static Property riscv_cpu_extensions[] = { /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), + DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d3191bf27b..ff92705010 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -474,6 +474,7 @@ struct RISCVCPUConfig { /* Vendor-specific custom extensions */ bool ext_xtheadba; + bool ext_xtheadbb; bool ext_xtheadcmo; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index a7da156869..ea6cd6e305 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -22,6 +22,12 @@ } \ } while (0) +#define REQUIRE_XTHEADBB(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadbb) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADCMO(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadcmo) { \ return false; \ @@ -67,6 +73,124 @@ GEN_TRANS_TH_ADDSL(1) GEN_TRANS_TH_ADDSL(2) GEN_TRANS_TH_ADDSL(3) +/* XTheadBb */ + +/* th.srri is an alternate encoding for rori (from Zbb) */ +static bool trans_th_srri(DisasContext *ctx, arg_th_srri * a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE, + tcg_gen_rotri_tl, gen_roriw, NULL); +} + +/* th.srriw is an alternate encoding for roriw (from Zbb) */ +static bool trans_th_srriw(DisasContext *ctx, arg_th_srriw *a) +{ + REQUIRE_XTHEADBB(ctx); + REQUIRE_64BIT(ctx); + ctx->ol = MXL_RV32; + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL); +} + +/* th.ext and th.extu perform signed/unsigned bitfield extraction */ +static bool gen_th_bfextract(DisasContext *ctx, arg_th_bfext *a, + void (*f)(TCGv, TCGv, unsigned int, unsigned int)) +{ + TCGv dest = dest_gpr(ctx, a->rd); + TCGv source = get_gpr(ctx, a->rs1, EXT_ZERO); + + if (a->lsb <= a->msb) { + f(dest, source, a->lsb, a->msb - a->lsb + 1); + gen_set_gpr(ctx, a->rd, dest); + } + return true; +} + +static bool trans_th_ext(DisasContext *ctx, arg_th_ext *a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_th_bfextract(ctx, a, tcg_gen_sextract_tl); +} + +static bool trans_th_extu(DisasContext *ctx, arg_th_extu *a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_th_bfextract(ctx, a, tcg_gen_extract_tl); +} + +/* th.ff0: find first zero (clz on an inverted input) */ +static bool gen_th_ff0(DisasContext *ctx, arg_th_ff0 *a, DisasExtend ext) +{ + TCGv dest = dest_gpr(ctx, a->rd); + TCGv src1 = get_gpr(ctx, a->rs1, ext); + + int olen = get_olen(ctx); + TCGv t = tcg_temp_new(); + + tcg_gen_not_tl(t, src1); + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + gen_clzw(dest, t); + } else { + g_assert_not_reached(); + } + } else { + gen_clz(dest, t); + } + + tcg_temp_free(t); + gen_set_gpr(ctx, a->rd, dest); + + return true; +} + +static bool trans_th_ff0(DisasContext *ctx, arg_th_ff0 *a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_th_ff0(ctx, a, EXT_NONE); +} + +/* th.ff1 is an alternate encoding for clz (from Zbb) */ +static bool trans_th_ff1(DisasContext *ctx, arg_th_ff1 *a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw); +} + +static void gen_th_revw(TCGv ret, TCGv arg1) +{ + tcg_gen_bswap32_tl(ret, arg1, TCG_BSWAP_OS); +} + +/* th.rev is an alternate encoding for the RV64 rev8 (from Zbb) */ +static bool trans_th_rev(DisasContext *ctx, arg_th_rev *a) +{ + REQUIRE_XTHEADBB(ctx); + + return gen_unary_per_ol(ctx, a, EXT_NONE, tcg_gen_bswap_tl, gen_th_revw); +} + +/* th.revw is a sign-extended byte-swap of the lower word */ +static bool trans_th_revw(DisasContext *ctx, arg_th_revw *a) +{ + REQUIRE_XTHEADBB(ctx); + REQUIRE_64BIT(ctx); + return gen_unary(ctx, a, EXT_NONE, gen_th_revw); +} + +/* th.tstnbz is equivalent to an orc.b (from Zbb) with inverted result */ +static void gen_th_tstnbz(TCGv ret, TCGv source1) +{ + gen_orc_b(ret, source1); + tcg_gen_not_tl(ret, ret); +} + +static bool trans_th_tstnbz(DisasContext *ctx, arg_th_tstnbz *a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_unary(ctx, a, EXT_ZERO, gen_th_tstnbz); +} + /* XTheadCmo */ static inline int priv_level(DisasContext *ctx) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 68baf84807..3bae961be0 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -130,8 +130,8 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { - return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadcmo || - ctx->cfg_ptr->ext_xtheadsync; + return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || + ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index b149f13018..8cd140891b 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -13,14 +13,23 @@ %rd 7:5 %rs1 15:5 %rs2 20:5 +%sh5 20:5 +%sh6 20:6 # Argument sets &r rd rs1 rs2 !extern +&r2 rd rs1 !extern +&shift shamt rs1 rd !extern +&th_bfext msb lsb rs1 rd # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd +@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd +@th_bfext msb:6 lsb:6 ..... ... ..... ....... &th_bfext %rs1 %rd +@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd +@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd # XTheadBa # Instead of defining a new encoding, we simply use the decoder to @@ -38,6 +47,17 @@ th_addsl1 0000001 ..... ..... 001 ..... 0001011 @r th_addsl2 0000010 ..... ..... 001 ..... 0001011 @r th_addsl3 0000011 ..... ..... 001 ..... 0001011 @r +# XTheadBb +th_ext ...... ...... ..... 010 ..... 0001011 @th_bfext +th_extu ...... ...... ..... 011 ..... 0001011 @th_bfext +th_ff0 1000010 00000 ..... 001 ..... 0001011 @r2 +th_ff1 1000011 00000 ..... 001 ..... 0001011 @r2 +th_srri 000100 ...... ..... 001 ..... 0001011 @sh6 +th_srriw 0001010 ..... ..... 001 ..... 0001011 @sh5 +th_rev 1000001 00000 ..... 001 ..... 0001011 @r2 +th_revw 1001000 00000 ..... 001 ..... 0001011 @r2 +th_tstnbz 1000000 00000 ..... 001 ..... 0001011 @r2 + # XTheadCmo th_dcache_call 0000000 00001 00000 000 00000 0001011 th_dcache_ciall 0000000 00011 00000 000 00000 0001011 -- 2.39.0 From MAILER-DAEMON Tue Jan 24 15:00:05 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKPSe-00072m-Pl for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id j26-20020a5d453a000000b002bdf3809f59sm2607005wra.38.2023.01.24.11.59.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 11:59:57 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v3 05/14] RISC-V: Adding XTheadBs ISA extension Date: Tue, 24 Jan 2023 20:59:36 +0100 Message-Id: <20230124195945.181842-6-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230124195945.181842-1-christoph.muellner@vrull.eu> References: <20230124195945.181842-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 20:00:01 -0000 From: Christoph Müllner This patch adds support for the XTheadBs ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Split XtheadB* extension into individual commits - Use single decoder for XThead extensions target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 15 +++++++++++++++ target/riscv/translate.c | 3 ++- target/riscv/xthead.decode | 3 +++ 5 files changed, 23 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b995470dd6..805fec4d76 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -111,6 +111,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), + ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), @@ -1077,6 +1078,7 @@ static Property riscv_cpu_extensions[] = { /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), + DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ff92705010..2f92211d9f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -475,6 +475,7 @@ struct RISCVCPUConfig { /* Vendor-specific custom extensions */ bool ext_xtheadba; bool ext_xtheadbb; + bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index ea6cd6e305..339a54e3d6 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -28,6 +28,12 @@ } \ } while (0) +#define REQUIRE_XTHEADBS(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadbs) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADCMO(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadcmo) { \ return false; \ @@ -191,6 +197,15 @@ static bool trans_th_tstnbz(DisasContext *ctx, arg_th_tstnbz *a) return gen_unary(ctx, a, EXT_ZERO, gen_th_tstnbz); } +/* XTheadBs */ + +/* th.tst is an alternate encoding for bexti (from Zbs) */ +static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a) +{ + REQUIRE_XTHEADBS(ctx); + return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext); +} + /* XTheadCmo */ static inline int priv_level(DisasContext *ctx) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3bae961be0..96bdf5fb73 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -131,7 +131,8 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || - ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || + ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 8cd140891b..8494805611 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -58,6 +58,9 @@ th_rev 1000001 00000 ..... 001 ..... 0001011 @r2 th_revw 1001000 00000 ..... 001 ..... 0001011 @r2 th_tstnbz 1000000 00000 ..... 001 ..... 0001011 @r2 +# XTheadBs +th_tst 100010 ...... ..... 001 ..... 0001011 @sh6 + # XTheadCmo th_dcache_call 0000000 00001 00000 000 00000 0001011 th_dcache_ciall 0000000 00011 00000 000 00000 0001011 -- 2.39.0 From MAILER-DAEMON Tue Jan 24 15:00:06 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKPSf-00073a-Jg for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 15:00:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKPSc-000723-MV for qemu-riscv@nongnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id j26-20020a5d453a000000b002bdf3809f59sm2607005wra.38.2023.01.24.11.59.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 11:59:58 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v3 06/14] RISC-V: Adding XTheadCondMov ISA extension Date: Tue, 24 Jan 2023 20:59:37 +0100 Message-Id: <20230124195945.181842-7-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230124195945.181842-1-christoph.muellner@vrull.eu> References: <20230124195945.181842-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 20:00:03 -0000 From: Christoph Müllner This patch adds support for the XTheadCondMov ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Fix invalid use of register from dest_gpr() - Use single decoder for XThead extensions target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 35 ++++++++++++++++++++++ target/riscv/translate.c | 2 +- target/riscv/xthead.decode | 4 +++ 5 files changed, 43 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 805fec4d76..b3ede7223a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -113,6 +113,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), + ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), }; @@ -1080,6 +1081,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), + DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2f92211d9f..5286bd487c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -477,6 +477,7 @@ struct RISCVCPUConfig { bool ext_xtheadbb; bool ext_xtheadbs; bool ext_xtheadcmo; + bool ext_xtheadcondmov; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index 339a54e3d6..894b95a741 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -40,6 +40,12 @@ } \ } while (0) +#define REQUIRE_XTHEADCONDMOV(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadcondmov) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADSYNC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadsync) { \ return false; \ @@ -264,6 +270,35 @@ NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +/* XTheadCondMov */ + +static bool gen_th_condmove(DisasContext *ctx, arg_r *a, TCGCond cond) +{ + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); + TCGv old = get_gpr(ctx, a->rd, EXT_NONE); + TCGv dest = dest_gpr(ctx, a->rd); + + tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, old); + + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +/* th.mveqz: "if (rs2 == 0) rd = rs1;" */ +static bool trans_th_mveqz(DisasContext *ctx, arg_th_mveqz *a) +{ + REQUIRE_XTHEADCONDMOV(ctx); + return gen_th_condmove(ctx, a, TCG_COND_EQ); +} + +/* th.mvnez: "if (rs2 != 0) rd = rs1;" */ +static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a) +{ + REQUIRE_XTHEADCONDMOV(ctx); + return gen_th_condmove(ctx, a, TCG_COND_NE); +} + /* XTheadSync */ static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 96bdf5fb73..d61705e775 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -132,7 +132,7 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || - ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 8494805611..a8ebd8a18b 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -84,6 +84,10 @@ th_l2cache_call 0000000 10101 00000 000 00000 0001011 th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 th_l2cache_iall 0000000 10110 00000 000 00000 0001011 +# XTheadCondMov +th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r +th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r + # XTheadSync th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s th_sync 0000000 11000 00000 000 00000 0001011 -- 2.39.0 From MAILER-DAEMON Tue Jan 24 15:00:09 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKPSi-000757-Vv for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id j26-20020a5d453a000000b002bdf3809f59sm2607005wra.38.2023.01.24.11.59.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 12:00:00 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v3 07/14] RISC-V: Adding T-Head multiply-accumulate instructions Date: Tue, 24 Jan 2023 20:59:38 +0100 Message-Id: <20230124195945.181842-8-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230124195945.181842-1-christoph.muellner@vrull.eu> References: <20230124195945.181842-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 20:00:06 -0000 From: Christoph Müllner This patch adds support for the T-Head MAC instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 83 ++++++++++++++++++++++ target/riscv/translate.c | 3 +- target/riscv/xthead.decode | 8 +++ 5 files changed, 96 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b3ede7223a..2ce8eb6a6f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), + ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), }; @@ -1082,6 +1083,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), + DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5286bd487c..55aea777a0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -478,6 +478,7 @@ struct RISCVCPUConfig { bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadcondmov; + bool ext_xtheadmac; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index 894b95a741..1c583ea8ec 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -46,6 +46,12 @@ } \ } while (0) +#define REQUIRE_XTHEADMAC(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadmac) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADSYNC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadsync) { \ return false; \ @@ -299,6 +305,83 @@ static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a) return gen_th_condmove(ctx, a, TCG_COND_NE); } +/* XTheadMac */ + +static bool gen_th_mac(DisasContext *ctx, arg_r *a, + void (*accumulate_func)(TCGv, TCGv, TCGv), + void (*extend_operand_func)(TCGv, TCGv)) +{ + TCGv dest = dest_gpr(ctx, a->rd); + TCGv src0 = get_gpr(ctx, a->rd, EXT_NONE); + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); + TCGv tmp = tcg_temp_new(); + + if (extend_operand_func) { + TCGv tmp2 = tcg_temp_new(); + extend_operand_func(tmp, src1); + extend_operand_func(tmp2, src2); + tcg_gen_mul_tl(tmp, tmp, tmp2); + tcg_temp_free(tmp2); + } else { + tcg_gen_mul_tl(tmp, src1, src2); + } + + accumulate_func(dest, src0, tmp); + gen_set_gpr(ctx, a->rd, dest); + tcg_temp_free(tmp); + + return true; +} + +/* th.mula: "rd = rd + rs1 * rs2" */ +static bool trans_th_mula(DisasContext *ctx, arg_th_mula *a) +{ + REQUIRE_XTHEADMAC(ctx); + return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL); +} + +/* th.mulah: "rd = sext.w(rd + sext.w(rs1[15:0]) * sext.w(rs2[15:0]))" */ +static bool trans_th_mulah(DisasContext *ctx, arg_th_mulah *a) +{ + REQUIRE_XTHEADMAC(ctx); + ctx->ol = MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_add_tl, tcg_gen_ext16s_tl); +} + +/* th.mulaw: "rd = sext.w(rd + rs1 * rs2)" */ +static bool trans_th_mulaw(DisasContext *ctx, arg_th_mulaw *a) +{ + REQUIRE_XTHEADMAC(ctx); + REQUIRE_64BIT(ctx); + ctx->ol = MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL); +} + +/* th.muls: "rd = rd - rs1 * rs2" */ +static bool trans_th_muls(DisasContext *ctx, arg_th_muls *a) +{ + REQUIRE_XTHEADMAC(ctx); + return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); +} + +/* th.mulsh: "rd = sext.w(rd - sext.w(rs1[15:0]) * sext.w(rs2[15:0]))" */ +static bool trans_th_mulsh(DisasContext *ctx, arg_th_mulsh *a) +{ + REQUIRE_XTHEADMAC(ctx); + ctx->ol = MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_sub_tl, tcg_gen_ext16s_tl); +} + +/* th.mulsw: "rd = sext.w(rd - rs1 * rs2)" */ +static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a) +{ + REQUIRE_XTHEADMAC(ctx); + REQUIRE_64BIT(ctx); + ctx->ol = MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); +} + /* XTheadSync */ static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index d61705e775..5be1c9da69 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -132,7 +132,8 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || - ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac || + ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index a8ebd8a18b..696de6cecf 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -88,6 +88,14 @@ th_l2cache_iall 0000000 10110 00000 000 00000 0001011 th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r +# XTheadMac +th_mula 00100 00 ..... ..... 001 ..... 0001011 @r +th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r +th_mulaw 00100 10 ..... ..... 001 ..... 0001011 @r +th_muls 00100 01 ..... ..... 001 ..... 0001011 @r +th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r +th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r + # XTheadSync th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s th_sync 0000000 11000 00000 000 00000 0001011 -- 2.39.0 From MAILER-DAEMON Tue Jan 24 15:00:15 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKPSn-00077I-7O for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id j26-20020a5d453a000000b002bdf3809f59sm2607005wra.38.2023.01.24.12.00.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 12:00:04 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v3 10/14] RISC-V: Adding T-Head FMemIdx extension Date: Tue, 24 Jan 2023 20:59:41 +0100 Message-Id: <20230124195945.181842-11-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230124195945.181842-1-christoph.muellner@vrull.eu> References: <20230124195945.181842-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 20:00:10 -0000 From: Christoph Müllner This patch adds support for the T-Head FMemIdx instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions - Use get_th_address_indexed for address calculations target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 108 +++++++++++++++++++++ target/riscv/translate.c | 3 +- target/riscv/xthead.decode | 10 ++ 5 files changed, 123 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index eb8bbfa436..6121a5e4ba 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), + ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx), ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), @@ -1085,6 +1086,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), + DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4882b9a9cc..b0ec5fcf9e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -478,6 +478,7 @@ struct RISCVCPUConfig { bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadcondmov; + bool ext_xtheadfmemidx; bool ext_xtheadmac; bool ext_xtheadmemidx; bool ext_xtheadmempair; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index e41f3be9a6..dc82a9fc03 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -46,6 +46,12 @@ } \ } while (0) +#define REQUIRE_XTHEADFMEMIDX(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadfmemidx) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADMAC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadmac) { \ return false; \ @@ -341,6 +347,108 @@ static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a) return gen_th_condmove(ctx, a, TCG_COND_NE); } +/* XTheadFMem */ + +/* + * Load 64-bit float from indexed address. + * If !zext_offs, then address is rs1 + (rs2 << imm2). + * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static bool gen_fload_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop, + bool zext_offs) +{ + TCGv_i64 rd = cpu_fpr[a->rd]; + TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs); + + tcg_gen_qemu_ld_i64(rd, addr, ctx->mem_idx, memop); + if ((memop & MO_SIZE) == MO_32) { + gen_nanbox_s(rd, rd); + } + + mark_fs_dirty(ctx); + return true; +} + +/* + * Store 64-bit float to indexed address. + * If !zext_offs, then address is rs1 + (rs2 << imm2). + * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static bool gen_fstore_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop, + bool zext_offs) +{ + TCGv_i64 rd = cpu_fpr[a->rd]; + TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs); + + tcg_gen_qemu_st_i64(rd, addr, ctx->mem_idx, memop); + + return true; +} + +static bool trans_th_flrd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + return gen_fload_idx(ctx, a, MO_TEUQ, false); +} + +static bool trans_th_flrw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + return gen_fload_idx(ctx, a, MO_TEUL, false); +} + +static bool trans_th_flurd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + return gen_fload_idx(ctx, a, MO_TEUQ, true); +} + +static bool trans_th_flurw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + return gen_fload_idx(ctx, a, MO_TEUL, true); +} + +static bool trans_th_fsrd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + return gen_fstore_idx(ctx, a, MO_TEUQ, false); +} + +static bool trans_th_fsrw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + return gen_fstore_idx(ctx, a, MO_TEUL, false); +} + +static bool trans_th_fsurd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + return gen_fstore_idx(ctx, a, MO_TEUQ, true); +} + +static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + return gen_fstore_idx(ctx, a, MO_TEUL, true); +} + /* XTheadMac */ static bool gen_th_mac(DisasContext *ctx, arg_r *a, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 2461bcda0f..c52bc5e0af 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -132,7 +132,8 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || - ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac || + ctx->cfg_ptr->ext_xtheadcondmov || + ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; } diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 69e40f22dc..81daf1d694 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -100,6 +100,16 @@ th_l2cache_iall 0000000 10110 00000 000 00000 0001011 th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r +# XTheadFMemIdx +th_flrd 01100 .. ..... ..... 110 ..... 0001011 @th_memidx +th_flrw 01000 .. ..... ..... 110 ..... 0001011 @th_memidx +th_flurd 01110 .. ..... ..... 110 ..... 0001011 @th_memidx +th_flurw 01010 .. ..... ..... 110 ..... 0001011 @th_memidx +th_fsrd 01100 .. ..... ..... 111 ..... 0001011 @th_memidx +th_fsrw 01000 .. ..... ..... 111 ..... 0001011 @th_memidx +th_fsurd 01110 .. ..... ..... 111 ..... 0001011 @th_memidx +th_fsurw 01010 .. ..... ..... 111 ..... 0001011 @th_memidx + # XTheadMac th_mula 00100 00 ..... ..... 001 ..... 0001011 @r th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r -- 2.39.0 From MAILER-DAEMON Tue Jan 24 15:00:09 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKPSj-00075B-5b for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id j26-20020a5d453a000000b002bdf3809f59sm2607005wra.38.2023.01.24.12.00.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 12:00:01 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension Date: Tue, 24 Jan 2023 20:59:39 +0100 Message-Id: <20230124195945.181842-9-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230124195945.181842-1-christoph.muellner@vrull.eu> References: <20230124195945.181842-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 20:00:06 -0000 From: Christoph Müllner This patch adds support for the T-Head MemPair instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions - Use get_address() to calculate addresses target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 88 ++++++++++++++++++++++ target/riscv/translate.c | 2 +- target/riscv/xthead.decode | 13 ++++ 5 files changed, 105 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2ce8eb6a6f..e3a10f782c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -115,6 +115,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), + ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), }; @@ -1084,6 +1085,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), + DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 55aea777a0..4f5f3b2c20 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -479,6 +479,7 @@ struct RISCVCPUConfig { bool ext_xtheadcmo; bool ext_xtheadcondmov; bool ext_xtheadmac; + bool ext_xtheadmempair; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index 1c583ea8ec..7ab2a7a48e 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -52,6 +52,12 @@ } \ } while (0) +#define REQUIRE_XTHEADMEMPAIR(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadmempair) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADSYNC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadsync) { \ return false; \ @@ -382,6 +388,88 @@ static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a) return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); } +/* XTheadMemPair */ + +static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop, + int shamt) +{ + TCGv rd1 = dest_gpr(ctx, a->rd1); + TCGv rd2 = dest_gpr(ctx, a->rd2); + TCGv addr1 = tcg_temp_new(); + TCGv addr2 = tcg_temp_new(); + + addr1 = get_address(ctx, a->rs, a->sh2 << shamt); + if ((memop & MO_SIZE) == MO_64) { + addr2 = get_address(ctx, a->rs, 8 + (a->sh2 << shamt)); + } else { + addr2 = get_address(ctx, a->rs, 4 + (a->sh2 << shamt)); + } + + tcg_gen_qemu_ld_tl(rd1, addr1, ctx->mem_idx, memop); + tcg_gen_qemu_ld_tl(rd2, addr2, ctx->mem_idx, memop); + gen_set_gpr(ctx, a->rd1, rd1); + gen_set_gpr(ctx, a->rd2, rd2); + + tcg_temp_free(addr1); + tcg_temp_free(addr2); + return true; +} + +static bool trans_th_ldd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + REQUIRE_64BIT(ctx); + return gen_loadpair_tl(ctx, a, MO_TESQ, 4); +} + +static bool trans_th_lwd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + return gen_loadpair_tl(ctx, a, MO_TESL, 3); +} + +static bool trans_th_lwud(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + return gen_loadpair_tl(ctx, a, MO_TEUL, 3); +} + +static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop, + int shamt) +{ + TCGv data1 = get_gpr(ctx, a->rd1, EXT_NONE); + TCGv data2 = get_gpr(ctx, a->rd2, EXT_NONE); + TCGv addr1 = tcg_temp_new(); + TCGv addr2 = tcg_temp_new(); + + addr1 = get_address(ctx, a->rs, a->sh2 << shamt); + if ((memop & MO_SIZE) == MO_64) { + addr2 = get_address(ctx, a->rs, 8 + (a->sh2 << shamt)); + } else { + addr2 = get_address(ctx, a->rs, 4 + (a->sh2 << shamt)); + } + + tcg_gen_qemu_st_tl(data1, addr1, ctx->mem_idx, memop); + tcg_gen_qemu_st_tl(data2, addr2, ctx->mem_idx, memop); + + tcg_temp_free(addr1); + tcg_temp_free(addr2); + return true; +} + +static bool trans_th_sdd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + REQUIRE_64BIT(ctx); + return gen_storepair_tl(ctx, a, MO_TESQ, 4); +} + +static bool trans_th_swd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + return gen_storepair_tl(ctx, a, MO_TESL, 3); +} + /* XTheadSync */ static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5be1c9da69..27bab07994 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -133,7 +133,7 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac || - ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 696de6cecf..ff2a83b56d 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -11,16 +11,21 @@ # Fields: %rd 7:5 +%rd1 7:5 +%rs 15:5 %rs1 15:5 +%rd2 20:5 %rs2 20:5 %sh5 20:5 %sh6 20:6 +%sh2 25:2 # Argument sets &r rd rs1 rs2 !extern &r2 rd rs1 !extern &shift shamt rs1 rd !extern &th_bfext msb lsb rs1 rd +&th_pair rd1 rs rd2 sh2 # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @@ -30,6 +35,7 @@ @th_bfext msb:6 lsb:6 ..... ... ..... ....... &th_bfext %rs1 %rd @sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd @sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd +@th_pair ..... .. ..... ..... ... ..... ....... &th_pair %rd1 %rs %rd2 %sh2 # XTheadBa # Instead of defining a new encoding, we simply use the decoder to @@ -96,6 +102,13 @@ th_muls 00100 01 ..... ..... 001 ..... 0001011 @r th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r +# XTheadMemPair +th_ldd 11111 .. ..... ..... 100 ..... 0001011 @th_pair +th_lwd 11100 .. ..... ..... 100 ..... 0001011 @th_pair +th_lwud 11110 .. ..... ..... 100 ..... 0001011 @th_pair +th_sdd 11111 .. ..... ..... 101 ..... 0001011 @th_pair +th_swd 11100 .. ..... ..... 101 ..... 0001011 @th_pair + # XTheadSync th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s th_sync 0000000 11000 00000 000 00000 0001011 -- 2.39.0 From MAILER-DAEMON Tue Jan 24 15:00:23 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKPSu-00078b-51 for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id j26-20020a5d453a000000b002bdf3809f59sm2607005wra.38.2023.01.24.12.00.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 12:00:02 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v3 09/14] RISC-V: Adding T-Head MemIdx extension Date: Tue, 24 Jan 2023 20:59:40 +0100 Message-Id: <20230124195945.181842-10-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230124195945.181842-1-christoph.muellner@vrull.eu> References: <20230124195945.181842-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 20:00:08 -0000 From: Christoph Müllner This patch adds support for the T-Head MemIdx instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions - Avoid signed-bitfield-extraction by using signed immediate field imm5 - Use get_address() to calculate addresses - Introduce helper get_th_address_indexed for rs1+(rs2<cfg_ptr->ext_xtheadmemidx) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADMEMPAIR(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadmempair) { \ return false; \ @@ -64,6 +70,30 @@ } \ } while (0) +/* + * Calculate and return the address for indexed mem operations: + * If !zext_offs, then the address is rs1 + (rs2 << imm2). + * If zext_offs, then the address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static TCGv get_th_address_indexed(DisasContext *ctx, int rs1, int rs2, + int imm2, bool zext_offs) +{ + TCGv src2 = get_gpr(ctx, rs2, EXT_NONE); + TCGv offs = tcg_temp_new(); + + if (zext_offs) { + tcg_gen_extract_tl(offs, src2, 0, 32); + tcg_gen_shli_tl(offs, offs, imm2); + } else { + tcg_gen_shli_tl(offs, src2, imm2); + } + + TCGv addr = get_address_indexed(ctx, rs1, offs); + + tcg_temp_free(offs); + return addr; +} + /* XTheadBa */ /* @@ -388,6 +418,353 @@ static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a) return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); } +/* XTheadMemIdx */ + +/* + * Load with memop from indexed address and add (imm5 << imm2) to rs1. + * If !preinc, then the load address is rs1. + * If preinc, then the load address is rs1 + (imm5) << imm2). + */ +static bool gen_load_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop, + bool preinc) +{ + TCGv rd = dest_gpr(ctx, a->rd); + TCGv addr = get_address(ctx, a->rs1, preinc ? a->imm5 << a->imm2 : 0); + + tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); + addr = get_address(ctx, a->rs1, !preinc ? a->imm5 << a->imm2 : 0); + gen_set_gpr(ctx, a->rd, rd); + gen_set_gpr(ctx, a->rs1, addr); + + return true; +} + +/* + * Store with memop to indexed address and add (imm5 << imm2) to rs1. + * If !preinc, then the store address is rs1. + * If preinc, then the store address is rs1 + (imm5) << imm2). + */ +static bool gen_store_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop, + bool preinc) +{ + TCGv data = get_gpr(ctx, a->rd, EXT_NONE); + TCGv addr = get_address(ctx, a->rs1, preinc ? a->imm5 << a->imm2 : 0); + + tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); + addr = get_address(ctx, a->rs1, !preinc ? a->imm5 << a->imm2 : 0); + gen_set_gpr(ctx, a->rs1, addr); + + return true; +} + +static bool trans_th_ldia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_inc(ctx, a, MO_TESQ, false); +} + +static bool trans_th_ldib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_inc(ctx, a, MO_TESQ, true); +} + +static bool trans_th_lwia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TESL, false); +} + +static bool trans_th_lwib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TESL, true); +} + +static bool trans_th_lwuia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_inc(ctx, a, MO_TEUL, false); +} + +static bool trans_th_lwuib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_inc(ctx, a, MO_TEUL, true); +} + +static bool trans_th_lhia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TESW, false); +} + +static bool trans_th_lhib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TESW, true); +} + +static bool trans_th_lhuia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TEUW, false); +} + +static bool trans_th_lhuib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TEUW, true); +} + +static bool trans_th_lbia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_SB, false); +} + +static bool trans_th_lbib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_SB, true); +} + +static bool trans_th_lbuia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_UB, false); +} + +static bool trans_th_lbuib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_UB, true); +} + +static bool trans_th_sdia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_store_inc(ctx, a, MO_TESQ, false); +} + +static bool trans_th_sdib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_store_inc(ctx, a, MO_TESQ, true); +} + +static bool trans_th_swia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_TESL, false); +} + +static bool trans_th_swib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_TESL, true); +} + +static bool trans_th_shia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_TESW, false); +} + +static bool trans_th_shib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_TESW, true); +} + +static bool trans_th_sbia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_SB, false); +} + +static bool trans_th_sbib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_SB, true); +} + +/* + * Load with memop from indexed address. + * If !zext_offs, then address is rs1 + (rs2 << imm2). + * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static bool gen_load_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop, + bool zext_offs) +{ + TCGv rd = dest_gpr(ctx, a->rd); + TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs); + + tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); + gen_set_gpr(ctx, a->rd, rd); + + return true; +} + +/* + * Store with memop to indexed address. + * If !zext_offs, then address is rs1 + (rs2 << imm2). + * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static bool gen_store_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop, + bool zext_offs) +{ + TCGv data = get_gpr(ctx, a->rd, EXT_NONE); + TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs); + + tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); + + return true; +} + +static bool trans_th_lrd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_idx(ctx, a, MO_TESQ, false); +} + +static bool trans_th_lrw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TESL, false); +} + +static bool trans_th_lrwu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_idx(ctx, a, MO_TEUL, false); +} + +static bool trans_th_lrh(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TESW, false); +} + +static bool trans_th_lrhu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TEUW, false); +} + +static bool trans_th_lrb(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_SB, false); +} + +static bool trans_th_lrbu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_UB, false); +} + +static bool trans_th_srd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_store_idx(ctx, a, MO_TESQ, false); +} + +static bool trans_th_srw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_TESL, false); +} + +static bool trans_th_srh(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_TESW, false); +} + +static bool trans_th_srb(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_SB, false); +} +static bool trans_th_lurd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_idx(ctx, a, MO_TESQ, true); +} + +static bool trans_th_lurw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TESL, true); +} + +static bool trans_th_lurwu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_idx(ctx, a, MO_TEUL, true); +} + +static bool trans_th_lurh(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TESW, true); +} + +static bool trans_th_lurhu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TEUW, true); +} + +static bool trans_th_lurb(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_SB, true); +} + +static bool trans_th_lurbu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_UB, true); +} + +static bool trans_th_surd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_store_idx(ctx, a, MO_TESQ, true); +} + +static bool trans_th_surw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_TESL, true); +} + +static bool trans_th_surh(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_TESW, true); +} + +static bool trans_th_surb(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_SB, true); +} + /* XTheadMemPair */ static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 27bab07994..2461bcda0f 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -133,7 +133,8 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac || - ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempair || + ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ @@ -595,6 +596,24 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm) return addr; } +/* Compute a canonical address from a register plus reg offset. */ +static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) +{ + TCGv addr = temp_new(ctx); + TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); + + tcg_gen_add_tl(addr, src1, offs); + if (ctx->pm_mask_enabled) { + tcg_gen_andc_tl(addr, addr, pm_mask); + } else if (get_xl(ctx) == MXL_RV32) { + tcg_gen_ext32u_tl(addr, addr); + } + if (ctx->pm_base_enabled) { + tcg_gen_or_tl(addr, addr, pm_base); + } + return addr; +} + #ifndef CONFIG_USER_ONLY /* The states of mstatus_fs are: * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index ff2a83b56d..69e40f22dc 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -17,8 +17,10 @@ %rd2 20:5 %rs2 20:5 %sh5 20:5 +%imm5 20:s5 %sh6 20:6 %sh2 25:2 +%imm2 25:2 # Argument sets &r rd rs1 rs2 !extern @@ -26,6 +28,8 @@ &shift shamt rs1 rd !extern &th_bfext msb lsb rs1 rd &th_pair rd1 rs rd2 sh2 +&th_memidx rd rs1 rs2 imm2 +&th_meminc rd rs1 imm5 imm2 # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @@ -36,6 +40,8 @@ @sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd @sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd @th_pair ..... .. ..... ..... ... ..... ....... &th_pair %rd1 %rs %rd2 %sh2 +@th_memidx ..... .. ..... ..... ... ..... ....... &th_memidx %rd %rs1 %rs2 %imm2 +@th_meminc ..... .. ..... ..... ... ..... ....... &th_meminc %rd %rs1 %imm5 %imm2 # XTheadBa # Instead of defining a new encoding, we simply use the decoder to @@ -102,6 +108,54 @@ th_muls 00100 01 ..... ..... 001 ..... 0001011 @r th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r +# XTheadMemIdx +th_ldia 01111 .. ..... ..... 100 ..... 0001011 @th_meminc +th_ldib 01101 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lwia 01011 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lwib 01001 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lwuia 11011 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lwuib 11001 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lhia 00111 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lhib 00101 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lhuia 10111 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lhuib 10101 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lbia 00011 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lbib 00001 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lbuia 10011 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lbuib 10001 .. ..... ..... 100 ..... 0001011 @th_meminc +th_sdia 01111 .. ..... ..... 101 ..... 0001011 @th_meminc +th_sdib 01101 .. ..... ..... 101 ..... 0001011 @th_meminc +th_swia 01011 .. ..... ..... 101 ..... 0001011 @th_meminc +th_swib 01001 .. ..... ..... 101 ..... 0001011 @th_meminc +th_shia 00111 .. ..... ..... 101 ..... 0001011 @th_meminc +th_shib 00101 .. ..... ..... 101 ..... 0001011 @th_meminc +th_sbia 00011 .. ..... ..... 101 ..... 0001011 @th_meminc +th_sbib 00001 .. ..... ..... 101 ..... 0001011 @th_meminc + +th_lrd 01100 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrw 01000 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrwu 11000 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrh 00100 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrhu 10100 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrb 00000 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrbu 10000 .. ..... ..... 100 ..... 0001011 @th_memidx +th_srd 01100 .. ..... ..... 101 ..... 0001011 @th_memidx +th_srw 01000 .. ..... ..... 101 ..... 0001011 @th_memidx +th_srh 00100 .. ..... ..... 101 ..... 0001011 @th_memidx +th_srb 00000 .. ..... ..... 101 ..... 0001011 @th_memidx + +th_lurd 01110 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurw 01010 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurwu 11010 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurh 00110 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurhu 10110 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurb 00010 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurbu 10010 .. ..... ..... 100 ..... 0001011 @th_memidx +th_surd 01110 .. ..... ..... 101 ..... 0001011 @th_memidx +th_surw 01010 .. ..... ..... 101 ..... 0001011 @th_memidx +th_surh 00110 .. ..... ..... 101 ..... 0001011 @th_memidx +th_surb 00010 .. ..... ..... 101 ..... 0001011 @th_memidx + # XTheadMemPair th_ldd 11111 .. ..... ..... 100 ..... 0001011 @th_pair th_lwd 11100 .. ..... ..... 100 ..... 0001011 @th_pair -- 2.39.0 From MAILER-DAEMON Tue Jan 24 15:00:37 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKPTA-0007FX-Fm for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id j26-20020a5d453a000000b002bdf3809f59sm2607005wra.38.2023.01.24.12.00.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 12:00:08 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v3 13/14] RISC-V: Adding XTheadFmv ISA extension Date: Tue, 24 Jan 2023 20:59:44 +0100 Message-Id: <20230124195945.181842-14-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230124195945.181842-1-christoph.muellner@vrull.eu> References: <20230124195945.181842-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 20:00:16 -0000 From: Christoph Müllner This patch adds support for the XTheadFmv ISA extension. The patch uses the T-Head specific decoder and translation. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 45 ++++++++++++++++++++++ target/riscv/translate.c | 6 +-- target/riscv/xthead.decode | 4 ++ 5 files changed, 55 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 627512a184..1878c17a59 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -115,6 +115,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), + ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv), ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx), ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), @@ -1116,6 +1117,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), + DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 134dc29c6e..04630f3b79 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -481,6 +481,7 @@ struct RISCVCPUConfig { bool ext_xtheadcmo; bool ext_xtheadcondmov; bool ext_xtheadfmemidx; + bool ext_xtheadfmv; bool ext_xtheadmac; bool ext_xtheadmemidx; bool ext_xtheadmempair; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index dc82a9fc03..0403e90d7a 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -52,6 +52,12 @@ } \ } while (0) +#define REQUIRE_XTHEADFMV(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadfmv) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADMAC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadmac) { \ return false; \ @@ -449,6 +455,45 @@ static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a) return gen_fstore_idx(ctx, a, MO_TEUL, true); } +/* XTheadFmv */ + +static bool trans_th_fmv_hw_x(DisasContext *ctx, arg_th_fmv_hw_x *a) +{ + REQUIRE_XTHEADFMV(ctx); + REQUIRE_32BIT(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO); + TCGv_i64 t1 = tcg_temp_new_i64(); + + tcg_gen_extu_tl_i64(t1, src1); + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], t1, 32, 32); + tcg_temp_free_i64(t1); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_th_fmv_x_hw(DisasContext *ctx, arg_th_fmv_x_hw *a) +{ + REQUIRE_XTHEADFMV(ctx); + REQUIRE_32BIT(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + TCGv dst; + TCGv_i64 t1; + + dst = dest_gpr(ctx, a->rd); + t1 = tcg_temp_new_i64(); + + tcg_gen_extract_i64(t1, cpu_fpr[a->rs1], 32, 32); + tcg_gen_trunc_i64_tl(dst, t1); + gen_set_gpr(ctx, a->rd, dst); + tcg_temp_free_i64(t1); + mark_fs_dirty(ctx); + return true; +} + /* XTheadMac */ static bool gen_th_mac(DisasContext *ctx, arg_r *a, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index c52bc5e0af..d6163daeb2 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -133,9 +133,9 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadcondmov || - ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadmac || - ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempair || - ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv || + ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx || + ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 81daf1d694..d1d104bcf2 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -110,6 +110,10 @@ th_fsrw 01000 .. ..... ..... 111 ..... 0001011 @th_memidx th_fsurd 01110 .. ..... ..... 111 ..... 0001011 @th_memidx th_fsurw 01010 .. ..... ..... 111 ..... 0001011 @th_memidx +# XTheadFmv +th_fmv_hw_x 1010000 00000 ..... 001 ..... 0001011 @r2 +th_fmv_x_hw 1100000 00000 ..... 001 ..... 0001011 @r2 + # XTheadMac th_mula 00100 00 ..... ..... 001 ..... 0001011 @r th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r -- 2.39.0 From MAILER-DAEMON Tue Jan 24 15:00:39 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKPTC-0007GL-Fl for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id j26-20020a5d453a000000b002bdf3809f59sm2607005wra.38.2023.01.24.12.00.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 12:00:06 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v3 11/14] RISC-V: Set minimum priv version for Zfh to 1.11 Date: Tue, 24 Jan 2023 20:59:42 +0100 Message-Id: <20230124195945.181842-12-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230124195945.181842-1-christoph.muellner@vrull.eu> References: <20230124195945.181842-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 20:00:12 -0000 From: Christoph Müllner There are no differences for floating point instructions in priv version 1.11 and 1.12. There is also no dependency for Zfh to priv version 1.12. Therefore allow Zfh to be enabled for priv version 1.11. Acked-by: Alistair Francis Signed-off-by: Christoph Müllner --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6121a5e4ba..b18df9fa2a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -77,7 +77,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), - ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), + ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh), ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), -- 2.39.0 From MAILER-DAEMON Tue Jan 24 15:00:39 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKPTD-0007HW-CO for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 15:00:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKPSk-00076Y-W3 for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 15:00:11 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKPSj-0002P3-8B for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 15:00:10 -0500 Received: by mail-wr1-x42f.google.com with SMTP id r2so14986227wrv.7 for ; Tue, 24 Jan 2023 12:00:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3HHWLUiZToI0AX70Am5kjHM8u39NwJHXGmBjJ+SWShc=; b=aBGdg5z9s2o7pISwSLh3a67th55mbtYgwwzrIOycWHSDLm1/7LFkJcQWSaJ7eUX+f1 0hkd9zaAxorUuWbwbbl4e6UkX6nO64GYwpxbbvWcZRuDKv6wQ1eGfvrLyiLqaLL1HxVU unShW5XAUEOF+soOdOjS9Cr3lvC+jQtuJIuC88zi+O7pOgVqo+USBIT/BxqtJTWaqpfc 5Yx79j/ngavSTytb+X3CgevG6lpiFEvaGbJipwwS6sUSq6FMv/Un95G0sTgNeR41smBT dg/UigZMCm3Tonlgz8ceLLWE4Cae6aa4x1OgoajgWJUui2WZlJgozyj8Br82Wq4gjduM j/Rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3HHWLUiZToI0AX70Am5kjHM8u39NwJHXGmBjJ+SWShc=; b=lFdhLoOyOz+lWHqXDB3h+ySweLhAryrrV1WDHhnPORR4IAaO5He76agr/BwxW9zbrG OVoHt3RLvFY3lWkxmuenX8AypaZe2aoFNeVWIxuHNGt6I2q7OSidvm0Rrk4xZ8jKCvLz AYyYyE8SGpEPl3BUULQYpM0cU5YvWDmQ4I+XDoM35+53TLpGRyZxVv+fqyiAygfW3Stx YVycUZAjPUtY7+jy4x0BkQWTr7KxIil3nsXnVMk998cu8PN2ZFPDQViZynNS6CgcdSDJ A1LDFc3fY9uqpfc6+pnk/x8QbROaanQfIghBbY+tBU5xRxK4V4z8uMbBthXW/ccjiySq 2PxQ== X-Gm-Message-State: AFqh2koI6+APjKbjxDx/4+awv824gPA+xUXW/fenhyfTynJTA/YElftB 7pBerMoVX9hKda62gD9rl16kNUO3aL+BXrXh X-Google-Smtp-Source: AMrXdXvdpMCqZjz6e86BidlPjBHgQHn56xBMUw43xVXX6wOhd8kuxqdGjBECmdFW7R5GbBf7oE7g4A== X-Received: by 2002:adf:f90e:0:b0:2bc:aa67:28fb with SMTP id b14-20020adff90e000000b002bcaa6728fbmr22912707wrr.49.1674590408020; Tue, 24 Jan 2023 12:00:08 -0800 (PST) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id j26-20020a5d453a000000b002bdf3809f59sm2607005wra.38.2023.01.24.12.00.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 12:00:07 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v3 12/14] RISC-V: Add initial support for T-Head C906 Date: Tue, 24 Jan 2023 20:59:43 +0100 Message-Id: <20230124195945.181842-13-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230124195945.181842-1-christoph.muellner@vrull.eu> References: <20230124195945.181842-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 20:00:13 -0000 From: Christoph Müllner This patch adds the T-Head C906 to the list of known CPUs. Selecting this CPUs will automatically enable the available ISA extensions of the CPUs (incl. vendor extensions). Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Drop C910 as it does not differ from C906 - Set priv version to 1.11 (new fmin/fmax behaviour) Changes in v3: - Removed setting dropped 'xtheadxmae' extension target/riscv/cpu.c | 30 ++++++++++++++++++++++++++++++ target/riscv/cpu.h | 2 ++ target/riscv/cpu_vendorid.h | 6 ++++++ 3 files changed, 38 insertions(+) create mode 100644 target/riscv/cpu_vendorid.h diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b18df9fa2a..627512a184 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -279,6 +279,35 @@ static void rv64_sifive_e_cpu_init(Object *obj) cpu->cfg.mmu = false; } +static void rv64_thead_c906_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_priv_version(env, PRIV_VERSION_1_11_0); + + cpu->cfg.ext_g = true; + cpu->cfg.ext_c = true; + cpu->cfg.ext_u = true; + cpu->cfg.ext_s = true; + cpu->cfg.ext_icsr = true; + cpu->cfg.ext_zfh = true; + cpu->cfg.mmu = true; + cpu->cfg.ext_xtheadba = true; + cpu->cfg.ext_xtheadbb = true; + cpu->cfg.ext_xtheadbs = true; + cpu->cfg.ext_xtheadcmo = true; + cpu->cfg.ext_xtheadcondmov = true; + cpu->cfg.ext_xtheadfmemidx = true; + cpu->cfg.ext_xtheadmac = true; + cpu->cfg.ext_xtheadmemidx = true; + cpu->cfg.ext_xtheadmempair = true; + cpu->cfg.ext_xtheadsync = true; + + cpu->cfg.mvendorid = THEAD_VENDOR_ID; +} + static void rv128_base_cpu_init(Object *obj) { if (qemu_tcg_mttcg_enabled()) { @@ -1320,6 +1349,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), #endif }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b0ec5fcf9e..134dc29c6e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -27,6 +27,7 @@ #include "qom/object.h" #include "qemu/int128.h" #include "cpu_bits.h" +#include "cpu_vendorid.h" #define TCG_GUEST_DEFAULT_MO 0 @@ -53,6 +54,7 @@ #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") #if defined(TARGET_RISCV32) diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h new file mode 100644 index 0000000000..a5aa249bc9 --- /dev/null +++ b/target/riscv/cpu_vendorid.h @@ -0,0 +1,6 @@ +#ifndef TARGET_RISCV_CPU_VENDORID_H +#define TARGET_RISCV_CPU_VENDORID_H + +#define THEAD_VENDOR_ID 0x5b7 + +#endif /* TARGET_RISCV_CPU_VENDORID_H */ -- 2.39.0 From MAILER-DAEMON Tue Jan 24 15:00:39 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKPTD-0007Hy-Gm for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id j26-20020a5d453a000000b002bdf3809f59sm2607005wra.38.2023.01.24.12.00.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 12:00:10 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v3 14/14] target/riscv: add a MAINTAINERS entry for XThead* extension support Date: Tue, 24 Jan 2023 20:59:45 +0100 Message-Id: <20230124195945.181842-15-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.0 In-Reply-To: <20230124195945.181842-1-christoph.muellner@vrull.eu> References: <20230124195945.181842-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 20:00:16 -0000 From: Christoph Müllner The XThead* extensions are maintained by T-Head and VRULL. Adding a point of contact from both companies. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6982be48c6..f16916fd07 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -295,6 +295,14 @@ F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux-user/host/riscv64/ +RISC-V XThead* extensions +M: Christoph Muellner +M: LIU Zhiwei +L: qemu-riscv@nongnu.org +S: Supported +F: target/riscv/insn_trans/trans_xthead.c.inc +F: target/riscv/xthead*.decode + RISC-V XVentanaCondOps extension M: Philipp Tomsich L: qemu-riscv@nongnu.org -- 2.39.0 From MAILER-DAEMON Tue Jan 24 15:22:02 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKPnu-0005Wq-9T for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 15:22:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKPns-0005Vs-V3 for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 15:22:00 -0500 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKPnr-00065z-83 for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 15:22:00 -0500 Received: by mail-pg1-x52a.google.com with SMTP id e10so12053398pgc.9 for ; Tue, 24 Jan 2023 12:21:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=R47D02kk2u0RONXG5ssJGk0Q8tFn4GgB13wTpJ1cq5U=; b=pGWD4ZroX882+6RYqyXrIVvJstROkMVXkhXBnZVVW/NpyYjC6zO9O+0VawtDcJ/rnw RUzPAMV6/2EE/MK5q4nBaIE+CP64K1WN5GiVzzk8OaBcc5qDGltUe2veF9uQ6bZICemD NWG+U+xjsIM3i/67tjbcRT5v+nx8mH/oKbdv7V62fsVH9It5+0ExTmhMo+ut1VBFwVtO QNGpPjp8xqRPm+y0BSGUzZTplgthtRuAI3HvEY5wfeME9VkjMOfoCGX1PdjfYoU3GqTr APIT8/Z7uoEWGXffDJuTHcfAMWYw99PKcqmrujVIrqdmbQAUGc/aQck+1gvHQ2/ddamK Rl0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=R47D02kk2u0RONXG5ssJGk0Q8tFn4GgB13wTpJ1cq5U=; b=VviAq9aIWScz/wHj4kKreoaPSl0j/FVRYK0WwlFB9gX52DYq8FmI+/ToC8h4zs6JQU rhwoTBDCB+4EMcjWmvGzAAAxy7v44kr1ih5Oii8U3Pb9wlkYa8W6XNo2PMllTo6QGfly AgPlWcZBBkph2yUhSvdizSBuaNaAambSG5s3RtqBFTYE4mZxZ4cBl+Hew/hz9yVfccWz oMRhRk80HVQMkjMgnHVUH0++8xJAIaUPrIH5LtF6Pevk0WHWVJvlIobFckctlmLJrTy4 LQdLMOxJLORK3NRjg7sKQcKeFH17tsHFYS7SN6swjLJIkJ/byEjZU0/3ubGdPGNYvPmi 7QhA== X-Gm-Message-State: AFqh2kp0cn92hVyn4W4sgdzB6m7gNu+mTnO3Y58tgxPULIyDdgAy+DXk JIWKjOOs3BcDvEpMpCKp2KDULw== X-Google-Smtp-Source: AMrXdXs+QZU9rFS85FqU5cAQM+bSJUTO9xOn0T0wgdxO4YAxJ4ZTW+DJsTCoRbYfTsFKO2SE9Cv34A== X-Received: by 2002:a62:1556:0:b0:58b:c9db:c015 with SMTP id 83-20020a621556000000b0058bc9dbc015mr31756425pfv.30.1674591717569; Tue, 24 Jan 2023 12:21:57 -0800 (PST) Received: from [192.168.5.146] (rrcs-173-198-77-218.west.biz.rr.com. [173.198.77.218]) by smtp.gmail.com with ESMTPSA id u2-20020a056a00158200b0058ba2ebee1bsm2000457pfk.213.2023.01.24.12.21.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Jan 2023 12:21:56 -0800 (PST) Message-ID: <8a81e02c-5bb7-a82b-be16-e93362169a44@linaro.org> Date: Tue, 24 Jan 2023 10:21:52 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v3 02/14] RISC-V: Adding XTheadSync ISA extension Content-Language: en-US To: Christoph Muellner , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=c3=bcbner?= , Palmer Dabbelt , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu References: <20230124195945.181842-1-christoph.muellner@vrull.eu> <20230124195945.181842-3-christoph.muellner@vrull.eu> From: Richard Henderson In-Reply-To: <20230124195945.181842-3-christoph.muellner@vrull.eu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.148, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 20:22:01 -0000 On 1/24/23 09:59, Christoph Muellner wrote: > +static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a) > +{ > + (void) a; > + REQUIRE_XTHEADSYNC(ctx); > + > +#ifndef CONFIG_USER_ONLY > + REQUIRE_PRIV_MS(ctx); > + decode_save_opc(ctx); > + gen_helper_tlb_flush_all(cpu_env); Why are you using decode_save_opc() when helper_tlb_flush_all() cannot raise an exception? r~ From MAILER-DAEMON Tue Jan 24 15:30:53 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKPwT-00085f-6e for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 15:30:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKNeg-00068L-MF; Tue, 24 Jan 2023 13:04:33 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKNee-0006Qj-UJ; Tue, 24 Jan 2023 13:04:22 -0500 Received: by mail-wr1-x42a.google.com with SMTP id bk16so14698521wrb.11; Tue, 24 Jan 2023 10:04:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=WNOdRMqZW1+9BMIW8PgIFJ3fdOuSUkIMnKM8A3/iBtk=; b=Af1yp1jkcgoJL9KCUM/3EOswCm7YxlEdK+2MV05qczS1k2D0WfOeqeuCwl9ARkmjQA SWYttUampYMRMM9AaPKy5B+Rlle7TUJil/lxr3lsShNjG3ZmiS9ioiVnu2fhLNL8Sxhq zEKGTb3BTT6KAR4BzBN2jwnuV3YzF3pJdzySLKuwN17pT52nDSWW77emCfpiYlhsqHYv 3uec5/jBfdvhKHfUqi3+IF/5/s2LPjfdUBMt/eBMVLmAKsdcKUJZymNDU7R1C2kQOCs3 QGxIKmGKgefgbDZoEYWSnonydZ5AcT/lY7SoNxCyolB/Dfft+zHLytOeM03PujOgVgPz 4UJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=WNOdRMqZW1+9BMIW8PgIFJ3fdOuSUkIMnKM8A3/iBtk=; b=UTm4CPpEZtIxY1NVAVjl+zCQKot2Hc2rf7kYuA+MNCV8FwHPwh6Ob1pT8U6ZIBQ250 X3XRUkx7kWlFVXJtD6Xqfoqh21jib8kqpo7oEpHS4QLtuGILvCTwZpm5hMkD615NpGl8 zUM1ZXr8np5dbneatERr4J8hKsSpVVPCIQ+eHR7tTWFEWhCsMjmK6WZMZF/Y1k6Oe4dA 6yqwJSITUB/EfckKfOlW+RAeij5145FgK0KzivlNKaJPCcixG2EDnyozuC55RpjKaQc5 HsrA/mg+4ZQGrF91Gb6bNAmNg7Zo0o71G/vbU2MKQiqHDHUQAqNNEoPOEm2uv4gICLDj K+4Q== X-Gm-Message-State: AFqh2ko2XIItgkomh0tp3Oo04DUgIQVs0Mn688DMjwuhWZbFtBK/dA+J /flO8kL1BldCj4BzjDDaggnoOYkR9dw= X-Google-Smtp-Source: AMrXdXtW8QM9m3/YrlFjdBhagkyGe39yMmnbAxVB7oDrrizuLE1xNDtETwZi+qDLn8TgKhr5EKwKzw== X-Received: by 2002:adf:e98b:0:b0:2bc:804a:d1bb with SMTP id h11-20020adfe98b000000b002bc804ad1bbmr25127556wrm.49.1674583457891; Tue, 24 Jan 2023 10:04:17 -0800 (PST) Received: from debian ([2a10:d582:3bb:0:63f8:f640:f53e:dd47]) by smtp.gmail.com with ESMTPSA id v15-20020a5d43cf000000b002bdec340a1csm2413867wrr.110.2023.01.24.10.04.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 10:04:17 -0800 (PST) Date: Tue, 24 Jan 2023 18:04:10 +0000 From: Sudip Mukherjee To: Christoph Muellner Cc: Atish Patra , Anup Patel , =?iso-8859-1?B?RnLpZOlyaWMgUOl0cm90?= , Palmer Dabbelt , Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Philipp Tomsich , Richard Henderson , Weiwei Li Subject: Re: [PATCH v4 0/2] riscv: Add support for Zicbo[m,z,p] instructions Message-ID: References: <20220216154839.1024927-1-cmuellner@linux.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220216154839.1024927-1-cmuellner@linux.com> Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=sudipm.mukherjee@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Tue, 24 Jan 2023 15:30:50 -0500 X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 18:04:33 -0000 Hi Christoph, On Wed, Feb 16, 2022 at 04:48:37PM +0100, Christoph Muellner wrote: > The RISC-V base cache management operation ISA extension has been > ratified [1]. This patchset adds support for the defined instructions. > > As the exception behavior of these instructions depend on the PMP > configuration, the first patch introduces a new API to probe the access > of an address range with a specified size with optional nonfaulting > behavior. > > The Zicbo[m,z,p] patch should be straight-forward and has been reviewed > in previous versions of this patchset. I have not seen any v5 yet, unless I have missed. Are you planning to send one? fwiw, I rebased them on top of v7.2.0 and tested that it works. -- Regards Sudip From MAILER-DAEMON Tue Jan 24 15:44:38 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKQ9m-0002MN-9d for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 15:44:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKQ9k-0002M5-Nn for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 15:44:36 -0500 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKQ9j-0001Ip-4x for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 15:44:36 -0500 Received: by mail-pf1-x42d.google.com with SMTP id z3so12088192pfb.2 for ; Tue, 24 Jan 2023 12:44:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=VAYOki1uaj12loXH/2FrXicsk+HnZHDlpAPzgpMrWrM=; b=w0bId2wLOtNmMeKygTO4/L0x1W3b3PgpOIYNNwF6PJpqWGH0L5uC6898HeBHZME43z RO6PNDOduquES7+4Z6haNIoG2JfxlPq1MOyY6utlgKBFe+JJCQhaSkX7MC+zLtgz1FSP PNrRJMd54eeEj43g1xzzFJ4I1rVXcixQRMLIwVVNcpjy2u+Oby1eixFbvXPrT0Vm5Jji UT/gqqkBw8dRvMZxkoe1qgu0BPzLJumWn57foy204UK9UEg4dfu8P6GUFM6+SI/xItfz SN5Cdjxplg2GYxxPlPnzZiwkh1IqQpx7TX+BUuRKd8kgK3OrOGcW111SZ4SNBEkDnNmj moOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=VAYOki1uaj12loXH/2FrXicsk+HnZHDlpAPzgpMrWrM=; b=N9HRms5mopKobUgsLUlWSmi1CzFrJyVbr3PWO/DdhODVj4i/08xltd5WGWAF1Z/fhd e7VZwly4BMmOxj1WJ+UzK28V6luDGEquvZUgi+x6ZQBfN6aDIEBvn24foDAcTFBGbez5 2/XeBVgx8cOyTKTE5VSNw/25EP8Lf/N8aQYezxxTclbE/jm4cDdjjGcT7MjYnitH2MiI YykxpyBv5nrB9KITnhPeI4U/5QoeYXbkFp2Nt9tc+tTj9Rv4fFRdZU72KVADmX6re5By dE4P70/sVxRZsA9kYNIdFyqOQxRJb8At47mVZ/HY9mlIYXpxgIKeBxathOttzlrFnqz4 4ZAg== X-Gm-Message-State: AFqh2kpGEwZC45E1ZagxZwY/sTT7AZiJ4+lx15E6ZBqKh4jhg6PKOeLB 9fD5mIFSnkvHRF7fPoQoFsa2OA== X-Google-Smtp-Source: AMrXdXt4vqxiR3B+SvvxxUX6kwjPlCvUIvIJsTSBFB7uBYHdUg2CMJWtYZ4W8xEGtki74qnoH95eFQ== X-Received: by 2002:a05:6a00:1887:b0:58c:b0a:e504 with SMTP id x7-20020a056a00188700b0058c0b0ae504mr39647679pfh.18.1674593073494; Tue, 24 Jan 2023 12:44:33 -0800 (PST) Received: from [192.168.5.146] (rrcs-173-198-77-218.west.biz.rr.com. [173.198.77.218]) by smtp.gmail.com with ESMTPSA id q9-20020aa79609000000b005882b189a44sm2027619pfg.104.2023.01.24.12.44.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Jan 2023 12:44:32 -0800 (PST) Message-ID: <48ff4151-25d9-4b4d-d50a-6516000599c7@linaro.org> Date: Tue, 24 Jan 2023 10:44:28 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension Content-Language: en-US To: Christoph Muellner , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=c3=bcbner?= , Palmer Dabbelt , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu References: <20230124195945.181842-1-christoph.muellner@vrull.eu> <20230124195945.181842-9-christoph.muellner@vrull.eu> From: Richard Henderson In-Reply-To: <20230124195945.181842-9-christoph.muellner@vrull.eu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.148, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 20:44:37 -0000 On 1/24/23 09:59, Christoph Muellner wrote: > +static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop, > + int shamt) > +{ > + TCGv rd1 = dest_gpr(ctx, a->rd1); > + TCGv rd2 = dest_gpr(ctx, a->rd2); > + TCGv addr1 = tcg_temp_new(); > + TCGv addr2 = tcg_temp_new(); > + > + addr1 = get_address(ctx, a->rs, a->sh2 << shamt); > + if ((memop & MO_SIZE) == MO_64) { > + addr2 = get_address(ctx, a->rs, 8 + (a->sh2 << shamt)); > + } else { > + addr2 = get_address(ctx, a->rs, 4 + (a->sh2 << shamt)); > + } > + > + tcg_gen_qemu_ld_tl(rd1, addr1, ctx->mem_idx, memop); > + tcg_gen_qemu_ld_tl(rd2, addr2, ctx->mem_idx, memop); > + gen_set_gpr(ctx, a->rd1, rd1); > + gen_set_gpr(ctx, a->rd2, rd2); Since dest_gpr may return cpu_gpr[n], this may update the rd1 before recognizing the exception that the second load may generate. Is that correct? The manual says that rd1, rd2, and rs1 must not be the same, but you do not check this. r~ From MAILER-DAEMON Tue Jan 24 16:21:16 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKQjE-0003g5-Et for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 16:21:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKQjD-0003f4-2J for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 16:21:15 -0500 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKQjB-0006jx-J7 for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 16:21:14 -0500 Received: by mail-pf1-x42d.google.com with SMTP id 207so12120593pfv.5 for ; Tue, 24 Jan 2023 13:21:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=rYGKGO1HsVl+R3QDbx/CEvCzK1aj3hBceg6yCyxSRPo=; b=hU4qo4sQkj9t3FAYiv65Be7Boa93RjXxc8bf8Wd6Mzq46BOz86wAZhgfNek7BVs7Lq 3FfNuCE+6fKsUu+6qvJjmV/b5MpPBRs66vcnCa6dfvz/KipXu6KA6WH/jVZYACfJ9ihY 9IV6drRNmos5d55QYBMCm9OhccLUtux0BHgvk/FUJgLQ3CSjx9I7z1kqxCS+i4x5czb+ ZQ2L+vYaZlSka8C8qlWkqq4CcNqqL/BL5+8+NK/Oo8qiYjTPogKnFT8iDw2Rnmm3gGAX dP1rr7k8DyEW8MhIw2WLKlB8Qvibez/WcM/m76P72nJlSlgRaFaJNUCuOV5u718jUotw Bbnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=rYGKGO1HsVl+R3QDbx/CEvCzK1aj3hBceg6yCyxSRPo=; b=WONx/9HfDq24CtFlwIn7Y09eCH1rpB50q0pJHKT0UoZrrxjZ+BTMMJ8AyaCUeWoU+m CW9HuU9fIK9b2wBxjrwnBR9Tb15WhD+FX+WfMjSEjpBGCGyfOhJCuDM6Ydgm+fPR1cDo WpGw6emJibaE8D54hKnjC3/hd4Xwh0Y0xhOAbyb4CrggInJhv8spdf/6bciO47x3SN7w 740BkbCPZEhWjTPwUmrobO0rhBwKEmvhGloDSy/IeLEvrpHbQ+x6DrIs7zlbzgmTyDfI 7PNVR1zgf2KnI9G+88WLlHwRYbiNGt+lCFx0WlQFQoKpEaBAtjBSl+tWQCYbbX3uFv9E xw3A== X-Gm-Message-State: AFqh2kpa3AIZx0L3jOGbwt8yuMGYzTnFsYAAmTro1Ce3vD3FfB2PuaN7 GtSSW2dlgI/n3i/G5dhc0TjKxA== X-Google-Smtp-Source: AMrXdXuwxHFP1TsjkmqE+jTV72EW5dTbC5iSrBgKjKVpIeWzk7Ba9pFcsJ7vlyx02zgI4pKyWA52KA== X-Received: by 2002:a05:6a00:1d23:b0:58d:a91d:e9f8 with SMTP id a35-20020a056a001d2300b0058da91de9f8mr25464968pfx.18.1674595272021; Tue, 24 Jan 2023 13:21:12 -0800 (PST) Received: from [192.168.5.146] (rrcs-173-198-77-218.west.biz.rr.com. [173.198.77.218]) by smtp.gmail.com with ESMTPSA id p186-20020a62d0c3000000b0058abddad316sm2033267pfg.209.2023.01.24.13.21.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Jan 2023 13:21:11 -0800 (PST) Message-ID: <3d864ae7-5430-8db9-f91c-fd24f428b04d@linaro.org> Date: Tue, 24 Jan 2023 11:21:06 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v3 09/14] RISC-V: Adding T-Head MemIdx extension Content-Language: en-US To: Christoph Muellner , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=c3=bcbner?= , Palmer Dabbelt , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu References: <20230124195945.181842-1-christoph.muellner@vrull.eu> <20230124195945.181842-10-christoph.muellner@vrull.eu> From: Richard Henderson In-Reply-To: <20230124195945.181842-10-christoph.muellner@vrull.eu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.148, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 21:21:15 -0000 On 1/24/23 09:59, Christoph Muellner wrote: > +/* XTheadMemIdx */ > + > +/* > + * Load with memop from indexed address and add (imm5 << imm2) to rs1. > + * If !preinc, then the load address is rs1. > + * If preinc, then the load address is rs1 + (imm5) << imm2). > + */ > +static bool gen_load_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop, > + bool preinc) > +{ > + TCGv rd = dest_gpr(ctx, a->rd); > + TCGv addr = get_address(ctx, a->rs1, preinc ? a->imm5 << a->imm2 : 0); > + > + tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); > + addr = get_address(ctx, a->rs1, !preinc ? a->imm5 << a->imm2 : 0); First, you're leaking the previous 'addr' temporary. Second, get_address may make modifications to 'addr' which you don't want to write back. Third, you are not checking for rd != rs1. I think what you want is int imm = a->imm5 << a->imm2; TCGv addr = get_address(ctx, a->rs1, preinc ? imm : 0); TCGv rd = dest_gpr(ctx, a->rd); TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE); tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); tcg_gen_addi_tl(rs1, rs1, imm); gen_set_gpr(ctx, a->rd, rd); gen_set_gpr(ctx, a->rs1, rs1); r~ From MAILER-DAEMON Tue Jan 24 16:22:44 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKQke-0004R6-L7 for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 16:22:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKQkc-0004QM-Di for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 16:22:42 -0500 Received: from mail-oa1-x43.google.com ([2001:4860:4864:20::43]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKQka-0006sm-TR for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 16:22:42 -0500 Received: by mail-oa1-x43.google.com with SMTP id 586e51a60fabf-15085b8a2f7so19233986fac.2 for ; Tue, 24 Jan 2023 13:22:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=2a6Ii3+/fNqTRusHknv7wUakA1g7otz+I/pIaSQxpHM=; b=ATcSaoyPGCuf+L3nLfOGsmFlc3TSdsifLX6d1gcel9/6P6XNxORjeL/6hsq+JeMzdC 2Lq01//641yFgK2B6VTQO9uTiBQ56GHdfOmAqcYEYXNkOG62O678WzNIiCXeE5ra7ZdS JAcXf4rra/rl6araULA9ZRtonL+rzPbGjmoWrz6rx56eNTS7R1IVBwbXPqvj8W4E41zL 5TbUDCxxmN/kcnjIQETiem7a0VsKqxtiATeAISCoYXpXno6+LxnRAm0BpaxQ60mr+WcM cubPcpEG7kw98v4TjWZzAnWP/2k/7wKv/o2pWh0awA/O9vJy2UOGO1IJqFnwxdMy8S5Z hsFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=2a6Ii3+/fNqTRusHknv7wUakA1g7otz+I/pIaSQxpHM=; b=KBIEWNCZhSOUJYcr5A3nLsUWR7GB/TmNi2dg7I2MZ6r45QmD5wJjY3UzLMKA3eG5Nj nYZ1/QnwSHyJqSOmt0hO1UJeLeNqeVDGx/LDObLzBnFj5lWky2cmPqNcBrkbiBhUfVz0 5JepP45jyeZhEySdC7V/Rc97yCOcN6XJKPg7+fREjz2p45smhcQr35pEOLUH0ZdBEhUr 52IbyBsFeDZE2xF0ej2a90G0Y52laAJNJlPZNen82H59IhmJKx+r3VHwN29SwoMEK7Iw VYpjjZYghUUDUE/iSERMj6GPC9I7+sN90utGSQ9yCJ95ggj/RGrfBPHPIa7mCsF/lGa+ bLlw== X-Gm-Message-State: AO0yUKVtg/ig0x2Ti5ZI4PJpaAIO63Nbbkmm48c0JadzXBeHoX3xdSzi 0HAYtZdleq4BfuBMcLFrK7enkQ== X-Google-Smtp-Source: AK7set8tE7rqJRIpA65NvxCdOFAqlUBWJOBmrRKsEpBtABl/P3+SDOypaph9NDrVasEZWCx4VvoiYA== X-Received: by 2002:a05:6870:d796:b0:163:1b4d:d58a with SMTP id bd22-20020a056870d79600b001631b4dd58amr1445697oab.33.1674595359107; Tue, 24 Jan 2023 13:22:39 -0800 (PST) Received: from grind.dc1.ventanamicro.com (200-148-13-157.dsl.telesp.net.br. [200.148.13.157]) by smtp.gmail.com with ESMTPSA id go3-20020a056870da0300b0014474019e50sm1212306oab.24.2023.01.24.13.22.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 13:22:38 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v4 0/3] hw/riscv: misc cleanups Date: Tue, 24 Jan 2023 18:22:31 -0300 Message-Id: <20230124212234.412630-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::43; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x43.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 21:22:42 -0000 Hi, These are the last 3 patches from the series "[PATCH v3 0/7] riscv: fdt related cleanups" That can be sent in separate from the fdt work. Patches are all acked. Changes from v3: - patches 1,2,3: - former patches 5, 6 and 7 from "[PATCH v3 0/7] riscv: fdt related cleanups" - v3 link: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg04464.html Daniel Henrique Barboza (3): hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' hw/riscv/spike.c | 18 +- hw/riscv/virt.c | 462 ++++++++++++++++++++++++----------------------- 2 files changed, 242 insertions(+), 238 deletions(-) -- 2.39.1 From MAILER-DAEMON Tue Jan 24 16:22:45 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKQkf-0004T0-Pf for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 16:22:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKQke-0004Qz-BL for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 16:22:44 -0500 Received: from mail-oa1-x29.google.com ([2001:4860:4864:20::29]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKQkc-0006t2-HA for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 16:22:44 -0500 Received: by mail-oa1-x29.google.com with SMTP id 586e51a60fabf-1631b928691so2858442fac.11 for ; Tue, 24 Jan 2023 13:22:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=G4ceGBcbRnx19klib3zZuWCsu8sIygPXzbiLUBOWnuU=; b=PUh0hlOd7HHNmbsmzlBO5vPNFauYI7IWjGKSE6EQQV+iZ8oz7oqitguIj6Zkfp4LF0 J0Yx8M756hl/ipNApDHXu9yGPvHiA8fGa5EavqEPXcImNvRJwYZq28srErdbfHzzb8Va lTlcjqCyEkymGI7eBsn2RvW1jqChbyrCfAvP3CNwkpZt0JoQHln3kHDH+8RONa/+dviK uu8/Cv7pX5pWc8F61yjQpecsGM/Csc4XVu6PY+EUOCxhkoPjF7mvfInWeRksF/KS3Kbc io8/D/E952iynU1Paf70hPv1fEKwuu7dUeZBy5PioCfwyXRppXhNf7Rukz2nXzZoZb/6 kllw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=G4ceGBcbRnx19klib3zZuWCsu8sIygPXzbiLUBOWnuU=; b=dddctlORc/Bbwnh0h3McKTB2HKdXOdklrb1a7TKoPEZB6ikamF1PbBHa7X8ZbTQWxJ cBBgpaFq9Wa3QEVVbYFRl2EuLe6mTML1pR2FNMUt6HGjyDM510ElPvtwXmpOIOIl0E2f JNgfAOzXU0ektmyZqxLq3wDYWVjl0O0AI9ztb6yurhf1JRMd08iUJEHuHfdTm+qtKRTW s46nU9Na7MI1zYq5UILdQ5QwEt0UtfhhSHblEEedY8D/gx7U8pbDkrOSP5Uvc55hU5bC joqjg0Em42o1x68y01wD71wMfOfZclRJOXsfooa+dqOUdPgF/9Iioq7Zx3GxtPBph0bx cpEA== X-Gm-Message-State: AFqh2koNYKkynFOdf5S5lhB6aIkEAR1V/6Fuy1ZjlDxU5/uMvY4NJvQw 8mb+4V8lzGKBlovySgpTim4RaRWcMwotwChzXtI= X-Google-Smtp-Source: AK7set94fGtL7qe/gcVWCrRt/ZGDQYRGLy+2BaNC6xaUMP7syRAw1X7vWVtjEMK3ttkZ/Qe68/iF5g== X-Received: by 2002:a05:6870:a454:b0:160:bcee:d00e with SMTP id n20-20020a056870a45400b00160bceed00emr2715024oal.59.1674595361507; Tue, 24 Jan 2023 13:22:41 -0800 (PST) Received: from grind.dc1.ventanamicro.com (200-148-13-157.dsl.telesp.net.br. [200.148.13.157]) by smtp.gmail.com with ESMTPSA id go3-20020a056870da0300b0014474019e50sm1212306oab.24.2023.01.24.13.22.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 13:22:41 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 1/3] hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() Date: Tue, 24 Jan 2023 18:22:32 -0300 Message-Id: <20230124212234.412630-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230124212234.412630-1-dbarboza@ventanamicro.com> References: <20230124212234.412630-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::29; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x29.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 21:22:44 -0000 riscv_socket_count() returns either ms->numa_state->num_nodes or 1 depending on NUMA support. In any case the value can be retrieved only once and used in the rest of the function. This will also alleviate the rename we're going to do next by reducing the instances of MachineState 'mc' inside hw/riscv/virt.c. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 48326406fd..f0fdb295e0 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -505,13 +505,14 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, int cpu, socket; char *imsic_name; MachineState *mc = MACHINE(s); + int socket_count = riscv_socket_count(mc); uint32_t imsic_max_hart_per_socket, imsic_guest_bits; uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; *msi_m_phandle = (*phandle)++; *msi_s_phandle = (*phandle)++; imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2); - imsic_regs = g_new0(uint32_t, riscv_socket_count(mc) * 4); + imsic_regs = g_new0(uint32_t, socket_count * 4); /* M-level IMSIC node */ for (cpu = 0; cpu < mc->smp.cpus; cpu++) { @@ -519,7 +520,7 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); } imsic_max_hart_per_socket = 0; - for (socket = 0; socket < riscv_socket_count(mc); socket++) { + for (socket = 0; socket < socket_count; socket++) { imsic_addr = memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; imsic_size = IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; @@ -545,14 +546,14 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, - riscv_socket_count(mc) * sizeof(uint32_t) * 4); + socket_count * sizeof(uint32_t) * 4); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); - if (riscv_socket_count(mc) > 1) { + if (socket_count > 1) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", - imsic_num_bits(riscv_socket_count(mc))); + imsic_num_bits(socket_count)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); } @@ -567,7 +568,7 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, } imsic_guest_bits = imsic_num_bits(s->aia_guests + 1); imsic_max_hart_per_socket = 0; - for (socket = 0; socket < riscv_socket_count(mc); socket++) { + for (socket = 0; socket < socket_count; socket++) { imsic_addr = memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX_SIZE; imsic_size = IMSIC_HART_SIZE(imsic_guest_bits) * @@ -594,18 +595,18 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, - riscv_socket_count(mc) * sizeof(uint32_t) * 4); + socket_count * sizeof(uint32_t) * 4); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); if (imsic_guest_bits) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits", imsic_guest_bits); } - if (riscv_socket_count(mc) > 1) { + if (socket_count > 1) { qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", - imsic_num_bits(riscv_socket_count(mc))); + imsic_num_bits(socket_count)); qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); } @@ -733,6 +734,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, MachineState *mc = MACHINE(s); uint32_t msi_m_phandle = 0, msi_s_phandle = 0; uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; + int socket_count = riscv_socket_count(mc); qemu_fdt_add_subnode(mc->fdt, "/cpus"); qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", @@ -744,7 +746,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, intc_phandles = g_new0(uint32_t, mc->smp.cpus); phandle_pos = mc->smp.cpus; - for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { + for (socket = (socket_count - 1); socket >= 0; socket--) { phandle_pos -= s->soc[socket].num_harts; clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); @@ -775,7 +777,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, } phandle_pos = mc->smp.cpus; - for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { + for (socket = (socket_count - 1); socket >= 0; socket--) { phandle_pos -= s->soc[socket].num_harts; if (s->aia_type == VIRT_AIA_TYPE_NONE) { @@ -790,7 +792,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, g_free(intc_phandles); - for (socket = 0; socket < riscv_socket_count(mc); socket++) { + for (socket = 0; socket < socket_count; socket++) { if (socket == 0) { *irq_mmio_phandle = xplic_phandles[socket]; *irq_virtio_phandle = xplic_phandles[socket]; @@ -1051,7 +1053,8 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) /* Pass seed to RNG */ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); - qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); + qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", + rng_seed, sizeof(rng_seed)); } static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, @@ -1320,9 +1323,10 @@ static void virt_machine_init(MachineState *machine) char *soc_name; DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; int i, base_hartid, hart_count; + int socket_count = riscv_socket_count(machine); /* Check socket count limit */ - if (VIRT_SOCKETS_MAX < riscv_socket_count(machine)) { + if (VIRT_SOCKETS_MAX < socket_count) { error_report("number of sockets/nodes should be less than %d", VIRT_SOCKETS_MAX); exit(1); @@ -1330,7 +1334,7 @@ static void virt_machine_init(MachineState *machine) /* Initialize sockets */ mmio_irqchip = virtio_irqchip = pcie_irqchip = NULL; - for (i = 0; i < riscv_socket_count(machine); i++) { + for (i = 0; i < socket_count; i++) { if (!riscv_socket_check_hartids(machine, i)) { error_report("discontinuous hartids in socket%d", i); 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[200.148.13.157]) by smtp.gmail.com with ESMTPSA id go3-20020a056870da0300b0014474019e50sm1212306oab.24.2023.01.24.13.22.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 13:22:43 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 2/3] hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' Date: Tue, 24 Jan 2023 18:22:33 -0300 Message-Id: <20230124212234.412630-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230124212234.412630-1-dbarboza@ventanamicro.com> References: <20230124212234.412630-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::30; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 21:22:49 -0000 We have a convention in other QEMU boards/archs to name MachineState pointers as either 'machine' or 'ms'. MachineClass pointers are usually called 'mc'. The 'virt' RISC-V machine has a lot of instances where MachineState pointers are named 'mc'. There is nothing wrong with that, but we gain more compatibility with the rest of the QEMU code base, and easier reviews, if we follow QEMU conventions. Rename all 'mc' MachineState pointers to 'ms'. This is a very tedious and mechanical patch that was produced by doing the following: - find/replace all 'MachineState *mc' to 'MachineState *ms'; - find/replace all 'mc->fdt' to 'ms->fdt'; - find/replace all 'mc->smp.cpus' to 'ms->smp.cpus'; - replace any remaining occurrences of 'mc' that the compiler complained about. Suggested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza --- hw/riscv/virt.c | 434 ++++++++++++++++++++++++------------------------ 1 file changed, 217 insertions(+), 217 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index f0fdb295e0..02edfcf71f 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -227,7 +227,7 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, { int cpu; uint32_t cpu_phandle; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); char *name, *cpu_name, *core_name, *intc_name; bool is_32_bit = riscv_is_32bit(&s->soc[0]); @@ -236,40 +236,40 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); - qemu_fdt_add_subnode(mc->fdt, cpu_name); + qemu_fdt_add_subnode(ms->fdt, cpu_name); if (riscv_feature(&s->soc[socket].harts[cpu].env, RISCV_FEATURE_MMU)) { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", + qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); } else { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", + qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type", "riscv,none"); } name = riscv_isa_string(&s->soc[socket].harts[cpu]); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); + qemu_fdt_setprop_string(ms->fdt, cpu_name, "riscv,isa", name); g_free(name); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "compatible", "riscv"); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "status", "okay"); - qemu_fdt_setprop_cell(mc->fdt, cpu_name, "reg", + qemu_fdt_setprop_string(ms->fdt, cpu_name, "compatible", "riscv"); + qemu_fdt_setprop_string(ms->fdt, cpu_name, "status", "okay"); + qemu_fdt_setprop_cell(ms->fdt, cpu_name, "reg", s->soc[socket].hartid_base + cpu); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, cpu_name, socket); - qemu_fdt_setprop_cell(mc->fdt, cpu_name, "phandle", cpu_phandle); + qemu_fdt_setprop_string(ms->fdt, cpu_name, "device_type", "cpu"); + riscv_socket_fdt_write_id(ms, cpu_name, socket); + qemu_fdt_setprop_cell(ms->fdt, cpu_name, "phandle", cpu_phandle); intc_phandles[cpu] = (*phandle)++; intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); - qemu_fdt_add_subnode(mc->fdt, intc_name); - qemu_fdt_setprop_cell(mc->fdt, intc_name, "phandle", + qemu_fdt_add_subnode(ms->fdt, intc_name); + qemu_fdt_setprop_cell(ms->fdt, intc_name, "phandle", intc_phandles[cpu]); - qemu_fdt_setprop_string(mc->fdt, intc_name, "compatible", + qemu_fdt_setprop_string(ms->fdt, intc_name, "compatible", "riscv,cpu-intc"); - qemu_fdt_setprop(mc->fdt, intc_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(mc->fdt, intc_name, "#interrupt-cells", 1); + qemu_fdt_setprop(ms->fdt, intc_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, intc_name, "#interrupt-cells", 1); core_name = g_strdup_printf("%s/core%d", clust_name, cpu); - qemu_fdt_add_subnode(mc->fdt, core_name); - qemu_fdt_setprop_cell(mc->fdt, core_name, "cpu", cpu_phandle); + qemu_fdt_add_subnode(ms->fdt, core_name); + qemu_fdt_setprop_cell(ms->fdt, core_name, "cpu", cpu_phandle); g_free(core_name); g_free(intc_name); @@ -282,16 +282,16 @@ static void create_fdt_socket_memory(RISCVVirtState *s, { char *mem_name; uint64_t addr, size; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); - addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(mc, socket); - size = riscv_socket_mem_size(mc, socket); + addr = memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms, socket); + size = riscv_socket_mem_size(ms, socket); mem_name = g_strdup_printf("/memory@%lx", (long)addr); - qemu_fdt_add_subnode(mc->fdt, mem_name); - qemu_fdt_setprop_cells(mc->fdt, mem_name, "reg", + qemu_fdt_add_subnode(ms->fdt, mem_name); + qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); - qemu_fdt_setprop_string(mc->fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, mem_name, socket); + qemu_fdt_setprop_string(ms->fdt, mem_name, "device_type", "memory"); + riscv_socket_fdt_write_id(ms, mem_name, socket); g_free(mem_name); } @@ -303,7 +303,7 @@ static void create_fdt_socket_clint(RISCVVirtState *s, char *clint_name; uint32_t *clint_cells; unsigned long clint_addr; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); static const char * const clint_compat[2] = { "sifive,clint0", "riscv,clint0" }; @@ -319,15 +319,15 @@ static void create_fdt_socket_clint(RISCVVirtState *s, clint_addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); clint_name = g_strdup_printf("/soc/clint@%lx", clint_addr); - qemu_fdt_add_subnode(mc->fdt, clint_name); - qemu_fdt_setprop_string_array(mc->fdt, clint_name, "compatible", + qemu_fdt_add_subnode(ms->fdt, clint_name); + qemu_fdt_setprop_string_array(ms->fdt, clint_name, "compatible", (char **)&clint_compat, ARRAY_SIZE(clint_compat)); - qemu_fdt_setprop_cells(mc->fdt, clint_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, clint_name, "reg", 0x0, clint_addr, 0x0, memmap[VIRT_CLINT].size); - qemu_fdt_setprop(mc->fdt, clint_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, clint_name, socket); + riscv_socket_fdt_write_id(ms, clint_name, socket); g_free(clint_name); g_free(clint_cells); @@ -344,7 +344,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, uint32_t *aclint_mswi_cells; uint32_t *aclint_sswi_cells; uint32_t *aclint_mtimer_cells; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); aclint_mswi_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); aclint_mtimer_cells = g_new0(uint32_t, s->soc[socket].num_harts * 2); @@ -363,16 +363,16 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { addr = memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); name = g_strdup_printf("/soc/mswi@%lx", addr); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-mswi"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", aclint_mswi_cells, aclint_cells_size); - qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, name, socket); + qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); + riscv_socket_fdt_write_id(ms, name, socket); g_free(name); } @@ -386,33 +386,33 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, size = memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; } name = g_strdup_printf("/soc/mtimer@%lx", addr); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-mtimer"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 0x0, RISCV_ACLINT_DEFAULT_MTIME); - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", aclint_mtimer_cells, aclint_cells_size); - riscv_socket_fdt_write_id(mc, name, socket); + riscv_socket_fdt_write_id(ms, name, socket); g_free(name); if (s->aia_type != VIRT_AIA_TYPE_APLIC_IMSIC) { addr = memmap[VIRT_ACLINT_SSWI].base + (memmap[VIRT_ACLINT_SSWI].size * socket); name = g_strdup_printf("/soc/sswi@%lx", addr); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "riscv,aclint-sswi"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, name, "interrupts-extended", aclint_sswi_cells, aclint_cells_size); - qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, name, socket); + qemu_fdt_setprop(ms->fdt, name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", 0); + riscv_socket_fdt_write_id(ms, name, socket); g_free(name); } @@ -430,7 +430,7 @@ static void create_fdt_socket_plic(RISCVVirtState *s, char *plic_name; uint32_t *plic_cells; unsigned long plic_addr; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); static const char * const plic_compat[2] = { "sifive,plic-1.0.0", "riscv,plic0" }; @@ -456,27 +456,27 @@ static void create_fdt_socket_plic(RISCVVirtState *s, plic_phandles[socket] = (*phandle)++; plic_addr = memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socket); plic_name = g_strdup_printf("/soc/plic@%lx", plic_addr); - qemu_fdt_add_subnode(mc->fdt, plic_name); - qemu_fdt_setprop_cell(mc->fdt, plic_name, + qemu_fdt_add_subnode(ms->fdt, plic_name); + qemu_fdt_setprop_cell(ms->fdt, plic_name, "#interrupt-cells", FDT_PLIC_INT_CELLS); - qemu_fdt_setprop_cell(mc->fdt, plic_name, + qemu_fdt_setprop_cell(ms->fdt, plic_name, "#address-cells", FDT_PLIC_ADDR_CELLS); - qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", + qemu_fdt_setprop_string_array(ms->fdt, plic_name, "compatible", (char **)&plic_compat, ARRAY_SIZE(plic_compat)); - qemu_fdt_setprop(mc->fdt, plic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, plic_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, plic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(ms->fdt, plic_name, "interrupts-extended", plic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cells(mc->fdt, plic_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, plic_name, "reg", 0x0, plic_addr, 0x0, memmap[VIRT_PLIC].size); - qemu_fdt_setprop_cell(mc->fdt, plic_name, "riscv,ndev", + qemu_fdt_setprop_cell(ms->fdt, plic_name, "riscv,ndev", VIRT_IRQCHIP_NUM_SOURCES - 1); - riscv_socket_fdt_write_id(mc, plic_name, socket); - qemu_fdt_setprop_cell(mc->fdt, plic_name, "phandle", + riscv_socket_fdt_write_id(ms, plic_name, socket); + qemu_fdt_setprop_cell(ms->fdt, plic_name, "phandle", plic_phandles[socket]); if (!socket) { - platform_bus_add_all_fdt_nodes(mc->fdt, plic_name, + platform_bus_add_all_fdt_nodes(ms->fdt, plic_name, memmap[VIRT_PLATFORM_BUS].base, memmap[VIRT_PLATFORM_BUS].size, VIRT_PLATFORM_BUS_IRQ); @@ -504,18 +504,18 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, { int cpu, socket; char *imsic_name; - MachineState *mc = MACHINE(s); - int socket_count = riscv_socket_count(mc); + MachineState *ms = MACHINE(s); + int socket_count = riscv_socket_count(ms); uint32_t imsic_max_hart_per_socket, imsic_guest_bits; uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; *msi_m_phandle = (*phandle)++; *msi_s_phandle = (*phandle)++; - imsic_cells = g_new0(uint32_t, mc->smp.cpus * 2); + imsic_cells = g_new0(uint32_t, ms->smp.cpus * 2); imsic_regs = g_new0(uint32_t, socket_count * 4); /* M-level IMSIC node */ - for (cpu = 0; cpu < mc->smp.cpus; cpu++) { + for (cpu = 0; cpu < ms->smp.cpus; cpu++) { imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_EXT); } @@ -534,35 +534,35 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, } imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)memmap[VIRT_IMSIC_M].base); - qemu_fdt_add_subnode(mc->fdt, imsic_name); - qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", + qemu_fdt_add_subnode(ms->fdt, imsic_name); + qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", FDT_IMSIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", - imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); - qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", + imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); + qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, socket_count * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); if (socket_count > 1) { - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", imsic_num_bits(socket_count)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); } - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle); + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_m_phandle); g_free(imsic_name); /* S-level IMSIC node */ - for (cpu = 0; cpu < mc->smp.cpus; cpu++) { + for (cpu = 0; cpu < ms->smp.cpus; cpu++) { imsic_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); imsic_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_S_EXT); } @@ -583,34 +583,34 @@ static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, } imsic_name = g_strdup_printf("/soc/imsics@%lx", (unsigned long)memmap[VIRT_IMSIC_S].base); - qemu_fdt_add_subnode(mc->fdt, imsic_name); - qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", + qemu_fdt_add_subnode(ms->fdt, imsic_name); + qemu_fdt_setprop_string(ms->fdt, imsic_name, "compatible", "riscv,imsics"); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "#interrupt-cells", FDT_IMSIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", + qemu_fdt_setprop(ms->fdt, imsic_name, "msi-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", - imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); - qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, + qemu_fdt_setprop(ms->fdt, imsic_name, "interrupts-extended", + imsic_cells, ms->smp.cpus * sizeof(uint32_t) * 2); + qemu_fdt_setprop(ms->fdt, imsic_name, "reg", imsic_regs, socket_count * sizeof(uint32_t) * 4); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,num-ids", VIRT_IRQCHIP_NUM_MSIS); if (imsic_guest_bits) { - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,guest-index-bits", imsic_guest_bits); } if (socket_count > 1) { - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,hart-index-bits", imsic_num_bits(imsic_max_hart_per_socket)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-bits", imsic_num_bits(socket_count)); - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shift", + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "riscv,group-index-shift", IMSIC_MMIO_GROUP_MIN_SHIFT); } - qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle); + qemu_fdt_setprop_cell(ms->fdt, imsic_name, "phandle", *msi_s_phandle); g_free(imsic_name); g_free(imsic_regs); @@ -629,7 +629,7 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, char *aplic_name; uint32_t *aplic_cells; unsigned long aplic_addr; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); uint32_t aplic_m_phandle, aplic_s_phandle; aplic_m_phandle = (*phandle)++; @@ -644,28 +644,28 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_addr = memmap[VIRT_APLIC_M].base + (memmap[VIRT_APLIC_M].size * socket); aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); - qemu_fdt_add_subnode(mc->fdt, aplic_name); - qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, + qemu_fdt_add_subnode(ms->fdt, aplic_name); + qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#interrupt-cells", FDT_APLIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); if (s->aia_type == VIRT_AIA_TYPE_APLIC) { - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); } else { - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_m_phandle); } - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", VIRT_IRQCHIP_NUM_SOURCES); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,children", aplic_s_phandle); - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "riscv,delegate", aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(mc, aplic_name, socket); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); + riscv_socket_fdt_write_id(ms, aplic_name, socket); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_m_phandle); g_free(aplic_name); /* S-level APLIC node */ @@ -676,27 +676,27 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, aplic_addr = memmap[VIRT_APLIC_S].base + (memmap[VIRT_APLIC_S].size * socket); aplic_name = g_strdup_printf("/soc/aplic@%lx", aplic_addr); - qemu_fdt_add_subnode(mc->fdt, aplic_name); - qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,aplic"); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, + qemu_fdt_add_subnode(ms->fdt, aplic_name); + qemu_fdt_setprop_string(ms->fdt, aplic_name, "compatible", "riscv,aplic"); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "#interrupt-cells", FDT_APLIC_INT_CELLS); - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupt-controller", NULL, 0); if (s->aia_type == VIRT_AIA_TYPE_APLIC) { - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", + qemu_fdt_setprop(ms->fdt, aplic_name, "interrupts-extended", aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); } else { - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "msi-parent", msi_s_phandle); } - qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", + qemu_fdt_setprop_cells(ms->fdt, aplic_name, "reg", 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "riscv,num-sources", VIRT_IRQCHIP_NUM_SOURCES); - riscv_socket_fdt_write_id(mc, aplic_name, socket); - qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); + riscv_socket_fdt_write_id(ms, aplic_name, socket); + qemu_fdt_setprop_cell(ms->fdt, aplic_name, "phandle", aplic_s_phandle); if (!socket) { - platform_bus_add_all_fdt_nodes(mc->fdt, aplic_name, + platform_bus_add_all_fdt_nodes(ms->fdt, aplic_name, memmap[VIRT_PLATFORM_BUS].base, memmap[VIRT_PLATFORM_BUS].size, VIRT_PLATFORM_BUS_IRQ); @@ -711,13 +711,13 @@ static void create_fdt_socket_aplic(RISCVVirtState *s, static void create_fdt_pmu(RISCVVirtState *s) { char *pmu_name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); RISCVCPU hart = s->soc[0].harts[0]; pmu_name = g_strdup_printf("/soc/pmu"); - qemu_fdt_add_subnode(mc->fdt, pmu_name); - qemu_fdt_setprop_string(mc->fdt, pmu_name, "compatible", "riscv,pmu"); - riscv_pmu_generate_fdt_node(mc->fdt, hart.cfg.pmu_num, pmu_name); + qemu_fdt_add_subnode(ms->fdt, pmu_name); + qemu_fdt_setprop_string(ms->fdt, pmu_name, "compatible", "riscv,pmu"); + riscv_pmu_generate_fdt_node(ms->fdt, hart.cfg.pmu_num, pmu_name); g_free(pmu_name); } @@ -731,26 +731,26 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, { char *clust_name; int socket, phandle_pos; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); uint32_t msi_m_phandle = 0, msi_s_phandle = 0; uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; - int socket_count = riscv_socket_count(mc); + int socket_count = riscv_socket_count(ms); - qemu_fdt_add_subnode(mc->fdt, "/cpus"); - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", + qemu_fdt_add_subnode(ms->fdt, "/cpus"); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "timebase-frequency", RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ); - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#size-cells", 0x0); - qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); - qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); + qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); + qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); - intc_phandles = g_new0(uint32_t, mc->smp.cpus); + intc_phandles = g_new0(uint32_t, ms->smp.cpus); - phandle_pos = mc->smp.cpus; + phandle_pos = ms->smp.cpus; for (socket = (socket_count - 1); socket >= 0; socket--) { phandle_pos -= s->soc[socket].num_harts; clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); - qemu_fdt_add_subnode(mc->fdt, clust_name); + qemu_fdt_add_subnode(ms->fdt, clust_name); create_fdt_socket_cpus(s, socket, clust_name, phandle, &intc_phandles[phandle_pos]); @@ -776,7 +776,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, *msi_pcie_phandle = msi_s_phandle; } - phandle_pos = mc->smp.cpus; + phandle_pos = ms->smp.cpus; for (socket = (socket_count - 1); socket >= 0; socket--) { phandle_pos -= s->soc[socket].num_harts; @@ -807,7 +807,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, } } - riscv_socket_fdt_write_distance_matrix(mc); + riscv_socket_fdt_write_distance_matrix(ms); } static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, @@ -815,23 +815,23 @@ static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, { int i; char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); for (i = 0; i < VIRTIO_COUNT; i++) { name = g_strdup_printf("/soc/virtio_mmio@%lx", (long)(memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size)); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "virtio,mmio"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "virtio,mmio"); + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 0x0, memmap[VIRT_VIRTIO].size); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_virtio_phandle); if (s->aia_type == VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", VIRTIO_IRQ + i); } else { - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", VIRTIO_IRQ + i, 0x4); } g_free(name); @@ -843,29 +843,29 @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, uint32_t msi_pcie_phandle) { char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); name = g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_cell(mc->fdt, name, "#address-cells", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_cell(ms->fdt, name, "#address-cells", FDT_PCI_ADDR_CELLS); - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", + qemu_fdt_setprop_cell(ms->fdt, name, "#interrupt-cells", FDT_PCI_INT_CELLS); - qemu_fdt_setprop_cell(mc->fdt, name, "#size-cells", 0x2); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_setprop_cell(ms->fdt, name, "#size-cells", 0x2); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "pci-host-ecam-generic"); - qemu_fdt_setprop_string(mc->fdt, name, "device_type", "pci"); - qemu_fdt_setprop_cell(mc->fdt, name, "linux,pci-domain", 0); - qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0, + qemu_fdt_setprop_string(ms->fdt, name, "device_type", "pci"); + qemu_fdt_setprop_cell(ms->fdt, name, "linux,pci-domain", 0); + qemu_fdt_setprop_cells(ms->fdt, name, "bus-range", 0, memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); - qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0); + qemu_fdt_setprop(ms->fdt, name, "dma-coherent", NULL, 0); if (s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC) { - qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "msi-parent", msi_pcie_phandle); } - qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0, + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0, memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); - qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges", + qemu_fdt_setprop_sized_cells(ms->fdt, name, "ranges", 1, FDT_PCI_RANGE_IOPORT, 2, 0, 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 1, FDT_PCI_RANGE_MMIO, @@ -875,7 +875,7 @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); - create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle); + create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); g_free(name); } @@ -884,39 +884,39 @@ static void create_fdt_reset(RISCVVirtState *s, const MemMapEntry *memmap, { char *name; uint32_t test_phandle; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); test_phandle = (*phandle)++; name = g_strdup_printf("/soc/test@%lx", (long)memmap[VIRT_TEST].base); - qemu_fdt_add_subnode(mc->fdt, name); + qemu_fdt_add_subnode(ms->fdt, name); { static const char * const compat[3] = { "sifive,test1", "sifive,test0", "syscon" }; - qemu_fdt_setprop_string_array(mc->fdt, name, "compatible", + qemu_fdt_setprop_string_array(ms->fdt, name, "compatible", (char **)&compat, ARRAY_SIZE(compat)); } - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); - qemu_fdt_setprop_cell(mc->fdt, name, "phandle", test_phandle); - test_phandle = qemu_fdt_get_phandle(mc->fdt, name); + qemu_fdt_setprop_cell(ms->fdt, name, "phandle", test_phandle); + test_phandle = qemu_fdt_get_phandle(ms->fdt, name); g_free(name); name = g_strdup_printf("/reboot"); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-reboot"); - qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); - qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); - qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_RESET); + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-reboot"); + qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); + qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_RESET); g_free(name); name = g_strdup_printf("/poweroff"); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "syscon-poweroff"); - qemu_fdt_setprop_cell(mc->fdt, name, "regmap", test_phandle); - qemu_fdt_setprop_cell(mc->fdt, name, "offset", 0x0); - qemu_fdt_setprop_cell(mc->fdt, name, "value", FINISHER_PASS); + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "syscon-poweroff"); + qemu_fdt_setprop_cell(ms->fdt, name, "regmap", test_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "offset", 0x0); + qemu_fdt_setprop_cell(ms->fdt, name, "value", FINISHER_PASS); g_free(name); } @@ -924,24 +924,24 @@ static void create_fdt_uart(RISCVVirtState *s, const MemMapEntry *memmap, uint32_t irq_mmio_phandle) { char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); name = g_strdup_printf("/soc/serial@%lx", (long)memmap[VIRT_UART0].base); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "ns16550a"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "ns16550a"); + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_UART0].base, 0x0, memmap[VIRT_UART0].size); - qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle); + qemu_fdt_setprop_cell(ms->fdt, name, "clock-frequency", 3686400); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); if (s->aia_type == VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", UART0_IRQ); } else { - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4); + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", UART0_IRQ, 0x4); } - qemu_fdt_add_subnode(mc->fdt, "/chosen"); - qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); + qemu_fdt_add_subnode(ms->fdt, "/chosen"); + qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", name); g_free(name); } @@ -949,20 +949,20 @@ static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, uint32_t irq_mmio_phandle) { char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); name = g_strdup_printf("/soc/rtc@%lx", (long)memmap[VIRT_RTC].base); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "google,goldfish-rtc"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", + qemu_fdt_setprop_cells(ms->fdt, name, "reg", 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", + qemu_fdt_setprop_cell(ms->fdt, name, "interrupt-parent", irq_mmio_phandle); if (s->aia_type == VIRT_AIA_TYPE_NONE) { - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); + qemu_fdt_setprop_cell(ms->fdt, name, "interrupts", RTC_IRQ); } else { - qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4); + qemu_fdt_setprop_cells(ms->fdt, name, "interrupts", RTC_IRQ, 0x4); } g_free(name); } @@ -970,68 +970,68 @@ static void create_fdt_rtc(RISCVVirtState *s, const MemMapEntry *memmap, static void create_fdt_flash(RISCVVirtState *s, const MemMapEntry *memmap) { char *name; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; hwaddr flashbase = virt_memmap[VIRT_FLASH].base; name = g_strdup_printf("/flash@%" PRIx64, flashbase); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "cfi-flash"); - qemu_fdt_setprop_sized_cells(mc->fdt, name, "reg", + qemu_fdt_add_subnode(ms->fdt, name); + qemu_fdt_setprop_string(ms->fdt, name, "compatible", "cfi-flash"); + qemu_fdt_setprop_sized_cells(ms->fdt, name, "reg", 2, flashbase, 2, flashsize, 2, flashbase + flashsize, 2, flashsize); - qemu_fdt_setprop_cell(mc->fdt, name, "bank-width", 4); + qemu_fdt_setprop_cell(ms->fdt, name, "bank-width", 4); g_free(name); } static void create_fdt_fw_cfg(RISCVVirtState *s, const MemMapEntry *memmap) { char *nodename; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); hwaddr base = memmap[VIRT_FW_CFG].base; hwaddr size = memmap[VIRT_FW_CFG].size; nodename = g_strdup_printf("/fw-cfg@%" PRIx64, base); - qemu_fdt_add_subnode(mc->fdt, nodename); - qemu_fdt_setprop_string(mc->fdt, nodename, + qemu_fdt_add_subnode(ms->fdt, nodename); + qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "qemu,fw-cfg-mmio"); - qemu_fdt_setprop_sized_cells(mc->fdt, nodename, "reg", + qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); - qemu_fdt_setprop(mc->fdt, nodename, "dma-coherent", NULL, 0); + qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); g_free(nodename); } static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) { - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; uint8_t rng_seed[32]; - if (mc->dtb) { - mc->fdt = load_device_tree(mc->dtb, &s->fdt_size); - if (!mc->fdt) { + if (ms->dtb) { + ms->fdt = load_device_tree(ms->dtb, &s->fdt_size); + if (!ms->fdt) { error_report("load_device_tree() failed"); exit(1); } } else { - mc->fdt = create_device_tree(&s->fdt_size); - if (!mc->fdt) { + ms->fdt = create_device_tree(&s->fdt_size); + if (!ms->fdt) { error_report("create_device_tree() failed"); exit(1); } } - qemu_fdt_setprop_string(mc->fdt, "/", "model", "riscv-virtio,qemu"); - qemu_fdt_setprop_string(mc->fdt, "/", "compatible", "riscv-virtio"); - qemu_fdt_setprop_cell(mc->fdt, "/", "#size-cells", 0x2); - qemu_fdt_setprop_cell(mc->fdt, "/", "#address-cells", 0x2); + qemu_fdt_setprop_string(ms->fdt, "/", "model", "riscv-virtio,qemu"); + qemu_fdt_setprop_string(ms->fdt, "/", "compatible", "riscv-virtio"); + qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); + qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); - qemu_fdt_add_subnode(mc->fdt, "/soc"); - qemu_fdt_setprop(mc->fdt, "/soc", "ranges", NULL, 0); - qemu_fdt_setprop_string(mc->fdt, "/soc", "compatible", "simple-bus"); - qemu_fdt_setprop_cell(mc->fdt, "/soc", "#size-cells", 0x2); - qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); + qemu_fdt_add_subnode(ms->fdt, "/soc"); + qemu_fdt_setprop(ms->fdt, "/soc", "ranges", NULL, 0); + qemu_fdt_setprop_string(ms->fdt, "/soc", "compatible", "simple-bus"); + qemu_fdt_setprop_cell(ms->fdt, "/soc", "#size-cells", 0x2); + qemu_fdt_setprop_cell(ms->fdt, "/soc", "#address-cells", 0x2); create_fdt_sockets(s, memmap, &phandle, &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, @@ -1053,7 +1053,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap) /* Pass seed to RNG */ qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); - qemu_fdt_setprop(mc->fdt, "/chosen", "rng-seed", + qemu_fdt_setprop(ms->fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed)); } @@ -1106,14 +1106,14 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, return dev; } -static FWCfgState *create_fw_cfg(const MachineState *mc) +static FWCfgState *create_fw_cfg(const MachineState *ms) { hwaddr base = virt_memmap[VIRT_FW_CFG].base; FWCfgState *fw_cfg; fw_cfg = fw_cfg_init_mem_wide(base + 8, base, 8, base + 16, &address_space_memory); - fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)mc->smp.cpus); + fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); return fw_cfg; } -- 2.39.1 From MAILER-DAEMON Tue Jan 24 16:22:53 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKQkm-0004Vf-PU for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 16:22:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKQkk-0004U3-3z for qemu-riscv@nongnu.org; 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[200.148.13.157]) by smtp.gmail.com with ESMTPSA id go3-20020a056870da0300b0014474019e50sm1212306oab.24.2023.01.24.13.22.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Jan 2023 13:22:45 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PATCH v4 3/3] hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' Date: Tue, 24 Jan 2023 18:22:34 -0300 Message-Id: <20230124212234.412630-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230124212234.412630-1-dbarboza@ventanamicro.com> References: <20230124212234.412630-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 21:22:50 -0000 Follow the QEMU convention of naming MachineState pointers as 'ms' by renaming the instances where we're calling it 'mc'. Suggested-by: Philippe Mathieu-Daudé Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza --- hw/riscv/spike.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 483581e05f..4cc877bea9 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -56,7 +56,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, uint64_t addr, size; unsigned long clint_addr; int cpu, socket; - MachineState *mc = MACHINE(s); + MachineState *ms = MACHINE(s); uint32_t *clint_cells; uint32_t cpu_phandle, intc_phandle, phandle = 1; char *name, *mem_name, *clint_name, *clust_name; @@ -65,7 +65,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, "sifive,clint0", "riscv,clint0" }; - fdt = mc->fdt = create_device_tree(&fdt_size); + fdt = ms->fdt = create_device_tree(&fdt_size); if (!fdt) { error_report("create_device_tree() failed"); exit(1); @@ -96,7 +96,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); qemu_fdt_add_subnode(fdt, "/cpus/cpu-map"); - for (socket = (riscv_socket_count(mc) - 1); socket >= 0; socket--) { + for (socket = (riscv_socket_count(ms) - 1); socket >= 0; socket--) { clust_name = g_strdup_printf("/cpus/cpu-map/cluster%d", socket); qemu_fdt_add_subnode(fdt, clust_name); @@ -121,7 +121,7 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, qemu_fdt_setprop_cell(fdt, cpu_name, "reg", s->soc[socket].hartid_base + cpu); qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu"); - riscv_socket_fdt_write_id(mc, cpu_name, socket); + riscv_socket_fdt_write_id(ms, cpu_name, socket); qemu_fdt_setprop_cell(fdt, cpu_name, "phandle", cpu_phandle); intc_name = g_strdup_printf("%s/interrupt-controller", cpu_name); @@ -147,14 +147,14 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, g_free(cpu_name); } - addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(mc, socket); - size = riscv_socket_mem_size(mc, socket); + addr = memmap[SPIKE_DRAM].base + riscv_socket_mem_offset(ms, socket); + size = riscv_socket_mem_size(ms, socket); mem_name = g_strdup_printf("/memory@%lx", (long)addr); qemu_fdt_add_subnode(fdt, mem_name); qemu_fdt_setprop_cells(fdt, mem_name, "reg", addr >> 32, addr, size >> 32, size); qemu_fdt_setprop_string(fdt, mem_name, "device_type", "memory"); - riscv_socket_fdt_write_id(mc, mem_name, socket); + riscv_socket_fdt_write_id(ms, mem_name, socket); g_free(mem_name); clint_addr = memmap[SPIKE_CLINT].base + @@ -167,14 +167,14 @@ static void create_fdt(SpikeState *s, const MemMapEntry *memmap, 0x0, clint_addr, 0x0, memmap[SPIKE_CLINT].size); qemu_fdt_setprop(fdt, clint_name, "interrupts-extended", clint_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 4); - riscv_socket_fdt_write_id(mc, clint_name, socket); + riscv_socket_fdt_write_id(ms, clint_name, socket); g_free(clint_name); g_free(clint_cells); g_free(clust_name); } - riscv_socket_fdt_write_distance_matrix(mc); + riscv_socket_fdt_write_distance_matrix(ms); qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", "/htif"); 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[173.198.77.218]) by smtp.gmail.com with ESMTPSA id jl16-20020a170903135000b001869ba04c83sm2114872plb.245.2023.01.24.13.26.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Jan 2023 13:26:35 -0800 (PST) Message-ID: <64af1437-b910-e5b3-c462-0ef0c416ba39@linaro.org> Date: Tue, 24 Jan 2023 11:26:31 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v3 12/14] RISC-V: Add initial support for T-Head C906 Content-Language: en-US To: Christoph Muellner , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=c3=bcbner?= , Palmer Dabbelt , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu References: <20230124195945.181842-1-christoph.muellner@vrull.eu> <20230124195945.181842-13-christoph.muellner@vrull.eu> From: Richard Henderson In-Reply-To: <20230124195945.181842-13-christoph.muellner@vrull.eu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.148, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 21:26:39 -0000 On 1/24/23 09:59, Christoph Muellner wrote: > +++ b/target/riscv/cpu.h > @@ -27,6 +27,7 @@ > #include "qom/object.h" > #include "qemu/int128.h" > #include "cpu_bits.h" > +#include "cpu_vendorid.h" I don't see that this ID is required for all users of riscv/cpu.h. This include should be limited to cpu.c. r~ From MAILER-DAEMON Tue Jan 24 16:47:26 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKR8Y-0003yA-Am for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 16:47:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKR8E-0003wq-5u for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 16:47:24 -0500 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKR8B-0003WW-Mi for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 16:47:05 -0500 Received: by mail-pg1-x529.google.com with SMTP id g68so12192584pgc.11 for ; Tue, 24 Jan 2023 13:47:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=vZbBMAJHV9ndC14OdFP77XoK2HSlmIdxWS4+suYgqAw=; b=e+TI4FA8MYad0BmBtmOnXWM/K4+StGRNeuOYFFlfDkGSJoarYQjYH2FBEBy9wvfkRo bBz/tExKW3ZUiXbW+PJz9gG87GdODFCw2Cn1W8LQ88voj+Kqb5EHeGUo0PbcINRrNYrq vyx056i0Z+6fhB8VB4OH222RGH7Zh46bhkng59xR4kGQlZOHImZ9woFB0MReVnTWYyqF JOcYc1uqM9FyuHd5Jt0feOZiQb9YkV080mZ4En/hkvHlSQk5w9Ge4vV0L+7tQnFFhmmo gNLncG4Yvi2S5e0+6oX9J+v8yUkE3VUkEh56eMJ82iJgBSy6wI/Q6BCx6ENNbFmfnhec lYeg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=vZbBMAJHV9ndC14OdFP77XoK2HSlmIdxWS4+suYgqAw=; b=ETPe0KjcN0aWSSAKiQ1nq97vwEkJXt1kPMVUjNCqamY5tlw3V0TTM9phengzcuyAnT CbztFMHCujGPyKM5nge2K41QL30eRh97SqB5uZq3dbK+tVTi4279K1vP/OLiqoO7B5jm 7J6olrEsXjgSD+kIeJDu/1tAveHZ7zLICZmMV4sv6LED59/AmmKvJcatmBLL7m2KCS5K FirgOhauuEHnzXo8n6L0AKP9RwzDNfXLXHaLl/Kd9c0ZKj+QKLv17d/+2S7+MMdopb+B 0qMkP3y+a6WlKmZpb+sZfh0U1xwbWZaI5rNtwyfV5aormtxjnLGaeDBuSNiGwP7Ympn/ UsDQ== X-Gm-Message-State: AFqh2koBVPzaNTyOW8w11Gfhi6BcfijpKBRxXoQT0k4P7ZY2dZL9M0kE BsOw6I108XqtE/exUqwrsDIHJg== X-Google-Smtp-Source: AMrXdXsEfwmJQFdNVNuPKmX0ieDvjodkkR2E1ubozBD62aaszG2OR1paX7aTXSIOPFxw9g8KK3Yn4g== X-Received: by 2002:a62:640f:0:b0:581:f301:23fc with SMTP id y15-20020a62640f000000b00581f30123fcmr44370061pfb.12.1674596821109; Tue, 24 Jan 2023 13:47:01 -0800 (PST) Received: from [192.168.5.146] (rrcs-173-198-77-218.west.biz.rr.com. [173.198.77.218]) by smtp.gmail.com with ESMTPSA id z11-20020aa785cb000000b00582579cb0e0sm2068154pfn.129.2023.01.24.13.46.58 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Jan 2023 13:47:00 -0800 (PST) Message-ID: <9edfb063-eb7e-7b89-779b-e786e7adbd49@linaro.org> Date: Tue, 24 Jan 2023 11:46:56 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v4 00/36] tcg: Support for Int128 with helpers Content-Language: en-US To: Mark Cave-Ayland , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net References: <20230108023719.2466341-1-richard.henderson@linaro.org> <73231653-7149-6376-633c-c4f61e576c5b@ilande.co.uk> From: Richard Henderson In-Reply-To: <73231653-7149-6376-633c-c4f61e576c5b@ilande.co.uk> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.148, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 21:47:25 -0000 On 1/10/23 13:12, Mark Cave-Ayland wrote: > Now that the TCG documentation is more visible, would it be possible to add a patch to > update the relevant parts of docs/devel/tcg-ops.rst to reflect the new Int128 support? For avoidance of doubt, this document covers the intermediate representation and some backend specifics. There are no changes to either of these at this time. The TCGv_i128 type is lowered to TCG_TYPE_REG (either I32 or I64 per host) during translation of guest instructions to intermediate opcodes. Not to say another document shouldn't be written covering the translation interface... r~ From MAILER-DAEMON Tue Jan 24 16:54:28 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKRFM-0005Hi-MS for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 16:54:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKRFK-0005Gb-RH for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 16:54:26 -0500 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKRFI-00054h-Ha for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 16:54:26 -0500 Received: by mail-pj1-x102d.google.com with SMTP id h5-20020a17090a9c0500b0022bb85eb35dso52429pjp.3 for ; Tue, 24 Jan 2023 13:54:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:references:cc:to:from :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=33I3gmOMrqXDAgIkPqkp+uQ5domRkC5NGptWhMIhogg=; b=U5wHs2p3QtL3fW7wbrxQmXxNAqb4wBp2iWS60BzdogxkZJBB2UYiLDWU3OL4X4EywO tngiXdj/DHWAMZIiAdvDAuFmyjscdAwn7ya1ItxKVR0Ki2UvBK0ReEIszPW6jZWopIxW +Bp3fS9gKWLrhsxpyVQAu4KrrcilQqWGmfwU1/fYLT9dTdNw1ZBliCbOC0tdcobXc7oI ZGSKudJs6mw6LACWb+qWhisJHSj3W8DNuvIZ+gVrgizgKIgIoyEPJOh0U1pilQFOI3Pn +Bmq8dArqt23Rqt0/QC0/qQ+VGFyFViFLr2VYPgoCeklFIqZxd+dIijie8TtXp26RvQc 4AQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:references:cc:to:from :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=33I3gmOMrqXDAgIkPqkp+uQ5domRkC5NGptWhMIhogg=; b=SQ6hAtVzE45E/wIISTTjWgdewI1oBIW+w83pQTEBYjD4jrLPFUzQd606Uxko1nSqtT t2PiwOceYI6hnsJ5FVkJedmvmGpHSAufiu0zNt2UitLGkO/A3CruyTYZak2Zgwp7jn2m eHwGfe2xFfUkbHCzSMGy1IlF8jzSFL+78O7MSsiqScLYDrOJqF85491zUP0N1wQpWvGP OpbLMPrlJ1rLYIhIL5rSlKEdiWaw6eyaq4CYtK55irinmc/njZE1SLzWTfDvoItmeA+L ba9CKS0jocWhfK5rLqqhjXt2xs+QT0RP3kpAiY3Bqs+sqA9iP1swIDRFl6MzzZ3LNmaT D6fw== X-Gm-Message-State: AO0yUKX1iP5rVrC3bbw/5js7789t+SLDPvLx36I/gRYYV4N4kKgZi+vZ ADENEoJwQd9K77wvuZr4GuHggw== X-Google-Smtp-Source: AK7set90rRdU2o7QMLyGc0kQ4H+BIf4JTmjvmC7Bw/tjOEeqCT38lwBRR10aWc21bDf3z9d83PK5Sg== X-Received: by 2002:a17:903:1107:b0:196:191b:6b22 with SMTP id n7-20020a170903110700b00196191b6b22mr3760694plh.59.1674597262967; Tue, 24 Jan 2023 13:54:22 -0800 (PST) Received: from [192.168.5.146] (rrcs-173-198-77-218.west.biz.rr.com. [173.198.77.218]) by smtp.gmail.com with ESMTPSA id z2-20020aa791c2000000b0058a7bacd31fsm2083427pfa.32.2023.01.24.13.54.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Jan 2023 13:54:22 -0800 (PST) Message-ID: <4068c032-2210-65c7-3f5c-04f89b778e04@linaro.org> Date: Tue, 24 Jan 2023 11:54:18 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v4 00/36] tcg: Support for Int128 with helpers Content-Language: en-US From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net References: <20230108023719.2466341-1-richard.henderson@linaro.org> In-Reply-To: <20230108023719.2466341-1-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.148, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 21:54:27 -0000 On 1/7/23 16:36, Richard Henderson wrote: > Patches requiring review: > 01-tcg-Define-TCG_TYPE_I128-and-related-helper-macro.patch > 02-tcg-Handle-dh_typecode_i128-with-TCG_CALL_-RET-AR.patch > 03-tcg-Allocate-objects-contiguously-in-temp_allocat.patch > 05-tcg-Add-TCG_CALL_-RET-ARG-_BY_REF.patch > 07-tcg-Add-TCG_CALL_RET_BY_VEC.patch > 08-include-qemu-int128-Use-Int128-structure-for-TCI.patch > 09-tcg-i386-Add-TCG_TARGET_CALL_-RET-ARG-_I128.patch > 10-tcg-tci-Fix-big-endian-return-register-ordering.patch > 11-tcg-tci-Add-TCG_TARGET_CALL_-RET-ARG-_I128.patch > 13-tcg-Add-temp-allocation-for-TCGv_i128.patch > 14-tcg-Add-basic-data-movement-for-TCGv_i128.patch > 15-tcg-Add-guest-load-store-primitives-for-TCGv_i128.patch > 16-tcg-Add-tcg_gen_-non-atomic_cmpxchg_i128.patch > 17-tcg-Split-out-tcg_gen_nonatomic_cmpxchg_i-32-64.patch > 24-target-s390x-Use-a-single-return-for-helper_divs3.patch > 31-target-s390x-Use-Int128-for-passing-float128.patch > 32-target-s390x-Use-tcg_gen_atomic_cmpxchg_i128-for-.patch > 33-target-s390x-Implement-CC_OP_NZ-in-gen_op_calc_cc.patch > 34-target-i386-Split-out-gen_cmpxchg8b-gen_cmpxchg16.patch > 35-target-i386-Inline-cmpxchg8b.patch > 36-target-i386-Inline-cmpxchg16b.patch Ping. Only 2, 3, 10, 14 reviewed in the past 2 weeks. There is a very minor patch conflict now in patch 4, nothing worth re-posting over. r~ From MAILER-DAEMON Tue Jan 24 18:44:32 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKSxs-0006fj-Lb for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 18:44:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKSxr-0006el-1H for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 18:44:31 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKSxo-0003Ps-5X for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 18:44:30 -0500 Received: by mail-wr1-x42a.google.com with SMTP id bk16so15431326wrb.11 for ; Tue, 24 Jan 2023 15:44:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:content-language :references:cc:to:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; 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Tue, 24 Jan 2023 15:44:26 -0800 (PST) Received: from [192.168.0.114] ([196.89.153.183]) by smtp.gmail.com with ESMTPSA id q3-20020adff943000000b002bfae43109fsm2793612wrr.93.2023.01.24.15.44.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Jan 2023 15:44:26 -0800 (PST) Message-ID: <4add4fd6-3996-8e5a-e75d-3eb262a251ed@linaro.org> Date: Wed, 25 Jan 2023 00:44:24 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v4 01/36] tcg: Define TCG_TYPE_I128 and related helper macros To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net References: <20230108023719.2466341-1-richard.henderson@linaro.org> <20230108023719.2466341-2-richard.henderson@linaro.org> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230108023719.2466341-2-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.148, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 23:44:31 -0000 On 8/1/23 03:36, Richard Henderson wrote: > Begin staging in support for TCGv_i128 with Int128. > Define the type enumerator, the typedef, and the > helper-head.h macros. > > This cannot yet be used, because you can't allocate > temporaries of this new type. > > Signed-off-by: Richard Henderson > --- > include/exec/helper-head.h | 7 +++++++ > include/tcg/tcg.h | 17 ++++++++++------- > 2 files changed, 17 insertions(+), 7 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Tue Jan 24 18:59:42 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKTCY-0000FP-Ev for mharc-qemu-riscv@gnu.org; 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Tue, 24 Jan 2023 15:59:37 -0800 (PST) Message-ID: <32faa412-7b03-2f91-fde6-024be8276488@linaro.org> Date: Wed, 25 Jan 2023 00:59:27 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v4 08/36] include/qemu/int128: Use Int128 structure for TCI Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net References: <20230108023719.2466341-1-richard.henderson@linaro.org> <20230108023719.2466341-9-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230108023719.2466341-9-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.148, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jan 2023 23:59:40 -0000 On 8/1/23 03:36, Richard Henderson wrote: > We are about to allow passing Int128 to/from tcg helper functions, > but libffi doesn't support __int128_t, so use the structure. > > In order for atomic128.h to continue working, we must provide > a mechanism to frob between real __int128_t and the structure. > Provide a new union, Int128Alias, for this. We cannot modify > Int128 itself, as any changed alignment would also break libffi. > > Signed-off-by: Richard Henderson > --- > include/qemu/atomic128.h | 29 +++++++++++++++++++++------ > include/qemu/int128.h | 25 +++++++++++++++++++++--- > util/int128.c | 42 ++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 87 insertions(+), 9 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Tue Jan 24 19:13:43 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKTQ6-0003Q2-Uf for mharc-qemu-riscv@gnu.org; Tue, 24 Jan 2023 19:13:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKTQ5-0003PP-RV for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 19:13:41 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKTQ3-0002Z9-0t for qemu-riscv@nongnu.org; Tue, 24 Jan 2023 19:13:41 -0500 Received: by mail-wm1-x32d.google.com with SMTP id q8so12635842wmo.5 for ; Tue, 24 Jan 2023 16:13:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=IAanV1cmzpvJ/BO7ybZI1dsSXlZ2W2XaMUYjkULGVBs=; b=M8O09S39o0BdB2IT7y6xIXtqPhWOWkVzWbwIqPP7hgQ5QQ9xPgvhY80qgwnFjDp8Jx FPi4e3NqWmW7+WMqJqExMirrf7j4/1/hsjNSyxJHFDQWmNvV3psRaSfY4VA06wSPVXa8 K8kMguUrPTbluO8t4/vTuz/gol0cAC+nhlfGsTp5CqAl2iS7nCkXzJ5rCfrmBYVjD5HI 0sP6qHFBP7eQW0eVglRumz/Jfxg/oMvkgMQvWQvyfbdzoED8c5BlB699eryjmw/PpLtZ oGAvJ5EmpA7V1ze/K9J4hWV4yl8CEuSMZCxVk56m9DgQBRtO16wHKcQRLbmApjIoa3iB FKMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=IAanV1cmzpvJ/BO7ybZI1dsSXlZ2W2XaMUYjkULGVBs=; b=DCXEfQrPC6fpBNFSZjJdcQKSbsyULa5aM18qEYOWNyTZILvRTBHAn0dyhait4OnfbG JCZGnJktvHJyTMEWNqvxKEnaWosD2+MHMaEE//VxsVu6HCmDfCMzTPPICgf2vwKIO/wE x+zeh4JP8VbeKsk/tOh1splpg6isc9L5lsmGObMH23KRqbOfhUAlRFcpFffw4kMzyMRM 9fYNUIW/BP29ix6Nk6MLEJ9vtrzqiD0hFGLE7a6QdsUlGKs6D1RqIzknVC9NcXBdFHD5 TG+BEuykGSOCXyRSxMEQ2V+hW/hoVi8Wfei/2gm4nIy/MA1I16VD8PuATGr2HNaxpzeW 1D0w== X-Gm-Message-State: AFqh2krWk0QG0EZ1/9oucyUxfQqAjgFGe81GZe7zeWoS705Bg5fEQVay eP5R74YMqHCoBPYi6TKuTQum8Q== X-Google-Smtp-Source: AMrXdXvmPQ3nNpR5V9uLmWg69b97JjUGFKiN69alS1w1hhkRi4Lotxsfo8+hBN5cYn6cpyOPUTiEOw== X-Received: by 2002:a05:600c:5488:b0:3da:1e3e:1ce8 with SMTP id iv8-20020a05600c548800b003da1e3e1ce8mr29468908wmb.13.1674605617245; Tue, 24 Jan 2023 16:13:37 -0800 (PST) Received: from [192.168.0.114] ([196.89.153.183]) by smtp.gmail.com with ESMTPSA id p10-20020a05600c430a00b003dc0d5b4f75sm189261wme.43.2023.01.24.16.13.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Jan 2023 16:13:36 -0800 (PST) Message-ID: Date: Wed, 25 Jan 2023 01:13:34 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v4 13/36] tcg: Add temp allocation for TCGv_i128 Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net References: <20230108023719.2466341-1-richard.henderson@linaro.org> <20230108023719.2466341-14-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230108023719.2466341-14-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.148, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 00:13:42 -0000 On 8/1/23 03:36, Richard Henderson wrote: > This enables allocation of i128. The type is not yet > usable, as we have not yet added data movement ops. > > Signed-off-by: Richard Henderson > --- > include/tcg/tcg.h | 32 +++++++++++++++++++++++++ > tcg/tcg.c | 60 +++++++++++++++++++++++++++++++++-------------- > 2 files changed, 74 insertions(+), 18 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Wed Jan 25 03:32:13 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKbCV-0005Yz-FI for mharc-qemu-riscv@gnu.org; Wed, 25 Jan 2023 03:32:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKbCR-0005Xn-5c for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 03:32:07 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKbCP-0005wx-Du for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 03:32:06 -0500 Received: by mail-wm1-x334.google.com with SMTP id m15so13139458wms.4 for ; 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Wed, 25 Jan 2023 00:32:03 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id p23-20020a1c5457000000b003da286f8332sm983539wmi.18.2023.01.25.00.32.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 00:32:03 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A75F81FFB7; Wed, 25 Jan 2023 08:32:02 +0000 (GMT) References: <20230108023719.2466341-1-richard.henderson@linaro.org> <20230108023719.2466341-5-richard.henderson@linaro.org> User-agent: mu4e 1.9.16; emacs 29.0.60 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Daniel Henrique Barboza , qemu-arm@nongnu.org Subject: Re: [PATCH v4 04/36] tcg: Introduce tcg_out_addi_ptr Date: Wed, 25 Jan 2023 08:31:57 +0000 In-reply-to: <20230108023719.2466341-5-richard.henderson@linaro.org> Message-ID: <87wn5bqakd.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 08:32:07 -0000 Richard Henderson writes: > Implement the function for arm, i386, and s390x, which will use it. > Add stubs for all other backends. > > Reviewed-by: Daniel Henrique Barboza > Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro From MAILER-DAEMON Wed Jan 25 03:41:20 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKbLJ-0007Qq-Mp for mharc-qemu-riscv@gnu.org; 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[2.7.42.160]) by smtp.gmail.com with ESMTPSA id x6-20020a5d4906000000b002bc6c180738sm4358952wrq.90.2023.01.25.00.41.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 00:41:11 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v7 0/5] riscv: Allow user to set the satp mode Date: Wed, 25 Jan 2023 09:41:02 +0100 Message-Id: <20230125084107.1580972-1-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x42b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 08:41:16 -0000 This introduces new properties to allow the user to set the satp mode, see patch 3 for full syntax. In addition, it prevents cpus to boot in a satp mode they do not support (see patch 5). v7: - Expand map to contain all valid modes, Andrew - Fix commit log for patch 3, Andrew - Remove is_32_bit argument from set_satp_mode_default, Andrew - Move and fixed comment, Andrew - Fix satp_mode_map_max in riscv_cpu_satp_mode_finalize which was set too early, Alex - Remove is_32_bit argument from set_satp_mode_max_supported, Andrew - Use satp_mode directly instead of a string in set_satp_mode_max_supported, Andrew - Swap the patch introducing supported bitmap and the patch that sets sv57 in the dt, Andrew - Add various RB from Andrew and Alistair, thanks v6: - Remove the valid_vm check in validate_vm and add it to the finalize function so that map already contains the constraint, Alex - Add forgotten mbare to satp_mode_from_str, Alex - Move satp mode properties handling to riscv_cpu_satp_mode_finalize, Andrew - Only add satp mode properties corresponding to the cpu, and then remove the check against valid_vm_1_10_32/64 in riscv_cpu_satp_mode_finalize, Andrew/Alistair/Alex - Move mmu-type setting to its own patch, Andrew - patch 5 is new and is a fix, Alex v5: - Simplify v4 implementation by leveraging valid_vm_1_10_32/64, as suggested by Andrew - Split the v4 patch into 2 patches as suggested by Andrew - Lot of other minor corrections, from Andrew - Set the satp mode N by disabling the satp mode N + 1 - Add a helper to set satp mode from a string, as suggested by Frank v4: - Use custom boolean properties instead of OnOffAuto properties, based on ARMVQMap, as suggested by Andrew v3: - Free sv_name as pointed by Bin - Replace satp-mode with boolean properties as suggested by Andrew - Removed RB from Atish as the patch considerably changed v2: - Use error_setg + return as suggested by Alistair - Add RB from Atish - Fixed checkpatch issues missed in v1 - Replaced Ludovic email address with the rivos one Alexandre Ghiti (5): riscv: Pass Object to register_cpu_props instead of DeviceState riscv: Change type of valid_vm_1_10_[32|64] to bool riscv: Allow user to set the satp mode riscv: Introduce satp mode hw capabilities riscv: Correctly set the device-tree entry 'mmu-type' hw/riscv/virt.c | 19 ++-- target/riscv/cpu.c | 248 +++++++++++++++++++++++++++++++++++++++++++-- target/riscv/cpu.h | 23 +++++ target/riscv/csr.c | 29 +++--- 4 files changed, 288 insertions(+), 31 deletions(-) -- 2.37.2 From MAILER-DAEMON Wed Jan 25 03:42:18 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKbMI-0007pa-QP for mharc-qemu-riscv@gnu.org; Wed, 25 Jan 2023 03:42:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKbMG-0007ol-VO for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 03:42:16 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKbME-0007QN-PZ for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 03:42:16 -0500 Received: by mail-wr1-x433.google.com with SMTP id m7so2596512wru.8 for ; Wed, 25 Jan 2023 00:42:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cwmWUou3n7EK2dJeuj7/aaDxziEUHfXgfhDPpUIodg0=; b=WpL9rvglxaPJswbSjl+3hVNq/kFYhxjifUM9Ob7HJnPn44ZYY8X53kpuVkvdyBz9Rr hLwUupIAy7G/JYeO/Hbk1XcZXonFtqRWNmQENa1CzUguuVnvjeiXkCqN7YLqE/xd1UjT GCNjbuvpYkZPiUFfZQG6yfb65mY9ZYzzG2bQV/OLHaMBC2lfmSva7hg/hLktnR3/j2fe AK2Ky2IFPyBZz9jAbEKSmdOvu9JyB5PiqpJe7wrStb2qXOIGZJwEZafKqDU2X4tLqIiU BIZVsTYzDupDfl/BK1I1LR4Ee3J2Phrvfch69vKmDgrxR4hXomowtt57vFtyhgK/HJG3 SiqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cwmWUou3n7EK2dJeuj7/aaDxziEUHfXgfhDPpUIodg0=; b=Cy9687SNN9jCNOGDjHY/+SCJaXfPJNi7+OvrUlR341p0kxcUe51WD4zxQAiq4NMSIK S8YGv0iILAExirp5Y9nQbyc8GFtAkjDRUxFIe+HusJwdsVsA1in7VQi+3s1fli2u0MvL WFw6LjoOkS+a1nzg2mQg+hyy0DsqJ565YMMgc8K6AzJCjdAHVtS45f8IxgfnAv38yZpH xY20rlRqGRoxozhU+CibVSmjuiqWisbY1eC6LiIejSkS6aPkzShB/br3YMvDY/ReoUPW puiQNNqOMFefy213kLmbmsjour0ugF+EIAQpA41MExQETgCsbo01gckJSODjG7zZjCSR MDbg== X-Gm-Message-State: AO0yUKVj0QSKarrQmC/VTDM7lw4wEAGyHNIK/J4M+8Z4IUnVTFS231Uz HvZ3FVh+DxOP05/mSUtIoMABGw== X-Google-Smtp-Source: AK7set/F+bJPoWvq+YGQie12Nf1t3royEghLt6hYxMUUxx43b8XbzIBllSNNcA2OeN/X+GqwuX6nzQ== X-Received: by 2002:a05:6000:257:b0:2bf:bb48:ddaf with SMTP id m23-20020a056000025700b002bfbb48ddafmr834899wrz.7.1674636133233; Wed, 25 Jan 2023 00:42:13 -0800 (PST) Received: from alex-rivos.home (lfbn-lyo-1-450-160.w2-7.abo.wanadoo.fr. [2.7.42.160]) by smtp.gmail.com with ESMTPSA id w14-20020a5d608e000000b002bc84c55758sm4609145wrt.63.2023.01.25.00.42.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 00:42:12 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v7 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState Date: Wed, 25 Jan 2023 09:41:03 +0100 Message-Id: <20230125084107.1580972-2-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230125084107.1580972-1-alexghiti@rivosinc.com> References: <20230125084107.1580972-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 08:42:17 -0000 One can extract the DeviceState pointer from the Object pointer, so pass the Object for future commits to access other fields of Object. No functional changes intended. Signed-off-by: Alexandre Ghiti Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cc75ca7667..7181b34f86 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -200,7 +200,7 @@ static const char * const riscv_intr_names[] = { "reserved" }; -static void register_cpu_props(DeviceState *dev); +static void register_cpu_props(Object *obj); const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { @@ -238,7 +238,7 @@ static void riscv_any_cpu_init(Object *obj) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif set_priv_version(env, PRIV_VERSION_1_12_0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); } #if defined(TARGET_RISCV64) @@ -247,7 +247,7 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -280,7 +280,7 @@ static void rv128_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -290,7 +290,7 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -343,7 +343,7 @@ static void riscv_host_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, 0); #endif - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); } #endif @@ -1083,9 +1083,10 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_END_OF_LIST(), }; -static void register_cpu_props(DeviceState *dev) +static void register_cpu_props(Object *obj) { Property *prop; + DeviceState *dev = DEVICE(obj); for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); -- 2.37.2 From MAILER-DAEMON Wed Jan 25 03:43:20 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKbNI-0000f1-6o for mharc-qemu-riscv@gnu.org; Wed, 25 Jan 2023 03:43:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKbNF-0000eI-3P for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 03:43:17 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKbND-0007bn-I8 for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 03:43:16 -0500 Received: by mail-wr1-x42d.google.com with SMTP id bk16so16244281wrb.11 for ; Wed, 25 Jan 2023 00:43:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+TrQUDShuSlYfHT4YnhyHx3S9WBzIjkLW6v+vF/2lyw=; b=8R8nHv1V9HmeyRvkLYOz7Z1J45Ddw22pteExu33h0koeI9zCq3p8DqaqXl2yapLjmg 7pRUe0+YqAWByDSBGW0x9Nk72aKZwFvkoDQVNR8xidwYTifRFvwxpCqR4PLoZeSGPijg Z4NTSfl5urKLdMp/uVtGcruqM7jLVU/svfqezBd2vkiNeNg52l/LlbaEv17gJlJwNRVd tP6nZOQQWQqxS/bXx/g1XP9CQNC42DBS/pnXtpJP8QTFzoi+vscpQmLIoMAGzGHQiNhK U1P9Qd+bmtmQWxyvbxrb5Kn6SBA9YYxv5BanCPXNsxD+BD7ALSEG+PQbT/X5uxGH2Fca JbVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+TrQUDShuSlYfHT4YnhyHx3S9WBzIjkLW6v+vF/2lyw=; b=0PuexdX/XP5fbPAmSGIL/01d45VJJCl2Douu/s+qqggPt3A1HPvozJWfQ+63bmaLYe ujCztS/KaRdOeaNjYnsfrfZ+/IYW4ylf/D+Q8XSqpT3XFdNHt+HLVzCFmoKodM09g+wl lKX4VstKzq01/aul7BlKqJXnVl259GIk4FaivHCGPwJi5dmOxtyTNHxfgzPprXD8bANo RDmxmmnlFNCa9L1xW5hWv4M0MKbkcHXsSklX9okdpH2kgCubLjJC1prbHCL/EqXFmmau vyDfkItIYbxIbOyGeKIYc7Q06S7sUXfz18g0Kd8ZiV51UdbKOtrZweqLA8RUFzsDaXGb inYQ== X-Gm-Message-State: AFqh2kpBdN1jWjeF8mNGp5D64HZKxxFzq6jNqgdwEUrwDcCldTfy5Ucc rCzfuYnollF2xtapzDngIH1cHw== X-Google-Smtp-Source: AMrXdXud3UfGnFAFnf/YYiPjD1LXALQ4hLzEvqlmsCQaKviyKF25Mqoy8ZEt7oOHGIfvB5h1fQyNzQ== X-Received: by 2002:a05:6000:1f81:b0:2bd:f444:9677 with SMTP id bw1-20020a0560001f8100b002bdf4449677mr28128780wrb.66.1674636194042; Wed, 25 Jan 2023 00:43:14 -0800 (PST) Received: from alex-rivos.home (lfbn-lyo-1-450-160.w2-7.abo.wanadoo.fr. [2.7.42.160]) by smtp.gmail.com with ESMTPSA id x6-20020a5d4906000000b002bc6c180738sm4363839wrq.90.2023.01.25.00.43.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 00:43:13 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v7 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool Date: Wed, 25 Jan 2023 09:41:04 +0100 Message-Id: <20230125084107.1580972-3-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230125084107.1580972-1-alexghiti@rivosinc.com> References: <20230125084107.1580972-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x42d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 08:43:17 -0000 This array is actually used as a boolean so swap its current char type to a boolean and at the same time, change the type of validate_vm to bool since it returns valid_vm_1_10_[32|64]. Suggested-by: Andrew Jones Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/csr.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0db2c233e5..6b157806a5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1117,16 +1117,16 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; static const target_ulong vsip_writable_mask = MIP_VSSIP; -static const char valid_vm_1_10_32[16] = { - [VM_1_10_MBARE] = 1, - [VM_1_10_SV32] = 1 +static const bool valid_vm_1_10_32[16] = { + [VM_1_10_MBARE] = true, + [VM_1_10_SV32] = true }; -static const char valid_vm_1_10_64[16] = { - [VM_1_10_MBARE] = 1, - [VM_1_10_SV39] = 1, - [VM_1_10_SV48] = 1, - [VM_1_10_SV57] = 1 +static const bool valid_vm_1_10_64[16] = { + [VM_1_10_MBARE] = true, + [VM_1_10_SV39] = true, + [VM_1_10_SV48] = true, + [VM_1_10_SV57] = true }; /* Machine Information Registers */ @@ -1209,7 +1209,7 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static int validate_vm(CPURISCVState *env, target_ulong vm) +static bool validate_vm(CPURISCVState *env, target_ulong vm) { if (riscv_cpu_mxl(env) == MXL_RV32) { return valid_vm_1_10_32[vm & 0xf]; @@ -2648,7 +2648,8 @@ static RISCVException read_satp(CPURISCVState *env, int csrno, static RISCVException write_satp(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong vm, mask; + target_ulong mask; + bool vm; if (!riscv_feature(env, RISCV_FEATURE_MMU)) { return RISCV_EXCP_NONE; -- 2.37.2 From MAILER-DAEMON Wed Jan 25 03:44:24 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKbOJ-0001Qd-PT for mharc-qemu-riscv@gnu.org; Wed, 25 Jan 2023 03:44:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKbOG-0001OO-FD for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 03:44:20 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKbOD-0007iO-OB for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 03:44:19 -0500 Received: by mail-wr1-x435.google.com with SMTP id b7so16275418wrt.3 for ; Wed, 25 Jan 2023 00:44:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6QAs4M/qcXVtPbdoNDbH0G/oO1ltrtInKZG8GbtYJvI=; b=HVPnIBEQQ/nTjrj3D5+nVXv6Cbv2/N1RRrTRakrU3v4g9WOvH26LwEDvI5HsAUnp7Z yp/UVOUnaUlNl5t1AURgx+zPjISmlmw21ZxAImza/x9+HUM45cxDDLUdg5vEwt82fg4U jyiHKnHmRxg+kjEblwDusUzWqa7INRSz/nqsHDNADMSDXMu92b1k5pJ1LEnXGceABKPM fgaOCOGzMvva3EeISwQlQmniQ8XzU9/RuKelP+Pz3XnHCOorcxXE6PDtLaO8wWgXL3Ko X92GET6t1Tpp95JqL2bN/5OHTJ+1TGZ7DTpLl2pIGZjpfyXYlmpsZy8tEkJSG2AZxAfE L6Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6QAs4M/qcXVtPbdoNDbH0G/oO1ltrtInKZG8GbtYJvI=; b=4TZmK7dSRw++P793FgdWmPzL1e3P9fZ2ORidR7zVG9XraGphaqsAPU1pTJs6WnFeFi 8g65rAUyxIP4D65wuJcuby3wHtuYRVn5CjwPl3ouwKBDdEID5gN16HP2RVm1cN7Hj7bo BYNrDiEC6qxsaUxK1qRvF++p/na6u4tHze3ajDlF+Vv+5pX/7an5OuD3XjJxzvvn4iSu 8CE+xBvpUJJ+DD9AdNfmgVTgHm0AkM7Psrt4NKLM998Ok+v+FofWernwr80lVDkDVFEO 9bB/V+k6CD5aeB60H4h/l2Udr44vhcbjgwtV5I6X8H9D13iB1jLW1qEdjqtWsMdi1VTz Z8ZA== X-Gm-Message-State: AFqh2kqfXax/S8qewq0aga7fTKwP3YmnU6SD/P3giaIk+AySz5cY2YTp zVlV9/c38vhbCQvjfQ5NPx1Usw== X-Google-Smtp-Source: AMrXdXuVJSs2flQ7w8pGYIC54Iv+KmKAVeAmWoZOMqFIeli8fCDaGxWjudBV5zsKnvVhkLeciIHdYg== X-Received: by 2002:a05:6000:a06:b0:2bc:858a:3df0 with SMTP id co6-20020a0560000a0600b002bc858a3df0mr32641392wrb.48.1674636254954; Wed, 25 Jan 2023 00:44:14 -0800 (PST) Received: from alex-rivos.home (lfbn-lyo-1-450-160.w2-7.abo.wanadoo.fr. [2.7.42.160]) by smtp.gmail.com with ESMTPSA id e14-20020adfa44e000000b002be15ee1377sm3906440wra.22.2023.01.25.00.44.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 00:44:14 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Ludovic Henry Subject: [PATCH v7 3/5] riscv: Allow user to set the satp mode Date: Wed, 25 Jan 2023 09:41:05 +0100 Message-Id: <20230125084107.1580972-4-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230125084107.1580972-1-alexghiti@rivosinc.com> References: <20230125084107.1580972-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 08:44:20 -0000 RISC-V specifies multiple sizes for addressable memory and Linux probes for the machine's support at startup via the satp CSR register (done in csr.c:validate_vm). As per the specification, sv64 must support sv57, which in turn must support sv48...etc. So we can restrict machine support by simply setting the "highest" supported mode and the bare mode is always supported. You can set the satp mode using the new properties "sv32", "sv39", "sv48", "sv57" and "sv64" as follows: -cpu rv64,sv57=on # Linux will boot using sv57 scheme -cpu rv64,sv39=on # Linux will boot using sv39 scheme -cpu rv64,sv57=off # Linux will boot using sv48 scheme -cpu rv64 # Linux will boot using sv57 scheme by default We take the highest level set by the user: -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme We make sure that invalid configurations are rejected: -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are # enabled We accept "redundant" configurations: -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme And contradictory configurations: -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme Co-Developed-by: Ludovic Henry Signed-off-by: Ludovic Henry Signed-off-by: Alexandre Ghiti --- target/riscv/cpu.c | 207 +++++++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 19 +++++ target/riscv/csr.c | 12 ++- 3 files changed, 231 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7181b34f86..87153a0219 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -27,6 +27,7 @@ #include "time_helper.h" #include "exec/exec-all.h" #include "qapi/error.h" +#include "qapi/visitor.h" #include "qemu/error-report.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" @@ -229,6 +230,81 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) env->vext_ver = vext_ver; } +static uint8_t satp_mode_from_str(const char *satp_mode_str) +{ + if (!strncmp(satp_mode_str, "mbare", 5)) { + return VM_1_10_MBARE; + } + + if (!strncmp(satp_mode_str, "sv32", 4)) { + return VM_1_10_SV32; + } + + if (!strncmp(satp_mode_str, "sv39", 4)) { + return VM_1_10_SV39; + } + + if (!strncmp(satp_mode_str, "sv48", 4)) { + return VM_1_10_SV48; + } + + if (!strncmp(satp_mode_str, "sv57", 4)) { + return VM_1_10_SV57; + } + + if (!strncmp(satp_mode_str, "sv64", 4)) { + return VM_1_10_SV64; + } + + g_assert_not_reached(); +} + +uint8_t satp_mode_max_from_map(uint32_t map) +{ + /* map here has at least one bit set, so no problem with clz */ + return 31 - __builtin_clz(map); +} + +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) +{ + if (is_32_bit) { + switch (satp_mode) { + case VM_1_10_SV32: + return "sv32"; + case VM_1_10_MBARE: + return "none"; + } + } else { + switch (satp_mode) { + case VM_1_10_SV64: + return "sv64"; + case VM_1_10_SV57: + return "sv57"; + case VM_1_10_SV48: + return "sv48"; + case VM_1_10_SV39: + return "sv39"; + case VM_1_10_MBARE: + return "none"; + } + } + + g_assert_not_reached(); +} + +/* Sets the satp mode to the max supported */ +static void set_satp_mode_default(RISCVCPU *cpu) +{ + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; + + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { + cpu->cfg.satp_mode.map |= + (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); + } else { + cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); + } +} + static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; @@ -619,6 +695,83 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) } } +static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) +{ + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; + uint8_t satp_mode_max; + + if (cpu->cfg.satp_mode.map == 0) { + if (cpu->cfg.satp_mode.init == 0) { + /* If unset by the user, we fallback to the default satp mode. */ + set_satp_mode_default(cpu); + } else { + /* + * Find the lowest level that was disabled and then enable the + * first valid level below which can be found in + * valid_vm_1_10_32/64. + */ + for (int i = 1; i < 16; ++i) { + if (!(cpu->cfg.satp_mode.map & (1 << i)) && + (cpu->cfg.satp_mode.init & (1 << i)) && + valid_vm[i]) { + for (int j = i - 1; j >= 0; --j) { + if (valid_vm[j]) { + cpu->cfg.satp_mode.map |= (1 << j); + break; + } + } + break; + } + } + } + } + + /* Make sure the configuration asked is supported by qemu */ + for (int i = 0; i < 16; ++i) { + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { + error_setg(errp, "satp_mode %s is not valid", + satp_mode_str(i, rv32)); + return; + } + } + + /* + * Make sure the user did not ask for an invalid configuration as per + * the specification. + */ + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); + + if (!rv32) { + for (int i = satp_mode_max - 1; i >= 0; --i) { + if (!(cpu->cfg.satp_mode.map & (1 << i)) && + (cpu->cfg.satp_mode.init & (1 << i)) && + valid_vm[i]) { + error_setg(errp, "cannot disable %s satp mode if %s " + "is enabled", satp_mode_str(i, false), + satp_mode_str(satp_mode_max, false)); + return; + } + } + } + + /* Finally expand the map so that all valid modes are set */ + for (int i = satp_mode_max - 1; i >= 0; --i) { + cpu->cfg.satp_mode.map |= (1 << i); + } +} + +static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) +{ + Error *local_err = NULL; + + riscv_cpu_satp_mode_finalize(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } +} + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -919,6 +1072,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } #endif + riscv_cpu_finalize_features(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + riscv_cpu_register_gdb_regs_for_features(cs); qemu_init_vcpu(cs); @@ -927,6 +1086,52 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) mcc->parent_realize(dev, errp); } +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVSATPMap *satp_map = opaque; + uint8_t satp = satp_mode_from_str(name); + bool value; + + value = (satp_map->map & (1 << satp)); + + visit_type_bool(v, name, &value, errp); +} + +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVSATPMap *satp_map = opaque; + uint8_t satp = satp_mode_from_str(name); + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + satp_map->map = deposit32(satp_map->map, satp, 1, value); + satp_map->init |= 1 << satp; +} + +static void riscv_add_satp_mode_properties(Object *obj) +{ + RISCVCPU *cpu = RISCV_CPU(obj); + + if (cpu->env.misa_mxl == MXL_RV32) { + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + } else { + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + } +} + #ifndef CONFIG_USER_ONLY static void riscv_cpu_set_irq(void *opaque, int irq, int level) { @@ -1091,6 +1296,8 @@ static void register_cpu_props(Object *obj) for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } + + riscv_add_satp_mode_properties(obj); } static Property riscv_cpu_properties[] = { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f5609b62a2..e37177db5c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -27,6 +27,7 @@ #include "qom/object.h" #include "qemu/int128.h" #include "cpu_bits.h" +#include "qapi/qapi-types-common.h" #define TCG_GUEST_DEFAULT_MO 0 @@ -413,6 +414,17 @@ struct RISCVCPUClass { ResettablePhases parent_phases; }; +/* + * map is a 16-bit bitmap: the most significant set bit in map is the maximum + * satp mode that is supported. + * + * init is a 16-bit bitmap used to make sure the user selected a correct + * configuration as per the specification. + */ +typedef struct { + uint16_t map, init; +} RISCVSATPMap; + struct RISCVCPUConfig { bool ext_i; bool ext_e; @@ -488,6 +500,8 @@ struct RISCVCPUConfig { bool debug; bool short_isa_string; + + RISCVSATPMap satp_mode; }; typedef struct RISCVCPUConfig RISCVCPUConfig; @@ -794,9 +808,14 @@ enum riscv_pmu_event_idx { /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; +extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; + void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); +uint8_t satp_mode_max_from_map(uint32_t map); +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); + #endif /* RISCV_CPU_H */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6b157806a5..3c02055825 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1117,12 +1117,12 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; static const target_ulong vsip_writable_mask = MIP_VSSIP; -static const bool valid_vm_1_10_32[16] = { +const bool valid_vm_1_10_32[16] = { [VM_1_10_MBARE] = true, [VM_1_10_SV32] = true }; -static const bool valid_vm_1_10_64[16] = { +const bool valid_vm_1_10_64[16] = { [VM_1_10_MBARE] = true, [VM_1_10_SV39] = true, [VM_1_10_SV48] = true, @@ -1211,11 +1211,9 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, static bool validate_vm(CPURISCVState *env, target_ulong vm) { - if (riscv_cpu_mxl(env) == MXL_RV32) { - return valid_vm_1_10_32[vm & 0xf]; - } else { - return valid_vm_1_10_64[vm & 0xf]; - } + RISCVCPU *cpu = RISCV_CPU(env_cpu(env)); + + return ((vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map)); } static RISCVException write_mstatus(CPURISCVState *env, int csrno, -- 2.37.2 From MAILER-DAEMON Wed Jan 25 03:45:22 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKbPG-0003Pl-AJ for mharc-qemu-riscv@gnu.org; Wed, 25 Jan 2023 03:45:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKbPF-0003Is-2W for qemu-riscv@nongnu.org; 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[2.7.42.160]) by smtp.gmail.com with ESMTPSA id i28-20020a05600c4b1c00b003dab40f9eafsm1109101wmp.35.2023.01.25.00.45.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 00:45:15 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v7 4/5] riscv: Introduce satp mode hw capabilities Date: Wed, 25 Jan 2023 09:41:06 +0100 Message-Id: <20230125084107.1580972-5-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230125084107.1580972-1-alexghiti@rivosinc.com> References: <20230125084107.1580972-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x32d.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 08:45:21 -0000 Currently, the max satp mode is set with the only constraint that it must be implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. But we actually need to add another level of constraint: what the hw is actually capable of, because currently, a linux booting on a sifive-u54 boots in sv57 mode which is incompatible with the cpu's sv39 max capability. So add a new bitmap to RISCVSATPMap which contains this capability and initialize it in every XXX_cpu_init. Finally: - valid_vm_1_10_[32|64] constrains which satp mode the CPU can use - the CPU hw capabilities constrains what the user may select - the user's selection then constrains what's available to the guest OS. Signed-off-by: Alexandre Ghiti --- target/riscv/cpu.c | 74 +++++++++++++++++++++++++++++++--------------- target/riscv/cpu.h | 8 +++-- 2 files changed, 56 insertions(+), 26 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 87153a0219..bba9c39bb8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -292,26 +292,36 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) g_assert_not_reached(); } -/* Sets the satp mode to the max supported */ -static void set_satp_mode_default(RISCVCPU *cpu) +static void set_satp_mode_max_supported(RISCVCPU *cpu, + uint8_t satp_mode) { bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { - cpu->cfg.satp_mode.map |= - (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); - } else { - cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); + for (int i = 0; i <= satp_mode; ++i) { + if (valid_vm[i]) { + cpu->cfg.satp_mode.supported |= (1 << i); + } } } +/* Sets the satp mode to the max supported */ +static void set_satp_mode_default(RISCVCPU *cpu) +{ + cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; +} + static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + #if defined(TARGET_RISCV32) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_satp_mode_max_supported(cpu, VM_1_10_SV32); #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_satp_mode_max_supported(cpu, VM_1_10_SV57); #endif set_priv_version(env, PRIV_VERSION_1_12_0); register_cpu_props(obj); @@ -321,18 +331,24 @@ static void riscv_any_cpu_init(Object *obj) static void rv64_base_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); + set_satp_mode_max_supported(cpu, VM_1_10_SV57); } static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); + set_satp_mode_max_supported(cpu, VM_1_10_SV39); } static void rv64_sifive_e_cpu_init(Object *obj) @@ -343,6 +359,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); } static void rv128_base_cpu_init(Object *obj) @@ -354,11 +371,13 @@ static void rv128_base_cpu_init(Object *obj) exit(EXIT_FAILURE); } CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); + set_satp_mode_max_supported(cpu, VM_1_10_SV57); } #else static void rv32_base_cpu_init(Object *obj) @@ -369,13 +388,17 @@ static void rv32_base_cpu_init(Object *obj) register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); + set_satp_mode_max_supported(cpu, VM_1_10_SV32); } static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); + set_satp_mode_max_supported(cpu, VM_1_10_SV32); } static void rv32_sifive_e_cpu_init(Object *obj) @@ -386,6 +409,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); } static void rv32_ibex_cpu_init(Object *obj) @@ -396,6 +420,7 @@ static void rv32_ibex_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.mmu = false; + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); cpu->cfg.epmp = true; } @@ -407,6 +432,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); } #endif @@ -698,8 +724,9 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) { bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; - const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; - uint8_t satp_mode_max; + uint8_t satp_mode_map_max; + uint8_t satp_mode_supported_max = + satp_mode_max_from_map(cpu->cfg.satp_mode.supported); if (cpu->cfg.satp_mode.map == 0) { if (cpu->cfg.satp_mode.init == 0) { @@ -714,9 +741,9 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) for (int i = 1; i < 16; ++i) { if (!(cpu->cfg.satp_mode.map & (1 << i)) && (cpu->cfg.satp_mode.init & (1 << i)) && - valid_vm[i]) { + (cpu->cfg.satp_mode.supported & (1 << i))) { for (int j = i - 1; j >= 0; --j) { - if (valid_vm[j]) { + if (cpu->cfg.satp_mode.supported & (1 << j)) { cpu->cfg.satp_mode.map |= (1 << j); break; } @@ -727,36 +754,35 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) } } - /* Make sure the configuration asked is supported by qemu */ - for (int i = 0; i < 16; ++i) { - if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { - error_setg(errp, "satp_mode %s is not valid", - satp_mode_str(i, rv32)); - return; - } + satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); + + /* Make sure the user asked for a supported configuration (HW and qemu) */ + if (satp_mode_map_max > satp_mode_supported_max) { + error_setg(errp, "satp_mode %s is higher than hw max capability %s", + satp_mode_str(satp_mode_map_max, rv32), + satp_mode_str(satp_mode_supported_max, rv32)); + return; } /* * Make sure the user did not ask for an invalid configuration as per * the specification. */ - satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); - if (!rv32) { - for (int i = satp_mode_max - 1; i >= 0; --i) { + for (int i = satp_mode_map_max - 1; i >= 0; --i) { if (!(cpu->cfg.satp_mode.map & (1 << i)) && (cpu->cfg.satp_mode.init & (1 << i)) && - valid_vm[i]) { + (cpu->cfg.satp_mode.supported & (1 << i))) { error_setg(errp, "cannot disable %s satp mode if %s " "is enabled", satp_mode_str(i, false), - satp_mode_str(satp_mode_max, false)); + satp_mode_str(satp_mode_map_max, false)); return; } } } /* Finally expand the map so that all valid modes are set */ - for (int i = satp_mode_max - 1; i >= 0; --i) { + for (int i = satp_mode_map_max - 1; i >= 0; --i) { cpu->cfg.satp_mode.map |= (1 << i); } } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e37177db5c..b591122099 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -416,13 +416,17 @@ struct RISCVCPUClass { /* * map is a 16-bit bitmap: the most significant set bit in map is the maximum - * satp mode that is supported. + * satp mode that is supported. It may be chosen by the user and must respect + * what qemu implements (valid_1_10_32/64) and what the hw is capable of + * (supported bitmap below). * * init is a 16-bit bitmap used to make sure the user selected a correct * configuration as per the specification. + * + * supported is a 16-bit bitmap used to reflect the hw capabilities. */ typedef struct { - uint16_t map, init; + uint16_t map, init, supported; } RISCVSATPMap; struct RISCVCPUConfig { -- 2.37.2 From MAILER-DAEMON Wed Jan 25 03:46:26 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKbQI-0006kY-Lg for mharc-qemu-riscv@gnu.org; Wed, 25 Jan 2023 03:46:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKbQC-0006Ks-Ih for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 03:46:22 -0500 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKbQA-0008BY-6a for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 03:46:19 -0500 Received: by mail-wm1-x330.google.com with SMTP id f25-20020a1c6a19000000b003da221fbf48so718902wmc.1 for ; Wed, 25 Jan 2023 00:46:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IRWvpmPRHrukoIwIrFR+ERY535b3mU7yJB9xTFeVSNc=; b=bpklNfsyt9jwLJshAAnAoZ/GHctkWTO28Qwllz1TSEUmsKBGcN2pb1RYJM6MOv+cSa CncmPExEEvKiR75sKhOVuTSdI3IxUowLNcWQr9ftcGEcd1BqgBTut0Yy0nkyk8M89hgU vCjAXGz+GAbQudECk9/DKbDwJvpYtiDwl7E7lqfUpGtfISdVT0rr+m6sqCUD16HEGa24 KKmTrsgLLCt/2fyCGPmFDGFZoZmN+C2p0BJwtPfwqvgPKGDtZPyYkc2JVyMgxOCXyGjy WC35zA5hkvU0578RO43hyzARzBz0pGptxpg0Jo7686dJYKrD0Bad7fjk6pe/QRWnTyZj ByRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IRWvpmPRHrukoIwIrFR+ERY535b3mU7yJB9xTFeVSNc=; b=Hs92cNtg8x1zplNUwRB4K5wR4ozTkgdZBmZkhHyoUBCip34yFFOdQK8PHXaVDVdfyP Krd+t9dWEmEp/qI4FiuI7V0coNh/Q7yDP7xIh2yj6IR5SGmu2GRSOTpBK/tZAVN8BOpN T/5/Z+5qMMK/IHyfiU15Z25OkFgnpq9ba/t5/an7IufrA8WTfSJ9X+QkIK/OaZS2mcmy YfWAsEODqMq44IIk373iyo8ePbrnUj2DIH1H2ZctqfhUCgkQh7XENKGvZeCMj9sDqLwk 3m7d5d1Z8bXiNULcTAB0pPMl09Vuc4Yc4A/waw7+/LXxjmAXLaRLjtiniB4/6i4Mq2+7 SCSA== X-Gm-Message-State: AFqh2krNf7AUmPkYZx7zAFxWHwAYhOLr9Ez9hgVGLoQs8jLvcuH8f4ta LQNIeoTFuVfk/JPTfDtNlA9omg== X-Google-Smtp-Source: AMrXdXvne5enjH73X+2/5xZIXijlQmkC4gon0WWBwXXANi6Ki2QTTFD2siDqqA2TIe2H1l4DylpQag== X-Received: by 2002:a05:600c:4191:b0:3d4:5741:af9b with SMTP id p17-20020a05600c419100b003d45741af9bmr38612590wmh.0.1674636376790; Wed, 25 Jan 2023 00:46:16 -0800 (PST) Received: from alex-rivos.home (lfbn-lyo-1-450-160.w2-7.abo.wanadoo.fr. [2.7.42.160]) by smtp.gmail.com with ESMTPSA id m18-20020adfe952000000b00286ad197346sm3850791wrn.70.2023.01.25.00.46.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 00:46:16 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v7 5/5] riscv: Correctly set the device-tree entry 'mmu-type' Date: Wed, 25 Jan 2023 09:41:07 +0100 Message-Id: <20230125084107.1580972-6-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230125084107.1580972-1-alexghiti@rivosinc.com> References: <20230125084107.1580972-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x330.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 08:46:24 -0000 The 'mmu-type' should reflect what the hardware is capable of so use the new satp_mode field in RISCVCPUConfig to do that. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- hw/riscv/virt.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 94ff2a1584..48d034a5f7 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -228,7 +228,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, int cpu; uint32_t cpu_phandle; MachineState *mc = MACHINE(s); - char *name, *cpu_name, *core_name, *intc_name; + uint8_t satp_mode_max; + char *name, *cpu_name, *core_name, *intc_name, *sv_name; for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { cpu_phandle = (*phandle)++; @@ -236,14 +237,14 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(mc->fdt, cpu_name); - if (riscv_feature(&s->soc[socket].harts[cpu].env, - RISCV_FEATURE_MMU)) { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", - (is_32_bit) ? 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charset=us-ascii Content-Disposition: inline In-Reply-To: <20230125084107.1580972-4-alexghiti@rivosinc.com> Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=ajones@ventanamicro.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 12:01:14 -0000 On Wed, Jan 25, 2023 at 09:41:05AM +0100, Alexandre Ghiti wrote: > RISC-V specifies multiple sizes for addressable memory and Linux probes for > the machine's support at startup via the satp CSR register (done in > csr.c:validate_vm). > > As per the specification, sv64 must support sv57, which in turn must > support sv48...etc. So we can restrict machine support by simply setting the > "highest" supported mode and the bare mode is always supported. > > You can set the satp mode using the new properties "sv32", "sv39", "sv48", > "sv57" and "sv64" as follows: > -cpu rv64,sv57=on # Linux will boot using sv57 scheme > -cpu rv64,sv39=on # Linux will boot using sv39 scheme > -cpu rv64,sv57=off # Linux will boot using sv48 scheme > -cpu rv64 # Linux will boot using sv57 scheme by default > > We take the highest level set by the user: > -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme > > We make sure that invalid configurations are rejected: > -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are > # enabled > > We accept "redundant" configurations: > -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme > > And contradictory configurations: > -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme > > Co-Developed-by: Ludovic Henry > Signed-off-by: Ludovic Henry > Signed-off-by: Alexandre Ghiti > --- > target/riscv/cpu.c | 207 +++++++++++++++++++++++++++++++++++++++++++++ > target/riscv/cpu.h | 19 +++++ > target/riscv/csr.c | 12 ++- > 3 files changed, 231 insertions(+), 7 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 7181b34f86..87153a0219 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -27,6 +27,7 @@ > #include "time_helper.h" > #include "exec/exec-all.h" > #include "qapi/error.h" > +#include "qapi/visitor.h" > #include "qemu/error-report.h" > #include "hw/qdev-properties.h" > #include "migration/vmstate.h" > @@ -229,6 +230,81 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) > env->vext_ver = vext_ver; > } > > +static uint8_t satp_mode_from_str(const char *satp_mode_str) > +{ > + if (!strncmp(satp_mode_str, "mbare", 5)) { > + return VM_1_10_MBARE; > + } > + > + if (!strncmp(satp_mode_str, "sv32", 4)) { > + return VM_1_10_SV32; > + } > + > + if (!strncmp(satp_mode_str, "sv39", 4)) { > + return VM_1_10_SV39; > + } > + > + if (!strncmp(satp_mode_str, "sv48", 4)) { > + return VM_1_10_SV48; > + } > + > + if (!strncmp(satp_mode_str, "sv57", 4)) { > + return VM_1_10_SV57; > + } > + > + if (!strncmp(satp_mode_str, "sv64", 4)) { > + return VM_1_10_SV64; > + } > + > + g_assert_not_reached(); > +} > + > +uint8_t satp_mode_max_from_map(uint32_t map) > +{ > + /* map here has at least one bit set, so no problem with clz */ > + return 31 - __builtin_clz(map); > +} > + > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > +{ > + if (is_32_bit) { > + switch (satp_mode) { > + case VM_1_10_SV32: > + return "sv32"; > + case VM_1_10_MBARE: > + return "none"; > + } > + } else { > + switch (satp_mode) { > + case VM_1_10_SV64: > + return "sv64"; > + case VM_1_10_SV57: > + return "sv57"; > + case VM_1_10_SV48: > + return "sv48"; > + case VM_1_10_SV39: > + return "sv39"; > + case VM_1_10_MBARE: > + return "none"; > + } > + } > + > + g_assert_not_reached(); > +} > + > +/* Sets the satp mode to the max supported */ > +static void set_satp_mode_default(RISCVCPU *cpu) > +{ > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > + > + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > + cpu->cfg.satp_mode.map |= > + (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); > + } else { > + cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > + } > +} > + > static void riscv_any_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > @@ -619,6 +695,83 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > } > } > > +static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > +{ > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > + uint8_t satp_mode_max; > + > + if (cpu->cfg.satp_mode.map == 0) { > + if (cpu->cfg.satp_mode.init == 0) { > + /* If unset by the user, we fallback to the default satp mode. */ > + set_satp_mode_default(cpu); > + } else { > + /* > + * Find the lowest level that was disabled and then enable the > + * first valid level below which can be found in > + * valid_vm_1_10_32/64. > + */ > + for (int i = 1; i < 16; ++i) { > + if (!(cpu->cfg.satp_mode.map & (1 << i)) && We don't need the condition above because we came here with map == 0 and we only visit each bit once. > + (cpu->cfg.satp_mode.init & (1 << i)) && > + valid_vm[i]) { > + for (int j = i - 1; j >= 0; --j) { > + if (valid_vm[j]) { > + cpu->cfg.satp_mode.map |= (1 << j); > + break; > + } > + } > + break; > + } > + } > + } > + } > + > + /* Make sure the configuration asked is supported by qemu */ > + for (int i = 0; i < 16; ++i) { > + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > + error_setg(errp, "satp_mode %s is not valid", > + satp_mode_str(i, rv32)); > + return; > + } > + } > + > + /* > + * Make sure the user did not ask for an invalid configuration as per > + * the specification. > + */ > + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > + > + if (!rv32) { > + for (int i = satp_mode_max - 1; i >= 0; --i) { satp_mode_max can be zero when configs only support mbare, so we need to be careful here. We should only run this loop when it's greater than zero. > + if (!(cpu->cfg.satp_mode.map & (1 << i)) && > + (cpu->cfg.satp_mode.init & (1 << i)) && > + valid_vm[i]) { > + error_setg(errp, "cannot disable %s satp mode if %s " > + "is enabled", satp_mode_str(i, false), > + satp_mode_str(satp_mode_max, false)); > + return; > + } > + } > + } > + > + /* Finally expand the map so that all valid modes are set */ > + for (int i = satp_mode_max - 1; i >= 0; --i) { Same here, need to heck satp_mode_max is greater than zero. > + cpu->cfg.satp_mode.map |= (1 << i); > + } > +} > + > +static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > +{ > + Error *local_err = NULL; > + > + riscv_cpu_satp_mode_finalize(cpu, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > + } > +} > + > static void riscv_cpu_realize(DeviceState *dev, Error **errp) > { > CPUState *cs = CPU(dev); > @@ -919,6 +1072,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > #endif > > + riscv_cpu_finalize_features(cpu, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > + } > + > riscv_cpu_register_gdb_regs_for_features(cs); > > qemu_init_vcpu(cs); > @@ -927,6 +1086,52 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > mcc->parent_realize(dev, errp); > } > > +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + RISCVSATPMap *satp_map = opaque; > + uint8_t satp = satp_mode_from_str(name); > + bool value; > + > + value = (satp_map->map & (1 << satp)); > + > + visit_type_bool(v, name, &value, errp); > +} > + > +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + RISCVSATPMap *satp_map = opaque; > + uint8_t satp = satp_mode_from_str(name); > + bool value; > + > + if (!visit_type_bool(v, name, &value, errp)) { > + return; > + } > + > + satp_map->map = deposit32(satp_map->map, satp, 1, value); > + satp_map->init |= 1 << satp; > +} > + > +static void riscv_add_satp_mode_properties(Object *obj) > +{ > + RISCVCPU *cpu = RISCV_CPU(obj); > + > + if (cpu->env.misa_mxl == MXL_RV32) { > + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + } else { > + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + } > +} > + > #ifndef CONFIG_USER_ONLY > static void riscv_cpu_set_irq(void *opaque, int irq, int level) > { > @@ -1091,6 +1296,8 @@ static void register_cpu_props(Object *obj) > for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > qdev_property_add_static(dev, prop); > } > + > + riscv_add_satp_mode_properties(obj); > } > > static Property riscv_cpu_properties[] = { > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index f5609b62a2..e37177db5c 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -27,6 +27,7 @@ > #include "qom/object.h" > #include "qemu/int128.h" > #include "cpu_bits.h" > +#include "qapi/qapi-types-common.h" > > #define TCG_GUEST_DEFAULT_MO 0 > > @@ -413,6 +414,17 @@ struct RISCVCPUClass { > ResettablePhases parent_phases; > }; > > +/* > + * map is a 16-bit bitmap: the most significant set bit in map is the maximum > + * satp mode that is supported. > + * > + * init is a 16-bit bitmap used to make sure the user selected a correct > + * configuration as per the specification. > + */ > +typedef struct { > + uint16_t map, init; > +} RISCVSATPMap; > + > struct RISCVCPUConfig { > bool ext_i; > bool ext_e; > @@ -488,6 +500,8 @@ struct RISCVCPUConfig { > bool debug; > > bool short_isa_string; > + > + RISCVSATPMap satp_mode; > }; > > typedef struct RISCVCPUConfig RISCVCPUConfig; > @@ -794,9 +808,14 @@ enum riscv_pmu_event_idx { > /* CSR function table */ > extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; > > +extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; > + > void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); > void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); > > void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); > > +uint8_t satp_mode_max_from_map(uint32_t map); > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); > + > #endif /* RISCV_CPU_H */ > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 6b157806a5..3c02055825 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1117,12 +1117,12 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; > static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; > static const target_ulong vsip_writable_mask = MIP_VSSIP; > > -static const bool valid_vm_1_10_32[16] = { > +const bool valid_vm_1_10_32[16] = { > [VM_1_10_MBARE] = true, > [VM_1_10_SV32] = true > }; > > -static const bool valid_vm_1_10_64[16] = { > +const bool valid_vm_1_10_64[16] = { > [VM_1_10_MBARE] = true, > [VM_1_10_SV39] = true, > [VM_1_10_SV48] = true, > @@ -1211,11 +1211,9 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, > > static bool validate_vm(CPURISCVState *env, target_ulong vm) > { > - if (riscv_cpu_mxl(env) == MXL_RV32) { > - return valid_vm_1_10_32[vm & 0xf]; > - } else { > - return valid_vm_1_10_64[vm & 0xf]; > - } > + RISCVCPU *cpu = RISCV_CPU(env_cpu(env)); > + > + return ((vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map)); > } > > static RISCVException write_mstatus(CPURISCVState *env, int csrno, > -- > 2.37.2 > Thanks, drew From MAILER-DAEMON Wed Jan 25 07:06:54 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKeYI-0005zc-8t for mharc-qemu-riscv@gnu.org; Wed, 25 Jan 2023 07:06:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKeXg-0005SM-Pd for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 07:06:34 -0500 Received: from mail-ed1-x530.google.com ([2a00:1450:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKeXa-0005uC-Un for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 07:06:13 -0500 Received: by mail-ed1-x530.google.com with SMTP id y19so21543508edc.2 for ; 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Wed, 25 Jan 2023 04:06:08 -0800 (PST) Received: from localhost ([93.99.189.36]) by smtp.gmail.com with ESMTPSA id v26-20020a056402175a00b0049ef70a2894sm2307102edx.38.2023.01.25.04.06.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 04:06:08 -0800 (PST) Date: Wed, 25 Jan 2023 13:06:07 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: Re: [PATCH v7 4/5] riscv: Introduce satp mode hw capabilities Message-ID: <20230125120607.v3ooio7hh3uadinj@orel> References: <20230125084107.1580972-1-alexghiti@rivosinc.com> <20230125084107.1580972-5-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230125084107.1580972-5-alexghiti@rivosinc.com> Received-SPF: pass client-ip=2a00:1450:4864:20::530; envelope-from=ajones@ventanamicro.com; helo=mail-ed1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 12:06:42 -0000 On Wed, Jan 25, 2023 at 09:41:06AM +0100, Alexandre Ghiti wrote: > Currently, the max satp mode is set with the only constraint that it must be > implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. > > But we actually need to add another level of constraint: what the hw is > actually capable of, because currently, a linux booting on a sifive-u54 > boots in sv57 mode which is incompatible with the cpu's sv39 max > capability. > > So add a new bitmap to RISCVSATPMap which contains this capability and > initialize it in every XXX_cpu_init. > > Finally: > - valid_vm_1_10_[32|64] constrains which satp mode the CPU can use > - the CPU hw capabilities constrains what the user may select > - the user's selection then constrains what's available to the guest > OS. > > Signed-off-by: Alexandre Ghiti > --- > target/riscv/cpu.c | 74 +++++++++++++++++++++++++++++++--------------- > target/riscv/cpu.h | 8 +++-- > 2 files changed, 56 insertions(+), 26 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 87153a0219..bba9c39bb8 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -292,26 +292,36 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > g_assert_not_reached(); > } > > -/* Sets the satp mode to the max supported */ > -static void set_satp_mode_default(RISCVCPU *cpu) > +static void set_satp_mode_max_supported(RISCVCPU *cpu, > + uint8_t satp_mode) > { > bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > > - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > - cpu->cfg.satp_mode.map |= > - (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); > - } else { > - cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > + for (int i = 0; i <= satp_mode; ++i) { > + if (valid_vm[i]) { > + cpu->cfg.satp_mode.supported |= (1 << i); > + } > } > } > > +/* Sets the satp mode to the max supported */ > +static void set_satp_mode_default(RISCVCPU *cpu) > +{ > + cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; > +} > + > static void riscv_any_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > #if defined(TARGET_RISCV32) > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > + set_satp_mode_max_supported(cpu, VM_1_10_SV32); > #elif defined(TARGET_RISCV64) > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > + set_satp_mode_max_supported(cpu, VM_1_10_SV57); > #endif > set_priv_version(env, PRIV_VERSION_1_12_0); > register_cpu_props(obj); > @@ -321,18 +331,24 @@ static void riscv_any_cpu_init(Object *obj) > static void rv64_base_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > /* We set this in the realise function */ > set_misa(env, MXL_RV64, 0); > register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > + set_satp_mode_max_supported(cpu, VM_1_10_SV57); > } > > static void rv64_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > + set_satp_mode_max_supported(cpu, VM_1_10_SV39); > } > > static void rv64_sifive_e_cpu_init(Object *obj) > @@ -343,6 +359,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > } > > static void rv128_base_cpu_init(Object *obj) > @@ -354,11 +371,13 @@ static void rv128_base_cpu_init(Object *obj) > exit(EXIT_FAILURE); > } > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > /* We set this in the realise function */ > set_misa(env, MXL_RV128, 0); > register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > + set_satp_mode_max_supported(cpu, VM_1_10_SV57); > } > #else > static void rv32_base_cpu_init(Object *obj) > @@ -369,13 +388,17 @@ static void rv32_base_cpu_init(Object *obj) > register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > + set_satp_mode_max_supported(cpu, VM_1_10_SV32); > } > > static void rv32_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > + set_satp_mode_max_supported(cpu, VM_1_10_SV32); > } > > static void rv32_sifive_e_cpu_init(Object *obj) > @@ -386,6 +409,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > } > > static void rv32_ibex_cpu_init(Object *obj) > @@ -396,6 +420,7 @@ static void rv32_ibex_cpu_init(Object *obj) > set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_11_0); > cpu->cfg.mmu = false; > + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > cpu->cfg.epmp = true; > } > > @@ -407,6 +432,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > } > #endif > > @@ -698,8 +724,9 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > { > bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > - const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > - uint8_t satp_mode_max; > + uint8_t satp_mode_map_max; > + uint8_t satp_mode_supported_max = > + satp_mode_max_from_map(cpu->cfg.satp_mode.supported); > > if (cpu->cfg.satp_mode.map == 0) { > if (cpu->cfg.satp_mode.init == 0) { > @@ -714,9 +741,9 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > for (int i = 1; i < 16; ++i) { > if (!(cpu->cfg.satp_mode.map & (1 << i)) && > (cpu->cfg.satp_mode.init & (1 << i)) && > - valid_vm[i]) { > + (cpu->cfg.satp_mode.supported & (1 << i))) { > for (int j = i - 1; j >= 0; --j) { > - if (valid_vm[j]) { > + if (cpu->cfg.satp_mode.supported & (1 << j)) { > cpu->cfg.satp_mode.map |= (1 << j); > break; > } > @@ -727,36 +754,35 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > } > } > > - /* Make sure the configuration asked is supported by qemu */ > - for (int i = 0; i < 16; ++i) { > - if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > - error_setg(errp, "satp_mode %s is not valid", > - satp_mode_str(i, rv32)); > - return; > - } > + satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > + > + /* Make sure the user asked for a supported configuration (HW and qemu) */ > + if (satp_mode_map_max > satp_mode_supported_max) { > + error_setg(errp, "satp_mode %s is higher than hw max capability %s", > + satp_mode_str(satp_mode_map_max, rv32), > + satp_mode_str(satp_mode_supported_max, rv32)); > + return; > } > > /* > * Make sure the user did not ask for an invalid configuration as per > * the specification. > */ > - satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > - > if (!rv32) { > - for (int i = satp_mode_max - 1; i >= 0; --i) { > + for (int i = satp_mode_map_max - 1; i >= 0; --i) { > if (!(cpu->cfg.satp_mode.map & (1 << i)) && > (cpu->cfg.satp_mode.init & (1 << i)) && > - valid_vm[i]) { > + (cpu->cfg.satp_mode.supported & (1 << i))) { > error_setg(errp, "cannot disable %s satp mode if %s " > "is enabled", satp_mode_str(i, false), > - satp_mode_str(satp_mode_max, false)); > + satp_mode_str(satp_mode_map_max, false)); > return; > } > } > } > > /* Finally expand the map so that all valid modes are set */ > - for (int i = satp_mode_max - 1; i >= 0; --i) { > + for (int i = satp_mode_map_max - 1; i >= 0; --i) { > cpu->cfg.satp_mode.map |= (1 << i); > } > } > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index e37177db5c..b591122099 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -416,13 +416,17 @@ struct RISCVCPUClass { > > /* > * map is a 16-bit bitmap: the most significant set bit in map is the maximum > - * satp mode that is supported. > + * satp mode that is supported. It may be chosen by the user and must respect > + * what qemu implements (valid_1_10_32/64) and what the hw is capable of > + * (supported bitmap below). > * > * init is a 16-bit bitmap used to make sure the user selected a correct > * configuration as per the specification. > + * > + * supported is a 16-bit bitmap used to reflect the hw capabilities. > */ > typedef struct { > - uint16_t map, init; > + uint16_t map, init, supported; > } RISCVSATPMap; > > struct RISCVCPUConfig { > -- > 2.37.2 > Reviewed-by: Andrew Jones Thanks, drew From MAILER-DAEMON Wed Jan 25 07:24:18 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKep6-0007aH-AW for mharc-qemu-riscv@gnu.org; Wed, 25 Jan 2023 07:24:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKeor-0007ZG-GL for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 07:24:01 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKeoo-0001LH-J0 for qemu-riscv@nongnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x331.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 12:24:01 -0000 On Wed, Jan 25, 2023 at 1:01 PM Andrew Jones wrote: > > On Wed, Jan 25, 2023 at 09:41:05AM +0100, Alexandre Ghiti wrote: > > RISC-V specifies multiple sizes for addressable memory and Linux probes for > > the machine's support at startup via the satp CSR register (done in > > csr.c:validate_vm). > > > > As per the specification, sv64 must support sv57, which in turn must > > support sv48...etc. So we can restrict machine support by simply setting the > > "highest" supported mode and the bare mode is always supported. > > > > You can set the satp mode using the new properties "sv32", "sv39", "sv48", > > "sv57" and "sv64" as follows: > > -cpu rv64,sv57=on # Linux will boot using sv57 scheme > > -cpu rv64,sv39=on # Linux will boot using sv39 scheme > > -cpu rv64,sv57=off # Linux will boot using sv48 scheme > > -cpu rv64 # Linux will boot using sv57 scheme by default > > > > We take the highest level set by the user: > > -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme > > > > We make sure that invalid configurations are rejected: > > -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are > > # enabled > > > > We accept "redundant" configurations: > > -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme > > > > And contradictory configurations: > > -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme > > > > Co-Developed-by: Ludovic Henry > > Signed-off-by: Ludovic Henry > > Signed-off-by: Alexandre Ghiti > > --- > > target/riscv/cpu.c | 207 +++++++++++++++++++++++++++++++++++++++++++++ > > target/riscv/cpu.h | 19 +++++ > > target/riscv/csr.c | 12 ++- > > 3 files changed, 231 insertions(+), 7 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 7181b34f86..87153a0219 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -27,6 +27,7 @@ > > #include "time_helper.h" > > #include "exec/exec-all.h" > > #include "qapi/error.h" > > +#include "qapi/visitor.h" > > #include "qemu/error-report.h" > > #include "hw/qdev-properties.h" > > #include "migration/vmstate.h" > > @@ -229,6 +230,81 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) > > env->vext_ver = vext_ver; > > } > > > > +static uint8_t satp_mode_from_str(const char *satp_mode_str) > > +{ > > + if (!strncmp(satp_mode_str, "mbare", 5)) { > > + return VM_1_10_MBARE; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv32", 4)) { > > + return VM_1_10_SV32; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv39", 4)) { > > + return VM_1_10_SV39; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv48", 4)) { > > + return VM_1_10_SV48; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv57", 4)) { > > + return VM_1_10_SV57; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv64", 4)) { > > + return VM_1_10_SV64; > > + } > > + > > + g_assert_not_reached(); > > +} > > + > > +uint8_t satp_mode_max_from_map(uint32_t map) > > +{ > > + /* map here has at least one bit set, so no problem with clz */ > > + return 31 - __builtin_clz(map); > > +} > > + > > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > > +{ > > + if (is_32_bit) { > > + switch (satp_mode) { > > + case VM_1_10_SV32: > > + return "sv32"; > > + case VM_1_10_MBARE: > > + return "none"; > > + } > > + } else { > > + switch (satp_mode) { > > + case VM_1_10_SV64: > > + return "sv64"; > > + case VM_1_10_SV57: > > + return "sv57"; > > + case VM_1_10_SV48: > > + return "sv48"; > > + case VM_1_10_SV39: > > + return "sv39"; > > + case VM_1_10_MBARE: > > + return "none"; > > + } > > + } > > + > > + g_assert_not_reached(); > > +} > > + > > +/* Sets the satp mode to the max supported */ > > +static void set_satp_mode_default(RISCVCPU *cpu) > > +{ > > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > > + > > + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > > + cpu->cfg.satp_mode.map |= > > + (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); > > + } else { > > + cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > > + } > > +} > > + > > static void riscv_any_cpu_init(Object *obj) > > { > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > @@ -619,6 +695,83 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > > } > > } > > > > +static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > > +{ > > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > > + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > > + uint8_t satp_mode_max; > > + > > + if (cpu->cfg.satp_mode.map == 0) { > > + if (cpu->cfg.satp_mode.init == 0) { > > + /* If unset by the user, we fallback to the default satp mode. */ > > + set_satp_mode_default(cpu); > > + } else { > > + /* > > + * Find the lowest level that was disabled and then enable the > > + * first valid level below which can be found in > > + * valid_vm_1_10_32/64. > > + */ > > + for (int i = 1; i < 16; ++i) { > > + if (!(cpu->cfg.satp_mode.map & (1 << i)) && > > We don't need the condition above because we came here with map == 0 > and we only visit each bit once. Ok, I spin a v8 for this. > > > + (cpu->cfg.satp_mode.init & (1 << i)) && > > + valid_vm[i]) { > > + for (int j = i - 1; j >= 0; --j) { > > + if (valid_vm[j]) { > > + cpu->cfg.satp_mode.map |= (1 << j); > > + break; > > + } > > + } > > + break; > > + } > > + } > > + } > > + } > > + > > + /* Make sure the configuration asked is supported by qemu */ > > + for (int i = 0; i < 16; ++i) { > > + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > > + error_setg(errp, "satp_mode %s is not valid", > > + satp_mode_str(i, rv32)); > > + return; > > + } > > + } > > + > > + /* > > + * Make sure the user did not ask for an invalid configuration as per > > + * the specification. > > + */ > > + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > > + > > + if (!rv32) { > > + for (int i = satp_mode_max - 1; i >= 0; --i) { > > satp_mode_max can be zero when configs only support mbare, so we need > to be careful here. We should only run this loop when it's greater than > zero. If satp_mode_max == 0, we don't enter the loop, so no problem for me. > > > + if (!(cpu->cfg.satp_mode.map & (1 << i)) && > > + (cpu->cfg.satp_mode.init & (1 << i)) && > > + valid_vm[i]) { > > + error_setg(errp, "cannot disable %s satp mode if %s " > > + "is enabled", satp_mode_str(i, false), > > + satp_mode_str(satp_mode_max, false)); > > + return; > > + } > > + } > > + } > > + > > + /* Finally expand the map so that all valid modes are set */ > > + for (int i = satp_mode_max - 1; i >= 0; --i) { > > Same here, need to heck satp_mode_max is greater than zero. Ditto here. > > > + cpu->cfg.satp_mode.map |= (1 << i); > > + } > > +} > > + > > +static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > > +{ > > + Error *local_err = NULL; > > + > > + riscv_cpu_satp_mode_finalize(cpu, &local_err); > > + if (local_err != NULL) { > > + error_propagate(errp, local_err); > > + return; > > + } > > +} > > + > > static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > { > > CPUState *cs = CPU(dev); > > @@ -919,6 +1072,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > } > > #endif > > > > + riscv_cpu_finalize_features(cpu, &local_err); > > + if (local_err != NULL) { > > + error_propagate(errp, local_err); > > + return; > > + } > > + > > riscv_cpu_register_gdb_regs_for_features(cs); > > > > qemu_init_vcpu(cs); > > @@ -927,6 +1086,52 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > mcc->parent_realize(dev, errp); > > } > > > > +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, > > + void *opaque, Error **errp) > > +{ > > + RISCVSATPMap *satp_map = opaque; > > + uint8_t satp = satp_mode_from_str(name); > > + bool value; > > + > > + value = (satp_map->map & (1 << satp)); > > + > > + visit_type_bool(v, name, &value, errp); > > +} > > + > > +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, > > + void *opaque, Error **errp) > > +{ > > + RISCVSATPMap *satp_map = opaque; > > + uint8_t satp = satp_mode_from_str(name); > > + bool value; > > + > > + if (!visit_type_bool(v, name, &value, errp)) { > > + return; > > + } > > + > > + satp_map->map = deposit32(satp_map->map, satp, 1, value); > > + satp_map->init |= 1 << satp; > > +} > > + > > +static void riscv_add_satp_mode_properties(Object *obj) > > +{ > > + RISCVCPU *cpu = RISCV_CPU(obj); > > + > > + if (cpu->env.misa_mxl == MXL_RV32) { > > + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + } else { > > + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + } > > +} > > + > > #ifndef CONFIG_USER_ONLY > > static void riscv_cpu_set_irq(void *opaque, int irq, int level) > > { > > @@ -1091,6 +1296,8 @@ static void register_cpu_props(Object *obj) > > for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > > qdev_property_add_static(dev, prop); > > } > > + > > + riscv_add_satp_mode_properties(obj); > > } > > > > static Property riscv_cpu_properties[] = { > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index f5609b62a2..e37177db5c 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -27,6 +27,7 @@ > > #include "qom/object.h" > > #include "qemu/int128.h" > > #include "cpu_bits.h" > > +#include "qapi/qapi-types-common.h" > > > > #define TCG_GUEST_DEFAULT_MO 0 > > > > @@ -413,6 +414,17 @@ struct RISCVCPUClass { > > ResettablePhases parent_phases; > > }; > > > > +/* > > + * map is a 16-bit bitmap: the most significant set bit in map is the maximum > > + * satp mode that is supported. > > + * > > + * init is a 16-bit bitmap used to make sure the user selected a correct > > + * configuration as per the specification. > > + */ > > +typedef struct { > > + uint16_t map, init; > > +} RISCVSATPMap; > > + > > struct RISCVCPUConfig { > > bool ext_i; > > bool ext_e; > > @@ -488,6 +500,8 @@ struct RISCVCPUConfig { > > bool debug; > > > > bool short_isa_string; > > + > > + RISCVSATPMap satp_mode; > > }; > > > > typedef struct RISCVCPUConfig RISCVCPUConfig; > > @@ -794,9 +808,14 @@ enum riscv_pmu_event_idx { > > /* CSR function table */ > > extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; > > > > +extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; > > + > > void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); > > void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); > > > > void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); > > > > +uint8_t satp_mode_max_from_map(uint32_t map); > > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); > > + > > #endif /* RISCV_CPU_H */ > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 6b157806a5..3c02055825 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -1117,12 +1117,12 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; > > static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; > > static const target_ulong vsip_writable_mask = MIP_VSSIP; > > > > -static const bool valid_vm_1_10_32[16] = { > > +const bool valid_vm_1_10_32[16] = { > > [VM_1_10_MBARE] = true, > > [VM_1_10_SV32] = true > > }; > > > > -static const bool valid_vm_1_10_64[16] = { > > +const bool valid_vm_1_10_64[16] = { > > [VM_1_10_MBARE] = true, > > [VM_1_10_SV39] = true, > > [VM_1_10_SV48] = true, > > @@ -1211,11 +1211,9 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, > > > > static bool validate_vm(CPURISCVState *env, target_ulong vm) > > { > > - if (riscv_cpu_mxl(env) == MXL_RV32) { > > - return valid_vm_1_10_32[vm & 0xf]; > > - } else { > > - return valid_vm_1_10_64[vm & 0xf]; > > - } > > + RISCVCPU *cpu = RISCV_CPU(env_cpu(env)); > > + > > + return ((vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map)); > > } > > > > static RISCVException write_mstatus(CPURISCVState *env, int csrno, > > -- > > 2.37.2 > > > > Thanks, > drew From MAILER-DAEMON Wed Jan 25 10:00:52 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKhGe-0003Zd-4a for mharc-qemu-riscv@gnu.org; Wed, 25 Jan 2023 10:00:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKhGY-0003YX-1v for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 10:00:50 -0500 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKhGW-0005um-5s for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 10:00:45 -0500 Received: by mail-ej1-x631.google.com with SMTP id v6so48399031ejg.6 for ; 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[31.30.173.16]) by smtp.gmail.com with ESMTPSA id p18-20020a17090635d200b007c0b28b85c5sm2434816ejb.138.2023.01.25.07.00.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 07:00:42 -0800 (PST) Date: Wed, 25 Jan 2023 16:00:35 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Subject: Re: [PATCH v7 3/5] riscv: Allow user to set the satp mode Message-ID: <20230125150035.mx6y65aqx7si32mm@orel> References: <20230125084107.1580972-1-alexghiti@rivosinc.com> <20230125084107.1580972-4-alexghiti@rivosinc.com> <20230125120107.mjh54hcmustfplgi@orel> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=ajones@ventanamicro.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 15:00:50 -0000 On Wed, Jan 25, 2023 at 01:23:45PM +0100, Alexandre Ghiti wrote: > On Wed, Jan 25, 2023 at 1:01 PM Andrew Jones wrote: > > > > On Wed, Jan 25, 2023 at 09:41:05AM +0100, Alexandre Ghiti wrote: ... > > > + if (!rv32) { > > > + for (int i = satp_mode_max - 1; i >= 0; --i) { > > > > satp_mode_max can be zero when configs only support mbare, so we need > > to be careful here. We should only run this loop when it's greater than > > zero. > > If satp_mode_max == 0, we don't enter the loop, so no problem for me. > Oh, right, i is signed. I reviewed this right after reviewing some unsigned comparisons and had the wrong thought process engaged... And now I recall that when I'd read this before in previous revisions I had had the same impulse at least once, but those times I noticed it was signed before sending comments. Anyway, sorry for the noise. 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[2.7.42.160]) by smtp.gmail.com with ESMTPSA id l12-20020a05600012cc00b002bfba730b0fsm1895458wrx.65.2023.01.25.08.20.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 08:20:11 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v8 0/5] riscv: Allow user to set the satp mode Date: Wed, 25 Jan 2023 17:20:05 +0100 Message-Id: <20230125162010.1615787-1-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x433.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 16:20:16 -0000 This introduces new properties to allow the user to set the satp mode, see patch 3 for full syntax. In addition, it prevents cpus to boot in a satp mode they do not support (see patch 4). v8: - Remove useless !map check, Andrew - Add RB from Andrew v7: - Expand map to contain all valid modes, Andrew - Fix commit log for patch 3, Andrew - Remove is_32_bit argument from set_satp_mode_default, Andrew - Move and fixed comment, Andrew - Fix satp_mode_map_max in riscv_cpu_satp_mode_finalize which was set too early, Alex - Remove is_32_bit argument from set_satp_mode_max_supported, Andrew - Use satp_mode directly instead of a string in set_satp_mode_max_supported, Andrew - Swap the patch introducing supported bitmap and the patch that sets sv57 in the dt, Andrew - Add various RB from Andrew and Alistair, thanks v6: - Remove the valid_vm check in validate_vm and add it to the finalize function so that map already contains the constraint, Alex - Add forgotten mbare to satp_mode_from_str, Alex - Move satp mode properties handling to riscv_cpu_satp_mode_finalize, Andrew - Only add satp mode properties corresponding to the cpu, and then remove the check against valid_vm_1_10_32/64 in riscv_cpu_satp_mode_finalize, Andrew/Alistair/Alex - Move mmu-type setting to its own patch, Andrew - patch 5 is new and is a fix, Alex v5: - Simplify v4 implementation by leveraging valid_vm_1_10_32/64, as suggested by Andrew - Split the v4 patch into 2 patches as suggested by Andrew - Lot of other minor corrections, from Andrew - Set the satp mode N by disabling the satp mode N + 1 - Add a helper to set satp mode from a string, as suggested by Frank v4: - Use custom boolean properties instead of OnOffAuto properties, based on ARMVQMap, as suggested by Andrew v3: - Free sv_name as pointed by Bin - Replace satp-mode with boolean properties as suggested by Andrew - Removed RB from Atish as the patch considerably changed v2: - Use error_setg + return as suggested by Alistair - Add RB from Atish - Fixed checkpatch issues missed in v1 - Replaced Ludovic email address with the rivos one Alexandre Ghiti (5): riscv: Pass Object to register_cpu_props instead of DeviceState riscv: Change type of valid_vm_1_10_[32|64] to bool riscv: Allow user to set the satp mode riscv: Introduce satp mode hw capabilities riscv: Correctly set the device-tree entry 'mmu-type' hw/riscv/virt.c | 19 ++-- target/riscv/cpu.c | 247 +++++++++++++++++++++++++++++++++++++++++++-- target/riscv/cpu.h | 23 +++++ target/riscv/csr.c | 29 +++--- 4 files changed, 287 insertions(+), 31 deletions(-) -- 2.37.2 From MAILER-DAEMON Wed Jan 25 11:21:21 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKiWX-0001Tx-4b for mharc-qemu-riscv@gnu.org; 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[2.7.42.160]) by smtp.gmail.com with ESMTPSA id n13-20020a05600c500d00b003db2b81660esm2412943wmr.21.2023.01.25.08.21.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 08:21:12 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v8 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState Date: Wed, 25 Jan 2023 17:20:06 +0100 Message-Id: <20230125162010.1615787-2-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230125162010.1615787-1-alexghiti@rivosinc.com> References: <20230125162010.1615787-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 16:21:16 -0000 One can extract the DeviceState pointer from the Object pointer, so pass the Object for future commits to access other fields of Object. No functional changes intended. Signed-off-by: Alexandre Ghiti Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cc75ca7667..7181b34f86 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -200,7 +200,7 @@ static const char * const riscv_intr_names[] = { "reserved" }; -static void register_cpu_props(DeviceState *dev); +static void register_cpu_props(Object *obj); const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { @@ -238,7 +238,7 @@ static void riscv_any_cpu_init(Object *obj) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif set_priv_version(env, PRIV_VERSION_1_12_0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); } #if defined(TARGET_RISCV64) @@ -247,7 +247,7 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -280,7 +280,7 @@ static void rv128_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -290,7 +290,7 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -343,7 +343,7 @@ static void riscv_host_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, 0); #endif - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); } #endif @@ -1083,9 +1083,10 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_END_OF_LIST(), }; -static void register_cpu_props(DeviceState *dev) +static void register_cpu_props(Object *obj) { Property *prop; + DeviceState *dev = DEVICE(obj); for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); -- 2.37.2 From MAILER-DAEMON Wed Jan 25 11:22:24 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKiXY-0002FO-LF for mharc-qemu-riscv@gnu.org; Wed, 25 Jan 2023 11:22:24 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKiXW-0002Ex-OX for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 11:22:22 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKiXP-00034s-DP for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 11:22:22 -0500 Received: by mail-wr1-x42e.google.com with SMTP id q10so651343wrm.4 for ; Wed, 25 Jan 2023 08:22:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+TrQUDShuSlYfHT4YnhyHx3S9WBzIjkLW6v+vF/2lyw=; b=j78R8EUbLB+t+ezNAfwZm897Sxg2Lpfpjcme/JuW1DO+v6n0geq0aWdZz2IVDv+/gy 6QS4wmYrxSqXQN/kHeem6kMFx6mkNwHgD1ny8BYWGaOcjvuWjnU5VvratGRTqiL9zq9d wdCJxbSUZzru5Uq6RtegyChLAyeDE2otgocHdvr29uOksXBxmSMb8R6RY5+0wnjG28Rc AJFsFipxxDy/h9p1aVje3CUw9h3PLsUSO9G9qLPRWr5mJe+wvT9Pbad1MVwGoX3hJU2L 5dfSkv8C/i/qpy+bYYB0FGCvzuuGYtqz3ntdLx8/9OyLxq1Og2qhP1zKn+s6emSwiVTM TZNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+TrQUDShuSlYfHT4YnhyHx3S9WBzIjkLW6v+vF/2lyw=; b=gH0EERg5uTgZxHsU7ho6apHS0RuLh+2G/OzIkyqmPPGEQfwzZzTxdWtO07kW0tHPhp jE38WH7ul3b+CpVE8HBnFELc1S7P2KJnFl3B3zl7uHn8wvcC2/mETXsvsFLewUc4KrvQ XzdXdqzjM9BXTrBUmVL4qd+LWFA4ajOc6FtUbcghjrkQWD+dxkd7JAQQ7n0McK726kzK 4YN1HNmvUFAUfGciHl//VD6G/z72d7Mvhom/nAKLTHWY+0ijmvXwNgi7AbQhe9quqdAW 0oVxncQxX+w5BvZuhQ8pN/LodwnoPowc2k3eBvxUHqy7tLk8AMK/Rgng5AjN1BBdqFeM 1Qfw== X-Gm-Message-State: AO0yUKVI06c/U6uhR2vDpGy2XaRec3tnBs+vwmd2T7ktJYpIWbNitJEp q+/wzGYYQ6000eFG4wTMtd4+Og== X-Google-Smtp-Source: AK7set+eKx//tojLN+1VBYzk+Z/r9boFi+pPxRf0DZD17+Ic9PgxWkqEm4eKT6nBvUAMiX08p0cNaA== X-Received: by 2002:a5d:4f09:0:b0:2bf:b9b1:28d0 with SMTP id c9-20020a5d4f09000000b002bfb9b128d0mr2836441wru.66.1674663733944; Wed, 25 Jan 2023 08:22:13 -0800 (PST) Received: from alex-rivos.home (lfbn-lyo-1-450-160.w2-7.abo.wanadoo.fr. [2.7.42.160]) by smtp.gmail.com with ESMTPSA id l10-20020a05600012ca00b002bfb02153d1sm5128696wrx.45.2023.01.25.08.22.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 08:22:13 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v8 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool Date: Wed, 25 Jan 2023 17:20:07 +0100 Message-Id: <20230125162010.1615787-3-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230125162010.1615787-1-alexghiti@rivosinc.com> References: <20230125162010.1615787-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x42e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 16:22:23 -0000 This array is actually used as a boolean so swap its current char type to a boolean and at the same time, change the type of validate_vm to bool since it returns valid_vm_1_10_[32|64]. Suggested-by: Andrew Jones Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- target/riscv/csr.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0db2c233e5..6b157806a5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1117,16 +1117,16 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; static const target_ulong vsip_writable_mask = MIP_VSSIP; -static const char valid_vm_1_10_32[16] = { - [VM_1_10_MBARE] = 1, - [VM_1_10_SV32] = 1 +static const bool valid_vm_1_10_32[16] = { + [VM_1_10_MBARE] = true, + [VM_1_10_SV32] = true }; -static const char valid_vm_1_10_64[16] = { - [VM_1_10_MBARE] = 1, - [VM_1_10_SV39] = 1, - [VM_1_10_SV48] = 1, - [VM_1_10_SV57] = 1 +static const bool valid_vm_1_10_64[16] = { + [VM_1_10_MBARE] = true, + [VM_1_10_SV39] = true, + [VM_1_10_SV48] = true, + [VM_1_10_SV57] = true }; /* Machine Information Registers */ @@ -1209,7 +1209,7 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static int validate_vm(CPURISCVState *env, target_ulong vm) +static bool validate_vm(CPURISCVState *env, target_ulong vm) { if (riscv_cpu_mxl(env) == MXL_RV32) { return valid_vm_1_10_32[vm & 0xf]; @@ -2648,7 +2648,8 @@ static RISCVException read_satp(CPURISCVState *env, int csrno, static RISCVException write_satp(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong vm, mask; + target_ulong mask; + bool vm; if (!riscv_feature(env, RISCV_FEATURE_MMU)) { return RISCV_EXCP_NONE; -- 2.37.2 From MAILER-DAEMON Wed Jan 25 11:23:22 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKiYS-0002vE-Rn for mharc-qemu-riscv@gnu.org; Wed, 25 Jan 2023 11:23:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKiYQ-0002uh-Oq for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 11:23:18 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKiYO-0003JE-G4 for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 11:23:18 -0500 Received: by mail-wr1-x42f.google.com with SMTP id b7so17615791wrt.3 for ; Wed, 25 Jan 2023 08:23:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fwjN1wWFp+4NmnGfRneNohI94W/q5fZWyINEdyeiUKs=; b=PA0Nx04goQP+EQB6e8O0pEyDboEHKQG3ysyoItKZiq0ag77h8zJTjuyY3pfcOOHbkI 9lCE9/qp6871irN5Q95LhrlCt5Yp+XG50Xnid5aqPBC3mN6tm/pZIhVg1UrI8yQB6bhS XEKVnmI98J7NGdQCpWbozd8p6u/AbOqmz9ER14H3lC2qhuakyA73c0HmgyV5Wk2leglL VC5zKTIrO1N4hNqbvrfJnr5WU5qVBWI8UpYqSuLiB+uEDUgjKww0d6bs7dCTbFh4MHdC icx0hLO2TMnyT/473L3E6oXVOPmWYct6klDj8f1JuMhC51gi4/oxAb+2177YtB3dStHM Fnqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fwjN1wWFp+4NmnGfRneNohI94W/q5fZWyINEdyeiUKs=; b=n+PhJ+Ur/4Zi3/6s3sakuvnHmQO1omYNsTfj+cszCjOmhZoKwngkakzNVAF7L6ubxV 10GnztpV5ayat8GcqfSjVDVbXMYVqJ+AvzFzGhu9aH35eXFFLxrineCwJvh7/mCvwAKF NKAgxzmv1+xFmj0QfYjrEqwKUlgh15gxFHiIL6hbqrF0xwqRyy0GAe/ulwSO09v4dXfG RD15gtcWIUs6JoaSAVcMQ1tutcY4xrthGRbxBYqiVHNw73XNFulCjMwH3tTPYzb0ypy+ YDGdEZOG4mye1V9D6hIaLXBDEPSKf7Rv3UzM36nHVitn4Mzw979AysQO0JlxxOXBATs9 wFSg== X-Gm-Message-State: AFqh2koYq9SQFgFi5E4mviwE2WG+G8VqxjvvIHROwHRBTYssDoJmWAL3 3+Fpemu29D74wnhtR5AKudAYyw== X-Google-Smtp-Source: AMrXdXsL4DOUQH3+0FTYHMVK01NrKIVy5IMBixlHVrOxmaxqh51tJinsuRdc6iiOIju/fLiJ2DvStA== X-Received: by 2002:a5d:5b0d:0:b0:2bb:62bf:f5d1 with SMTP id bx13-20020a5d5b0d000000b002bb62bff5d1mr29946662wrb.29.1674663795050; Wed, 25 Jan 2023 08:23:15 -0800 (PST) Received: from alex-rivos.home (lfbn-lyo-1-450-160.w2-7.abo.wanadoo.fr. [2.7.42.160]) by smtp.gmail.com with ESMTPSA id q1-20020a5d5741000000b0029a06f11022sm4667718wrw.112.2023.01.25.08.23.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 08:23:14 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Ludovic Henry Subject: [PATCH v8 3/5] riscv: Allow user to set the satp mode Date: Wed, 25 Jan 2023 17:20:08 +0100 Message-Id: <20230125162010.1615787-4-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230125162010.1615787-1-alexghiti@rivosinc.com> References: <20230125162010.1615787-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x42f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 16:23:19 -0000 RISC-V specifies multiple sizes for addressable memory and Linux probes for the machine's support at startup via the satp CSR register (done in csr.c:validate_vm). As per the specification, sv64 must support sv57, which in turn must support sv48...etc. So we can restrict machine support by simply setting the "highest" supported mode and the bare mode is always supported. You can set the satp mode using the new properties "sv32", "sv39", "sv48", "sv57" and "sv64" as follows: -cpu rv64,sv57=on # Linux will boot using sv57 scheme -cpu rv64,sv39=on # Linux will boot using sv39 scheme -cpu rv64,sv57=off # Linux will boot using sv48 scheme -cpu rv64 # Linux will boot using sv57 scheme by default We take the highest level set by the user: -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme We make sure that invalid configurations are rejected: -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are # enabled We accept "redundant" configurations: -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme And contradictory configurations: -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme Co-Developed-by: Ludovic Henry Signed-off-by: Ludovic Henry Signed-off-by: Alexandre Ghiti --- target/riscv/cpu.c | 206 +++++++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 19 +++++ target/riscv/csr.c | 12 ++- 3 files changed, 230 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7181b34f86..54494a72be 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -27,6 +27,7 @@ #include "time_helper.h" #include "exec/exec-all.h" #include "qapi/error.h" +#include "qapi/visitor.h" #include "qemu/error-report.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" @@ -229,6 +230,81 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) env->vext_ver = vext_ver; } +static uint8_t satp_mode_from_str(const char *satp_mode_str) +{ + if (!strncmp(satp_mode_str, "mbare", 5)) { + return VM_1_10_MBARE; + } + + if (!strncmp(satp_mode_str, "sv32", 4)) { + return VM_1_10_SV32; + } + + if (!strncmp(satp_mode_str, "sv39", 4)) { + return VM_1_10_SV39; + } + + if (!strncmp(satp_mode_str, "sv48", 4)) { + return VM_1_10_SV48; + } + + if (!strncmp(satp_mode_str, "sv57", 4)) { + return VM_1_10_SV57; + } + + if (!strncmp(satp_mode_str, "sv64", 4)) { + return VM_1_10_SV64; + } + + g_assert_not_reached(); +} + +uint8_t satp_mode_max_from_map(uint32_t map) +{ + /* map here has at least one bit set, so no problem with clz */ + return 31 - __builtin_clz(map); +} + +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) +{ + if (is_32_bit) { + switch (satp_mode) { + case VM_1_10_SV32: + return "sv32"; + case VM_1_10_MBARE: + return "none"; + } + } else { + switch (satp_mode) { + case VM_1_10_SV64: + return "sv64"; + case VM_1_10_SV57: + return "sv57"; + case VM_1_10_SV48: + return "sv48"; + case VM_1_10_SV39: + return "sv39"; + case VM_1_10_MBARE: + return "none"; + } + } + + g_assert_not_reached(); +} + +/* Sets the satp mode to the max supported */ +static void set_satp_mode_default(RISCVCPU *cpu) +{ + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; + + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { + cpu->cfg.satp_mode.map |= + (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); + } else { + cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); + } +} + static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; @@ -619,6 +695,82 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) } } +static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) +{ + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; + uint8_t satp_mode_max; + + if (cpu->cfg.satp_mode.map == 0) { + if (cpu->cfg.satp_mode.init == 0) { + /* If unset by the user, we fallback to the default satp mode. */ + set_satp_mode_default(cpu); + } else { + /* + * Find the lowest level that was disabled and then enable the + * first valid level below which can be found in + * valid_vm_1_10_32/64. + */ + for (int i = 1; i < 16; ++i) { + if ((cpu->cfg.satp_mode.init & (1 << i)) && + valid_vm[i]) { + for (int j = i - 1; j >= 0; --j) { + if (valid_vm[j]) { + cpu->cfg.satp_mode.map |= (1 << j); + break; + } + } + break; + } + } + } + } + + /* Make sure the configuration asked is supported by qemu */ + for (int i = 0; i < 16; ++i) { + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { + error_setg(errp, "satp_mode %s is not valid", + satp_mode_str(i, rv32)); + return; + } + } + + /* + * Make sure the user did not ask for an invalid configuration as per + * the specification. + */ + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); + + if (!rv32) { + for (int i = satp_mode_max - 1; i >= 0; --i) { + if (!(cpu->cfg.satp_mode.map & (1 << i)) && + (cpu->cfg.satp_mode.init & (1 << i)) && + valid_vm[i]) { + error_setg(errp, "cannot disable %s satp mode if %s " + "is enabled", satp_mode_str(i, false), + satp_mode_str(satp_mode_max, false)); + return; + } + } + } + + /* Finally expand the map so that all valid modes are set */ + for (int i = satp_mode_max - 1; i >= 0; --i) { + cpu->cfg.satp_mode.map |= (1 << i); + } +} + +static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) +{ + Error *local_err = NULL; + + riscv_cpu_satp_mode_finalize(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } +} + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -919,6 +1071,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } #endif + riscv_cpu_finalize_features(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + riscv_cpu_register_gdb_regs_for_features(cs); qemu_init_vcpu(cs); @@ -927,6 +1085,52 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) mcc->parent_realize(dev, errp); } +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVSATPMap *satp_map = opaque; + uint8_t satp = satp_mode_from_str(name); + bool value; + + value = (satp_map->map & (1 << satp)); + + visit_type_bool(v, name, &value, errp); +} + +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVSATPMap *satp_map = opaque; + uint8_t satp = satp_mode_from_str(name); + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + satp_map->map = deposit32(satp_map->map, satp, 1, value); + satp_map->init |= 1 << satp; +} + +static void riscv_add_satp_mode_properties(Object *obj) +{ + RISCVCPU *cpu = RISCV_CPU(obj); + + if (cpu->env.misa_mxl == MXL_RV32) { + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + } else { + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + } +} + #ifndef CONFIG_USER_ONLY static void riscv_cpu_set_irq(void *opaque, int irq, int level) { @@ -1091,6 +1295,8 @@ static void register_cpu_props(Object *obj) for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } + + riscv_add_satp_mode_properties(obj); } static Property riscv_cpu_properties[] = { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f5609b62a2..e37177db5c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -27,6 +27,7 @@ #include "qom/object.h" #include "qemu/int128.h" #include "cpu_bits.h" +#include "qapi/qapi-types-common.h" #define TCG_GUEST_DEFAULT_MO 0 @@ -413,6 +414,17 @@ struct RISCVCPUClass { ResettablePhases parent_phases; }; +/* + * map is a 16-bit bitmap: the most significant set bit in map is the maximum + * satp mode that is supported. + * + * init is a 16-bit bitmap used to make sure the user selected a correct + * configuration as per the specification. + */ +typedef struct { + uint16_t map, init; +} RISCVSATPMap; + struct RISCVCPUConfig { bool ext_i; bool ext_e; @@ -488,6 +500,8 @@ struct RISCVCPUConfig { bool debug; bool short_isa_string; + + RISCVSATPMap satp_mode; }; typedef struct RISCVCPUConfig RISCVCPUConfig; @@ -794,9 +808,14 @@ enum riscv_pmu_event_idx { /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; +extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; + void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); +uint8_t satp_mode_max_from_map(uint32_t map); +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); + #endif /* RISCV_CPU_H */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6b157806a5..3c02055825 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1117,12 +1117,12 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; static const target_ulong vsip_writable_mask = MIP_VSSIP; -static const bool valid_vm_1_10_32[16] = { +const bool valid_vm_1_10_32[16] = { [VM_1_10_MBARE] = true, [VM_1_10_SV32] = true }; -static const bool valid_vm_1_10_64[16] = { +const bool valid_vm_1_10_64[16] = { [VM_1_10_MBARE] = true, [VM_1_10_SV39] = true, [VM_1_10_SV48] = true, @@ -1211,11 +1211,9 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, static bool validate_vm(CPURISCVState *env, target_ulong vm) { - if (riscv_cpu_mxl(env) == MXL_RV32) { - return valid_vm_1_10_32[vm & 0xf]; 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[2.7.42.160]) by smtp.gmail.com with ESMTPSA id bi24-20020a05600c3d9800b003d1d5a83b2esm2228191wmb.35.2023.01.25.08.24.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 08:24:15 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v8 4/5] riscv: Introduce satp mode hw capabilities Date: Wed, 25 Jan 2023 17:20:09 +0100 Message-Id: <20230125162010.1615787-5-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230125162010.1615787-1-alexghiti@rivosinc.com> References: <20230125162010.1615787-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x334.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 16:24:21 -0000 Currently, the max satp mode is set with the only constraint that it must be implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. But we actually need to add another level of constraint: what the hw is actually capable of, because currently, a linux booting on a sifive-u54 boots in sv57 mode which is incompatible with the cpu's sv39 max capability. So add a new bitmap to RISCVSATPMap which contains this capability and initialize it in every XXX_cpu_init. Finally: - valid_vm_1_10_[32|64] constrains which satp mode the CPU can use - the CPU hw capabilities constrains what the user may select - the user's selection then constrains what's available to the guest OS. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 74 +++++++++++++++++++++++++++++++--------------- target/riscv/cpu.h | 8 +++-- 2 files changed, 56 insertions(+), 26 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 54494a72be..e7e1fb96dc 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -292,26 +292,36 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) g_assert_not_reached(); } -/* Sets the satp mode to the max supported */ -static void set_satp_mode_default(RISCVCPU *cpu) +static void set_satp_mode_max_supported(RISCVCPU *cpu, + uint8_t satp_mode) { bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { - cpu->cfg.satp_mode.map |= - (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); - } else { - cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); + for (int i = 0; i <= satp_mode; ++i) { + if (valid_vm[i]) { + cpu->cfg.satp_mode.supported |= (1 << i); + } } } +/* Sets the satp mode to the max supported */ +static void set_satp_mode_default(RISCVCPU *cpu) +{ + cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; +} + static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + #if defined(TARGET_RISCV32) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_satp_mode_max_supported(cpu, VM_1_10_SV32); #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_satp_mode_max_supported(cpu, VM_1_10_SV57); #endif set_priv_version(env, PRIV_VERSION_1_12_0); register_cpu_props(obj); @@ -321,18 +331,24 @@ static void riscv_any_cpu_init(Object *obj) static void rv64_base_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); + set_satp_mode_max_supported(cpu, VM_1_10_SV57); } static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); + set_satp_mode_max_supported(cpu, VM_1_10_SV39); } static void rv64_sifive_e_cpu_init(Object *obj) @@ -343,6 +359,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); } static void rv128_base_cpu_init(Object *obj) @@ -354,11 +371,13 @@ static void rv128_base_cpu_init(Object *obj) exit(EXIT_FAILURE); } CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); + set_satp_mode_max_supported(cpu, VM_1_10_SV57); } #else static void rv32_base_cpu_init(Object *obj) @@ -369,13 +388,17 @@ static void rv32_base_cpu_init(Object *obj) register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); + set_satp_mode_max_supported(cpu, VM_1_10_SV32); } static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); + set_satp_mode_max_supported(cpu, VM_1_10_SV32); } static void rv32_sifive_e_cpu_init(Object *obj) @@ -386,6 +409,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); } static void rv32_ibex_cpu_init(Object *obj) @@ -396,6 +420,7 @@ static void rv32_ibex_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.mmu = false; + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); cpu->cfg.epmp = true; } @@ -407,6 +432,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); } #endif @@ -698,8 +724,9 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) { bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; - const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; - uint8_t satp_mode_max; + uint8_t satp_mode_map_max; + uint8_t satp_mode_supported_max = + satp_mode_max_from_map(cpu->cfg.satp_mode.supported); if (cpu->cfg.satp_mode.map == 0) { if (cpu->cfg.satp_mode.init == 0) { @@ -713,9 +740,9 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) */ for (int i = 1; i < 16; ++i) { if ((cpu->cfg.satp_mode.init & (1 << i)) && - valid_vm[i]) { + (cpu->cfg.satp_mode.supported & (1 << i))) { for (int j = i - 1; j >= 0; --j) { - if (valid_vm[j]) { + if (cpu->cfg.satp_mode.supported & (1 << j)) { cpu->cfg.satp_mode.map |= (1 << j); break; } @@ -726,36 +753,35 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) } } - /* Make sure the configuration asked is supported by qemu */ - for (int i = 0; i < 16; ++i) { - if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { - error_setg(errp, "satp_mode %s is not valid", - satp_mode_str(i, rv32)); - return; - } + satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); + + /* Make sure the user asked for a supported configuration (HW and qemu) */ + if (satp_mode_map_max > satp_mode_supported_max) { + error_setg(errp, "satp_mode %s is higher than hw max capability %s", + satp_mode_str(satp_mode_map_max, rv32), + satp_mode_str(satp_mode_supported_max, rv32)); + return; } /* * Make sure the user did not ask for an invalid configuration as per * the specification. */ - satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); - if (!rv32) { - for (int i = satp_mode_max - 1; i >= 0; --i) { + for (int i = satp_mode_map_max - 1; i >= 0; --i) { if (!(cpu->cfg.satp_mode.map & (1 << i)) && (cpu->cfg.satp_mode.init & (1 << i)) && - valid_vm[i]) { + (cpu->cfg.satp_mode.supported & (1 << i))) { error_setg(errp, "cannot disable %s satp mode if %s " "is enabled", satp_mode_str(i, false), - satp_mode_str(satp_mode_max, false)); + satp_mode_str(satp_mode_map_max, false)); return; } } } /* Finally expand the map so that all valid modes are set */ - for (int i = satp_mode_max - 1; i >= 0; --i) { + for (int i = satp_mode_map_max - 1; i >= 0; --i) { cpu->cfg.satp_mode.map |= (1 << i); } } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e37177db5c..b591122099 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -416,13 +416,17 @@ struct RISCVCPUClass { /* * map is a 16-bit bitmap: the most significant set bit in map is the maximum - * satp mode that is supported. + * satp mode that is supported. It may be chosen by the user and must respect + * what qemu implements (valid_1_10_32/64) and what the hw is capable of + * (supported bitmap below). * * init is a 16-bit bitmap used to make sure the user selected a correct * configuration as per the specification. + * + * supported is a 16-bit bitmap used to reflect the hw capabilities. */ typedef struct { - uint16_t map, init; + uint16_t map, init, supported; } RISCVSATPMap; struct RISCVCPUConfig { -- 2.37.2 From MAILER-DAEMON Wed Jan 25 11:25:21 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKiaP-0004Sk-Gx for mharc-qemu-riscv@gnu.org; Wed, 25 Jan 2023 11:25:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKiaO-0004Rc-3U for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 11:25:20 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKiaM-0003hU-AH for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 11:25:19 -0500 Received: by mail-wm1-x335.google.com with SMTP id iv8-20020a05600c548800b003db04a0a46bso2950906wmb.0 for ; Wed, 25 Jan 2023 08:25:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IRWvpmPRHrukoIwIrFR+ERY535b3mU7yJB9xTFeVSNc=; b=u8xwkJQ431YoZL9zTSlf1eOJDtGIIjBweMr0a8u+YXfX2JbFXYaVombwMOQtNTclrS rCxXTpNygppUn8EWX/RbGRg9CtoJx8QupG2lK5SW6Jus4doSs3SalFuUs85N+IaXq7Ko O9lwFKWLfNM2hpWOzSLyenqpiIYX7etVFy/X74tjRzHWdOfuNXQPgMK1b8zeQm7ng1yG 9MWZ9YuRq+CS+ybjJw7+5QpP2WA8gvIsKq09u4hGpIoGnc8Sej1CdO3cuuAH5TrBMbaS 4NmF0itFzGiS2serzNBCfauGGIglJHRFlwZwiypG08qSKxwHuuJtF8Pq7kZfPeVqyw7K nlYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IRWvpmPRHrukoIwIrFR+ERY535b3mU7yJB9xTFeVSNc=; b=ughz/tWln/F2XiAgSkYxmFOalYDL7KJ1K6fJsINfg7A/iRmZROErEwpz12EqcN6vwe DGHftFfo6AOpf03xujfOaP86jsHLDPKjuL5c/pweYGTBa+NiwQ1vVpWlDM9DhbGYk+3z p95BZKHRZoYrK6Ql4zCkfnv+3tg8kH8/bi7V+VzfjVtleEte2bihZFtgnmkisKaPegVe 2/UPpmDXrkZeYh1g4S1FffJYKrjvfgML0O/boVlhIdXP/CYerXbcxy1dx8HKjsx4TDXf RuUB73gjxAsbw4GFIE+XaAjrcXaVYBk3zOAXB+d2Uzrn3hOuEiF0LZgrgjZjNmHkb3ql 757g== X-Gm-Message-State: AFqh2kpJmgBq8i7UbwfpvuOTlGQLoSObfg+czPBTylX0HKmyc59IoPbA LLne8dBreP3BUm/3QagSK86GRA== X-Google-Smtp-Source: AMrXdXt93mW9IbCg+gH994ue2/kTMRkVjJ6YCxiJpQvjqNbQnGrZSUTGjvCz4nq4ypH7/yfIC1UvJg== X-Received: by 2002:a05:600c:54eb:b0:3da:2090:d404 with SMTP id jb11-20020a05600c54eb00b003da2090d404mr32770630wmb.18.1674663916789; Wed, 25 Jan 2023 08:25:16 -0800 (PST) Received: from alex-rivos.home (lfbn-lyo-1-450-160.w2-7.abo.wanadoo.fr. [2.7.42.160]) by smtp.gmail.com with ESMTPSA id v10-20020a05600c12ca00b003d9df9e59c4sm2180076wmd.37.2023.01.25.08.25.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 08:25:16 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v8 5/5] riscv: Correctly set the device-tree entry 'mmu-type' Date: Wed, 25 Jan 2023 17:20:10 +0100 Message-Id: <20230125162010.1615787-6-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230125162010.1615787-1-alexghiti@rivosinc.com> References: <20230125162010.1615787-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x335.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 16:25:20 -0000 The 'mmu-type' should reflect what the hardware is capable of so use the new satp_mode field in RISCVCPUConfig to do that. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis --- hw/riscv/virt.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 94ff2a1584..48d034a5f7 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -228,7 +228,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, int cpu; uint32_t cpu_phandle; MachineState *mc = MACHINE(s); - char *name, *cpu_name, *core_name, *intc_name; + uint8_t satp_mode_max; + char *name, *cpu_name, *core_name, *intc_name, *sv_name; for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { cpu_phandle = (*phandle)++; @@ -236,14 +237,14 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(mc->fdt, cpu_name); - if (riscv_feature(&s->soc[socket].harts[cpu].env, - RISCV_FEATURE_MMU)) { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", - (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); - } else { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", - "riscv,none"); - } + + satp_mode_max = satp_mode_max_from_map( + s->soc[socket].harts[cpu].cfg.satp_mode.map); + sv_name = g_strdup_printf("riscv,%s", + satp_mode_str(satp_mode_max, is_32_bit)); + qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", sv_name); + g_free(sv_name); + name = riscv_isa_string(&s->soc[socket].harts[cpu]); qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); g_free(name); -- 2.37.2 From MAILER-DAEMON Wed Jan 25 11:52:46 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKj0w-0000rw-P5 for mharc-qemu-riscv@gnu.org; Wed, 25 Jan 2023 11:52:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKj0w-0000rW-1e for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 11:52:46 -0500 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKj0t-00083h-Qi for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 11:52:45 -0500 Received: by mail-ej1-x632.google.com with SMTP id bk15so49240343ejb.9 for ; Wed, 25 Jan 2023 08:52:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=MI9fyJVZC93wFVxaBakNIon6Pku11HQK4m7rdJJ9vyQ=; b=ARDCQ2I+fIA4x2I0IDiwsmkp99CZmQbwCKnEx+QIOzFPey/gbNivY13HcQoV0fLAfo 7aEvR7IWaBC7nXhcW9WHrwNjOex1bVy5pUclPCNgkZIsGNAVPQrTJbydHVtZKvQowWXH F8kYY9Q3oQH900XjWbC4XyQZaKv/Bv9Y3bNNTI+yFcuKEqUTepteclRGE5VrdMQNU5y9 ryslbe3RUaXqK6mwaVuc+/kiol2mtRm2PoADTVIF0xHkq7RRg8sW3PXfUJ9G1bYJBMK5 xNITAy9J+yPN/L4rr8uH1PndtiB4o3KNy9ot24rO8n8lSbKi6xgr1Wqi25U/FyGnXfBN UBRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=MI9fyJVZC93wFVxaBakNIon6Pku11HQK4m7rdJJ9vyQ=; b=f1l/ihzCgZwT40VPObjNj+Dp0WwV3aZ7+gkSokRl6D8EiKOQbCeFkMZAqTLz59lvRU GKnLfx0MP0iAcV9PwshCsXY43b9jRICqBPaa3qxJye8vNPQYaM+GZXKrLF0DOBIsYuOR lQ/5ytfY2KoAKuUQh6DD47dIIy37taDDhGe+leZWcvy8VUZ8jnhGLysE2Z9G0O5mmhcl Ohls6rkthqnyfYCs0M0rcUqjvY05af+d6LNhcNzpuSIZBnVd0jGJewH2c1CJSlHpE69N 3HtR5tcgz0aKOV4p9w1cP8jpgmdkRDPapCoGDTDX/VzvpWSrCuLBEUzVY13AsP124HCW sFbg== X-Gm-Message-State: AFqh2koukdynfNM9zqPIaU9yiwbXcPK2N1sAYAAL3TijBYGqt3kpO6/8 B+tFx1KXwqATw1TdnDb+wnv2Aw== X-Google-Smtp-Source: AMrXdXuKP2DDTHESclTAs4oqPADulxTabS4yvLke8wW0QIlcg0xUZKQLLt6tMrXIawHCjIGMIxauDA== X-Received: by 2002:a17:906:3795:b0:84d:1366:c74d with SMTP id n21-20020a170906379500b0084d1366c74dmr29174060ejc.63.1674665560950; Wed, 25 Jan 2023 08:52:40 -0800 (PST) Received: from localhost (cst2-173-16.cust.vodafone.cz. [31.30.173.16]) by smtp.gmail.com with ESMTPSA id lv3-20020a170906bc8300b0087848a5daf5sm244008ejb.225.2023.01.25.08.52.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 08:52:40 -0800 (PST) Date: Wed, 25 Jan 2023 17:52:39 +0100 From: Andrew Jones To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Subject: Re: [PATCH v8 3/5] riscv: Allow user to set the satp mode Message-ID: <20230125165239.tmooowvwq7zez76y@orel> References: <20230125162010.1615787-1-alexghiti@rivosinc.com> <20230125162010.1615787-4-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230125162010.1615787-4-alexghiti@rivosinc.com> Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=ajones@ventanamicro.com; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 16:52:46 -0000 On Wed, Jan 25, 2023 at 05:20:08PM +0100, Alexandre Ghiti wrote: > RISC-V specifies multiple sizes for addressable memory and Linux probes for > the machine's support at startup via the satp CSR register (done in > csr.c:validate_vm). > > As per the specification, sv64 must support sv57, which in turn must > support sv48...etc. So we can restrict machine support by simply setting the > "highest" supported mode and the bare mode is always supported. > > You can set the satp mode using the new properties "sv32", "sv39", "sv48", > "sv57" and "sv64" as follows: > -cpu rv64,sv57=on # Linux will boot using sv57 scheme > -cpu rv64,sv39=on # Linux will boot using sv39 scheme > -cpu rv64,sv57=off # Linux will boot using sv48 scheme > -cpu rv64 # Linux will boot using sv57 scheme by default > > We take the highest level set by the user: > -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme > > We make sure that invalid configurations are rejected: > -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are > # enabled > > We accept "redundant" configurations: > -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme > > And contradictory configurations: > -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme > > Co-Developed-by: Ludovic Henry > Signed-off-by: Ludovic Henry > Signed-off-by: Alexandre Ghiti > --- > target/riscv/cpu.c | 206 +++++++++++++++++++++++++++++++++++++++++++++ > target/riscv/cpu.h | 19 +++++ > target/riscv/csr.c | 12 ++- > 3 files changed, 230 insertions(+), 7 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 7181b34f86..54494a72be 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -27,6 +27,7 @@ > #include "time_helper.h" > #include "exec/exec-all.h" > #include "qapi/error.h" > +#include "qapi/visitor.h" > #include "qemu/error-report.h" > #include "hw/qdev-properties.h" > #include "migration/vmstate.h" > @@ -229,6 +230,81 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) > env->vext_ver = vext_ver; > } > > +static uint8_t satp_mode_from_str(const char *satp_mode_str) > +{ > + if (!strncmp(satp_mode_str, "mbare", 5)) { > + return VM_1_10_MBARE; > + } > + > + if (!strncmp(satp_mode_str, "sv32", 4)) { > + return VM_1_10_SV32; > + } > + > + if (!strncmp(satp_mode_str, "sv39", 4)) { > + return VM_1_10_SV39; > + } > + > + if (!strncmp(satp_mode_str, "sv48", 4)) { > + return VM_1_10_SV48; > + } > + > + if (!strncmp(satp_mode_str, "sv57", 4)) { > + return VM_1_10_SV57; > + } > + > + if (!strncmp(satp_mode_str, "sv64", 4)) { > + return VM_1_10_SV64; > + } > + > + g_assert_not_reached(); > +} > + > +uint8_t satp_mode_max_from_map(uint32_t map) > +{ > + /* map here has at least one bit set, so no problem with clz */ > + return 31 - __builtin_clz(map); > +} > + > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > +{ > + if (is_32_bit) { > + switch (satp_mode) { > + case VM_1_10_SV32: > + return "sv32"; > + case VM_1_10_MBARE: > + return "none"; > + } > + } else { > + switch (satp_mode) { > + case VM_1_10_SV64: > + return "sv64"; > + case VM_1_10_SV57: > + return "sv57"; > + case VM_1_10_SV48: > + return "sv48"; > + case VM_1_10_SV39: > + return "sv39"; > + case VM_1_10_MBARE: > + return "none"; > + } > + } > + > + g_assert_not_reached(); > +} > + > +/* Sets the satp mode to the max supported */ > +static void set_satp_mode_default(RISCVCPU *cpu) > +{ > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > + > + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > + cpu->cfg.satp_mode.map |= > + (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); > + } else { > + cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > + } > +} > + > static void riscv_any_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > @@ -619,6 +695,82 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > } > } > > +static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > +{ > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > + uint8_t satp_mode_max; > + > + if (cpu->cfg.satp_mode.map == 0) { > + if (cpu->cfg.satp_mode.init == 0) { > + /* If unset by the user, we fallback to the default satp mode. */ > + set_satp_mode_default(cpu); > + } else { > + /* > + * Find the lowest level that was disabled and then enable the > + * first valid level below which can be found in > + * valid_vm_1_10_32/64. > + */ > + for (int i = 1; i < 16; ++i) { > + if ((cpu->cfg.satp_mode.init & (1 << i)) && > + valid_vm[i]) { nit: Could have brought this valid_vm[i] up now that everything fits on one line. > + for (int j = i - 1; j >= 0; --j) { > + if (valid_vm[j]) { > + cpu->cfg.satp_mode.map |= (1 << j); > + break; > + } > + } > + break; > + } > + } > + } > + } > + > + /* Make sure the configuration asked is supported by qemu */ > + for (int i = 0; i < 16; ++i) { > + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > + error_setg(errp, "satp_mode %s is not valid", > + satp_mode_str(i, rv32)); > + return; > + } > + } > + > + /* > + * Make sure the user did not ask for an invalid configuration as per > + * the specification. > + */ > + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > + > + if (!rv32) { > + for (int i = satp_mode_max - 1; i >= 0; --i) { > + if (!(cpu->cfg.satp_mode.map & (1 << i)) && > + (cpu->cfg.satp_mode.init & (1 << i)) && > + valid_vm[i]) { > + error_setg(errp, "cannot disable %s satp mode if %s " > + "is enabled", satp_mode_str(i, false), > + satp_mode_str(satp_mode_max, false)); > + return; > + } > + } > + } > + > + /* Finally expand the map so that all valid modes are set */ > + for (int i = satp_mode_max - 1; i >= 0; --i) { > + cpu->cfg.satp_mode.map |= (1 << i); > + } > +} > + > +static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > +{ > + Error *local_err = NULL; > + > + riscv_cpu_satp_mode_finalize(cpu, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > + } > +} > + > static void riscv_cpu_realize(DeviceState *dev, Error **errp) > { > CPUState *cs = CPU(dev); > @@ -919,6 +1071,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > #endif > > + riscv_cpu_finalize_features(cpu, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > + } > + > riscv_cpu_register_gdb_regs_for_features(cs); > > qemu_init_vcpu(cs); > @@ -927,6 +1085,52 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > mcc->parent_realize(dev, errp); > } > > +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + RISCVSATPMap *satp_map = opaque; > + uint8_t satp = satp_mode_from_str(name); > + bool value; > + > + value = (satp_map->map & (1 << satp)); > + > + visit_type_bool(v, name, &value, errp); > +} > + > +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) > +{ > + RISCVSATPMap *satp_map = opaque; > + uint8_t satp = satp_mode_from_str(name); > + bool value; > + > + if (!visit_type_bool(v, name, &value, errp)) { > + return; > + } > + > + satp_map->map = deposit32(satp_map->map, satp, 1, value); > + satp_map->init |= 1 << satp; > +} > + > +static void riscv_add_satp_mode_properties(Object *obj) > +{ > + RISCVCPU *cpu = RISCV_CPU(obj); > + > + if (cpu->env.misa_mxl == MXL_RV32) { > + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + } else { > + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + } > +} > + > #ifndef CONFIG_USER_ONLY > static void riscv_cpu_set_irq(void *opaque, int irq, int level) > { > @@ -1091,6 +1295,8 @@ static void register_cpu_props(Object *obj) > for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > qdev_property_add_static(dev, prop); > } > + > + riscv_add_satp_mode_properties(obj); > } > > static Property riscv_cpu_properties[] = { > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index f5609b62a2..e37177db5c 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -27,6 +27,7 @@ > #include "qom/object.h" > #include "qemu/int128.h" > #include "cpu_bits.h" > +#include "qapi/qapi-types-common.h" > > #define TCG_GUEST_DEFAULT_MO 0 > > @@ -413,6 +414,17 @@ struct RISCVCPUClass { > ResettablePhases parent_phases; > }; > > +/* > + * map is a 16-bit bitmap: the most significant set bit in map is the maximum > + * satp mode that is supported. > + * > + * init is a 16-bit bitmap used to make sure the user selected a correct > + * configuration as per the specification. > + */ > +typedef struct { > + uint16_t map, init; > +} RISCVSATPMap; > + > struct RISCVCPUConfig { > bool ext_i; > bool ext_e; > @@ -488,6 +500,8 @@ struct RISCVCPUConfig { > bool debug; > > bool short_isa_string; > + > + RISCVSATPMap satp_mode; > }; > > typedef struct RISCVCPUConfig RISCVCPUConfig; > @@ -794,9 +808,14 @@ enum riscv_pmu_event_idx { > /* CSR function table */ > extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; > > +extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; > + > void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); > void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); > > void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); > > +uint8_t satp_mode_max_from_map(uint32_t map); > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); > + > #endif /* RISCV_CPU_H */ > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 6b157806a5..3c02055825 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1117,12 +1117,12 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; > static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; > static const target_ulong vsip_writable_mask = MIP_VSSIP; > > -static const bool valid_vm_1_10_32[16] = { > +const bool valid_vm_1_10_32[16] = { > [VM_1_10_MBARE] = true, > [VM_1_10_SV32] = true > }; > > -static const bool valid_vm_1_10_64[16] = { > +const bool valid_vm_1_10_64[16] = { > [VM_1_10_MBARE] = true, > [VM_1_10_SV39] = true, > [VM_1_10_SV48] = true, > @@ -1211,11 +1211,9 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, > > static bool validate_vm(CPURISCVState *env, target_ulong vm) > { > - if (riscv_cpu_mxl(env) == MXL_RV32) { > - return valid_vm_1_10_32[vm & 0xf]; > - } else { > - return valid_vm_1_10_64[vm & 0xf]; > - } > + RISCVCPU *cpu = RISCV_CPU(env_cpu(env)); > + > + return ((vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map)); > } > > static RISCVException write_mstatus(CPURISCVState *env, int csrno, > -- > 2.37.2 > Other than the minor nit Reviewed-by: Andrew Jones Thanks, drew From MAILER-DAEMON Wed Jan 25 16:12:34 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKn4M-0005zO-Cc for mharc-qemu-riscv@gnu.org; Wed, 25 Jan 2023 16:12:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKn4K-0005x8-NK for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 16:12:32 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKn4G-0007tg-QH for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 16:12:32 -0500 Received: by mail-wm1-x332.google.com with SMTP id fl11-20020a05600c0b8b00b003daf72fc844so2122996wmb.0 for ; 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Wed, 25 Jan 2023 13:12:27 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id ip6-20020a05600ca68600b003d04e4ed873sm2820187wmb.22.2023.01.25.13.12.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 13:12:26 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 0222A1FFB7; Wed, 25 Jan 2023 21:12:26 +0000 (GMT) References: <20230108023719.2466341-1-richard.henderson@linaro.org> <20230108023719.2466341-7-richard.henderson@linaro.org> User-agent: mu4e 1.9.16; emacs 29.0.60 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Daniel Henrique Barboza , qemu-devel@nongnu.org Subject: Re: [PATCH v4 06/36] tcg: Introduce tcg_target_call_oarg_reg Date: Wed, 25 Jan 2023 21:09:23 +0000 In-reply-to: <20230108023719.2466341-7-richard.henderson@linaro.org> Message-ID: <877cxaqpxi.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 21:12:32 -0000 Richard Henderson writes: > Replace the flat array tcg_target_call_oarg_regs[] with > a function call including the TCGCallReturnKind. > > Reviewed-by: Daniel Henrique Barboza > Signed-off-by: Richard Henderson > --- > tcg/tcg.c | 9 ++++++--- > tcg/aarch64/tcg-target.c.inc | 10 +++++++--- > tcg/arm/tcg-target.c.inc | 10 +++++++--- > tcg/i386/tcg-target.c.inc | 16 ++++++++++------ > tcg/loongarch64/tcg-target.c.inc | 10 ++++++---- > tcg/mips/tcg-target.c.inc | 10 ++++++---- > tcg/ppc/tcg-target.c.inc | 10 ++++++---- > tcg/riscv/tcg-target.c.inc | 10 ++++++---- > tcg/s390x/tcg-target.c.inc | 9 ++++++--- > tcg/sparc64/tcg-target.c.inc | 12 ++++++------ > tcg/tci/tcg-target.c.inc | 12 ++++++------ > 11 files changed, 72 insertions(+), 46 deletions(-) > > diff --git a/tcg/tcg.c b/tcg/tcg.c > index 93d1331f93..092cdaf422 100644 > --- a/tcg/tcg.c > +++ b/tcg/tcg.c > @@ -148,6 +148,7 @@ static bool tcg_out_sti(TCGContext *s, TCGType type, = TCGArg val, > TCGReg base, intptr_t ofs); > static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, > const TCGHelperInfo *info); > +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot); > static bool tcg_target_const_match(int64_t val, TCGType type, int ct); > #ifdef TCG_TARGET_NEED_LDST_LABELS > static int tcg_out_ldst_finalize(TCGContext *s); > @@ -719,14 +720,16 @@ static void init_call_layout(TCGHelperInfo *info) > case dh_typecode_s64: > info->nr_out =3D 64 / TCG_TARGET_REG_BITS; > info->out_kind =3D TCG_CALL_RET_NORMAL; > - assert(info->nr_out <=3D ARRAY_SIZE(tcg_target_call_oarg_regs)); > + /* Query the last register now to trigger any assert early. */ > + tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); > break; > case dh_typecode_i128: > info->nr_out =3D 128 / TCG_TARGET_REG_BITS; > info->out_kind =3D TCG_CALL_RET_NORMAL; /* TODO */ > switch (/* TODO */ TCG_CALL_RET_NORMAL) { > case TCG_CALL_RET_NORMAL: > - assert(info->nr_out <=3D ARRAY_SIZE(tcg_target_call_oarg_reg= s)); > + /* Query the last register now to trigger any assert early. = */ > + tcg_target_call_oarg_reg(info->out_kind, info->nr_out - 1); > break; > case TCG_CALL_RET_BY_REF: > /* > @@ -4563,7 +4566,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp= *op) > case TCG_CALL_RET_NORMAL: > for (i =3D 0; i < nb_oargs; i++) { > TCGTemp *ts =3D arg_temp(op->args[i]); > - TCGReg reg =3D tcg_target_call_oarg_regs[i]; > + TCGReg reg =3D tcg_target_call_oarg_reg(TCG_CALL_RET_NORMAL,= i); >=20=20 > /* ENV should not be modified. */ > tcg_debug_assert(!temp_readonly(ts)); > diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc > index 2279a14c11..dfe569dd8c 100644 > --- a/tcg/aarch64/tcg-target.c.inc > +++ b/tcg/aarch64/tcg-target.c.inc > @@ -63,9 +63,13 @@ static const int tcg_target_call_iarg_regs[8] =3D { > TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3, > TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7 > }; > -static const int tcg_target_call_oarg_regs[1] =3D { > - TCG_REG_X0 > -}; > + > +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) > +{ > + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); > + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); > + return TCG_REG_X0 + slot; > +} >=20=20 > #define TCG_REG_TMP TCG_REG_X30 > #define TCG_VEC_TMP TCG_REG_V31 > diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc > index 8b24481d8c..4e1d06dcd8 100644 > --- a/tcg/arm/tcg-target.c.inc > +++ b/tcg/arm/tcg-target.c.inc > @@ -79,9 +79,13 @@ static const int tcg_target_reg_alloc_order[] =3D { > static const int tcg_target_call_iarg_regs[4] =3D { > TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3 > }; > -static const int tcg_target_call_oarg_regs[2] =3D { > - TCG_REG_R0, TCG_REG_R1 > -}; > + > +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) > +{ > + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); > + tcg_debug_assert(slot >=3D 0 && slot <=3D 3); > + return TCG_REG_R0 + slot; > +} So this is now returning allocations of TCG_REG_R0 to TCG_REG_R3? Do we have to take care to get things right if slot is ever bigger w.r.t. tcg_target_reg_alloc_order? >=20=20 > #define TCG_REG_TMP TCG_REG_R12 > #define TCG_VEC_TMP TCG_REG_Q15 > diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc > index 6a021dda8b..ab6881a4f3 100644 > --- a/tcg/i386/tcg-target.c.inc > +++ b/tcg/i386/tcg-target.c.inc > @@ -109,12 +109,16 @@ static const int tcg_target_call_iarg_regs[] =3D { > #endif > }; >=20=20 > -static const int tcg_target_call_oarg_regs[] =3D { > - TCG_REG_EAX, > -#if TCG_TARGET_REG_BITS =3D=3D 32 > - TCG_REG_EDX > -#endif > -}; > +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) > +{ > + switch (kind) { > + case TCG_CALL_RET_NORMAL: > + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); > + return slot ? TCG_REG_EDX : TCG_REG_EAX; > + default: > + g_assert_not_reached(); > + } > +} >=20=20 > /* Constants we accept. */ > #define TCG_CT_CONST_S32 0x100 > diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-targe= t.c.inc > index 54b1dcd911..f6b0ed00bb 100644 > --- a/tcg/loongarch64/tcg-target.c.inc > +++ b/tcg/loongarch64/tcg-target.c.inc > @@ -114,10 +114,12 @@ static const int tcg_target_call_iarg_regs[] =3D { > TCG_REG_A7, > }; >=20=20 > -static const int tcg_target_call_oarg_regs[] =3D { > - TCG_REG_A0, > - TCG_REG_A1, > -}; > +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) > +{ > + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); > + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); > + return TCG_REG_A0 + slot; > +} >=20=20 > #ifndef CONFIG_SOFTMMU > #define USE_GUEST_BASE (guest_base !=3D 0) > diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc > index 22b5463f0f..92883176c6 100644 > --- a/tcg/mips/tcg-target.c.inc > +++ b/tcg/mips/tcg-target.c.inc > @@ -136,10 +136,12 @@ static const TCGReg tcg_target_call_iarg_regs[] =3D= { > #endif > }; >=20=20 > -static const TCGReg tcg_target_call_oarg_regs[2] =3D { > - TCG_REG_V0, > - TCG_REG_V1 > -}; > +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) > +{ > + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); > + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); > + return TCG_REG_V0 + slot; > +} >=20=20 > static const tcg_insn_unit *tb_ret_addr; > static const tcg_insn_unit *bswap32_addr; > diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc > index bf3812eb8d..d31e6c3de4 100644 > --- a/tcg/ppc/tcg-target.c.inc > +++ b/tcg/ppc/tcg-target.c.inc > @@ -186,10 +186,12 @@ static const int tcg_target_call_iarg_regs[] =3D { > TCG_REG_R10 > }; >=20=20 > -static const int tcg_target_call_oarg_regs[] =3D { > - TCG_REG_R3, > - TCG_REG_R4 > -}; > +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) > +{ > + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); > + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); > + return TCG_REG_R3 + slot; > +} >=20=20 > static const int tcg_target_callee_save_regs[] =3D { > #ifdef _CALL_DARWIN > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index b961972b9f..7cfd35e753 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -113,10 +113,12 @@ static const int tcg_target_call_iarg_regs[] =3D { > TCG_REG_A7, > }; >=20=20 > -static const int tcg_target_call_oarg_regs[] =3D { > - TCG_REG_A0, > - TCG_REG_A1, > -}; > +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) > +{ > + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); > + tcg_debug_assert(slot >=3D 0 && slot <=3D 1); > + return TCG_REG_A0 + slot; > +} >=20=20 > #define TCG_CT_CONST_ZERO 0x100 > #define TCG_CT_CONST_S12 0x200 > diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc > index d65cd79899..cebf180777 100644 > --- a/tcg/s390x/tcg-target.c.inc > +++ b/tcg/s390x/tcg-target.c.inc > @@ -390,9 +390,12 @@ static const int tcg_target_call_iarg_regs[] =3D { > TCG_REG_R6, > }; >=20=20 > -static const int tcg_target_call_oarg_regs[] =3D { > - TCG_REG_R2, > -}; > +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) > +{ > + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); > + tcg_debug_assert(slot =3D=3D 0); > + return TCG_REG_R2; > +} >=20=20 > #define S390_CC_EQ 8 > #define S390_CC_LT 4 > diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc > index f6a8a8e605..9b5afb8248 100644 > --- a/tcg/sparc64/tcg-target.c.inc > +++ b/tcg/sparc64/tcg-target.c.inc > @@ -133,12 +133,12 @@ static const int tcg_target_call_iarg_regs[6] =3D { > TCG_REG_O5, > }; >=20=20 > -static const int tcg_target_call_oarg_regs[] =3D { > - TCG_REG_O0, > - TCG_REG_O1, > - TCG_REG_O2, > - TCG_REG_O3, > -}; > +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) > +{ > + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); > + tcg_debug_assert(slot >=3D 0 && slot <=3D 3); > + return TCG_REG_O0 + slot; > +} >=20=20 > #define INSN_OP(x) ((x) << 30) > #define INSN_OP2(x) ((x) << 22) > diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc > index 633345d74b..cd53cb6b6b 100644 > --- a/tcg/tci/tcg-target.c.inc > +++ b/tcg/tci/tcg-target.c.inc > @@ -200,12 +200,12 @@ static const int tcg_target_reg_alloc_order[] =3D { > /* No call arguments via registers. All will be stored on the "stack". = */ > static const int tcg_target_call_iarg_regs[] =3D { }; >=20=20 > -static const int tcg_target_call_oarg_regs[] =3D { > - TCG_REG_R0, > -#if TCG_TARGET_REG_BITS =3D=3D 32 > - TCG_REG_R1 > -#endif > -}; > +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) > +{ > + tcg_debug_assert(kind =3D=3D TCG_CALL_RET_NORMAL); > + tcg_debug_assert(slot >=3D 0 && slot < 64 / TCG_TARGET_REG_BITS); > + return TCG_REG_R0 + slot; > +} >=20=20 > #ifdef CONFIG_DEBUG_TCG > static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] =3D { Otherwise: Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro From MAILER-DAEMON Wed Jan 25 16:13:43 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKn5S-000796-S9 for mharc-qemu-riscv@gnu.org; Wed, 25 Jan 2023 16:13:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKn5P-00075b-49 for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 16:13:40 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKn5N-00086C-3m for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 16:13:38 -0500 Received: by mail-wr1-x42a.google.com with SMTP id r2so18337875wrv.7 for ; Wed, 25 Jan 2023 13:13:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:in-reply-to:date :subject:cc:to:from:user-agent:references:from:to:cc:subject:date :message-id:reply-to; bh=1rhIEXn0pLuoc5qeKsCE66/f36q7EcfKoWih67jlqRc=; b=t0KnwWJAql55WRy4VNQhg4iHSJA/Z+HxSdfycFhUqj8rwWzSzF7mhYsgcsLoKx/dlT JDZnlSScs8J+WkgZUuIiNCHNgNdKw4Xpv7IZvGOHTn7VeyCzLiwHe01e7dXbjxq9YVvc 6OVOFZYJMDC2NDhBOcSw2C1Ei/DTQIijvvlG0B+Oob+OM07lvelbzw8mlhL2EtAOaI5f pugsd/jU0JzQikxb+wW69+WhYQhqtsLtELJDk730JhUZJA+t9IRruANp0BKpMfwNh6+M 2HTY7Zrybax1XJ8kAibnxthFaFwBUQTQga3wDPTMtUBhB2Sx1k3qLzcrItDBGlWqGmBB rH+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:in-reply-to:date :subject:cc:to:from:user-agent:references:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=1rhIEXn0pLuoc5qeKsCE66/f36q7EcfKoWih67jlqRc=; b=1Xz/kA8lgrxrfF4CoB67UtlAk4Jcaj6nOOGxboUTU193xfseS1BlHo+8b+uZCZfHGf ppC6J3RDT/GuM4BMHcnttQgu8IL1NT52YhIWHKuNUdSkRZxnu2RjObF0CcWNv595wIBv 6tKBQJ1kZ4a3D59DzStl06nTgJAz26ts9VyfHbJ3nyQJedvuRjJEvOAfbbLilW/g02ha b9niVXw25QzkwsG4l93mZlgoyCgAjwu48FN6/z5nlXUt4KI6Lwwchnj6zRxHbujKviwq wYD1BukwxOQpUnVsJSNpN69+efXFpbOIlqJtYdZaS2chcosRB+6tBB1R87El655UeLRt 3pAQ== X-Gm-Message-State: AFqh2ko/33/JgWs5PjmJ0n+HZ8lClPXOc1jEYixfXVQgmgJEQ90G9w3E yrqaDKVsgpgsIFPAohKStLsK0w== X-Google-Smtp-Source: AMrXdXs8K04BkAmYGGOB3ozwhu/qJwHs+UNMN2as9ghMk+SvxeJoItXE+OwG97BDzTONwtdfxQyYxg== X-Received: by 2002:a05:6000:1049:b0:242:15d6:1a75 with SMTP id c9-20020a056000104900b0024215d61a75mr26404607wrx.66.1674681215488; Wed, 25 Jan 2023 13:13:35 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id bj7-20020a0560001e0700b002bfb5618ee7sm3692468wrb.91.2023.01.25.13.13.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 13:13:35 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 86BB71FFB7; Wed, 25 Jan 2023 21:13:34 +0000 (GMT) References: <20230108023719.2466341-1-richard.henderson@linaro.org> <20230108023719.2466341-8-richard.henderson@linaro.org> User-agent: mu4e 1.9.16; emacs 29.0.60 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, qemu-arm@nongnu.org Subject: Re: [PATCH v4 07/36] tcg: Add TCG_CALL_RET_BY_VEC Date: Wed, 25 Jan 2023 21:13:30 +0000 In-reply-to: <20230108023719.2466341-8-richard.henderson@linaro.org> Message-ID: <87357yqpvl.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 21:13:40 -0000 Richard Henderson writes: > This will be used by _WIN64 to return i128. Not yet used, > because allocation is not yet enabled. > > Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro From MAILER-DAEMON Wed Jan 25 16:51:38 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKng9-0001pS-Kt for mharc-qemu-riscv@gnu.org; Wed, 25 Jan 2023 16:51:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKng6-0001oy-TW for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 16:51:35 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKng3-0007Kb-OY for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 16:51:34 -0500 Received: by mail-wm1-x335.google.com with SMTP id m5-20020a05600c4f4500b003db03b2559eso2275986wmq.5 for ; Wed, 25 Jan 2023 13:51:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:in-reply-to:date :subject:cc:to:from:user-agent:references:from:to:cc:subject:date :message-id:reply-to; bh=gtMjrYQEvWpG2AuLNdEHTTKCQ6D1LPu1b90gG5rRUBI=; b=sl2jTDL2kpnjDtqoj7P93pBhaQit//zoES0nH/n1mu/dTbSgEQcBvCZ224Dg0Ucbdo 8z6fOdDeKZ8zX0jJ+Q3BToa9zmdTV6Wj6btgML8K9AD1rSbffso14pimIF4zk3xcil7C aLGVY0xFITanNBYO88+xNMI+kSy7EFzrPUSWXI3M3l+1x9hvbAMVh3QayPMeAhySLTt0 RIAqWGHP5DAf0EiW7daJZElVjQL210ANnsCHw2y9VF33fo+7Oozg7Ml6NPOD/OU4ThXD mD7xdDjuE3F4IXIN6VK/ZLA66Eb/Lvx0WnTuIsw67CZF1G67GiC8xsXAYzIDwsK7ke0D oLLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:in-reply-to:date :subject:cc:to:from:user-agent:references:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=gtMjrYQEvWpG2AuLNdEHTTKCQ6D1LPu1b90gG5rRUBI=; b=mBW0fK0fWMuZAxNzTceC1W8EWDLATxkjZVi3qD7pJ//UBtGP86PEPk1xDyjp8jyjX2 SLDrlZth+ZfX656XCbMpvQSRFGreIEjAnvvKGDX+URMVpIPk3xsZ2un1UsEaeLHq8TS7 Iw5YZvnMLBwJINfo1PfG6P4gM8q8/qL8RTKonrYeFBmGqmW24EWgjrTPIDDyMs5j4FVx 4ijeOqG8GjceBkr5eUW/5eDfFM1gkhsdr3QE86lRjjE+hpCd2hku6maNLOLP8x0ftB8R gxAXE+ZkskVJiv3UV+VVZs1GOW6+jbZkYINQzlySao0ThsrCHABHuxcmxc7mxrzYBBZt QSRQ== X-Gm-Message-State: AFqh2krr60s0PiT2mUFGy/LrsCMpO1mR5WEI6rybXW4H7Zwl/FVhd48W +SEwU4J+yWjcPqyARIzhXhGA1A== X-Google-Smtp-Source: AMrXdXsVyq6GB3Qknv7H5TE6LfYAt0dA10avnqZsU6gWGDU6GkphiLwDFL7r9HRoAeWAKj76kcI1Sg== X-Received: by 2002:a7b:c5cb:0:b0:3da:fac4:7da3 with SMTP id n11-20020a7bc5cb000000b003dafac47da3mr32834870wmk.36.1674683489842; Wed, 25 Jan 2023 13:51:29 -0800 (PST) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id v23-20020a05600c4d9700b003db1ca20170sm2857931wmp.37.2023.01.25.13.51.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Jan 2023 13:51:29 -0800 (PST) Received: from zen (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id EF2631FFB7; Wed, 25 Jan 2023 21:51:28 +0000 (GMT) References: <20230108023719.2466341-1-richard.henderson@linaro.org> User-agent: mu4e 1.9.16; emacs 29.0.60 From: Alex =?utf-8?Q?Benn=C3=A9e?= To: Richard Henderson Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, qemu-devel@nongnu.org Subject: Re: [PATCH v4 00/36] tcg: Support for Int128 with helpers Date: Wed, 25 Jan 2023 21:50:55 +0000 In-reply-to: <20230108023719.2466341-1-richard.henderson@linaro.org> Message-ID: <87y1pqp9jz.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 21:51:35 -0000 Richard Henderson writes: > Changes for v4: > * About half of the v3 series has been merged, > * AArch64 host requires even argument register. > * target/{arm,ppc,s390x,i386} uses included here. Have you got a branch or a new re-base? I tried applying but got messy conflicts I couldn't cleanly resolve. --=20 Alex Benn=C3=A9e Virtualisation Tech Lead @ Linaro From MAILER-DAEMON Wed Jan 25 17:53:29 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKoe1-000097-0X for mharc-qemu-riscv@gnu.org; Wed, 25 Jan 2023 17:53:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKody-00007k-Pl for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 17:53:27 -0500 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKods-0008Fy-Ld for qemu-riscv@nongnu.org; Wed, 25 Jan 2023 17:53:26 -0500 Received: by mail-wm1-x333.google.com with SMTP id fl24so67985wmb.1 for ; Wed, 25 Jan 2023 14:53:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; 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Wed, 25 Jan 2023 14:53:14 -0800 (PST) Received: from [192.168.0.114] ([196.77.22.181]) by smtp.gmail.com with ESMTPSA id j38-20020a05600c1c2600b003daff80f16esm4429343wms.27.2023.01.25.14.53.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 25 Jan 2023 14:53:14 -0800 (PST) Message-ID: <3fe9d8c3-233c-4673-78af-694f0a452400@linaro.org> Date: Wed, 25 Jan 2023 23:53:12 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v4 34/36] target/i386: Split out gen_cmpxchg8b, gen_cmpxchg16b Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net References: <20230108023719.2466341-1-richard.henderson@linaro.org> <20230108023719.2466341-35-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20230108023719.2466341-35-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.148, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Jan 2023 22:53:27 -0000 On 8/1/23 03:37, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > target/i386/tcg/translate.c | 48 ++++++++++++++++++++++++------------- > 1 file changed, 31 insertions(+), 17 deletions(-) Reviewed-by: Philippe Mathieu-Daudé From MAILER-DAEMON Wed Jan 25 23:12:00 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKtcG-0003fM-M5 for mharc-qemu-riscv@gnu.org; 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id 15-20020a62190f000000b0058dc1d54db1sm4378899pfz.206.2023.01.25.20.11.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 25 Jan 2023 20:11:49 -0800 (PST) Message-ID: <74fe37d9-331c-7e00-e642-365f1a04ff80@linaro.org> Date: Wed, 25 Jan 2023 18:11:45 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v4 06/36] tcg: Introduce tcg_target_call_oarg_reg Content-Language: en-US To: =?UTF-8?Q?Alex_Benn=c3=a9e?= Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, Daniel Henrique Barboza , qemu-devel@nongnu.org References: <20230108023719.2466341-1-richard.henderson@linaro.org> <20230108023719.2466341-7-richard.henderson@linaro.org> <877cxaqpxi.fsf@linaro.org> From: Richard Henderson In-Reply-To: <877cxaqpxi.fsf@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.148, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Jan 2023 04:11:54 -0000 On 1/25/23 11:09, Alex Bennée wrote: >> -static const int tcg_target_call_oarg_regs[2] = { >> - TCG_REG_R0, TCG_REG_R1 >> -}; >> + >> +static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) >> +{ >> + tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); >> + tcg_debug_assert(slot >= 0 && slot <= 3); >> + return TCG_REG_R0 + slot; >> +} > > So this is now returning allocations of TCG_REG_R0 to TCG_REG_R3? Yes, should have mentioned in the patch description. Done. > Do we > have to take care to get things right if slot is ever bigger w.r.t. > tcg_target_reg_alloc_order? No, reg_alloc_order is optimization for call-saved vs call-clobbered vs call arguments. It should not affect correctness at all. Nor will it ever affect call return -- those registers die immediately before the call, and become live with these values immediately after the call. r~ From MAILER-DAEMON Thu Jan 26 04:36:13 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKyg0-0006Kx-VD for mharc-qemu-riscv@gnu.org; Thu, 26 Jan 2023 04:36:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKyfq-0006D7-At for qemu-riscv@nongnu.org; Thu, 26 Jan 2023 04:36:04 -0500 Received: from mail-ej1-x633.google.com ([2a00:1450:4864:20::633]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pKyfj-0000HA-IS for qemu-riscv@nongnu.org; Thu, 26 Jan 2023 04:35:59 -0500 Received: by mail-ej1-x633.google.com with SMTP id me3so3488028ejb.7 for ; Thu, 26 Jan 2023 01:35:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=DT0Lu1S7bVZWSJ/5KBhAOZTAy5/bIBsgUk28kymJUw4=; b=sb+UdAvKJWjfVzhyZl5yV7hTO0JFMMhtb5a7x8dTqWV2/lT+CEtMFw5YVva/45BzVK F/tVlsryDH9PpY70gohDVM7QG+0TrUVf+UuDkP0odQOz7nLHFDPZvQX+TwgLg1PJD7Ua Bu2/oBX7E12T72StK7L77RL6OMGqYgyv4yLAR+CNgj35jp7ucn5z27r9R6Cc7gz9k3Ob boU/Hcf1HSv+4AcklCTn7S1UizecblG++85Dzsj8sFO+SbD03s8b6Vl2VLHo/JRLXgTL PPF5YjN2aNKF2SQRfDG+J2dfhXSf5OzZ37QuYJQo+xnLlM9ACSDJ+HX/s5pEqwTxIzLG IP/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=DT0Lu1S7bVZWSJ/5KBhAOZTAy5/bIBsgUk28kymJUw4=; b=Fu3KsOpV7hxJgvvVcTd/Ik34NyOZk89M8HixUQ3zeXcmObujnO0aDvN8xyY+8dmNTE Nz+7bdXP1LrQHq5Ww0/kKifOGZHAC5yq8vIwETLSchujUR9P89bo+qwtvKmk8pjHzGq1 AuICl6s4DY0b7hnaisnL1kyCpeZqB5/Mnbc65F4Hbs1k4/Ot6JL/464MiAjBUYq/sbb9 +mUAk2/Qcxr2b0x+B8rppispSmGAu8838g7GnVQrGxrVM2q8KkZy/THHkUs4cXPK01Bt XsziL526GkwOBVK6Ts4OrJ9Q16/bx15k6V1dCA9XhARQwCaTjYmyCpZRJsL/LQU78VEu 5F9w== X-Gm-Message-State: AFqh2kqHUYcIv8ksrj+9321PfPNoDJwYRAE0PxeAGULgOFq6v/Q8C/rx U8JU0TP7U6qW6w4Xfymd/BlZkDYaAM6LpVVCeP9AEw== X-Google-Smtp-Source: AMrXdXsscODI8IrXD1LeP41GmLRUpd22QIcs84drJwKJ3t1ISnggbG38fGMBrlgSNvlGJpdHxxvf8lhEP2SjemjowBY= X-Received: by 2002:a17:906:9c50:b0:86a:12b:d096 with SMTP id fg16-20020a1709069c5000b0086a012bd096mr4288572ejc.70.1674725747678; Thu, 26 Jan 2023 01:35:47 -0800 (PST) MIME-Version: 1.0 References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> <380600FF-17AC-4134-85C7-CBDF6E34F0E2@getmailspring.com> In-Reply-To: <380600FF-17AC-4134-85C7-CBDF6E34F0E2@getmailspring.com> From: Philipp Tomsich Date: Thu, 26 Jan 2023 10:35:36 +0100 Message-ID: Subject: Re: [RFC PATCH 00/39] Add RISC-V cryptography extensions standardisation To: Lawrence Hunter Cc: "alistair.francis@wdc.com" , "bin.meng@windriver.com" , "dickon.hood@codethink.co.uk" , "frank.chang@sifive.com" , "kvm@vger.kernel.org" , "palmer@dabbelt.com" , "pbonzini@redhat.com" , "qemu-riscv@nongnu.org" Content-Type: multipart/alternative; boundary="00000000000049800a05f327797f" Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=philipp.tomsich@vrull.eu; helo=mail-ej1-x633.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Jan 2023 09:36:06 -0000 --00000000000049800a05f327797f Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Lawrence, we=E2=80=98ll review, as we=E2=80=98ve also been developing a similar serie= s and have the know how readily available. Seems like you beat us to submitting it ;-) I=E2=80=99ll make sure reviews go up by next week. Philipp. On Thu 26. Jan 2023 at 10:21, Lawrence Hunter < lawrence.hunter@codethink.co.uk> wrote: > Follow up for add RISC-V vector cryptography extensions standardisation > RFC: we've not received any comments and would like to move this series > towards getting merged. Does anyone have time to review it, and should > we look at resubmitting for merging soon? > > ---------- Forwarded Message --------- > > From: Lawrence Hunter > Subject: [RFC PATCH 00/39] Add RISC-V cryptography extensions > standardisation > Date: Jan 19 2023, at 2:34 pm > To: qemu-riscv@nongnu.org > Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence Hunter = < > lawrence.hunter@codethink.co.uk> > > > > This RFC introduces an implementation for the six instruction sets > > of the draft RISC-V cryptography extensions standardisation > > specification. Once the specification has been ratified we will submit > > these changes as a pull request email to this mailing list. Would this > > be prefered by instruction group or unified as in this RFC? > > > > This patch set implements the instruction sets as per the 20221202 > > version of the specification (1). > > > > Work performed by Dickon, Lawrence, Nazar, Kiran, and William from > Codethink > > sponsored by SiFive, and Max Chou from SiFive. > > > > 1. https://github.com/riscv/riscv-crypto/releases > > > > Dickon Hood (1): > > target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] decoding, > > translation and execution support > > > > Kiran Ostrolenk (4): > > target/riscv: Add vsha2ms.vv decoding, translation and execution > > support > > target/riscv: add zvksh cpu property > > target/riscv: Add vsm3c.vi decoding, translation and execution support > > target/riscv: expose zvksh cpu property > > > > Lawrence Hunter (16): > > target/riscv: Add vclmul.vv decoding, translation and execution > > support > > target/riscv: Add vclmul.vx decoding, translation and execution > > support > > target/riscv: Add vclmulh.vv decoding, translation and execution > > support > > target/riscv: Add vclmulh.vx decoding, translation and execution > > support > > target/riscv: Add vaesef.vv decoding, translation and execution > > support > > target/riscv: Add vaesef.vs decoding, translation and execution > > support > > target/riscv: Add vaesdf.vv decoding, translation and execution > > support > > target/riscv: Add vaesdf.vs decoding, translation and execution > > support > > target/riscv: Add vaesdm.vv decoding, translation and execution > > support > > target/riscv: Add vaesdm.vs decoding, translation and execution > > support > > target/riscv: Add vaesz.vs decoding, translation and execution support > > target/riscv: Add vsha2c[hl].vv decoding, translation and execution > > support > > target/riscv: Add vsm3me.vv decoding, translation and execution > > support > > target/riscv: add zvkg cpu property > > target/riscv: Add vghmac.vv decoding, translation and execution > > support > > target/riscv: expose zvkg cpu property > > > > Max Chou (5): > > crypto: Move SM4_SBOXWORD from target/riscv > > crypto: Add SM4 constant parameter CK. > > target/riscv: Add zvksed cfg property > > target/riscv: Add Zvksed support > > target/riscv: Expose Zvksed property > > > > Nazar Kazakov (10): > > target/riscv: add zvkb cpu property > > target/riscv: Add vrev8.v decoding, translation and execution support > > target/riscv: Add vandn.[vv,vx,vi] decoding, translation and execution > > support > > target/riscv: expose zvkb cpu property > > target/riscv: add zvkns cpu property > > target/riscv: Add vaeskf1.vi decoding, translation and execution > > support > > target/riscv: Add vaeskf2.vi decoding, translation and execution > > support > > target/riscv: expose zvkns cpu property > > target/riscv: add zvknh cpu properties > > target/riscv: expose zvknh cpu properties > > > > William Salmon (3): > > target/riscv: Add vbrev8.v decoding, translation and execution support > > target/riscv: Add vaesem.vv decoding, translation and execution > > support > > target/riscv: Add vaesem.vs decoding, translation and execution > > support > > > > crypto/sm4.c | 10 + > > include/crypto/sm4.h | 8 + > > include/qemu/bitops.h | 32 + > > target/arm/crypto_helper.c | 10 +- > > target/riscv/cpu.c | 15 + > > target/riscv/cpu.h | 7 + > > target/riscv/crypto_helper.c | 1 + > > target/riscv/helper.h | 69 ++ > > target/riscv/insn32.decode | 48 + > > target/riscv/insn_trans/trans_rvzvkb.c.inc | 164 +++ > > target/riscv/insn_trans/trans_rvzvkg.c.inc | 8 + > > target/riscv/insn_trans/trans_rvzvknh.c.inc | 47 + > > target/riscv/insn_trans/trans_rvzvkns.c.inc | 121 +++ > > target/riscv/insn_trans/trans_rvzvksed.c.inc | 38 + > > target/riscv/insn_trans/trans_rvzvksh.c.inc | 20 + > > target/riscv/meson.build | 4 +- > > target/riscv/translate.c | 6 + > > target/riscv/vcrypto_helper.c | 1013 ++++++++++++++++++ > > target/riscv/vector_helper.c | 242 +---- > > target/riscv/vector_internals.c | 63 ++ > > target/riscv/vector_internals.h | 226 ++++ > > 21 files changed, 1902 insertions(+), 250 deletions(-) > > create mode 100644 target/riscv/insn_trans/trans_rvzvkb.c.inc > > create mode 100644 target/riscv/insn_trans/trans_rvzvkg.c.inc > > create mode 100644 target/riscv/insn_trans/trans_rvzvknh.c.inc > > create mode 100644 target/riscv/insn_trans/trans_rvzvkns.c.inc > > create mode 100644 target/riscv/insn_trans/trans_rvzvksed.c.inc > > create mode 100644 target/riscv/insn_trans/trans_rvzvksh.c.inc > > create mode 100644 target/riscv/vcrypto_helper.c > > create mode 100644 target/riscv/vector_internals.c > > create mode 100644 target/riscv/vector_internals.h > > > > -- > > 2.39.1 > > > > > > > --00000000000049800a05f327797f Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Lawrence,

we=E2=80=98ll review, as we=E2=80=98ve also been developing a similar s= eries and have the know how readily available.=C2=A0 Seems like you beat us= to submitting it ;-)

I= =E2=80=99ll make sure reviews go up by next week.
Philipp.

On Thu 26. Jan 2023 at 10:21, Lawren= ce Hunter <lawrence.h= unter@codethink.co.uk> wrote:
lawrence.hunter@codethink.co.uk>
Subject: [RFC PATCH 00/39] Add RISC-V cryptography extensions standardisati= on
Date: Jan 19 2023, at 2:34 pm
To: qemu-riscv@n= ongnu.org
Cc: dickon= .hood@codethink.co.uk, frank.chang@sifive.com, Lawrence Hunter <lawrence.hunter@codet= hink.co.uk>


> This RFC introduces an implementation for the six instruction sets
> of the draft RISC-V cryptography extensions standardisation
> specification. Once the specification has been ratified we will submit=
> these changes as a pull request email to this mailing list. Would this=
> be prefered by instruction group or unified as in this RFC?
>
> This patch set implements the instruction sets as per the 20221202
> version of the specification (1).
>
> Work performed by Dickon, Lawrence, Nazar, Kiran, and William from Cod= ethink
> sponsored by SiFive, and Max Chou from SiFive.
>
> 1. https://github.com/riscv/riscv-crypto/releases=
>
> Dickon Hood (1):
>=C2=A0 target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] decoding,
>=C2=A0 =C2=A0 translation and execution support
>
> Kiran Ostrolenk (4):
>=C2=A0 target/riscv: Add vsha2ms.vv decoding, translation and execution=
>=C2=A0 =C2=A0 support
>=C2=A0 target/riscv: add zvksh cpu property
>=C2=A0 target/riscv: Add vsm3c.vi decoding, translation and execution support=
>=C2=A0 target/riscv: expose zvksh cpu property
>
> Lawrence Hunter (16):
>=C2=A0 target/riscv: Add vclmul.vv decoding, translation and execution<= br> >=C2=A0 =C2=A0 support
>=C2=A0 target/riscv: Add vclmul.vx decoding, translation and execution<= br> >=C2=A0 =C2=A0 support
>=C2=A0 target/riscv: Add vclmulh.vv decoding, translation and execution=
>=C2=A0 =C2=A0 support
>=C2=A0 target/riscv: Add vclmulh.vx decoding, translation and execution=
>=C2=A0 =C2=A0 support
>=C2=A0 target/riscv: Add vaesef.vv decoding, translation and execution<= br> >=C2=A0 =C2=A0 support
>=C2=A0 target/riscv: Add vaesef.vs decoding, translation and execution<= br> >=C2=A0 =C2=A0 support
>=C2=A0 target/riscv: Add vaesdf.vv decoding, translation and execution<= br> >=C2=A0 =C2=A0 support
>=C2=A0 target/riscv: Add vaesdf.vs decoding, translation and execution<= br> >=C2=A0 =C2=A0 support
>=C2=A0 target/riscv: Add vaesdm.vv decoding, translation and execution<= br> >=C2=A0 =C2=A0 support
>=C2=A0 target/riscv: Add vaesdm.vs decoding, translation and execution<= br> >=C2=A0 =C2=A0 support
>=C2=A0 target/riscv: Add vaesz.vs decoding, translation and execution s= upport
>=C2=A0 target/riscv: Add vsha2c[hl].vv decoding, translation and execut= ion
>=C2=A0 =C2=A0 support
>=C2=A0 target/riscv: Add vsm3me.vv decoding, translation and execution<= br> >=C2=A0 =C2=A0 support
>=C2=A0 target/riscv: add zvkg cpu property
>=C2=A0 target/riscv: Add vghmac.vv decoding, translation and execution<= br> >=C2=A0 =C2=A0 support
>=C2=A0 target/riscv: expose zvkg cpu property
>
> Max Chou (5):
>=C2=A0 crypto: Move SM4_SBOXWORD from target/riscv
>=C2=A0 crypto: Add SM4 constant parameter CK.
>=C2=A0 target/riscv: Add zvksed cfg property
>=C2=A0 target/riscv: Add Zvksed support
>=C2=A0 target/riscv: Expose Zvksed property
>
> Nazar Kazakov (10):
>=C2=A0 target/riscv: add zvkb cpu property
>=C2=A0 target/riscv: Add vrev8.v decoding, translation and execution su= pport
>=C2=A0 target/riscv: Add vandn.[vv,vx,vi] decoding, translation and exe= cution
>=C2=A0 =C2=A0 support
>=C2=A0 target/riscv: expose zvkb cpu property
>=C2=A0 target/riscv: add zvkns cpu property
>=C2=A0 target/riscv: Add vaeskf1.vi decoding, translation and execution
>=C2=A0 =C2=A0 support
>=C2=A0 target/riscv: Add vaeskf2.vi decoding, translation and execution
>=C2=A0 =C2=A0 support
>=C2=A0 target/riscv: expose zvkns cpu property
>=C2=A0 target/riscv: add zvknh cpu properties
>=C2=A0 target/riscv: expose zvknh cpu properties
>
> William Salmon (3):
>=C2=A0 target/riscv: Add vbrev8.v decoding, translation and execution s= upport
>=C2=A0 target/riscv: Add vaesem.vv decoding, translation and execution<= br> >=C2=A0 =C2=A0 support
>=C2=A0 target/riscv: Add vaesem.vs decoding, translation and execution<= br> >=C2=A0 =C2=A0 support
>
> crypto/sm4.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2= =A010 +
> include/crypto/sm4.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A0 8 +
> include/qemu/bitops.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A032 +
> target/arm/crypto_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A010 +-
> target/riscv/cpu.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A015 +
> target/riscv/cpu.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A0 7 +
> target/riscv/crypto_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A0 1 +
> target/riscv/helper.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A069 ++
> target/riscv/insn32.decode=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A048 +
> target/riscv/insn_trans/trans_rvzvkb.c.inc=C2=A0 =C2=A0|=C2=A0 164 +++=
> target/riscv/insn_trans/trans_rvzvkg.c.inc=C2=A0 =C2=A0|=C2=A0 =C2=A0 = 8 +
> target/riscv/insn_trans/trans_rvzvknh.c.inc=C2=A0 |=C2=A0 =C2=A047 + > target/riscv/insn_trans/trans_rvzvkns.c.inc=C2=A0 |=C2=A0 121 +++
> target/riscv/insn_trans/trans_rvzvksed.c.inc |=C2=A0 =C2=A038 +
> target/riscv/insn_trans/trans_rvzvksh.c.inc=C2=A0 |=C2=A0 =C2=A020 + > target/riscv/meson.build=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A0 4 +-
> target/riscv/translate.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 =C2=A0 6 +
> target/riscv/vcrypto_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 | 1013 ++++++++++++++++++
> target/riscv/vector_helper.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0|=C2=A0 242 +----
> target/riscv/vector_internals.c=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 |=C2=A0 =C2=A063 ++
> target/riscv/vector_internals.h=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 |=C2=A0 226 ++++
> 21 files changed, 1902 insertions(+), 250 deletions(-)
> create mode 100644 target/riscv/insn_trans/trans_rvzvkb.c.inc
> create mode 100644 target/riscv/insn_trans/trans_rvzvkg.c.inc
> create mode 100644 target/riscv/insn_trans/trans_rvzvknh.c.inc
> create mode 100644 target/riscv/insn_trans/trans_rvzvkns.c.inc
> create mode 100644 target/riscv/insn_trans/trans_rvzvksed.c.inc
> create mode 100644 target/riscv/insn_trans/trans_rvzvksh.c.inc
> create mode 100644 target/riscv/vcrypto_helper.c
> create mode 100644 target/riscv/vector_internals.c
> create mode 100644 target/riscv/vector_internals.h
>
> --
> 2.39.1
>
>
>
--00000000000049800a05f327797f-- From MAILER-DAEMON Thu Jan 26 04:49:41 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pKyt2-00010b-MO for mharc-qemu-riscv@gnu.org; Thu, 26 Jan 2023 04:49:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKysv-000109-56 for qemu-riscv@nongnu.org; Thu, 26 Jan 2023 04:49:34 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pKyst-0005Oa-1B for qemu-riscv@nongnu.org; Thu, 26 Jan 2023 04:49:32 -0500 Received: from [167.98.27.226] (helo=lawrence-thinkpad) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pKyRN-000Kay-RL; Thu, 26 Jan 2023 09:21:06 +0000 Date: Thu, 26 Jan 2023 09:21:05 +0000 From: Lawrence Hunter To: "=?utf-8?Q?qemu-riscv=40nongnu.org?=" Cc: "=?utf-8?Q?dickon.hood=40codethink.co.uk?=" , "=?utf-8?Q?frank.chang=40sifive.com?=" , "=?utf-8?Q?palmer=40dabbelt.com?=" , "=?utf-8?Q?alistair.francis=40wdc.com?=" , "=?utf-8?Q?bin.meng=40windriver.com?=" , "=?utf-8?Q?pbonzini=40redhat.com?=" , "=?utf-8?Q?philipp.tomsich=40vrull.eu?=" , "=?utf-8?Q?kvm=40vger.kernel.org?=" Message-ID: <380600FF-17AC-4134-85C7-CBDF6E34F0E2@getmailspring.com> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> Subject: Fwd: [RFC PATCH 00/39] Add RISC-V cryptography extensions standardisation X-Mailer: Mailspring MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Jan 2023 09:49:35 -0000 Follow up for add RISC-V vector cryptography extensions standardisation RFC: we've not received any comments and would like to move this series towards getting merged. Does anyone have time to review it, and should we look at resubmitting for merging soon? ---------- Forwarded Message --------- From: Lawrence Hunter Subject: [RFC PATCH 00/39] Add RISC-V cryptography extensions standardisation Date: Jan 19 2023, at 2:34 pm To: qemu-riscv@nongnu.org Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence Hunter > This RFC introduces an implementation for the six instruction sets > of the draft RISC-V cryptography extensions standardisation > specification. Once the specification has been ratified we will submit > these changes as a pull request email to this mailing list. Would this > be prefered by instruction group or unified as in this RFC? > > This patch set implements the instruction sets as per the 20221202 > version of the specification (1). > > Work performed by Dickon, Lawrence, Nazar, Kiran, and William from Codethink > sponsored by SiFive, and Max Chou from SiFive. > > 1. https://github.com/riscv/riscv-crypto/releases > > Dickon Hood (1): > target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] decoding, > translation and execution support > > Kiran Ostrolenk (4): > target/riscv: Add vsha2ms.vv decoding, translation and execution > support > target/riscv: add zvksh cpu property > target/riscv: Add vsm3c.vi decoding, translation and execution support > target/riscv: expose zvksh cpu property > > Lawrence Hunter (16): > target/riscv: Add vclmul.vv decoding, translation and execution > support > target/riscv: Add vclmul.vx decoding, translation and execution > support > target/riscv: Add vclmulh.vv decoding, translation and execution > support > target/riscv: Add vclmulh.vx decoding, translation and execution > support > target/riscv: Add vaesef.vv decoding, translation and execution > support > target/riscv: Add vaesef.vs decoding, translation and execution > support > target/riscv: Add vaesdf.vv decoding, translation and execution > support > target/riscv: Add vaesdf.vs decoding, translation and execution > support > target/riscv: Add vaesdm.vv decoding, translation and execution > support > target/riscv: Add vaesdm.vs decoding, translation and execution > support > target/riscv: Add vaesz.vs decoding, translation and execution support > target/riscv: Add vsha2c[hl].vv decoding, translation and execution > support > target/riscv: Add vsm3me.vv decoding, translation and execution > support > target/riscv: add zvkg cpu property > target/riscv: Add vghmac.vv decoding, translation and execution > support > target/riscv: expose zvkg cpu property > > Max Chou (5): > crypto: Move SM4_SBOXWORD from target/riscv > crypto: Add SM4 constant parameter CK. > target/riscv: Add zvksed cfg property > target/riscv: Add Zvksed support > target/riscv: Expose Zvksed property > > Nazar Kazakov (10): > target/riscv: add zvkb cpu property > target/riscv: Add vrev8.v decoding, translation and execution support > target/riscv: Add vandn.[vv,vx,vi] decoding, translation and execution > support > target/riscv: expose zvkb cpu property > target/riscv: add zvkns cpu property > target/riscv: Add vaeskf1.vi decoding, translation and execution > support > target/riscv: Add vaeskf2.vi decoding, translation and execution > support > target/riscv: expose zvkns cpu property > target/riscv: add zvknh cpu properties > target/riscv: expose zvknh cpu properties > > William Salmon (3): > target/riscv: Add vbrev8.v decoding, translation and execution support > target/riscv: Add vaesem.vv decoding, translation and execution > support > target/riscv: Add vaesem.vs decoding, translation and execution > support > > crypto/sm4.c | 10 + > include/crypto/sm4.h | 8 + > include/qemu/bitops.h | 32 + > target/arm/crypto_helper.c | 10 +- > target/riscv/cpu.c | 15 + > target/riscv/cpu.h | 7 + > target/riscv/crypto_helper.c | 1 + > target/riscv/helper.h | 69 ++ > target/riscv/insn32.decode | 48 + > target/riscv/insn_trans/trans_rvzvkb.c.inc | 164 +++ > target/riscv/insn_trans/trans_rvzvkg.c.inc | 8 + > target/riscv/insn_trans/trans_rvzvknh.c.inc | 47 + > target/riscv/insn_trans/trans_rvzvkns.c.inc | 121 +++ > target/riscv/insn_trans/trans_rvzvksed.c.inc | 38 + > target/riscv/insn_trans/trans_rvzvksh.c.inc | 20 + > target/riscv/meson.build | 4 +- > target/riscv/translate.c | 6 + > target/riscv/vcrypto_helper.c | 1013 ++++++++++++++++++ > target/riscv/vector_helper.c | 242 +---- > target/riscv/vector_internals.c | 63 ++ > target/riscv/vector_internals.h | 226 ++++ > 21 files changed, 1902 insertions(+), 250 deletions(-) > create mode 100644 target/riscv/insn_trans/trans_rvzvkb.c.inc > create mode 100644 target/riscv/insn_trans/trans_rvzvkg.c.inc > create mode 100644 target/riscv/insn_trans/trans_rvzvknh.c.inc > create mode 100644 target/riscv/insn_trans/trans_rvzvkns.c.inc > create mode 100644 target/riscv/insn_trans/trans_rvzvksed.c.inc > create mode 100644 target/riscv/insn_trans/trans_rvzvksh.c.inc > create mode 100644 target/riscv/vcrypto_helper.c > create mode 100644 target/riscv/vector_internals.c > create mode 100644 target/riscv/vector_internals.h > > -- > 2.39.1 > > > From MAILER-DAEMON Thu Jan 26 07:03:57 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pL0yz-0000P4-D4 for mharc-qemu-riscv@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Jan 2023 12:03:48 -0000 On Tue, Jan 24, 2023 at 9:42 AM Alistair Francis wrote: > > On Tue, Jan 24, 2023 at 11:24 AM Bin Meng wrote: > > > > On Mon, Jan 23, 2023 at 11:58 AM Alistair Francis > > wrote: > > > > > > From: Alistair Francis > > > > > > If the CSRs and CSR instructions are disabled because the Zicsr > > > extension isn't enabled then we want to make sure we don't run any CSR > > > instructions in the boot ROM. > > > > > > This patches removes the CSR instructions from the reset-vec if the > > > extension isn't enabled. We replace the instruction with a NOP instead. > > > > > > Note that we don't do this for the SiFive U machine, as we are modelling > > > the hardware in that case. > > > > > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1447 > > > Signed-off-by: Alistair Francis > > > --- > > > hw/riscv/boot.c | 9 +++++++++ > > > 1 file changed, 9 insertions(+) > > > > > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > > > index 2594276223..cb27798a25 100644 > > > --- a/hw/riscv/boot.c > > > +++ b/hw/riscv/boot.c > > > @@ -356,6 +356,15 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts > > > reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ > > > } > > > > > > + if (!harts->harts[0].cfg.ext_icsr) { > > > + /* > > > + * The Zicsr extension has been disabled, so let's ensure we don't > > > + * run the CSR instruction. Let's fill the address with a non > > > + * compressed nop. > > > + */ > > > + reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */ > > > + } > > > > This is fine for a UP system. I am not sure how SMP can be supported > > without Zicsr as we need to assign hartid in a0. > > Yeah. My thinking was that no one would be using a multicore system > without Zicsr as it's such a core extension. If they are running > without Zicsr they have probably hard coded a lot of things anyway and > don't expect this to work. > > In general I think it's pretty rare to even run a RISC-V core without > Zicsr at all. > As QEMU implements Zicsr anyway, and there is no way to support SMP without Zicsr, should we disallow user to disable Zicsr in QEMU? Regards, Bin From MAILER-DAEMON Thu Jan 26 07:08:07 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pL12y-0003GK-W5 for mharc-qemu-riscv@gnu.org; Thu, 26 Jan 2023 07:08:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pL12r-0003AF-2n; Thu, 26 Jan 2023 07:07:58 -0500 Received: from mail-ej1-x62a.google.com ([2a00:1450:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pL12p-0005k8-7x; Thu, 26 Jan 2023 07:07:56 -0500 Received: by mail-ej1-x62a.google.com with SMTP id kt14so4506722ejc.3; Thu, 26 Jan 2023 04:07:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=ozZDDQPu756cdggNVo7hNGEpna7Trfyoz81RZ42y4VY=; b=MdsV64vqKhMaf78PyKmquIxNLfxmO0ahIMOIpuuAVVP+X0oTOLjcb+vq8p2hIfPu+D wwuyMKpBo6RttpotDOyDKaV66KQcx4hIytw5rZf4z136Y6MoR3NsjZxI8hr/L1acUb33 T9ueCE5BwjxXKOwvUkqFGvlvpszerL4kh/iKmYknqFu8KmEVcr53DFNkRUxAEjzmBmq4 RtCsi7hXXk9dHr32y/vv3Q/F4s8GYOxVHRHVqznw16IxCYYE4ejwTjQ+Sso0vyaHEMgN 1r7RtPy94UdVnopG0xCoZnL0yePd47GFN8WjQszThXPNMj6XHgn7FRnCwTEQ9ettKpdd Qvfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=ozZDDQPu756cdggNVo7hNGEpna7Trfyoz81RZ42y4VY=; b=DXd0llux7X9HJ735Gd8XTw0ahY+nUMOVCWEQ3GaRrCGDpbZhg+RePMNA4DmfGT6LUX 058JnBJ5eKaDKpdn0WoQy14IDIgdETnv6+Xb1BGlID6YHCEFTibuY66P3eeEcX9cMpxU tpIQwoh9kaNSG3ByYNBB38onKqyvqUJb+HqmsPcRZ7xgqq6cuiCZgLw8IyWwyYGJiYht XhuWYZjovI/hRWaDFOJzB7BXVpgCCvcruvmY0ZSQcjAz/EIUZGhawlFlsuSoKRX7Qdrj X93YyJQZXF3OsrsS9lGlhD2A/y2cF3eQn91N87+3CQ/XwUxg2S03etnaG9NB4esz89lU CK9A== X-Gm-Message-State: AO0yUKWAovLfPr9mJrlRkjo1rHoXlg5E4cG+ZgyczjnwrRnU+MJ7pIy/ Q8Iwumb1f6lpZm7HL3Iu0USVafteJX8yIquFOiEEWqbY X-Google-Smtp-Source: AK7set/zby+EGgWdFCPSsduz2ZbIj2gP+ARvJKvQEQDMv4OMZkKohoGnXZhm+jA6QWTNyOTH/owbwyNWZ34HxgdoddA= X-Received: by 2002:a17:906:8514:b0:878:786e:8c39 with SMTP id i20-20020a170906851400b00878786e8c39mr138062ejx.105.1674734871894; Thu, 26 Jan 2023 04:07:51 -0800 (PST) MIME-Version: 1.0 References: <20230113171805.470252-1-dbarboza@ventanamicro.com> <20230113171805.470252-4-dbarboza@ventanamicro.com> In-Reply-To: From: Bin Meng Date: Thu, 26 Jan 2023 20:07:40 +0800 Message-ID: Subject: Re: [PATCH v7 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym() To: Alistair Francis Cc: Daniel Henrique Barboza , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Jan 2023 12:08:03 -0000 Hi Alistair, On Mon, Jan 16, 2023 at 12:28 PM Alistair Francis wrote: > > On Sat, Jan 14, 2023 at 11:41 PM Bin Meng wrote: > > > > On Sat, Jan 14, 2023 at 1:18 AM Daniel Henrique Barboza > > wrote: > > > > > > Recent hw/risc/boot.c changes caused a regression in an use case with > > > the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel' > > > stopped working. The reason seems to be that Xvisor is using 64 bit to > > > encode the 32 bit addresses from the guest, and load_elf_ram_sym() is > > > sign-extending the result with '1's [1]. > > > > I would say it's not a regression of QEMU but something weird happened > > to Alistair's 32-bit Xvisor image. > > I don't think it's a Xvisor issue. > > > > > I just built a 32-bit Xvisor image from the latest Xvisor head > > following the instructions provided in its source tree. With the > > mainline QEMU only BIN file boots, but ELF does not. My 32-bit Xvisor > > image has an address of 0x10000000. Apparently this address is not > > correct, and the issue I saw is different from Alistair's. Alistair, > > could you investigate why your 32-bit Xvisor ELF image has an address > > of 0xffffffff80000000 set to kernel_load_base? > > Looking in load_elf() in include/hw/elf_ops.h at this line: > > if (lowaddr) > *lowaddr = (uint64_t)(elf_sword)low; > > I can see that `low` is 0x80000000 but lowaddr is set to > 0xffffffff80000000. So the address is being sign extended with 1s. > I don't understand the sign extension here. This seems intentional as the codes does the signed extension then casted to unsigned 64-bit. Do you know why? > This patch seems to be the correct fix. > Regards, Bin From MAILER-DAEMON Thu Jan 26 08:52:34 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pL2g6-0003dK-K3 for mharc-qemu-riscv@gnu.org; Thu, 26 Jan 2023 08:52:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pL2g2-0003c2-4Z for qemu-riscv@nongnu.org; Thu, 26 Jan 2023 08:52:31 -0500 Received: from mail-ot1-x343.google.com ([2607:f8b0:4864:20::343]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pL2fz-000437-9v for qemu-riscv@nongnu.org; Thu, 26 Jan 2023 08:52:28 -0500 Received: by mail-ot1-x343.google.com with SMTP id g2-20020a9d6b02000000b006864bf5e658so833559otp.1 for ; Thu, 26 Jan 2023 05:52:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=d1knL1PmLCMTfdnT7lvIVkkfe7oOtwmHZaVkSwNWmqw=; b=QitkWlK1WurRhOImB4F+o4hbcghU1t9PZuTGbiFZV/sOD5OSZKTtSnjR2Zc0QGX7dx GDc3EsjvifediunAkPanKvDNg//XLRkU8prHpyGy7sGu2GxaP+wo1kZzRlYBDtekpUuC 48XTiJD+VgNY5g2dKFJUWE9lJg05cTRicd8xBF+Oq+nOoAepxUgKMVZStifalXvM50TA 6R13aFbCv06T1hmoN8K1Wt3feV9jsKeblplIWMIzIwD1aBFQcjGYEtuOem4wGR4jCaC6 0nceJHt3EF+j+/gutG+KPQhkigQML6gjo/t43JI7NN1nCvEK2B8C1jGAse5TgVuG/hXZ 2S0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=d1knL1PmLCMTfdnT7lvIVkkfe7oOtwmHZaVkSwNWmqw=; b=qHl0b0/TFjgfs7l0pymk0/fcPNnHK66kCfZ1z6F4fZZ/joSCrqQCD1mO5ey3os90cL Ke54I+NHvru814/SGbih0olArq3yuHY4uyGebdYt3eZU7vNkGOxB1Z116HG65vtakGv1 oAVHCvXMPlj6RcElnXIEhPIoub5HqGdeyge/xl09EOjEMJvpBHpA2ASJRmetNKHAIFyL OgZ6mFHHcssyTSG9bkr526vnsbqPk3W1V6xSfO9HhQg1mXbojC4jtNs2f1tYzKdFa6UQ lGvqFzL6arKDaEtUTuh8LMdR+97GRfGKjbwQJVRqPPCd3VVlDIkxySAtkouKH7v1orR2 GYVw== X-Gm-Message-State: AFqh2kpvdrvzBTtfTw4q1ovMPJizGfaFl70mlYCPQEcI6d1/ZS56Kmvb imvG192YsWAUNhmed+PSYGo4ag== X-Google-Smtp-Source: AMrXdXuhkf7F4ATl6Y3nqZlQ3OXKc60D0jpBgIRVz5DMWIzI9FXv58cOL6rtU+gcBcLD4ORL8dfXdw== X-Received: by 2002:a9d:12a4:0:b0:686:628b:a9d9 with SMTP id g33-20020a9d12a4000000b00686628ba9d9mr14103789otg.14.1674741145416; Thu, 26 Jan 2023 05:52:25 -0800 (PST) Received: from grind.dc1.ventanamicro.com (200-148-13-157.dsl.telesp.net.br. [200.148.13.157]) by smtp.gmail.com with ESMTPSA id w19-20020a9d77d3000000b00661b46cc26bsm496323otl.9.2023.01.26.05.52.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 05:52:24 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v4 0/3] riscv_load_fdt() semantics change Date: Thu, 26 Jan 2023 10:52:16 -0300 Message-Id: <20230126135219.1054658-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::343; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x343.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Jan 2023 13:52:31 -0000 Hi, After discussions in the previous version, where we ended up discovering the details of why the current riscv_load_fdt() works with the Microchip Icicle Kit board almost by accident, I decided to change how riscv_compute_fdt_addr() (the FDT address calculation from riscv_load_fdt()) operates. Instead of relying on premises that the Icicle Kit board can't hold right from start, since dram_base + mem_size will never be contained in a contiguous RAM area, change the FDT address calculation to also receive the bondaries of the DRAM block that the board guarantees that it's not sparse. With this extra information we're able to make a more consistent FDT address calculation that will cover all existing cases we have today. Changes from v3: - patch 3: - function to handle Icicle Kit FDT separately: discarded - change riscv_compute_fdt_addr() to clearly handle cases like the Icicle Kit board where not all RAM is contiguous - v3 link: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg04464.html Daniel Henrique Barboza (3): hw/riscv/boot.c: calculate fdt size after fdt_pack() hw/riscv: split fdt address calculation from fdt load hw/riscv: change riscv_compute_fdt_addr() semantics hw/riscv/boot.c | 56 +++++++++++++++++++++++++++++++------- hw/riscv/microchip_pfsoc.c | 7 +++-- hw/riscv/sifive_u.c | 8 ++++-- hw/riscv/spike.c | 7 +++-- hw/riscv/virt.c | 8 ++++-- include/hw/riscv/boot.h | 4 ++- 6 files changed, 68 insertions(+), 22 deletions(-) -- 2.39.1 From MAILER-DAEMON Thu Jan 26 08:52:35 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pL2g7-0003di-Jc for mharc-qemu-riscv@gnu.org; Thu, 26 Jan 2023 08:52:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pL2g4-0003ch-Aq for qemu-riscv@nongnu.org; Thu, 26 Jan 2023 08:52:33 -0500 Received: from mail-ot1-x334.google.com ([2607:f8b0:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pL2g1-00043T-JQ for qemu-riscv@nongnu.org; Thu, 26 Jan 2023 08:52:32 -0500 Received: by mail-ot1-x334.google.com with SMTP id g2-20020a9d6b02000000b006864bf5e658so833580otp.1 for ; Thu, 26 Jan 2023 05:52:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mxEbgjU5aR+oYquuJNQfmH8bDfSRZI4C/R+GpocfbUU=; b=bAvDSRmBFUuJkmr4IsvIij0ABtll3YYYB/6wTXyyku/jVNEdS/8QKX/dhEkn3mlij5 KxIdRClG/LSNDRfwHLtzvTvt/GZqrAJypwSKwAY4OJUskXfwDqsnZoCndXuFsiNZQYE5 3pu8daJDu1r8RUumLWmYFmdA7pxgjqqPisUqWwKby9kfi/Z4ROCac+VAb2tMWG3uOky2 t68RMzdjhUZI6lWncEXvmwBA4pFQQ9x/8x2Fq7YFwHKYW0lryG8NPY4+HKuC1/jYvZN9 jbBnp/GIaGHH0SwEnfuhXV2sev3HD5B4IVR+zbuEUHKmHPDyHXai5XrpFke8OsO3Ay83 LYVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mxEbgjU5aR+oYquuJNQfmH8bDfSRZI4C/R+GpocfbUU=; b=4eEnPzm9CNLG2cI3pfDh+Oe1KqhGW4oOzB9c7uHzwxNDtfJ7MlH/EOe9HNM7Ttuz/k bF0R+v1quYJ9heEdLfDrymylOKZrpRc18H0vs2Y0USg4nVPq0rkySUqpO53eLOh6s/DF YUzeTXlBlBzZOIPdU4G85PiFjh7zjiQlHxZDCdA8cBOU/P7Mswk9OI0l8pDV1mhdlWSt EzR+5VtiNrYffXwp/z3PSs3z4bbljCw+B/C6oZQiT4xg7Nwa9YH9xHrouSBGAHxNlzIL ihG4Y6B4XUU5fYCYJ7cYZWM+g3LCfjSkHNZBKRRhlZowGd2wW1Xk+NAUk05sK5kFGJsT rQrw== X-Gm-Message-State: AO0yUKXdlpUepV7A/VXhqG7y3eCUme/f3zlkucusgSL+9pMc+OWO2D4/ hRI6W/cF99D/TkvEVpFaBLly82FQFvBrQuV+lTM= X-Google-Smtp-Source: AK7set/k15wnJxSWRgAyFRWeZR7ga6ybjDtDjFSyKgTKNCavX825cV1qqIhzP+u4p7YCOKLPqOa8pQ== X-Received: by 2002:a9d:174:0:b0:686:4528:8b9a with SMTP id 107-20020a9d0174000000b0068645288b9amr1078715otu.13.1674741147487; Thu, 26 Jan 2023 05:52:27 -0800 (PST) Received: from grind.dc1.ventanamicro.com (200-148-13-157.dsl.telesp.net.br. [200.148.13.157]) by smtp.gmail.com with ESMTPSA id w19-20020a9d77d3000000b00661b46cc26bsm496323otl.9.2023.01.26.05.52.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 05:52:27 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v4 1/3] hw/riscv/boot.c: calculate fdt size after fdt_pack() Date: Thu, 26 Jan 2023 10:52:17 -0300 Message-Id: <20230126135219.1054658-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230126135219.1054658-1-dbarboza@ventanamicro.com> References: <20230126135219.1054658-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Jan 2023 13:52:33 -0000 fdt_pack() can change the fdt size, meaning that fdt_totalsize() can contain a now deprecated (bigger) value. Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 3172a76220..a563b7482a 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -287,8 +287,13 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) { uint64_t temp, fdt_addr; hwaddr dram_end = dram_base + mem_size; - int ret, fdtsize = fdt_totalsize(fdt); + int ret = fdt_pack(fdt); + int fdtsize; + /* Should only fail if we've built a corrupted tree */ + g_assert(ret == 0); + + fdtsize = fdt_totalsize(fdt); if (fdtsize <= 0) { error_report("invalid device-tree"); exit(1); -- 2.39.1 From MAILER-DAEMON Thu Jan 26 08:52:37 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pL2g7-0003e2-PQ for mharc-qemu-riscv@gnu.org; Thu, 26 Jan 2023 08:52:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pL2g5-0003cm-1K for qemu-riscv@nongnu.org; Thu, 26 Jan 2023 08:52:33 -0500 Received: from mail-oi1-x232.google.com ([2607:f8b0:4864:20::232]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pL2g2-00043z-Ud for qemu-riscv@nongnu.org; Thu, 26 Jan 2023 08:52:32 -0500 Received: by mail-oi1-x232.google.com with SMTP id i9so1426429oif.4 for ; Thu, 26 Jan 2023 05:52:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J7bp6OWxKmqGSF5SEiZBAGPU/QdVvSpCmmITMPl8D0o=; b=A3GD4qNst3zaCM83QgWFYix9P0svsdTKPmsLQda1l2A0BUp4oh9URMUY97crsS6c2X 4GU83PFNonO2DlHOoaaT/LId7cRxblEuziOXNKCBm2oxpmeEDujdvdmMm6Eggs0inESZ ARrVhOGykRAVvgEyanKZ9fu/0ZiDaKC2yYNOgmrkvZbTs4LJivs4TqIjjtRa1Pq+Q6/V R1fUZxIhMVKWvrrT8gb66WGuY9dLjlA5/HOEWcLN33M9WCWM1thoZBPsFZXEentVaii7 LdmkIBgMFBxVRBMNDifruXv0VyX/DWckj4y0Bl8kfIckkq7s53Yg5Xsbwx2d8OKoN6Kj heyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J7bp6OWxKmqGSF5SEiZBAGPU/QdVvSpCmmITMPl8D0o=; b=Sc7YuRfeTFwwgI9SK8tPVs16HAGdcugpZTQW4xd2UPucdsWGEsLMFMWbH/G1ZfmTCC WouEoBQDFXAAzea5L46+CKvJRVSuv5FKkINoZlTDKHVjnVyRAMqAYz8mdUgbzoz5C+dg EzC95sFEZKTF5gde830s8kxLUhvQT+Yg0ydIN75dzRcLHAwnbYwlNQXuOvkoGc3I+QSg dFiv/rMud7EdB/AHXfMNGANki6Kl/l3SkcaWw28dL7C2pJTiU+gS3Lt+Uy9r5X3e5uo+ Az6DPQJ4Q+bdSdTR2OiL94Y3+Ps4nEBgx97xjO76GkkQCBk3cqy93VezBMbWLdTcDh34 vz2w== X-Gm-Message-State: AFqh2krCaQdiz9nNcVXmW2yTgbQD4o3fSY+s5YYl+SpVph3g1cZNbGWt XWjSNXoYmBVJ2x581mpHUzgf6w== X-Google-Smtp-Source: AMrXdXvt6pffvoqelaHZVawGGcMmL3SdAa+ScoInhgFypDphwdebx62VyQkYslawKHdevQrcm4goUQ== X-Received: by 2002:a54:4195:0:b0:35e:1a0f:7dc0 with SMTP id 21-20020a544195000000b0035e1a0f7dc0mr14207849oiy.8.1674741149532; Thu, 26 Jan 2023 05:52:29 -0800 (PST) Received: from grind.dc1.ventanamicro.com (200-148-13-157.dsl.telesp.net.br. [200.148.13.157]) by smtp.gmail.com with ESMTPSA id w19-20020a9d77d3000000b00661b46cc26bsm496323otl.9.2023.01.26.05.52.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 05:52:29 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v4 2/3] hw/riscv: split fdt address calculation from fdt load Date: Thu, 26 Jan 2023 10:52:18 -0300 Message-Id: <20230126135219.1054658-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230126135219.1054658-1-dbarboza@ventanamicro.com> References: <20230126135219.1054658-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::232; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x232.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Jan 2023 13:52:33 -0000 A common trend in other archs is to calculate the fdt address, which is usually straightforward, and then calling a function that loads the fdt/dtb by using that address. riscv_load_fdt() is doing a bit too much in comparison. It's calculating the fdt address via an elaborated heuristic to put the FDT at the bottom of DRAM, and "bottom of DRAM" will vary across boards and configurations, then it's actually loading the fdt, and finally it's returning the fdt address used to the caller. Reduce the existing complexity of riscv_load_fdt() by splitting its code into a new function, riscv_compute_fdt_addr(), that will take care of all fdt address logic. riscv_load_fdt() can then be a simple function that just loads a fdt at the given fdt address. We're also taken the opportunity to clarify the intentions and assumptions made by these functions. riscv_load_fdt() is now receiving a hwaddr as fdt_addr because there is no restriction of having to load the fdt in higher addresses that doesn't fit in an uint32_t. Reviewed-by: Alistair Francis Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 33 +++++++++++++++++++++++++-------- hw/riscv/microchip_pfsoc.c | 6 ++++-- hw/riscv/sifive_u.c | 7 ++++--- hw/riscv/spike.c | 6 +++--- hw/riscv/virt.c | 7 ++++--- include/hw/riscv/boot.h | 4 +++- 6 files changed, 43 insertions(+), 20 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index a563b7482a..a6f7b8ae8e 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -283,9 +283,21 @@ out: return kernel_entry; } -uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) +/* + * The FDT should be put at the farthest point possible to + * avoid overwriting it with the kernel/initrd. + * + * This function makes an assumption that the DRAM is + * contiguous. It also cares about 32-bit systems and + * will limit fdt_addr to be addressable by them even for + * 64-bit CPUs. + * + * The FDT is fdt_packed() during the calculation. + */ +uint32_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size, + void *fdt) { - uint64_t temp, fdt_addr; + uint64_t temp; hwaddr dram_end = dram_base + mem_size; int ret = fdt_pack(fdt); int fdtsize; @@ -306,11 +318,18 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) * end of dram or 3GB whichever is lesser. */ temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; - fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); - ret = fdt_pack(fdt); - /* Should only fail if we've built a corrupted tree */ - g_assert(ret == 0); + return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); +} + +/* + * 'fdt_addr' is received as hwaddr because boards might put + * the FDT beyond 32-bit addressing boundary. + */ +void riscv_load_fdt(hwaddr fdt_addr, void *fdt) +{ + uint32_t fdtsize = fdt_totalsize(fdt); + /* copy in the device tree */ qemu_fdt_dumpdtb(fdt, fdtsize); @@ -318,8 +337,6 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) &address_space_memory); qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize)); - - return fdt_addr; } void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index b7e171b605..a30203db85 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -633,8 +633,10 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) kernel_start_addr, true, NULL); /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base, + machine->ram_size, machine->fdt); + riscv_load_fdt(fdt_load_addr, machine->fdt); + /* Load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr, memmap[MICROCHIP_PFSOC_ENVM_DATA].base, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index b0b3e6f03a..6bbdbe5fb7 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -608,9 +608,10 @@ static void sifive_u_machine_init(MachineState *machine) kernel_entry = 0; } - /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, + machine->ram_size, machine->fdt); + riscv_load_fdt(fdt_load_addr, machine->fdt); + if (!riscv_is_32bit(&s->soc.u_cpus)) { start_addr_hi32 = (uint64_t)start_addr >> 32; } diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 483581e05f..ceebe34c5f 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -316,9 +316,9 @@ static void spike_board_init(MachineState *machine) kernel_entry = 0; } - /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, + machine->ram_size, machine->fdt); + riscv_load_fdt(fdt_load_addr, machine->fdt); /* load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 48326406fd..43fca597f0 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1292,9 +1292,10 @@ static void virt_machine_done(Notifier *notifier, void *data) start_addr = virt_memmap[VIRT_FLASH].base; } - /* Compute the fdt load address in dram */ - fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, - machine->ram_size, machine->fdt); + fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, + machine->ram_size, machine->fdt); + riscv_load_fdt(fdt_load_addr, machine->fdt); + /* load the reset vector */ riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, virt_memmap[VIRT_MROM].base, diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index bc9faed397..7babd669c7 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -48,7 +48,9 @@ target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, bool load_initrd, symbol_fn_t sym_cb); -uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); +uint32_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, + void *fdt); +void riscv_load_fdt(hwaddr fdt_addr, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr, hwaddr rom_base, hwaddr rom_size, -- 2.39.1 From MAILER-DAEMON Thu Jan 26 08:52:40 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pL2gB-0003fF-O7 for mharc-qemu-riscv@gnu.org; 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[200.148.13.157]) by smtp.gmail.com with ESMTPSA id w19-20020a9d77d3000000b00661b46cc26bsm496323otl.9.2023.01.26.05.52.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 05:52:31 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v4 3/3] hw/riscv: change riscv_compute_fdt_addr() semantics Date: Thu, 26 Jan 2023 10:52:19 -0300 Message-Id: <20230126135219.1054658-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230126135219.1054658-1-dbarboza@ventanamicro.com> References: <20230126135219.1054658-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Jan 2023 13:52:35 -0000 As it is now, riscv_compute_fdt_addr() is receiving a dram_base, a mem_size (which is defaulted to MachineState::ram_size in all boards) and the FDT pointer. And it makes a very important assumption: the DRAM interval dram_base + mem_size is contiguous. This is indeed the case for most boards that uses a FDT. The Icicle Kit board works with 2 distinct RAM banks that are separated by a gap. We have a lower bank with 1GiB size, a gap follows, then at 64GiB the high memory starts. MachineClass::default_ram_size for this board is set to 1.5Gb, and machine_init() is enforcing it as minimal RAM size, meaning that there we'll always have at least 512 MiB in the Hi RAM area. Using riscv_compute_fdt_addr() in this board is weird because not only the board has sparse RAM, and it's calling it using the base address of the Lo RAM area, but it's also using a mem_size that we have guarantees that it will go up to the Hi RAM. All the function assumptions doesn't work for this board. In fact, what makes the function works at all in this case is a coincidence. Commit 1a475d39ef54 introduced a 3GB boundary for the FDT, down from 4Gb, that is enforced if dram_base is lower than 3072 MiB. For the Icicle Kit board, memmap[MICROCHIP_PFSOC_DRAM_LO].base is 0x80000000 (2 Gb) and it has a 1Gb size, so it will fall in the conditions to put the FDT under a 3Gb address, which happens to be exactly at the end of DRAM_LO. If the base address of the Lo area started later than 3Gb this function would be unusable by the board. Changing any assumptions inside riscv_compute_fdt_addr() can also break it by accident as well. Let's change riscv_compute_fdt_addr() semantics to be appropriate to the Icicle Kit board and for future boards that might have sparse RAM topologies to worry about: - relieve the condition that the dram_base + mem_size area is contiguous, since this is already not the case today; - receive an extra 'dram_size' size attribute that refers to a contiguous RAM block that the board wants the FDT to reside on. Together with 'mem_size' and 'fdt', which are now now being consumed by a MachineState pointer, we're able to make clear assumptions based on the DRAM block and total mem_size available to ensure that the FDT will be put in a valid RAM address. Signed-off-by: Daniel Henrique Barboza --- hw/riscv/boot.c | 38 ++++++++++++++++++++++++++------------ hw/riscv/microchip_pfsoc.c | 3 ++- hw/riscv/sifive_u.c | 3 ++- hw/riscv/spike.c | 3 ++- hw/riscv/virt.c | 3 ++- include/hw/riscv/boot.h | 4 ++-- 6 files changed, 36 insertions(+), 18 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index a6f7b8ae8e..8f4991480b 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -284,33 +284,47 @@ out: } /* - * The FDT should be put at the farthest point possible to - * avoid overwriting it with the kernel/initrd. + * This function makes an assumption that the DRAM interval + * 'dram_base' + 'dram_size' is contiguous. * - * This function makes an assumption that the DRAM is - * contiguous. It also cares about 32-bit systems and - * will limit fdt_addr to be addressable by them even for - * 64-bit CPUs. + * Considering that 'dram_end' is the lowest value between + * the end of the DRAM block and MachineState->ram_size, the + * FDT location will vary according to 'dram_base': + * + * - if 'dram_base' is less that 3072 MiB, the FDT will be + * put at the lowest value between 3072 MiB and 'dram_end'; + * + * - if 'dram_base' is higher than 3072 MiB, the FDT will be + * put at 'dram_end'. * * The FDT is fdt_packed() during the calculation. */ -uint32_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size, - void *fdt) +hwaddr riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, + MachineState *ms) { - uint64_t temp; - hwaddr dram_end = dram_base + mem_size; - int ret = fdt_pack(fdt); + int ret = fdt_pack(ms->fdt); + hwaddr dram_end, temp; int fdtsize; /* Should only fail if we've built a corrupted tree */ g_assert(ret == 0); - fdtsize = fdt_totalsize(fdt); + fdtsize = fdt_totalsize(ms->fdt); if (fdtsize <= 0) { error_report("invalid device-tree"); exit(1); } + /* + * A dram_size == 0, usually from a MemMapEntry[].size element, + * means that the DRAM block goes all the way to ms->ram_size. + */ + if (dram_size == 0x0) { + dram_end = dram_base + ms->ram_size; + } else { + dram_end = dram_base + MIN(ms->ram_size, dram_size); + } + /* * We should put fdt as far as possible to avoid kernel/initrd overwriting * its content. But it should be addressable by 32 bit system as well. diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index a30203db85..e81bbd12df 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -634,7 +634,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) /* Compute the fdt load address in dram */ fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base, - machine->ram_size, machine->fdt); + memmap[MICROCHIP_PFSOC_DRAM_LO].size, + machine); riscv_load_fdt(fdt_load_addr, machine->fdt); /* Load the reset vector */ diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 6bbdbe5fb7..ad3bb35b34 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -609,7 +609,8 @@ static void sifive_u_machine_init(MachineState *machine) } fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, - machine->ram_size, machine->fdt); + memmap[SIFIVE_U_DEV_DRAM].size, + machine); riscv_load_fdt(fdt_load_addr, machine->fdt); if (!riscv_is_32bit(&s->soc.u_cpus)) { diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index ceebe34c5f..b5979eddd6 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -317,7 +317,8 @@ static void spike_board_init(MachineState *machine) } fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, - machine->ram_size, machine->fdt); + memmap[SPIKE_DRAM].size, + machine); riscv_load_fdt(fdt_load_addr, machine->fdt); /* load the reset vector */ diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 43fca597f0..f079a30b60 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1293,7 +1293,8 @@ static void virt_machine_done(Notifier *notifier, void *data) } fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, - machine->ram_size, machine->fdt); + memmap[VIRT_DRAM].size, + machine); riscv_load_fdt(fdt_load_addr, machine->fdt); /* load the reset vector */ diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 7babd669c7..a6099c2dc6 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -48,8 +48,8 @@ target_ulong riscv_load_kernel(MachineState *machine, target_ulong firmware_end_addr, bool load_initrd, symbol_fn_t sym_cb); -uint32_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, - void *fdt); +hwaddr riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, + MachineState *ms); void riscv_load_fdt(hwaddr fdt_addr, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr, -- 2.39.1 From MAILER-DAEMON Thu Jan 26 13:40:15 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pL7AU-0008Lt-Vq for mharc-qemu-riscv@gnu.org; Thu, 26 Jan 2023 13:40:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pL7AT-0008Lf-Nd; Thu, 26 Jan 2023 13:40:14 -0500 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pL7AS-0006w1-8R; Thu, 26 Jan 2023 13:40:13 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id BE14C61919; Thu, 26 Jan 2023 18:40:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 28A44C433D2; Thu, 26 Jan 2023 18:40:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1674758408; bh=e0C//wuvKVD9zed85QQkWU1A8Ukk9WLALPJMngLmHFs=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=aO0QRU+/9q8YSpU7lgp2T4lXXHIMP6Xg1bqdhUYbXneYd1E4VMpbDCAeKkM4T92hX 9NeAW4PxS7sn/Tu14NRJOyZsrEqFoRM0KkHkIV8ZvZXH74YzrtBvnHPkAQvLD3sq21 pYzUsJYZ/mat39gn7clJggK3gZ/qOkGtCZeCh9COhOE5fDn5p+VKELIG8dMJaPumzk 5qJH3YOhC/HZORoptVyG7ft0+QyWUh4+j+IAYtCAP7XKrnTow/aQCYzwZ4KgG/vxbt 5pwJFErZ1M+CeGYcKr5xR071Ooj9kSHoJPnGvNZBGyzKPErWwJl/EMw8UpQefyfVFJ SQXUW8MnO/e3w== Date: Thu, 26 Jan 2023 18:40:04 +0000 From: Conor Dooley To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Subject: Re: [PATCH v4 0/3] riscv_load_fdt() semantics change Message-ID: References: <20230126135219.1054658-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="8kz61MWQLtsspw2U" Content-Disposition: inline In-Reply-To: <20230126135219.1054658-1-dbarboza@ventanamicro.com> Received-SPF: pass client-ip=2604:1380:4641:c500::1; envelope-from=conor@kernel.org; helo=dfw.source.kernel.org X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Jan 2023 18:40:14 -0000 --8kz61MWQLtsspw2U Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Jan 26, 2023 at 10:52:16AM -0300, Daniel Henrique Barboza wrote: > Hi, >=20 > After discussions in the previous version, where we ended up discovering > the details of why the current riscv_load_fdt() works with the Microchip > Icicle Kit board almost by accident, I decided to change how > riscv_compute_fdt_addr() (the FDT address calculation from > riscv_load_fdt()) operates.=20 >=20 > Instead of relying on premises that the Icicle Kit board can't hold > right from start, since dram_base + mem_size will never be contained in > a contiguous RAM area, change the FDT address calculation to also > receive the bondaries of the DRAM block that the board guarantees that > it's not sparse. With this extra information we're able to make a more > consistent FDT address calculation that will cover all existing cases we > have today. The "test" case that fail before, is now back passing again. Thanks Daniel! Tested-by: Conor Dooley --8kz61MWQLtsspw2U Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY9LJBAAKCRB4tDGHoIJi 0m2zAQC9nF5qddNmQl7znhXV9/SrqYirNcqv641Pk7wmfLzNewEAkBRlfFIDW86H Yqo5BaQIfs2P2sKsN6TjOQkSpZCbeAw= =m5N9 -----END PGP SIGNATURE----- --8kz61MWQLtsspw2U-- From MAILER-DAEMON Thu Jan 26 13:52:22 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pL7MD-0006hk-Iv for mharc-qemu-riscv@gnu.org; Thu, 26 Jan 2023 13:52:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pL7LM-00063a-1x for qemu-riscv@nongnu.org; Thu, 26 Jan 2023 13:51:28 -0500 Received: from ams.source.kernel.org ([145.40.68.75]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pL7LK-0002xX-GT for qemu-riscv@nongnu.org; Thu, 26 Jan 2023 13:51:27 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 331C9B81EDF; Thu, 26 Jan 2023 18:51:24 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0962BC433D2; Thu, 26 Jan 2023 18:51:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1674759082; bh=8CAa1ig598cZkMIBh8o5mGnF0bobz6eP88r0ewRnrDk=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=T4Zx4L33ovU7AMv75Rrg1dakTiIStUdxiGfrX/xb3JoJADjK0MoyMIX4FWcpLBy8H yq3G2JG7Kyjoib7pQor3GkC1Wj7hVyGAfZsr6ZJH1HID/FYKmEEFq+/8S335T4G8JL ZvHF3IA8QPL3TOysFhCc4NnrA0y/Z2bCkGgWaNAvUqI3Iok77KPJt+NNtZiksvwtVh YCPdZ0mGRz6g7EoLCr5TZkAYvc4BmzhJD78cehUxKuF03F/BWeTF0frhpVtTtU0x1N nfHF3vNKYKEa1O6yQuxPAUHWQMMa3GKaMX8Wa0g7A6fzcRxc4SF4TL4k6iXW+czGlL pVcf6xGj3FpeA== Date: Thu, 26 Jan 2023 18:51:19 +0000 From: Conor Dooley To: Bin Meng Cc: stage TC , qemu-riscv@nongnu.org Subject: Re: qemu icicle kit es Message-ID: References: <2882065D-831B-4E8C-BFD3-677BB8ECA2AD@kernel.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="ZxGCtcIMQTSP7Q9y" Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=145.40.68.75; envelope-from=conor@kernel.org; helo=ams.source.kernel.org X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Jan 2023 18:51:28 -0000 --ZxGCtcIMQTSP7Q9y Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Jan 19, 2023 at 01:45:58PM +0800, Bin Meng wrote: > On Sat, Jan 14, 2023 at 10:30 PM Conor Dooley wrote: > > > > Perhaps if you still have the original wic image you'll have more luck! I can't find exactly where I mentioned it, but I asked around about the image that is listed in the docs. The answer I was pretty much "if it's not on the FTP any more, it's gone". Unfortunately, our Yocto stuff used autorev at that time so I am not sure if the image would even be re-creatable. --ZxGCtcIMQTSP7Q9y Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRh246EGq/8RLhDjO14tDGHoIJi0gUCY9LLpwAKCRB4tDGHoIJi 0g3iAP4wmsULmO9ADfe0LQVGpcc4+q3+7mMxadCG9McI+Hop/wD+Nm+cVux595Rw 9OwHtNF2f9Wb9dBfUpRptSQEcv2ppAA= =kKku -----END PGP SIGNATURE----- --ZxGCtcIMQTSP7Q9y-- From MAILER-DAEMON Fri Jan 27 07:01:50 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pLNQU-0003Dm-9l for mharc-qemu-riscv@gnu.org; Fri, 27 Jan 2023 07:01:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLNQS-0003Ct-9a for qemu-riscv@nongnu.org; Fri, 27 Jan 2023 07:01:48 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLNQP-0003Y1-D4 for qemu-riscv@nongnu.org; Fri, 27 Jan 2023 07:01:48 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674820904; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=ZpK5Tc64IDoUl1RuwOVz0IrTQMLUjbCIHprBMNSPciY=; b=He17aNaT81hTpvE3J0sS7yefgMMSpDxW2oHm7MBLRDBXLg9jWRzlvLhlW5lUD7Al7aOAyG SjtHD3SBPWD1NlN+9p1ON1RMoIYazsYLGj5j5ZWBNDv25QjzS+DXBwdXVM2xp0LtAU046/ +gjbfLVCSNTE0NC75Ru0x4H+UZ2bREg= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-648-TEZMbr0WN6Kg4skNhsk8Fw-1; Fri, 27 Jan 2023 07:01:40 -0500 X-MC-Unique: TEZMbr0WN6Kg4skNhsk8Fw-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id DEAF6857F48; Fri, 27 Jan 2023 12:01:39 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 677AC14171C0; Fri, 27 Jan 2023 12:01:38 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id A10E221E6A1F; Fri, 27 Jan 2023 13:01:36 +0100 (CET) From: Markus Armbruster To: Warner Losh Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 04/19] bsd-user: Clean up includes References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-5-armbru@redhat.com> <87r0vqpjbt.fsf@pond.sub.org> Date: Fri, 27 Jan 2023 13:01:36 +0100 In-Reply-To: (Warner Losh's message of "Thu, 19 Jan 2023 10:05:01 -0700") Message-ID: <87zga42nkv.fsf@pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Jan 2023 12:01:48 -0000 Warner Losh writes: [...] > So I'm happy with it. Thanks for the cleanup and the time to answer my > questions. > > Reviewed-by: Warner Losh Thank *you* for reviewing my patch :) From MAILER-DAEMON Fri Jan 27 07:05:32 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pLNTw-0007dN-Nc for mharc-qemu-riscv@gnu.org; Fri, 27 Jan 2023 07:05:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLNTs-0007JC-DW for qemu-riscv@nongnu.org; Fri, 27 Jan 2023 07:05:20 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLNTq-0004ci-5e for qemu-riscv@nongnu.org; Fri, 27 Jan 2023 07:05:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674821117; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+NHkTA5r3OIEcJQhnqhj4XyOXQN0y1Tqe9QrLqNZ2c8=; b=WbYsLMgEOjI3WFMWv1akbkcb4CmLdweNzy27/ejsxGdMsNMBwEYEDhH7Z3W9o8jKmEdE1g 6UPFO8eLZf0NqGUN+3EI8JPi6cCAy3dlyFPc0aLLVr+UKO+LeJJq7z98Bo9EZchYi86XHB vNOKhph9B/DjNCg51A4R/0uaxV0kHAs= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-70-aicR2qCsO0ypVV-D51APlQ-1; Fri, 27 Jan 2023 07:05:11 -0500 X-MC-Unique: aicR2qCsO0ypVV-D51APlQ-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 86A391C0A596; Fri, 27 Jan 2023 12:05:10 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 429872166B29; Fri, 27 Jan 2023 12:05:10 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 021B521E6A1F; Fri, 27 Jan 2023 13:05:09 +0100 (CET) From: Markus Armbruster To: Philippe =?utf-8?Q?Mathieu-Daud=C3=A9?= Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 16/19] Fix non-first inclusions of qemu/osdep.h References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-17-armbru@redhat.com> <873586u4yj.fsf@pond.sub.org> Date: Fri, 27 Jan 2023 13:05:08 +0100 In-Reply-To: ("Philippe =?utf-8?Q?Mathieu-Daud=C3=A9=22's?= message of "Thu, 19 Jan 2023 12:52:02 +0100") Message-ID: <87v8ks2nez.fsf@pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.1 on 10.11.54.6 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Jan 2023 12:05:21 -0000 Philippe Mathieu-Daud=C3=A9 writes: > On 19/1/23 12:41, Markus Armbruster wrote: >> Philippe Mathieu-Daud=C3=A9 writes: >>=20 >>> On 19/1/23 07:59, Markus Armbruster wrote: >>>> This commit was created with scripts/clean-includes. >>>> Signed-off-by: Markus Armbruster >> [...] >>=20 >>> Up to here: >>> >>> Reviewed-by: Philippe Mathieu-Daud=C3=A9 >>> >>>> diff --git a/util/async-teardown.c b/util/async-teardown.c >>>> index 62bfce1b3c..62cdeb0f20 100644 >>>> --- a/util/async-teardown.c >>>> +++ b/util/async-teardown.c >>>> @@ -10,16 +10,12 @@ >>>> * option) any later version. See the COPYING file in the top-leve= l directory. >>>> * >>>> */ >>>> -#include >>>> -#include >>>> -#include >>>> -#include >>>> -#include >>>> -#include >>>> -#include >>>> -#include >>>> #include "qemu/osdep.h" >>>> +#include >>>> +#include >>>> +#include >>>> + >>>> #include "qemu/async-teardown.h" >>> >>> This file has more changes. >> I'm not sure I understand. >> The patch does two related things: >> 1. It puts qemu/osdep.h first. The diff makes it look like we leave it >> in place and move other stuff across, but that's the same. >> 2. It deletes inclusions of headers qemu/osdep.h already includes: >> >> >> >> >> > > Ah, the other files get this done in the "Drop duplicate #include" patch. I assume this extends your R-by to the complete patch. Correct me if I'm wrong, please. From MAILER-DAEMON Fri Jan 27 09:54:50 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pLQ7t-0000w7-UG for mharc-qemu-riscv@gnu.org; Fri, 27 Jan 2023 09:54:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLQ7s-0000vU-90 for qemu-riscv@nongnu.org; Fri, 27 Jan 2023 09:54:48 -0500 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pLQ7n-00032u-Nw for qemu-riscv@nongnu.org; Fri, 27 Jan 2023 09:54:45 -0500 Received: by mail-pl1-x631.google.com with SMTP id z13so5177482plg.6 for ; Fri, 27 Jan 2023 06:54:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=LkDqyGrdQP09P8B3VOXn+2snrIqZ+RVtQwBSGQWoOuE=; b=tbV+DtYfL0Tt3h2SY0kE72VJ3f3GRcNM3eERMngALVTmFr4w3HvaHqdRSl/yJUNkfD 8KEda7J0BuobaAq6VsFTrGQBThFt6Tj9pra9379MYarW87eRD7Mij4dk1O3m2TTV0daQ V3uS9MpvkY+bPFmOCoB7tzKqzwRgCdDFhfpoTF0kkCwaobzit8vutClr+rSYX2R//XjB rgjArxqS+KjE/niw3FHKeefz8atQnLwnv/t396aRMcPhavopo2IWwtP5JhM2n5H8tk25 F3e4+UPYqlM2BJotAbFwRBq9Dsw8w/85a5xnj6gB/YaSAp1kR03Ez8iBW397pbhgohU4 aKTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=LkDqyGrdQP09P8B3VOXn+2snrIqZ+RVtQwBSGQWoOuE=; b=rChRLhFWhHJwvQpeFf9syrElPGHAzAD7CCr290pfQX6xihVsEPTWcTn45st29F5/it WkE+KZqIKVZIp4LgUu6sYJjaIHM3zVZQvwP0YREUJLGDowuxebfPWXgbBZ3mCV5CJCP8 QDQgjIRZSGYfIc12qkFZ5nUno44zHwvFTHBz6W5vevNOK0TzoRMB0MpSYAeNeq/buMQe NdMnTGZ5UqFCK+HIfIQtL5cPt68YISu2VWlva7HX3PXfOrMbDXNYY4JQ8IyW8WgYYXQw /OJcW+kpMtgMhA8IRUMT3thh/GuzvaNU5I4z+fOdteiUY6d7Aszro6guCQRnu2gUGC+6 kXmQ== X-Gm-Message-State: AO0yUKVZpDLlMSRHtHalppbsAXuRwFZCF7qEnaL9XtRwamD6hVpdMFgd 4orM5BVz8EG4RWLswGf3RUs1MdRKc1edZvK6BFev4w== X-Google-Smtp-Source: AK7set+BwyxAKfRkJOIWYhmGmtqgxW/nvVV/wOB8DP+JLuUxKYXjGigYlwPknE1fpi3tOE6uxD7mb3NqRa6uPxGwO8M= X-Received: by 2002:a17:90a:71c6:b0:22c:dfb:a9da with SMTP id m6-20020a17090a71c600b0022c0dfba9damr1928136pjs.115.1674831282251; Fri, 27 Jan 2023 06:54:42 -0800 (PST) MIME-Version: 1.0 References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-5-armbru@redhat.com> In-Reply-To: From: Peter Maydell Date: Fri, 27 Jan 2023 14:54:30 +0000 Message-ID: Subject: Re: [PATCH v4 04/19] bsd-user: Clean up includes To: Warner Losh Cc: Markus Armbruster , qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=peter.maydell@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Jan 2023 14:54:48 -0000 On Thu, 19 Jan 2023 at 14:42, Warner Losh wrote: > > Also, why didn't you move sys/resource.h and other such files > to os-dep.h? I'm struggling to understand the rules around what > is or isn't included where? The rough rule of thumb is that if some OS needs a compatibility fixup or workaround for a system header (eg not every mmap.h defines MAP_ANONYMOUS; on Windows unistd.h has to come before time.h) then we put that header include and the compat workaround into osdep.h. This avoids "only fails on obscure platform" issues where somebody puts a header include into some specific .c file but not the compat workaround, and it works on the Linux host that most people develop and test on and we only find the problem later. There's also no doubt some includes there for historical reasons, and some which really are "everybody needs these" convenience ones. But we should probably not add new includes to osdep.h unless they fall into the "working around system header issues" bucket. thanks -- PMM From MAILER-DAEMON Fri Jan 27 10:02:27 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pLQF5-0002Rk-ST for mharc-qemu-riscv@gnu.org; Fri, 27 Jan 2023 10:02:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLQF0-0002Qa-8s for qemu-riscv@nongnu.org; Fri, 27 Jan 2023 10:02:13 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLQEx-0004Ii-Ky for qemu-riscv@nongnu.org; Fri, 27 Jan 2023 10:02:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674831727; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=BCAWQePqlmcUdEfpPWmFWDPQKTGxJINbp8IdMUJzeiY=; b=K2mQtm2I2NeEk5u5lsIJ8wVkGAjBRx9hlEaITcISLrEzEWmIT3prrrARIOapgYP4vfR4gp aOW0zSGkD52wnytOtfF0M/cG2122LSqoXaZgFjAW+rJNjRAgBXpejodqwve8TqrCFyY9Sq eIrCDjmV/icAmL/ToY0YWzDH5FKuFkY= Received: from mail-lj1-f199.google.com (mail-lj1-f199.google.com [209.85.208.199]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-515-SatQ2BoVNA2bHonDaWXSPw-1; Fri, 27 Jan 2023 10:02:00 -0500 X-MC-Unique: SatQ2BoVNA2bHonDaWXSPw-1 Received: by mail-lj1-f199.google.com with SMTP id y9-20020a05651c154900b0028571631915so1414868ljp.18 for ; Fri, 27 Jan 2023 07:02:00 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=BCAWQePqlmcUdEfpPWmFWDPQKTGxJINbp8IdMUJzeiY=; b=FO841M+BZ5yKVB4uUGpYxjLkRvDiY3NQyvy//7/eotNS2IJSRrBzXoKUlNklfNAcf1 mbpB1HU+TbUFwW2JmuWyvXd0+XbdeSV6fwRQdEM2CGlbpZI7EZKK2uLH3LfsDQQVeXBB wYYYe44MzeIWAf6MIUVmqc3GtBufWI42unfKhiPOCbwN44Z269OrLWwTGkyrFDgkMImN jrO0cDf/pPMIDm+QGi0g4CXKqmICIfNKvEgfF6IbM/iVMjVZqE5JpIVQ/yH5LI90hiMD LZEWpIuaCdkLy98G2bVr/k6j/TvxHNcFcanAmeoT4tx+ivMSZ8GTTWFaie+YgJqyBJob BRTw== X-Gm-Message-State: AO0yUKWoUeed0USD2pfKP8vxHt0KD3tSeOFLaF0JrzvENG2Dr5BXg8Uw YdQgobrbtbTIZbQjrRmmS529uAkti1RlBy7izY92de46kGus6BDeqyDnRPe/VUtz3485IOp+FVP UBtIsQgnBXC2Y8y4= X-Received: by 2002:a2e:a4b6:0:b0:28f:8fa4:7c25 with SMTP id g22-20020a2ea4b6000000b0028f8fa47c25mr1203842ljm.25.1674831718788; Fri, 27 Jan 2023 07:01:58 -0800 (PST) X-Google-Smtp-Source: AK7set+JBei17P+JlKSLUUJ2snxVBR2+znakBl4L/6Mt+b5zgCQP9Nf+lOhDJKMfTt0XG4UjFdntSA== X-Received: by 2002:a2e:a4b6:0:b0:28f:8fa4:7c25 with SMTP id g22-20020a2ea4b6000000b0028f8fa47c25mr1203715ljm.25.1674831717017; Fri, 27 Jan 2023 07:01:57 -0800 (PST) Received: from redhat.com ([2.52.137.69]) by smtp.gmail.com with ESMTPSA id cm20-20020a170907939400b00871cb1b8f63sm2370175ejc.26.2023.01.27.07.01.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Jan 2023 07:01:56 -0800 (PST) Date: Fri, 27 Jan 2023 10:01:50 -0500 From: "Michael S. Tsirkin" To: Peter Maydell Cc: Warner Losh , Markus Armbruster , qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, philmd@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 04/19] bsd-user: Clean up includes Message-ID: <20230127100052-mutt-send-email-mst@kernel.org> References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-5-armbru@redhat.com> MIME-Version: 1.0 In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Jan 2023 15:02:14 -0000 On Fri, Jan 27, 2023 at 02:54:30PM +0000, Peter Maydell wrote: > On Thu, 19 Jan 2023 at 14:42, Warner Losh wrote: > > > > Also, why didn't you move sys/resource.h and other such files > > to os-dep.h? I'm struggling to understand the rules around what > > is or isn't included where? > > The rough rule of thumb is that if some OS needs a compatibility > fixup or workaround for a system header (eg not every mmap.h > defines MAP_ANONYMOUS; on Windows unistd.h has to come before > time.h) then we put that header include and the compat workaround > into osdep.h. This avoids "only fails on obscure platform" issues > where somebody puts a header include into some specific .c file > but not the compat workaround, and it works on the Linux host > that most people develop and test on and we only find the > problem later. > > There's also no doubt some includes there for historical > reasons, and some which really are "everybody needs these" > convenience ones. But we should probably not add new > includes to osdep.h unless they fall into the "working around > system header issues" bucket. > > thanks > -- PMM BTW maybe we should teach checkpatch about that rule: if a header is in osdep do not include it directly. -- MST From MAILER-DAEMON Fri Jan 27 15:36:17 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pLVSL-0007pl-77 for mharc-qemu-riscv@gnu.org; Fri, 27 Jan 2023 15:36:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLUGI-0000Y2-4f for qemu-riscv@nongnu.org; Fri, 27 Jan 2023 14:19:46 -0500 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pLUGG-0003eL-2c for qemu-riscv@nongnu.org; Fri, 27 Jan 2023 14:19:45 -0500 Received: by mail-pl1-x62f.google.com with SMTP id z13so5999851plg.6 for ; Fri, 27 Jan 2023 11:19:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=jKhtk5rxl5pbRoYF48eqgFTbbHBid5hhGXVt7A76ZuQ=; b=jkrUHGogXM1IVwB7vwddZQamh2RQpgQwLUpkue+ZJvq5+50hN6OdLimYXt4LQCNBZD a87nCjYlp23FKW8E9g6F9YFySavQTQ5AwUf6lSL9HW6b7zLXSMpoE9KaYh6yGV+HjeGv ZAuU1CFP6iBIdTNrAE5l3dioE9y2LcsaRPFtjE0prKGBhgUMSFpAVIOOv45MsN0MPW7+ S725RwBjbu/9cQkwDOp966XLaTJtbuk0GqKpLcC+YtvlHL69yh/7dYhWDigorVWgoepZ jdWQtn4+QdZAlqQSHHzZJOcOpWX+2u6Cokhh9e5VQhvCouqn8+5CHBjYaCuIz1tbhcGA ov2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=jKhtk5rxl5pbRoYF48eqgFTbbHBid5hhGXVt7A76ZuQ=; b=j5YPGOjXWZCG3wNi6nidJrTqSnbW8jjLMt6C66+HYxW1ZIZnvuCSFCOP8+xLo8rewD AMlhhuS1dWVZ3HGfwKqiO9Z+ulqa/5nmf1l2PmRd8MeF1EP4rZMccLCgvucmtkx8urFV n+pGewAV9oe7+Xc+1fvP7+0HbhceeiXN0Mic+ywHvElRfnyEDG66jJNUexJK4mMYx3hr CgDAu4g9gQUQRAykg7HqM5x3sbyNPkblQPs82UDXFWCaCBsbyjjweAdnstrpLSkONCgE iMP2hn6IarjP9Gj1PTTLvtKU7pq2k935dMXHychq6WHejSfo5iuZBEiqJXSOIpHAZ3Uu 6HuA== X-Gm-Message-State: AO0yUKUiy7PtQ329mjQ5UDKntXDOiAVV96Pkikhpa8PnFvh54kixHxhU ya2LVtooZJPAE4LcN/ulPp+o+te12F/R2UZFkWg= X-Google-Smtp-Source: AK7set94Y9obB3EFPKA5uq3XM0ReUFMnWSHTsvvSoCYinBw075FjFyzJqF6fsIn9wS0qAO0OL3+2rg== X-Received: by 2002:a17:902:6b89:b0:193:6520:739a with SMTP id p9-20020a1709026b8900b001936520739amr5678622plk.46.1674847182142; Fri, 27 Jan 2023 11:19:42 -0800 (PST) Received: from debug.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id x2-20020a170902820200b00196065e8d78sm3238688pln.50.2023.01.27.11.19.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Jan 2023 11:19:41 -0800 (PST) From: Deepak Gupta To: qemu-riscv@nongnu.org Cc: Deepak Gupta Subject: [PATCH: fix for virt instr exception] target/riscv: fix for virtual instr exception Date: Fri, 27 Jan 2023 11:19:38 -0800 Message-Id: <20230127191938.756071-1-debug@rivosinc.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=debug@rivosinc.com; helo=mail-pl1-x62f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 27 Jan 2023 15:36:14 -0500 X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Jan 2023 19:19:46 -0000 commit fb3f3730e4 added mechanism to generate virtual instruction exception during instruction decode when virt is enabled. However in some situations, illegal instruction exception can be raised due to state of CPU. One such situation is implementing branch tracking. [1] An indirect branch if doesn't land on a landing pad instruction, then cpu must raise an illegal instruction exception. Implementation would raise such expcetion due to missing landing pad inst and not due to decode. Thus DisasContext must have `virt_inst_excp` initialized to false during DisasContxt initialization for TB. [1] - https://github.com/riscv/riscv-cfi Signed-off-by: Deepak Gupta --- target/riscv/translate.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index df38db7553..76f61a39d3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1167,6 +1167,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->pm_base_enabled = FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLED); ctx->itrigger = FIELD_EX32(tb_flags, TB_FLAGS, ITRIGGER); ctx->zero = tcg_constant_tl(0); + ctx->virt_inst_excp = false; } static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) -- 2.25.1 From MAILER-DAEMON Fri Jan 27 16:29:46 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pLWI5-00088d-Vq for mharc-qemu-riscv@gnu.org; Fri, 27 Jan 2023 16:29:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLWI4-00088T-Uu for qemu-riscv@nongnu.org; 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Fri, 27 Jan 2023 16:29:39 -0500 X-MC-Unique: jClL65yzO6q0dGkB3TSMVQ-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id CA5D3811E6E; Fri, 27 Jan 2023 21:29:38 +0000 (UTC) Received: from redhat.com (unknown [10.2.17.173]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 2B90E14171BE; Fri, 27 Jan 2023 21:29:35 +0000 (UTC) Date: Fri, 27 Jan 2023 15:29:33 -0600 From: Eric Blake To: Markus Armbruster Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 01/19] scripts/clean-includes: Fully skip / ignore files Message-ID: <20230127212933.5bcwjqn6ht6fd7uq@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-2-armbru@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230119065959.3104012-2-armbru@redhat.com> User-Agent: NeoMutt/20220429 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 Received-SPF: pass client-ip=170.10.133.124; envelope-from=eblake@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Jan 2023 21:29:45 -0000 On Thu, Jan 19, 2023 at 07:59:41AM +0100, Markus Armbruster wrote: ... > > Fix the script to fully skip files. > > Fixes: fd3e39a40ca2ee26b09a5de3149af8b056b85233 > Fixes: d66253e46ae2b9c36a9dd90b2b74c0dfa5804b22 > Signed-off-by: Markus Armbruster > --- > scripts/clean-includes | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/scripts/clean-includes b/scripts/clean-includes > index d37bd4f692..86944f27fc 100755 > --- a/scripts/clean-includes > +++ b/scripts/clean-includes > @@ -111,6 +111,7 @@ cat >"$COCCIFILE" < ) > EOT > > +files= > for f in "$@"; do > case "$f" in > *.c.inc) > @@ -144,6 +145,7 @@ for f in "$@"; do > continue > ;; > esac > + files="$files $f" Bash's += might perform faster here, but this is a #!/bin/sh script. Reviewed-by: Eric Blake -- Eric Blake, Principal Software Engineer Red Hat, Inc. +1-919-301-3266 Virtualization: qemu.org | libvirt.org From MAILER-DAEMON Fri Jan 27 16:38:47 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pLWQp-00031S-93 for mharc-qemu-riscv@gnu.org; Fri, 27 Jan 2023 16:38:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLWQn-00030g-Uj for qemu-riscv@nongnu.org; Fri, 27 Jan 2023 16:38:45 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLWQk-0002qQ-Rr for qemu-riscv@nongnu.org; Fri, 27 Jan 2023 16:38:45 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674855521; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=Ya3zFGla2F6Utbg1telArH2Elj2nIZTjDf4ias2Q7yw=; b=RFffHq9PzZgAq3QSV6cmDLECgaCPR6uCsaXg4SkHq+uuIPpWotDVcC92CO8IosxInDdoko LqSfHf1Ac6vouV6/YHsL0r1U1XVmkoDFyMRiqFmAaPKlw4dClx34EuI6lhKH1l/+7oGNr7 mHIwFUGU5z9FQCu6K/kme6kNpZOocYg= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-331-TfwT3yR3MuiFniYt48dwAA-1; Fri, 27 Jan 2023 16:38:38 -0500 X-MC-Unique: TfwT3yR3MuiFniYt48dwAA-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 040C8101A55E; Fri, 27 Jan 2023 21:38:37 +0000 (UTC) Received: from redhat.com (unknown [10.2.17.173]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 214397AD4; Fri, 27 Jan 2023 21:38:34 +0000 (UTC) Date: Fri, 27 Jan 2023 15:38:32 -0600 From: Eric Blake To: Markus Armbruster Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 02/19] scripts/clean-includes: Don't claim duplicate headers found when not Message-ID: <20230127213832.qzjhacznhvpochpn@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-3-armbru@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230119065959.3104012-3-armbru@redhat.com> User-Agent: NeoMutt/20220429 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.5 Received-SPF: pass client-ip=170.10.129.124; envelope-from=eblake@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Jan 2023 21:38:46 -0000 On Thu, Jan 19, 2023 at 07:59:42AM +0100, Markus Armbruster wrote: > When running with --check-dup-head, the script always claims it "Found > duplicate header file includes." Fix to do it only when it actually > found some. > > Fixes: d66253e46ae2b9c36a9dd90b2b74c0dfa5804b22 > Signed-off-by: Markus Armbruster > --- > scripts/clean-includes | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > > diff --git a/scripts/clean-includes b/scripts/clean-includes > index 86944f27fc..8e8420d785 100755 > --- a/scripts/clean-includes > +++ b/scripts/clean-includes > @@ -177,9 +177,8 @@ for f in "$@"; do > done > > if [ "$DUPHEAD" = "yes" ] && [ -n "$files" ]; then > - egrep "^[[:space:]]*#[[:space:]]*include" $files | tr -d '[:blank:]' \ > - | sort | uniq -c | awk '{if ($1 > 1) print $0}' > - if [ $? -eq 0 ]; then > + if egrep "^[[:space:]]*#[[:space:]]*include" $files | tr -d '[:blank:]' \ > + | sort | uniq -c | grep -v '^ *1 '; then Indeed - the awk script was succeeding even if it printed nothing, whereas the grep -v is a bit lighter-weight and has the intended semantics of exit status based on output. Reviewed-by: Eric Blake > echo "Found duplicate header file includes. Please check the above files manually." > exit 1 > fi > -- > 2.39.0 > > -- Eric Blake, Principal Software Engineer Red Hat, Inc. +1-919-301-3266 Virtualization: qemu.org | libvirt.org From MAILER-DAEMON Fri Jan 27 17:48:18 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pLXVz-0002o4-2g for mharc-qemu-riscv@gnu.org; Fri, 27 Jan 2023 17:48:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLXVn-0002mT-1I for qemu-riscv@nongnu.org; Fri, 27 Jan 2023 17:47:59 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLXVk-0001f0-Ft for qemu-riscv@nongnu.org; Fri, 27 Jan 2023 17:47:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674859675; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=1e0/PGUN4/1YKyQq5ZEih9uomfIieCqX5fsFRyBTOgw=; b=YITe2UWRZz0lPayYMxqU6HLh/NzQEKInTV7mFzDi+aAVSg9k2L3JNOAI+UWDmAidrxG4xK KmJDjVhhlkAYer0a0m0mMuYv6gVrSTiOVp78MZvPLCMH8WtpHKU+sFrB2YLE6V32R7iTRP LnvFHC8nY7JnY+zcSxWRb4YSURuKIM0= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-484-8Chw50bYPpmpxbNeEHK_cw-1; Fri, 27 Jan 2023 17:47:52 -0500 X-MC-Unique: 8Chw50bYPpmpxbNeEHK_cw-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 620D7887400; Fri, 27 Jan 2023 22:47:51 +0000 (UTC) Received: from redhat.com (unknown [10.2.17.173]) by smtp.corp.redhat.com (Postfix) with ESMTPS id A40DC492B01; Fri, 27 Jan 2023 22:47:48 +0000 (UTC) Date: Fri, 27 Jan 2023 16:47:46 -0600 From: Eric Blake To: Markus Armbruster Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 03/19] scripts/clean-includes: Skip symbolic links Message-ID: <20230127224746.2rqorp2ushelp4wj@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-4-armbru@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230119065959.3104012-4-armbru@redhat.com> User-Agent: NeoMutt/20220429 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.133.124; envelope-from=eblake@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Jan 2023 22:47:59 -0000 On Thu, Jan 19, 2023 at 07:59:43AM +0100, Markus Armbruster wrote: > When a symbolic link points to a file that needs cleaning, the script > replaces the link with a cleaned regular file. Not wanted; skip them. > > We have a few symbolic links under subprojects/libvduse/ and > subprojects/libvhost-user/. > > Signed-off-by: Markus Armbruster > --- > scripts/clean-includes | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/scripts/clean-includes b/scripts/clean-includes > index 8e8420d785..f0466a6262 100755 > --- a/scripts/clean-includes > +++ b/scripts/clean-includes > @@ -113,6 +113,10 @@ EOT > > files= > for f in "$@"; do > + if [ -L "$f" ]; then I don't see -L used with test very often, but POSIX requires it, so it is safe for our choice of /bin/sh. Reviewed-by: Eric Blake -- Eric Blake, Principal Software Engineer Red Hat, Inc. +1-919-301-3266 Virtualization: qemu.org | libvirt.org From MAILER-DAEMON Fri Jan 27 17:55:39 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pLXdD-0005HF-7I for mharc-qemu-riscv@gnu.org; Fri, 27 Jan 2023 17:55:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLXdA-0005Gj-CV for qemu-riscv@nongnu.org; Fri, 27 Jan 2023 17:55:36 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLXd8-0002gu-AI for qemu-riscv@nongnu.org; Fri, 27 Jan 2023 17:55:36 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674860133; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=WryUFBl66HGK4gCI9EH/8uEtyd4e2kmqtTQTKV9nerQ=; b=ZeWHuOdepy3LYI2f9p44Ol4awVKZzbUwvWILwS96kioJCSfp6NhPHzN0Z9N8TLBcQ5oOU6 k0O/OWk3wZCnIzMn5TiC9P+4iJ+tf5z2vFT+Ty9hJc8zlywulLhGro9Tt9MJChYIH3gvwL qTcQXnmdmoVYZ97Z3x7cSEoAAc7rmv0= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-148-1jGQ55FrNy6C5QsacWUdMQ-1; Fri, 27 Jan 2023 17:55:29 -0500 X-MC-Unique: 1jGQ55FrNy6C5QsacWUdMQ-1 Received: from smtp.corp.redhat.com (int-mx09.intmail.prod.int.rdu2.redhat.com [10.11.54.9]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id E8EF829AA3B3; Fri, 27 Jan 2023 22:55:28 +0000 (UTC) Received: from redhat.com (unknown [10.2.17.173]) by smtp.corp.redhat.com (Postfix) with ESMTPS id AABD4492C14; Fri, 27 Jan 2023 22:55:26 +0000 (UTC) Date: Fri, 27 Jan 2023 16:55:25 -0600 From: Eric Blake To: Markus Armbruster Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 14/19] block: Clean up includes Message-ID: <20230127225525.t5bexrnx76a4oxdm@redhat.com> References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-15-armbru@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230119065959.3104012-15-armbru@redhat.com> User-Agent: NeoMutt/20220429 X-Scanned-By: MIMEDefang 3.1 on 10.11.54.9 Received-SPF: pass client-ip=170.10.133.124; envelope-from=eblake@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Jan 2023 22:55:37 -0000 On Thu, Jan 19, 2023 at 07:59:54AM +0100, Markus Armbruster wrote: > Clean up includes so that osdep.h is included first and headers > which it implies are not included manually. > > This commit was created with scripts/clean-includes. > > Signed-off-by: Markus Armbruster > --- > include/block/graph-lock.h | 1 - > include/block/write-threshold.h | 2 -- > block/qapi.c | 1 - > 3 files changed, 4 deletions(-) Reviewed-by: Eric Blake -- Eric Blake, Principal Software Engineer Red Hat, Inc. +1-919-301-3266 Virtualization: qemu.org | libvirt.org From MAILER-DAEMON Fri Jan 27 18:08:30 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pLXpe-0002RT-EA for mharc-qemu-riscv@gnu.org; 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boundary="0000000000003829ed05f346f145" Received-SPF: none client-ip=2a00:1450:4864:20::52c; envelope-from=wlosh@bsdimp.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 27 Jan 2023 23:08:29 -0000 --0000000000003829ed05f346f145 Content-Type: text/plain; charset="UTF-8" On Fri, Jan 27, 2023 at 3:47 PM Eric Blake wrote: > On Thu, Jan 19, 2023 at 07:59:43AM +0100, Markus Armbruster wrote: > > When a symbolic link points to a file that needs cleaning, the script > > replaces the link with a cleaned regular file. Not wanted; skip them. > > > > We have a few symbolic links under subprojects/libvduse/ and > > subprojects/libvhost-user/. > > > > Signed-off-by: Markus Armbruster > > --- > > scripts/clean-includes | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/scripts/clean-includes b/scripts/clean-includes > > index 8e8420d785..f0466a6262 100755 > > --- a/scripts/clean-includes > > +++ b/scripts/clean-includes > > @@ -113,6 +113,10 @@ EOT > > > > files= > > for f in "$@"; do > > + if [ -L "$f" ]; then > > I don't see -L used with test very often, but POSIX requires it, so it > is safe for our choice of /bin/sh. > FYI: -L is in FreeBSD, NetBSD, OpenBSD, etc. It's been in all these trees since the mid 90s. It wasn't in 4.4BSD, but all these projects have imported the code from pdksh's test. So in addition to POSIX, it's been widely implemented, at least in the BSD world, for over 20 years. Warner --0000000000003829ed05f346f145 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Fri, Jan 27, 2023 at 3:47 PM Eric = Blake <eblake@redhat.com> wr= ote:
On Thu, Jan= 19, 2023 at 07:59:43AM +0100, Markus Armbruster wrote:
> When a symbolic link points to a file that needs cleaning, the script<= br> > replaces the link with a cleaned regular file.=C2=A0 Not wanted; skip = them.
>
> We have a few symbolic links under subprojects/libvduse/ and
> subprojects/libvhost-user/.
>
> Signed-off-by: Markus Armbruster <armbru@redhat.com>
> ---
>=C2=A0 scripts/clean-includes | 4 ++++
>=C2=A0 1 file changed, 4 insertions(+)
>
> diff --git a/scripts/clean-includes b/scripts/clean-includes
> index 8e8420d785..f0466a6262 100755
> --- a/scripts/clean-includes
> +++ b/scripts/clean-includes
> @@ -113,6 +113,10 @@ EOT
>=C2=A0
>=C2=A0 files=3D
>=C2=A0 for f in "$@"; do
> +=C2=A0 if [ -L "$f" ]; then

I don't see -L used with test very often, but POSIX requires it, so it<= br> is safe for our choice of /bin/sh.

FYI:= -L is in FreeBSD, NetBSD, OpenBSD, etc. It's been in all these trees s= ince the mid 90s. It wasn't in 4.4BSD, but all these projects have impo= rted the code from pdksh's test.

So in additio= n to POSIX, it's been widely implemented, at least in the BSD world, fo= r over 20 years.

Warner
--0000000000003829ed05f346f145-- From MAILER-DAEMON Sat Jan 28 05:28:41 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pLiRt-0005FS-5B for mharc-qemu-riscv@gnu.org; Sat, 28 Jan 2023 05:28:41 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLiRp-0005Er-Eq for qemu-riscv@nongnu.org; Sat, 28 Jan 2023 05:28:37 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLiRn-0004AC-HW for qemu-riscv@nongnu.org; Sat, 28 Jan 2023 05:28:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674901714; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=onqBJLAeKWJ00rmW8PmLFuUlG7BY36S6l8hn+KpBJ40=; b=ArVzU5VH3oZcSYXQhkplr/SN86R4bnCkjNvXH6FI9TJVSV5MIrY/7Q1/n/x/helCr8Wd8m pm1l7ramWPK6IdqdHESQw5JpjPo3x1qROW4ZFoxaV8spRmkZBYfB7un36R0CkRyhoA1ra6 gXa1OMBoQJV0LgkXstwTDH4AY8EVo2Y= Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-125-n0iV9FFHPx-tkPQujyK4xg-1; Sat, 28 Jan 2023 05:28:33 -0500 X-MC-Unique: n0iV9FFHPx-tkPQujyK4xg-1 Received: by mail-wm1-f71.google.com with SMTP id l8-20020a05600c1d0800b003dc25f6bb5dso4207180wms.0 for ; Sat, 28 Jan 2023 02:28:32 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=onqBJLAeKWJ00rmW8PmLFuUlG7BY36S6l8hn+KpBJ40=; b=NFyUPxQmNECsUHjT33F4HRcDJH6wWxti2sbCyfXzrRWi5XPqR9+ZygD0CN1HpfB+74 P5lDkFJ830LjQlktgZwdeA4zKWUmipHmVMA025NRsMgsPwAJ4tL9MrnF3M8SH2dK6TBM 8JgBqX8oLE/7Jq6c5F1yaBsExytiSJDpUmNmAhylmjnDJLDgFNzH1rVPbrM/eZ/LtrrB nWE2xPWHvQHnaod6AKnagtqt1SVprbtXUR2pqc34zB2HlgH2f54DMZMQ+A6prAFKum5x wmlnLaU3229jUGEYmdjVTkYMZ3oxcPJYvkD5bpP2TSYTZ8W4QJaYWV5oRQPZrrrli5pe uWPw== X-Gm-Message-State: AFqh2kqqt0TZpZkUHqygGfzWQ9FN7z24ZPuU9UDWso+Q0DM38+dXT6hU IuTMjvd99jTL7OcLbtOL/BQXMW/kmsemoTGTAQF3mzfki5EJFEEt3TWCTI05CqMnwxftSESqeYY H8hBf7wWXrK+0Wbs= X-Received: by 2002:a05:600c:4fd3:b0:3cf:7197:e68a with SMTP id o19-20020a05600c4fd300b003cf7197e68amr40912372wmq.18.1674901711961; Sat, 28 Jan 2023 02:28:31 -0800 (PST) X-Google-Smtp-Source: AMrXdXt3lUkHn8aJG6qvJP8kZYFw9zdQXqkr1X9X+WoFGy4L56cs6qzCQ1Ax+cxM/ct9NBtuqpx90w== X-Received: by 2002:a05:600c:4fd3:b0:3cf:7197:e68a with SMTP id o19-20020a05600c4fd300b003cf7197e68amr40912341wmq.18.1674901711722; Sat, 28 Jan 2023 02:28:31 -0800 (PST) Received: from redhat.com ([2.52.20.248]) by smtp.gmail.com with ESMTPSA id z24-20020a1cf418000000b003dc36981727sm4465426wma.14.2023.01.28.02.28.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Jan 2023 02:28:31 -0800 (PST) Date: Sat, 28 Jan 2023 05:28:26 -0500 From: "Michael S. Tsirkin" To: Markus Armbruster Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 01/19] scripts/clean-includes: Fully skip / ignore files Message-ID: <20230128052749-mutt-send-email-mst@kernel.org> References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-2-armbru@redhat.com> MIME-Version: 1.0 In-Reply-To: <20230119065959.3104012-2-armbru@redhat.com> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=170.10.129.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 28 Jan 2023 10:28:37 -0000 On Thu, Jan 19, 2023 at 07:59:41AM +0100, Markus Armbruster wrote: > When clean-includes claims to skip or ignore a file, only the part > that sanitizes use of qemu/osdep.h skips the file. The part that > looks for duplicate #include does not, and neither does committing to > Git. > > The latter can get unrelated stuff included in the commit, but only if > you run clean-includes in a dirty tree, which is unwise. Messed up > when we added skipping in commit fd3e39a40c "scripts/clean-includes: > Enhance to handle header files". > > The former can cause bogus reports for --check-dup-head. Added in > commit d66253e46a "scripts/clean-includes: added duplicate #include > check", duplicating the prior mistake. > > Fix the script to fully skip files. > > Fixes: fd3e39a40ca2ee26b09a5de3149af8b056b85233 > Fixes: d66253e46ae2b9c36a9dd90b2b74c0dfa5804b22 Isn't Fixes: %h (\"%s\") the accepted format for this? > Signed-off-by: Markus Armbruster > --- > scripts/clean-includes | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/scripts/clean-includes b/scripts/clean-includes > index d37bd4f692..86944f27fc 100755 > --- a/scripts/clean-includes > +++ b/scripts/clean-includes > @@ -111,6 +111,7 @@ cat >"$COCCIFILE" < ) > EOT > > +files= > for f in "$@"; do > case "$f" in > *.c.inc) > @@ -144,6 +145,7 @@ for f in "$@"; do > continue > ;; > esac > + files="$files $f" > > if [ "$MODE" = "c" ]; then > # First, use Coccinelle to add qemu/osdep.h before the first existing include > @@ -174,8 +176,8 @@ for f in "$@"; do > > done > > -if [ "$DUPHEAD" = "yes" ]; then > - egrep "^[[:space:]]*#[[:space:]]*include" "$@" | tr -d '[:blank:]' \ > +if [ "$DUPHEAD" = "yes" ] && [ -n "$files" ]; then > + egrep "^[[:space:]]*#[[:space:]]*include" $files | tr -d '[:blank:]' \ > | sort | uniq -c | awk '{if ($1 > 1) print $0}' > if [ $? -eq 0 ]; then > echo "Found duplicate header file includes. Please check the above files manually." > @@ -184,7 +186,7 @@ if [ "$DUPHEAD" = "yes" ]; then > fi > > if [ "$GIT" = "yes" ]; then > - git add -- "$@" > + git add -- $files > git commit --signoff -F - < $GITSUBJ: Clean up includes > > -- > 2.39.0 From MAILER-DAEMON Sat Jan 28 05:30:00 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pLiTA-0006H0-3V for mharc-qemu-riscv@gnu.org; Sat, 28 Jan 2023 05:30:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLiT8-0006Gs-Hq for qemu-riscv@nongnu.org; Sat, 28 Jan 2023 05:29:58 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLiT6-0004IG-Ab for qemu-riscv@nongnu.org; Sat, 28 Jan 2023 05:29:57 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1674901795; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=6FB+edsbb44QCZ358g73Bl78hzSRCKhojxU7VjQ1JnU=; b=DqQ2siUyyzpGkblGexlCQ2MnoFhqe29XYdUXiNtMyioEvKXn7mH5TbyrW/r9ZHjrgvAKJv QA8PKElMMZxxi3dP2PH0uU5KaPQL6te10oKanSDtzeX/9kDhxvK8WkvI7p7rTDhhuW4RX1 t/VSPTgqb4Hnxlv6Bxjv/JCEY1q31xw= Received: from mail-wm1-f72.google.com (mail-wm1-f72.google.com [209.85.128.72]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_128_GCM_SHA256) id us-mta-632-evhGpABgNveK72D0JOUSPA-1; Sat, 28 Jan 2023 05:29:54 -0500 X-MC-Unique: evhGpABgNveK72D0JOUSPA-1 Received: by mail-wm1-f72.google.com with SMTP id o5-20020a05600c4fc500b003db0b3230efso6128669wmq.9 for ; Sat, 28 Jan 2023 02:29:54 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=6FB+edsbb44QCZ358g73Bl78hzSRCKhojxU7VjQ1JnU=; b=BMBTh4coGEtUIaiVmoUz4u9qxMAuEwiiQ3CleYZeQys5fPR7VxrdF4RSjOapZNRMKQ 8SLFsqM8AH95D0CN9lkxYnEjhZ6jFHQV5k1rn1zy8KEiy6GtoFNwTqtP5boJmzZVFY2r 6cZMt+1gFB5NOlcClm8/ClSlAtL3xEBv25pTJPR7UOh4dH7Olva5w0b8LddpdjjApzOj jovbJNrENO77bEe8+1YrHFMgLuyL1xQw3b2lf3j36pAngB7QERWKD7rNjy7me6KKdEHr jy0EO5KiYG1MdYSkU6MrtC6sKEOKIJrU6b4DzE1dkmqxpbdZBohx9xlYcHJIXQE3oS4G xmXg== X-Gm-Message-State: AFqh2kp60B/l5Lq5bM1crowyAQNVsgSJUHhHOg6FZGvuUy8vMwZ6hiP6 BYYr85TCR+i3TsAyeS9Wgm9OdcWWvQ/5Kv/pN6CxLoDglz6GHe+nRFapS7ErO89p705Pil5nTyK YvTJRNfH331LrvCQ= X-Received: by 2002:a05:600c:4f4a:b0:3db:5f1:53a5 with SMTP id m10-20020a05600c4f4a00b003db05f153a5mr44594788wmq.20.1674901793169; Sat, 28 Jan 2023 02:29:53 -0800 (PST) X-Google-Smtp-Source: AMrXdXuno6zz4nZQndocIplzwwOWQovv2WGK1jCz73RtkVbRaHT41YIqt6ePM429fHAtdaFDUUjG+g== X-Received: by 2002:a05:600c:4f4a:b0:3db:5f1:53a5 with SMTP id m10-20020a05600c4f4a00b003db05f153a5mr44594772wmq.20.1674901792934; Sat, 28 Jan 2023 02:29:52 -0800 (PST) Received: from redhat.com ([2.52.20.248]) by smtp.gmail.com with ESMTPSA id i20-20020a05600c071400b003db0ad636d1sm9927098wmn.28.2023.01.28.02.29.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 28 Jan 2023 02:29:52 -0800 (PST) Date: Sat, 28 Jan 2023 05:29:47 -0500 From: "Michael S. Tsirkin" To: Peter Maydell Cc: Warner Losh , Markus Armbruster , qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, philmd@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 04/19] bsd-user: Clean up includes Message-ID: <20230128052729-mutt-send-email-mst@kernel.org> References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-5-armbru@redhat.com> <20230127100052-mutt-send-email-mst@kernel.org> MIME-Version: 1.0 In-Reply-To: <20230127100052-mutt-send-email-mst@kernel.org> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 28 Jan 2023 10:29:58 -0000 On Fri, Jan 27, 2023 at 10:01:57AM -0500, Michael S. Tsirkin wrote: > On Fri, Jan 27, 2023 at 02:54:30PM +0000, Peter Maydell wrote: > > On Thu, 19 Jan 2023 at 14:42, Warner Losh wrote: > > > > > > Also, why didn't you move sys/resource.h and other such files > > > to os-dep.h? I'm struggling to understand the rules around what > > > is or isn't included where? > > > > The rough rule of thumb is that if some OS needs a compatibility > > fixup or workaround for a system header (eg not every mmap.h > > defines MAP_ANONYMOUS; on Windows unistd.h has to come before > > time.h) then we put that header include and the compat workaround > > into osdep.h. This avoids "only fails on obscure platform" issues > > where somebody puts a header include into some specific .c file > > but not the compat workaround, and it works on the Linux host > > that most people develop and test on and we only find the > > problem later. > > > > There's also no doubt some includes there for historical > > reasons, and some which really are "everybody needs these" > > convenience ones. But we should probably not add new > > includes to osdep.h unless they fall into the "working around > > system header issues" bucket. > > > > thanks > > -- PMM > > > BTW maybe we should teach checkpatch about that rule: > if a header is in osdep do not include it directly. To be more precise, make checkpatch run clean-includes somehow? Or just make CI run clean-includes on the tree and verify result is empty? > -- > MST From MAILER-DAEMON Sat Jan 28 21:21:14 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pLxJh-0004Wc-Um for mharc-qemu-riscv@gnu.org; Sat, 28 Jan 2023 21:21:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLxJf-0004W4-P3; Sat, 28 Jan 2023 21:21:11 -0500 Received: from mail-ed1-x52d.google.com ([2a00:1450:4864:20::52d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pLxJe-00038A-9h; Sat, 28 Jan 2023 21:21:11 -0500 Received: by mail-ed1-x52d.google.com with SMTP id n6so5331211edo.9; Sat, 28 Jan 2023 18:21:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=qwLDTk9CmgoO7XlG9QyaEWRrleW3MOLcZ5s2N37WJPc=; b=St+XqyCOoWmjCrzyI1xbLUaYhVjGgFJz6B8b2rlsnlbvAFtn5IpDYvsupKr2qvbNXw QfzCjMX6Iw2VXr9uusIrpkrALBda/pjYQtxYEE07hhNH1eH/aTaRXHza4hiYc/Lqhqll RDrUS03vEC4tPHA/qThySDBWUq5vONpq6VUugvwXDd04iMfaRbfL5wQvENCIc2OGiQsI Nl4IXg+grkUUuaUy1d+mk8Oso9ivHlaczW49jw5nMejoeBzK9SXesMo6YTj0PmgbtbAP EPFH80gCHWIByYc/q9GRLL5jn6eGUPBhKbgYEwe9cOHzVJjQTj0wofyvhuLqCgfyX/3b faHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=qwLDTk9CmgoO7XlG9QyaEWRrleW3MOLcZ5s2N37WJPc=; b=0k5kbdlp13fTr4riyl7c6hoI9IiBzpkVJOPSXjkNSivPjin8w/HZSL3vdBboqwQ7wG ElhiDEtceW/N+NUltAiJuF11SQo8Ee7e7tgKGKOkM6DpHbT8ODPpbt5lou54mJDk74oI xR5OnwLDMt/uWLv641z8rca3xr/PrDF/Cb2/Dl5YB4Mwq1C39DG+1ABte58wqg/D12l6 ifuwbe58g3ZAJjj8orMATja+fjY380hcRzNLta2t1IhQJQFf3Tu0wIyFmvdXu1f/x2YT kLJaspj/d12yQyheT2yvYqRXH6H6NaXYVfDa7j/A5xpwbzT0jdOjWOhLYiIqaKzOygSi yK6A== X-Gm-Message-State: AO0yUKWhKlDtIh5dkAVMd6EZt1wJMyyMX4IxURLSszhYnQbBF2uCKsV+ CTYJC/FU7t8XphSCzFlRzfjOdQuPqFed+hIyCfI= X-Google-Smtp-Source: AK7set9o7VEQmtIOUBKFHvBQLqmHFwbed+QD+86s/khPeSGRl23rBzkV8C8NeNy/0+miw4AVmswZu/rTTLtAGEWBEvw= X-Received: by 2002:aa7:ca48:0:b0:4a2:3637:568 with SMTP id j8-20020aa7ca48000000b004a236370568mr186240edt.83.1674958867404; Sat, 28 Jan 2023 18:21:07 -0800 (PST) MIME-Version: 1.0 References: <20230126135219.1054658-1-dbarboza@ventanamicro.com> <20230126135219.1054658-2-dbarboza@ventanamicro.com> In-Reply-To: <20230126135219.1054658-2-dbarboza@ventanamicro.com> From: Bin Meng Date: Sun, 29 Jan 2023 10:20:56 +0800 Message-ID: Subject: Re: [PATCH v4 1/3] hw/riscv/boot.c: calculate fdt size after fdt_pack() To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=bmeng.cn@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 29 Jan 2023 02:21:12 -0000 Hi Daniel, On Thu, Jan 26, 2023 at 9:53 PM Daniel Henrique Barboza wrote: > > fdt_pack() can change the fdt size, meaning that fdt_totalsize() can > contain a now deprecated (bigger) value. The commit message is a bit confusing. The original code in this patch does not call fdt_pack(). So not sure where the issue of "deprecated (bigger) value" happens? > > Reviewed-by: Alistair Francis > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/boot.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 3172a76220..a563b7482a 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -287,8 +287,13 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) > { > uint64_t temp, fdt_addr; > hwaddr dram_end = dram_base + mem_size; > - int ret, fdtsize = fdt_totalsize(fdt); > + int ret = fdt_pack(fdt); > + int fdtsize; > > + /* Should only fail if we've built a corrupted tree */ > + g_assert(ret == 0); > + > + fdtsize = fdt_totalsize(fdt); > if (fdtsize <= 0) { > error_report("invalid device-tree"); > exit(1); Regards, Bin From MAILER-DAEMON Sat Jan 28 22:06:25 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pLy1R-0004Gy-Hf for mharc-qemu-riscv@gnu.org; Sat, 28 Jan 2023 22:06:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pLy1Q-0004Gb-1z; Sat, 28 Jan 2023 22:06:24 -0500 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pLy1O-0000sV-GD; Sat, 28 Jan 2023 22:06:23 -0500 Received: by mail-ej1-x636.google.com with SMTP id ud5so23284582ejc.4; Sat, 28 Jan 2023 19:06:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=vIYkdqunurwh8P2gFKYHKvjT4itwtXwM5y2oVwh82PU=; b=ZqTedarW6/Am/0vYwCMO8kyXyRRNx7VVuVC/0cnPLtbKbCVGcc423f5UwGZmyDgIg+ Heiq2qqZb4NOavP63LK/EOs9cih7M6E9Tjf6+qZLaoPHqNjHBFiJ0HJaDd7HxgjxgKed T/S/lYVXzbypEDFl/SyqoUekLRPSBYroHrBvpC0dkaPKXr9PC3bUSvBNDebRYoLPrzmB LZR+E2N5Dog2lQYSzzSOiEGT3J+2i8ozn9goznyKg2z0h0CG6+S56OoM7CNRo+RKYZd1 tHN2suOk+zwGQd5cWQXY4t1sd9qEC0aeVU3eSVp1Zh6ULx9mdeJ8HmN/+tM9rfTB40Df GU4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=vIYkdqunurwh8P2gFKYHKvjT4itwtXwM5y2oVwh82PU=; b=FQUceqDJ8dWNXzQOfuabxURfxtd6GbxZJmBruTMgf10nEhNdqbnKRc4SmJ5NCtkuZh bQIJZtEGwfG7L/nTgx5tDiGz4Hx8ZejMykVoDHGKuTsgio+fNMt4FOMaiJ6iXJ2vpQZG u6leslccpVcOEoY3NRWzQfxrBvmQpd1TX8iokiPnOoUN1CZtvJwZ+fTkfM+8pI/jnCum fru0SZrQxS3ZwOLqRUwTnSoft/HUrqD4lAztI77QuS5/NBmPPgKoV5CCBxUAuZ0u0lFK 5OLZafyLI3YaFUzY3P7IUCvEMtlTobEnzXBbOhKPQ5Pr6nRXnjHcPQCDSZrOG1vD1xao hnuQ== X-Gm-Message-State: AFqh2kpMokvVOYpzvHyVGKffz6BCg5PSXCx4XILIESffEH4HPORkMi8x KXUYOUEqhUxYSMA0OyyYp6ZdAv2I5mBjggkqNkg= X-Google-Smtp-Source: AMrXdXuf6EvYoNPeTHX0eqOQN79Y4OJnA5lK3IIX1GqJzwC5RQNpbZ9x40fXEvUY3ra2Oe1oRDKgJWSMShZyqz4hzQI= X-Received: by 2002:a17:907:a2c4:b0:877:5ff6:e340 with SMTP id re4-20020a170907a2c400b008775ff6e340mr6647540ejc.163.1674961580392; Sat, 28 Jan 2023 19:06:20 -0800 (PST) MIME-Version: 1.0 References: <20230126135219.1054658-1-dbarboza@ventanamicro.com> <20230126135219.1054658-2-dbarboza@ventanamicro.com> In-Reply-To: From: Bin Meng Date: Sun, 29 Jan 2023 11:06:09 +0800 Message-ID: Subject: Re: [PATCH v4 1/3] hw/riscv/boot.c: calculate fdt size after fdt_pack() To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 29 Jan 2023 03:06:24 -0000 On Sun, Jan 29, 2023 at 10:20 AM Bin Meng wrote: > > Hi Daniel, > > On Thu, Jan 26, 2023 at 9:53 PM Daniel Henrique Barboza > wrote: > > > > fdt_pack() can change the fdt size, meaning that fdt_totalsize() can > > contain a now deprecated (bigger) value. > > The commit message is a bit confusing. > > The original code in this patch does not call fdt_pack(). So not sure > where the issue of "deprecated (bigger) value" happens? I see where the call to fdt_pack() happens. I think you should move the following changes in patch#2 of this series to this commit. - ret = fdt_pack(fdt); - /* Should only fail if we've built a corrupted tree */ - g_assert(ret == 0); After that, your commit message makes sense, as it describes the problem and how your patch fixes the problem. > > > > > Reviewed-by: Alistair Francis > > Signed-off-by: Daniel Henrique Barboza > > --- > > hw/riscv/boot.c | 7 ++++++- > > 1 file changed, 6 insertions(+), 1 deletion(-) > > > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > > index 3172a76220..a563b7482a 100644 > > --- a/hw/riscv/boot.c > > +++ b/hw/riscv/boot.c > > @@ -287,8 +287,13 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) > > { > > uint64_t temp, fdt_addr; > > hwaddr dram_end = dram_base + mem_size; > > - int ret, fdtsize = fdt_totalsize(fdt); > > + int ret = fdt_pack(fdt); > > + int fdtsize; > > > > + /* Should only fail if we've built a corrupted tree */ > > + g_assert(ret == 0); > > + > > + fdtsize = fdt_totalsize(fdt); > > if (fdtsize <= 0) { > > error_report("invalid device-tree"); > > exit(1); > Regards, Bin From MAILER-DAEMON Sun Jan 29 00:17:12 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pM040-0007qd-Li for mharc-qemu-riscv@gnu.org; Sun, 29 Jan 2023 00:17:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pM03z-0007qN-1B; Sun, 29 Jan 2023 00:17:11 -0500 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pM03w-0004Xl-UL; Sun, 29 Jan 2023 00:17:10 -0500 Received: by mail-ej1-x630.google.com with SMTP id dr8so1983701ejc.12; Sat, 28 Jan 2023 21:17:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=8j5+nWSOs8eGB4svczUf3aHIju/fmNote9HAx8Vm6yw=; b=FGdys+Upufy6OUukkDQX+uLfkawuIUq/CS1hl/hxA8HQkoIC5Xbc9vjkwwLOtWOv3v 8prsZGsrHaXirbo97j6j+yFYqD/uKpN46gf5AprpJT852gfsP5HLCDxzTtrqchBpq3KJ Dx5NEgEwtbQOoTpjHFDykmzpgKi+5fq26SqO8Y13RlTJ4gSk5YOphZGdkgVAPztWpBX2 NQHUeV0acC02yQoEwJ28Haz6iJ+ODYa0cocgzIVoJT4I7UMPGCqDH4fMnw0a3e5vHUl8 i9p+P4CRB8ef+W/6Ln6n9jZIn7+QFBv7TZzz0L2Xe6/U5vg0oNJblJ2QeT5JqZ/9mp7D +oaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=8j5+nWSOs8eGB4svczUf3aHIju/fmNote9HAx8Vm6yw=; b=xeGz9WJeL3G/HA/1+KKNr5vwPwmbyezL272btE4qDdfJF9i+TZzgBKOCP2xDoiWIqu InCsmvOdXUTrE+hPay+KDYZfJZt3Z8inARrEPHij1wRTdGvO+Upco67m86+UJGhZ/21Q /jpRxKBSJp5AeSJmbaKqBrTnpjSk8QoQjywXzZ+6hsQPgCr2KUPGzgvjkS/BkJSLLaY/ 4o92o5l36xnkfCMb4Wd423OvQ9rDCGogTvrVqeGT4v/9tLcy3fHX77nHCuTq5e4J89Lw rTU9SbltMvLNixce6ELU4QHBYl60dMYN+zryhfzxBfB5893tHZshZwwNYbtElGaUrnCX Qq6Q== X-Gm-Message-State: AFqh2kr3N4hDRioiCYPLq7al6IkW0cfjD6uTPNDrRRQLe0fkIQqKIF2q 9J0Rg0a4Kv11+iBhX0qO7Brm1zMrPf05+asMUvg= X-Google-Smtp-Source: AMrXdXtz2G9d9gD7xcMHlygoWPWA7w6AiSSE6ol13ESDjGB/jGfZou2/eRvWhkzm7/EDFbUQE8hrG5/AqaL/OOIb8/Y= X-Received: by 2002:a17:906:a00b:b0:7c0:beef:79e2 with SMTP id p11-20020a170906a00b00b007c0beef79e2mr7931890ejy.148.1674969426805; Sat, 28 Jan 2023 21:17:06 -0800 (PST) MIME-Version: 1.0 References: <20230126135219.1054658-1-dbarboza@ventanamicro.com> <20230126135219.1054658-3-dbarboza@ventanamicro.com> In-Reply-To: <20230126135219.1054658-3-dbarboza@ventanamicro.com> From: Bin Meng Date: Sun, 29 Jan 2023 13:16:55 +0800 Message-ID: Subject: Re: [PATCH v4 2/3] hw/riscv: split fdt address calculation from fdt load To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 29 Jan 2023 05:17:11 -0000 On Thu, Jan 26, 2023 at 9:53 PM Daniel Henrique Barboza wrote: > > A common trend in other archs is to calculate the fdt address, which is > usually straightforward, and then calling a function that loads the > fdt/dtb by using that address. > > riscv_load_fdt() is doing a bit too much in comparison. It's calculating > the fdt address via an elaborated heuristic to put the FDT at the bottom > of DRAM, and "bottom of DRAM" will vary across boards and > configurations, then it's actually loading the fdt, and finally it's > returning the fdt address used to the caller. > > Reduce the existing complexity of riscv_load_fdt() by splitting its code > into a new function, riscv_compute_fdt_addr(), that will take care of > all fdt address logic. riscv_load_fdt() can then be a simple function > that just loads a fdt at the given fdt address. > > We're also taken the opportunity to clarify the intentions and > assumptions made by these functions. riscv_load_fdt() is now receiving a > hwaddr as fdt_addr because there is no restriction of having to load the > fdt in higher addresses that doesn't fit in an uint32_t. > > Reviewed-by: Alistair Francis > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/boot.c | 33 +++++++++++++++++++++++++-------- > hw/riscv/microchip_pfsoc.c | 6 ++++-- > hw/riscv/sifive_u.c | 7 ++++--- > hw/riscv/spike.c | 6 +++--- > hw/riscv/virt.c | 7 ++++--- > include/hw/riscv/boot.h | 4 +++- > 6 files changed, 43 insertions(+), 20 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index a563b7482a..a6f7b8ae8e 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -283,9 +283,21 @@ out: > return kernel_entry; > } > > -uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) > +/* > + * The FDT should be put at the farthest point possible to > + * avoid overwriting it with the kernel/initrd. > + * > + * This function makes an assumption that the DRAM is > + * contiguous. It also cares about 32-bit systems and > + * will limit fdt_addr to be addressable by them even for > + * 64-bit CPUs. > + * > + * The FDT is fdt_packed() during the calculation. > + */ > +uint32_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size, > + void *fdt) The original code returns a uint64_t for fdt_addr but now this is uint32_t? > { > - uint64_t temp, fdt_addr; > + uint64_t temp; > hwaddr dram_end = dram_base + mem_size; > int ret = fdt_pack(fdt); > int fdtsize; > @@ -306,11 +318,18 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) > * end of dram or 3GB whichever is lesser. > */ > temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; > - fdt_addr = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); > > - ret = fdt_pack(fdt); > - /* Should only fail if we've built a corrupted tree */ > - g_assert(ret == 0); > + return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); > +} > + > +/* > + * 'fdt_addr' is received as hwaddr because boards might put > + * the FDT beyond 32-bit addressing boundary. > + */ > +void riscv_load_fdt(hwaddr fdt_addr, void *fdt) > +{ > + uint32_t fdtsize = fdt_totalsize(fdt); > + > /* copy in the device tree */ > qemu_fdt_dumpdtb(fdt, fdtsize); > > @@ -318,8 +337,6 @@ uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) > &address_space_memory); > qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, > rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize)); > - > - return fdt_addr; > } > > void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index b7e171b605..a30203db85 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -633,8 +633,10 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) > kernel_start_addr, true, NULL); > > /* Compute the fdt load address in dram */ > - fdt_load_addr = riscv_load_fdt(memmap[MICROCHIP_PFSOC_DRAM_LO].base, > - machine->ram_size, machine->fdt); > + fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base, > + machine->ram_size, machine->fdt); > + riscv_load_fdt(fdt_load_addr, machine->fdt); > + > /* Load the reset vector */ > riscv_setup_rom_reset_vec(machine, &s->soc.u_cpus, firmware_load_addr, > memmap[MICROCHIP_PFSOC_ENVM_DATA].base, > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index b0b3e6f03a..6bbdbe5fb7 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -608,9 +608,10 @@ static void sifive_u_machine_init(MachineState *machine) > kernel_entry = 0; > } > > - /* Compute the fdt load address in dram */ > - fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base, > - machine->ram_size, machine->fdt); > + fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, > + machine->ram_size, machine->fdt); > + riscv_load_fdt(fdt_load_addr, machine->fdt); > + > if (!riscv_is_32bit(&s->soc.u_cpus)) { > start_addr_hi32 = (uint64_t)start_addr >> 32; > } > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index 483581e05f..ceebe34c5f 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -316,9 +316,9 @@ static void spike_board_init(MachineState *machine) > kernel_entry = 0; > } > > - /* Compute the fdt load address in dram */ > - fdt_load_addr = riscv_load_fdt(memmap[SPIKE_DRAM].base, > - machine->ram_size, machine->fdt); > + fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, > + machine->ram_size, machine->fdt); > + riscv_load_fdt(fdt_load_addr, machine->fdt); > > /* load the reset vector */ > riscv_setup_rom_reset_vec(machine, &s->soc[0], memmap[SPIKE_DRAM].base, > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 48326406fd..43fca597f0 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -1292,9 +1292,10 @@ static void virt_machine_done(Notifier *notifier, void *data) > start_addr = virt_memmap[VIRT_FLASH].base; > } > > - /* Compute the fdt load address in dram */ > - fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base, > - machine->ram_size, machine->fdt); > + fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, > + machine->ram_size, machine->fdt); > + riscv_load_fdt(fdt_load_addr, machine->fdt); > + > /* load the reset vector */ > riscv_setup_rom_reset_vec(machine, &s->soc[0], start_addr, > virt_memmap[VIRT_MROM].base, > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h > index bc9faed397..7babd669c7 100644 > --- a/include/hw/riscv/boot.h > +++ b/include/hw/riscv/boot.h > @@ -48,7 +48,9 @@ target_ulong riscv_load_kernel(MachineState *machine, > target_ulong firmware_end_addr, > bool load_initrd, > symbol_fn_t sym_cb); > -uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); > +uint32_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, > + void *fdt); > +void riscv_load_fdt(hwaddr fdt_addr, void *fdt); > void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, > hwaddr saddr, > hwaddr rom_base, hwaddr rom_size, > -- Regards, Bin From MAILER-DAEMON Sun Jan 29 00:46:09 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pM0W1-0006xx-Me for mharc-qemu-riscv@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 29 Jan 2023 05:46:08 -0000 On Thu, Jan 26, 2023 at 9:54 PM Daniel Henrique Barboza wrote: > > As it is now, riscv_compute_fdt_addr() is receiving a dram_base, a > mem_size (which is defaulted to MachineState::ram_size in all boards) > and the FDT pointer. And it makes a very important assumption: the DRAM > interval dram_base + mem_size is contiguous. This is indeed the case for > most boards that uses a FDT. s/uses/use > > The Icicle Kit board works with 2 distinct RAM banks that are separated > by a gap. We have a lower bank with 1GiB size, a gap follows, then at > 64GiB the high memory starts. MachineClass::default_ram_size for this > board is set to 1.5Gb, and machine_init() is enforcing it as minimal RAM > size, meaning that there we'll always have at least 512 MiB in the Hi > RAM area. > > Using riscv_compute_fdt_addr() in this board is weird because not only > the board has sparse RAM, and it's calling it using the base address of > the Lo RAM area, but it's also using a mem_size that we have guarantees > that it will go up to the Hi RAM. All the function assumptions doesn't > work for this board. > > In fact, what makes the function works at all in this case is a > coincidence. Commit 1a475d39ef54 introduced a 3GB boundary for the FDT, > down from 4Gb, that is enforced if dram_base is lower than 3072 MiB. For > the Icicle Kit board, memmap[MICROCHIP_PFSOC_DRAM_LO].base is 0x80000000 > (2 Gb) and it has a 1Gb size, so it will fall in the conditions to put > the FDT under a 3Gb address, which happens to be exactly at the end of > DRAM_LO. If the base address of the Lo area started later than 3Gb this > function would be unusable by the board. Changing any assumptions inside > riscv_compute_fdt_addr() can also break it by accident as well. > > Let's change riscv_compute_fdt_addr() semantics to be appropriate to the > Icicle Kit board and for future boards that might have sparse RAM > topologies to worry about: > > - relieve the condition that the dram_base + mem_size area is contiguous, > since this is already not the case today; > > - receive an extra 'dram_size' size attribute that refers to a contiguous > RAM block that the board wants the FDT to reside on. > > Together with 'mem_size' and 'fdt', which are now now being consumed by a > MachineState pointer, we're able to make clear assumptions based on the > DRAM block and total mem_size available to ensure that the FDT will be put > in a valid RAM address. > Well written commit message. Thanks! > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/boot.c | 38 ++++++++++++++++++++++++++------------ > hw/riscv/microchip_pfsoc.c | 3 ++- > hw/riscv/sifive_u.c | 3 ++- > hw/riscv/spike.c | 3 ++- > hw/riscv/virt.c | 3 ++- > include/hw/riscv/boot.h | 4 ++-- > 6 files changed, 36 insertions(+), 18 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index a6f7b8ae8e..8f4991480b 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -284,33 +284,47 @@ out: > } > > /* > - * The FDT should be put at the farthest point possible to > - * avoid overwriting it with the kernel/initrd. > + * This function makes an assumption that the DRAM interval > + * 'dram_base' + 'dram_size' is contiguous. > * > - * This function makes an assumption that the DRAM is > - * contiguous. It also cares about 32-bit systems and > - * will limit fdt_addr to be addressable by them even for > - * 64-bit CPUs. > + * Considering that 'dram_end' is the lowest value between > + * the end of the DRAM block and MachineState->ram_size, the > + * FDT location will vary according to 'dram_base': > + * > + * - if 'dram_base' is less that 3072 MiB, the FDT will be > + * put at the lowest value between 3072 MiB and 'dram_end'; > + * > + * - if 'dram_base' is higher than 3072 MiB, the FDT will be > + * put at 'dram_end'. > * > * The FDT is fdt_packed() during the calculation. > */ > -uint32_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size, > - void *fdt) > +hwaddr riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, Using hwaddr to represent a size looks weird. Although technically they are the same ... I would leave this as it is. > + MachineState *ms) > { > - uint64_t temp; > - hwaddr dram_end = dram_base + mem_size; > - int ret = fdt_pack(fdt); > + int ret = fdt_pack(ms->fdt); > + hwaddr dram_end, temp; > int fdtsize; > > /* Should only fail if we've built a corrupted tree */ > g_assert(ret == 0); > > - fdtsize = fdt_totalsize(fdt); > + fdtsize = fdt_totalsize(ms->fdt); > if (fdtsize <= 0) { > error_report("invalid device-tree"); > exit(1); > } > > + /* > + * A dram_size == 0, usually from a MemMapEntry[].size element, > + * means that the DRAM block goes all the way to ms->ram_size. > + */ > + if (dram_size == 0x0) { > + dram_end = dram_base + ms->ram_size; > + } else { > + dram_end = dram_base + MIN(ms->ram_size, dram_size); > + } How about: g_assert(dram_size < ms->ram_size); dram_end = dram_base + (dram_size ? dram_size : ms->ram_size); > + > /* > * We should put fdt as far as possible to avoid kernel/initrd overwriting > * its content. But it should be addressable by 32 bit system as well. > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index a30203db85..e81bbd12df 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -634,7 +634,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) > > /* Compute the fdt load address in dram */ > fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base, > - machine->ram_size, machine->fdt); > + memmap[MICROCHIP_PFSOC_DRAM_LO].size, > + machine); > riscv_load_fdt(fdt_load_addr, machine->fdt); > > /* Load the reset vector */ > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 6bbdbe5fb7..ad3bb35b34 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -609,7 +609,8 @@ static void sifive_u_machine_init(MachineState *machine) > } > > fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, > - machine->ram_size, machine->fdt); > + memmap[SIFIVE_U_DEV_DRAM].size, > + machine); > riscv_load_fdt(fdt_load_addr, machine->fdt); > > if (!riscv_is_32bit(&s->soc.u_cpus)) { > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index ceebe34c5f..b5979eddd6 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -317,7 +317,8 @@ static void spike_board_init(MachineState *machine) > } > > fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, > - machine->ram_size, machine->fdt); > + memmap[SPIKE_DRAM].size, > + machine); > riscv_load_fdt(fdt_load_addr, machine->fdt); > > /* load the reset vector */ > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 43fca597f0..f079a30b60 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -1293,7 +1293,8 @@ static void virt_machine_done(Notifier *notifier, void *data) > } > > fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, > - machine->ram_size, machine->fdt); > + memmap[VIRT_DRAM].size, > + machine); > riscv_load_fdt(fdt_load_addr, machine->fdt); > > /* load the reset vector */ > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h > index 7babd669c7..a6099c2dc6 100644 > --- a/include/hw/riscv/boot.h > +++ b/include/hw/riscv/boot.h > @@ -48,8 +48,8 @@ target_ulong riscv_load_kernel(MachineState *machine, > target_ulong firmware_end_addr, > bool load_initrd, > symbol_fn_t sym_cb); > -uint32_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, > - void *fdt); > +hwaddr riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, > + MachineState *ms); > void riscv_load_fdt(hwaddr fdt_addr, void *fdt); > void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, > hwaddr saddr, > -- Regards, Bin From MAILER-DAEMON Sun Jan 29 00:54:27 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pM0e3-0000Qk-GP for mharc-qemu-riscv@gnu.org; Sun, 29 Jan 2023 00:54:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps 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3-20020a170906328300b008823e56a854mr920560ejw.263.1674971661224; Sat, 28 Jan 2023 21:54:21 -0800 (PST) MIME-Version: 1.0 References: <20230125162010.1615787-1-alexghiti@rivosinc.com> <20230125162010.1615787-2-alexghiti@rivosinc.com> In-Reply-To: <20230125162010.1615787-2-alexghiti@rivosinc.com> From: Bin Meng Date: Sun, 29 Jan 2023 13:54:10 +0800 Message-ID: Subject: Re: [PATCH v8 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, 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AMrXdXunkINYMgPaQTTbCmE4g2aSlO92W54QGMMHS+9K/EArN8NV3eYXo05L/9PsocMbaJMfhT0P79eKMQCkNWdiuJs= X-Received: by 2002:a17:906:a00b:b0:7c0:beef:79e2 with SMTP id p11-20020a170906a00b00b007c0beef79e2mr7945464ejy.148.1674971764326; Sat, 28 Jan 2023 21:56:04 -0800 (PST) MIME-Version: 1.0 References: <20230125162010.1615787-1-alexghiti@rivosinc.com> <20230125162010.1615787-3-alexghiti@rivosinc.com> In-Reply-To: <20230125162010.1615787-3-alexghiti@rivosinc.com> From: Bin Meng Date: Sun, 29 Jan 2023 13:55:53 +0800 Message-ID: Subject: Re: [PATCH v8 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) 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29 Jan 2023 14:12:36 -0800 (PST) MIME-Version: 1.0 References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> <380600FF-17AC-4134-85C7-CBDF6E34F0E2@getmailspring.com> In-Reply-To: From: Philipp Tomsich Date: Sun, 29 Jan 2023 23:12:25 +0100 Message-ID: Subject: Re: Fwd: [RFC PATCH 00/39] Add RISC-V cryptography extensions standardisation To: Alistair Francis Cc: "qemu-riscv@nongnu.org" , "lawrence.hunter@codethink.co.uk" , "palmer@dabbelt.com" , "bin.meng@windriver.com" , "pbonzini@redhat.com" , "dickon.hood@codethink.co.uk" , "frank.chang@sifive.com" , "kvm@vger.kernel.org" Content-Type: multipart/alternative; boundary="0000000000006abee005f36e6580" Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=philipp.tomsich@vrull.eu; helo=mail-ej1-x62c.google.com X-Spam_score_int: -15 X-Spam_score: -1.6 X-Spam_bar: - X-Spam_report: (-1.6 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 29 Jan 2023 22:13:03 -0000 --0000000000006abee005f36e6580 Content-Type: text/plain; charset="UTF-8" On Sun, 29 Jan 2023 at 23:08, Alistair Francis wrote: > On Thu, 2023-01-26 at 09:21 +0000, Lawrence Hunter wrote: > > Follow up for add RISC-V vector cryptography extensions > > standardisation > > RFC: we've not received any comments and would like to move this > > series > > towards getting merged. Does anyone have time to review it, and > > should > > we look at resubmitting for merging soon? > > Hello, > > This series never made it to the QEMU list. It looks like it was never > sent to the general qemu-devel mailing list. > This has so far been more than a little painful for our review, as we can't just pull the patches down from patchwork to use our regular test-and-review flow. Should we wait until the resubmission for our review? Note that the current series is not in-sync with the latest specification. We'll try to point out the specific deviations (we have a tree that we've been keeping in sync with the changes to the spec since mid-December) in our reviews. Cheers, Philipp. > When submitting patches can you please follow the steps here: > > https://www.qemu.org/docs/master/devel/submitting-a-patch.html#submitting-your-patches > > It's important that all patches are sent to the qemu-devel mailing list > (that's actually much more important then the RISC-V mailing list). > > Alistair > > > > > ---------- Forwarded Message --------- > > > > From: Lawrence Hunter > > Subject: [RFC PATCH 00/39] Add RISC-V cryptography extensions > > standardisation > > Date: Jan 19 2023, at 2:34 pm > > To: qemu-riscv@nongnu.org > > Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence > > Hunter > > > > > > > This RFC introduces an implementation for the six instruction sets > > > of the draft RISC-V cryptography extensions standardisation > > > specification. Once the specification has been ratified we will > > > submit > > > these changes as a pull request email to this mailing list. Would > > > this > > > be prefered by instruction group or unified as in this RFC? > > > > > > This patch set implements the instruction sets as per the 20221202 > > > version of the specification (1). > > > > > > Work performed by Dickon, Lawrence, Nazar, Kiran, and William from > > > Codethink > > > sponsored by SiFive, and Max Chou from SiFive. > > > > > > 1. https://github.com/riscv/riscv-crypto/releases > > > > > > Dickon Hood (1): > > > target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] decoding, > > > translation and execution support > > > > > > Kiran Ostrolenk (4): > > > target/riscv: Add vsha2ms.vv decoding, translation and execution > > > support > > > target/riscv: add zvksh cpu property > > > target/riscv: Add vsm3c.vi decoding, translation and execution > > > support > > > target/riscv: expose zvksh cpu property > > > > > > Lawrence Hunter (16): > > > target/riscv: Add vclmul.vv decoding, translation and execution > > > support > > > target/riscv: Add vclmul.vx decoding, translation and execution > > > support > > > target/riscv: Add vclmulh.vv decoding, translation and execution > > > support > > > target/riscv: Add vclmulh.vx decoding, translation and execution > > > support > > > target/riscv: Add vaesef.vv decoding, translation and execution > > > support > > > target/riscv: Add vaesef.vs decoding, translation and execution > > > support > > > target/riscv: Add vaesdf.vv decoding, translation and execution > > > support > > > target/riscv: Add vaesdf.vs decoding, translation and execution > > > support > > > target/riscv: Add vaesdm.vv decoding, translation and execution > > > support > > > target/riscv: Add vaesdm.vs decoding, translation and execution > > > support > > > target/riscv: Add vaesz.vs decoding, translation and execution > > > support > > > target/riscv: Add vsha2c[hl].vv decoding, translation and > > > execution > > > support > > > target/riscv: Add vsm3me.vv decoding, translation and execution > > > support > > > target/riscv: add zvkg cpu property > > > target/riscv: Add vghmac.vv decoding, translation and execution > > > support > > > target/riscv: expose zvkg cpu property > > > > > > Max Chou (5): > > > crypto: Move SM4_SBOXWORD from target/riscv > > > crypto: Add SM4 constant parameter CK. > > > target/riscv: Add zvksed cfg property > > > target/riscv: Add Zvksed support > > > target/riscv: Expose Zvksed property > > > > > > Nazar Kazakov (10): > > > target/riscv: add zvkb cpu property > > > target/riscv: Add vrev8.v decoding, translation and execution > > > support > > > target/riscv: Add vandn.[vv,vx,vi] decoding, translation and > > > execution > > > support > > > target/riscv: expose zvkb cpu property > > > target/riscv: add zvkns cpu property > > > target/riscv: Add vaeskf1.vi decoding, translation and execution > > > support > > > target/riscv: Add vaeskf2.vi decoding, translation and execution > > > support > > > target/riscv: expose zvkns cpu property > > > target/riscv: add zvknh cpu properties > > > target/riscv: expose zvknh cpu properties > > > > > > William Salmon (3): > > > target/riscv: Add vbrev8.v decoding, translation and execution > > > support > > > target/riscv: Add vaesem.vv decoding, translation and execution > > > support > > > target/riscv: Add vaesem.vs decoding, translation and execution > > > support > > > > > > crypto/sm4.c | 10 + > > > include/crypto/sm4.h | 8 + > > > include/qemu/bitops.h | 32 + > > > target/arm/crypto_helper.c | 10 +- > > > target/riscv/cpu.c | 15 + > > > target/riscv/cpu.h | 7 + > > > target/riscv/crypto_helper.c | 1 + > > > target/riscv/helper.h | 69 ++ > > > target/riscv/insn32.decode | 48 + > > > target/riscv/insn_trans/trans_rvzvkb.c.inc | 164 +++ > > > target/riscv/insn_trans/trans_rvzvkg.c.inc | 8 + > > > target/riscv/insn_trans/trans_rvzvknh.c.inc | 47 + > > > target/riscv/insn_trans/trans_rvzvkns.c.inc | 121 +++ > > > target/riscv/insn_trans/trans_rvzvksed.c.inc | 38 + > > > target/riscv/insn_trans/trans_rvzvksh.c.inc | 20 + > > > target/riscv/meson.build | 4 +- > > > target/riscv/translate.c | 6 + > > > target/riscv/vcrypto_helper.c | 1013 > > > ++++++++++++++++++ > > > target/riscv/vector_helper.c | 242 +---- > > > target/riscv/vector_internals.c | 63 ++ > > > target/riscv/vector_internals.h | 226 ++++ > > > 21 files changed, 1902 insertions(+), 250 deletions(-) > > > create mode 100644 target/riscv/insn_trans/trans_rvzvkb.c.inc > > > create mode 100644 target/riscv/insn_trans/trans_rvzvkg.c.inc > > > create mode 100644 target/riscv/insn_trans/trans_rvzvknh.c.inc > > > create mode 100644 target/riscv/insn_trans/trans_rvzvkns.c.inc > > > create mode 100644 target/riscv/insn_trans/trans_rvzvksed.c.inc > > > create mode 100644 target/riscv/insn_trans/trans_rvzvksh.c.inc > > > create mode 100644 target/riscv/vcrypto_helper.c > > > create mode 100644 target/riscv/vector_internals.c > > > create mode 100644 target/riscv/vector_internals.h > > > > > > -- > > > 2.39.1 > > > > > > > > > > > --0000000000006abee005f36e6580 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Sun, 29 Jan 2023 at 23:08, Alistai= r Francis <Alistair.Francis@= wdc.com> wrote:
On Thu, 2023-01-26 at 09:21 +0000, Lawrence Hunter wrote:
> Follow up for add RISC-V vector cryptography extensions
> standardisation
> RFC: we've not received any comments and would like to move this > series
> towards getting merged. Does anyone have time to review it, and
> should
> we look at resubmitting for merging soon?

Hello,

This series never made it to the QEMU list. It looks like it was never
sent to the general qemu-devel mailing list.

This has so far been more than a little painful for our review, as we= can't just pull the patches down from patchwork to use our regular tes= t-and-review flow.
Should we wait until the resubmission for our = review?

Note that the current series is not in-syn= c with the latest specification.
We'll try to point out the s= pecific deviations (we have a tree that we've been keeping in sync with= the changes to the spec since mid-December) in our reviews.

=
Cheers,
Philipp.
=C2=A0
When submitting patches can you please follow the steps here:
https://www.qe= mu.org/docs/master/devel/submitting-a-patch.html#submitting-your-patches

It's important that all patches are sent to the qemu-devel mailing list=
(that's actually much more important then the RISC-V mailing list).

Alistair

>
> ---------- Forwarded Message ---------
>
> From: Lawrence Hunter <
lawrence.hunter@codethink.co.uk>
> Subject: [RFC PATCH 00/39] Add RISC-V cryptography extensions
> standardisation
> Date: Jan 19 2023, at 2:34 pm
> To: qemu-ri= scv@nongnu.org
> Cc: d= ickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence
> Hunter <lawrence.hunter@codethink.co.uk>
>
>
> > This RFC introduces an implementation for the six instruction set= s
> > of the draft RISC-V cryptography extensions standardisation
> > specification. Once the specification has been ratified we will > > submit
> > these changes as a pull request email to this mailing list. Would=
> > this
> > be prefered by instruction group or unified as in this RFC?
> >
> > This patch set implements the instruction sets as per the 2022120= 2
> > version of the specification (1).
> >
> > Work performed by Dickon, Lawrence, Nazar, Kiran, and William fro= m
> > Codethink
> > sponsored by SiFive, and Max Chou from SiFive.
> >
> > 1. https://github.com/riscv/riscv-crypto/rel= eases
> >
> > Dickon Hood (1):
> > =C2=A0target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] decoding= ,
> > =C2=A0=C2=A0 translation and execution support
> >
> > Kiran Ostrolenk (4):
> > =C2=A0target/riscv: Add vsha2ms.vv decoding, translation and exec= ution
> > =C2=A0=C2=A0 support
> > =C2=A0target/riscv: add zvksh cpu property
> > =C2=A0target/riscv: Add vsm3c.vi decoding, translation and execution > > support
> > =C2=A0target/riscv: expose zvksh cpu property
> >
> > Lawrence Hunter (16):
> > =C2=A0target/riscv: Add vclmul.vv decoding, translation and execu= tion
> > =C2=A0=C2=A0 support
> > =C2=A0target/riscv: Add vclmul.vx decoding, translation and execu= tion
> > =C2=A0=C2=A0 support
> > =C2=A0target/riscv: Add vclmulh.vv decoding, translation and exec= ution
> > =C2=A0=C2=A0 support
> > =C2=A0target/riscv: Add vclmulh.vx decoding, translation and exec= ution
> > =C2=A0=C2=A0 support
> > =C2=A0target/riscv: Add vaesef.vv decoding, translation and execu= tion
> > =C2=A0=C2=A0 support
> > =C2=A0target/riscv: Add vaesef.vs decoding, translation and execu= tion
> > =C2=A0=C2=A0 support
> > =C2=A0target/riscv: Add vaesdf.vv decoding, translation and execu= tion
> > =C2=A0=C2=A0 support
> > =C2=A0target/riscv: Add vaesdf.vs decoding, translation and execu= tion
> > =C2=A0=C2=A0 support
> > =C2=A0target/riscv: Add vaesdm.vv decoding, translation and execu= tion
> > =C2=A0=C2=A0 support
> > =C2=A0target/riscv: Add vaesdm.vs decoding, translation and execu= tion
> > =C2=A0=C2=A0 support
> > =C2=A0target/riscv: Add vaesz.vs decoding, translation and execut= ion
> > support
> > =C2=A0target/riscv: Add vsha2c[hl].vv decoding, translation and > > execution
> > =C2=A0=C2=A0 support
> > =C2=A0target/riscv: Add vsm3me.vv decoding, translation and execu= tion
> > =C2=A0=C2=A0 support
> > =C2=A0target/riscv: add zvkg cpu property
> > =C2=A0target/riscv: Add vghmac.vv decoding, translation and execu= tion
> > =C2=A0=C2=A0 support
> > =C2=A0target/riscv: expose zvkg cpu property
> >
> > Max Chou (5):
> > =C2=A0crypto: Move SM4_SBOXWORD from target/riscv
> > =C2=A0crypto: Add SM4 constant parameter CK.
> > =C2=A0target/riscv: Add zvksed cfg property
> > =C2=A0target/riscv: Add Zvksed support
> > =C2=A0target/riscv: Expose Zvksed property
> >
> > Nazar Kazakov (10):
> > =C2=A0target/riscv: add zvkb cpu property
> > =C2=A0target/riscv: Add vrev8.v decoding, translation and executi= on
> > support
> > =C2=A0target/riscv: Add vandn.[vv,vx,vi] decoding, translation an= d
> > execution
> > =C2=A0=C2=A0 support
> > =C2=A0target/riscv: expose zvkb cpu property
> > =C2=A0target/riscv: add zvkns cpu property
> > =C2=A0target/riscv: Add vaeskf1.vi decoding, translation and executio= n
> > =C2=A0=C2=A0 support
> > =C2=A0target/riscv: Add vaeskf2.vi decoding, translation and executio= n
> > =C2=A0=C2=A0 support
> > =C2=A0target/riscv: expose zvkns cpu property
> > =C2=A0target/riscv: add zvknh cpu properties
> > =C2=A0target/riscv: expose zvknh cpu properties
> >
> > William Salmon (3):
> > =C2=A0target/riscv: Add vbrev8.v decoding, translation and execut= ion
> > support
> > =C2=A0target/riscv: Add vaesem.vv decoding, translation and execu= tion
> > =C2=A0=C2=A0 support
> > =C2=A0target/riscv: Add vaesem.vs decoding, translation and execu= tion
> > =C2=A0=C2=A0 support
> >
> > crypto/sm4.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0= =C2=A0 10 +
> > include/crypto/sm4.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0=C2=A0 8 +
> > include/qemu/bitops.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 32 +
> > target/arm/crypto_helper.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2= =A0=C2=A0 10 +-
> > target/riscv/cpu.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 15 +
> > target/riscv/cpu.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0=C2=A0 7 +
> > target/riscv/crypto_helper.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0= =C2=A0 1 +
> > target/riscv/helper.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 69 ++
> > target/riscv/insn32.decode=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2= =A0=C2=A0 48 +
> > target/riscv/insn_trans/trans_rvzvkb.c.inc=C2=A0=C2=A0 |=C2=A0 16= 4 +++
> > target/riscv/insn_trans/trans_rvzvkg.c.inc=C2=A0=C2=A0 |=C2=A0=C2= =A0=C2=A0 8 +
> > target/riscv/insn_trans/trans_rvzvknh.c.inc=C2=A0 |=C2=A0=C2=A0 4= 7 +
> > target/riscv/insn_trans/trans_rvzvkns.c.inc=C2=A0 |=C2=A0 121 +++=
> > target/riscv/insn_trans/trans_rvzvksed.c.inc |=C2=A0=C2=A0 38 + > > target/riscv/insn_trans/trans_rvzvksh.c.inc=C2=A0 |=C2=A0=C2=A0 2= 0 +
> > target/riscv/meson.build=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 |=C2=A0=C2=A0=C2=A0 4 +-
> > target/riscv/translate.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 |=C2=A0=C2=A0=C2=A0 6 +
> > target/riscv/vcrypto_helper.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 1013
> > ++++++++++++++++++
> > target/riscv/vector_helper.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 242 +-= ---
> > target/riscv/vector_internals.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0 63 ++
> > target/riscv/vector_internals.h=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 226 ++++
> > 21 files changed, 1902 insertions(+), 250 deletions(-)
> > create mode 100644 target/riscv/insn_trans/trans_rvzvkb.c.inc
> > create mode 100644 target/riscv/insn_trans/trans_rvzvkg.c.inc
> > create mode 100644 target/riscv/insn_trans/trans_rvzvknh.c.inc > > create mode 100644 target/riscv/insn_trans/trans_rvzvkns.c.inc > > create mode 100644 target/riscv/insn_trans/trans_rvzvksed.c.inc > > create mode 100644 target/riscv/insn_trans/trans_rvzvksh.c.inc > > create mode 100644 target/riscv/vcrypto_helper.c
> > create mode 100644 target/riscv/vector_internals.c
> > create mode 100644 target/riscv/vector_internals.h
> >
> > --
> > 2.39.1
> >
> >
> >

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X-Google-Smtp-Source: AK7set/pY8mgGFvQpSwzqYFy12QCC7CsrgaaGrNfsNx0v0AC1yAlIT/GErdinIzLhrbaU0/mfBzEOYxCm8oYoYiBgDg= X-Received: by 2002:a67:e184:0:b0:3eb:f205:2c08 with SMTP id e4-20020a67e184000000b003ebf2052c08mr1589258vsl.10.1675032032747; Sun, 29 Jan 2023 14:40:32 -0800 (PST) MIME-Version: 1.0 References: <20221223180016.2068508-1-christoph.muellner@vrull.eu> <20221223180016.2068508-2-christoph.muellner@vrull.eu> In-Reply-To: From: Alistair Francis Date: Mon, 30 Jan 2023 08:40:06 +1000 Message-ID: Subject: Re: [PATCH v2 01/15] RISC-V: Adding XTheadCmo ISA extension To: =?UTF-8?Q?Christoph_M=C3=BCllner?= Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::e33; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe33.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 29 Jan 2023 22:40:38 -0000 On Wed, Jan 25, 2023 at 5:51 AM Christoph M=C3=BCllner wrote: > > > > On Tue, Jan 24, 2023 at 6:31 PM Christoph M=C3=BCllner wrote: >> >> >> >> On Mon, Jan 23, 2023 at 11:50 PM Alistair Francis = wrote: >>> >>> On Sat, Dec 24, 2022 at 4:09 AM Christoph Muellner >>> wrote: >>> > >>> > From: Christoph M=C3=BCllner >>> > >>> > This patch adds support for the XTheadCmo ISA extension. >>> > To avoid interfering with standard extensions, decoder and translatio= n >>> > are in its own xthead* specific files. >>> > Future patches should be able to easily add additional T-Head extensi= on. >>> > >>> > The implementation does not have much functionality (besides acceptin= g >>> > the instructions and not qualifying them as illegal instructions if >>> > the hart executes in the required privilege level for the instruction= ), >>> > as QEMU does not model CPU caches and instructions are documented >>> > to not raise any exceptions. >>> > >>> > Changes in v2: >>> > - Add ISA_EXT_DATA_ENTRY() >>> > - Explicit test for PRV_U >>> > - Encapsule access to env-priv in inline function >>> > - Use single decoder for XThead extensions >>> > >>> > Co-developed-by: LIU Zhiwei >>> > Signed-off-by: Christoph M=C3=BCllner >>> > --- >>> > target/riscv/cpu.c | 2 + >>> > target/riscv/cpu.h | 1 + >>> > target/riscv/insn_trans/trans_xthead.c.inc | 89 ++++++++++++++++++++= ++ >>> > target/riscv/meson.build | 1 + >>> > target/riscv/translate.c | 15 +++- >>> > target/riscv/xthead.decode | 38 +++++++++ >>> > 6 files changed, 143 insertions(+), 3 deletions(-) >>> > create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc >>> > create mode 100644 target/riscv/xthead.decode >>> > >>> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >>> > index 6fe176e483..a90b82c5c5 100644 >>> > --- a/target/riscv/cpu.c >>> > +++ b/target/riscv/cpu.c >>> > @@ -108,6 +108,7 @@ static const struct isa_ext_data isa_edata_arr[] = =3D { >>> > ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinv= al), >>> > ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnap= ot), >>> > ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt= ), >>> > + ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xth= eadcmo), >>> > ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, e= xt_XVentanaCondOps), >>> > }; >>> > >>> > @@ -1060,6 +1061,7 @@ static Property riscv_cpu_extensions[] =3D { >>> > DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), >>> > >>> > /* Vendor-specific custom extensions */ >>> > + DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false= ), >>> > DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCo= ndOps, false), >>> > >>> > /* These are experimental so mark with 'x-' */ >>> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h >>> > index 443d15a47c..ad1c19f870 100644 >>> > --- a/target/riscv/cpu.h >>> > +++ b/target/riscv/cpu.h >>> > @@ -465,6 +465,7 @@ struct RISCVCPUConfig { >>> > uint64_t mimpid; >>> > >>> > /* Vendor-specific custom extensions */ >>> > + bool ext_xtheadcmo; >>> > bool ext_XVentanaCondOps; >>> > >>> > uint8_t pmu_num; >>> > diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/risc= v/insn_trans/trans_xthead.c.inc >>> > new file mode 100644 >>> > index 0000000000..00e75c7dca >>> > --- /dev/null >>> > +++ b/target/riscv/insn_trans/trans_xthead.c.inc >>> > @@ -0,0 +1,89 @@ >>> > +/* >>> > + * RISC-V translation routines for the T-Head vendor extensions (xth= ead*). >>> > + * >>> > + * Copyright (c) 2022 VRULL GmbH. >>> > + * >>> > + * This program is free software; you can redistribute it and/or mod= ify it >>> > + * under the terms and conditions of the GNU General Public License, >>> > + * version 2 or later, as published by the Free Software Foundation. >>> > + * >>> > + * This program is distributed in the hope it will be useful, but WI= THOUT >>> > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILIT= Y or >>> > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public Lic= ense for >>> > + * more details. >>> > + * >>> > + * You should have received a copy of the GNU General Public License= along with >>> > + * this program. If not, see . >>> > + */ >>> > + >>> > +#define REQUIRE_XTHEADCMO(ctx) do { \ >>> > + if (!ctx->cfg_ptr->ext_xtheadcmo) { \ >>> > + return false; \ >>> > + } \ >>> > +} while (0) >>> > + >>> > +/* XTheadCmo */ >>> > + >>> > +static inline int priv_level(DisasContext *ctx) >>> > +{ >>> > +#ifdef CONFIG_USER_ONLY >>> > + return PRV_U; >>> > +#else >>> > + /* Priv level equals mem_idx -- see cpu_mmu_index. */ >>> > + return ctx->mem_idx; >>> >>> This should be ANDed with TB_FLAGS_PRIV_MMU_MASK as sometimes this can >>> include hypervisor priv access information >> >> >> Ok. >> >>> >>> >>> > +#endif >>> > +} >>> > + >>> > +#define REQUIRE_PRIV_MHSU(ctx) \ >>> > +do { \ >>> > + int priv =3D priv_level(ctx); \ >>> > + if (!(priv =3D=3D PRV_M || = \ >>> > + priv =3D=3D PRV_H || = \ >>> >>> PRV_H isn't used >>> >>> > + priv =3D=3D PRV_S || = \ >>> > + priv =3D=3D PRV_U)) { = \ >>> > + return false; \ >>> >>> When would this not be the case? >> >> >> Ok, I will make this a macro that expands to nothing (and a comment). >> >>> >>> >>> > + } \ >>> > +} while (0) >>> > + >>> > +#define REQUIRE_PRIV_MHS(ctx) \ >>> > +do { \ >>> > + int priv =3D priv_level(ctx); \ >>> > + if (!(priv =3D=3D PRV_M || = \ >>> > + priv =3D=3D PRV_H || = \ >>> >>> Also not used >> >> >> Ok, I will remove the PRV_H. >> >>> >>> >>> > + priv =3D=3D PRV_S)) { = \ >>> > + return false; \ >>> > + } \ >>> > +} while (0) >>> > + >>> > +#define NOP_PRIVCHECK(insn, extcheck, privcheck) \ >>> > +static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn * a) \ >>> > +{ \ >>> > + (void) a; \ >>> > + extcheck(ctx); \ >>> > + privcheck(ctx); \ >>> > + return true; \ >>> > +} >>> > + >>> > +NOP_PRIVCHECK(th_dcache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >>> > +NOP_PRIVCHECK(th_dcache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >>> > +NOP_PRIVCHECK(th_dcache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >>> > +NOP_PRIVCHECK(th_dcache_cpa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >>> > +NOP_PRIVCHECK(th_dcache_cipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >>> > +NOP_PRIVCHECK(th_dcache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >>> > +NOP_PRIVCHECK(th_dcache_cva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) >>> > +NOP_PRIVCHECK(th_dcache_civa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) >>> > +NOP_PRIVCHECK(th_dcache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) >>> > +NOP_PRIVCHECK(th_dcache_csw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >>> > +NOP_PRIVCHECK(th_dcache_cisw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >>> > +NOP_PRIVCHECK(th_dcache_isw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >>> > +NOP_PRIVCHECK(th_dcache_cpal1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >>> > +NOP_PRIVCHECK(th_dcache_cval1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >>> > + >>> > +NOP_PRIVCHECK(th_icache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >>> > +NOP_PRIVCHECK(th_icache_ialls, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >>> > +NOP_PRIVCHECK(th_icache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >>> > +NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) >>> > + >>> > +NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >>> > +NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >>> > +NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) >>> > diff --git a/target/riscv/meson.build b/target/riscv/meson.build >>> > index ba25164d74..5dee37a242 100644 >>> > --- a/target/riscv/meson.build >>> > +++ b/target/riscv/meson.build >>> > @@ -2,6 +2,7 @@ >>> > gen =3D [ >>> > decodetree.process('insn16.decode', extra_args: ['--static-decode= =3Ddecode_insn16', '--insnwidth=3D16']), >>> > decodetree.process('insn32.decode', extra_args: '--static-decode= =3Ddecode_insn32'), >>> > + decodetree.process('xthead.decode', extra_args: '--static-decode= =3Ddecode_xthead'), >>> > decodetree.process('XVentanaCondOps.decode', extra_args: '--static= -decode=3Ddecode_XVentanaCodeOps'), >>> > ] >>> > >>> > diff --git a/target/riscv/translate.c b/target/riscv/translate.c >>> > index db123da5ec..14d9116975 100644 >>> > --- a/target/riscv/translate.c >>> > +++ b/target/riscv/translate.c >>> > @@ -125,13 +125,18 @@ static bool always_true_p(DisasContext *ctx __= attribute__((__unused__))) >>> > return true; >>> > } >>> > >>> > +static bool has_xthead_p(DisasContext *ctx __attribute__((__unused_= _))) >>> > +{ >>> > + return ctx->cfg_ptr->ext_xtheadcmo; >>> > +} >>> > + >>> > #define MATERIALISE_EXT_PREDICATE(ext) \ >>> > static bool has_ ## ext ## _p(DisasContext *ctx) \ >>> > { \ >>> > return ctx->cfg_ptr->ext_ ## ext ; \ >>> > } >>> > >>> > -MATERIALISE_EXT_PREDICATE(XVentanaCondOps); >>> > +MATERIALISE_EXT_PREDICATE(XVentanaCondOps) >>> >>> Do we need this change? >> >> >> It is indeed a drive-by cleanup, that is not necessary. >> In v1 we were using this macro, therefore it made sense back then. >> Will be dropped. >> >>> >>> >>> > >>> > #ifdef TARGET_RISCV32 >>> > #define get_xl(ctx) MXL_RV32 >>> > @@ -732,6 +737,10 @@ static int ex_rvc_shiftri(DisasContext *ctx, int= imm) >>> > /* Include the auto-generated decoder for 32 bit insn */ >>> > #include "decode-insn32.c.inc" >>> > >>> > +/* Include decoders for factored-out extensions */ >>> > +#include "decode-xthead.c.inc" >>> > +#include "decode-XVentanaCondOps.c.inc" >>> > + >>> > static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, >>> > void (*func)(TCGv, TCGv, target_long)) >>> > { >>> > @@ -1033,12 +1042,11 @@ static uint32_t opcode_at(DisasContextBase *d= cbase, target_ulong pc) >>> > #include "insn_trans/trans_rvk.c.inc" >>> > #include "insn_trans/trans_privileged.c.inc" >>> > #include "insn_trans/trans_svinval.c.inc" >>> > +#include "insn_trans/trans_xthead.c.inc" >>> > #include "insn_trans/trans_xventanacondops.c.inc" >>> > >>> > /* Include the auto-generated decoder for 16 bit insn */ >>> > #include "decode-insn16.c.inc" >>> > -/* Include decoders for factored-out extensions */ >>> > -#include "decode-XVentanaCondOps.c.inc" >>> >>> Can we not leave these at the bottom? >> >> >> Ok. > > > I got reminded again, why this is like it is: > The decoder code needs to be included before the translation functions, > because the translation functions use types that are defined in the gener= ated decoder code. > And I wanted to keep all vendor extensions together. Ah ok, why not keep each extension together instead, like this: #include "decode-xthead.c.inc" #include "insn_trans/trans_xthead.c.inc" #include "decode-XVentanaCondOps.c.inc" Alistair From MAILER-DAEMON Sun Jan 29 17:51:46 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMGWW-000461-AY for mharc-qemu-riscv@gnu.org; Sun, 29 Jan 2023 17:51:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMGWG-00045B-6x; Sun, 29 Jan 2023 17:51:31 -0500 Received: from mail-vs1-xe35.google.com ([2607:f8b0:4864:20::e35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMGWE-0001g5-8h; Sun, 29 Jan 2023 17:51:27 -0500 Received: by mail-vs1-xe35.google.com with SMTP id i185so10758609vsc.6; Sun, 29 Jan 2023 14:51:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=NlAGN8yc5gDGgu9f/88EGyDV5hZRAa54oGqx6U59crU=; b=SaJxDbWOMfRIRdnjvrQ+tMSw5qYEtOKJeDmmuCrr4nENAobM/knrM0yYAtwsaw6REV epAh1ARlojqs+jXrUGZgJjOAKvxWMQmRANio3BU+fMTsiSE7aoNYzsHCG3ZV7/rtD65g QHfrokZipEF3gcDONUT30pz0exbgFxar7KeO39VjkSXEHiqpQ4IifblSuB8wAcqfnkSy U8pPN4y7iEirBxu+sO2e4bNrDvuSw/vthR8LwtpJY9P7T5EoWazQ/ijSEOKHJOveK3qc LTlFAhbS+IwCogH0YZAHXv9sNJY1+VrMstu3B+BdvnlTfux0hgTAGXH9fnT0mtDDW3T3 /d2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=NlAGN8yc5gDGgu9f/88EGyDV5hZRAa54oGqx6U59crU=; b=gskNaPmo9ySgwRzpI2Ck3M3oWjG2k/8O6pAXDv/azzkt7J2J5k2D/KIpebVUOR/No9 rdDoU9ZcKRxGOTNm1TPOFhawQweWAYKoN3IOxf9cS2+/I+lC3zcl5TXNVjnkajSrFj2A PSdljgZbebbnYSNkehENISyi5W3RtQWCfl9E7AuaFrtp7o2cvnLNJBsTBhhCzfZFvutz h3Z1gIRN0GSUVy3PRSZsgKeasQyD/xppYIKo/kf6WOjQDM4gPfO06Y4nY85i09CnO4VR rBHIp7FxnHDmDxjhRpDgbiLjIw6w7f+nERzi75FuBEWxrQSeODq0qCU01pkQREfhQJok dzaA== X-Gm-Message-State: AO0yUKXj9uRdw72n79OkrGwHoJ4uFpDrQ1LtU/PgoCKJQlL75FHFIU25 NbHm+AZh69msby8u4YzwxiJ+9frA4aCl7Xi8+0LKt/MXN3I= X-Google-Smtp-Source: AK7set/NJl3cpVbUztJNzm7NhgPzf2OR3eVanxy5a8EKpgAp1FxqpHFMjbNSSnVhtMDpgOPEDRHu3Gde6rmxTZzZzdI= X-Received: by 2002:a67:e184:0:b0:3eb:f205:2c08 with SMTP id e4-20020a67e184000000b003ebf2052c08mr1591684vsl.10.1675032683354; Sun, 29 Jan 2023 14:51:23 -0800 (PST) MIME-Version: 1.0 References: <20230113171805.470252-1-dbarboza@ventanamicro.com> <20230113171805.470252-4-dbarboza@ventanamicro.com> In-Reply-To: From: Alistair Francis Date: Mon, 30 Jan 2023 08:50:57 +1000 Message-ID: Subject: Re: [PATCH v7 3/3] hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym() To: Bin Meng Cc: Daniel Henrique Barboza , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com, =?UTF-8?Q?Philippe_Mathieu=2DDaud=C3=A9?= Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e35; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe35.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 29 Jan 2023 22:51:40 -0000 On Thu, Jan 26, 2023 at 10:07 PM Bin Meng wrote: > > Hi Alistair, > > On Mon, Jan 16, 2023 at 12:28 PM Alistair Francis wrote: > > > > On Sat, Jan 14, 2023 at 11:41 PM Bin Meng wrote: > > > > > > On Sat, Jan 14, 2023 at 1:18 AM Daniel Henrique Barboza > > > wrote: > > > > > > > > Recent hw/risc/boot.c changes caused a regression in an use case with > > > > the Xvisor hypervisor. Running a 32 bit QEMU guest with '-kernel' > > > > stopped working. The reason seems to be that Xvisor is using 64 bit to > > > > encode the 32 bit addresses from the guest, and load_elf_ram_sym() is > > > > sign-extending the result with '1's [1]. > > > > > > I would say it's not a regression of QEMU but something weird happened > > > to Alistair's 32-bit Xvisor image. > > > > I don't think it's a Xvisor issue. > > > > > > > > I just built a 32-bit Xvisor image from the latest Xvisor head > > > following the instructions provided in its source tree. With the > > > mainline QEMU only BIN file boots, but ELF does not. My 32-bit Xvisor > > > image has an address of 0x10000000. Apparently this address is not > > > correct, and the issue I saw is different from Alistair's. Alistair, > > > could you investigate why your 32-bit Xvisor ELF image has an address > > > of 0xffffffff80000000 set to kernel_load_base? > > > > Looking in load_elf() in include/hw/elf_ops.h at this line: > > > > if (lowaddr) > > *lowaddr = (uint64_t)(elf_sword)low; > > > > I can see that `low` is 0x80000000 but lowaddr is set to > > 0xffffffff80000000. So the address is being sign extended with 1s. > > > > I don't understand the sign extension here. This seems intentional as > the codes does the signed extension then casted to unsigned 64-bit. > > Do you know why? No idea! Alistair > > > This patch seems to be the correct fix. > > > > Regards, > Bin From MAILER-DAEMON Sun Jan 29 18:19:16 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMGx9-0000om-Sn for mharc-qemu-riscv@gnu.org; Sun, 29 Jan 2023 18:19:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMGx7-0000oV-QJ; Sun, 29 Jan 2023 18:19:13 -0500 Received: from mail-vs1-xe2f.google.com ([2607:f8b0:4864:20::e2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMGx6-0005vT-2k; Sun, 29 Jan 2023 18:19:13 -0500 Received: by mail-vs1-xe2f.google.com with SMTP id i188so10775760vsi.8; Sun, 29 Jan 2023 15:19:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=cH+miPkzbGDTbf0TElGPqQol+Y6u3aLOc3n01pQi59o=; b=HIRjxsbg8vGSvn2FDh4G2WkK8sjaTYjt/D64aCiLYjtX38ZSdXVzDvsjkqlKTrdt8N 1ZCwm2wCD01l8uV3wwtKZ//MHDM9Q/EqEgP0//+lakYlyMg4ECEilsAp/zsr1CG6lOJ4 0VwdPaSaSURlqsSXjMEJKjmtnX7wqlGLMkoRPBn7J08M52DfqqFvzFRPtd7nXOmpigEY nJx1np9oxVzaWfkLjwj+ch4j7T0N3MHOW5XUcEvGU+gC+YZm2BnQBN5MpQHsawGIBcqt IDuYanALL6KZ63q6w22FvmF3VtV5JM+aVcwAHUfdcOFsufqKqse3tZFd+OukHHQXnobq ExKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=cH+miPkzbGDTbf0TElGPqQol+Y6u3aLOc3n01pQi59o=; b=DLzRhVpQ6lcAFZhGhery1zbl2mf7ul64WSy3Wyt4ql0m2VdsccqDYQ/A6WpMQWBLl0 +661B/wcg0+b4RTjOVDKAZbDw005ecK7LhEu2jnBDMDkbT3PNbiVUysSX1Xiqb/7ECa0 P7MSy86ABP88SpuQQeLudiXTzAfOQo0CKS7Y0Y7WLfJJYVCyp0ZlTkdrPNXr529QUmcJ MCdQ4daMexXwxjQK7BO2YMYpNG+ySeG6mgnl0PNJEkZ1CA7HtepDBD7PfkkXMdSQyStX uSZ0SPKcJ/7zIbyae0ZGs+FoOMkzX3qeo1Gyb9494OrjTnbX0sXIksUlyZOGp/NLoW+T DMIQ== X-Gm-Message-State: AO0yUKXkBDVg5iJqsrI853zh71EvwoeIZyA9J5oyRFdRNosVNaAJYLLv BAen211Q7XRKLqiLm1s+dkX7OYIhEfItkJjRvIIFIMpOL4iXdA== X-Google-Smtp-Source: AK7set8HWAIXxuPRgacse35G3WsNIe1R9bmRYaqi1tnfJcyge+wmoQ67KS9nQXhcw5ArJBViJR7FZDQ6kn+hfb05PJA= X-Received: by 2002:a67:e101:0:b0:3f0:89e1:7c80 with SMTP id d1-20020a67e101000000b003f089e17c80mr796810vsl.72.1675034350837; Sun, 29 Jan 2023 15:19:10 -0800 (PST) MIME-Version: 1.0 References: <20230123035754.75553-1-alistair.francis@opensource.wdc.com> In-Reply-To: From: Alistair Francis Date: Mon, 30 Jan 2023 09:18:44 +1000 Message-ID: Subject: Re: [PATCH] hw/riscv: boot: Don't use CSRs if they are disabled To: Bin Meng Cc: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e2f; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2f.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 29 Jan 2023 23:19:14 -0000 On Thu, Jan 26, 2023 at 10:03 PM Bin Meng wrote: > > On Tue, Jan 24, 2023 at 9:42 AM Alistair Francis wrote: > > > > On Tue, Jan 24, 2023 at 11:24 AM Bin Meng wrote: > > > > > > On Mon, Jan 23, 2023 at 11:58 AM Alistair Francis > > > wrote: > > > > > > > > From: Alistair Francis > > > > > > > > If the CSRs and CSR instructions are disabled because the Zicsr > > > > extension isn't enabled then we want to make sure we don't run any CSR > > > > instructions in the boot ROM. > > > > > > > > This patches removes the CSR instructions from the reset-vec if the > > > > extension isn't enabled. We replace the instruction with a NOP instead. > > > > > > > > Note that we don't do this for the SiFive U machine, as we are modelling > > > > the hardware in that case. > > > > > > > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1447 > > > > Signed-off-by: Alistair Francis > > > > --- > > > > hw/riscv/boot.c | 9 +++++++++ > > > > 1 file changed, 9 insertions(+) > > > > > > > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > > > > index 2594276223..cb27798a25 100644 > > > > --- a/hw/riscv/boot.c > > > > +++ b/hw/riscv/boot.c > > > > @@ -356,6 +356,15 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts > > > > reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ > > > > } > > > > > > > > + if (!harts->harts[0].cfg.ext_icsr) { > > > > + /* > > > > + * The Zicsr extension has been disabled, so let's ensure we don't > > > > + * run the CSR instruction. Let's fill the address with a non > > > > + * compressed nop. > > > > + */ > > > > + reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */ > > > > + } > > > > > > This is fine for a UP system. I am not sure how SMP can be supported > > > without Zicsr as we need to assign hartid in a0. > > > > Yeah. My thinking was that no one would be using a multicore system > > without Zicsr as it's such a core extension. If they are running > > without Zicsr they have probably hard coded a lot of things anyway and > > don't expect this to work. > > > > In general I think it's pretty rare to even run a RISC-V core without > > Zicsr at all. > > > > As QEMU implements Zicsr anyway, and there is no way to support SMP > without Zicsr, should we disallow user to disable Zicsr in QEMU? I feel like we don't need to do that. Here's my thinking: Zicsr is a RISC-V extension, the RISC-V spec splits it out so that it can be disabled. In theory someone could build a multi-hart CPU without Zicsr in hardware, so QEMU should be able to model it. As well as that Zicsr is enabled by default, so a user has to know enough to disable it manually. At which point they probably know what they are doing, especially as no standard software will run without Zicsr. If that's what someone wants to do then we should allow them to, even if it's a bit strange. Alistair > > Regards, > Bin From MAILER-DAEMON Sun Jan 29 20:47:07 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMJGE-0005uu-9A for mharc-qemu-riscv@gnu.org; Sun, 29 Jan 2023 20:47:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMJG4-0005uA-A2; Sun, 29 Jan 2023 20:46:57 -0500 Received: from mail-vs1-xe31.google.com ([2607:f8b0:4864:20::e31]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMJG1-0002HZ-HB; Sun, 29 Jan 2023 20:46:55 -0500 Received: by mail-vs1-xe31.google.com with SMTP id 187so10970062vsv.10; Sun, 29 Jan 2023 17:46:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=jTcyvn84Ktx1SzMuYPD98jEGHANSEo8cFAF3Fz3MzO8=; b=F/TfoWK6JIcQ7bghBKyH8suyY8KDEAWTdpEtajQLYGOfWLr9bJIxi+VgREdPCcP4Ce uck7HKsBqeU7bcy4nLZYEr4nL/ELNHPz4YtT9fNttFbuCg9dHmm+fn69X7ZLgVldyrAq /JH/6McoaN+6rhhFkjjJUR9wldIvb7MdtJRIFkc27FehQ4RPmxbBYAGKQdPe/I1xXvsR hcXXL1U5JPW6BkvlpGhbmvgEM9axkYMm1qMf2Tdzi9s28/NPRzAD63yq/VkLPA4nfvHh jVmCAQkO2unZdp5ZNoxT0kPQFcTwYUzjQaMV4ZYrSRrs6/xciNTxcxhfeaWtrQ95EFIn z6yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=jTcyvn84Ktx1SzMuYPD98jEGHANSEo8cFAF3Fz3MzO8=; b=oiyDQBT0ytrqCCU5P+9oS4ajpHh9w3RQSo+FBxitwF5d8FmE3Nqu9utpG2BNGXN5ob 3plt7Kf05jGWCNcwyXea7UM/qFJtW5UWvQ5YKbfV3WWXD2tGXvQd+37LZHQOb1YobL39 J45AeEK1KHKLr5i55Ap+K/dGbmZeqt+r5Q0+mT1Kqrdyp7kdx46oDpkvsikmdAod7xO3 5b33r60Gwg/LFF0x09Bwsk1mtrIE2x4Qx8aPQKrI8Ov+EdfwucY6BDYfJ94y9hy9MQJm mQksFtAjbNkpsw40hNGaRdT7zLuQtVr2ElIeYx83XYUq5HQ3kvhorJQxoIrvnLySa+oJ 1xiw== X-Gm-Message-State: AO0yUKUeivHwP/70tJKZfLmnWs4V34NErvgzJco/bOChQyyEM2HQBt/C 3YNqYOl/f2KAiua8+wd/OdEoOUEXREj4ts4QCaY= X-Google-Smtp-Source: AK7set9+ATjERnsmXGraOfm4XULr7IQBTJRBueuh27WRU7M/x+6rnGxVhuknV1m8oBzNv1fzLWi6w9pBn7Xd6ZMJqt8= X-Received: by 2002:a05:6102:232e:b0:3ee:4ef8:45d3 with SMTP id b14-20020a056102232e00b003ee4ef845d3mr1165177vsa.64.1675043211636; Sun, 29 Jan 2023 17:46:51 -0800 (PST) MIME-Version: 1.0 References: <20230124212234.412630-1-dbarboza@ventanamicro.com> In-Reply-To: <20230124212234.412630-1-dbarboza@ventanamicro.com> From: Alistair Francis Date: Mon, 30 Jan 2023 11:46:25 +1000 Message-ID: Subject: Re: [PATCH v4 0/3] hw/riscv: misc cleanups To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e31; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe31.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 01:47:00 -0000 On Wed, Jan 25, 2023 at 7:23 AM Daniel Henrique Barboza wrote: > > Hi, > > These are the last 3 patches from the series > > "[PATCH v3 0/7] riscv: fdt related cleanups" > > That can be sent in separate from the fdt work. Patches are all acked. > > Changes from v3: > - patches 1,2,3: > - former patches 5, 6 and 7 from "[PATCH v3 0/7] riscv: fdt related cleanups" > - v3 link: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg04464.html > > Daniel Henrique Barboza (3): > hw/riscv/virt.c: calculate socket count once in create_fdt_imsic() > hw/riscv/virt.c: rename MachineState 'mc' pointers to 'ms' > hw/riscv/spike.c: rename MachineState 'mc' pointers to' ms' Thanks! Applied to riscv-to-apply.next Alistair > > hw/riscv/spike.c | 18 +- > hw/riscv/virt.c | 462 ++++++++++++++++++++++++----------------------- > 2 files changed, 242 insertions(+), 238 deletions(-) > > -- > 2.39.1 > > From MAILER-DAEMON Sun Jan 29 21:04:16 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMJWp-0008KG-Nh for mharc-qemu-riscv@gnu.org; Sun, 29 Jan 2023 21:04:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMJWS-0008Ih-Du; Sun, 29 Jan 2023 21:04:08 -0500 Received: from out30-110.freemail.mail.aliyun.com ([115.124.30.110]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMJWO-0004dV-GE; Sun, 29 Jan 2023 21:03:50 -0500 X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R521e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046056; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=14; SR=0; TI=SMTPD_---0VaM2vy._1675044203; Received: from 30.39.235.119(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0VaM2vy._1675044203) by smtp.aliyun-inc.com; Mon, 30 Jan 2023 10:03:24 +0800 Message-ID: <8385d954-678e-d78d-c3ae-d74a4a902907@linux.alibaba.com> Date: Mon, 30 Jan 2023 10:03:08 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension To: Richard Henderson , Christoph Muellner , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=c3=bcbner?= , Palmer Dabbelt , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang References: <20230124195945.181842-1-christoph.muellner@vrull.eu> <20230124195945.181842-9-christoph.muellner@vrull.eu> <48ff4151-25d9-4b4d-d50a-6516000599c7@linaro.org> Content-Language: en-US From: LIU Zhiwei In-Reply-To: <48ff4151-25d9-4b4d-d50a-6516000599c7@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=115.124.30.110; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-110.freemail.mail.aliyun.com X-Spam_score_int: -99 X-Spam_score: -10.0 X-Spam_bar: ---------- X-Spam_report: (-10.0 / 5.0 requ) BAYES_00=-1.9, ENV_AND_HDR_SPF_MATCH=-0.5, NICE_REPLY_A=-0.092, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 02:04:13 -0000 On 2023/1/25 4:44, Richard Henderson wrote: > On 1/24/23 09:59, Christoph Muellner wrote: >> +static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp >> memop, >> +                            int shamt) >> +{ >> +    TCGv rd1 = dest_gpr(ctx, a->rd1); >> +    TCGv rd2 = dest_gpr(ctx, a->rd2); >> +    TCGv addr1 = tcg_temp_new(); >> +    TCGv addr2 = tcg_temp_new(); >> + >> +    addr1 = get_address(ctx, a->rs, a->sh2 << shamt); >> +    if ((memop & MO_SIZE) == MO_64) { >> +        addr2 = get_address(ctx, a->rs, 8 + (a->sh2 << shamt)); >> +    } else { >> +        addr2 = get_address(ctx, a->rs, 4 + (a->sh2 << shamt)); >> +    } >> + >> +    tcg_gen_qemu_ld_tl(rd1, addr1, ctx->mem_idx, memop); >> +    tcg_gen_qemu_ld_tl(rd2, addr2, ctx->mem_idx, memop); >> +    gen_set_gpr(ctx, a->rd1, rd1); >> +    gen_set_gpr(ctx, a->rd2, rd2); > > Since dest_gpr may return cpu_gpr[n], this may update the rd1 before > recognizing the exception that the second load may generate.  Is that > correct? Thanks. It's a bug. We should load all memory addresses to  local TCG  temps first. Do you think we should probe all the memory addresses for the store pair instructions? If so, can we avoid the use of a helper function? > > The manual says that rd1, rd2, and rs1 must not be the same, but you > do not check this. The main reason is that assembler can do this check. Is it necessary to check this in QEMU? Best Regards, Zhiwei > > > r~ From MAILER-DAEMON Sun Jan 29 23:11:57 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMLWP-000753-B4 for mharc-qemu-riscv@gnu.org; Sun, 29 Jan 2023 23:11:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMLWO-00074Y-1k for qemu-riscv@nongnu.org; Sun, 29 Jan 2023 23:11:56 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMLWM-00014N-Jt for qemu-riscv@nongnu.org; Sun, 29 Jan 2023 23:11:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1675051912; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type:in-reply-to:in-reply-to: references:references; bh=MGdaT5bvuLQsbnKTmhYEgxvxJGVouGB8/uGbyCZ1Syk=; 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Sun, 29 Jan 2023 20:11:50 -0800 (PST) X-Google-Smtp-Source: AK7set9PrQoiJWa4Jju2OJXeaQpCMAKn/3ZFDL05ufOnJUvHZgjK5BymTZTePkBgeWvTc4M9o00Dbw== X-Received: by 2002:a05:600c:1c9f:b0:3dc:5aa8:952e with SMTP id k31-20020a05600c1c9f00b003dc5aa8952emr1331245wms.21.1675051909833; Sun, 29 Jan 2023 20:11:49 -0800 (PST) Received: from redhat.com ([46.136.252.173]) by smtp.gmail.com with ESMTPSA id l4-20020a7bc444000000b003db03725e86sm11403628wmi.8.2023.01.29.20.11.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Jan 2023 20:11:49 -0800 (PST) From: Juan Quintela To: Markus Armbruster Cc: "Dr. David Alan Gilbert" , qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 10/19] migration: Clean up includes In-Reply-To: <87wn5hoeqf.fsf@pond.sub.org> (Markus Armbruster's message of "Fri, 20 Jan 2023 08:19:04 +0100") References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-11-armbru@redhat.com> <87wn5ivmru.fsf@pond.sub.org> <87wn5hoeqf.fsf@pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) Reply-To: quintela@redhat.com Date: Mon, 30 Jan 2023 05:11:48 +0100 Message-ID: <87bkmgpsor.fsf@secure.mitica> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain Received-SPF: pass client-ip=170.10.129.124; envelope-from=quintela@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 04:11:56 -0000 Markus Armbruster wrote: > "Dr. David Alan Gilbert" writes: > >> * Markus Armbruster (armbru@redhat.com) wrote: >>> "Dr. David Alan Gilbert" writes: >>> >>> > * Markus Armbruster (armbru@redhat.com) wrote: >>> >> Clean up includes so that osdep.h is included first and headers >>> >> which it implies are not included manually. >>> > >>> > That change doesn't seem to match the message; the patch is removing the >>> > osdep.h include. >>> >>> It's the commit message scripts/clean-includes creates :) >>> >>> I can throw in another patch to the script so it mentions it also >>> removes qemu/osdep.h from headers. >> >> Oh hmm it would be clearer; > > What about > > $GITSUBJ: Clean up includes > > Clean up includes so that osdep.h is included first in .c and not in > .h, and headers which it implies are not included manually. > > This commit was created with scripts/clean-includes. > > >> but OK then, so >> >> Reviewed-by: Dr. David Alan Gilbert Sounds ok to me. Reviewed-by: Juan Quintela From MAILER-DAEMON Sun Jan 29 23:13:31 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMLXv-0007rt-F2 for mharc-qemu-riscv@gnu.org; Sun, 29 Jan 2023 23:13:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMLXu-0007rW-2z for qemu-riscv@nongnu.org; Sun, 29 Jan 2023 23:13:30 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMLXs-0001KK-TK for qemu-riscv@nongnu.org; Sun, 29 Jan 2023 23:13:29 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1675052008; h=from:from:reply-to:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type:in-reply-to:in-reply-to: references:references; bh=f8LlpqFMBZVRcZHC0EnU984o9h8pM2ZpA8U/VQuUvn0=; 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Sun, 29 Jan 2023 20:13:24 -0800 (PST) X-Google-Smtp-Source: AK7set+XglkjkINPW4f9AT1zRF3CVQglpRm0o9aHj+JzjrACrSAbCWbRtNg/iugAEO1yWV5b8lh7ig== X-Received: by 2002:a05:600c:b4d:b0:3dc:3f51:c697 with SMTP id k13-20020a05600c0b4d00b003dc3f51c697mr9491262wmr.18.1675052003885; Sun, 29 Jan 2023 20:13:23 -0800 (PST) Received: from redhat.com ([46.136.252.173]) by smtp.gmail.com with ESMTPSA id o2-20020a05600c510200b003db16770bc5sm3110464wms.6.2023.01.29.20.13.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Jan 2023 20:13:23 -0800 (PST) From: Juan Quintela To: Markus Armbruster Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 16/19] Fix non-first inclusions of qemu/osdep.h In-Reply-To: <20230119065959.3104012-17-armbru@redhat.com> (Markus Armbruster's message of "Thu, 19 Jan 2023 07:59:56 +0100") References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-17-armbru@redhat.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) Reply-To: quintela@redhat.com Date: Mon, 30 Jan 2023 05:13:22 +0100 Message-ID: <877cx4psm5.fsf@secure.mitica> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain Received-SPF: pass client-ip=170.10.129.124; envelope-from=quintela@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 04:13:30 -0000 Markus Armbruster wrote: > This commit was created with scripts/clean-includes. > > Signed-off-by: Markus Armbruster Reviewed-by: Juan Quintela From MAILER-DAEMON Sun Jan 29 23:17:13 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMLbM-0000cG-7V for mharc-qemu-riscv@gnu.org; Sun, 29 Jan 2023 23:17:13 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMLb1-0000aQ-RR for qemu-riscv@nongnu.org; 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Sun, 29 Jan 2023 20:16:39 -0800 (PST) X-Google-Smtp-Source: AK7set/NuJm0/GGFcSWLl2wNg3skVv07Dwu7LNXy9+q+i4AjVPh3KV/Q5F/R/gsH9xGlHqFeji8eAg== X-Received: by 2002:a7b:c85a:0:b0:3d2:813:138a with SMTP id c26-20020a7bc85a000000b003d20813138amr4048227wml.35.1675052198873; Sun, 29 Jan 2023 20:16:38 -0800 (PST) Received: from redhat.com ([46.136.252.173]) by smtp.gmail.com with ESMTPSA id 19-20020a05600c26d300b003dc50c38921sm4586064wmv.35.2023.01.29.20.16.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 29 Jan 2023 20:16:38 -0800 (PST) From: Juan Quintela To: Markus Armbruster Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 19/19] Drop duplicate #include In-Reply-To: <20230119065959.3104012-20-armbru@redhat.com> (Markus Armbruster's message of "Thu, 19 Jan 2023 07:59:59 +0100") References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-20-armbru@redhat.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) Reply-To: quintela@redhat.com Date: Mon, 30 Jan 2023 05:16:37 +0100 Message-ID: <87357spsgq.fsf@secure.mitica> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain Received-SPF: pass client-ip=170.10.133.124; envelope-from=quintela@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 04:17:01 -0000 Markus Armbruster wrote: > Tracked down with the help of scripts/clean-includes. > > Signed-off-by: Markus Armbruster > diff --git a/migration/postcopy-ram.c b/migration/postcopy-ram.c > index b9a37ef255..8b7d1af75d 100644 > --- a/migration/postcopy-ram.c > +++ b/migration/postcopy-ram.c > @@ -17,7 +17,6 @@ > */ > > #include "qemu/osdep.h" > -#include "qemu/rcu.h" > #include "qemu/madvise.h" > #include "exec/target_page.h" > #include "migration.h" > @@ -34,7 +33,6 @@ > #include "hw/boards.h" > #include "exec/ramblock.h" > #include "socket.h" > -#include "qemu-file.h" > #include "yank_functions.h" > #include "tls.h" Ouch Reviewed-by: Juan Quintela I don't want to look into the logs. They *could* say that it was me the one doing the mess. From MAILER-DAEMON Sun Jan 29 23:22:50 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMLgw-0003JH-Nu for mharc-qemu-riscv@gnu.org; Sun, 29 Jan 2023 23:22:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMLgv-0003Il-3P; Sun, 29 Jan 2023 23:22:49 -0500 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMLgs-0002d8-Tp; Sun, 29 Jan 2023 23:22:48 -0500 Received: by mail-ed1-x529.google.com with SMTP id s3so9753229edd.4; Sun, 29 Jan 2023 20:22:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=C6np+RYCepeqPXqjfNTRSDnPt2LN4thT/gRm3PIUeWs=; b=lkhhYRSVCVIxNLBQaDcsAGXGCeKK8jBh/vwAcbg9cqRewrw0g1S05lDuzky72skrtm UokpgY/Q6uUbg7K8G7U0k/0CJ0uqySeicKBaa29l7TnV5VYdX6NG8L/7VSi3nGY3EDQl k/gyWHXZ6JuRH4UoBFZKnqv8THdKvVYeFfQu1UWuGXMN6r7RGxTYIUc2YD+Trja9uugz uf4i09nv7gN/e70GQ9Q9J4ZQTS3JSg929ShQ3/sVUPq9SCJOQ85PrSc3IOCAhhHqUavy w4qDVkLc1f29M/MVD/zyjLvoJt3biS77J8jlHGvutwXFgGBFuAZmrC+OxohzWYqOLVV9 weJg== X-Google-DKIM-Signature: v=1; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=bmeng.cn@gmail.com; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 04:22:49 -0000 On Thu, Jan 26, 2023 at 12:23 AM Alexandre Ghiti wrote: > > RISC-V specifies multiple sizes for addressable memory and Linux probes for > the machine's support at startup via the satp CSR register (done in > csr.c:validate_vm). > > As per the specification, sv64 must support sv57, which in turn must > support sv48...etc. So we can restrict machine support by simply setting the > "highest" supported mode and the bare mode is always supported. > > You can set the satp mode using the new properties "sv32", "sv39", "sv48", > "sv57" and "sv64" as follows: > -cpu rv64,sv57=on # Linux will boot using sv57 scheme > -cpu rv64,sv39=on # Linux will boot using sv39 scheme > -cpu rv64,sv57=off # Linux will boot using sv48 scheme > -cpu rv64 # Linux will boot using sv57 scheme by default > > We take the highest level set by the user: > -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme > > We make sure that invalid configurations are rejected: > -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are > # enabled > > We accept "redundant" configurations: > -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme > > And contradictory configurations: > -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme > > Co-Developed-by: Ludovic Henry > Signed-off-by: Ludovic Henry > Signed-off-by: Alexandre Ghiti > --- > target/riscv/cpu.c | 206 +++++++++++++++++++++++++++++++++++++++++++++ > target/riscv/cpu.h | 19 +++++ > target/riscv/csr.c | 12 ++- > 3 files changed, 230 insertions(+), 7 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 7181b34f86..54494a72be 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -27,6 +27,7 @@ > #include "time_helper.h" > #include "exec/exec-all.h" > #include "qapi/error.h" > +#include "qapi/visitor.h" > #include "qemu/error-report.h" > #include "hw/qdev-properties.h" > #include "migration/vmstate.h" > @@ -229,6 +230,81 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) > env->vext_ver = vext_ver; > } > > +static uint8_t satp_mode_from_str(const char *satp_mode_str) > +{ > + if (!strncmp(satp_mode_str, "mbare", 5)) { > + return VM_1_10_MBARE; > + } > + > + if (!strncmp(satp_mode_str, "sv32", 4)) { > + return VM_1_10_SV32; > + } > + > + if (!strncmp(satp_mode_str, "sv39", 4)) { > + return VM_1_10_SV39; > + } > + > + if (!strncmp(satp_mode_str, "sv48", 4)) { > + return VM_1_10_SV48; > + } > + > + if (!strncmp(satp_mode_str, "sv57", 4)) { > + return VM_1_10_SV57; > + } > + > + if (!strncmp(satp_mode_str, "sv64", 4)) { > + return VM_1_10_SV64; > + } > + > + g_assert_not_reached(); > +} > + > +uint8_t satp_mode_max_from_map(uint32_t map) > +{ > + /* map here has at least one bit set, so no problem with clz */ > + return 31 - __builtin_clz(map); > +} > + > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > +{ > + if (is_32_bit) { > + switch (satp_mode) { > + case VM_1_10_SV32: > + return "sv32"; > + case VM_1_10_MBARE: > + return "none"; > + } > + } else { > + switch (satp_mode) { > + case VM_1_10_SV64: > + return "sv64"; > + case VM_1_10_SV57: > + return "sv57"; > + case VM_1_10_SV48: > + return "sv48"; > + case VM_1_10_SV39: > + return "sv39"; > + case VM_1_10_MBARE: > + return "none"; > + } > + } > + > + g_assert_not_reached(); > +} > + > +/* Sets the satp mode to the max supported */ > +static void set_satp_mode_default(RISCVCPU *cpu) This function is better named as set_satp_mode_default_map > +{ > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > + > + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > + cpu->cfg.satp_mode.map |= > + (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); > + } else { > + cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > + } I believe the "mbare" bit should always be set, so this can be: cpu->cfg.satp_mode.map = 1 << satp_mode_from_str("mbare"); if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); > +} > + > static void riscv_any_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > @@ -619,6 +695,82 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > } > } > > +static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > +{ > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > + uint8_t satp_mode_max; > + > + if (cpu->cfg.satp_mode.map == 0) { > + if (cpu->cfg.satp_mode.init == 0) { > + /* If unset by the user, we fallback to the default satp mode. */ > + set_satp_mode_default(cpu); > + } else { > + /* > + * Find the lowest level that was disabled and then enable the > + * first valid level below which can be found in > + * valid_vm_1_10_32/64. > + */ > + for (int i = 1; i < 16; ++i) { > + if ((cpu->cfg.satp_mode.init & (1 << i)) && > + valid_vm[i]) { > + for (int j = i - 1; j >= 0; --j) { > + if (valid_vm[j]) { > + cpu->cfg.satp_mode.map |= (1 << j); > + break; > + } > + } > + break; > + } > + } > + } > + } > + > + /* Make sure the configuration asked is supported by qemu */ > + for (int i = 0; i < 16; ++i) { > + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > + error_setg(errp, "satp_mode %s is not valid", > + satp_mode_str(i, rv32)); > + return; > + } > + } > + > + /* > + * Make sure the user did not ask for an invalid configuration as per > + * the specification. > + */ > + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > + > + if (!rv32) { > + for (int i = satp_mode_max - 1; i >= 0; --i) { > + if (!(cpu->cfg.satp_mode.map & (1 << i)) && > + (cpu->cfg.satp_mode.init & (1 << i)) && > + valid_vm[i]) { > + error_setg(errp, "cannot disable %s satp mode if %s " > + "is enabled", satp_mode_str(i, false), > + satp_mode_str(satp_mode_max, false)); > + return; > + } > + } > + } > + > + /* Finally expand the map so that all valid modes are set */ > + for (int i = satp_mode_max - 1; i >= 0; --i) { > + cpu->cfg.satp_mode.map |= (1 << i); This blindly expands the map regardless whether it's a valid mode. > + } > +} > + > +static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > +{ > + Error *local_err = NULL; > + > + riscv_cpu_satp_mode_finalize(cpu, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > + } > +} > + > static void riscv_cpu_realize(DeviceState *dev, Error **errp) > { > CPUState *cs = CPU(dev); > @@ -919,6 +1071,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > } > #endif > > + riscv_cpu_finalize_features(cpu, &local_err); > + if (local_err != NULL) { > + error_propagate(errp, local_err); > + return; > + } > + > riscv_cpu_register_gdb_regs_for_features(cs); > > qemu_init_vcpu(cs); > @@ -927,6 +1085,52 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > mcc->parent_realize(dev, errp); > } > > +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) nits: should align to ( > +{ > + RISCVSATPMap *satp_map = opaque; > + uint8_t satp = satp_mode_from_str(name); > + bool value; > + > + value = (satp_map->map & (1 << satp)); nits: remove the outer () > + > + visit_type_bool(v, name, &value, errp); > +} > + > +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, > + void *opaque, Error **errp) ditto > +{ > + RISCVSATPMap *satp_map = opaque; > + uint8_t satp = satp_mode_from_str(name); > + bool value; > + > + if (!visit_type_bool(v, name, &value, errp)) { > + return; > + } > + > + satp_map->map = deposit32(satp_map->map, satp, 1, value); > + satp_map->init |= 1 << satp; > +} > + > +static void riscv_add_satp_mode_properties(Object *obj) > +{ > + RISCVCPU *cpu = RISCV_CPU(obj); > + > + if (cpu->env.misa_mxl == MXL_RV32) { > + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + } else { > + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > + } > +} > + > #ifndef CONFIG_USER_ONLY > static void riscv_cpu_set_irq(void *opaque, int irq, int level) > { > @@ -1091,6 +1295,8 @@ static void register_cpu_props(Object *obj) > for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > qdev_property_add_static(dev, prop); > } > + > + riscv_add_satp_mode_properties(obj); > } > > static Property riscv_cpu_properties[] = { > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index f5609b62a2..e37177db5c 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -27,6 +27,7 @@ > #include "qom/object.h" > #include "qemu/int128.h" > #include "cpu_bits.h" > +#include "qapi/qapi-types-common.h" > > #define TCG_GUEST_DEFAULT_MO 0 > > @@ -413,6 +414,17 @@ struct RISCVCPUClass { > ResettablePhases parent_phases; > }; > > +/* > + * map is a 16-bit bitmap: the most significant set bit in map is the maximum > + * satp mode that is supported. > + * > + * init is a 16-bit bitmap used to make sure the user selected a correct > + * configuration as per the specification. > + */ > +typedef struct { > + uint16_t map, init; > +} RISCVSATPMap; > + > struct RISCVCPUConfig { > bool ext_i; > bool ext_e; > @@ -488,6 +500,8 @@ struct RISCVCPUConfig { > bool debug; > > bool short_isa_string; > + > + RISCVSATPMap satp_mode; > }; > > typedef struct RISCVCPUConfig RISCVCPUConfig; > @@ -794,9 +808,14 @@ enum riscv_pmu_event_idx { > /* CSR function table */ > extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; > > +extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; > + > void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); > void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); > > void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); > > +uint8_t satp_mode_max_from_map(uint32_t map); > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); > + > #endif /* RISCV_CPU_H */ > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index 6b157806a5..3c02055825 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -1117,12 +1117,12 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; > static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; > static const target_ulong vsip_writable_mask = MIP_VSSIP; > > -static const bool valid_vm_1_10_32[16] = { > +const bool valid_vm_1_10_32[16] = { > [VM_1_10_MBARE] = true, > [VM_1_10_SV32] = true > }; > > -static const bool valid_vm_1_10_64[16] = { > +const bool valid_vm_1_10_64[16] = { > [VM_1_10_MBARE] = true, > [VM_1_10_SV39] = true, > [VM_1_10_SV48] = true, > @@ -1211,11 +1211,9 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, > > static bool validate_vm(CPURISCVState *env, target_ulong vm) > { > - if (riscv_cpu_mxl(env) == MXL_RV32) { > - return valid_vm_1_10_32[vm & 0xf]; > - } else { > - return valid_vm_1_10_64[vm & 0xf]; > - } > + RISCVCPU *cpu = RISCV_CPU(env_cpu(env)); > + > + return ((vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map)); nits: remove the outer () > } > > static RISCVException write_mstatus(CPURISCVState *env, int csrno, > -- Regards, Bin From MAILER-DAEMON Sun Jan 29 23:29:39 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMLnX-0005aC-I2 for mharc-qemu-riscv@gnu.org; Sun, 29 Jan 2023 23:29:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMLnW-0005Zn-SE; Sun, 29 Jan 2023 23:29:38 -0500 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMLnU-0003WB-Si; Sun, 29 Jan 2023 23:29:38 -0500 Received: by mail-ej1-x631.google.com with SMTP id m2so27822538ejb.8; Sun, 29 Jan 2023 20:29:36 -0800 (PST) DKIM-Signature: v=1; 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Sun, 29 Jan 2023 20:29:34 -0800 (PST) MIME-Version: 1.0 References: <20230125162010.1615787-1-alexghiti@rivosinc.com> <20230125162010.1615787-5-alexghiti@rivosinc.com> In-Reply-To: <20230125162010.1615787-5-alexghiti@rivosinc.com> From: Bin Meng Date: Mon, 30 Jan 2023 12:29:23 +0800 Message-ID: Subject: Re: [PATCH v8 4/5] riscv: Introduce satp mode hw capabilities To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 04:29:39 -0000 On Thu, Jan 26, 2023 at 12:24 AM Alexandre Ghiti wrote: > > Currently, the max satp mode is set with the only constraint that it must be > implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. nits: s/qemu/QEMU/g > > But we actually need to add another level of constraint: what the hw is > actually capable of, because currently, a linux booting on a sifive-u54 > boots in sv57 mode which is incompatible with the cpu's sv39 max > capability. > > So add a new bitmap to RISCVSATPMap which contains this capability and > initialize it in every XXX_cpu_init. > > Finally: > - valid_vm_1_10_[32|64] constrains which satp mode the CPU can use > - the CPU hw capabilities constrains what the user may select > - the user's selection then constrains what's available to the guest > OS. > > Signed-off-by: Alexandre Ghiti > Reviewed-by: Andrew Jones > --- > target/riscv/cpu.c | 74 +++++++++++++++++++++++++++++++--------------- > target/riscv/cpu.h | 8 +++-- > 2 files changed, 56 insertions(+), 26 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 54494a72be..e7e1fb96dc 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -292,26 +292,36 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > g_assert_not_reached(); > } > > -/* Sets the satp mode to the max supported */ > -static void set_satp_mode_default(RISCVCPU *cpu) > +static void set_satp_mode_max_supported(RISCVCPU *cpu, > + uint8_t satp_mode) > { > bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > > - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > - cpu->cfg.satp_mode.map |= > - (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); > - } else { > - cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > + for (int i = 0; i <= satp_mode; ++i) { > + if (valid_vm[i]) { > + cpu->cfg.satp_mode.supported |= (1 << i); > + } > } > } > > +/* Sets the satp mode to the max supported */ nits: s/Sets/Set > +static void set_satp_mode_default(RISCVCPU *cpu) > +{ > + cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; > +} > + > static void riscv_any_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > #if defined(TARGET_RISCV32) > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > + set_satp_mode_max_supported(cpu, VM_1_10_SV32); > #elif defined(TARGET_RISCV64) > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > + set_satp_mode_max_supported(cpu, VM_1_10_SV57); > #endif > set_priv_version(env, PRIV_VERSION_1_12_0); > register_cpu_props(obj); > @@ -321,18 +331,24 @@ static void riscv_any_cpu_init(Object *obj) > static void rv64_base_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > /* We set this in the realise function */ > set_misa(env, MXL_RV64, 0); > register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > + set_satp_mode_max_supported(cpu, VM_1_10_SV57); > } > > static void rv64_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > + set_satp_mode_max_supported(cpu, VM_1_10_SV39); > } > > static void rv64_sifive_e_cpu_init(Object *obj) > @@ -343,6 +359,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > } > > static void rv128_base_cpu_init(Object *obj) > @@ -354,11 +371,13 @@ static void rv128_base_cpu_init(Object *obj) > exit(EXIT_FAILURE); > } > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > /* We set this in the realise function */ > set_misa(env, MXL_RV128, 0); > register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > + set_satp_mode_max_supported(cpu, VM_1_10_SV57); > } > #else > static void rv32_base_cpu_init(Object *obj) > @@ -369,13 +388,17 @@ static void rv32_base_cpu_init(Object *obj) > register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > + set_satp_mode_max_supported(cpu, VM_1_10_SV32); Does this compile? 'cpu' seems undeclared ..? > } > > static void rv32_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > + set_satp_mode_max_supported(cpu, VM_1_10_SV32); > } > > static void rv32_sifive_e_cpu_init(Object *obj) > @@ -386,6 +409,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > } > > static void rv32_ibex_cpu_init(Object *obj) > @@ -396,6 +420,7 @@ static void rv32_ibex_cpu_init(Object *obj) > set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_11_0); > cpu->cfg.mmu = false; > + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > cpu->cfg.epmp = true; > } > > @@ -407,6 +432,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > } > #endif > > @@ -698,8 +724,9 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > { > bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > - const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > - uint8_t satp_mode_max; > + uint8_t satp_mode_map_max; > + uint8_t satp_mode_supported_max = > + satp_mode_max_from_map(cpu->cfg.satp_mode.supported); > > if (cpu->cfg.satp_mode.map == 0) { > if (cpu->cfg.satp_mode.init == 0) { > @@ -713,9 +740,9 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > */ > for (int i = 1; i < 16; ++i) { > if ((cpu->cfg.satp_mode.init & (1 << i)) && > - valid_vm[i]) { > + (cpu->cfg.satp_mode.supported & (1 << i))) { > for (int j = i - 1; j >= 0; --j) { > - if (valid_vm[j]) { > + if (cpu->cfg.satp_mode.supported & (1 << j)) { > cpu->cfg.satp_mode.map |= (1 << j); > break; > } > @@ -726,36 +753,35 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > } > } > > - /* Make sure the configuration asked is supported by qemu */ > - for (int i = 0; i < 16; ++i) { > - if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > - error_setg(errp, "satp_mode %s is not valid", > - satp_mode_str(i, rv32)); > - return; > - } > + satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > + > + /* Make sure the user asked for a supported configuration (HW and qemu) */ > + if (satp_mode_map_max > satp_mode_supported_max) { > + error_setg(errp, "satp_mode %s is higher than hw max capability %s", > + satp_mode_str(satp_mode_map_max, rv32), > + satp_mode_str(satp_mode_supported_max, rv32)); > + return; > } > > /* > * Make sure the user did not ask for an invalid configuration as per > * the specification. > */ > - satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > - > if (!rv32) { > - for (int i = satp_mode_max - 1; i >= 0; --i) { > + for (int i = satp_mode_map_max - 1; i >= 0; --i) { > if (!(cpu->cfg.satp_mode.map & (1 << i)) && > (cpu->cfg.satp_mode.init & (1 << i)) && > - valid_vm[i]) { > + (cpu->cfg.satp_mode.supported & (1 << i))) { > error_setg(errp, "cannot disable %s satp mode if %s " > "is enabled", satp_mode_str(i, false), > - satp_mode_str(satp_mode_max, false)); > + satp_mode_str(satp_mode_map_max, false)); > return; > } > } > } > > /* Finally expand the map so that all valid modes are set */ > - for (int i = satp_mode_max - 1; i >= 0; --i) { > + for (int i = satp_mode_map_max - 1; i >= 0; --i) { > cpu->cfg.satp_mode.map |= (1 << i); > } > } > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index e37177db5c..b591122099 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -416,13 +416,17 @@ struct RISCVCPUClass { > > /* > * map is a 16-bit bitmap: the most significant set bit in map is the maximum > - * satp mode that is supported. > + * satp mode that is supported. It may be chosen by the user and must respect > + * what qemu implements (valid_1_10_32/64) and what the hw is capable of > + * (supported bitmap below). > * > * init is a 16-bit bitmap used to make sure the user selected a correct > * configuration as per the specification. > + * > + * supported is a 16-bit bitmap used to reflect the hw capabilities. > */ > typedef struct { > - uint16_t map, init; > + uint16_t map, init, supported; > } RISCVSATPMap; > > struct RISCVCPUConfig { > -- Regards, Bin From MAILER-DAEMON Sun Jan 29 23:30:36 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMLoR-0006JI-Tc for mharc-qemu-riscv@gnu.org; Sun, 29 Jan 2023 23:30:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMLoP-0006It-1g; Sun, 29 Jan 2023 23:30:34 -0500 Received: from mail-ed1-x534.google.com ([2a00:1450:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMLoN-0003ln-MK; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=bmeng.cn@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 04:30:34 -0000 On Thu, Jan 26, 2023 at 12:25 AM Alexandre Ghiti wrote: > > The 'mmu-type' should reflect what the hardware is capable of so use the > new satp_mode field in RISCVCPUConfig to do that. > > Signed-off-by: Alexandre Ghiti > Reviewed-by: Andrew Jones > Reviewed-by: Alistair Francis > --- > hw/riscv/virt.c | 19 ++++++++++--------- > 1 file changed, 10 insertions(+), 9 deletions(-) > Reviewed-by: Bin Meng From MAILER-DAEMON Mon Jan 30 00:43:57 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMMxR-0005uP-GF for mharc-qemu-riscv@gnu.org; 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Sun, 29 Jan 2023 21:43:51 -0800 (PST) Message-ID: <7f8383f6-e860-5e3e-e89c-dfdac4e05dc5@linaro.org> Date: Sun, 29 Jan 2023 19:43:43 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension To: LIU Zhiwei , Christoph Muellner , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=c3=bcbner?= , Palmer Dabbelt , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang References: <20230124195945.181842-1-christoph.muellner@vrull.eu> <20230124195945.181842-9-christoph.muellner@vrull.eu> <48ff4151-25d9-4b4d-d50a-6516000599c7@linaro.org> <8385d954-678e-d78d-c3ae-d74a4a902907@linux.alibaba.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <8385d954-678e-d78d-c3ae-d74a4a902907@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.092, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 05:43:55 -0000 On 1/29/23 16:03, LIU Zhiwei wrote: > Thanks. It's a bug. We should load all memory addresses to  local TCG temps first. > > Do you think we should probe all the memory addresses for the store pair instructions? If > so, can we avoid the use of a helper function? Depends on what the hardware does. Even with a trap in the middle the stores are restartable, since no register state changes. But if you'd like no changes verifying both stores, for this case you can pack the pair into a larger data type: TCGv_i64 for pair of 32-bit, and TCGv_i128 for pair of 64-bit. Patches for TCGv_i128 [1] are just finishing review; patches to describe atomicity of the larger operation are also on list [2]. Anyway, the idea is that you issue one TCG memory operation, the entire operation is validated, and then the stores happen. > The main reason is that assembler can do this check. Is it necessary to check this in QEMU? Yes. Conciser what happens when the insn is encoded with .long. Does the hardware trap an illegal instruction? Is the behavior simply unspecified? The manual could be improved to specify, akin to the Arm terms: UNDEFINED, CONSTRAINED UNPREDICTABLE, IMPLEMENTATION DEFINED, etc. r~ [1] https://patchew.org/QEMU/20230126043824.54819-1-richard.henderson@linaro.org/ [2] https://patchew.org/QEMU/20221118094754.242910-1-richard.henderson@linaro.org/ From MAILER-DAEMON Mon Jan 30 03:41:40 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMPjQ-0006LS-Gw for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 03:41:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMPjO-00066C-5S; Mon, 30 Jan 2023 03:41:38 -0500 Received: from out30-97.freemail.mail.aliyun.com ([115.124.30.97]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMPjJ-0006v8-7j; Mon, 30 Jan 2023 03:41:37 -0500 X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R381e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018045170; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=14; SR=0; TI=SMTPD_---0VaQTWCF_1675068080; Received: from 30.221.97.63(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0VaQTWCF_1675068080) by smtp.aliyun-inc.com; Mon, 30 Jan 2023 16:41:21 +0800 Content-Type: multipart/alternative; boundary="------------R9GyhGRl0ph5OT0O0r2XcIHp" Message-ID: <82e49515-512f-9439-ceab-6c5df3bb20e4@linux.alibaba.com> Date: Mon, 30 Jan 2023 16:41:05 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension Content-Language: en-US To: Richard Henderson , Christoph Muellner , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=c3=bcbner?= , Palmer Dabbelt , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang References: <20230124195945.181842-1-christoph.muellner@vrull.eu> <20230124195945.181842-9-christoph.muellner@vrull.eu> <48ff4151-25d9-4b4d-d50a-6516000599c7@linaro.org> <8385d954-678e-d78d-c3ae-d74a4a902907@linux.alibaba.com> <7f8383f6-e860-5e3e-e89c-dfdac4e05dc5@linaro.org> From: LIU Zhiwei In-Reply-To: <7f8383f6-e860-5e3e-e89c-dfdac4e05dc5@linaro.org> Received-SPF: pass client-ip=115.124.30.97; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-97.freemail.mail.aliyun.com X-Spam_score_int: -99 X-Spam_score: -10.0 X-Spam_bar: ---------- X-Spam_report: (-10.0 / 5.0 requ) BAYES_00=-1.9, ENV_AND_HDR_SPF_MATCH=-0.5, HTML_MESSAGE=0.001, NICE_REPLY_A=-0.092, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 08:41:38 -0000 This is a multi-part message in MIME format. --------------R9GyhGRl0ph5OT0O0r2XcIHp Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 2023/1/30 13:43, Richard Henderson wrote: > On 1/29/23 16:03, LIU Zhiwei wrote: >> Thanks. It's a bug. We should load all memory addresses to  local TCG >> temps first. >> >> Do you think we should probe all the memory addresses for the store >> pair instructions? If so, can we avoid the use of a helper function? > > Depends on what the hardware does.  Even with a trap in the middle the > stores are restartable, since no register state changes. I refer to the specification of LDP and STP on AARCH64. The specification allows "any access performed before the exception was taken is repeated". In detailed, "If, according to these rules, an instruction is executed as a sequence of accesses, exceptions, including interrupts, can be taken during that sequence, regardless of the memory type being accessed. If any of these exceptions are returned from using their preferred return address, the instruction that generated the sequence of accesses is re-executed, and so any access performed before the exception was taken is repeated. See also Taking an interrupt during a multi-access load or store on page D1-4664." However I see the implementation of LDP and STP on QEMU are in different ways. LDP will only load the first register when it ensures no trap in the second access. So I have two questions here. 1) One for the QEMU implementation about LDP. Can we implement the LDP as two directly loads to cpu registers instead of local TCG temps? 2) One for the comment. Why register state changes cause non-restartable? Do you mean if the first register changes, it may influence the calculation of address after the trap? "Even with a trap in the middle the stores are restartable, since no register state changes." > > But if you'd like no changes verifying both stores, for this case you > can pack the pair into a larger data type: TCGv_i64 for pair of > 32-bit, and TCGv_i128 for pair of 64-bit. > Patches for TCGv_i128 [1] are just finishing review; patches to > describe atomicity of the larger operation are also on list [2]. > Anyway, the idea is that you issue one TCG memory operation, the > entire operation is validated, and then the stores happen. > > >> The main reason is that assembler can do this check. Is it necessary >> to check this in QEMU? > > Yes.  Conciser what happens when the insn is encoded with .long. Does > the hardware trap an illegal instruction?  Is the behavior simply > unspecified?  The manual could be improved to specify, akin to the Arm > terms: UNDEFINED, CONSTRAINED UNPREDICTABLE, IMPLEMENTATION DEFINED, etc. > > Thanks, I will fix the manual. Best Regards, Zhiwei > r~ > > [1] > https://patchew.org/QEMU/20230126043824.54819-1-richard.henderson@linaro.org/ > [2] > https://patchew.org/QEMU/20221118094754.242910-1-richard.henderson@linaro.org/ --------------R9GyhGRl0ph5OT0O0r2XcIHp Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 8bit


On 2023/1/30 13:43, Richard Henderson wrote:
On 1/29/23 16:03, LIU Zhiwei wrote:
Thanks. It's a bug. We should load all memory addresses to  local TCG temps first.

Do you think we should probe all the memory addresses for the store pair instructions? If so, can we avoid the use of a helper function?

Depends on what the hardware does.  Even with a trap in the middle the stores are restartable, since no register state changes.

I refer to the specification of LDP and STP on AARCH64. The specification allows

"any access performed before the exception was taken is repeated".

In detailed,
"If, according to these rules, an instruction is executed as a sequence of accesses, exceptions, including interrupts,
can be taken during that sequence, regardless of the memory type being accessed. If any of these exceptions are
returned from using their preferred return address, the instruction that generated the sequence of accesses is
re-executed, and so any access performed before the exception was taken is repeated. See also Taking an interrupt
during a multi-access load or store on page D1-4664."

However I see the implementation of LDP and STP on QEMU are in different ways. LDP will only load the first register when it ensures no trap in the second access.

So I have two questions here.

1) One for the QEMU implementation about LDP. Can we implement the LDP as two directly loads to cpu registers instead of local TCG temps?

2) One for the comment. Why register state changes cause non-restartable? Do you mean if the first register changes, it may influence the calculation of address after the trap?

"Even with a trap in the middle the stores are restartable, since no register state changes."


But if you'd like no changes verifying both stores, for this case you can pack the pair into a larger data type: TCGv_i64 for pair of 32-bit, and TCGv_i128 for pair of 64-bit.
Patches for TCGv_i128 [1] are just finishing review; patches to describe atomicity of the larger operation are also on list [2]. Anyway, the idea is that you issue one TCG memory operation, the entire operation is validated, and then the stores happen.


The main reason is that assembler can do this check. Is it necessary to check this in QEMU?

Yes.  Conciser what happens when the insn is encoded with .long.  Does the hardware trap an illegal instruction?  Is the behavior simply unspecified?  The manual could be improved to specify, akin to the Arm terms: UNDEFINED, CONSTRAINED UNPREDICTABLE, IMPLEMENTATION DEFINED, etc.


Thanks, I will fix the manual.

Best Regards,
Zhiwei

r~

[1] https://patchew.org/QEMU/20230126043824.54819-1-richard.henderson@linaro.org/
[2] https://patchew.org/QEMU/20221118094754.242910-1-richard.henderson@linaro.org/
--------------R9GyhGRl0ph5OT0O0r2XcIHp-- From MAILER-DAEMON Mon Jan 30 04:04:45 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMQ5l-0007Ew-17 for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 04:04:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMQ5f-0007EH-6K; Mon, 30 Jan 2023 04:04:40 -0500 Received: from out30-1.freemail.mail.aliyun.com ([115.124.30.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMQ5b-0002Cm-WA; Mon, 30 Jan 2023 04:04:38 -0500 X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R141e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018045168; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=14; SR=0; TI=SMTPD_---0VaR58Jo_1675069464; Received: from 30.221.97.63(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0VaR58Jo_1675069464) by smtp.aliyun-inc.com; Mon, 30 Jan 2023 17:04:25 +0800 Message-ID: <3dc36bdc-97df-9ba5-ee12-3a9b5f7793d3@linux.alibaba.com> Date: Mon, 30 Jan 2023 17:04:08 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v3 09/14] RISC-V: Adding T-Head MemIdx extension Content-Language: en-US To: Richard Henderson , Christoph Muellner , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=c3=bcbner?= , Palmer Dabbelt , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang References: <20230124195945.181842-1-christoph.muellner@vrull.eu> <20230124195945.181842-10-christoph.muellner@vrull.eu> <3d864ae7-5430-8db9-f91c-fd24f428b04d@linaro.org> From: LIU Zhiwei In-Reply-To: <3d864ae7-5430-8db9-f91c-fd24f428b04d@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=115.124.30.1; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-1.freemail.mail.aliyun.com X-Spam_score_int: -99 X-Spam_score: -10.0 X-Spam_bar: ---------- X-Spam_report: (-10.0 / 5.0 requ) BAYES_00=-1.9, ENV_AND_HDR_SPF_MATCH=-0.5, NICE_REPLY_A=-0.092, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 09:04:42 -0000 On 2023/1/25 5:21, Richard Henderson wrote: > On 1/24/23 09:59, Christoph Muellner wrote: >> +/* XTheadMemIdx */ >> + >> +/* >> + * Load with memop from indexed address and add (imm5 << imm2) to rs1. >> + * If !preinc, then the load address is rs1. >> + * If  preinc, then the load address is rs1 + (imm5) << imm2). >> + */ >> +static bool gen_load_inc(DisasContext *ctx, arg_th_meminc *a, MemOp >> memop, >> +                         bool preinc) >> +{ >> +    TCGv rd = dest_gpr(ctx, a->rd); >> +    TCGv addr = get_address(ctx, a->rs1, preinc ? a->imm5 << a->imm2 >> : 0); >> + >> +    tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); >> +    addr = get_address(ctx, a->rs1, !preinc ? a->imm5 << a->imm2 : 0); > > First, you're leaking the previous 'addr' temporary. Although all temps allocated by temp_new() will be freed after the instruction translation automatically, we can improve current implementation. > Second, get_address may make modifications to 'addr' which you don't > want to write back. Good catch. > Third, you are not checking for rd != rs1. Yes. > > I think what you want is > >     int imm = a->imm5 << a->imm2; >     TCGv addr = get_address(ctx, a->rs1, preinc ? imm : 0); >     TCGv rd = dest_gpr(ctx, a->rd); >     TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE); > >     tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); >     tcg_gen_addi_tl(rs1, rs1, imm); >     gen_set_gpr(ctx, a->rd, rd); >     gen_set_gpr(ctx, a->rs1, rs1); Yes, we should write back the 'addr' without modification. Best Regards, Zhiwei > > > r~ From MAILER-DAEMON Mon Jan 30 04:07:37 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMQ8W-0008OW-F4 for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 04:07:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMQ7p-0008Hj-4D; Mon, 30 Jan 2023 04:06:53 -0500 Received: from out30-6.freemail.mail.aliyun.com ([115.124.30.6]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMQ7m-0002XS-2t; Mon, 30 Jan 2023 04:06:51 -0500 X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R161e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046056; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=14; SR=0; TI=SMTPD_---0VaRafXj_1675069602; Received: from 30.221.97.63(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0VaRafXj_1675069602) by smtp.aliyun-inc.com; Mon, 30 Jan 2023 17:06:43 +0800 Message-ID: <9d672153-609e-a8f5-31b6-218f2398f10b@linux.alibaba.com> Date: Mon, 30 Jan 2023 17:06:27 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v3 12/14] RISC-V: Add initial support for T-Head C906 Content-Language: en-US To: Richard Henderson , Christoph Muellner , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=c3=bcbner?= , Palmer Dabbelt , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang References: <20230124195945.181842-1-christoph.muellner@vrull.eu> <20230124195945.181842-13-christoph.muellner@vrull.eu> <64af1437-b910-e5b3-c462-0ef0c416ba39@linaro.org> From: LIU Zhiwei In-Reply-To: <64af1437-b910-e5b3-c462-0ef0c416ba39@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=115.124.30.6; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-6.freemail.mail.aliyun.com X-Spam_score_int: -99 X-Spam_score: -10.0 X-Spam_bar: ---------- X-Spam_report: (-10.0 / 5.0 requ) BAYES_00=-1.9, ENV_AND_HDR_SPF_MATCH=-0.5, NICE_REPLY_A=-0.092, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 09:07:13 -0000 On 2023/1/25 5:26, Richard Henderson wrote: > On 1/24/23 09:59, Christoph Muellner wrote: >> +++ b/target/riscv/cpu.h >> @@ -27,6 +27,7 @@ >>   #include "qom/object.h" >>   #include "qemu/int128.h" >>   #include "cpu_bits.h" >> +#include "cpu_vendorid.h" > > I don't see that this ID is required for all users of riscv/cpu.h. > This include should be limited to cpu.c. > OK. We can move it to cpu.c Best Regards, Zhiwei > > r~ From MAILER-DAEMON Mon Jan 30 05:08:20 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMR5I-0007UT-8K for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 05:08:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMR56-0007T7-Qy; Mon, 30 Jan 2023 05:08:14 -0500 Received: from mail-ej1-x62b.google.com ([2a00:1450:4864:20::62b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMR55-0004RN-69; Mon, 30 Jan 2023 05:08:08 -0500 Received: by mail-ej1-x62b.google.com with SMTP id p26so18923200ejx.13; Mon, 30 Jan 2023 02:08:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=6KLMCo5biRiC7s1o2u7KTvaufRUzTlqDNiiarYgvWeM=; b=BzByR55tE0uOEQiY12DWDyfoTa2a4Z/wa9jqZ3qZG7mOjrUQ0odXQUELqpRAFT9+xq zK63uj3qoZ8khVOSOEbx37NsLx2k4xLsg7EvDmnonq1THAX4wpocxVGTrmp2Nu+1DQV0 CzGNMDyF+Hhkq1XCuYOT8Ie7zAvPDvUY+H+exrV1iOIFKCq5/TcnXwowFLa3poD9iDVL +m/3iQrRpP4PfWhvgehkXZ0BO0iS+cmhbUa8M8ZPH1uNwQvOrbxMWyFYM5KIfOedwzME u0Y3nF9xSQ2s2CR7vgVUoUSkmxgzGf+MQv2BcycXn2OqtT6oDPG0jF8eIhMc5GB/WHY5 kO+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=6KLMCo5biRiC7s1o2u7KTvaufRUzTlqDNiiarYgvWeM=; b=A358TbXTLbgHK2cVxiNYMFOFPA0gCKAJrNsln43GYrxK1LBxHPpRZ4RehbSCFB/KiN 8nyTqci++tovc2UDNTuIqKzsuclZ9aShfjSEbTWwBF2XXbg+g2YRjKW7+OrwiWS3Jzp4 6gvkIgCi65asVGZrpsWjObayTEybHxkKLsvPmVXQY6SPAjelqAhcYNpXrUJMq+5n6wXQ QI9vr1av/MxRZ9do10IFksT+tNx865kH7MaG8BWSjN4K0Elkgi5l1LFZPqtcC9MqWoNC s/Tw4lVI/rRGuZGd/zfHktCOXOirzhH+Qqumg+OgJYivZ2vfojkqCFgSsulZHe/xXfFn LcRw== X-Gm-Message-State: AO0yUKV4Hu4tZpgXJABXbXyFuiCZyDfv48nvINVdL2IlMkQrAfe+gY7y hwTrpNKRTgKf+O6+WBo6Is6VdgQlFF6SQaKZ X-Google-Smtp-Source: AK7set9YyjbWy6OW1oJO5WXZnAhO6TIXUaZhiBn+YCL2/c/e+GKMGLNSkW5VsZDNNqHcDlng8S3sTQ== X-Received: by 2002:a17:906:d8c4:b0:87f:546d:7cb5 with SMTP id re4-20020a170906d8c400b0087f546d7cb5mr9990632ejb.37.1675073284752; Mon, 30 Jan 2023 02:08:04 -0800 (PST) Received: from localhost.localdomain ([80.211.22.60]) by smtp.googlemail.com with ESMTPSA id y11-20020a50eb0b000000b00467481df198sm6562461edp.48.2023.01.30.02.08.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 02:08:03 -0800 (PST) From: Sergey Matyukevich To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Sergey Matyukevich Subject: [PATCH] target/riscv: set tval for triggered watchpoints Date: Mon, 30 Jan 2023 13:07:57 +0300 Message-Id: <20230130100757.721372-1-geomatsi@gmail.com> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62b; envelope-from=geomatsi@gmail.com; helo=mail-ej1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 10:08:14 -0000 From: Sergey Matyukevich According to priviledged spec, if [sm]tval is written with a nonzero value when a breakpoint exception occurs, then [sm]tval will contain the faulting virtual address. Set tval to hit address when breakpoint exception is triggered by hardware watchpoint. Signed-off-by: Sergey Matyukevich --- target/riscv/cpu_helper.c | 3 +++ target/riscv/debug.c | 1 + 2 files changed, 4 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9a28816521..d3be8c0511 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1641,6 +1641,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: tval = env->bins; break; + case RISCV_EXCP_BREAKPOINT: + tval = env->badaddr; + break; default: break; } diff --git a/target/riscv/debug.c b/target/riscv/debug.c index bf4840a6a3..48ef3c59ea 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -761,6 +761,7 @@ void riscv_cpu_debug_excp_handler(CPUState *cs) if (cs->watchpoint_hit) { if (cs->watchpoint_hit->flags & BP_CPU) { + env->badaddr = cs->watchpoint_hit->hitaddr; cs->watchpoint_hit = NULL; do_trigger_action(env, DBG_ACTION_BP); } -- 2.39.0 From MAILER-DAEMON Mon Jan 30 06:38:26 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMSUU-00080l-8Z for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 06:38:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMSUT-000801-4A for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 06:38:25 -0500 Received: from imap5.colo.codethink.co.uk ([78.40.148.171]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMSUQ-0002Gl-Em for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 06:38:24 -0500 Received: from [78.40.148.178] (helo=webmail.codethink.co.uk) by imap5.colo.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pMSUH-002RNM-2F; Mon, 30 Jan 2023 11:38:13 +0000 MIME-Version: 1.0 Date: Mon, 30 Jan 2023 11:38:13 +0000 From: Lawrence Hunter To: Alistair Francis Cc: philipp.tomsich@vrull.eu, frank.chang@sifive.com, dickon.hood@codethink.co.uk, qemu-riscv@nongnu.org, palmer@dabbelt.com, kvm@vger.kernel.org, pbonzini@redhat.com, bin.meng@windriver.com Subject: Re: Fwd: [RFC PATCH 00/39] Add RISC-V cryptography extensions standardisation In-Reply-To: <606a3bcc7c7428d2504d2c60055e76255454c558.camel@wdc.com> References: <20230119143528.1290950-1-lawrence.hunter@codethink.co.uk> <380600FF-17AC-4134-85C7-CBDF6E34F0E2@getmailspring.com> <606a3bcc7c7428d2504d2c60055e76255454c558.camel@wdc.com> Message-ID: X-Sender: lawrence.hunter@codethink.co.uk Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=78.40.148.171; envelope-from=lawrence.hunter@codethink.co.uk; helo=imap5.colo.codethink.co.uk X-Spam_score_int: -13 X-Spam_score: -1.4 X-Spam_bar: - X-Spam_report: (-1.4 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URI_NOVOWEL=0.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 11:38:25 -0000 On 2023-01-29 22:23, Alistair Francis wrote: > On Sun, 2023-01-29 at 23:12 +0100, Philipp Tomsich wrote: >> >> >> On Sun, 29 Jan 2023 at 23:08, Alistair Francis >> wrote: >> > On Thu, 2023-01-26 at 09:21 +0000, Lawrence Hunter wrote: >> > > Follow up for add RISC-V vector cryptography extensions >> > > standardisation >> > > RFC: we've not received any comments and would like to move this >> > > series >> > > towards getting merged. Does anyone have time to review it, and >> > > should >> > > we look at resubmitting for merging soon? >> > >> > Hello, >> > >> > This series never made it to the QEMU list. It looks like it was >> > never >> > sent to the general qemu-devel mailing list. >> > >> >> >> This has so far been more than a little painful for our review, as we >> can't just pull the patches down from patchwork to use our regular >> test-and-review flow. >> Should we wait until the resubmission for our review? We have pushed a branch 'rfc-zvk-19-01-23' with our commits based on a fairly recent master. Hopefully this will ease the review process. https://github.com/CodethinkLabs/qemu-ct.git > > Up to you. It won't be merged unless it has been sent to the general > mailing list, so you can either get a head start or just wait. > >> >> Note that the current series is not in-sync with the latest >> specification. > > It's only an RFC, so for now that's ok as it won't be merged anyway. > > Alistair > >> We'll try to point out the specific deviations (we have a tree that >> we've been keeping in sync with the changes to the spec since mid- >> December) in our reviews. >> >> Cheers, >> Philipp. >>   >> > When submitting patches can you please follow the steps here: >> > https://www.qemu.org/docs/master/devel/submitting-a-patch.html#submitting-your-patches >> > >> > It's important that all patches are sent to the qemu-devel mailing >> > list >> > (that's actually much more important then the RISC-V mailing list). >> > >> > Alistair >> > >> > > >> > > ---------- Forwarded Message --------- >> > > >> > > From: Lawrence Hunter >> > > Subject: [RFC PATCH 00/39] Add RISC-V cryptography extensions >> > > standardisation >> > > Date: Jan 19 2023, at 2:34 pm >> > > To: qemu-riscv@nongnu.org >> > > Cc: dickon.hood@codethink.co.uk, frank.chang@sifive.com, Lawrence >> > > Hunter >> > > >> > > >> > > > This RFC introduces an implementation for the six instruction >> > > > sets >> > > > of the draft RISC-V cryptography extensions standardisation >> > > > specification. Once the specification has been ratified we will >> > > > submit >> > > > these changes as a pull request email to this mailing list. >> > > > Would >> > > > this >> > > > be prefered by instruction group or unified as in this RFC? >> > > > >> > > > This patch set implements the instruction sets as per the >> > > > 20221202 >> > > > version of the specification (1). >> > > > >> > > > Work performed by Dickon, Lawrence, Nazar, Kiran, and William >> > > > from >> > > > Codethink >> > > > sponsored by SiFive, and Max Chou from SiFive. >> > > > >> > > > 1. https://github.com/riscv/riscv-crypto/releases >> > > > >> > > > Dickon Hood (1): >> > > >  target/riscv: Add vrol.[vv,vx] and vror.[vv,vx,vi] decoding, >> > > >    translation and execution support >> > > > >> > > > Kiran Ostrolenk (4): >> > > >  target/riscv: Add vsha2ms.vv decoding, translation and >> > > > execution >> > > >    support >> > > >  target/riscv: add zvksh cpu property >> > > >  target/riscv: Add vsm3c.vi decoding, translation and execution >> > > > support >> > > >  target/riscv: expose zvksh cpu property >> > > > >> > > > Lawrence Hunter (16): >> > > >  target/riscv: Add vclmul.vv decoding, translation and >> > > > execution >> > > >    support >> > > >  target/riscv: Add vclmul.vx decoding, translation and >> > > > execution >> > > >    support >> > > >  target/riscv: Add vclmulh.vv decoding, translation and >> > > > execution >> > > >    support >> > > >  target/riscv: Add vclmulh.vx decoding, translation and >> > > > execution >> > > >    support >> > > >  target/riscv: Add vaesef.vv decoding, translation and >> > > > execution >> > > >    support >> > > >  target/riscv: Add vaesef.vs decoding, translation and >> > > > execution >> > > >    support >> > > >  target/riscv: Add vaesdf.vv decoding, translation and >> > > > execution >> > > >    support >> > > >  target/riscv: Add vaesdf.vs decoding, translation and >> > > > execution >> > > >    support >> > > >  target/riscv: Add vaesdm.vv decoding, translation and >> > > > execution >> > > >    support >> > > >  target/riscv: Add vaesdm.vs decoding, translation and >> > > > execution >> > > >    support >> > > >  target/riscv: Add vaesz.vs decoding, translation and execution >> > > > support >> > > >  target/riscv: Add vsha2c[hl].vv decoding, translation and >> > > > execution >> > > >    support >> > > >  target/riscv: Add vsm3me.vv decoding, translation and >> > > > execution >> > > >    support >> > > >  target/riscv: add zvkg cpu property >> > > >  target/riscv: Add vghmac.vv decoding, translation and >> > > > execution >> > > >    support >> > > >  target/riscv: expose zvkg cpu property >> > > > >> > > > Max Chou (5): >> > > >  crypto: Move SM4_SBOXWORD from target/riscv >> > > >  crypto: Add SM4 constant parameter CK. >> > > >  target/riscv: Add zvksed cfg property >> > > >  target/riscv: Add Zvksed support >> > > >  target/riscv: Expose Zvksed property >> > > > >> > > > Nazar Kazakov (10): >> > > >  target/riscv: add zvkb cpu property >> > > >  target/riscv: Add vrev8.v decoding, translation and execution >> > > > support >> > > >  target/riscv: Add vandn.[vv,vx,vi] decoding, translation and >> > > > execution >> > > >    support >> > > >  target/riscv: expose zvkb cpu property >> > > >  target/riscv: add zvkns cpu property >> > > >  target/riscv: Add vaeskf1.vi decoding, translation and >> > > > execution >> > > >    support >> > > >  target/riscv: Add vaeskf2.vi decoding, translation and >> > > > execution >> > > >    support >> > > >  target/riscv: expose zvkns cpu property >> > > >  target/riscv: add zvknh cpu properties >> > > >  target/riscv: expose zvknh cpu properties >> > > > >> > > > William Salmon (3): >> > > >  target/riscv: Add vbrev8.v decoding, translation and execution >> > > > support >> > > >  target/riscv: Add vaesem.vv decoding, translation and >> > > > execution >> > > >    support >> > > >  target/riscv: Add vaesem.vs decoding, translation and >> > > > execution >> > > >    support >> > > > >> > > > crypto/sm4.c                                 |   10 + >> > > > include/crypto/sm4.h                         |    8 + >> > > > include/qemu/bitops.h                        |   32 + >> > > > target/arm/crypto_helper.c                   |   10 +- >> > > > target/riscv/cpu.c                           |   15 + >> > > > target/riscv/cpu.h                           |    7 + >> > > > target/riscv/crypto_helper.c                 |    1 + >> > > > target/riscv/helper.h                        |   69 ++ >> > > > target/riscv/insn32.decode                   |   48 + >> > > > target/riscv/insn_trans/trans_rvzvkb.c.inc   |  164 +++ >> > > > target/riscv/insn_trans/trans_rvzvkg.c.inc   |    8 + >> > > > target/riscv/insn_trans/trans_rvzvknh.c.inc  |   47 + >> > > > target/riscv/insn_trans/trans_rvzvkns.c.inc  |  121 +++ >> > > > target/riscv/insn_trans/trans_rvzvksed.c.inc |   38 + >> > > > target/riscv/insn_trans/trans_rvzvksh.c.inc  |   20 + >> > > > target/riscv/meson.build                     |    4 +- >> > > > target/riscv/translate.c                     |    6 + >> > > > target/riscv/vcrypto_helper.c                | 1013 >> > > > ++++++++++++++++++ >> > > > target/riscv/vector_helper.c                 |  242 +---- >> > > > target/riscv/vector_internals.c              |   63 ++ >> > > > target/riscv/vector_internals.h              |  226 ++++ >> > > > 21 files changed, 1902 insertions(+), 250 deletions(-) >> > > > create mode 100644 target/riscv/insn_trans/trans_rvzvkb.c.inc >> > > > create mode 100644 target/riscv/insn_trans/trans_rvzvkg.c.inc >> > > > create mode 100644 target/riscv/insn_trans/trans_rvzvknh.c.inc >> > > > create mode 100644 target/riscv/insn_trans/trans_rvzvkns.c.inc >> > > > create mode 100644 target/riscv/insn_trans/trans_rvzvksed.c.inc >> > > > create mode 100644 target/riscv/insn_trans/trans_rvzvksh.c.inc >> > > > create mode 100644 target/riscv/vcrypto_helper.c >> > > > create mode 100644 target/riscv/vector_internals.c >> > > > create mode 100644 target/riscv/vector_internals.h >> > > > >> > > > -- >> > > > 2.39.1 >> > > > >> > > > >> > > > >> > From MAILER-DAEMON Mon Jan 30 07:56:06 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMTha-0000iz-3j for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 07:56:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMThX-0000iA-KN for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 07:56:00 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMThW-0000is-2p for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 07:55:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1675083357; 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Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 5B7922166B26; Mon, 30 Jan 2023 12:55:49 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 467DE21E6A1F; Mon, 30 Jan 2023 13:55:48 +0100 (CET) From: Markus Armbruster To: "Michael S. Tsirkin" Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 01/19] scripts/clean-includes: Fully skip / ignore files References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-2-armbru@redhat.com> <20230128052749-mutt-send-email-mst@kernel.org> Date: Mon, 30 Jan 2023 13:55:48 +0100 In-Reply-To: <20230128052749-mutt-send-email-mst@kernel.org> (Michael S. Tsirkin's message of "Sat, 28 Jan 2023 05:28:26 -0500") Message-ID: <87r0vcb2qz.fsf@pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Scanned-By: MIMEDefang 3.1 on 10.11.54.6 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 12:56:00 -0000 "Michael S. Tsirkin" writes: > On Thu, Jan 19, 2023 at 07:59:41AM +0100, Markus Armbruster wrote: >> When clean-includes claims to skip or ignore a file, only the part >> that sanitizes use of qemu/osdep.h skips the file. The part that >> looks for duplicate #include does not, and neither does committing to >> Git. >> >> The latter can get unrelated stuff included in the commit, but only if >> you run clean-includes in a dirty tree, which is unwise. Messed up >> when we added skipping in commit fd3e39a40c "scripts/clean-includes: >> Enhance to handle header files". >> >> The former can cause bogus reports for --check-dup-head. Added in >> commit d66253e46a "scripts/clean-includes: added duplicate #include >> check", duplicating the prior mistake. >> >> Fix the script to fully skip files. >> >> Fixes: fd3e39a40ca2ee26b09a5de3149af8b056b85233 >> Fixes: d66253e46ae2b9c36a9dd90b2b74c0dfa5804b22 > > Isn't > Fixes: %h (\"%s\") > > the accepted format for this? It seems to be common these days. I'll adjust. From MAILER-DAEMON Mon Jan 30 08:12:37 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMTxd-0007eY-CR for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 08:12:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMTxc-0007e3-2c for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:12:36 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMTxa-00046F-JH for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:12:35 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1675084353; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=l077ML8x2aUA3BfSYxSnF/pmWEsvNiSwJ/mn/qtcnMc=; b=OvuyTKh3KyRzid59vaBPaeViSPd2AFlrUmr2I5luZTGkShYnwD1DvCwrl2SFKVYvjpsIif AWr6EeKa90rVO3nKWRHlLrd/5X+hkXkxJelamnPevhE9+1PzNjvRWKJT6bZLg83h+LCLcJ OlE+jmIJTB0wtMe0vdASLNPvnBFapXM= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-532-iyGpN8YgPiKfsf49FspL_w-1; Mon, 30 Jan 2023 08:12:30 -0500 X-MC-Unique: iyGpN8YgPiKfsf49FspL_w-1 Received: from smtp.corp.redhat.com (int-mx09.intmail.prod.int.rdu2.redhat.com [10.11.54.9]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 9DD93100F90A; Mon, 30 Jan 2023 13:12:29 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 629F7492B05; Mon, 30 Jan 2023 13:12:29 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 6783421E6A1F; Mon, 30 Jan 2023 14:12:28 +0100 (CET) From: Markus Armbruster To: "Michael S. Tsirkin" Cc: Peter Maydell , Warner Losh , qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, philmd@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v4 04/19] bsd-user: Clean up includes References: <20230119065959.3104012-1-armbru@redhat.com> <20230119065959.3104012-5-armbru@redhat.com> <20230127100052-mutt-send-email-mst@kernel.org> <20230128052729-mutt-send-email-mst@kernel.org> Date: Mon, 30 Jan 2023 14:12:28 +0100 In-Reply-To: <20230128052729-mutt-send-email-mst@kernel.org> (Michael S. Tsirkin's message of "Sat, 28 Jan 2023 05:29:47 -0500") Message-ID: <87mt60b1z7.fsf@pond.sub.org> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain X-Scanned-By: MIMEDefang 3.1 on 10.11.54.9 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:12:36 -0000 "Michael S. Tsirkin" writes: > On Fri, Jan 27, 2023 at 10:01:57AM -0500, Michael S. Tsirkin wrote: >> On Fri, Jan 27, 2023 at 02:54:30PM +0000, Peter Maydell wrote: >> > On Thu, 19 Jan 2023 at 14:42, Warner Losh wrote: >> > > >> > > Also, why didn't you move sys/resource.h and other such files >> > > to os-dep.h? I'm struggling to understand the rules around what >> > > is or isn't included where? >> > >> > The rough rule of thumb is that if some OS needs a compatibility >> > fixup or workaround for a system header (eg not every mmap.h >> > defines MAP_ANONYMOUS; on Windows unistd.h has to come before >> > time.h) then we put that header include and the compat workaround >> > into osdep.h. This avoids "only fails on obscure platform" issues >> > where somebody puts a header include into some specific .c file >> > but not the compat workaround, and it works on the Linux host >> > that most people develop and test on and we only find the >> > problem later. >> > >> > There's also no doubt some includes there for historical >> > reasons, and some which really are "everybody needs these" >> > convenience ones. But we should probably not add new >> > includes to osdep.h unless they fall into the "working around >> > system header issues" bucket. >> > >> > thanks >> > -- PMM >> >> >> BTW maybe we should teach checkpatch about that rule: >> if a header is in osdep do not include it directly. > > To be more precise, make checkpatch run clean-includes somehow? > Or just make CI run clean-includes on the tree and verify result > is empty? scripts/clean-includes isn't quite happy even after my series. Offenders: ebpf/rss.bpf.skeleton.h subprojects/libvduse/libvduse.h subprojects/libvhost-user/libvhost-user-glib.h subprojects/libvhost-user/libvhost-user.h target/hexagon/idef-parser/idef-parser.h target/hexagon/idef-parser/parser-helpers.h tests/fp/platform.h contrib/plugins/cache.c contrib/plugins/drcov.c contrib/plugins/execlog.c contrib/plugins/hotblocks.c contrib/plugins/hotpages.c contrib/plugins/howvec.c contrib/plugins/hwprofile.c contrib/plugins/lockstep.c linux-user/mips64/cpu_loop.c linux-user/mips64/signal.c linux-user/x86_64/cpu_loop.c linux-user/x86_64/signal.c plugins/core.c plugins/loader.c scripts/xen-detect.c subprojects/libvduse/libvduse.c subprojects/libvhost-user/libvhost-user-glib.c subprojects/libvhost-user/libvhost-user.c subprojects/libvhost-user/link-test.c target/hexagon/gen_dectree_import.c target/hexagon/gen_semantics.c target/hexagon/idef-parser/parser-helpers.c target/s390x/gen-features.c tests/migration/s390x/a-b-bios.c tests/plugin/bb.c tests/plugin/empty.c tests/plugin/insn.c tests/plugin/mem.c tests/plugin/syscall.c tests/uefi-test-tools/UefiTestToolsPkg/BiosTablesTest/BiosTablesTest.c tests/unit/test-rcu-simpleq.c tests/unit/test-rcu-slist.c tests/unit/test-rcu-tailq.c tools/ebpf/rss.bpf.c To support automatic checking, we'd have to fix the ones that need need fixing, and add the remainder to the script's XDIRREGEX. From MAILER-DAEMON Mon Jan 30 08:22:16 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMU6x-0004c4-Ne for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 08:22:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6q-0004G4-Pu for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:10 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6l-0005iR-8U for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1675084922; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=DJiHbzsUPbzscCIZ93jw6C9YFJo0iZODwW3q92R4LoU=; b=XidInL+RUGfS6kLIN//KJ+mvVuJbWkaweux/wGtyDgR5YYSFoVqjkDHUQ5LfPHI7tg+kTL 6964kRP7emd3N0Bl92PDp0Vz2Zj8r3AoPJrjbfiai1FIZDJ1jNpjCYyNDCQYFDn0nxl2gq 7yycn7M3rbAATvY282jFogn3CKr5Qmg= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-75-eMNRH04WOKGCe40U5o3sAQ-1; Mon, 30 Jan 2023 08:21:58 -0500 X-MC-Unique: eMNRH04WOKGCe40U5o3sAQ-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 935308828C2; Mon, 30 Jan 2023 13:21:57 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 4B21F492B00; Mon, 30 Jan 2023 13:21:57 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 3D24421E6A1F; Mon, 30 Jan 2023 14:21:56 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 00/20] Clean up includes Date: Mon, 30 Jan 2023 14:21:36 +0100 Message-Id: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:22:12 -0000 Back in 2016, we discussed[1] rules for headers, and these were generally liked: 1. Have a carefully curated header that's included everywhere first. We got that already thanks to Peter: osdep.h. 2. Headers should normally include everything they need beyond osdep.h. If exceptions are needed for some reason, they must be documented in the header. If all that's needed from a header is typedefs, put those into qemu/typedefs.h instead of including the header. 3. Cyclic inclusion is forbidden. This series fixes violations of rule 2. I may have split patches too aggressively. Let me know if you want some squashed together. v4: * PATCH 01+02: Commit message Fixes: format adjusted [Michael] * PATCH 04: New [David] * PATCH 05-16: Commit messages updated for PATCH 04 v4: * PATCH 01-03: New * PATCH 04-15: Previous version redone with scripts/clean-includes, result split up for review * PATCH 16-19: New v3: * Rebased, old PATCH 1+2+4 are in master as commit 881e019770..f07ceffdf5 * PATCH 1: Fix bsd-user v2: * Rebased * PATCH 3: v1 posted separately * PATCH 4: New [1] Message-ID: <87h9g8j57d.fsf@blackfin.pond.sub.org> https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg03345.html Markus Armbruster (20): scripts/clean-includes: Fully skip / ignore files scripts/clean-includes: Don't claim duplicate headers found when not scripts/clean-includes: Skip symbolic links scripts/clean-includes: Improve --git commit message bsd-user: Clean up includes crypto: Clean up includes hw/cxl: Clean up includes hw/input: Clean up includes hw/tricore: Clean up includes qga: Clean up includes migration: Clean up includes net: Clean up includes target/hexagon: Clean up includes riscv: Clean up includes block: Clean up includes accel: Clean up includes Fix non-first inclusions of qemu/osdep.h Don't include headers already included by qemu/osdep.h 9p: Drop superfluous include of linux/limits.h Drop duplicate #include backends/tpm/tpm_ioctl.h | 2 -- bsd-user/bsd-proc.h | 4 ---- bsd-user/qemu.h | 1 - crypto/block-luks-priv.h | 1 - fsdev/p9array.h | 2 -- include/block/graph-lock.h | 1 - include/block/write-threshold.h | 2 -- include/hw/arm/fsl-imx6ul.h | 1 - include/hw/arm/fsl-imx7.h | 1 - include/hw/cxl/cxl_component.h | 2 -- include/hw/cxl/cxl_host.h | 1 - include/hw/cxl/cxl_pci.h | 1 - include/hw/input/pl050.h | 1 - include/hw/misc/aspeed_lpc.h | 2 -- include/hw/pci/pcie_doe.h | 1 - include/hw/tricore/triboard.h | 1 - include/qemu/async-teardown.h | 2 -- include/qemu/dbus.h | 1 - include/qemu/host-utils.h | 1 - include/qemu/userfaultfd.h | 1 - include/sysemu/accel-blocker.h | 1 - include/sysemu/event-loop-base.h | 1 - net/vmnet_int.h | 1 - qga/cutils.h | 2 -- target/hexagon/hex_arch_types.h | 1 - target/hexagon/mmvec/macros.h | 1 - target/riscv/pmu.h | 1 - accel/tcg/cpu-exec.c | 1 - audio/sndioaudio.c | 2 +- backends/hostmem-epc.c | 2 +- backends/tpm/tpm_emulator.c | 1 - block/export/vduse-blk.c | 2 +- block/qapi.c | 1 - bsd-user/arm/signal.c | 1 + bsd-user/arm/target_arch_cpu.c | 2 ++ bsd-user/freebsd/os-sys.c | 1 + bsd-user/i386/signal.c | 1 + bsd-user/i386/target_arch_cpu.c | 3 +-- bsd-user/main.c | 4 +--- bsd-user/strace.c | 1 - bsd-user/x86_64/signal.c | 1 + bsd-user/x86_64/target_arch_cpu.c | 3 +-- hw/9pfs/9p.c | 5 ----- hw/acpi/piix4.c | 1 - hw/alpha/dp264.c | 1 - hw/arm/virt.c | 1 - hw/arm/xlnx-versal.c | 1 - hw/block/pflash_cfi01.c | 1 - hw/core/machine.c | 1 - hw/display/virtio-gpu-udmabuf.c | 1 - hw/hppa/machine.c | 1 - hw/hyperv/syndbg.c | 2 +- hw/i2c/pmbus_device.c | 1 - hw/i386/acpi-build.c | 1 - hw/input/tsc210x.c | 1 - hw/loongarch/acpi-build.c | 1 - hw/misc/macio/cuda.c | 1 - hw/misc/macio/pmu.c | 1 - hw/net/xilinx_axienet.c | 1 - hw/ppc/ppc405_uc.c | 2 -- hw/ppc/ppc440_bamboo.c | 1 - hw/ppc/spapr_drc.c | 1 - hw/rdma/vmw/pvrdma_dev_ring.c | 1 - hw/remote/machine.c | 1 - hw/remote/proxy-memory-listener.c | 1 - hw/remote/remote-obj.c | 1 - hw/rtc/mc146818rtc.c | 1 - hw/s390x/virtio-ccw-serial.c | 1 - hw/sensor/adm1272.c | 1 - hw/usb/dev-storage-bot.c | 1 - hw/usb/dev-storage-classic.c | 1 - migration/postcopy-ram.c | 2 -- qga/commands-posix.c | 1 - qga/cutils.c | 3 ++- softmmu/dirtylimit.c | 1 - softmmu/runstate.c | 1 - softmmu/vl.c | 3 --- target/loongarch/translate.c | 1 - target/mips/tcg/translate.c | 1 - target/nios2/translate.c | 2 -- tcg/tci.c | 1 - tests/unit/test-cutils.c | 1 - tests/unit/test-seccomp.c | 1 - ui/gtk.c | 1 - ui/udmabuf.c | 1 - util/async-teardown.c | 12 ++++-------- util/main-loop.c | 1 - util/oslib-posix.c | 6 ------ scripts/clean-includes | 19 ++++++++++++------- 89 files changed, 31 insertions(+), 125 deletions(-) -- 2.39.0 From MAILER-DAEMON Mon Jan 30 08:22:18 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMU70-0004nP-E8 for mharc-qemu-riscv@gnu.org; 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Mon, 30 Jan 2023 08:22:00 -0500 X-MC-Unique: i4zfRAlfOz2kCM7dyMxnqg-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.rdu2.redhat.com [10.11.54.1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 9F30929DD985; Mon, 30 Jan 2023 13:21:59 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 77F1D40C2064; Mon, 30 Jan 2023 13:21:59 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 6E11821E691A; Mon, 30 Jan 2023 14:21:56 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 16/20] accel: Clean up includes Date: Mon, 30 Jan 2023 14:21:52 +0100 Message-Id: <20230130132156.1868019-17-armbru@redhat.com> In-Reply-To: <20230130132156.1868019-1-armbru@redhat.com> References: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.1 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:22:12 -0000 Clean up includes so that qemu/osdep.h is included first in .c, and not in .h, and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin --- include/sysemu/accel-blocker.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/sysemu/accel-blocker.h b/include/sysemu/accel-blocker.h index 72020529ef..0733783bcc 100644 --- a/include/sysemu/accel-blocker.h +++ b/include/sysemu/accel-blocker.h @@ -14,7 +14,6 @@ #ifndef ACCEL_BLOCKER_H #define ACCEL_BLOCKER_H -#include "qemu/osdep.h" #include "sysemu/cpus.h" extern void accel_blocker_init(void); -- 2.39.0 From MAILER-DAEMON Mon Jan 30 08:22:19 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMU70-0004or-SQ for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 08:22:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6n-0004F3-Be for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:10 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6k-0005hK-JI for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1675084921; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FMxl36Bz4aHtswUyLTzYVqdyTS4VJBWDPTNwMT0G9V8=; b=XJyKHnJ30WMGN0vsQPhzOrdmKioDuHyDOb4xCSN1spR4rRhQ42RszbXTjXpg13Z3OE6aX2 8yssH+aNfu4yi3e3htGZEdPLdImS7uQs/JmFjBOgfBTQGtWpOZkojh1B3jFOXURguqXgmr MUYIRGTOYwJZqikWdmDCkWjoxepKC4k= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-364-b-Z2UpSLM6WIbTHrrKki1Q-1; Mon, 30 Jan 2023 08:21:59 -0500 X-MC-Unique: b-Z2UpSLM6WIbTHrrKki1Q-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 8AB7B183B3CB; Mon, 30 Jan 2023 13:21:58 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 642E22026D4B; Mon, 30 Jan 2023 13:21:58 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 5302A21E6A26; Mon, 30 Jan 2023 14:21:56 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 07/20] hw/cxl: Clean up includes Date: Mon, 30 Jan 2023 14:21:43 +0100 Message-Id: <20230130132156.1868019-8-armbru@redhat.com> In-Reply-To: <20230130132156.1868019-1-armbru@redhat.com> References: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.4 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:22:12 -0000 Clean up includes so that qemu/osdep.h is included first in .c, and not in .h, and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster Reviewed-by: Michael S. Tsirkin --- include/hw/cxl/cxl_component.h | 2 -- include/hw/cxl/cxl_host.h | 1 - include/hw/cxl/cxl_pci.h | 1 - 3 files changed, 4 deletions(-) diff --git a/include/hw/cxl/cxl_component.h b/include/hw/cxl/cxl_component.h index 5dca21e95b..692d7a5507 100644 --- a/include/hw/cxl/cxl_component.h +++ b/include/hw/cxl/cxl_component.h @@ -15,9 +15,7 @@ #define CXL2_COMPONENT_CM_REGION_SIZE 0x1000 #define CXL2_COMPONENT_BLOCK_SIZE 0x10000 -#include "qemu/compiler.h" #include "qemu/range.h" -#include "qemu/typedefs.h" #include "hw/cxl/cxl_cdat.h" #include "hw/register.h" #include "qapi/error.h" diff --git a/include/hw/cxl/cxl_host.h b/include/hw/cxl/cxl_host.h index a1b662ce40..c9bc9c7c50 100644 --- a/include/hw/cxl/cxl_host.h +++ b/include/hw/cxl/cxl_host.h @@ -7,7 +7,6 @@ * COPYING file in the top-level directory. */ -#include "qemu/osdep.h" #include "hw/cxl/cxl.h" #include "hw/boards.h" diff --git a/include/hw/cxl/cxl_pci.h b/include/hw/cxl/cxl_pci.h index 01e15ed5b4..407be95b9e 100644 --- a/include/hw/cxl/cxl_pci.h +++ b/include/hw/cxl/cxl_pci.h @@ -10,7 +10,6 @@ #ifndef CXL_PCI_H #define CXL_PCI_H -#include "qemu/compiler.h" #define CXL_VENDOR_ID 0x1e98 -- 2.39.0 From MAILER-DAEMON Mon Jan 30 08:22:19 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMU71-0004qI-4R for mharc-qemu-riscv@gnu.org; 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Mon, 30 Jan 2023 08:21:58 -0500 X-MC-Unique: pEESqWQsOaChMZ27xPra1Q-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 75E35802D2A; Mon, 30 Jan 2023 13:21:57 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 4E0FF2166B29; Mon, 30 Jan 2023 13:21:57 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 4703221E6A22; Mon, 30 Jan 2023 14:21:56 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Eric Blake Subject: [PATCH v5 03/20] scripts/clean-includes: Skip symbolic links Date: Mon, 30 Jan 2023 14:21:39 +0100 Message-Id: <20230130132156.1868019-4-armbru@redhat.com> In-Reply-To: <20230130132156.1868019-1-armbru@redhat.com> References: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.6 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:22:12 -0000 When a symbolic link points to a file that needs cleaning, the script replaces the link with a cleaned regular file. Not wanted; skip them. We have a few symbolic links under subprojects/libvduse/ and subprojects/libvhost-user/. Signed-off-by: Markus Armbruster Reviewed-by: Michael S. Tsirkin Reviewed-by: Eric Blake --- scripts/clean-includes | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/scripts/clean-includes b/scripts/clean-includes index 8e8420d785..f0466a6262 100755 --- a/scripts/clean-includes +++ b/scripts/clean-includes @@ -113,6 +113,10 @@ EOT files= for f in "$@"; do + if [ -L "$f" ]; then + echo "SKIPPING $f (symbolic link)" + continue + fi case "$f" in *.c.inc) # These aren't standalone C source files -- 2.39.0 From MAILER-DAEMON Mon Jan 30 08:22:23 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMU74-000524-JD for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 08:22:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6t-0004Hw-P4 for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:12 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6m-0005ip-PA for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1675084922; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kQTECgeSjibAtcqpg1Jqu3tTDHdutMd7+vlY7cuVCHY=; b=I4/B7wpnZIv1yTQXIV4PnVBXRPdI0wK/Jh+x4jrNL2Tt1Ed2OJKCMmv0Qe8pYsQ/Y7+PIf 7JEqpL7Z2AYMxl36m+Yy5Uk/dLhJdOD9vgrZU54HWUTIuWWu5DvJoFS4ygvNz80TcLLhNp Sien1pSetQpLfAqgfLuXW9P4TWkWv0I= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-38-xajR0OanO5OASfhLtGYGBA-1; Mon, 30 Jan 2023 08:21:59 -0500 X-MC-Unique: xajR0OanO5OASfhLtGYGBA-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.rdu2.redhat.com [10.11.54.1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 9BFB7101A52E; Mon, 30 Jan 2023 13:21:58 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 7485840C2064; Mon, 30 Jan 2023 13:21:58 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 5908921E6900; Mon, 30 Jan 2023 14:21:56 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 09/20] hw/tricore: Clean up includes Date: Mon, 30 Jan 2023 14:21:45 +0100 Message-Id: <20230130132156.1868019-10-armbru@redhat.com> In-Reply-To: <20230130132156.1868019-1-armbru@redhat.com> References: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.1 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:22:12 -0000 Clean up includes so that qemu/osdep.h is included first in .c, and not in .h, and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin --- include/hw/tricore/triboard.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/hw/tricore/triboard.h b/include/hw/tricore/triboard.h index 094c8bd563..4fdd2d7d97 100644 --- a/include/hw/tricore/triboard.h +++ b/include/hw/tricore/triboard.h @@ -18,7 +18,6 @@ * License along with this library; if not, see . */ -#include "qemu/osdep.h" #include "qapi/error.h" #include "hw/boards.h" #include "sysemu/sysemu.h" -- 2.39.0 From MAILER-DAEMON Mon Jan 30 08:22:25 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMU75-000539-C8 for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 08:22:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6w-0004Va-JZ for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:14 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6m-0005hE-Su for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1675084921; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/zOw3ANZ93b1EaMNC9IP7T/tBF2PIXPfFkeYR5KfLXI=; b=bR7ULGnCNlNgxdXTNV7Y7gBF5EVwV45e3ytbdQ4zXnMW3198QtfU90yUUGlfLcwo0zGkGW A3lEy7Xcd6obKUieORdB05m4jtXIfqOTDUvX5woE6lmisCj8JJNRBwvgajNKfQZvijk2wU 1Z0wpk0yxdrdZlhAQUZ1NPqNvXYnjUw= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-267-e1wi64RGPdGAzKQY_URnvA-1; Mon, 30 Jan 2023 08:21:58 -0500 X-MC-Unique: e1wi64RGPdGAzKQY_URnvA-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.rdu2.redhat.com [10.11.54.8]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 7EF733C0E453; Mon, 30 Jan 2023 13:21:57 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 58708C15BAE; Mon, 30 Jan 2023 13:21:57 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 4A0A121E6A23; Mon, 30 Jan 2023 14:21:56 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 04/20] scripts/clean-includes: Improve --git commit message Date: Mon, 30 Jan 2023 14:21:40 +0100 Message-Id: <20230130132156.1868019-5-armbru@redhat.com> In-Reply-To: <20230130132156.1868019-1-armbru@redhat.com> References: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.8 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:22:15 -0000 The script drops #include "qemu/osdep.h" from headers. Mention it in the commit message it uses for --git. Signed-off-by: Markus Armbruster --- scripts/clean-includes | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/scripts/clean-includes b/scripts/clean-includes index f0466a6262..f9722c3aec 100755 --- a/scripts/clean-includes +++ b/scripts/clean-includes @@ -193,8 +193,8 @@ if [ "$GIT" = "yes" ]; then git commit --signoff -F - <) id 1pMU6v-0004QY-Ei for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:13 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6m-0005ib-R5 for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1675084922; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=UQUxkL7EuhNEBgL8q7w9wAIfDxyboEPhoa8v5slvyus=; b=VLKz6Lnb7res6uv5iKWHltL1Bj2UrezB03/Sl2jqcTNjcCLIGYSFfTwuKSr3NzRDlCPl1x JZ7aQ2uoH/nSfUyzG9vLy5p4Sbu9gGp8A/QPnzoiMvUL3Hn81HCejzxa9as1mB5YZ6ETr2 P2fiaQ3tJFFZZpiM1060n8zbZ7YOHP4= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-122-3ljnLZYbPuO1oQqLgo2xJQ-1; Mon, 30 Jan 2023 08:21:59 -0500 X-MC-Unique: 3ljnLZYbPuO1oQqLgo2xJQ-1 Received: from smtp.corp.redhat.com (int-mx09.intmail.prod.int.rdu2.redhat.com [10.11.54.9]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 93DC9802D19; Mon, 30 Jan 2023 13:21:58 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 6E21B492B05; Mon, 30 Jan 2023 13:21:58 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 5619721E6A28; Mon, 30 Jan 2023 14:21:56 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 08/20] hw/input: Clean up includes Date: Mon, 30 Jan 2023 14:21:44 +0100 Message-Id: <20230130132156.1868019-9-armbru@redhat.com> In-Reply-To: <20230130132156.1868019-1-armbru@redhat.com> References: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.9 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:22:13 -0000 X-List-Received-Date: Mon, 30 Jan 2023 13:22:13 -0000 Clean up includes so that qemu/osdep.h is included first in .c, and not in .h, and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster Reviewed-by: Michael S. Tsirkin --- include/hw/input/pl050.h | 1 - hw/input/tsc210x.c | 1 - 2 files changed, 2 deletions(-) diff --git a/include/hw/input/pl050.h b/include/hw/input/pl050.h index 89ec4fafc9..4cb8985f31 100644 --- a/include/hw/input/pl050.h +++ b/include/hw/input/pl050.h @@ -10,7 +10,6 @@ #ifndef HW_PL050_H #define HW_PL050_H -#include "qemu/osdep.h" #include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/input/ps2.h" diff --git a/hw/input/tsc210x.c b/hw/input/tsc210x.c index fdd5ff87d9..7eae5989f7 100644 --- a/hw/input/tsc210x.c +++ b/hw/input/tsc210x.c @@ -20,7 +20,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "hw/hw.h" #include "audio/audio.h" #include "qemu/timer.h" -- 2.39.0 From MAILER-DAEMON Mon Jan 30 08:22:57 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMU7d-0005o4-EC for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 08:22:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU72-0004uK-4u for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:20 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6o-0005k8-8I for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1675084923; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=JYJgOYLIY3Zd9s8hgjp2CZMM0oC/9ABdj6PFiCWfZkM=; b=IG9mGC049aUlrUNL0H6Ozn3gG98sPZFJHi4XwZe7+cjRnOquQZByZuz/gg0kxBGWzuHgiT HcPoOVtdExdx1fdTIMGxKQp7aKBp3t7B54KWLLj8v9c5l5rD5cTh1n8owXfqvLYLt+vRPd chaKr+Pi2Tj20GLY0Edu86EqYyy097k= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-445-3dcuylNfOLulD11Nx49pbQ-1; Mon, 30 Jan 2023 08:22:01 -0500 X-MC-Unique: 3dcuylNfOLulD11Nx49pbQ-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 9F07A3C0E453; Mon, 30 Jan 2023 13:21:59 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 78E90140EBF5; Mon, 30 Jan 2023 13:21:59 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 6B05E21E6916; Mon, 30 Jan 2023 14:21:56 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Eric Blake Subject: [PATCH v5 15/20] block: Clean up includes Date: Mon, 30 Jan 2023 14:21:51 +0100 Message-Id: <20230130132156.1868019-16-armbru@redhat.com> In-Reply-To: <20230130132156.1868019-1-armbru@redhat.com> References: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:22:20 -0000 Clean up includes so that qemu/osdep.h is included first in .c, and not in .h, and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster Reviewed-by: Michael S. Tsirkin Reviewed-by: Eric Blake --- include/block/graph-lock.h | 1 - include/block/write-threshold.h | 2 -- block/qapi.c | 1 - 3 files changed, 4 deletions(-) diff --git a/include/block/graph-lock.h b/include/block/graph-lock.h index 3ab924d5e2..18cc14de22 100644 --- a/include/block/graph-lock.h +++ b/include/block/graph-lock.h @@ -20,7 +20,6 @@ #ifndef GRAPH_LOCK_H #define GRAPH_LOCK_H -#include "qemu/osdep.h" #include "qemu/clang-tsa.h" /** diff --git a/include/block/write-threshold.h b/include/block/write-threshold.h index f50f923e7e..63d1583887 100644 --- a/include/block/write-threshold.h +++ b/include/block/write-threshold.h @@ -13,8 +13,6 @@ #ifndef BLOCK_WRITE_THRESHOLD_H #define BLOCK_WRITE_THRESHOLD_H -#include "qemu/typedefs.h" - /* * bdrv_write_threshold_set: * diff --git a/block/qapi.c b/block/qapi.c index 9b4da12966..4f8df48cf4 100644 --- a/block/qapi.c +++ b/block/qapi.c @@ -40,7 +40,6 @@ #include "qapi/qmp/qstring.h" #include "qemu/qemu-print.h" #include "sysemu/block-backend.h" -#include "qemu/cutils.h" BlockDeviceInfo *bdrv_block_device_info(BlockBackend *blk, BlockDriverState *bs, -- 2.39.0 From MAILER-DAEMON Mon Jan 30 08:22:58 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMU7d-0005qD-Qg for mharc-qemu-riscv@gnu.org; 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Mon, 30 Jan 2023 08:21:59 -0500 X-MC-Unique: PCtyP2RAOnysF9uDZtnTHQ-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 89FBC8828C6; Mon, 30 Jan 2023 13:21:58 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 63747422F2; Mon, 30 Jan 2023 13:21:58 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 5017421E6A25; Mon, 30 Jan 2023 14:21:56 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 06/20] crypto: Clean up includes Date: Mon, 30 Jan 2023 14:21:42 +0100 Message-Id: <20230130132156.1868019-7-armbru@redhat.com> In-Reply-To: <20230130132156.1868019-1-armbru@redhat.com> References: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.5 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:22:21 -0000 Clean up includes so that qemu/osdep.h is included first in .c, and not in .h, and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin --- crypto/block-luks-priv.h | 1 - 1 file changed, 1 deletion(-) diff --git a/crypto/block-luks-priv.h b/crypto/block-luks-priv.h index dc2dd14e52..8fc967afcb 100644 --- a/crypto/block-luks-priv.h +++ b/crypto/block-luks-priv.h @@ -18,7 +18,6 @@ * */ -#include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/bswap.h" -- 2.39.0 From MAILER-DAEMON Mon Jan 30 08:22:59 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMU7e-0005t1-Vs for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 08:22:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU73-0004yA-Ht for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:21 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6o-0005kC-Sm for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1675084923; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yo8RxmgtVnXL0bS5vFdivfD1QYbRW3xw/y/5lPafAos=; b=KvD/AnLKxiEI3XGnfUoV9FY6owQrrl81ZZ8/TLSEJ2uwAMwMvZQYqbqhCS+yEiQnu6K0hq sjZ0AJWjCundppnsTdXvhQDqrWdpcfPiHaS6yVzMxga5pSHz/wkduZwN+IVx+EOfdwLUDO xZcmnqfEuD0kdEkgyH/+6y6RqOtwXNI= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-414-VoGU1dxEMEmw3cT9DBkhhg-1; Mon, 30 Jan 2023 08:21:59 -0500 X-MC-Unique: VoGU1dxEMEmw3cT9DBkhhg-1 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id C00138030D5; Mon, 30 Jan 2023 13:21:58 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 974CA492B03; Mon, 30 Jan 2023 13:21:58 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 64FC121E6914; Mon, 30 Jan 2023 14:21:56 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 13/20] target/hexagon: Clean up includes Date: Mon, 30 Jan 2023 14:21:49 +0100 Message-Id: <20230130132156.1868019-14-armbru@redhat.com> In-Reply-To: <20230130132156.1868019-1-armbru@redhat.com> References: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.10 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:22:22 -0000 Clean up includes so that qemu/osdep.h is included first in .c, and not in .h, and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Changes to standalone programs dropped, because these intentionally don't use qemu/osdep.h: target/hexagon/gen_dectree_import.c target/hexagon/gen_semantics.c target/hexagon/idef-parser/idef-parser.h target/hexagon/idef-parser/parser-helpers.c target/hexagon/idef-parser/parser-helpers.h Signed-off-by: Markus Armbruster Reviewed-by: Taylor Simpson Reviewed-by: Michael S. Tsirkin --- target/hexagon/hex_arch_types.h | 1 - target/hexagon/mmvec/macros.h | 1 - 2 files changed, 2 deletions(-) diff --git a/target/hexagon/hex_arch_types.h b/target/hexagon/hex_arch_types.h index 885f68f760..52a7f2b2f3 100644 --- a/target/hexagon/hex_arch_types.h +++ b/target/hexagon/hex_arch_types.h @@ -18,7 +18,6 @@ #ifndef HEXAGON_HEX_ARCH_TYPES_H #define HEXAGON_HEX_ARCH_TYPES_H -#include "qemu/osdep.h" #include "mmvec/mmvec.h" #include "qemu/int128.h" diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index 8c864e8c68..1201d778d0 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -18,7 +18,6 @@ #ifndef HEXAGON_MMVEC_MACROS_H #define HEXAGON_MMVEC_MACROS_H -#include "qemu/osdep.h" #include "qemu/host-utils.h" #include "arch.h" #include "mmvec/system_ext_mmvec.h" -- 2.39.0 From MAILER-DAEMON Mon Jan 30 08:23:01 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMU7g-0005y5-VP for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 08:23:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6u-0004K3-DC for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:12 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6m-0005hb-QS for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1675084921; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qcRImc2dDs0fev9FIlKyp+kjuB8jSu/a15QT63yaRK8=; b=cDB0pom8wO5GvfHaJWN3sVhAAsvoePPW30GTiQJMjXzuAP6u8U5ei4mW/UK8uOphVRdO3V fuF+G1kT8pkTAtWPODvwblZR1ldcZfHbhqhrAtTdvI67OKWvSm0QBm6FvIMeyGWfrmvVLg B8j1Lqz7sl64V/6o/iA824jdGfkN8c4= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-663-LUrub_A-MRCrkV-xrq18mg-1; Mon, 30 Jan 2023 08:21:58 -0500 X-MC-Unique: LUrub_A-MRCrkV-xrq18mg-1 Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.rdu2.redhat.com [10.11.54.4]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 74DE5183B3C3; Mon, 30 Jan 2023 13:21:57 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 4AC912026D76; Mon, 30 Jan 2023 13:21:57 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 3FC4B21E6A20; Mon, 30 Jan 2023 14:21:56 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Eric Blake Subject: [PATCH v5 01/20] scripts/clean-includes: Fully skip / ignore files Date: Mon, 30 Jan 2023 14:21:37 +0100 Message-Id: <20230130132156.1868019-2-armbru@redhat.com> In-Reply-To: <20230130132156.1868019-1-armbru@redhat.com> References: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.4 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:22:12 -0000 When clean-includes claims to skip or ignore a file, only the part that sanitizes use of qemu/osdep.h skips the file. The part that looks for duplicate #include does not, and neither does committing to Git. The latter can get unrelated stuff included in the commit, but only if you run clean-includes in a dirty tree, which is unwise. Messed up when we added skipping in commit fd3e39a40c "scripts/clean-includes: Enhance to handle header files". The former can cause bogus reports for --check-dup-head. Added in commit d66253e46a "scripts/clean-includes: added duplicate #include check", duplicating the prior mistake. Fix the script to fully skip files. Fixes: fd3e39a40ca2 ("scripts/clean-includes: Enhance to handle header files") Fixes: d66253e46ae2 ("scripts/clean-includes: added duplicate #include check") Signed-off-by: Markus Armbruster Reviewed-by: Michael S. Tsirkin Reviewed-by: Eric Blake --- scripts/clean-includes | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/scripts/clean-includes b/scripts/clean-includes index d37bd4f692..86944f27fc 100755 --- a/scripts/clean-includes +++ b/scripts/clean-includes @@ -111,6 +111,7 @@ cat >"$COCCIFILE" < 1) print $0}' if [ $? -eq 0 ]; then echo "Found duplicate header file includes. Please check the above files manually." @@ -184,7 +186,7 @@ if [ "$DUPHEAD" = "yes" ]; then fi if [ "$GIT" = "yes" ]; then - git add -- "$@" + git add -- $files git commit --signoff -F - <) id 1pMU6v-0004RP-Nj for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:13 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6m-0005i3-SE for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:13 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1675084921; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7Lsooe6AIqRlDKr8oVmxGSClV1yzmJJRHR2bzlPP/6Q=; b=NdA4bzwX+/krxPxNjfprKL/2VSDN4AnWZYjzqA4rwQQwRJV/Lujoi4hXfOZwpIBFbgqeoK SL6lIK6E/P2BtxvlXfIa5u9A1gdcpNro+3pmZ/cZEJWXPTR9imxAfHrTYdbkDC9mjMhBNy jhXGIC34j/KAqO1f+OrBdog6CDj+sp4= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-249-DanFbV5BNXyokyNA3sjBkw-1; Mon, 30 Jan 2023 08:21:59 -0500 X-MC-Unique: DanFbV5BNXyokyNA3sjBkw-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.rdu2.redhat.com [10.11.54.1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id A143C183B3D1; Mon, 30 Jan 2023 13:21:58 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 7B06640C2004; Mon, 30 Jan 2023 13:21:58 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 5C15021E6901; Mon, 30 Jan 2023 14:21:56 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 10/20] qga: Clean up includes Date: Mon, 30 Jan 2023 14:21:46 +0100 Message-Id: <20230130132156.1868019-11-armbru@redhat.com> In-Reply-To: <20230130132156.1868019-1-armbru@redhat.com> References: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.1 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:22:14 -0000 Clean up includes so that qemu/osdep.h is included first in .c, and not in .h, and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster Reviewed-by: Konstantin Kostiuk Reviewed-by: Michael S. Tsirkin --- qga/cutils.h | 2 -- qga/commands-posix.c | 1 - qga/cutils.c | 3 ++- 3 files changed, 2 insertions(+), 4 deletions(-) diff --git a/qga/cutils.h b/qga/cutils.h index f0f30a7d28..c1f2f4b17a 100644 --- a/qga/cutils.h +++ b/qga/cutils.h @@ -1,8 +1,6 @@ #ifndef CUTILS_H_ #define CUTILS_H_ -#include "qemu/osdep.h" - int qga_open_cloexec(const char *name, int flags, mode_t mode); #endif /* CUTILS_H_ */ diff --git a/qga/commands-posix.c b/qga/commands-posix.c index ebd33a643c..079689d79a 100644 --- a/qga/commands-posix.c +++ b/qga/commands-posix.c @@ -51,7 +51,6 @@ #else #include #endif -#include #ifdef CONFIG_SOLARIS #include #endif diff --git a/qga/cutils.c b/qga/cutils.c index b8e142ef64..b21bcf3683 100644 --- a/qga/cutils.c +++ b/qga/cutils.c @@ -2,8 +2,9 @@ * This work is licensed under the terms of the GNU GPL, version 2 or later. * See the COPYING file in the top-level directory. */ -#include "cutils.h" +#include "qemu/osdep.h" +#include "cutils.h" #include "qapi/error.h" /** -- 2.39.0 From MAILER-DAEMON Mon Jan 30 08:23:02 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMU7h-0005zi-Kb for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 08:23:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6w-0004Wt-TX for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:15 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6m-0005j2-R4 for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:14 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1675084923; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/362Z3pcgaH/3G/FmJLvNtlNA+dkVrK5ca4wZjXOGww=; b=YclujDVMTZERXZ+IYlgmcADfaBmfsuGwpR8KTp1RjSGm2tJai2pPODN0DjWrF2jkOZTPU6 JxpKEVNeavpsRb6dSTiyl9drQmRqV29rRVK/mCFresDimq9IMf13EQEOhZ5VEuQw5RkKAY R+OvLAGzI1EqSpcqlvITQsUtQE4Ynx8= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-414-yuw6uEm8P0avxDzICJrltA-1; Mon, 30 Jan 2023 08:21:59 -0500 X-MC-Unique: yuw6uEm8P0avxDzICJrltA-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id DE55429DD987; Mon, 30 Jan 2023 13:21:58 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id A4C75140EBF6; Mon, 30 Jan 2023 13:21:58 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 6803B21E6915; Mon, 30 Jan 2023 14:21:56 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Alistair Francis Subject: [PATCH v5 14/20] riscv: Clean up includes Date: Mon, 30 Jan 2023 14:21:50 +0100 Message-Id: <20230130132156.1868019-15-armbru@redhat.com> In-Reply-To: <20230130132156.1868019-1-armbru@redhat.com> References: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:22:15 -0000 Clean up includes so that qemu/osdep.h is included first in .c, and not in .h, and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alistair Francis Reviewed-by: Michael S. Tsirkin --- target/riscv/pmu.h | 1 - 1 file changed, 1 deletion(-) diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 3004ce37b6..0c819ca983 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -16,7 +16,6 @@ * this program. If not, see . */ -#include "qemu/osdep.h" #include "qemu/log.h" #include "cpu.h" #include "qemu/main-loop.h" -- 2.39.0 From MAILER-DAEMON Mon Jan 30 08:23:03 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMU7j-00067d-Fp for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 08:23:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU78-000549-7V for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:27 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6q-0005m2-Iz for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1675084925; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xnuUy+MzQFFeHaD2MZP50NQ29I1xF6AysNgDL67JsxU=; b=AFLo/G+zyOhyVkspi80aLwCzSI2jhjwKENxy+7hktrP1AkALEkAz6mgfxIbl0giIXNNsIs KlmOKh9EnV+MJUFacvL3AIS0HCb+xZiyDtd6wrEd8ylfhnv1un1ejgnX4YCxdw1j9/NKjE G7VzRVkywIlShiaaAbKqecV3+0qMS6o= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-146-JlEXRDP7OEuWVmr0Y5n3qQ-1; Mon, 30 Jan 2023 08:22:00 -0500 X-MC-Unique: JlEXRDP7OEuWVmr0Y5n3qQ-1 Received: from smtp.corp.redhat.com (int-mx09.intmail.prod.int.rdu2.redhat.com [10.11.54.9]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id B03413C0E449; Mon, 30 Jan 2023 13:21:59 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 8A001492B05; Mon, 30 Jan 2023 13:21:59 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 7829321E691F; Mon, 30 Jan 2023 14:21:56 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 19/20] 9p: Drop superfluous include of linux/limits.h Date: Mon, 30 Jan 2023 14:21:55 +0100 Message-Id: <20230130132156.1868019-20-armbru@redhat.com> In-Reply-To: <20230130132156.1868019-1-armbru@redhat.com> References: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.9 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:22:29 -0000 Signed-off-by: Markus Armbruster Reviewed-by: Christian Schoenebeck Reviewed-by: Michael S. Tsirkin --- hw/9pfs/9p.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/hw/9pfs/9p.c b/hw/9pfs/9p.c index 9621ec1341..aa736af380 100644 --- a/hw/9pfs/9p.c +++ b/hw/9pfs/9p.c @@ -17,9 +17,6 @@ */ #include "qemu/osdep.h" -#ifdef CONFIG_LINUX -#include -#endif #include #include "hw/virtio/virtio.h" #include "qapi/error.h" -- 2.39.0 From MAILER-DAEMON Mon Jan 30 08:23:04 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMU7j-00068x-Rt for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 08:23:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU79-00057M-FD for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:27 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6q-0005mF-O0 for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:27 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1675084925; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HNe/b8G/bUVnuc9EJ0VT+9hFK8iT5SkRTdPWic3uM/U=; b=ChjuNv1N3jAeJtKakagaA2qsdwtoiUZmcNP7G7BT9ofiuH88U2AatTHjKg6mOPCTXYODoE 0o4QwomUoQeS0Eqg1KMX7KgVeeT3kNT2N0YGrtibpkR5EiMqbBR60EEFKm5FMMiBInj97g HdkgvZ3jcCV/WDXjsWHfiFpJPBmCS64= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-38-3-SVRO6VMdGDEiH2zlR-kQ-1; Mon, 30 Jan 2023 08:21:59 -0500 X-MC-Unique: 3-SVRO6VMdGDEiH2zlR-kQ-1 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.rdu2.redhat.com [10.11.54.5]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id B031D80D0FB; Mon, 30 Jan 2023 13:21:58 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 89B2E422AE; Mon, 30 Jan 2023 13:21:58 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 61FC921E6913; Mon, 30 Jan 2023 14:21:56 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 12/20] net: Clean up includes Date: Mon, 30 Jan 2023 14:21:48 +0100 Message-Id: <20230130132156.1868019-13-armbru@redhat.com> In-Reply-To: <20230130132156.1868019-1-armbru@redhat.com> References: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.5 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:22:31 -0000 Clean up includes so that qemu/osdep.h is included first in .c, and not in .h, and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin --- net/vmnet_int.h | 1 - 1 file changed, 1 deletion(-) diff --git a/net/vmnet_int.h b/net/vmnet_int.h index adf6e8c20d..d0b90594f2 100644 --- a/net/vmnet_int.h +++ b/net/vmnet_int.h @@ -10,7 +10,6 @@ #ifndef VMNET_INT_H #define VMNET_INT_H -#include "qemu/osdep.h" #include "vmnet_int.h" #include "clients.h" -- 2.39.0 From MAILER-DAEMON Mon Jan 30 08:23:05 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMU7k-0006Bw-T6 for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 08:23:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU70-0004oN-L5 for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:18 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6n-0005jN-UV for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1675084923; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=4XEfBKWNyAi2J68lpx37vHlrsNvIHgtAg8Q2XUV895I=; b=C/jdswaqFYx1MBZVZNnLFlMoV8/n+8TQ0gPFD62p3NOOZjIHJaEtOhD8MIkw9tDlbcLX99 fhGERcaopUMbJvenxwAaNmFF2PQxS8aEk72wfuYea04cAoqmx2i6CMz9dr0riYO/rkVz5/ qrbe5YDnClPT6iCyjoRSmmTfTBuvgT4= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-90-opOIk1mQOye4eg6pYkZ8Sw-1; Mon, 30 Jan 2023 08:21:59 -0500 X-MC-Unique: opOIk1mQOye4eg6pYkZ8Sw-1 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.rdu2.redhat.com [10.11.54.3]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id A7B8C802C15; Mon, 30 Jan 2023 13:21:58 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 63F001121314; Mon, 30 Jan 2023 13:21:58 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 4D16021E6A24; Mon, 30 Jan 2023 14:21:56 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 05/20] bsd-user: Clean up includes Date: Mon, 30 Jan 2023 14:21:41 +0100 Message-Id: <20230130132156.1868019-6-armbru@redhat.com> In-Reply-To: <20230130132156.1868019-1-armbru@redhat.com> References: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.3 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:22:19 -0000 Clean up includes so that qemu/osdep.h is included first in .c, and not in .h, and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster Reviewed-by: Warner Losh Reviewed-by: Michael S. Tsirkin --- bsd-user/bsd-proc.h | 4 ---- bsd-user/qemu.h | 1 - bsd-user/arm/signal.c | 1 + bsd-user/arm/target_arch_cpu.c | 2 ++ bsd-user/freebsd/os-sys.c | 1 + bsd-user/i386/signal.c | 1 + bsd-user/i386/target_arch_cpu.c | 3 +-- bsd-user/main.c | 4 +--- bsd-user/strace.c | 1 - bsd-user/x86_64/signal.c | 1 + bsd-user/x86_64/target_arch_cpu.c | 3 +-- 11 files changed, 9 insertions(+), 13 deletions(-) diff --git a/bsd-user/bsd-proc.h b/bsd-user/bsd-proc.h index 68b66e571d..a1061bffb8 100644 --- a/bsd-user/bsd-proc.h +++ b/bsd-user/bsd-proc.h @@ -20,11 +20,7 @@ #ifndef BSD_PROC_H_ #define BSD_PROC_H_ -#include -#include -#include #include -#include /* exit(2) */ static inline abi_long do_bsd_exit(void *cpu_env, abi_long arg1) diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index be6105385e..0ceecfb6df 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -17,7 +17,6 @@ #ifndef QEMU_H #define QEMU_H -#include "qemu/osdep.h" #include "cpu.h" #include "qemu/units.h" #include "exec/cpu_ldst.h" diff --git a/bsd-user/arm/signal.c b/bsd-user/arm/signal.c index 2b1dd745d1..9734407543 100644 --- a/bsd-user/arm/signal.c +++ b/bsd-user/arm/signal.c @@ -17,6 +17,7 @@ * along with this program; if not, see . */ +#include "qemu/osdep.h" #include "qemu.h" /* diff --git a/bsd-user/arm/target_arch_cpu.c b/bsd-user/arm/target_arch_cpu.c index 02bf9149d5..fe38ae2210 100644 --- a/bsd-user/arm/target_arch_cpu.c +++ b/bsd-user/arm/target_arch_cpu.c @@ -16,6 +16,8 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, see . */ + +#include "qemu/osdep.h" #include "target_arch.h" void target_cpu_set_tls(CPUARMState *env, target_ulong newtls) diff --git a/bsd-user/freebsd/os-sys.c b/bsd-user/freebsd/os-sys.c index 309e27b9d6..1676ec10f8 100644 --- a/bsd-user/freebsd/os-sys.c +++ b/bsd-user/freebsd/os-sys.c @@ -17,6 +17,7 @@ * along with this program; if not, see . */ +#include "qemu/osdep.h" #include "qemu.h" #include "target_arch_sysarch.h" diff --git a/bsd-user/i386/signal.c b/bsd-user/i386/signal.c index 5dd975ce56..a3131047b8 100644 --- a/bsd-user/i386/signal.c +++ b/bsd-user/i386/signal.c @@ -17,6 +17,7 @@ * along with this program; if not, see . */ +#include "qemu/osdep.h" #include "qemu.h" /* diff --git a/bsd-user/i386/target_arch_cpu.c b/bsd-user/i386/target_arch_cpu.c index d349e45299..2a3af2ddef 100644 --- a/bsd-user/i386/target_arch_cpu.c +++ b/bsd-user/i386/target_arch_cpu.c @@ -17,9 +17,8 @@ * along with this program; if not, see . */ -#include - #include "qemu/osdep.h" + #include "cpu.h" #include "qemu.h" #include "qemu/timer.h" diff --git a/bsd-user/main.c b/bsd-user/main.c index 6f09180d65..41290e16f9 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -18,12 +18,10 @@ * along with this program; if not, see . */ -#include -#include +#include "qemu/osdep.h" #include #include -#include "qemu/osdep.h" #include "qemu/help-texts.h" #include "qemu/units.h" #include "qemu/accel.h" diff --git a/bsd-user/strace.c b/bsd-user/strace.c index a77d10dd6b..96499751eb 100644 --- a/bsd-user/strace.c +++ b/bsd-user/strace.c @@ -20,7 +20,6 @@ #include #include #include -#include #include "qemu.h" diff --git a/bsd-user/x86_64/signal.c b/bsd-user/x86_64/signal.c index c3875bc4c6..46cb865180 100644 --- a/bsd-user/x86_64/signal.c +++ b/bsd-user/x86_64/signal.c @@ -16,6 +16,7 @@ * along with this program; if not, see . */ +#include "qemu/osdep.h" #include "qemu.h" /* diff --git a/bsd-user/x86_64/target_arch_cpu.c b/bsd-user/x86_64/target_arch_cpu.c index be7bd10720..1d32f18907 100644 --- a/bsd-user/x86_64/target_arch_cpu.c +++ b/bsd-user/x86_64/target_arch_cpu.c @@ -17,9 +17,8 @@ * along with this program; if not, see . */ -#include - #include "qemu/osdep.h" + #include "cpu.h" #include "qemu.h" #include "qemu/timer.h" -- 2.39.0 From MAILER-DAEMON Mon Jan 30 08:23:05 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMU7l-0006DJ-7f for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 08:23:05 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU72-0004uL-4r for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:20 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6o-0005jC-7m for qemu-riscv@nongnu.org; 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Mon, 30 Jan 2023 13:21:58 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 821DC1415113; Mon, 30 Jan 2023 13:21:58 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 5F22521E690F; Mon, 30 Jan 2023 14:21:56 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 11/20] migration: Clean up includes Date: Mon, 30 Jan 2023 14:21:47 +0100 Message-Id: <20230130132156.1868019-12-armbru@redhat.com> In-Reply-To: <20230130132156.1868019-1-armbru@redhat.com> References: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:22:20 -0000 Clean up includes so that qemu/osdep.h is included first in .c, and not in .h, and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster Reviewed-by: Dr. David Alan Gilbert Reviewed-by: Michael S. Tsirkin Reviewed-by: Juan Quintela --- include/qemu/userfaultfd.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/qemu/userfaultfd.h b/include/qemu/userfaultfd.h index 6b74f92792..55c95998e8 100644 --- a/include/qemu/userfaultfd.h +++ b/include/qemu/userfaultfd.h @@ -13,7 +13,6 @@ #ifndef USERFAULTFD_H #define USERFAULTFD_H -#include "qemu/osdep.h" #include "exec/hwaddr.h" #include -- 2.39.0 From MAILER-DAEMON Mon Jan 30 08:23:15 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMU7u-0006hh-MU for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 08:23:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU7E-0005GY-7N for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:33 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6q-0005lP-QW for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:31 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1675084924; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NGpagByXc6J4MIDUTVLoDzWnIbFD7ozyvTMvhgaYQTI=; b=JnwZNVoKfZbWEQyWv5aqog/A0WaEL2l0XSNY0RlXT+8KT090RBsS3Tn8JyL7aMJUfE+zMC f7exI1FfADtnfjmTS+CYr2D9MGjWyxF6t2poPRmgnEbxHI9GfY+fFml26wh3JJv9DsX7uE QV0CRLe4oA7pMX11KYNbIPZQusmW8DY= Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-445-eIymWka5PfyXRLu6sOtO3Q-1; Mon, 30 Jan 2023 08:22:01 -0500 X-MC-Unique: eIymWka5PfyXRLu6sOtO3Q-1 Received: from smtp.corp.redhat.com (int-mx07.intmail.prod.int.rdu2.redhat.com [10.11.54.7]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id C413C3C0E44F; Mon, 30 Jan 2023 13:21:59 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 81878140EBF6; Mon, 30 Jan 2023 13:21:59 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 74E5821E691C; Mon, 30 Jan 2023 14:21:56 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 18/20] Don't include headers already included by qemu/osdep.h Date: Mon, 30 Jan 2023 14:21:54 +0100 Message-Id: <20230130132156.1868019-19-armbru@redhat.com> In-Reply-To: <20230130132156.1868019-1-armbru@redhat.com> References: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.7 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:22:43 -0000 This commit was created with scripts/clean-includes. Signed-off-by: Markus Armbruster Acked-by: Christian Schoenebeck Reviewed-by: Michael S. Tsirkin --- backends/tpm/tpm_ioctl.h | 2 -- fsdev/p9array.h | 2 -- include/hw/misc/aspeed_lpc.h | 2 -- include/hw/pci/pcie_doe.h | 1 - include/qemu/async-teardown.h | 2 -- include/qemu/dbus.h | 1 - include/qemu/host-utils.h | 1 - include/sysemu/event-loop-base.h | 1 - accel/tcg/cpu-exec.c | 1 - hw/9pfs/9p.c | 2 -- hw/display/virtio-gpu-udmabuf.c | 1 - hw/i2c/pmbus_device.c | 1 - hw/remote/proxy-memory-listener.c | 1 - hw/sensor/adm1272.c | 1 - hw/usb/dev-storage-bot.c | 1 - hw/usb/dev-storage-classic.c | 1 - softmmu/vl.c | 2 -- tcg/tci.c | 1 - tests/unit/test-seccomp.c | 1 - ui/udmabuf.c | 1 - util/main-loop.c | 1 - util/oslib-posix.c | 2 -- 22 files changed, 29 deletions(-) diff --git a/backends/tpm/tpm_ioctl.h b/backends/tpm/tpm_ioctl.h index e506ef5160..b1d31768a6 100644 --- a/backends/tpm/tpm_ioctl.h +++ b/backends/tpm/tpm_ioctl.h @@ -12,8 +12,6 @@ # define __USE_LINUX_IOCTL_DEFS #endif -#include -#include #ifndef _WIN32 #include #include diff --git a/fsdev/p9array.h b/fsdev/p9array.h index 90e83a7c7b..50a1b15fe9 100644 --- a/fsdev/p9array.h +++ b/fsdev/p9array.h @@ -27,8 +27,6 @@ #ifndef QEMU_P9ARRAY_H #define QEMU_P9ARRAY_H -#include "qemu/compiler.h" - /** * P9Array provides a mechanism to access arrays in common C-style (e.g. by * square bracket [] operator) in conjunction with reference variables that diff --git a/include/hw/misc/aspeed_lpc.h b/include/hw/misc/aspeed_lpc.h index fd228731d2..fa398959af 100644 --- a/include/hw/misc/aspeed_lpc.h +++ b/include/hw/misc/aspeed_lpc.h @@ -12,8 +12,6 @@ #include "hw/sysbus.h" -#include - #define TYPE_ASPEED_LPC "aspeed.lpc" #define ASPEED_LPC(obj) OBJECT_CHECK(AspeedLPCState, (obj), TYPE_ASPEED_LPC) diff --git a/include/hw/pci/pcie_doe.h b/include/hw/pci/pcie_doe.h index ba4d8b03bd..87dc17dcef 100644 --- a/include/hw/pci/pcie_doe.h +++ b/include/hw/pci/pcie_doe.h @@ -11,7 +11,6 @@ #define PCIE_DOE_H #include "qemu/range.h" -#include "qemu/typedefs.h" #include "hw/register.h" /* diff --git a/include/qemu/async-teardown.h b/include/qemu/async-teardown.h index 092e7a37e7..b281da005b 100644 --- a/include/qemu/async-teardown.h +++ b/include/qemu/async-teardown.h @@ -13,8 +13,6 @@ #ifndef QEMU_ASYNC_TEARDOWN_H #define QEMU_ASYNC_TEARDOWN_H -#include "config-host.h" - #ifdef CONFIG_LINUX void init_async_teardown(void); #endif diff --git a/include/qemu/dbus.h b/include/qemu/dbus.h index 08f00dfd53..81d3de8a5a 100644 --- a/include/qemu/dbus.h +++ b/include/qemu/dbus.h @@ -15,7 +15,6 @@ #include "qom/object.h" #include "chardev/char.h" #include "qemu/notify.h" -#include "qemu/typedefs.h" /* glib/gio 2.68 */ #define DBUS_METHOD_INVOCATION_HANDLED TRUE diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index 88d476161c..3ce62bf4a5 100644 --- a/include/qemu/host-utils.h +++ b/include/qemu/host-utils.h @@ -30,7 +30,6 @@ #ifndef HOST_UTILS_H #define HOST_UTILS_H -#include "qemu/compiler.h" #include "qemu/bswap.h" #include "qemu/int128.h" diff --git a/include/sysemu/event-loop-base.h b/include/sysemu/event-loop-base.h index 2748bf6ae1..a6c24f1351 100644 --- a/include/sysemu/event-loop-base.h +++ b/include/sysemu/event-loop-base.h @@ -14,7 +14,6 @@ #include "qom/object.h" #include "block/aio.h" -#include "qemu/typedefs.h" #define TYPE_EVENT_LOOP_BASE "event-loop-base" OBJECT_DECLARE_TYPE(EventLoopBase, EventLoopBaseClass, diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 04cd1f3092..8e0caf2fcc 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -28,7 +28,6 @@ #include "exec/exec-all.h" #include "tcg/tcg.h" #include "qemu/atomic.h" -#include "qemu/compiler.h" #include "qemu/timer.h" #include "qemu/rcu.h" #include "exec/log.h" diff --git a/hw/9pfs/9p.c b/hw/9pfs/9p.c index 072cf67956..9621ec1341 100644 --- a/hw/9pfs/9p.c +++ b/hw/9pfs/9p.c @@ -19,8 +19,6 @@ #include "qemu/osdep.h" #ifdef CONFIG_LINUX #include -#else -#include #endif #include #include "hw/virtio/virtio.h" diff --git a/hw/display/virtio-gpu-udmabuf.c b/hw/display/virtio-gpu-udmabuf.c index 8bdf4bac6e..847fa4c0cc 100644 --- a/hw/display/virtio-gpu-udmabuf.c +++ b/hw/display/virtio-gpu-udmabuf.c @@ -21,7 +21,6 @@ #include "exec/ramblock.h" #include "sysemu/hostmem.h" #include -#include #include #include "qemu/memfd.h" #include "standard-headers/linux/udmabuf.h" diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c index 4071a88cfc..c3d6046784 100644 --- a/hw/i2c/pmbus_device.c +++ b/hw/i2c/pmbus_device.c @@ -8,7 +8,6 @@ #include "qemu/osdep.h" #include -#include #include "hw/i2c/pmbus_device.h" #include "migration/vmstate.h" #include "qemu/module.h" diff --git a/hw/remote/proxy-memory-listener.c b/hw/remote/proxy-memory-listener.c index eb9918fe72..18d96a1d04 100644 --- a/hw/remote/proxy-memory-listener.c +++ b/hw/remote/proxy-memory-listener.c @@ -8,7 +8,6 @@ #include "qemu/osdep.h" -#include "qemu/compiler.h" #include "qemu/int128.h" #include "qemu/range.h" #include "exec/memory.h" diff --git a/hw/sensor/adm1272.c b/hw/sensor/adm1272.c index 7310c769be..8f4a1c2cd4 100644 --- a/hw/sensor/adm1272.c +++ b/hw/sensor/adm1272.c @@ -8,7 +8,6 @@ */ #include "qemu/osdep.h" -#include #include "hw/i2c/pmbus_device.h" #include "hw/irq.h" #include "migration/vmstate.h" diff --git a/hw/usb/dev-storage-bot.c b/hw/usb/dev-storage-bot.c index b24b3148c2..1e5c5c711f 100644 --- a/hw/usb/dev-storage-bot.c +++ b/hw/usb/dev-storage-bot.c @@ -8,7 +8,6 @@ */ #include "qemu/osdep.h" -#include "qemu/typedefs.h" #include "qapi/error.h" #include "hw/usb.h" #include "hw/usb/desc.h" diff --git a/hw/usb/dev-storage-classic.c b/hw/usb/dev-storage-classic.c index 00f25bade2..84d19752b5 100644 --- a/hw/usb/dev-storage-classic.c +++ b/hw/usb/dev-storage-classic.c @@ -8,7 +8,6 @@ */ #include "qemu/osdep.h" -#include "qemu/typedefs.h" #include "qapi/error.h" #include "qapi/visitor.h" #include "hw/usb.h" diff --git a/softmmu/vl.c b/softmmu/vl.c index 9177d95d4e..5355a7fe5a 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -136,8 +136,6 @@ #include "qemu/guest-random.h" #include "qemu/keyval.h" -#include "config-host.h" - #define MAX_VIRTIO_CONSOLES 1 typedef struct BlockdevOptionsQueueEntry { diff --git a/tcg/tci.c b/tcg/tci.c index 05a24163d3..e7ac74cab0 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -21,7 +21,6 @@ #include "exec/cpu_ldst.h" #include "tcg/tcg-op.h" #include "tcg/tcg-ldst.h" -#include "qemu/compiler.h" #include diff --git a/tests/unit/test-seccomp.c b/tests/unit/test-seccomp.c index 3d7771e46c..f02c79cafd 100644 --- a/tests/unit/test-seccomp.c +++ b/tests/unit/test-seccomp.c @@ -25,7 +25,6 @@ #include "qapi/error.h" #include "qemu/module.h" -#include #include static void test_seccomp_helper(const char *args, bool killed, diff --git a/ui/udmabuf.c b/ui/udmabuf.c index cebceb2610..cbf4357bb1 100644 --- a/ui/udmabuf.c +++ b/ui/udmabuf.c @@ -8,7 +8,6 @@ #include "qapi/error.h" #include "ui/console.h" -#include #include int udmabuf_fd(void) diff --git a/util/main-loop.c b/util/main-loop.c index 58f776a8c9..3c0f525192 100644 --- a/util/main-loop.c +++ b/util/main-loop.c @@ -33,7 +33,6 @@ #include "block/thread-pool.h" #include "qemu/error-report.h" #include "qemu/queue.h" -#include "qemu/compiler.h" #include "qom/object.h" #ifndef _WIN32 diff --git a/util/oslib-posix.c b/util/oslib-posix.c index 59a891b6a8..fd03fd32c8 100644 --- a/util/oslib-posix.c +++ b/util/oslib-posix.c @@ -40,7 +40,6 @@ #include "qemu/thread.h" #include #include "qemu/cutils.h" -#include "qemu/compiler.h" #include "qemu/units.h" #include "qemu/thread-context.h" @@ -50,7 +49,6 @@ #ifdef __FreeBSD__ #include -#include #include #include #endif -- 2.39.0 From MAILER-DAEMON Mon Jan 30 08:23:16 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMU7v-0006qI-VX for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 08:23:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) 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relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-288-ID4_w7c9MFunCxEIfhh2Aw-1; Mon, 30 Jan 2023 08:21:58 -0500 X-MC-Unique: ID4_w7c9MFunCxEIfhh2Aw-1 Received: from smtp.corp.redhat.com (int-mx06.intmail.prod.int.rdu2.redhat.com [10.11.54.6]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 7462A183B3C0; Mon, 30 Jan 2023 13:21:57 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 4A9BE2166B26; Mon, 30 Jan 2023 13:21:57 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 439F621E6A21; Mon, 30 Jan 2023 14:21:56 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, Eric Blake Subject: [PATCH v5 02/20] scripts/clean-includes: Don't claim duplicate headers found when not Date: Mon, 30 Jan 2023 14:21:38 +0100 Message-Id: <20230130132156.1868019-3-armbru@redhat.com> In-Reply-To: <20230130132156.1868019-1-armbru@redhat.com> References: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.6 Received-SPF: pass client-ip=170.10.133.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:22:26 -0000 When running with --check-dup-head, the script always claims it "Found duplicate header file includes." Fix to do it only when it actually found some. Fixes: d66253e46ae2 ("scripts/clean-includes: added duplicate #include check") Signed-off-by: Markus Armbruster Reviewed-by: Michael S. Tsirkin Reviewed-by: Eric Blake --- scripts/clean-includes | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/scripts/clean-includes b/scripts/clean-includes index 86944f27fc..8e8420d785 100755 --- a/scripts/clean-includes +++ b/scripts/clean-includes @@ -177,9 +177,8 @@ for f in "$@"; do done if [ "$DUPHEAD" = "yes" ] && [ -n "$files" ]; then - egrep "^[[:space:]]*#[[:space:]]*include" $files | tr -d '[:blank:]' \ - | sort | uniq -c | awk '{if ($1 > 1) print $0}' - if [ $? -eq 0 ]; then + if egrep "^[[:space:]]*#[[:space:]]*include" $files | tr -d '[:blank:]' \ + | sort | uniq -c | grep -v '^ *1 '; then echo "Found duplicate header file includes. Please check the above files manually." exit 1 fi -- 2.39.0 From MAILER-DAEMON Mon Jan 30 08:23:17 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMU7x-0006xV-3o for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 08:23:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU77-00053f-Gv for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:25 -0500 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMU6p-0005lF-8K for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 08:22:25 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1675084924; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=cSuD7wwfEIoR/KVA5CwwxW/I+dK80Y2fYpG2Yd3+XNQ=; b=bOLvCtWhoZzC+DMvtgnyNiu6V6NsCUhDUkODQ/v18mHTMdKx0U93GfM8whJSH8bNb6XZUP TRitoBggnuQ0IZbWKQMTztrHARqBOpllXGFhYKqOUcujuTV2moBPti6n0dLjau1sS6sE5J Kg30JV/qTTMbsdtuIcHnG++lTgqW0WE= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-339-SbaOCKQWNW--c6lW5a7udA-1; Mon, 30 Jan 2023 08:22:01 -0500 X-MC-Unique: SbaOCKQWNW--c6lW5a7udA-1 Received: from smtp.corp.redhat.com (int-mx08.intmail.prod.int.rdu2.redhat.com [10.11.54.8]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id D689A100F910; Mon, 30 Jan 2023 13:21:59 +0000 (UTC) Received: from blackfin.pond.sub.org (unknown [10.39.192.70]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 90A13C15BAE; Mon, 30 Jan 2023 13:21:59 +0000 (UTC) Received: by blackfin.pond.sub.org (Postfix, from userid 1000) id 7BF0C21E6921; Mon, 30 Jan 2023 14:21:56 +0100 (CET) From: Markus Armbruster To: qemu-devel@nongnu.org Cc: richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 20/20] Drop duplicate #include Date: Mon, 30 Jan 2023 14:21:56 +0100 Message-Id: <20230130132156.1868019-21-armbru@redhat.com> In-Reply-To: <20230130132156.1868019-1-armbru@redhat.com> References: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-type: text/plain Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.8 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 13:22:28 -0000 Tracked down with the help of scripts/clean-includes. Signed-off-by: Markus Armbruster Acked-by: Dr. David Alan Gilbert Reviewed-by: Greg Kurz Reviewed-by: Michael S. Tsirkin Reviewed-by: Juan Quintela --- include/hw/arm/fsl-imx6ul.h | 1 - include/hw/arm/fsl-imx7.h | 1 - backends/tpm/tpm_emulator.c | 1 - hw/acpi/piix4.c | 1 - hw/alpha/dp264.c | 1 - hw/arm/virt.c | 1 - hw/arm/xlnx-versal.c | 1 - hw/block/pflash_cfi01.c | 1 - hw/core/machine.c | 1 - hw/hppa/machine.c | 1 - hw/i386/acpi-build.c | 1 - hw/loongarch/acpi-build.c | 1 - hw/misc/macio/cuda.c | 1 - hw/misc/macio/pmu.c | 1 - hw/net/xilinx_axienet.c | 1 - hw/ppc/ppc405_uc.c | 2 -- hw/ppc/ppc440_bamboo.c | 1 - hw/ppc/spapr_drc.c | 1 - hw/rdma/vmw/pvrdma_dev_ring.c | 1 - hw/remote/machine.c | 1 - hw/remote/remote-obj.c | 1 - hw/rtc/mc146818rtc.c | 1 - hw/s390x/virtio-ccw-serial.c | 1 - migration/postcopy-ram.c | 2 -- softmmu/dirtylimit.c | 1 - softmmu/runstate.c | 1 - softmmu/vl.c | 1 - target/loongarch/translate.c | 1 - target/mips/tcg/translate.c | 1 - target/nios2/translate.c | 2 -- tests/unit/test-cutils.c | 1 - ui/gtk.c | 1 - util/oslib-posix.c | 4 ---- 33 files changed, 39 deletions(-) diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h index 7812e516a5..1952cb984d 100644 --- a/include/hw/arm/fsl-imx6ul.h +++ b/include/hw/arm/fsl-imx6ul.h @@ -30,7 +30,6 @@ #include "hw/timer/imx_gpt.h" #include "hw/timer/imx_epit.h" #include "hw/i2c/imx_i2c.h" -#include "hw/gpio/imx_gpio.h" #include "hw/sd/sdhci.h" #include "hw/ssi/imx_spi.h" #include "hw/net/imx_fec.h" diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h index 4e5e071864..355bd8ea83 100644 --- a/include/hw/arm/fsl-imx7.h +++ b/include/hw/arm/fsl-imx7.h @@ -32,7 +32,6 @@ #include "hw/timer/imx_gpt.h" #include "hw/timer/imx_epit.h" #include "hw/i2c/imx_i2c.h" -#include "hw/gpio/imx_gpio.h" #include "hw/sd/sdhci.h" #include "hw/ssi/imx_spi.h" #include "hw/net/imx_fec.h" diff --git a/backends/tpm/tpm_emulator.c b/backends/tpm/tpm_emulator.c index 67e7b212e3..d18144b92e 100644 --- a/backends/tpm/tpm_emulator.c +++ b/backends/tpm/tpm_emulator.c @@ -35,7 +35,6 @@ #include "sysemu/runstate.h" #include "sysemu/tpm_backend.h" #include "sysemu/tpm_util.h" -#include "sysemu/runstate.h" #include "tpm_int.h" #include "tpm_ioctl.h" #include "migration/blocker.h" diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 0a81f1ad93..df39f91294 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -35,7 +35,6 @@ #include "sysemu/xen.h" #include "qapi/error.h" #include "qemu/range.h" -#include "hw/acpi/pcihp.h" #include "hw/acpi/cpu_hotplug.h" #include "hw/acpi/cpu.h" #include "hw/hotplug.h" diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c index c502c8c62a..4161f559a7 100644 --- a/hw/alpha/dp264.c +++ b/hw/alpha/dp264.c @@ -18,7 +18,6 @@ #include "net/net.h" #include "qemu/cutils.h" #include "qemu/datadir.h" -#include "net/net.h" static uint64_t cpu_alpha_superpage_to_phys(void *opaque, uint64_t addr) { diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ea2413a0ba..d3849d7233 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -33,7 +33,6 @@ #include "qemu/units.h" #include "qemu/option.h" #include "monitor/qdev.h" -#include "qapi/error.h" #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "hw/arm/primecell.h" diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 57276e1506..69b1b99e93 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -22,7 +22,6 @@ #include "hw/misc/unimp.h" #include "hw/arm/xlnx-versal.h" #include "qemu/log.h" -#include "hw/sysbus.h" #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 36d68c70f6..3c066e3405 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -45,7 +45,6 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/bitops.h" -#include "qemu/error-report.h" #include "qemu/host-utils.h" #include "qemu/log.h" #include "qemu/module.h" diff --git a/hw/core/machine.c b/hw/core/machine.c index 616f3a207c..67cf9f9dcd 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -39,7 +39,6 @@ #include "exec/confidential-guest-support.h" #include "hw/virtio/virtio.h" #include "hw/virtio/virtio-pci.h" -#include "qom/object_interfaces.h" GlobalProperty hw_compat_7_2[] = {}; const size_t hw_compat_7_2_len = G_N_ELEMENTS(hw_compat_7_2); diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index de1cc7ab71..7ac68c943f 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -28,7 +28,6 @@ #include "qapi/error.h" #include "net/net.h" #include "qemu/log.h" -#include "net/net.h" #define MIN_SEABIOS_HPPA_VERSION 6 /* require at least this fw version */ diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 127c4e2d50..14f6f75454 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -76,7 +76,6 @@ #include "hw/acpi/hmat.h" #include "hw/acpi/viot.h" -#include "hw/acpi/cxl.h" #include CONFIG_DEVICES diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c index c2b237736d..f551296a0e 100644 --- a/hw/loongarch/acpi-build.c +++ b/hw/loongarch/acpi-build.c @@ -22,7 +22,6 @@ /* Supported chipsets: */ #include "hw/pci-host/ls7a.h" #include "hw/loongarch/virt.h" -#include "hw/acpi/aml-build.h" #include "hw/acpi/utils.h" #include "hw/acpi/pci.h" diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index 853e88bfed..29a8e5ed19 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -30,7 +30,6 @@ #include "hw/input/adb.h" #include "hw/misc/mos6522.h" #include "hw/misc/macio/cuda.h" -#include "qapi/error.h" #include "qemu/timer.h" #include "sysemu/runstate.h" #include "sysemu/rtc.h" diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c index 97ef8c771b..5a788e595a 100644 --- a/hw/misc/macio/pmu.c +++ b/hw/misc/macio/pmu.c @@ -36,7 +36,6 @@ #include "hw/misc/mos6522.h" #include "hw/misc/macio/gpio.h" #include "hw/misc/macio/pmu.h" -#include "qapi/error.h" #include "qemu/timer.h" #include "sysemu/runstate.h" #include "sysemu/rtc.h" diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index 7e00965323..5b19a01eaa 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -31,7 +31,6 @@ #include "net/net.h" #include "net/checksum.h" -#include "hw/hw.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/stream.h" diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index c973cfb04e..0cc68178ad 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -38,8 +38,6 @@ #include "sysemu/sysemu.h" #include "exec/address-spaces.h" #include "hw/intc/ppc-uic.h" -#include "hw/qdev-properties.h" -#include "qapi/error.h" #include "trace.h" /*****************************************************************************/ diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index 81d71adf34..2880c81cb1 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -13,7 +13,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" -#include "qemu/error-report.h" #include "qemu/datadir.h" #include "qemu/error-report.h" #include "net/net.h" diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c index 4923435a8b..b5c400a94d 100644 --- a/hw/ppc/spapr_drc.c +++ b/hw/ppc/spapr_drc.c @@ -17,7 +17,6 @@ #include "hw/ppc/spapr_drc.h" #include "qom/object.h" #include "migration/vmstate.h" -#include "qapi/error.h" #include "qapi/qapi-events-qdev.h" #include "qapi/visitor.h" #include "qemu/error-report.h" diff --git a/hw/rdma/vmw/pvrdma_dev_ring.c b/hw/rdma/vmw/pvrdma_dev_ring.c index 598e6adc5e..30ce22a5be 100644 --- a/hw/rdma/vmw/pvrdma_dev_ring.c +++ b/hw/rdma/vmw/pvrdma_dev_ring.c @@ -14,7 +14,6 @@ */ #include "qemu/osdep.h" -#include "qemu/cutils.h" #include "hw/pci/pci.h" #include "cpu.h" #include "qemu/cutils.h" diff --git a/hw/remote/machine.c b/hw/remote/machine.c index 519f855ec1..fdc6c441bb 100644 --- a/hw/remote/machine.c +++ b/hw/remote/machine.c @@ -22,7 +22,6 @@ #include "hw/remote/iohub.h" #include "hw/remote/iommu.h" #include "hw/qdev-core.h" -#include "hw/remote/iommu.h" #include "hw/remote/vfio-user-obj.h" #include "hw/pci/msi.h" diff --git a/hw/remote/remote-obj.c b/hw/remote/remote-obj.c index 333e5ac443..65b6f7cc86 100644 --- a/hw/remote/remote-obj.c +++ b/hw/remote/remote-obj.c @@ -12,7 +12,6 @@ #include "qemu/error-report.h" #include "qemu/notify.h" #include "qom/object_interfaces.h" -#include "hw/qdev-core.h" #include "io/channel.h" #include "hw/qdev-core.h" #include "hw/remote/machine.h" diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c index bc1192b7ae..ba612a151d 100644 --- a/hw/rtc/mc146818rtc.c +++ b/hw/rtc/mc146818rtc.c @@ -43,7 +43,6 @@ #include "qapi/error.h" #include "qapi/qapi-events-misc.h" #include "qapi/visitor.h" -#include "hw/rtc/mc146818rtc_regs.h" //#define DEBUG_CMOS //#define DEBUG_COALESCED diff --git a/hw/s390x/virtio-ccw-serial.c b/hw/s390x/virtio-ccw-serial.c index bf8057880f..8f8d2302f8 100644 --- a/hw/s390x/virtio-ccw-serial.c +++ b/hw/s390x/virtio-ccw-serial.c @@ -15,7 +15,6 @@ #include "hw/qdev-properties.h" #include "hw/virtio/virtio-serial.h" #include "virtio-ccw.h" -#include "hw/virtio/virtio-serial.h" #define TYPE_VIRTIO_SERIAL_CCW "virtio-serial-ccw" OBJECT_DECLARE_SIMPLE_TYPE(VirtioSerialCcw, VIRTIO_SERIAL_CCW) diff --git a/migration/postcopy-ram.c b/migration/postcopy-ram.c index b9a37ef255..8b7d1af75d 100644 --- a/migration/postcopy-ram.c +++ b/migration/postcopy-ram.c @@ -17,7 +17,6 @@ */ #include "qemu/osdep.h" -#include "qemu/rcu.h" #include "qemu/madvise.h" #include "exec/target_page.h" #include "migration.h" @@ -34,7 +33,6 @@ #include "hw/boards.h" #include "exec/ramblock.h" #include "socket.h" -#include "qemu-file.h" #include "yank_functions.h" #include "tls.h" diff --git a/softmmu/dirtylimit.c b/softmmu/dirtylimit.c index 12668555f2..c56f0f58c8 100644 --- a/softmmu/dirtylimit.c +++ b/softmmu/dirtylimit.c @@ -11,7 +11,6 @@ */ #include "qemu/osdep.h" -#include "qapi/error.h" #include "qemu/main-loop.h" #include "qapi/qapi-commands-migration.h" #include "qapi/qmp/qdict.h" diff --git a/softmmu/runstate.c b/softmmu/runstate.c index cab9f6fc07..f9ad88e6a7 100644 --- a/softmmu/runstate.c +++ b/softmmu/runstate.c @@ -41,7 +41,6 @@ #include "qapi/qapi-commands-run-state.h" #include "qapi/qapi-events-run-state.h" #include "qemu/error-report.h" -#include "qemu/log.h" #include "qemu/job.h" #include "qemu/log.h" #include "qemu/module.h" diff --git a/softmmu/vl.c b/softmmu/vl.c index 5355a7fe5a..b2ee3fee3f 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -129,7 +129,6 @@ #include "qapi/qapi-commands-misc.h" #include "qapi/qapi-visit-qom.h" #include "qapi/qapi-commands-ui.h" -#include "qapi/qmp/qdict.h" #include "block/qdict.h" #include "qapi/qmp/qerror.h" #include "sysemu/iothread.h" diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 38ced69803..72a6275665 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -12,7 +12,6 @@ #include "exec/helper-proto.h" #include "exec/helper-gen.h" -#include "exec/translator.h" #include "exec/log.h" #include "qemu/qemu-print.h" #include "fpu/softfloat.h" diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 624e6b7786..aa12bb708a 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -32,7 +32,6 @@ #include "semihosting/semihost.h" #include "trace.h" -#include "exec/translator.h" #include "exec/log.h" #include "qemu/qemu-print.h" #include "fpu_helper.h" diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 4db8b47744..7aee65a089 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -938,8 +938,6 @@ static const char * const cr_regnames[NUM_CR_REGS] = { }; #endif -#include "exec/gen-icount.h" - /* generate intermediate code for basic block 'tb'. */ static void nios2_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { diff --git a/tests/unit/test-cutils.c b/tests/unit/test-cutils.c index 2126b46391..3c4f875420 100644 --- a/tests/unit/test-cutils.c +++ b/tests/unit/test-cutils.c @@ -26,7 +26,6 @@ */ #include "qemu/osdep.h" -#include "qemu/units.h" #include "qemu/cutils.h" #include "qemu/units.h" diff --git a/ui/gtk.c b/ui/gtk.c index 4817623c8f..7f752d8b7d 100644 --- a/ui/gtk.c +++ b/ui/gtk.c @@ -53,7 +53,6 @@ #include #include "trace.h" -#include "qemu/cutils.h" #include "ui/input.h" #include "sysemu/runstate.h" #include "sysemu/sysemu.h" diff --git a/util/oslib-posix.c b/util/oslib-posix.c index fd03fd32c8..77d882e681 100644 --- a/util/oslib-posix.c +++ b/util/oslib-posix.c @@ -59,10 +59,6 @@ #include "qemu/mmap-alloc.h" -#ifdef CONFIG_DEBUG_STACK_USAGE -#include "qemu/error-report.h" -#endif - #define MAX_MEM_PREALLOC_THREAD_COUNT 16 struct MemsetThread; -- 2.39.0 From MAILER-DAEMON Mon Jan 30 08:23:18 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMU7y-00077I-Aj for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 08:23:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps 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hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, quintela@redhat.com, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v5 17/20] Fix non-first inclusions of qemu/osdep.h Date: Mon, 30 Jan 2023 14:21:53 +0100 Message-Id: <20230130132156.1868019-18-armbru@redhat.com> In-Reply-To: <20230130132156.1868019-1-armbru@redhat.com> References: <20230130132156.1868019-1-armbru@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Scanned-By: MIMEDefang 3.1 on 10.11.54.1 Received-SPF: pass client-ip=170.10.129.124; envelope-from=armbru@redhat.com; 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Signed-off-by: Markus Armbruster Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Michael S. Tsirkin Reviewed-by: Juan Quintela --- audio/sndioaudio.c | 2 +- backends/hostmem-epc.c | 2 +- block/export/vduse-blk.c | 2 +- hw/hyperv/syndbg.c | 2 +- util/async-teardown.c | 12 ++++-------- 5 files changed, 8 insertions(+), 12 deletions(-) diff --git a/audio/sndioaudio.c b/audio/sndioaudio.c index 632b0e3825..3fde01fdbd 100644 --- a/audio/sndioaudio.c +++ b/audio/sndioaudio.c @@ -14,9 +14,9 @@ * to recording, which is what guest systems expect. */ +#include "qemu/osdep.h" #include #include -#include "qemu/osdep.h" #include "qemu/main-loop.h" #include "audio.h" #include "trace.h" diff --git a/backends/hostmem-epc.c b/backends/hostmem-epc.c index 037292d267..4e162d6789 100644 --- a/backends/hostmem-epc.c +++ b/backends/hostmem-epc.c @@ -9,9 +9,9 @@ * This work is licensed under the terms of the GNU GPL, version 2 or later. * See the COPYING file in the top-level directory. */ -#include #include "qemu/osdep.h" +#include #include "qom/object_interfaces.h" #include "qapi/error.h" #include "sysemu/hostmem.h" diff --git a/block/export/vduse-blk.c b/block/export/vduse-blk.c index 350d6fdaf0..f7ae44e3ce 100644 --- a/block/export/vduse-blk.c +++ b/block/export/vduse-blk.c @@ -10,9 +10,9 @@ * later. See the COPYING file in the top-level directory. */ +#include "qemu/osdep.h" #include -#include "qemu/osdep.h" #include "qapi/error.h" #include "block/export.h" #include "qemu/error-report.h" diff --git a/hw/hyperv/syndbg.c b/hw/hyperv/syndbg.c index 16d04cfdc6..94fe1b534b 100644 --- a/hw/hyperv/syndbg.c +++ b/hw/hyperv/syndbg.c @@ -5,8 +5,8 @@ * See the COPYING file in the top-level directory. */ -#include "qemu/ctype.h" #include "qemu/osdep.h" +#include "qemu/ctype.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" #include "qemu/sockets.h" diff --git a/util/async-teardown.c b/util/async-teardown.c index 62bfce1b3c..62cdeb0f20 100644 --- a/util/async-teardown.c +++ b/util/async-teardown.c @@ -10,16 +10,12 @@ * option) any later version. See the COPYING file in the top-level directory. * */ -#include -#include -#include -#include -#include -#include -#include -#include #include "qemu/osdep.h" +#include +#include +#include + #include "qemu/async-teardown.h" #ifdef _SC_THREAD_STACK_MIN -- 2.39.0 From MAILER-DAEMON Mon Jan 30 09:05:14 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMUmY-00052B-5a for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 09:05:14 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMUmW-0004yC-BB for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 09:05:12 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMUmT-00076E-Fn for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 09:05:12 -0500 Received: by mail-wr1-x434.google.com with SMTP id a3so4461760wrt.6 for ; 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Mon, 30 Jan 2023 06:05:04 -0800 (PST) MIME-Version: 1.0 References: <20221223180016.2068508-1-christoph.muellner@vrull.eu> <20221223180016.2068508-2-christoph.muellner@vrull.eu> In-Reply-To: From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Mon, 30 Jan 2023 15:04:52 +0100 Message-ID: Subject: Re: [PATCH v2 01/15] RISC-V: Adding XTheadCmo ISA extension To: Alistair Francis Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 14:05:12 -0000 On Sun, Jan 29, 2023 at 11:40 PM Alistair Francis wr= ote: > > On Wed, Jan 25, 2023 at 5:51 AM Christoph M=C3=BCllner > wrote: > > > > > > > > On Tue, Jan 24, 2023 at 6:31 PM Christoph M=C3=BCllner wrote: > >> > >> > >> > >> On Mon, Jan 23, 2023 at 11:50 PM Alistair Francis wrote: > >>> > >>> On Sat, Dec 24, 2022 at 4:09 AM Christoph Muellner > >>> wrote: > >>> > > >>> > From: Christoph M=C3=BCllner > >>> > > >>> > This patch adds support for the XTheadCmo ISA extension. > >>> > To avoid interfering with standard extensions, decoder and translat= ion > >>> > are in its own xthead* specific files. > >>> > Future patches should be able to easily add additional T-Head exten= sion. > >>> > > >>> > The implementation does not have much functionality (besides accept= ing > >>> > the instructions and not qualifying them as illegal instructions if > >>> > the hart executes in the required privilege level for the instructi= on), > >>> > as QEMU does not model CPU caches and instructions are documented > >>> > to not raise any exceptions. > >>> > > >>> > Changes in v2: > >>> > - Add ISA_EXT_DATA_ENTRY() > >>> > - Explicit test for PRV_U > >>> > - Encapsule access to env-priv in inline function > >>> > - Use single decoder for XThead extensions > >>> > > >>> > Co-developed-by: LIU Zhiwei > >>> > Signed-off-by: Christoph M=C3=BCllner > >>> > --- > >>> > target/riscv/cpu.c | 2 + > >>> > target/riscv/cpu.h | 1 + > >>> > target/riscv/insn_trans/trans_xthead.c.inc | 89 ++++++++++++++++++= ++++ > >>> > target/riscv/meson.build | 1 + > >>> > target/riscv/translate.c | 15 +++- > >>> > target/riscv/xthead.decode | 38 +++++++++ > >>> > 6 files changed, 143 insertions(+), 3 deletions(-) > >>> > create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc > >>> > create mode 100644 target/riscv/xthead.decode > >>> > > >>> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > >>> > index 6fe176e483..a90b82c5c5 100644 > >>> > --- a/target/riscv/cpu.c > >>> > +++ b/target/riscv/cpu.c > >>> > @@ -108,6 +108,7 @@ static const struct isa_ext_data isa_edata_arr[= ] =3D { > >>> > ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svi= nval), > >>> > ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svn= apot), > >>> > ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpb= mt), > >>> > + ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_x= theadcmo), > >>> > ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0,= ext_XVentanaCondOps), > >>> > }; > >>> > > >>> > @@ -1060,6 +1061,7 @@ static Property riscv_cpu_extensions[] =3D { > >>> > DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), > >>> > > >>> > /* Vendor-specific custom extensions */ > >>> > + DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, fal= se), > >>> > DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentana= CondOps, false), > >>> > > >>> > /* These are experimental so mark with 'x-' */ > >>> > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > >>> > index 443d15a47c..ad1c19f870 100644 > >>> > --- a/target/riscv/cpu.h > >>> > +++ b/target/riscv/cpu.h > >>> > @@ -465,6 +465,7 @@ struct RISCVCPUConfig { > >>> > uint64_t mimpid; > >>> > > >>> > /* Vendor-specific custom extensions */ > >>> > + bool ext_xtheadcmo; > >>> > bool ext_XVentanaCondOps; > >>> > > >>> > uint8_t pmu_num; > >>> > diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/ri= scv/insn_trans/trans_xthead.c.inc > >>> > new file mode 100644 > >>> > index 0000000000..00e75c7dca > >>> > --- /dev/null > >>> > +++ b/target/riscv/insn_trans/trans_xthead.c.inc > >>> > @@ -0,0 +1,89 @@ > >>> > +/* > >>> > + * RISC-V translation routines for the T-Head vendor extensions (x= thead*). > >>> > + * > >>> > + * Copyright (c) 2022 VRULL GmbH. > >>> > + * > >>> > + * This program is free software; you can redistribute it and/or m= odify it > >>> > + * under the terms and conditions of the GNU General Public Licens= e, > >>> > + * version 2 or later, as published by the Free Software Foundatio= n. > >>> > + * > >>> > + * This program is distributed in the hope it will be useful, but = WITHOUT > >>> > + * ANY WARRANTY; without even the implied warranty of MERCHANTABIL= ITY or > >>> > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public L= icense for > >>> > + * more details. > >>> > + * > >>> > + * You should have received a copy of the GNU General Public Licen= se along with > >>> > + * this program. If not, see . > >>> > + */ > >>> > + > >>> > +#define REQUIRE_XTHEADCMO(ctx) do { \ > >>> > + if (!ctx->cfg_ptr->ext_xtheadcmo) { \ > >>> > + return false; \ > >>> > + } \ > >>> > +} while (0) > >>> > + > >>> > +/* XTheadCmo */ > >>> > + > >>> > +static inline int priv_level(DisasContext *ctx) > >>> > +{ > >>> > +#ifdef CONFIG_USER_ONLY > >>> > + return PRV_U; > >>> > +#else > >>> > + /* Priv level equals mem_idx -- see cpu_mmu_index. */ > >>> > + return ctx->mem_idx; > >>> > >>> This should be ANDed with TB_FLAGS_PRIV_MMU_MASK as sometimes this ca= n > >>> include hypervisor priv access information > >> > >> > >> Ok. > >> > >>> > >>> > >>> > +#endif > >>> > +} > >>> > + > >>> > +#define REQUIRE_PRIV_MHSU(ctx) \ > >>> > +do { \ > >>> > + int priv =3D priv_level(ctx); = \ > >>> > + if (!(priv =3D=3D PRV_M || = \ > >>> > + priv =3D=3D PRV_H || = \ > >>> > >>> PRV_H isn't used > >>> > >>> > + priv =3D=3D PRV_S || = \ > >>> > + priv =3D=3D PRV_U)) { = \ > >>> > + return false; \ > >>> > >>> When would this not be the case? > >> > >> > >> Ok, I will make this a macro that expands to nothing (and a comment). > >> > >>> > >>> > >>> > + } \ > >>> > +} while (0) > >>> > + > >>> > +#define REQUIRE_PRIV_MHS(ctx) \ > >>> > +do { \ > >>> > + int priv =3D priv_level(ctx); = \ > >>> > + if (!(priv =3D=3D PRV_M || = \ > >>> > + priv =3D=3D PRV_H || = \ > >>> > >>> Also not used > >> > >> > >> Ok, I will remove the PRV_H. > >> > >>> > >>> > >>> > + priv =3D=3D PRV_S)) { = \ > >>> > + return false; \ > >>> > + } \ > >>> > +} while (0) > >>> > + > >>> > +#define NOP_PRIVCHECK(insn, extcheck, privcheck) \ > >>> > +static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn * a) \ > >>> > +{ \ > >>> > + (void) a; \ > >>> > + extcheck(ctx); \ > >>> > + privcheck(ctx); \ > >>> > + return true; \ > >>> > +} > >>> > + > >>> > +NOP_PRIVCHECK(th_dcache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > >>> > +NOP_PRIVCHECK(th_dcache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS= ) > >>> > +NOP_PRIVCHECK(th_dcache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > >>> > +NOP_PRIVCHECK(th_dcache_cpa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > >>> > +NOP_PRIVCHECK(th_dcache_cipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > >>> > +NOP_PRIVCHECK(th_dcache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > >>> > +NOP_PRIVCHECK(th_dcache_cva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) > >>> > +NOP_PRIVCHECK(th_dcache_civa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU= ) > >>> > +NOP_PRIVCHECK(th_dcache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) > >>> > +NOP_PRIVCHECK(th_dcache_csw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > >>> > +NOP_PRIVCHECK(th_dcache_cisw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > >>> > +NOP_PRIVCHECK(th_dcache_isw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > >>> > +NOP_PRIVCHECK(th_dcache_cpal1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS= ) > >>> > +NOP_PRIVCHECK(th_dcache_cval1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS= ) > >>> > + > >>> > +NOP_PRIVCHECK(th_icache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > >>> > +NOP_PRIVCHECK(th_icache_ialls, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS= ) > >>> > +NOP_PRIVCHECK(th_icache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS) > >>> > +NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHSU) > >>> > + > >>> > +NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS= ) > >>> > +NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MH= S) > >>> > +NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MHS= ) > >>> > diff --git a/target/riscv/meson.build b/target/riscv/meson.build > >>> > index ba25164d74..5dee37a242 100644 > >>> > --- a/target/riscv/meson.build > >>> > +++ b/target/riscv/meson.build > >>> > @@ -2,6 +2,7 @@ > >>> > gen =3D [ > >>> > decodetree.process('insn16.decode', extra_args: ['--static-decod= e=3Ddecode_insn16', '--insnwidth=3D16']), > >>> > decodetree.process('insn32.decode', extra_args: '--static-decode= =3Ddecode_insn32'), > >>> > + decodetree.process('xthead.decode', extra_args: '--static-decode= =3Ddecode_xthead'), > >>> > decodetree.process('XVentanaCondOps.decode', extra_args: '--stat= ic-decode=3Ddecode_XVentanaCodeOps'), > >>> > ] > >>> > > >>> > diff --git a/target/riscv/translate.c b/target/riscv/translate.c > >>> > index db123da5ec..14d9116975 100644 > >>> > --- a/target/riscv/translate.c > >>> > +++ b/target/riscv/translate.c > >>> > @@ -125,13 +125,18 @@ static bool always_true_p(DisasContext *ctx = __attribute__((__unused__))) > >>> > return true; > >>> > } > >>> > > >>> > +static bool has_xthead_p(DisasContext *ctx __attribute__((__unuse= d__))) > >>> > +{ > >>> > + return ctx->cfg_ptr->ext_xtheadcmo; > >>> > +} > >>> > + > >>> > #define MATERIALISE_EXT_PREDICATE(ext) \ > >>> > static bool has_ ## ext ## _p(DisasContext *ctx) \ > >>> > { \ > >>> > return ctx->cfg_ptr->ext_ ## ext ; \ > >>> > } > >>> > > >>> > -MATERIALISE_EXT_PREDICATE(XVentanaCondOps); > >>> > +MATERIALISE_EXT_PREDICATE(XVentanaCondOps) > >>> > >>> Do we need this change? > >> > >> > >> It is indeed a drive-by cleanup, that is not necessary. > >> In v1 we were using this macro, therefore it made sense back then. > >> Will be dropped. > >> > >>> > >>> > >>> > > >>> > #ifdef TARGET_RISCV32 > >>> > #define get_xl(ctx) MXL_RV32 > >>> > @@ -732,6 +737,10 @@ static int ex_rvc_shiftri(DisasContext *ctx, i= nt imm) > >>> > /* Include the auto-generated decoder for 32 bit insn */ > >>> > #include "decode-insn32.c.inc" > >>> > > >>> > +/* Include decoders for factored-out extensions */ > >>> > +#include "decode-xthead.c.inc" > >>> > +#include "decode-XVentanaCondOps.c.inc" > >>> > + > >>> > static bool gen_logic_imm_fn(DisasContext *ctx, arg_i *a, > >>> > void (*func)(TCGv, TCGv, target_long)= ) > >>> > { > >>> > @@ -1033,12 +1042,11 @@ static uint32_t opcode_at(DisasContextBase = *dcbase, target_ulong pc) > >>> > #include "insn_trans/trans_rvk.c.inc" > >>> > #include "insn_trans/trans_privileged.c.inc" > >>> > #include "insn_trans/trans_svinval.c.inc" > >>> > +#include "insn_trans/trans_xthead.c.inc" > >>> > #include "insn_trans/trans_xventanacondops.c.inc" > >>> > > >>> > /* Include the auto-generated decoder for 16 bit insn */ > >>> > #include "decode-insn16.c.inc" > >>> > -/* Include decoders for factored-out extensions */ > >>> > -#include "decode-XVentanaCondOps.c.inc" > >>> > >>> Can we not leave these at the bottom? > >> > >> > >> Ok. > > > > > > I got reminded again, why this is like it is: > > The decoder code needs to be included before the translation functions, > > because the translation functions use types that are defined in the gen= erated decoder code. > > And I wanted to keep all vendor extensions together. > > Ah ok, why not keep each extension together instead, like this: > > #include "decode-xthead.c.inc" > #include "insn_trans/trans_xthead.c.inc" > > #include "decode-XVentanaCondOps.c.inc" In v3 I had the decode included below decode-insn32.c.inc. And the trans_xthead.c.inc was at the end of the trans* includes. For v4 I will move the decode down to the inclusion of trans_xthead.c.inc. v4 will be sent out, once we have addressed the review comments from Richar= d. Thanks, Christoph > > > Alistair From MAILER-DAEMON Mon Jan 30 09:05:26 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMUmj-0005Mt-QU for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 09:05:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMUmi-0005Jm-34 for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 09:05:24 -0500 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMUmg-00079y-7T for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 09:05:23 -0500 Received: by mail-wr1-x42f.google.com with SMTP id y1so11177045wru.2 for ; Mon, 30 Jan 2023 06:05:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=4M4xtfnQMpx7jd/celDbU8GRpcb2Xrqa0e2A+umGAi0=; b=YuuIZWvRDP9+kd8cc+Mm2pGTX1ivhW8v9z1rZh3jTLYpEeSYbXg9VSovCpcmnoBT1y 079m/xiAbxmgqjR7OfQ8Nu/RfBoWPZBXaIw3Lb3muU91qfCArGLsNOtWlEAvVwErR5re Uf15v7TU2XDB5TfXU9oD/Oct6rF2v3y1pPbBJp/WgjxHbkyZCGoITIa6nzL3xAv4LwyX 5K1G7lAFttONHLiU2dT5r0qsXHpursaUphuPKZIozqt6UPylshn1+RyjjpKYD6k2v9nT MrLvXvWV4k7PD7VMdB+ovEXZt4eQY/ZqDZGuK6IeAbm805GXhtjh3nl7Z4wo4KjdhbqG 8Msg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=4M4xtfnQMpx7jd/celDbU8GRpcb2Xrqa0e2A+umGAi0=; b=ZOoxCzlB9fpoagq8yVTp3hfYiGsM4wSV2qw2TN9o3UbnFS/RxQRKsrXjCHgr1bDVnJ y9bZyivjl7teWYOzG2amin0kdGa+cSwP595wg1+3L/JoRl9eN/mD4MRMHqOFXT8bf3WP 4ddGkc9G1PTBMYG43kUxgFE8kWFvr0kybsoUMKtFRf16x3bs4Aji0RysCjZ7TFDXvIT0 6xo2K9BtpUWzYSkrLWjSqjfiqgrisjsLJtTDruG/6e0FwI8LLU8oIO7Bxp2BoVN5VfBU +r1w40vNLuOkhJcI42vVTxxha52dcDp5YRLi+zA0Ax/B9fhJ74hR+DFTpjkh/3v5s0QM K4fg== X-Gm-Message-State: AO0yUKVHPsh/MjbjMxltDaH+10tOfLM+UIzdb5Pvwlpm6g2wTjI0t2y/ fNa2jrKotd7b5ccO8cLlExoaRepZlXCXwXjpbrMLWQ== X-Google-Smtp-Source: AK7set89Q8f0tQCO7L8KnaMx/wvZRhD+1hX2+UqTaA/zM5rpfc4hs3mWJFiXRzdMH89qrFWpxwQdAGtysgolmdggWuQ= X-Received: by 2002:a5d:6a8b:0:b0:2bf:cd55:c9e with SMTP id s11-20020a5d6a8b000000b002bfcd550c9emr355968wru.674.1675087520430; Mon, 30 Jan 2023 06:05:20 -0800 (PST) MIME-Version: 1.0 References: <20230124195945.181842-1-christoph.muellner@vrull.eu> <20230124195945.181842-3-christoph.muellner@vrull.eu> <8a81e02c-5bb7-a82b-be16-e93362169a44@linaro.org> In-Reply-To: <8a81e02c-5bb7-a82b-be16-e93362169a44@linaro.org> From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Mon, 30 Jan 2023 15:05:08 +0100 Message-ID: Subject: Re: [PATCH v3 02/14] RISC-V: Adding XTheadSync ISA extension To: Richard Henderson Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Palmer Dabbelt , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: multipart/alternative; boundary="0000000000009f9df405f37bb43e" Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HTML_MESSAGE=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 14:05:24 -0000 --0000000000009f9df405f37bb43e Content-Type: text/plain; charset="UTF-8" On Tue, Jan 24, 2023 at 9:21 PM Richard Henderson < richard.henderson@linaro.org> wrote: > On 1/24/23 09:59, Christoph Muellner wrote: > > +static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas > *a) > > +{ > > + (void) a; > > + REQUIRE_XTHEADSYNC(ctx); > > + > > +#ifndef CONFIG_USER_ONLY > > + REQUIRE_PRIV_MS(ctx); > > + decode_save_opc(ctx); > > + gen_helper_tlb_flush_all(cpu_env); > > Why are you using decode_save_opc() when helper_tlb_flush_all() cannot > raise an exception? > No particular reason. Will be dropped. Thanks, Christoph > > > r~ > --0000000000009f9df405f37bb43e Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable


=
On Tue, Jan 24, 2023 at 9:21 PM Richa= rd Henderson <richard.he= nderson@linaro.org> wrote:
On 1/24/23 09:59, Christoph Muellner wrote:
> +static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vma= s *a)
> +{
> +=C2=A0 =C2=A0 (void) a;
> +=C2=A0 =C2=A0 REQUIRE_XTHEADSYNC(ctx);
> +
> +#ifndef CONFIG_USER_ONLY
> +=C2=A0 =C2=A0 REQUIRE_PRIV_MS(ctx);
> +=C2=A0 =C2=A0 decode_save_opc(ctx);
> +=C2=A0 =C2=A0 gen_helper_tlb_flush_all(cpu_env);

Why are you using decode_save_opc() when helper_tlb_flush_all() cannot rais= e an exception?

No particular reason.
Will be dropped.

Thanks,
Christ= oph
=C2=A0


r~
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Mon, 30 Jan 2023 06:12:35 -0800 (PST) X-Google-Smtp-Source: AMrXdXs9TAXpE01r9HA8uSktOWQsibC9/rxGSG9jlES6a9brbM56rTswWAF4+QxzlicTpQW/dLjj2A== X-Received: by 2002:a05:600c:1c2a:b0:3cf:d0b1:8aa1 with SMTP id j42-20020a05600c1c2a00b003cfd0b18aa1mr48027839wms.0.1675087955281; Mon, 30 Jan 2023 06:12:35 -0800 (PST) Received: from redhat.com ([46.136.252.173]) by smtp.gmail.com with ESMTPSA id o25-20020a1c7519000000b003daf6e3bc2fsm24805883wmc.1.2023.01.30.06.12.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 06:12:34 -0800 (PST) From: Juan Quintela To: Markus Armbruster Cc: qemu-devel@nongnu.org, richard.henderson@linaro.org, pbonzini@redhat.com, kwolf@redhat.com, hreitz@redhat.com, imp@bsdimp.com, kevans@freebsd.org, berrange@redhat.com, groug@kaod.org, qemu_oss@crudebyte.com, mst@redhat.com, philmd@linaro.org, peter.maydell@linaro.org, alistair@alistair23.me, jasowang@redhat.com, jonathan.cameron@huawei.com, kbastian@mail.uni-paderborn.de, dgilbert@redhat.com, michael.roth@amd.com, kkostiuk@redhat.com, tsimpson@quicinc.com, palmer@dabbelt.com, bin.meng@windriver.com, qemu-block@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org Subject: Re: [PATCH v5 04/20] scripts/clean-includes: Improve --git commit message In-Reply-To: <20230130132156.1868019-5-armbru@redhat.com> (Markus Armbruster's message of "Mon, 30 Jan 2023 14:21:40 +0100") References: <20230130132156.1868019-1-armbru@redhat.com> <20230130132156.1868019-5-armbru@redhat.com> User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/28.2 (gnu/linux) Reply-To: quintela@redhat.com Date: Mon, 30 Jan 2023 15:12:33 +0100 Message-ID: <87sffsnmb2.fsf@secure.mitica> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain Received-SPF: pass client-ip=170.10.133.124; envelope-from=quintela@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 14:12:43 -0000 Markus Armbruster wrote: > The script drops #include "qemu/osdep.h" from headers. Mention it in > the commit message it uses for --git. > > Signed-off-by: Markus Armbruster > --- > scripts/clean-includes | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/scripts/clean-includes b/scripts/clean-includes > index f0466a6262..f9722c3aec 100755 > --- a/scripts/clean-includes > +++ b/scripts/clean-includes > @@ -193,8 +193,8 @@ if [ "$GIT" = "yes" ]; then > git commit --signoff -F - < $GITSUBJ: Clean up includes > > -Clean up includes so that osdep.h is included first and headers > -which it implies are not included manually. > +Clean up includes so that qemu/osdep.h is included first in .c, and > +not in .h, and headers which it implies are not included manually. I give a tree. Clean up includes so qemu/osdep.h is never used in .h files. It makes sure that qemu/osdep.h is only used in .c files. Once there, it assures that .h files already included in qemu/osdep.h are not included a second time on the .c file. What do you think? And yes, not using "include" the "include files" is .... interesting/confusing/.... Anyways, if you preffer old text or net one. Reviewed-by: Juan Quintela From MAILER-DAEMON Mon Jan 30 12:16:33 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMXlg-0005nG-BS for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 12:16:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMXlQ-0005gs-EQ for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 12:16:22 -0500 Received: from mail-ot1-x331.google.com ([2607:f8b0:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMXlO-00042Y-Dr for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 12:16:16 -0500 Received: by mail-ot1-x331.google.com with SMTP id cm26-20020a056830651a00b00684e5c0108dso4701907otb.9 for ; Mon, 30 Jan 2023 09:16:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :from:to:cc:subject:date:message-id:reply-to; bh=Z60Bw3RVBRyw8SQ50rkyv54qMMhpqRTl0erlD+9/yME=; b=TUhG2KJZYK2qoRxAGTsA0ByU3Tbbxmz1S7hrE1iTw/Az0vtCFmdc/J0gXCJw5K490C jxwgq3wq+9FXSCY2CvFmwzu3dHcyih2zMG8gqC7FRpkGMdru7F9di7MYblYqbF8m4OCp 34TP9dKaQ/2SpkbDNVDxVZAMhMjSjexCAxm2VlEeM6W45OtV11YupqfgA0YzACXndF6X //tx88CK4+J+nhgipUWWWaCTimRKPcSBtSsv9nVpVrpakU/RzB0X3yoVWgJEo85Dw2wk Seue7amGt6/BIUNClZQpiig8kJvFepudIyyYFf+PTQXIdWITUFvjxIUM4fxAE/WA2vW5 cw2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:in-reply-to:from:references:cc:to :content-language:subject:user-agent:mime-version:date:message-id :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Z60Bw3RVBRyw8SQ50rkyv54qMMhpqRTl0erlD+9/yME=; b=dp3EBJTp5URvBlKOp8dq+XHX7Fg+WE9d6Ha7dSagR0UKNtsvQQTUVwsNnbryqT3EsL wBlHzSdJJQM753S9nCW80r7LGR17JK+se5XjCG4NVVlsdKep3SPTgwCVi3MfisV4HunB 3BM9HpaTIrS4FuhmdlzDPb2k45RX8IgaDbr2GNe10pgeq5+UajcTazJgaYq5hzagER/p lcJQ0kLSiQ/Gd5iOzGU5Ya9rzNfsWejfLjVkdU0Y4Ky7OznfOEQsJOCtyqWUmyqlVvnm RPzhixNuLMBZbFIjfB12TlCnWfBtzEQbo5OKgPHGLv0icz0mkMw6re9vuqVEmfwSjzRO eajA== X-Gm-Message-State: AFqh2kof6CUPp1NiIwiSRpVWFfXckm4HGYD4HbU6MZNu5mGmimob0NYJ bmybrHa2twv+ARY5K4k3BHTYbw== X-Google-Smtp-Source: AMrXdXvBZkAR1ZT78Xi93QulOAHuda26J9KwEYUL3L7bvPuvkO6vKTKvo2VBaVwA8l/cXSnC97YyZg== X-Received: by 2002:a9d:7658:0:b0:66c:cb4d:3498 with SMTP id o24-20020a9d7658000000b0066ccb4d3498mr23213333otl.27.1675098971844; Mon, 30 Jan 2023 09:16:11 -0800 (PST) Received: from [192.168.68.107] (200-148-13-157.dsl.telesp.net.br. [200.148.13.157]) by smtp.gmail.com with ESMTPSA id h1-20020a9d5541000000b00684c5211c58sm5586642oti.60.2023.01.30.09.16.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Jan 2023 09:16:10 -0800 (PST) Message-ID: <793f7432-4592-98a4-34e9-472c185be297@ventanamicro.com> Date: Mon, 30 Jan 2023 14:16:07 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH v4 3/3] hw/riscv: change riscv_compute_fdt_addr() semantics Content-Language: en-US To: Bin Meng Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com References: <20230126135219.1054658-1-dbarboza@ventanamicro.com> <20230126135219.1054658-4-dbarboza@ventanamicro.com> From: Daniel Henrique Barboza In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x331.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 17:16:25 -0000 On 1/29/23 02:45, Bin Meng wrote: > On Thu, Jan 26, 2023 at 9:54 PM Daniel Henrique Barboza > wrote: >> >> As it is now, riscv_compute_fdt_addr() is receiving a dram_base, a >> mem_size (which is defaulted to MachineState::ram_size in all boards) >> and the FDT pointer. And it makes a very important assumption: the DRAM >> interval dram_base + mem_size is contiguous. This is indeed the case for >> most boards that uses a FDT. > > s/uses/use > >> >> The Icicle Kit board works with 2 distinct RAM banks that are separated >> by a gap. We have a lower bank with 1GiB size, a gap follows, then at >> 64GiB the high memory starts. MachineClass::default_ram_size for this >> board is set to 1.5Gb, and machine_init() is enforcing it as minimal RAM >> size, meaning that there we'll always have at least 512 MiB in the Hi >> RAM area. >> >> Using riscv_compute_fdt_addr() in this board is weird because not only >> the board has sparse RAM, and it's calling it using the base address of >> the Lo RAM area, but it's also using a mem_size that we have guarantees >> that it will go up to the Hi RAM. All the function assumptions doesn't >> work for this board. >> >> In fact, what makes the function works at all in this case is a >> coincidence. Commit 1a475d39ef54 introduced a 3GB boundary for the FDT, >> down from 4Gb, that is enforced if dram_base is lower than 3072 MiB. For >> the Icicle Kit board, memmap[MICROCHIP_PFSOC_DRAM_LO].base is 0x80000000 >> (2 Gb) and it has a 1Gb size, so it will fall in the conditions to put >> the FDT under a 3Gb address, which happens to be exactly at the end of >> DRAM_LO. If the base address of the Lo area started later than 3Gb this >> function would be unusable by the board. Changing any assumptions inside >> riscv_compute_fdt_addr() can also break it by accident as well. >> >> Let's change riscv_compute_fdt_addr() semantics to be appropriate to the >> Icicle Kit board and for future boards that might have sparse RAM >> topologies to worry about: >> >> - relieve the condition that the dram_base + mem_size area is contiguous, >> since this is already not the case today; >> >> - receive an extra 'dram_size' size attribute that refers to a contiguous >> RAM block that the board wants the FDT to reside on. >> >> Together with 'mem_size' and 'fdt', which are now now being consumed by a >> MachineState pointer, we're able to make clear assumptions based on the >> DRAM block and total mem_size available to ensure that the FDT will be put >> in a valid RAM address. >> > > Well written commit message. Thanks! > >> Signed-off-by: Daniel Henrique Barboza >> --- >> hw/riscv/boot.c | 38 ++++++++++++++++++++++++++------------ >> hw/riscv/microchip_pfsoc.c | 3 ++- >> hw/riscv/sifive_u.c | 3 ++- >> hw/riscv/spike.c | 3 ++- >> hw/riscv/virt.c | 3 ++- >> include/hw/riscv/boot.h | 4 ++-- >> 6 files changed, 36 insertions(+), 18 deletions(-) >> >> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c >> index a6f7b8ae8e..8f4991480b 100644 >> --- a/hw/riscv/boot.c >> +++ b/hw/riscv/boot.c >> @@ -284,33 +284,47 @@ out: >> } >> >> /* >> - * The FDT should be put at the farthest point possible to >> - * avoid overwriting it with the kernel/initrd. >> + * This function makes an assumption that the DRAM interval >> + * 'dram_base' + 'dram_size' is contiguous. >> * >> - * This function makes an assumption that the DRAM is >> - * contiguous. It also cares about 32-bit systems and >> - * will limit fdt_addr to be addressable by them even for >> - * 64-bit CPUs. >> + * Considering that 'dram_end' is the lowest value between >> + * the end of the DRAM block and MachineState->ram_size, the >> + * FDT location will vary according to 'dram_base': >> + * >> + * - if 'dram_base' is less that 3072 MiB, the FDT will be >> + * put at the lowest value between 3072 MiB and 'dram_end'; >> + * >> + * - if 'dram_base' is higher than 3072 MiB, the FDT will be >> + * put at 'dram_end'. >> * >> * The FDT is fdt_packed() during the calculation. >> */ >> -uint32_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size, >> - void *fdt) >> +hwaddr riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, > > Using hwaddr to represent a size looks weird. Although technically > they are the same ... I would leave this as it is. I'll leave it as it was back in patch 2 (uint64_t). > >> + MachineState *ms) >> { >> - uint64_t temp; >> - hwaddr dram_end = dram_base + mem_size; >> - int ret = fdt_pack(fdt); >> + int ret = fdt_pack(ms->fdt); >> + hwaddr dram_end, temp; >> int fdtsize; >> >> /* Should only fail if we've built a corrupted tree */ >> g_assert(ret == 0); >> >> - fdtsize = fdt_totalsize(fdt); >> + fdtsize = fdt_totalsize(ms->fdt); >> if (fdtsize <= 0) { >> error_report("invalid device-tree"); >> exit(1); >> } >> >> + /* >> + * A dram_size == 0, usually from a MemMapEntry[].size element, >> + * means that the DRAM block goes all the way to ms->ram_size. >> + */ >> + if (dram_size == 0x0) { >> + dram_end = dram_base + ms->ram_size; >> + } else { >> + dram_end = dram_base + MIN(ms->ram_size, dram_size); >> + } > > How about: > > g_assert(dram_size < ms->ram_size); I don't believe that dram_size > ms->ram_size should be an error. A board can have a declared MemMapEntry.size that is larger than its current setting of ms->ram_size. > dram_end = dram_base + (dram_size ? dram_size : ms->ram_size); I can change the if/else statement up there for a ternary: dram_end = dram_base + (dram_size ? ms->ram_size : MIN(ms->ram_size, dram_size)) Thanks, Daniel > >> + >> /* >> * We should put fdt as far as possible to avoid kernel/initrd overwriting >> * its content. But it should be addressable by 32 bit system as well. >> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c >> index a30203db85..e81bbd12df 100644 >> --- a/hw/riscv/microchip_pfsoc.c >> +++ b/hw/riscv/microchip_pfsoc.c >> @@ -634,7 +634,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) >> >> /* Compute the fdt load address in dram */ >> fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base, >> - machine->ram_size, machine->fdt); >> + memmap[MICROCHIP_PFSOC_DRAM_LO].size, >> + machine); >> riscv_load_fdt(fdt_load_addr, machine->fdt); >> >> /* Load the reset vector */ >> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c >> index 6bbdbe5fb7..ad3bb35b34 100644 >> --- a/hw/riscv/sifive_u.c >> +++ b/hw/riscv/sifive_u.c >> @@ -609,7 +609,8 @@ static void sifive_u_machine_init(MachineState *machine) >> } >> >> fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, >> - machine->ram_size, machine->fdt); >> + memmap[SIFIVE_U_DEV_DRAM].size, >> + machine); >> riscv_load_fdt(fdt_load_addr, machine->fdt); >> >> if (!riscv_is_32bit(&s->soc.u_cpus)) { >> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c >> index ceebe34c5f..b5979eddd6 100644 >> --- a/hw/riscv/spike.c >> +++ b/hw/riscv/spike.c >> @@ -317,7 +317,8 @@ static void spike_board_init(MachineState *machine) >> } >> >> fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, >> - machine->ram_size, machine->fdt); >> + memmap[SPIKE_DRAM].size, >> + machine); >> riscv_load_fdt(fdt_load_addr, machine->fdt); >> >> /* load the reset vector */ >> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c >> index 43fca597f0..f079a30b60 100644 >> --- a/hw/riscv/virt.c >> +++ b/hw/riscv/virt.c >> @@ -1293,7 +1293,8 @@ static void virt_machine_done(Notifier *notifier, void *data) >> } >> >> fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, >> - machine->ram_size, machine->fdt); >> + memmap[VIRT_DRAM].size, >> + machine); >> riscv_load_fdt(fdt_load_addr, machine->fdt); >> >> /* load the reset vector */ >> diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h >> index 7babd669c7..a6099c2dc6 100644 >> --- a/include/hw/riscv/boot.h >> +++ b/include/hw/riscv/boot.h >> @@ -48,8 +48,8 @@ target_ulong riscv_load_kernel(MachineState *machine, >> target_ulong firmware_end_addr, >> bool load_initrd, >> symbol_fn_t sym_cb); >> -uint32_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, >> - void *fdt); >> +hwaddr riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, >> + MachineState *ms); >> void riscv_load_fdt(hwaddr fdt_addr, void *fdt); >> void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, >> hwaddr saddr, >> -- > > Regards, > Bin From MAILER-DAEMON Mon Jan 30 13:02:49 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMYUS-00072S-LX for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 13:02:49 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMYUQ-0006z5-C9 for qemu-riscv@nongnu.org; Mon, 30 Jan 2023 13:02:46 -0500 Received: from mail-oi1-x231.google.com ([2607:f8b0:4864:20::231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMYUN-0007OU-OD for qemu-riscv@nongnu.org; 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[200.148.13.157]) by smtp.gmail.com with ESMTPSA id n4-20020a9d4d04000000b0068bcd200247sm2104611otf.75.2023.01.30.10.02.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Jan 2023 10:02:41 -0800 (PST) Message-ID: <1a58ebfd-1ce8-2d2f-9e20-9d6d7c297185@ventanamicro.com> Date: Mon, 30 Jan 2023 15:02:38 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH v4 3/3] hw/riscv: change riscv_compute_fdt_addr() semantics Content-Language: en-US From: Daniel Henrique Barboza To: Bin Meng Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com References: <20230126135219.1054658-1-dbarboza@ventanamicro.com> <20230126135219.1054658-4-dbarboza@ventanamicro.com> <793f7432-4592-98a4-34e9-472c185be297@ventanamicro.com> In-Reply-To: <793f7432-4592-98a4-34e9-472c185be297@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x231.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 18:02:46 -0000 On 1/30/23 14:16, Daniel Henrique Barboza wrote: > > > On 1/29/23 02:45, Bin Meng wrote: >> On Thu, Jan 26, 2023 at 9:54 PM Daniel Henrique Barboza >> wrote: >>> >>> As it is now, riscv_compute_fdt_addr() is receiving a dram_base, a >>> mem_size (which is defaulted to MachineState::ram_size in all boards) >>> and the FDT pointer. And it makes a very important assumption: the DRAM >>> interval dram_base + mem_size is contiguous. This is indeed the case for >>> most boards that uses a FDT. >> >> s/uses/use >> >>> >>> The Icicle Kit board works with 2 distinct RAM banks that are separated >>> by a gap. We have a lower bank with 1GiB size, a gap follows, then at >>> 64GiB the high memory starts. MachineClass::default_ram_size for this >>> board is set to 1.5Gb, and machine_init() is enforcing it as minimal RAM >>> size, meaning that there we'll always have at least 512 MiB in the Hi >>> RAM area. >>> >>> Using riscv_compute_fdt_addr() in this board is weird because not only >>> the board has sparse RAM, and it's calling it using the base address of >>> the Lo RAM area, but it's also using a mem_size that we have guarantees >>> that it will go up to the Hi RAM. All the function assumptions doesn't >>> work for this board. >>> >>> In fact, what makes the function works at all in this case is a >>> coincidence.  Commit 1a475d39ef54 introduced a 3GB boundary for the FDT, >>> down from 4Gb, that is enforced if dram_base is lower than 3072 MiB. For >>> the Icicle Kit board, memmap[MICROCHIP_PFSOC_DRAM_LO].base is 0x80000000 >>> (2 Gb) and it has a 1Gb size, so it will fall in the conditions to put >>> the FDT under a 3Gb address, which happens to be exactly at the end of >>> DRAM_LO. If the base address of the Lo area started later than 3Gb this >>> function would be unusable by the board. Changing any assumptions inside >>> riscv_compute_fdt_addr() can also break it by accident as well. >>> >>> Let's change riscv_compute_fdt_addr() semantics to be appropriate to the >>> Icicle Kit board and for future boards that might have sparse RAM >>> topologies to worry about: >>> >>> - relieve the condition that the dram_base + mem_size area is contiguous, >>> since this is already not the case today; >>> >>> - receive an extra 'dram_size' size attribute that refers to a contiguous >>> RAM block that the board wants the FDT to reside on. >>> >>> Together with 'mem_size' and 'fdt', which are now now being consumed by a >>> MachineState pointer, we're able to make clear assumptions based on the >>> DRAM block and total mem_size available to ensure that the FDT will be put >>> in a valid RAM address. >>> >> >> Well written commit message. Thanks! >> >>> Signed-off-by: Daniel Henrique Barboza >>> --- >>>   hw/riscv/boot.c            | 38 ++++++++++++++++++++++++++------------ >>>   hw/riscv/microchip_pfsoc.c |  3 ++- >>>   hw/riscv/sifive_u.c        |  3 ++- >>>   hw/riscv/spike.c           |  3 ++- >>>   hw/riscv/virt.c            |  3 ++- >>>   include/hw/riscv/boot.h    |  4 ++-- >>>   6 files changed, 36 insertions(+), 18 deletions(-) >>> >>> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c >>> index a6f7b8ae8e..8f4991480b 100644 >>> --- a/hw/riscv/boot.c >>> +++ b/hw/riscv/boot.c >>> @@ -284,33 +284,47 @@ out: >>>   } >>> >>>   /* >>> - * The FDT should be put at the farthest point possible to >>> - * avoid overwriting it with the kernel/initrd. >>> + * This function makes an assumption that the DRAM interval >>> + * 'dram_base' + 'dram_size' is contiguous. >>>    * >>> - * This function makes an assumption that the DRAM is >>> - * contiguous. It also cares about 32-bit systems and >>> - * will limit fdt_addr to be addressable by them even for >>> - * 64-bit CPUs. >>> + * Considering that 'dram_end' is the lowest value between >>> + * the end of the DRAM block and MachineState->ram_size, the >>> + * FDT location will vary according to 'dram_base': >>> + * >>> + * - if 'dram_base' is less that 3072 MiB, the FDT will be >>> + * put at the lowest value between 3072 MiB and 'dram_end'; >>> + * >>> + * - if 'dram_base' is higher than 3072 MiB, the FDT will be >>> + * put at 'dram_end'. >>>    * >>>    * The FDT is fdt_packed() during the calculation. >>>    */ >>> -uint32_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size, >>> -                                void *fdt) >>> +hwaddr riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, >> >> Using hwaddr to represent a size looks weird. Although technically >> they are the same ... I would leave this as it is. > > I'll leave it as it was back in patch 2 (uint64_t). > >> >>> +                              MachineState *ms) >>>   { >>> -    uint64_t temp; >>> -    hwaddr dram_end = dram_base + mem_size; >>> -    int ret = fdt_pack(fdt); >>> +    int ret = fdt_pack(ms->fdt); >>> +    hwaddr dram_end, temp; >>>       int fdtsize; >>> >>>       /* Should only fail if we've built a corrupted tree */ >>>       g_assert(ret == 0); >>> >>> -    fdtsize = fdt_totalsize(fdt); >>> +    fdtsize = fdt_totalsize(ms->fdt); >>>       if (fdtsize <= 0) { >>>           error_report("invalid device-tree"); >>>           exit(1); >>>       } >>> >>> +    /* >>> +     * A dram_size == 0, usually from a MemMapEntry[].size element, >>> +     * means that the DRAM block goes all the way to ms->ram_size. >>> +     */ >>> +    if (dram_size == 0x0) { >>> +        dram_end = dram_base + ms->ram_size; >>> +    } else { >>> +        dram_end = dram_base + MIN(ms->ram_size, dram_size); >>> +    } >> >> How about: >> >> g_assert(dram_size < ms->ram_size); > > I don't believe that dram_size > ms->ram_size should be an error. A board can > have a declared MemMapEntry.size that is larger than its current setting of > ms->ram_size. > > >> dram_end = dram_base + (dram_size ? dram_size : ms->ram_size); > > I can change the if/else statement up there for a ternary: > > dram_end = dram_base + (dram_size ? ms->ram_size : MIN(ms->ram_size, dram_size)) This is an ooopsie. This ternary is doing the opposite of what it should do :/ I would do something like this, breaking in two lines to avoid 80+ chars in the same line: dram_end = dram_base; dram_end += dram_size ? MIN(ms->ram_size, dram_size) : ms->ram_size; Daniel > > > Thanks, > > Daniel > >> >>> + >>>       /* >>>        * We should put fdt as far as possible to avoid kernel/initrd overwriting >>>        * its content. But it should be addressable by 32 bit system as well. >>> diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c >>> index a30203db85..e81bbd12df 100644 >>> --- a/hw/riscv/microchip_pfsoc.c >>> +++ b/hw/riscv/microchip_pfsoc.c >>> @@ -634,7 +634,8 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) >>> >>>           /* Compute the fdt load address in dram */ >>>           fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base, >>> -                                               machine->ram_size, machine->fdt); >>> +                                               memmap[MICROCHIP_PFSOC_DRAM_LO].size, >>> +                                               machine); >>>           riscv_load_fdt(fdt_load_addr, machine->fdt); >>> >>>           /* Load the reset vector */ >>> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c >>> index 6bbdbe5fb7..ad3bb35b34 100644 >>> --- a/hw/riscv/sifive_u.c >>> +++ b/hw/riscv/sifive_u.c >>> @@ -609,7 +609,8 @@ static void sifive_u_machine_init(MachineState *machine) >>>       } >>> >>>       fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, >>> -                                           machine->ram_size, machine->fdt); >>> +                                           memmap[SIFIVE_U_DEV_DRAM].size, >>> +                                           machine); >>>       riscv_load_fdt(fdt_load_addr, machine->fdt); >>> >>>       if (!riscv_is_32bit(&s->soc.u_cpus)) { >>> diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c >>> index ceebe34c5f..b5979eddd6 100644 >>> --- a/hw/riscv/spike.c >>> +++ b/hw/riscv/spike.c >>> @@ -317,7 +317,8 @@ static void spike_board_init(MachineState *machine) >>>       } >>> >>>       fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, >>> -                                           machine->ram_size, machine->fdt); >>> +                                           memmap[SPIKE_DRAM].size, >>> +                                           machine); >>>       riscv_load_fdt(fdt_load_addr, machine->fdt); >>> >>>       /* load the reset vector */ >>> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c >>> index 43fca597f0..f079a30b60 100644 >>> --- a/hw/riscv/virt.c >>> +++ b/hw/riscv/virt.c >>> @@ -1293,7 +1293,8 @@ static void virt_machine_done(Notifier *notifier, void *data) >>>       } >>> >>>       fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, >>> -                                           machine->ram_size, machine->fdt); >>> +                                           memmap[VIRT_DRAM].size, >>> +                                           machine); >>>       riscv_load_fdt(fdt_load_addr, machine->fdt); >>> >>>       /* load the reset vector */ >>> diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h >>> index 7babd669c7..a6099c2dc6 100644 >>> --- a/include/hw/riscv/boot.h >>> +++ b/include/hw/riscv/boot.h >>> @@ -48,8 +48,8 @@ target_ulong riscv_load_kernel(MachineState *machine, >>>                                  target_ulong firmware_end_addr, >>>                                  bool load_initrd, >>>                                  symbol_fn_t sym_cb); >>> -uint32_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, >>> -                                void *fdt); >>> +hwaddr riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, >>> +                              MachineState *ms); >>>   void riscv_load_fdt(hwaddr fdt_addr, void *fdt); >>>   void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, >>>                                  hwaddr saddr, >>> -- >> >> Regards, >> Bin From MAILER-DAEMON Mon Jan 30 14:03:55 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMZRW-0006Xs-Nu for mharc-qemu-riscv@gnu.org; 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id p24-20020a170903249800b00195e6ea45a8sm8124901plw.305.2023.01.30.11.03.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Jan 2023 11:03:39 -0800 (PST) Message-ID: <41e5c5bd-9328-c99e-e37b-aadd2b7d308b@linaro.org> Date: Mon, 30 Jan 2023 09:03:32 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension Content-Language: en-US To: LIU Zhiwei , Christoph Muellner , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=c3=bcbner?= , Palmer Dabbelt , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang References: <20230124195945.181842-1-christoph.muellner@vrull.eu> <20230124195945.181842-9-christoph.muellner@vrull.eu> <48ff4151-25d9-4b4d-d50a-6516000599c7@linaro.org> <8385d954-678e-d78d-c3ae-d74a4a902907@linux.alibaba.com> <7f8383f6-e860-5e3e-e89c-dfdac4e05dc5@linaro.org> <82e49515-512f-9439-ceab-6c5df3bb20e4@linux.alibaba.com> From: Richard Henderson In-Reply-To: <82e49515-512f-9439-ceab-6c5df3bb20e4@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 19:03:43 -0000 On 1/29/23 22:41, LIU Zhiwei wrote: > > On 2023/1/30 13:43, Richard Henderson wrote: >> On 1/29/23 16:03, LIU Zhiwei wrote: >>> Thanks. It's a bug. We should load all memory addresses to  local TCG temps first. >>> >>> Do you think we should probe all the memory addresses for the store pair instructions? >>> If so, can we avoid the use of a helper function? >> >> Depends on what the hardware does.  Even with a trap in the middle the stores are >> restartable, since no register state changes. > > I refer to the specification of LDP and STP on AARCH64. The specification allows > > "any access performed before the exception was taken is repeated". > > In detailed, > > "If, according to these rules, an instruction is executed as a sequence of accesses, exceptions, including interrupts, > can be taken during that sequence, regardless of the memory type being accessed. If any of these exceptions are > returned from using their preferred return address, the instruction that generated the sequence of accesses is > re-executed, and so any access performed before the exception was taken is repeated. See also Taking an interrupt > during a multi-access load or store on page D1-4664." > > However I see the implementation of LDP and STP on QEMU are in different ways. LDP will > only load the first register when it ensures no trap in the second access. > > So I have two questions here. > > 1) One for the QEMU implementation about LDP. Can we implement the LDP as two directly > loads to cpu registers instead of local TCG temps? For the Thead specification, where rd1 != rs1 (and you enforce it), then yes, I suppose you could load directly to the cpu registers, because on restart rs1 would be unmodified. For AArch64, which you quote above, there is no constraint that the destinations do not overlap the address register, so we must implement "LDP r0, r1, [r0]" as a load into temps. > 2) One for the comment. Why register state changes cause non-restartable? Do you mean if > the first register changes, it may influence the calculation of address after the trap? Yes, that's what I mean about non-restartable -- if any of the input registers are changed before the trap is recognized. >> Yes.  Conciser what happens when the insn is encoded with .long. Does the hardware trap >> an illegal instruction?  Is the behavior simply unspecified?  The manual could be >> improved to specify, akin to the Arm terms: UNDEFINED, CONSTRAINED UNPREDICTABLE, >> IMPLEMENTATION DEFINED, etc. >> >> > Thanks, I will fix the manual. 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id y5-20020aa79e05000000b00593b72f6680sm2885314pfq.86.2023.01.30.11.10.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Jan 2023 11:10:56 -0800 (PST) Message-ID: <22ab5f33-5ab7-7260-391f-375cd98a68ae@linaro.org> Date: Mon, 30 Jan 2023 09:10:51 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH] target/riscv: set tval for triggered watchpoints Content-Language: en-US To: Sergey Matyukevich , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Sergey Matyukevich References: <20230130100757.721372-1-geomatsi@gmail.com> From: Richard Henderson In-Reply-To: <20230130100757.721372-1-geomatsi@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Jan 2023 19:11:01 -0000 On 1/30/23 00:07, Sergey Matyukevich wrote: > From: Sergey Matyukevich > > According to priviledged spec, if [sm]tval is written with a nonzero > value when a breakpoint exception occurs, then [sm]tval will contain > the faulting virtual address. Set tval to hit address when breakpoint > exception is triggered by hardware watchpoint. > > Signed-off-by: Sergey Matyukevich > --- > target/riscv/cpu_helper.c | 3 +++ > target/riscv/debug.c | 1 + > 2 files changed, 4 insertions(+) Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Mon Jan 30 19:20:02 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMeNW-000181-4D for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 19:20:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMeNU-00017I-L5; Mon, 30 Jan 2023 19:20:00 -0500 Received: from mail-vs1-xe2c.google.com ([2607:f8b0:4864:20::e2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMeNT-0001ek-1u; Mon, 30 Jan 2023 19:20:00 -0500 Received: by mail-vs1-xe2c.google.com with SMTP id d66so14396868vsd.9; Mon, 30 Jan 2023 16:19:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=gsNWlwcqUIirUHUk6ifpNKXKGCVsWuVEQn/MlUp+p/E=; b=C5n8y5DVNr5IQJi4EQn1dBvrykuAIMAUD4l+Lu9XQaBF+MQ2eHgpyU7kzIzzeEaAuu 4dyhIOPUxgyl0lfkfqMuF5coK1ef1qdN5PwVeVFqTV40b3r9/GnXwDqcOcKbcMUaIg0T vAWT9dMQ3fPAM4pSqWMLkB0gGearX+8AKAu+KlRedEdG4I2RIoOsid0EBM92PdzcQfgn /Q7rTFBjfkNrqQtOAmiQiuWOb+d1SCiE5LV1Z/K9xv8y18ZnTyXj9LQdP/qCI4Y32d93 +ZgTcDHE2H/7wMvcrMhYCyDPSx31Dcs3Z9z0Yl5Q8IgZ+0Yj8ueP/OQzgEZ8aPoZCzJy +K0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=gsNWlwcqUIirUHUk6ifpNKXKGCVsWuVEQn/MlUp+p/E=; b=nQ/F/QZUBjDDUHBKmN5ciNZe5JcXY+S/5lOoErQkAW+m0QHg89Bl0wCkLgFoHpXY4V TJbvaiigSc3WIJUpGhxR/jwt90GI7mEB531Kc8GimjmwbxuktL1DuP9a3iu5y8PjqvK/ qS9pnn3xhLu2Xm7E8w/MOTkG6Hq/MECDBzw7capvkz49DUJ/XWOxiRC5LqHZan1fifFI Le0arZrdsjosQmrgvaY/4dl6Sx2vdTc23R8hyNmIwRcRO+fEXVy4fQYU2nybVKfcXcEk pVKtO8MM2d1JlytPrsOFitfrPLNWkRVAKD0u1C36nYZ/YVfjpxZNB5a9YaCUCYCk/iGO 4OyA== X-Gm-Message-State: AFqh2koyryBouLeeeXXNaBAY8KVTvkb9vnhCvuswNkWnuz6QSuXayJuH A/eorRbBg1WqksQyL5W9PSDRtClAvAAzvNlw7Pc= X-Google-Smtp-Source: AMrXdXtKydD3LDx/YsLJyGI78jhlOPLmDXzffYTCvp0/0tIe11TENczWOtm5zQTd1utdxLf/BpzrsDqXWRpV+RDToRM= X-Received: by 2002:a05:6102:cd4:b0:3d0:c2e9:cb77 with SMTP id g20-20020a0561020cd400b003d0c2e9cb77mr6945984vst.54.1675124396208; Mon, 30 Jan 2023 16:19:56 -0800 (PST) MIME-Version: 1.0 References: <20230130100757.721372-1-geomatsi@gmail.com> In-Reply-To: <20230130100757.721372-1-geomatsi@gmail.com> From: Alistair Francis Date: Tue, 31 Jan 2023 10:19:30 +1000 Message-ID: Subject: Re: [PATCH] target/riscv: set tval for triggered watchpoints To: Sergey Matyukevich Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng , Sergey Matyukevich Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e2c; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe2c.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 00:20:00 -0000 On Mon, Jan 30, 2023 at 8:08 PM Sergey Matyukevich wrote: > > From: Sergey Matyukevich > > According to priviledged spec, if [sm]tval is written with a nonzero > value when a breakpoint exception occurs, then [sm]tval will contain > the faulting virtual address. Set tval to hit address when breakpoint > exception is triggered by hardware watchpoint. > > Signed-off-by: Sergey Matyukevich Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu_helper.c | 3 +++ > target/riscv/debug.c | 1 + > 2 files changed, 4 insertions(+) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 9a28816521..d3be8c0511 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -1641,6 +1641,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) > case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: > tval = env->bins; > break; > + case RISCV_EXCP_BREAKPOINT: > + tval = env->badaddr; > + break; > default: > break; > } > diff --git a/target/riscv/debug.c b/target/riscv/debug.c > index bf4840a6a3..48ef3c59ea 100644 > --- a/target/riscv/debug.c > +++ b/target/riscv/debug.c > @@ -761,6 +761,7 @@ void riscv_cpu_debug_excp_handler(CPUState *cs) > > if (cs->watchpoint_hit) { > if (cs->watchpoint_hit->flags & BP_CPU) { > + env->badaddr = cs->watchpoint_hit->hitaddr; > cs->watchpoint_hit = NULL; > do_trigger_action(env, DBG_ACTION_BP); > } > -- > 2.39.0 > > From MAILER-DAEMON Mon Jan 30 19:59:03 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMezH-0001wy-H5 for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 19:59:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMezF-0001wl-Gp; Mon, 30 Jan 2023 19:59:01 -0500 Received: from mail-vs1-xe35.google.com ([2607:f8b0:4864:20::e35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMezD-0008RF-3A; Mon, 30 Jan 2023 19:59:00 -0500 Received: by mail-vs1-xe35.google.com with SMTP id i185so14504031vsc.6; Mon, 30 Jan 2023 16:58:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=5YrtKzsIEeu5HdmG4qgzqGUF26ZFDk0oYv83WILhxi8=; b=j+RyWNnNkiP+lkKorHw8bnRYtyPl8I1dvW49wFQgwoDuSzuldlrS96+2D+gnKknPua d4ZpEkVjpdw05wKhOefA3jR1GGYTzk+x6oBQBSIP+JaGDv8/3+QzTnzFJiGlw5wMByld 7WT2tnOqTYrhrUrhjBcpFGtIQiLEt2ym+jbenRGD+/JNwMRi2Djmq1thI/enteFjRLeG ratF7Tr5oj0Xfsv2Le/bYryTEhwi6DFeYS08dcyh7YrxTgA6oo/4sEYZXLnVINKn3uyu vVtP8tcUOyiKphUhr+npnNjaczb0xgRMGfKci4euaQgp4DfYCHEXhuvhnvsm98xqL2AM owGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=5YrtKzsIEeu5HdmG4qgzqGUF26ZFDk0oYv83WILhxi8=; b=qL6kmyR2dXVd9uqW9+ZBbdZki6pqwJuFPdUpejsBRnlTZzfsNXVogH7pbMEPn9kGBx DQJyKwrLSXJAyYLsRHPJeFZt1L4RbhJ21gnSB/N3F59ELQDY07zLT/ZTrULJXDGsFU90 Bp3uaWRqpVAJSz6wMHU9yMIQFN/LFlnIIXPqhCvq8Rf171NGbrO3f4Op/8cdBISlXNGy 6hYnHiDiwSa5Bp81QOlivqrk3jZwS5X/y0YS3kn7IltozFwNvWYPU4gbesOiitDQCBic By7Jg7ngefiYnB2i5Q44oNMeLJnFkHpcB3MqyYLeO6wr9ihTDb1zXaM7nh74GVlocdcL D5Sw== X-Gm-Message-State: AO0yUKXbhLn/kt0U+EDPLZ+RipKRJgHhMYTOqC5D3A47Z25C6ZNyVKdQ 5RDPK/U9EhSx4BHQEwBL6wObmdRXpNaliKaq+AI= X-Google-Smtp-Source: AK7set/5rSg1Js6+z3K9YrBNm0pAqs/LJ9/fO73XS4DxfAuOMG/w5cWTAfIwTgkB6ZrWwLvl5hwiuT1LI6E8CJeJYUQ= X-Received: by 2002:a67:e184:0:b0:3eb:f205:2c08 with SMTP id e4-20020a67e184000000b003ebf2052c08mr2229609vsl.10.1675126737458; Mon, 30 Jan 2023 16:58:57 -0800 (PST) MIME-Version: 1.0 References: <20230130100757.721372-1-geomatsi@gmail.com> In-Reply-To: <20230130100757.721372-1-geomatsi@gmail.com> From: Alistair Francis Date: Tue, 31 Jan 2023 10:58:31 +1000 Message-ID: Subject: Re: [PATCH] target/riscv: set tval for triggered watchpoints To: Sergey Matyukevich Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng , Sergey Matyukevich Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2607:f8b0:4864:20::e35; envelope-from=alistair23@gmail.com; helo=mail-vs1-xe35.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 00:59:01 -0000 On Mon, Jan 30, 2023 at 8:08 PM Sergey Matyukevich wrote: > > From: Sergey Matyukevich > > According to priviledged spec, if [sm]tval is written with a nonzero > value when a breakpoint exception occurs, then [sm]tval will contain > the faulting virtual address. Set tval to hit address when breakpoint > exception is triggered by hardware watchpoint. > > Signed-off-by: Sergey Matyukevich Thanks! Applied to riscv-to-apply.next Alistair > --- > target/riscv/cpu_helper.c | 3 +++ > target/riscv/debug.c | 1 + > 2 files changed, 4 insertions(+) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index 9a28816521..d3be8c0511 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -1641,6 +1641,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) > case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: > tval = env->bins; > break; > + case RISCV_EXCP_BREAKPOINT: > + tval = env->badaddr; > + break; > default: > break; > } > diff --git a/target/riscv/debug.c b/target/riscv/debug.c > index bf4840a6a3..48ef3c59ea 100644 > --- a/target/riscv/debug.c > +++ b/target/riscv/debug.c > @@ -761,6 +761,7 @@ void riscv_cpu_debug_excp_handler(CPUState *cs) > > if (cs->watchpoint_hit) { > if (cs->watchpoint_hit->flags & BP_CPU) { > + env->badaddr = cs->watchpoint_hit->hitaddr; > cs->watchpoint_hit = NULL; > do_trigger_action(env, DBG_ACTION_BP); > } > -- > 2.39.0 > > From MAILER-DAEMON Mon Jan 30 20:00:20 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMf0W-0002aN-AJ for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 20:00:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMf0T-0002Zu-TC; Mon, 30 Jan 2023 20:00:18 -0500 Received: from mail-ed1-x533.google.com ([2a00:1450:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMf0R-0000Kb-Mf; Mon, 30 Jan 2023 20:00:17 -0500 Received: by mail-ed1-x533.google.com with SMTP id u21so12891524edv.3; Mon, 30 Jan 2023 17:00:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=txKewLhayIbfWQvtsqxwhLwY3PzNyZ2lkLg0bsm6m8A=; b=c1Nza5PHIig39PSk+z+s58OCAi/c+9PfGEyJhmMUEtnSUh5UPC8x1ykwmUXqBiOc0T Sjv7ZzCHeKUHZxEqwJoZo26BUpX8gGCHMSyjQZv3HLW45K5EXux2+7msl9TsRgnaTtT9 tPjcbN9ijFb8+ZvzPdVMwQG9z7ql6Zuq9GyQixkEyK+C6k8QXAHw4SveDHlZkqVPvMtO lo4DXJBUaIhftAIrTZwq0d7rRxSjztx24CoXVKEj7cMuEIpPxR0fwCJB8itFbRqh5k1d ekMbPBXlQcPSL9rf7UXZwNRZ80R1h7bAjKFm+a/TyeLIYf6bOKk26ma77Esph0qL+PQX JaUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=txKewLhayIbfWQvtsqxwhLwY3PzNyZ2lkLg0bsm6m8A=; b=V78QuT6PqnwT7nkrE2Ri9pFAgQZepyfkoYsDKyg4SiOjc9bo4dzUSoF81AtWSY2vlb a4RIQEV+n7R3N9XdsL+qP5ENwQvF6nW+FFxQ7t6XK6j4YT2T8TZklI1QsgcOAOBypUIF Hfhy73Xec4lFPMDGpyvWm3aoYmChpuA2Ro9lWPZbprTwipj+DVdI2GdtCDLVdMuqvpJ5 UR72yhM/58BG5uaqayQBHQNK5KQLQDQCCr9iF9Bj+YcYi92vFLiDPXseXkWYhBPF+3aM rIFDGaz8TjmkbjiHyrhQ9mCKtfb9xiweACNG2x5TIKnP95UmDKI+ZxC0V7jO+1KdngPv Q8wQ== X-Gm-Message-State: AO0yUKVjUndOBQrM5IIK5Q83P5Ne1vp7sNu/T8AqNRIEtDRDnHw54TJP OOzHych04R8m0wDtywiy0GVOUorc6t2yhVm6RRU= X-Google-Smtp-Source: AK7set+A/CTj+EWjjk4nHZ2I4IaCtkP47HvD+P1sURim8PVtWvGZ6xRZNjhwMlsCguDDmQNe+Rac4GdsafSOqX+0Kus= X-Received: by 2002:a05:6402:f24:b0:4a2:28f6:984b with SMTP id i36-20020a0564020f2400b004a228f6984bmr2878384eda.29.1675126812310; Mon, 30 Jan 2023 17:00:12 -0800 (PST) MIME-Version: 1.0 References: <20230126135219.1054658-1-dbarboza@ventanamicro.com> <20230126135219.1054658-4-dbarboza@ventanamicro.com> <793f7432-4592-98a4-34e9-472c185be297@ventanamicro.com> In-Reply-To: <793f7432-4592-98a4-34e9-472c185be297@ventanamicro.com> From: Bin Meng Date: Tue, 31 Jan 2023 09:00:00 +0800 Message-ID: Subject: Re: [PATCH v4 3/3] hw/riscv: change riscv_compute_fdt_addr() semantics To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=bmeng.cn@gmail.com; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 01:00:19 -0000 On Tue, Jan 31, 2023 at 1:16 AM Daniel Henrique Barboza wrote: > > > > On 1/29/23 02:45, Bin Meng wrote: > > On Thu, Jan 26, 2023 at 9:54 PM Daniel Henrique Barboza > > wrote: > >> > >> As it is now, riscv_compute_fdt_addr() is receiving a dram_base, a > >> mem_size (which is defaulted to MachineState::ram_size in all boards) > >> and the FDT pointer. And it makes a very important assumption: the DRAM > >> interval dram_base + mem_size is contiguous. This is indeed the case for > >> most boards that uses a FDT. > > > > s/uses/use > > > >> > >> The Icicle Kit board works with 2 distinct RAM banks that are separated > >> by a gap. We have a lower bank with 1GiB size, a gap follows, then at > >> 64GiB the high memory starts. MachineClass::default_ram_size for this > >> board is set to 1.5Gb, and machine_init() is enforcing it as minimal RAM > >> size, meaning that there we'll always have at least 512 MiB in the Hi > >> RAM area. > >> > >> Using riscv_compute_fdt_addr() in this board is weird because not only > >> the board has sparse RAM, and it's calling it using the base address of > >> the Lo RAM area, but it's also using a mem_size that we have guarantees > >> that it will go up to the Hi RAM. All the function assumptions doesn't > >> work for this board. > >> > >> In fact, what makes the function works at all in this case is a > >> coincidence. Commit 1a475d39ef54 introduced a 3GB boundary for the FDT, > >> down from 4Gb, that is enforced if dram_base is lower than 3072 MiB. For > >> the Icicle Kit board, memmap[MICROCHIP_PFSOC_DRAM_LO].base is 0x80000000 > >> (2 Gb) and it has a 1Gb size, so it will fall in the conditions to put > >> the FDT under a 3Gb address, which happens to be exactly at the end of > >> DRAM_LO. If the base address of the Lo area started later than 3Gb this > >> function would be unusable by the board. Changing any assumptions inside > >> riscv_compute_fdt_addr() can also break it by accident as well. > >> > >> Let's change riscv_compute_fdt_addr() semantics to be appropriate to the > >> Icicle Kit board and for future boards that might have sparse RAM > >> topologies to worry about: > >> > >> - relieve the condition that the dram_base + mem_size area is contiguous, > >> since this is already not the case today; > >> > >> - receive an extra 'dram_size' size attribute that refers to a contiguous > >> RAM block that the board wants the FDT to reside on. > >> > >> Together with 'mem_size' and 'fdt', which are now now being consumed by a > >> MachineState pointer, we're able to make clear assumptions based on the > >> DRAM block and total mem_size available to ensure that the FDT will be put > >> in a valid RAM address. > >> > > > > Well written commit message. Thanks! > > > >> Signed-off-by: Daniel Henrique Barboza > >> --- > >> hw/riscv/boot.c | 38 ++++++++++++++++++++++++++------------ > >> hw/riscv/microchip_pfsoc.c | 3 ++- > >> hw/riscv/sifive_u.c | 3 ++- > >> hw/riscv/spike.c | 3 ++- > >> hw/riscv/virt.c | 3 ++- > >> include/hw/riscv/boot.h | 4 ++-- > >> 6 files changed, 36 insertions(+), 18 deletions(-) > >> > >> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > >> index a6f7b8ae8e..8f4991480b 100644 > >> --- a/hw/riscv/boot.c > >> +++ b/hw/riscv/boot.c > >> @@ -284,33 +284,47 @@ out: > >> } > >> > >> /* > >> - * The FDT should be put at the farthest point possible to > >> - * avoid overwriting it with the kernel/initrd. > >> + * This function makes an assumption that the DRAM interval > >> + * 'dram_base' + 'dram_size' is contiguous. > >> * > >> - * This function makes an assumption that the DRAM is > >> - * contiguous. It also cares about 32-bit systems and > >> - * will limit fdt_addr to be addressable by them even for > >> - * 64-bit CPUs. > >> + * Considering that 'dram_end' is the lowest value between > >> + * the end of the DRAM block and MachineState->ram_size, the > >> + * FDT location will vary according to 'dram_base': > >> + * > >> + * - if 'dram_base' is less that 3072 MiB, the FDT will be > >> + * put at the lowest value between 3072 MiB and 'dram_end'; > >> + * > >> + * - if 'dram_base' is higher than 3072 MiB, the FDT will be > >> + * put at 'dram_end'. > >> * > >> * The FDT is fdt_packed() during the calculation. > >> */ > >> -uint32_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size, > >> - void *fdt) > >> +hwaddr riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, > > > > Using hwaddr to represent a size looks weird. Although technically > > they are the same ... I would leave this as it is. > > I'll leave it as it was back in patch 2 (uint64_t). > > > > >> + MachineState *ms) > >> { > >> - uint64_t temp; > >> - hwaddr dram_end = dram_base + mem_size; > >> - int ret = fdt_pack(fdt); > >> + int ret = fdt_pack(ms->fdt); > >> + hwaddr dram_end, temp; > >> int fdtsize; > >> > >> /* Should only fail if we've built a corrupted tree */ > >> g_assert(ret == 0); > >> > >> - fdtsize = fdt_totalsize(fdt); > >> + fdtsize = fdt_totalsize(ms->fdt); > >> if (fdtsize <= 0) { > >> error_report("invalid device-tree"); > >> exit(1); > >> } > >> > >> + /* > >> + * A dram_size == 0, usually from a MemMapEntry[].size element, > >> + * means that the DRAM block goes all the way to ms->ram_size. > >> + */ > >> + if (dram_size == 0x0) { > >> + dram_end = dram_base + ms->ram_size; > >> + } else { > >> + dram_end = dram_base + MIN(ms->ram_size, dram_size); > >> + } > > > > How about: > > > > g_assert(dram_size < ms->ram_size); > > I don't believe that dram_size > ms->ram_size should be an error. A board can > have a declared MemMapEntry.size that is larger than its current setting of > ms->ram_size. What use case is that? This updated function now has the assumption that: 1. dram_size being 0 meaning contiguous system RAM region from dram_base 2. otherwise dram_size being the *first* contiguous system RAM region from dram_base We can use g_assert(dram_size < ms->ram_size) to catch either case. > > > > dram_end = dram_base + (dram_size ? dram_size : ms->ram_size); > > I can change the if/else statement up there for a ternary: > > dram_end = dram_base + (dram_size ? ms->ram_size : MIN(ms->ram_size, dram_size)) > Regards, Bin From MAILER-DAEMON Mon Jan 30 20:52:37 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMfp7-0006Kl-0C for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 20:52:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMfp5-0006KQ-7L; Mon, 30 Jan 2023 20:52:35 -0500 Received: from mail-ej1-x631.google.com ([2a00:1450:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMfp3-0001Oj-LT; Mon, 30 Jan 2023 20:52:34 -0500 Received: by mail-ej1-x631.google.com with SMTP id qw12so21575601ejc.2; Mon, 30 Jan 2023 17:52:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=L0Gz4FCjZLtMEIrEO+t+wu6eeaYm1K9bsdu5Y0eSeoE=; b=EuTZqwoQhWquLdnUBekFKSXoarGXoAJSk2hlodmODqp2CuUyR8/gN7y6HZkC++flxO GjDc6/gahpoNWEzrpYx85qIRq1HMc+yPHdAn0FQuMaqqFjk+9Ra4DqNn+GzGbbttD9YM xv8PebhZcqaQUTd/1vX7SFhmweCnHB8kIvtbEso5DF7C8iBXmOrXu0Wx9shiQten+HCY CTF4E27IW9BVEKgAq3ih5QirXy6nFkj/zH09NDeCKHNdHirlox7iWl56Z2HWwRZIR0wb dp5Ttg+VjQJED3mGS79cEA1RYEvKnuwAkACGGt1mUeiVH4JXaL2n5/WRbZaq+CMNVF3j t2nA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=L0Gz4FCjZLtMEIrEO+t+wu6eeaYm1K9bsdu5Y0eSeoE=; b=IZa3Qz9Hsb8P5/uK7DGadO3PHqSIWZf5C/aVFAAoGOqP7HIETd16xT1ioprsEUN6vo iri00NO+xwG2+OY59l5ne0Pb9Pr4dOxjWM6H0YuVzhCa/sH/Eiade0Y9/7nj8++IPuik OeaLgXCBnht/Fv17+nvsZA2l2tqGKJC/CNMCrA29NsU3jAAMA2aSWBQKyRnzr4He7ZDw JxmQ7cGbFHWCPP2xnWdq0tYCZHcvbeDT/jyfbRU7aYdYtfLNm8l2ZKKq22I6VqWUMtRx 051jHHlDjrdbhxw1TVaYa2bdYosgvdQYtXqQsx6qC+Tabl+VT5caFhBn9URmDcZdhBQL 6iew== X-Gm-Message-State: AO0yUKWgvi1BYtEQjRS1CEWMgMky4M6AG9FZ54iSC/6fc6jKKOXm5uOo dBRQy1/2sw1YsOsUmQS7ZB6FMtWn3m9YpOt2Sl0= X-Google-Smtp-Source: AK7set9XV6FbF3Dka9uoplvmlXFUGJy7sOoMRCze9RgOySXbsmpdXGYwovzmizBxmFgyUVpeHZm4kKSlium4XXAD2HE= X-Received: by 2002:a17:906:7087:b0:878:4d11:2694 with SMTP id b7-20020a170906708700b008784d112694mr4355527ejk.26.1675129950588; Mon, 30 Jan 2023 17:52:30 -0800 (PST) MIME-Version: 1.0 References: <20230130100757.721372-1-geomatsi@gmail.com> In-Reply-To: From: Bin Meng Date: Tue, 31 Jan 2023 09:52:18 +0800 Message-ID: Subject: Re: [PATCH] target/riscv: set tval for triggered watchpoints To: Alistair Francis Cc: Sergey Matyukevich , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng , Sergey Matyukevich , Richard Henderson Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 01:52:36 -0000 On Tue, Jan 31, 2023 at 8:59 AM Alistair Francis wrote: > > On Mon, Jan 30, 2023 at 8:08 PM Sergey Matyukevich wrote: > > > > From: Sergey Matyukevich > > > > According to priviledged spec, if [sm]tval is written with a nonzero > > value when a breakpoint exception occurs, then [sm]tval will contain > > the faulting virtual address. Set tval to hit address when breakpoint > > exception is triggered by hardware watchpoint. > > > > Signed-off-by: Sergey Matyukevich > > Thanks! > > Applied to riscv-to-apply.next Oops, too quick, but I have one comment :) > > Alistair > > > --- > > target/riscv/cpu_helper.c | 3 +++ > > target/riscv/debug.c | 1 + > > 2 files changed, 4 insertions(+) > > > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > > index 9a28816521..d3be8c0511 100644 > > --- a/target/riscv/cpu_helper.c > > +++ b/target/riscv/cpu_helper.c > > @@ -1641,6 +1641,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) > > case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: > > tval = env->bins; > > break; > > + case RISCV_EXCP_BREAKPOINT: > > + tval = env->badaddr; RISCV_EXCP_BREAKPOINT may come from 'ebreak' so we should test if this exception comes from the debug module. The spec also says about icount trigger that: "If the trigger fires with action =0 then zero is written to the tval CSR on the breakpoint trap." So we can't blindly set tval for every breakpoint exception. > > + break; > > default: > > break; > > } > > diff --git a/target/riscv/debug.c b/target/riscv/debug.c > > index bf4840a6a3..48ef3c59ea 100644 > > --- a/target/riscv/debug.c > > +++ b/target/riscv/debug.c > > @@ -761,6 +761,7 @@ void riscv_cpu_debug_excp_handler(CPUState *cs) > > > > if (cs->watchpoint_hit) { > > if (cs->watchpoint_hit->flags & BP_CPU) { > > + env->badaddr = cs->watchpoint_hit->hitaddr; > > cs->watchpoint_hit = NULL; > > do_trigger_action(env, DBG_ACTION_BP); > > } > > -- Regards, Bin From MAILER-DAEMON Mon Jan 30 21:34:46 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMgTu-0006Jz-Qe for mharc-qemu-riscv@gnu.org; Mon, 30 Jan 2023 21:34:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMgTr-0006Ir-04; Mon, 30 Jan 2023 21:34:43 -0500 Received: from out30-119.freemail.mail.aliyun.com ([115.124.30.119]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMgTn-00085Q-6S; Mon, 30 Jan 2023 21:34:42 -0500 X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R911e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046056; MF=zhiwei_liu@linux.alibaba.com; NM=1; PH=DS; RN=14; SR=0; TI=SMTPD_---0VaUqnBz_1675132462; Received: from 30.221.97.63(mailfrom:zhiwei_liu@linux.alibaba.com fp:SMTPD_---0VaUqnBz_1675132462) by smtp.aliyun-inc.com; Tue, 31 Jan 2023 10:34:23 +0800 Message-ID: Date: Tue, 31 Jan 2023 10:34:07 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.6.1 Subject: Re: [PATCH v3 08/14] RISC-V: Adding T-Head MemPair extension Content-Language: en-US To: Richard Henderson , Christoph Muellner , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=c3=bcbner?= , Palmer Dabbelt , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang References: <20230124195945.181842-1-christoph.muellner@vrull.eu> <20230124195945.181842-9-christoph.muellner@vrull.eu> <48ff4151-25d9-4b4d-d50a-6516000599c7@linaro.org> <8385d954-678e-d78d-c3ae-d74a4a902907@linux.alibaba.com> <7f8383f6-e860-5e3e-e89c-dfdac4e05dc5@linaro.org> <82e49515-512f-9439-ceab-6c5df3bb20e4@linux.alibaba.com> <41e5c5bd-9328-c99e-e37b-aadd2b7d308b@linaro.org> From: LIU Zhiwei In-Reply-To: <41e5c5bd-9328-c99e-e37b-aadd2b7d308b@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=115.124.30.119; envelope-from=zhiwei_liu@linux.alibaba.com; helo=out30-119.freemail.mail.aliyun.com X-Spam_score_int: -99 X-Spam_score: -10.0 X-Spam_bar: ---------- X-Spam_report: (-10.0 / 5.0 requ) BAYES_00=-1.9, ENV_AND_HDR_SPF_MATCH=-0.5, NICE_REPLY_A=-0.09, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UNPARSEABLE_RELAY=0.001, USER_IN_DEF_SPF_WL=-7.5 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 02:34:44 -0000 On 2023/1/31 3:03, Richard Henderson wrote: > On 1/29/23 22:41, LIU Zhiwei wrote: >> >> On 2023/1/30 13:43, Richard Henderson wrote: >>> On 1/29/23 16:03, LIU Zhiwei wrote: >>>> Thanks. It's a bug. We should load all memory addresses to  local >>>> TCG temps first. >>>> >>>> Do you think we should probe all the memory addresses for the store >>>> pair instructions? If so, can we avoid the use of a helper function? >>> >>> Depends on what the hardware does.  Even with a trap in the middle >>> the stores are restartable, since no register state changes. >> >> I refer to the specification of LDP and STP on AARCH64. The >> specification allows >> >> "any access performed before the exception was taken is repeated". >> >> In detailed, >> >> "If, according to these rules, an instruction is executed as a >> sequence of accesses, exceptions, including interrupts, >> can be taken during that sequence, regardless of the memory type >> being accessed. If any of these exceptions are >> returned from using their preferred return address, the instruction >> that generated the sequence of accesses is >> re-executed, and so any access performed before the exception was >> taken is repeated. See also Taking an interrupt >> during a multi-access load or store on page D1-4664." >> >> However I see the implementation of LDP and STP on QEMU are in >> different ways. LDP will only load the first register when it ensures >> no trap in the second access. >> >> So I have two questions here. >> >> 1) One for the QEMU implementation about LDP. Can we implement the >> LDP as two directly loads to cpu registers instead of local TCG temps? > > For the Thead specification, where rd1 != rs1 (and you enforce it), > then yes, I suppose you could load directly to the cpu registers, > because on restart rs1 would be unmodified. > > For AArch64, which you quote above, there is no constraint that the > destinations do not overlap the address register, so we must implement > "LDP r0, r1, [r0]" as a load into temps. > Got it. Thanks. > >> 2) One for the comment. Why register state changes cause >> non-restartable? Do you mean if the first register changes, it may >> influence the calculation of address after the trap? > > Yes, that's what I mean about non-restartable -- if any of the input > registers are changed before the trap is recognized. > > Thanks for the clarification. Once I thought the reason of non-restartable is the side effects of repeat execution, which may cause watchpoint matches twice or access MMIO device twice. >>> Yes.  Conciser what happens when the insn is encoded with .long. >>> Does the hardware trap an illegal instruction?  Is the behavior >>> simply unspecified?  The manual could be improved to specify, akin >>> to the Arm terms: UNDEFINED, CONSTRAINED UNPREDICTABLE, >>> IMPLEMENTATION DEFINED, etc. >>> >>> >> Thanks, I will fix the manual. The manual has been fixed  by Christopher.  Thanks. Best Regards, Zhiwei > > Excellent, thanks. > > > r~ From MAILER-DAEMON Tue Jan 31 02:58:28 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMlX7-0005lv-9d for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 02:58:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMlX1-0005k1-K9; Tue, 31 Jan 2023 02:58:20 -0500 Received: from mail-ej1-x632.google.com ([2a00:1450:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMlWz-0002Qe-Dl; Tue, 31 Jan 2023 02:58:19 -0500 Received: by mail-ej1-x632.google.com with SMTP id p26so27906221ejx.13; Mon, 30 Jan 2023 23:58:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=yE1SDRPNQvKDzunWv7Z/9APPN2vtX0zkGAvX41ENnyo=; b=XmJVzBfSyrxQ1zEOyeHXEILpIYGRovM1d3npD+00XQw5z46oElPpfH/Z4Un6vYOuyl UAvu6ubGT4YU0xRZLaqa4AgbsnuYjWVgRv8vXK2Z5re+aeVCbFX3csE2IreWzd900sf1 oZQkcOj5Rh24NWbK5/nwiBWN7oj62iEIH01KCdbM0dpDazi9mKfcHcOQp+L8hec99MiO ZREf4Q1M2oyvsKUP216lFLIlGVlNxbqqhP7IObbrKLKghSVBoYMOsxYjMlM4/5sPp8TK SBf8Z67yd8Dhaigrz6PXll9AjdhDHp5vvHnL+GCjzXgsJ0pqBamjMf9NWSEnnf99KcRU YY2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=yE1SDRPNQvKDzunWv7Z/9APPN2vtX0zkGAvX41ENnyo=; b=1xaUqPyUYsrLVrCmuNon8T9pnbL3sCC6R8PR5XeH/8GqhA4YeLvy0PuAucEgTiCMRQ 72pG8TFTDOwKy667RB8CInnOBS2Y/Q1J2qEs+maAMP9PMxGyNMz3GW7NoMVe/FlJubKB xJciuTFERcTwwZZgmxEjJkdb+ejVXSPpanRwfC/AItPHTpcUhwzaaf8K4mksYI7AZ8la suqiEBf1ydEU731luaKbaaxC1Mq0213fFDflNwRL5qXQE8jN1i8prGskebMIqF1xZRJ8 DnBvS4ELObaotp+taEwekactUNNFj5eY/fg79DRksTflRH7fpYdVVqR9+h6FDqZQ1kOL FLGA== X-Gm-Message-State: AO0yUKXU4E/16Ava5hCM2la/9za1D1b90vVi6Bw1//K+9bvWHs2h6nX8 MA/AYlCgyMmQQx+tXsimFeM= X-Google-Smtp-Source: AK7set8FQiKx9PyqqRBGpJSwLkvvSYnDZTMshNoji8lnxnTWkMZgd62rr5xZ9bYCka32e9QjHRGMTg== X-Received: by 2002:a17:906:411:b0:88b:23bb:e61f with SMTP id d17-20020a170906041100b0088b23bbe61fmr3389222eja.25.1675151894622; Mon, 30 Jan 2023 23:58:14 -0800 (PST) Received: from curiosity ([80.211.22.60]) by smtp.gmail.com with ESMTPSA id e18-20020a17090681d200b0088519b92080sm4190546ejx.127.2023.01.30.23.58.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Jan 2023 23:58:13 -0800 (PST) Date: Tue, 31 Jan 2023 10:58:09 +0300 From: Sergey Matyukevich To: Bin Meng Cc: Alistair Francis , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng , Sergey Matyukevich , Richard Henderson Subject: Re: [PATCH] target/riscv: set tval for triggered watchpoints Message-ID: References: <20230130100757.721372-1-geomatsi@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=geomatsi@gmail.com; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 07:58:20 -0000 Hi Bin, > > > According to priviledged spec, if [sm]tval is written with a nonzero > > > value when a breakpoint exception occurs, then [sm]tval will contain > > > the faulting virtual address. Set tval to hit address when breakpoint > > > exception is triggered by hardware watchpoint. > > > > > > Signed-off-by: Sergey Matyukevich > > > > Thanks! > > > > Applied to riscv-to-apply.next > > Oops, too quick, but I have one comment :) > > > > > Alistair > > > > > --- > > > target/riscv/cpu_helper.c | 3 +++ > > > target/riscv/debug.c | 1 + > > > 2 files changed, 4 insertions(+) > > > > > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > > > index 9a28816521..d3be8c0511 100644 > > > --- a/target/riscv/cpu_helper.c > > > +++ b/target/riscv/cpu_helper.c > > > @@ -1641,6 +1641,9 @@ void riscv_cpu_do_interrupt(CPUState *cs) > > > case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: > > > tval = env->bins; > > > break; > > > + case RISCV_EXCP_BREAKPOINT: > > > + tval = env->badaddr; > > RISCV_EXCP_BREAKPOINT may come from 'ebreak' so we should test if this > exception comes from the debug module. > > The spec also says about icount trigger that: > > "If the trigger fires with action =0 then zero is written to the tval > CSR on the breakpoint trap." > > So we can't blindly set tval for every breakpoint exception. > Thanks for catching ! Initial idea was to set badaddr value only when it is needed in target/riscv/debug.c. For instance, icount code does not set badaddr, so tval will remain zero. On the other hand, breakpoint exception may come from ebreak and badaddr may keep non-zero value from some previous unrelated exception. Explicit check should be more safe, e.g. something like that: diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d3be8c0511..f1a0c65ad3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1642,7 +1642,10 @@ void riscv_cpu_do_interrupt(CPUState *cs) tval = env->bins; break; case RISCV_EXCP_BREAKPOINT: - tval = env->badaddr; + if (cs->watchpoint_hit) { + tval = cs->watchpoint_hit->hitaddr; + cs->watchpoint_hit = NULL; + } break; default: break; diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 48ef3c59ea..b091293069 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -761,8 +761,6 @@ void riscv_cpu_debug_excp_handler(CPUState *cs) if (cs->watchpoint_hit) { if (cs->watchpoint_hit->flags & BP_CPU) { - env->badaddr = cs->watchpoint_hit->hitaddr; - cs->watchpoint_hit = NULL; do_trigger_action(env, DBG_ACTION_BP); } } else { I will a fixup after testing. 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[200.148.13.157]) by smtp.gmail.com with ESMTPSA id k14-20020a056870350e00b0014813cc4a51sm5019723oah.29.2023.01.31.01.57.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 31 Jan 2023 01:57:51 -0800 (PST) Message-ID: <0be7a185-b023-31d4-d51e-a7dff59980ee@ventanamicro.com> Date: Tue, 31 Jan 2023 06:57:48 -0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [PATCH v4 3/3] hw/riscv: change riscv_compute_fdt_addr() semantics To: Bin Meng Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com References: <20230126135219.1054658-1-dbarboza@ventanamicro.com> <20230126135219.1054658-4-dbarboza@ventanamicro.com> <793f7432-4592-98a4-34e9-472c185be297@ventanamicro.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2001:4860:4864:20::2b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2b.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 09:57:56 -0000 On 1/30/23 22:00, Bin Meng wrote: > On Tue, Jan 31, 2023 at 1:16 AM Daniel Henrique Barboza > wrote: >> >> >> >> On 1/29/23 02:45, Bin Meng wrote: >>> On Thu, Jan 26, 2023 at 9:54 PM Daniel Henrique Barboza >>> wrote: >>>> >>>> As it is now, riscv_compute_fdt_addr() is receiving a dram_base, a >>>> mem_size (which is defaulted to MachineState::ram_size in all boards) >>>> and the FDT pointer. And it makes a very important assumption: the DRAM >>>> interval dram_base + mem_size is contiguous. This is indeed the case for >>>> most boards that uses a FDT. >>> >>> s/uses/use >>> >>>> >>>> The Icicle Kit board works with 2 distinct RAM banks that are separated >>>> by a gap. We have a lower bank with 1GiB size, a gap follows, then at >>>> 64GiB the high memory starts. MachineClass::default_ram_size for this >>>> board is set to 1.5Gb, and machine_init() is enforcing it as minimal RAM >>>> size, meaning that there we'll always have at least 512 MiB in the Hi >>>> RAM area. >>>> >>>> Using riscv_compute_fdt_addr() in this board is weird because not only >>>> the board has sparse RAM, and it's calling it using the base address of >>>> the Lo RAM area, but it's also using a mem_size that we have guarantees >>>> that it will go up to the Hi RAM. All the function assumptions doesn't >>>> work for this board. >>>> >>>> In fact, what makes the function works at all in this case is a >>>> coincidence. Commit 1a475d39ef54 introduced a 3GB boundary for the FDT, >>>> down from 4Gb, that is enforced if dram_base is lower than 3072 MiB. For >>>> the Icicle Kit board, memmap[MICROCHIP_PFSOC_DRAM_LO].base is 0x80000000 >>>> (2 Gb) and it has a 1Gb size, so it will fall in the conditions to put >>>> the FDT under a 3Gb address, which happens to be exactly at the end of >>>> DRAM_LO. If the base address of the Lo area started later than 3Gb this >>>> function would be unusable by the board. Changing any assumptions inside >>>> riscv_compute_fdt_addr() can also break it by accident as well. >>>> >>>> Let's change riscv_compute_fdt_addr() semantics to be appropriate to the >>>> Icicle Kit board and for future boards that might have sparse RAM >>>> topologies to worry about: >>>> >>>> - relieve the condition that the dram_base + mem_size area is contiguous, >>>> since this is already not the case today; >>>> >>>> - receive an extra 'dram_size' size attribute that refers to a contiguous >>>> RAM block that the board wants the FDT to reside on. >>>> >>>> Together with 'mem_size' and 'fdt', which are now now being consumed by a >>>> MachineState pointer, we're able to make clear assumptions based on the >>>> DRAM block and total mem_size available to ensure that the FDT will be put >>>> in a valid RAM address. >>>> >>> >>> Well written commit message. Thanks! >>> >>>> Signed-off-by: Daniel Henrique Barboza >>>> --- >>>> hw/riscv/boot.c | 38 ++++++++++++++++++++++++++------------ >>>> hw/riscv/microchip_pfsoc.c | 3 ++- >>>> hw/riscv/sifive_u.c | 3 ++- >>>> hw/riscv/spike.c | 3 ++- >>>> hw/riscv/virt.c | 3 ++- >>>> include/hw/riscv/boot.h | 4 ++-- >>>> 6 files changed, 36 insertions(+), 18 deletions(-) >>>> >>>> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c >>>> index a6f7b8ae8e..8f4991480b 100644 >>>> --- a/hw/riscv/boot.c >>>> +++ b/hw/riscv/boot.c >>>> @@ -284,33 +284,47 @@ out: >>>> } >>>> >>>> /* >>>> - * The FDT should be put at the farthest point possible to >>>> - * avoid overwriting it with the kernel/initrd. >>>> + * This function makes an assumption that the DRAM interval >>>> + * 'dram_base' + 'dram_size' is contiguous. >>>> * >>>> - * This function makes an assumption that the DRAM is >>>> - * contiguous. It also cares about 32-bit systems and >>>> - * will limit fdt_addr to be addressable by them even for >>>> - * 64-bit CPUs. >>>> + * Considering that 'dram_end' is the lowest value between >>>> + * the end of the DRAM block and MachineState->ram_size, the >>>> + * FDT location will vary according to 'dram_base': >>>> + * >>>> + * - if 'dram_base' is less that 3072 MiB, the FDT will be >>>> + * put at the lowest value between 3072 MiB and 'dram_end'; >>>> + * >>>> + * - if 'dram_base' is higher than 3072 MiB, the FDT will be >>>> + * put at 'dram_end'. >>>> * >>>> * The FDT is fdt_packed() during the calculation. >>>> */ >>>> -uint32_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size, >>>> - void *fdt) >>>> +hwaddr riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, >>> >>> Using hwaddr to represent a size looks weird. Although technically >>> they are the same ... I would leave this as it is. >> >> I'll leave it as it was back in patch 2 (uint64_t). >> >>> >>>> + MachineState *ms) >>>> { >>>> - uint64_t temp; >>>> - hwaddr dram_end = dram_base + mem_size; >>>> - int ret = fdt_pack(fdt); >>>> + int ret = fdt_pack(ms->fdt); >>>> + hwaddr dram_end, temp; >>>> int fdtsize; >>>> >>>> /* Should only fail if we've built a corrupted tree */ >>>> g_assert(ret == 0); >>>> >>>> - fdtsize = fdt_totalsize(fdt); >>>> + fdtsize = fdt_totalsize(ms->fdt); >>>> if (fdtsize <= 0) { >>>> error_report("invalid device-tree"); >>>> exit(1); >>>> } >>>> >>>> + /* >>>> + * A dram_size == 0, usually from a MemMapEntry[].size element, >>>> + * means that the DRAM block goes all the way to ms->ram_size. >>>> + */ >>>> + if (dram_size == 0x0) { >>>> + dram_end = dram_base + ms->ram_size; >>>> + } else { >>>> + dram_end = dram_base + MIN(ms->ram_size, dram_size); >>>> + } >>> >>> How about: >>> >>> g_assert(dram_size < ms->ram_size); >> >> I don't believe that dram_size > ms->ram_size should be an error. A board can >> have a declared MemMapEntry.size that is larger than its current setting of >> ms->ram_size. > > What use case is that? This updated function now has the assumption that: > > 1. dram_size being 0 meaning contiguous system RAM region from dram_base > 2. otherwise dram_size being the *first* contiguous system RAM region > from dram_base Yes, but that doesn't mean that dram_size is necessarily smaller than ms->ram_size. We don't have any board where this happens today but let's pretend that the Icicle Kit board didn't have the 1.5Gb minimal RAM restriction. Its first region has dram_size 1Gb: [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 }, So, if I start the board with 512M, ms->ram_size = 512M and this assert will trigger because dram_size = 1Gb. Thanks, Daniel > > We can use g_assert(dram_size < ms->ram_size) to catch either case. > >> >> >>> dram_end = dram_base + (dram_size ? dram_size : ms->ram_size); >> >> I can change the if/else statement up there for a ternary: >> >> dram_end = dram_base + (dram_size ? ms->ram_size : MIN(ms->ram_size, dram_size)) >> > > Regards, > Bin From MAILER-DAEMON Tue Jan 31 07:11:34 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMpU4-0003Jt-Qa for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 07:11:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMpTn-0003ER-T8; Tue, 31 Jan 2023 07:11:16 -0500 Received: from mail-ed1-x533.google.com ([2a00:1450:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMpTl-0008Ez-FV; Tue, 31 Jan 2023 07:11:15 -0500 Received: by mail-ed1-x533.google.com with SMTP id z11so14205230ede.1; Tue, 31 Jan 2023 04:11:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=3IPCPRHVk+uX0BnZnfk1IJfCqst8Hr8oNPuqTW/Qm9g=; b=FIX7lhVuEPvMjoWKyrHnjO/hrkVVP1JvM1eJYtKGXcljBYMWkN8giLBE/jX2qa34tV HIJG1lEHvVe51Fm7HaNcJyalSXVVESl769esntx2WPyGRDCKZeZD1RBSu7BGmdb9KBRB 5V4/tPKWGuRtgxeecjtzmeIMd2A/eem5yvVhroWn/+bm6jdE+37OiAjhFq9xZb14f1lM s3xcpq9JT6Xo7rh9mX24iwu8uyDHFjJVC3zvU504fXKmUmvsurzfZ4pLz12UlpFxWVeC oE2kvyaplDiPU3yyxYxmOzOk81G07rWFLxfOEY7qfMoQe/aUW/r7ChsGqGGPgSh+D1rm QR4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=3IPCPRHVk+uX0BnZnfk1IJfCqst8Hr8oNPuqTW/Qm9g=; b=iCdph3JLFqPHyqALMkmBpmH/bW5MHSp8Q8oSGiiEu4y+wV2V4XiYnaTHnK/ipFZjqB O7pn53kLxwBlBnVga25WyTBrO3GfqlXoE0KSHPK2D6H+phrXuoJ3uAhPyWvVcVtv5TIq VR0tPEhPUlXWICjBOtu/q34Qo97oRBNw0az6Oca3B/rQfe0m9rnQBDNIWEs0JgYjES00 6OvwMvWkP0vVUvmr1N/e81AGU1QYJLBjiuk6ziaJkNmZIExNSjaSIkdzIQvZVAXNtW/H PlNnS/bcAl5MDO/2/2ntjnU4hWVdLPKmq/a5tLCfpRAHONoUNi9M5cFDPGh6MN9kk9g6 P4ZQ== X-Gm-Message-State: AFqh2kqLKoflizforU2+FPfk0wtZ/r6/+ZlzSesNqpCUBN4dLtSm/2ZB hWD/LniYhCoevZiFskSyCquJ+q1+2DSvER+Xvzg= X-Google-Smtp-Source: AMrXdXu64MvRHeOCrAtBrwOljhRyFHbfSEbr3WE21WwFZ6RKbB8Jgk19ItwSMoWHXk8wKRWqECZfXUXZAbmvmT/7K0g= X-Received: by 2002:a05:6402:5288:b0:49e:66b8:a790 with SMTP id en8-20020a056402528800b0049e66b8a790mr10193966edb.47.1675167070606; Tue, 31 Jan 2023 04:11:10 -0800 (PST) MIME-Version: 1.0 References: <20230126135219.1054658-1-dbarboza@ventanamicro.com> <20230126135219.1054658-4-dbarboza@ventanamicro.com> <793f7432-4592-98a4-34e9-472c185be297@ventanamicro.com> <0be7a185-b023-31d4-d51e-a7dff59980ee@ventanamicro.com> In-Reply-To: <0be7a185-b023-31d4-d51e-a7dff59980ee@ventanamicro.com> From: Bin Meng Date: Tue, 31 Jan 2023 20:11:00 +0800 Message-ID: Subject: Re: [PATCH v4 3/3] hw/riscv: change riscv_compute_fdt_addr() semantics To: Daniel Henrique Barboza Cc: qemu-devel@nongnu.org, qemu-riscv@nongnu.org, alistair.francis@wdc.com Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=bmeng.cn@gmail.com; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 12:11:16 -0000 On Tue, Jan 31, 2023 at 5:57 PM Daniel Henrique Barboza wrote: > > > > On 1/30/23 22:00, Bin Meng wrote: > > On Tue, Jan 31, 2023 at 1:16 AM Daniel Henrique Barboza > > wrote: > >> > >> > >> > >> On 1/29/23 02:45, Bin Meng wrote: > >>> On Thu, Jan 26, 2023 at 9:54 PM Daniel Henrique Barboza > >>> wrote: > >>>> > >>>> As it is now, riscv_compute_fdt_addr() is receiving a dram_base, a > >>>> mem_size (which is defaulted to MachineState::ram_size in all boards) > >>>> and the FDT pointer. And it makes a very important assumption: the DRAM > >>>> interval dram_base + mem_size is contiguous. This is indeed the case for > >>>> most boards that uses a FDT. > >>> > >>> s/uses/use > >>> > >>>> > >>>> The Icicle Kit board works with 2 distinct RAM banks that are separated > >>>> by a gap. We have a lower bank with 1GiB size, a gap follows, then at > >>>> 64GiB the high memory starts. MachineClass::default_ram_size for this > >>>> board is set to 1.5Gb, and machine_init() is enforcing it as minimal RAM > >>>> size, meaning that there we'll always have at least 512 MiB in the Hi > >>>> RAM area. > >>>> > >>>> Using riscv_compute_fdt_addr() in this board is weird because not only > >>>> the board has sparse RAM, and it's calling it using the base address of > >>>> the Lo RAM area, but it's also using a mem_size that we have guarantees > >>>> that it will go up to the Hi RAM. All the function assumptions doesn't > >>>> work for this board. > >>>> > >>>> In fact, what makes the function works at all in this case is a > >>>> coincidence. Commit 1a475d39ef54 introduced a 3GB boundary for the FDT, > >>>> down from 4Gb, that is enforced if dram_base is lower than 3072 MiB. For > >>>> the Icicle Kit board, memmap[MICROCHIP_PFSOC_DRAM_LO].base is 0x80000000 > >>>> (2 Gb) and it has a 1Gb size, so it will fall in the conditions to put > >>>> the FDT under a 3Gb address, which happens to be exactly at the end of > >>>> DRAM_LO. If the base address of the Lo area started later than 3Gb this > >>>> function would be unusable by the board. Changing any assumptions inside > >>>> riscv_compute_fdt_addr() can also break it by accident as well. > >>>> > >>>> Let's change riscv_compute_fdt_addr() semantics to be appropriate to the > >>>> Icicle Kit board and for future boards that might have sparse RAM > >>>> topologies to worry about: > >>>> > >>>> - relieve the condition that the dram_base + mem_size area is contiguous, > >>>> since this is already not the case today; > >>>> > >>>> - receive an extra 'dram_size' size attribute that refers to a contiguous > >>>> RAM block that the board wants the FDT to reside on. > >>>> > >>>> Together with 'mem_size' and 'fdt', which are now now being consumed by a > >>>> MachineState pointer, we're able to make clear assumptions based on the > >>>> DRAM block and total mem_size available to ensure that the FDT will be put > >>>> in a valid RAM address. > >>>> > >>> > >>> Well written commit message. Thanks! > >>> > >>>> Signed-off-by: Daniel Henrique Barboza > >>>> --- > >>>> hw/riscv/boot.c | 38 ++++++++++++++++++++++++++------------ > >>>> hw/riscv/microchip_pfsoc.c | 3 ++- > >>>> hw/riscv/sifive_u.c | 3 ++- > >>>> hw/riscv/spike.c | 3 ++- > >>>> hw/riscv/virt.c | 3 ++- > >>>> include/hw/riscv/boot.h | 4 ++-- > >>>> 6 files changed, 36 insertions(+), 18 deletions(-) > >>>> > >>>> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > >>>> index a6f7b8ae8e..8f4991480b 100644 > >>>> --- a/hw/riscv/boot.c > >>>> +++ b/hw/riscv/boot.c > >>>> @@ -284,33 +284,47 @@ out: > >>>> } > >>>> > >>>> /* > >>>> - * The FDT should be put at the farthest point possible to > >>>> - * avoid overwriting it with the kernel/initrd. > >>>> + * This function makes an assumption that the DRAM interval > >>>> + * 'dram_base' + 'dram_size' is contiguous. > >>>> * > >>>> - * This function makes an assumption that the DRAM is > >>>> - * contiguous. It also cares about 32-bit systems and > >>>> - * will limit fdt_addr to be addressable by them even for > >>>> - * 64-bit CPUs. > >>>> + * Considering that 'dram_end' is the lowest value between > >>>> + * the end of the DRAM block and MachineState->ram_size, the > >>>> + * FDT location will vary according to 'dram_base': > >>>> + * > >>>> + * - if 'dram_base' is less that 3072 MiB, the FDT will be > >>>> + * put at the lowest value between 3072 MiB and 'dram_end'; > >>>> + * > >>>> + * - if 'dram_base' is higher than 3072 MiB, the FDT will be > >>>> + * put at 'dram_end'. > >>>> * > >>>> * The FDT is fdt_packed() during the calculation. > >>>> */ > >>>> -uint32_t riscv_compute_fdt_addr(hwaddr dram_base, uint64_t mem_size, > >>>> - void *fdt) > >>>> +hwaddr riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, > >>> > >>> Using hwaddr to represent a size looks weird. Although technically > >>> they are the same ... I would leave this as it is. > >> > >> I'll leave it as it was back in patch 2 (uint64_t). > >> > >>> > >>>> + MachineState *ms) > >>>> { > >>>> - uint64_t temp; > >>>> - hwaddr dram_end = dram_base + mem_size; > >>>> - int ret = fdt_pack(fdt); > >>>> + int ret = fdt_pack(ms->fdt); > >>>> + hwaddr dram_end, temp; > >>>> int fdtsize; > >>>> > >>>> /* Should only fail if we've built a corrupted tree */ > >>>> g_assert(ret == 0); > >>>> > >>>> - fdtsize = fdt_totalsize(fdt); > >>>> + fdtsize = fdt_totalsize(ms->fdt); > >>>> if (fdtsize <= 0) { > >>>> error_report("invalid device-tree"); > >>>> exit(1); > >>>> } > >>>> > >>>> + /* > >>>> + * A dram_size == 0, usually from a MemMapEntry[].size element, > >>>> + * means that the DRAM block goes all the way to ms->ram_size. > >>>> + */ > >>>> + if (dram_size == 0x0) { > >>>> + dram_end = dram_base + ms->ram_size; > >>>> + } else { > >>>> + dram_end = dram_base + MIN(ms->ram_size, dram_size); > >>>> + } > >>> > >>> How about: > >>> > >>> g_assert(dram_size < ms->ram_size); > >> > >> I don't believe that dram_size > ms->ram_size should be an error. A board can > >> have a declared MemMapEntry.size that is larger than its current setting of > >> ms->ram_size. > > > > What use case is that? This updated function now has the assumption that: > > > > 1. dram_size being 0 meaning contiguous system RAM region from dram_base > > 2. otherwise dram_size being the *first* contiguous system RAM region > > from dram_base > > Yes, but that doesn't mean that dram_size is necessarily smaller than ms->ram_size. > > We don't have any board where this happens today but let's pretend that the Icicle > Kit board didn't have the 1.5Gb minimal RAM restriction. Its first region has > dram_size 1Gb: > > [MICROCHIP_PFSOC_DRAM_LO] = { 0x80000000, 0x40000000 }, > > So, if I start the board with 512M, ms->ram_size = 512M and this assert will trigger > because dram_size = 1Gb. > Ah, I see. So for a machine whose memory size can be dynamically configured, yes that makes sense. Regards, Bin From MAILER-DAEMON Tue Jan 31 07:33:39 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMppT-0003DO-DM for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 07:33:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMppI-0003Cs-JM; Tue, 31 Jan 2023 07:33:37 -0500 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMpp7-0005px-28; Tue, 31 Jan 2023 07:33:28 -0500 Received: by mail-ed1-x536.google.com with SMTP id f7so7012770edw.5; Tue, 31 Jan 2023 04:32:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=343+g5zUBf606CxH8xv2eXqZDYhg3GIX04y6gCLwQdA=; b=i+jM3C2vetHZF3nRtPpSgMU3dIofSKgi1X1SYHLJPOFoOvJtWB/zz4WfIUlM/nxH9E MdCLO+H9ESKp98/1rRo0eOX8I+cC9qr3IXVXrDxf+mKcCrPchNOnh+nzmQ4h2beCDzBB Wc8LJw75hJOukg7HRnpva4VH3iGU2lx3PdyABW3FZt9Mz1st8E5YStdFuCzRylBy6+qa CMtFY61F1rHmNi64J8P+83OO0gLvKn8VLb0H7RsYotnjBstZ4hnXaGactbUjXiJuSChR /068FdPKHLjYVSJlPR0mwUoMhgUqken1YHed4Fwz/EkD8KrjZVk4i3F48IUpJSJD/hIr UANw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=343+g5zUBf606CxH8xv2eXqZDYhg3GIX04y6gCLwQdA=; b=FJLL44bodZJHVJSJgBcrSxZlvvrogIQMC8jU5Bli8LiGcoaOvPw4ch2G7+WmhrNdkM V+SDS/Br/mLHi17y2wHvYfkfszM1Ecc2aZEwxA1z6rrEVVCUgguFlhy+Lk/1pqRr3lvp 8NsLgx03Y7f5O0RPWp1izqzcTd31pb+JJC6cFMoKWP5wksREONQH6ovLiwTsx8oq1uLa oLQlip+FZQ0DKdzn4SP6hiz5hH1KoIXuIWxeMxeZ1g5k7XB+PgSQBC2FqNK6Mr9a5/0D JTOqVyiBcgWzTFsxJDvQLO2DYz16kq8WuQGKTskG1jT7LosgTPK8uvfXPZukelQswumj 61bg== X-Gm-Message-State: AFqh2kqbNOGUdCpq47DWgfg7Rg5DdrV+7hRtpW5J8lPT4y0w6WFwsMxU C47DdJEoZ+oT9rMCEyg4y/PY2FT1c5GcaMdtbeI= X-Google-Smtp-Source: AMrXdXuHnAEkLM+YabpiqvYOR1begTWcYK6q3x4XD5yK6A8HTpgWiK3j/t2qq/a59S2j4O2BhEdNO3zsQT2UyX+6pxU= X-Received: by 2002:a05:6402:20f:b0:49c:a68c:8b6b with SMTP id t15-20020a056402020f00b0049ca68c8b6bmr10420701edv.84.1675168316685; Tue, 31 Jan 2023 04:31:56 -0800 (PST) MIME-Version: 1.0 References: <20230123035754.75553-1-alistair.francis@opensource.wdc.com> In-Reply-To: From: Bin Meng Date: Tue, 31 Jan 2023 20:31:46 +0800 Message-ID: Subject: Re: [PATCH] hw/riscv: boot: Don't use CSRs if they are disabled To: Alistair Francis Cc: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair.francis@wdc.com, Bin Meng Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=bmeng.cn@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 12:33:37 -0000 On Mon, Jan 30, 2023 at 7:19 AM Alistair Francis wrote: > > On Thu, Jan 26, 2023 at 10:03 PM Bin Meng wrote: > > > > On Tue, Jan 24, 2023 at 9:42 AM Alistair Francis wrote: > > > > > > On Tue, Jan 24, 2023 at 11:24 AM Bin Meng wrote: > > > > > > > > On Mon, Jan 23, 2023 at 11:58 AM Alistair Francis > > > > wrote: > > > > > > > > > > From: Alistair Francis > > > > > > > > > > If the CSRs and CSR instructions are disabled because the Zicsr > > > > > extension isn't enabled then we want to make sure we don't run any CSR > > > > > instructions in the boot ROM. > > > > > > > > > > This patches removes the CSR instructions from the reset-vec if the > > > > > extension isn't enabled. We replace the instruction with a NOP instead. > > > > > > > > > > Note that we don't do this for the SiFive U machine, as we are modelling > > > > > the hardware in that case. > > > > > > > > > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1447 > > > > > Signed-off-by: Alistair Francis > > > > > --- > > > > > hw/riscv/boot.c | 9 +++++++++ > > > > > 1 file changed, 9 insertions(+) > > > > > > > > > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > > > > > index 2594276223..cb27798a25 100644 > > > > > --- a/hw/riscv/boot.c > > > > > +++ b/hw/riscv/boot.c > > > > > @@ -356,6 +356,15 @@ void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts > > > > > reset_vec[4] = 0x0182b283; /* ld t0, 24(t0) */ > > > > > } > > > > > > > > > > + if (!harts->harts[0].cfg.ext_icsr) { > > > > > + /* > > > > > + * The Zicsr extension has been disabled, so let's ensure we don't > > > > > + * run the CSR instruction. Let's fill the address with a non > > > > > + * compressed nop. > > > > > + */ > > > > > + reset_vec[2] = 0x00000013; /* addi x0, x0, 0 */ > > > > > + } > > > > > > > > This is fine for a UP system. I am not sure how SMP can be supported > > > > without Zicsr as we need to assign hartid in a0. > > > > > > Yeah. My thinking was that no one would be using a multicore system > > > without Zicsr as it's such a core extension. If they are running > > > without Zicsr they have probably hard coded a lot of things anyway and > > > don't expect this to work. > > > > > > In general I think it's pretty rare to even run a RISC-V core without > > > Zicsr at all. > > > > > > > As QEMU implements Zicsr anyway, and there is no way to support SMP > > without Zicsr, should we disallow user to disable Zicsr in QEMU? > > I feel like we don't need to do that. Here's my thinking: > > Zicsr is a RISC-V extension, the RISC-V spec splits it out so that it > can be disabled. In theory someone could build a multi-hart CPU > without Zicsr in hardware, so QEMU should be able to model it. Correct. But if Zicsr is not present, then the standard privileged architecture which qemu-system-riscv currently supports, is inherently not present, either. If a user chooses to disable Zicsr, current QEMU system emulation is useless then. That's why I believe we shouldn't allow users to disable Zicsr for qemu-system-riscv. > As well as that Zicsr is enabled by default, so a user has to know > enough to disable it manually. At which point they probably know what > they are doing, especially as no standard software will run without > Zicsr. If that's what someone wants to do then we should allow them > to, even if it's a bit strange. > For qemu-riscv, disabling Zicsr is feasible as long as the codes does not touch any CSR, e.g.: timer, counters, fcsr, etc. Regards, Bin From MAILER-DAEMON Tue Jan 31 08:05:21 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMqK9-00017T-Ax for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 08:05:21 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMqK8-00017F-Bx for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 08:05:20 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMqJs-00018C-3O for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 08:05:20 -0500 Received: by mail-wm1-x329.google.com with SMTP id bg26so4442406wmb.0 for ; Tue, 31 Jan 2023 05:05:01 -0800 (PST) DKIM-Signature: v=1; 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Tue, 31 Jan 2023 05:04:26 -0800 (PST) MIME-Version: 1.0 References: <20230125162010.1615787-1-alexghiti@rivosinc.com> <20230125162010.1615787-4-alexghiti@rivosinc.com> <20230125165239.tmooowvwq7zez76y@orel> In-Reply-To: <20230125165239.tmooowvwq7zez76y@orel> From: Alexandre Ghiti Date: Tue, 31 Jan 2023 14:04:15 +0100 Message-ID: Subject: Re: [PATCH v8 3/5] riscv: Allow user to set the satp mode To: Andrew Jones Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x329.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 13:05:20 -0000 On Wed, Jan 25, 2023 at 5:52 PM Andrew Jones wrote: > > On Wed, Jan 25, 2023 at 05:20:08PM +0100, Alexandre Ghiti wrote: > > RISC-V specifies multiple sizes for addressable memory and Linux probes for > > the machine's support at startup via the satp CSR register (done in > > csr.c:validate_vm). > > > > As per the specification, sv64 must support sv57, which in turn must > > support sv48...etc. So we can restrict machine support by simply setting the > > "highest" supported mode and the bare mode is always supported. > > > > You can set the satp mode using the new properties "sv32", "sv39", "sv48", > > "sv57" and "sv64" as follows: > > -cpu rv64,sv57=on # Linux will boot using sv57 scheme > > -cpu rv64,sv39=on # Linux will boot using sv39 scheme > > -cpu rv64,sv57=off # Linux will boot using sv48 scheme > > -cpu rv64 # Linux will boot using sv57 scheme by default > > > > We take the highest level set by the user: > > -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme > > > > We make sure that invalid configurations are rejected: > > -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are > > # enabled > > > > We accept "redundant" configurations: > > -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme > > > > And contradictory configurations: > > -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme > > > > Co-Developed-by: Ludovic Henry > > Signed-off-by: Ludovic Henry > > Signed-off-by: Alexandre Ghiti > > --- > > target/riscv/cpu.c | 206 +++++++++++++++++++++++++++++++++++++++++++++ > > target/riscv/cpu.h | 19 +++++ > > target/riscv/csr.c | 12 ++- > > 3 files changed, 230 insertions(+), 7 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 7181b34f86..54494a72be 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -27,6 +27,7 @@ > > #include "time_helper.h" > > #include "exec/exec-all.h" > > #include "qapi/error.h" > > +#include "qapi/visitor.h" > > #include "qemu/error-report.h" > > #include "hw/qdev-properties.h" > > #include "migration/vmstate.h" > > @@ -229,6 +230,81 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) > > env->vext_ver = vext_ver; > > } > > > > +static uint8_t satp_mode_from_str(const char *satp_mode_str) > > +{ > > + if (!strncmp(satp_mode_str, "mbare", 5)) { > > + return VM_1_10_MBARE; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv32", 4)) { > > + return VM_1_10_SV32; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv39", 4)) { > > + return VM_1_10_SV39; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv48", 4)) { > > + return VM_1_10_SV48; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv57", 4)) { > > + return VM_1_10_SV57; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv64", 4)) { > > + return VM_1_10_SV64; > > + } > > + > > + g_assert_not_reached(); > > +} > > + > > +uint8_t satp_mode_max_from_map(uint32_t map) > > +{ > > + /* map here has at least one bit set, so no problem with clz */ > > + return 31 - __builtin_clz(map); > > +} > > + > > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > > +{ > > + if (is_32_bit) { > > + switch (satp_mode) { > > + case VM_1_10_SV32: > > + return "sv32"; > > + case VM_1_10_MBARE: > > + return "none"; > > + } > > + } else { > > + switch (satp_mode) { > > + case VM_1_10_SV64: > > + return "sv64"; > > + case VM_1_10_SV57: > > + return "sv57"; > > + case VM_1_10_SV48: > > + return "sv48"; > > + case VM_1_10_SV39: > > + return "sv39"; > > + case VM_1_10_MBARE: > > + return "none"; > > + } > > + } > > + > > + g_assert_not_reached(); > > +} > > + > > +/* Sets the satp mode to the max supported */ > > +static void set_satp_mode_default(RISCVCPU *cpu) > > +{ > > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > > + > > + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > > + cpu->cfg.satp_mode.map |= > > + (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); > > + } else { > > + cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > > + } > > +} > > + > > static void riscv_any_cpu_init(Object *obj) > > { > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > @@ -619,6 +695,82 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > > } > > } > > > > +static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > > +{ > > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > > + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > > + uint8_t satp_mode_max; > > + > > + if (cpu->cfg.satp_mode.map == 0) { > > + if (cpu->cfg.satp_mode.init == 0) { > > + /* If unset by the user, we fallback to the default satp mode. */ > > + set_satp_mode_default(cpu); > > + } else { > > + /* > > + * Find the lowest level that was disabled and then enable the > > + * first valid level below which can be found in > > + * valid_vm_1_10_32/64. > > + */ > > + for (int i = 1; i < 16; ++i) { > > + if ((cpu->cfg.satp_mode.init & (1 << i)) && > > + valid_vm[i]) { > > nit: Could have brought this valid_vm[i] up now that everything fits on > one line. > Fixed in v9, thanks. > > + for (int j = i - 1; j >= 0; --j) { > > + if (valid_vm[j]) { > > + cpu->cfg.satp_mode.map |= (1 << j); > > + break; > > + } > > + } > > + break; > > + } > > + } > > + } > > + } > > + > > + /* Make sure the configuration asked is supported by qemu */ > > + for (int i = 0; i < 16; ++i) { > > + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > > + error_setg(errp, "satp_mode %s is not valid", > > + satp_mode_str(i, rv32)); > > + return; > > + } > > + } > > + > > + /* > > + * Make sure the user did not ask for an invalid configuration as per > > + * the specification. > > + */ > > + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > > + > > + if (!rv32) { > > + for (int i = satp_mode_max - 1; i >= 0; --i) { > > + if (!(cpu->cfg.satp_mode.map & (1 << i)) && > > + (cpu->cfg.satp_mode.init & (1 << i)) && > > + valid_vm[i]) { > > + error_setg(errp, "cannot disable %s satp mode if %s " > > + "is enabled", satp_mode_str(i, false), > > + satp_mode_str(satp_mode_max, false)); > > + return; > > + } > > + } > > + } > > + > > + /* Finally expand the map so that all valid modes are set */ > > + for (int i = satp_mode_max - 1; i >= 0; --i) { > > + cpu->cfg.satp_mode.map |= (1 << i); > > + } > > +} > > + > > +static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > > +{ > > + Error *local_err = NULL; > > + > > + riscv_cpu_satp_mode_finalize(cpu, &local_err); > > + if (local_err != NULL) { > > + error_propagate(errp, local_err); > > + return; > > + } > > +} > > + > > static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > { > > CPUState *cs = CPU(dev); > > @@ -919,6 +1071,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > } > > #endif > > > > + riscv_cpu_finalize_features(cpu, &local_err); > > + if (local_err != NULL) { > > + error_propagate(errp, local_err); > > + return; > > + } > > + > > riscv_cpu_register_gdb_regs_for_features(cs); > > > > qemu_init_vcpu(cs); > > @@ -927,6 +1085,52 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > mcc->parent_realize(dev, errp); > > } > > > > +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, > > + void *opaque, Error **errp) > > +{ > > + RISCVSATPMap *satp_map = opaque; > > + uint8_t satp = satp_mode_from_str(name); > > + bool value; > > + > > + value = (satp_map->map & (1 << satp)); > > + > > + visit_type_bool(v, name, &value, errp); > > +} > > + > > +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, > > + void *opaque, Error **errp) > > +{ > > + RISCVSATPMap *satp_map = opaque; > > + uint8_t satp = satp_mode_from_str(name); > > + bool value; > > + > > + if (!visit_type_bool(v, name, &value, errp)) { > > + return; > > + } > > + > > + satp_map->map = deposit32(satp_map->map, satp, 1, value); > > + satp_map->init |= 1 << satp; > > +} > > + > > +static void riscv_add_satp_mode_properties(Object *obj) > > +{ > > + RISCVCPU *cpu = RISCV_CPU(obj); > > + > > + if (cpu->env.misa_mxl == MXL_RV32) { > > + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + } else { > > + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + } > > +} > > + > > #ifndef CONFIG_USER_ONLY > > static void riscv_cpu_set_irq(void *opaque, int irq, int level) > > { > > @@ -1091,6 +1295,8 @@ static void register_cpu_props(Object *obj) > > for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > > qdev_property_add_static(dev, prop); > > } > > + > > + riscv_add_satp_mode_properties(obj); > > } > > > > static Property riscv_cpu_properties[] = { > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index f5609b62a2..e37177db5c 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -27,6 +27,7 @@ > > #include "qom/object.h" > > #include "qemu/int128.h" > > #include "cpu_bits.h" > > +#include "qapi/qapi-types-common.h" > > > > #define TCG_GUEST_DEFAULT_MO 0 > > > > @@ -413,6 +414,17 @@ struct RISCVCPUClass { > > ResettablePhases parent_phases; > > }; > > > > +/* > > + * map is a 16-bit bitmap: the most significant set bit in map is the maximum > > + * satp mode that is supported. > > + * > > + * init is a 16-bit bitmap used to make sure the user selected a correct > > + * configuration as per the specification. > > + */ > > +typedef struct { > > + uint16_t map, init; > > +} RISCVSATPMap; > > + > > struct RISCVCPUConfig { > > bool ext_i; > > bool ext_e; > > @@ -488,6 +500,8 @@ struct RISCVCPUConfig { > > bool debug; > > > > bool short_isa_string; > > + > > + RISCVSATPMap satp_mode; > > }; > > > > typedef struct RISCVCPUConfig RISCVCPUConfig; > > @@ -794,9 +808,14 @@ enum riscv_pmu_event_idx { > > /* CSR function table */ > > extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; > > > > +extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; > > + > > void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); > > void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); > > > > void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); > > > > +uint8_t satp_mode_max_from_map(uint32_t map); > > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); > > + > > #endif /* RISCV_CPU_H */ > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 6b157806a5..3c02055825 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -1117,12 +1117,12 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; > > static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; > > static const target_ulong vsip_writable_mask = MIP_VSSIP; > > > > -static const bool valid_vm_1_10_32[16] = { > > +const bool valid_vm_1_10_32[16] = { > > [VM_1_10_MBARE] = true, > > [VM_1_10_SV32] = true > > }; > > > > -static const bool valid_vm_1_10_64[16] = { > > +const bool valid_vm_1_10_64[16] = { > > [VM_1_10_MBARE] = true, > > [VM_1_10_SV39] = true, > > [VM_1_10_SV48] = true, > > @@ -1211,11 +1211,9 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, > > > > static bool validate_vm(CPURISCVState *env, target_ulong vm) > > { > > - if (riscv_cpu_mxl(env) == MXL_RV32) { > > - return valid_vm_1_10_32[vm & 0xf]; > > - } else { > > - return valid_vm_1_10_64[vm & 0xf]; > > - } > > + RISCVCPU *cpu = RISCV_CPU(env_cpu(env)); > > + > > + return ((vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map)); > > } > > > > static RISCVException write_mstatus(CPURISCVState *env, int csrno, > > -- > > 2.37.2 > > > > Other than the minor nit > > Reviewed-by: Andrew Jones \o/ Thanks for all your reviews Andrew, Alex > > Thanks, > drew From MAILER-DAEMON Tue Jan 31 08:30:46 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMqik-0002Bb-3g for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 08:30:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMqih-0002BH-8v for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 08:30:43 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMqiE-0003H7-2i for qemu-riscv@nongnu.org; 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b=RXPjQwgLPcYnqsgJ7VT1eq58O8XHORJqFCYoN/14xm82HpJQlmNJVNgO1s26ttTFQ3 vD2KV9z+Nj9/mPZFBSRtePK/qcAZPFCLnOKUnVC0LRkqEjCJiND5wsjU8puLR7r6qKM8 nO9BDrKQZeuGCS/zqySJt/Y84WyFS5YMa4wpplxhkzK+Ir9nIKMHwZpXU9GIOET6M95Q u2zYv2CYprck3iJ44sDRepOG50zOpintk3EDWmr3qBlLGqbo/FZuh5Xft/Yo9TxNLGHX pUvIz2gX/76VY49pUoZtP0zkr8doAswbSyvNrWP278C75Dj4fDFyMLmY5UPjgGGZnjGX oe7A== X-Gm-Message-State: AO0yUKX4G0Mrnacxe31lst0JwFu+X0fvcX3K9Kt9MNf0Olbi5u7hIJGd +2d8pcMyRwQulINjt9m5Dcf2/GQCvrapBzW8YjsVQg== X-Google-Smtp-Source: AK7set/BIMYfnBIyvdz7CirIE/8oLH0Ug80IdsJwdyL2qg0WBq/Kj3MGyJXj29bPCkpkomr/DNFaK1J3s8JWEfJFiEE= X-Received: by 2002:adf:e708:0:b0:2c2:de2b:e7d1 with SMTP id c8-20020adfe708000000b002c2de2be7d1mr49754wrm.55.1675171803539; Tue, 31 Jan 2023 05:30:03 -0800 (PST) MIME-Version: 1.0 References: <20230125162010.1615787-1-alexghiti@rivosinc.com> <20230125162010.1615787-5-alexghiti@rivosinc.com> In-Reply-To: From: Alexandre Ghiti Date: Tue, 31 Jan 2023 14:29:52 +0100 Message-ID: Subject: Re: [PATCH v8 4/5] riscv: Introduce satp mode hw capabilities To: Bin Meng Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 13:30:43 -0000 On Mon, Jan 30, 2023 at 5:29 AM Bin Meng wrote: > > On Thu, Jan 26, 2023 at 12:24 AM Alexandre Ghiti wrote: > > > > Currently, the max satp mode is set with the only constraint that it must be > > implemented in qemu, i.e. set in valid_vm_1_10_[32|64]. > > nits: s/qemu/QEMU/g Ok > > > > > But we actually need to add another level of constraint: what the hw is > > actually capable of, because currently, a linux booting on a sifive-u54 > > boots in sv57 mode which is incompatible with the cpu's sv39 max > > capability. > > > > So add a new bitmap to RISCVSATPMap which contains this capability and > > initialize it in every XXX_cpu_init. > > > > Finally: > > - valid_vm_1_10_[32|64] constrains which satp mode the CPU can use > > - the CPU hw capabilities constrains what the user may select > > - the user's selection then constrains what's available to the guest > > OS. > > > > Signed-off-by: Alexandre Ghiti > > Reviewed-by: Andrew Jones > > --- > > target/riscv/cpu.c | 74 +++++++++++++++++++++++++++++++--------------- > > target/riscv/cpu.h | 8 +++-- > > 2 files changed, 56 insertions(+), 26 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 54494a72be..e7e1fb96dc 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -292,26 +292,36 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > > g_assert_not_reached(); > > } > > > > -/* Sets the satp mode to the max supported */ > > -static void set_satp_mode_default(RISCVCPU *cpu) > > +static void set_satp_mode_max_supported(RISCVCPU *cpu, > > + uint8_t satp_mode) > > { > > bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > > + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > > > > - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > > - cpu->cfg.satp_mode.map |= > > - (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); > > - } else { > > - cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > > + for (int i = 0; i <= satp_mode; ++i) { > > + if (valid_vm[i]) { > > + cpu->cfg.satp_mode.supported |= (1 << i); > > + } > > } > > } > > > > +/* Sets the satp mode to the max supported */ > > nits: s/Sets/Set Ok > > > +static void set_satp_mode_default(RISCVCPU *cpu) > > +{ > > + cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; > > +} > > + > > static void riscv_any_cpu_init(Object *obj) > > { > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > + RISCVCPU *cpu = RISCV_CPU(obj); > > + > > #if defined(TARGET_RISCV32) > > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > > + set_satp_mode_max_supported(cpu, VM_1_10_SV32); > > #elif defined(TARGET_RISCV64) > > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > > + set_satp_mode_max_supported(cpu, VM_1_10_SV57); > > #endif > > set_priv_version(env, PRIV_VERSION_1_12_0); > > register_cpu_props(obj); > > @@ -321,18 +331,24 @@ static void riscv_any_cpu_init(Object *obj) > > static void rv64_base_cpu_init(Object *obj) > > { > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > + RISCVCPU *cpu = RISCV_CPU(obj); > > + > > /* We set this in the realise function */ > > set_misa(env, MXL_RV64, 0); > > register_cpu_props(obj); > > /* Set latest version of privileged specification */ > > set_priv_version(env, PRIV_VERSION_1_12_0); > > + set_satp_mode_max_supported(cpu, VM_1_10_SV57); > > } > > > > static void rv64_sifive_u_cpu_init(Object *obj) > > { > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > + RISCVCPU *cpu = RISCV_CPU(obj); > > + > > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > > set_priv_version(env, PRIV_VERSION_1_10_0); > > + set_satp_mode_max_supported(cpu, VM_1_10_SV39); > > } > > > > static void rv64_sifive_e_cpu_init(Object *obj) > > @@ -343,6 +359,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) > > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); > > set_priv_version(env, PRIV_VERSION_1_10_0); > > cpu->cfg.mmu = false; > > + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > > } > > > > static void rv128_base_cpu_init(Object *obj) > > @@ -354,11 +371,13 @@ static void rv128_base_cpu_init(Object *obj) > > exit(EXIT_FAILURE); > > } > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > + RISCVCPU *cpu = RISCV_CPU(obj); > > /* We set this in the realise function */ > > set_misa(env, MXL_RV128, 0); > > register_cpu_props(obj); > > /* Set latest version of privileged specification */ > > set_priv_version(env, PRIV_VERSION_1_12_0); > > + set_satp_mode_max_supported(cpu, VM_1_10_SV57); > > } > > #else > > static void rv32_base_cpu_init(Object *obj) > > @@ -369,13 +388,17 @@ static void rv32_base_cpu_init(Object *obj) > > register_cpu_props(obj); > > /* Set latest version of privileged specification */ > > set_priv_version(env, PRIV_VERSION_1_12_0); > > + set_satp_mode_max_supported(cpu, VM_1_10_SV32); > > Does this compile? 'cpu' seems undeclared ..? Oops, thanks. > > > } > > > > static void rv32_sifive_u_cpu_init(Object *obj) > > { > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > + RISCVCPU *cpu = RISCV_CPU(obj); > > + > > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > > set_priv_version(env, PRIV_VERSION_1_10_0); > > + set_satp_mode_max_supported(cpu, VM_1_10_SV32); > > } > > > > static void rv32_sifive_e_cpu_init(Object *obj) > > @@ -386,6 +409,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) > > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); > > set_priv_version(env, PRIV_VERSION_1_10_0); > > cpu->cfg.mmu = false; > > + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > > } > > > > static void rv32_ibex_cpu_init(Object *obj) > > @@ -396,6 +420,7 @@ static void rv32_ibex_cpu_init(Object *obj) > > set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); > > set_priv_version(env, PRIV_VERSION_1_11_0); > > cpu->cfg.mmu = false; > > + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > > cpu->cfg.epmp = true; > > } > > > > @@ -407,6 +432,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); > > set_priv_version(env, PRIV_VERSION_1_10_0); > > cpu->cfg.mmu = false; > > + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > > } > > #endif > > > > @@ -698,8 +724,9 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > > static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > > { > > bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > > - const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > > - uint8_t satp_mode_max; > > + uint8_t satp_mode_map_max; > > + uint8_t satp_mode_supported_max = > > + satp_mode_max_from_map(cpu->cfg.satp_mode.supported); > > > > if (cpu->cfg.satp_mode.map == 0) { > > if (cpu->cfg.satp_mode.init == 0) { > > @@ -713,9 +740,9 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > > */ > > for (int i = 1; i < 16; ++i) { > > if ((cpu->cfg.satp_mode.init & (1 << i)) && > > - valid_vm[i]) { > > + (cpu->cfg.satp_mode.supported & (1 << i))) { > > for (int j = i - 1; j >= 0; --j) { > > - if (valid_vm[j]) { > > + if (cpu->cfg.satp_mode.supported & (1 << j)) { > > cpu->cfg.satp_mode.map |= (1 << j); > > break; > > } > > @@ -726,36 +753,35 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > > } > > } > > > > - /* Make sure the configuration asked is supported by qemu */ > > - for (int i = 0; i < 16; ++i) { > > - if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > > - error_setg(errp, "satp_mode %s is not valid", > > - satp_mode_str(i, rv32)); > > - return; > > - } > > + satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > > + > > + /* Make sure the user asked for a supported configuration (HW and qemu) */ > > + if (satp_mode_map_max > satp_mode_supported_max) { > > + error_setg(errp, "satp_mode %s is higher than hw max capability %s", > > + satp_mode_str(satp_mode_map_max, rv32), > > + satp_mode_str(satp_mode_supported_max, rv32)); > > + return; > > } > > > > /* > > * Make sure the user did not ask for an invalid configuration as per > > * the specification. > > */ > > - satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > > - > > if (!rv32) { > > - for (int i = satp_mode_max - 1; i >= 0; --i) { > > + for (int i = satp_mode_map_max - 1; i >= 0; --i) { > > if (!(cpu->cfg.satp_mode.map & (1 << i)) && > > (cpu->cfg.satp_mode.init & (1 << i)) && > > - valid_vm[i]) { > > + (cpu->cfg.satp_mode.supported & (1 << i))) { > > error_setg(errp, "cannot disable %s satp mode if %s " > > "is enabled", satp_mode_str(i, false), > > - satp_mode_str(satp_mode_max, false)); > > + satp_mode_str(satp_mode_map_max, false)); > > return; > > } > > } > > } > > > > /* Finally expand the map so that all valid modes are set */ > > - for (int i = satp_mode_max - 1; i >= 0; --i) { > > + for (int i = satp_mode_map_max - 1; i >= 0; --i) { > > cpu->cfg.satp_mode.map |= (1 << i); > > } > > } > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index e37177db5c..b591122099 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -416,13 +416,17 @@ struct RISCVCPUClass { > > > > /* > > * map is a 16-bit bitmap: the most significant set bit in map is the maximum > > - * satp mode that is supported. > > + * satp mode that is supported. It may be chosen by the user and must respect > > + * what qemu implements (valid_1_10_32/64) and what the hw is capable of > > + * (supported bitmap below). > > * > > * init is a 16-bit bitmap used to make sure the user selected a correct > > * configuration as per the specification. > > + * > > + * supported is a 16-bit bitmap used to reflect the hw capabilities. > > */ > > typedef struct { > > - uint16_t map, init; > > + uint16_t map, init, supported; > > } RISCVSATPMap; > > > > struct RISCVCPUConfig { > > -- > > Regards, > Bin Thanks again, Alex From MAILER-DAEMON Tue Jan 31 08:39:16 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMqqx-0003AI-U3 for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 08:39:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMqqv-00037P-64 for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 08:39:13 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMqqs-0005OC-Gs for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 08:39:12 -0500 Received: by mail-wr1-x429.google.com with SMTP id h12so14217350wrv.10 for ; Tue, 31 Jan 2023 05:39:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=UBPBK/8WVUG281weFxX1rWV/1Fu5J7obKJ2aND06KEs=; b=eBsyw5GVD1D1B+FTX9KqHG0UNkBZagfyYcVNeLNuob1+jAkfgBEKC4lfBsekH6MqpZ JHw59HfseulJkKhMcg5OtfSgo9dILwsKSxKpEKHEbYR2fP8oybt5Sti0dVmrYio/JG6q MAx4rUcum80brvXGSuIwNRWxGdaabid+DxTkubKBBg8Al5tfosAoYRP4x3Cz35pfHpFz gsry9H2QnoP7HVp6GtSMvgh+sXkGv+PqoIPDi3ta4Mjo1OYmF4GOzmDaK2CeO6Z0Y+hj Ai0jOwRDMQPZWedxQlC99VwPkbK7Vk+rn86B5Ty1sHQxhBQuujtvTDsxfqGEDDE9Xfig yU6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=UBPBK/8WVUG281weFxX1rWV/1Fu5J7obKJ2aND06KEs=; b=uKrRzEwH0P27oOwk1cAi+NvawkF/JJo8cd0PTepAGIEva/Z6i/kT7hMva1CWbgvf4z IwM6kb0QTiRygj1JVA7VDdnRH6QRN9uYyJlyTaoC5y/WVhsqOLlyBtEc3KK6Lo3YZWUu praoLqVRMkV7uVyHEYz5R3icr7zuxxaMMqOz7jxmKHLZL+EVYbTaC7d3sCfo9W73SntJ TChAhOzjWiD4VM242gqJN5+ov7phwCMO2naDVx3JdV/SbBFI+n6wwxu64M6rS8YbmdVb pvBie9QfBz3Qxq1wDOjwt2x25eIe4U0cxhQBEU+JybyfLqUbSxGR8MljgDDwi/LOfD/J 85nw== X-Gm-Message-State: AO0yUKXAx5p7lBA7k4VOrPl0Oc86SNpNdG3vmPWlLu0KVYhdULDfLvNb WwZtlqyV6RgC9rMppOjeAnAdPg== X-Google-Smtp-Source: AK7set9Qfdgb5BZmU3uxbPpynohorwQC3BKjVfJVmwSR6bQjfCrD4M6fFLLyFpSoE2HBGh5uxGKLnw== X-Received: by 2002:a5d:5b19:0:b0:2bf:ee15:ba85 with SMTP id bx25-20020a5d5b19000000b002bfee15ba85mr6986745wrb.18.1675172348767; Tue, 31 Jan 2023 05:39:08 -0800 (PST) Received: from alex-rivos.ba.rivosinc.com (lfbn-lyo-1-450-160.w2-7.abo.wanadoo.fr. [2.7.42.160]) by smtp.gmail.com with ESMTPSA id e2-20020adfe382000000b002bfae43109fsm14687660wrm.93.2023.01.31.05.39.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 05:39:08 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v9 0/5] riscv: Allow user to set the satp mode Date: Tue, 31 Jan 2023 14:39:01 +0100 Message-Id: <20230131133906.1956228-1-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x429.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 13:39:14 -0000 This introduces new properties to allow the user to set the satp mode, see patch 3 for full syntax. In addition, it prevents cpus to boot in a satp mode they do not support (see patch 4). v9: - Move valid_vm[i] up, Andrew - Fixed expansion of the bitmap map, Bin - Rename set_satp_mode_default into set_satp_mode_default_map, Bin - Remove outer parenthesis and alignment, Bin - Fix qemu32 build failure, Bin - Fixed a few typos, Bin - Add RB from Andrew and Bin v8: - Remove useless !map check, Andrew - Add RB from Andrew v7: - Expand map to contain all valid modes, Andrew - Fix commit log for patch 3, Andrew - Remove is_32_bit argument from set_satp_mode_default, Andrew - Move and fixed comment, Andrew - Fix satp_mode_map_max in riscv_cpu_satp_mode_finalize which was set too early, Alex - Remove is_32_bit argument from set_satp_mode_max_supported, Andrew - Use satp_mode directly instead of a string in set_satp_mode_max_supported, Andrew - Swap the patch introducing supported bitmap and the patch that sets sv57 in the dt, Andrew - Add various RB from Andrew and Alistair, thanks v6: - Remove the valid_vm check in validate_vm and add it to the finalize function so that map already contains the constraint, Alex - Add forgotten mbare to satp_mode_from_str, Alex - Move satp mode properties handling to riscv_cpu_satp_mode_finalize, Andrew - Only add satp mode properties corresponding to the cpu, and then remove the check against valid_vm_1_10_32/64 in riscv_cpu_satp_mode_finalize, Andrew/Alistair/Alex - Move mmu-type setting to its own patch, Andrew - patch 5 is new and is a fix, Alex v5: - Simplify v4 implementation by leveraging valid_vm_1_10_32/64, as suggested by Andrew - Split the v4 patch into 2 patches as suggested by Andrew - Lot of other minor corrections, from Andrew - Set the satp mode N by disabling the satp mode N + 1 - Add a helper to set satp mode from a string, as suggested by Frank v4: - Use custom boolean properties instead of OnOffAuto properties, based on ARMVQMap, as suggested by Andrew v3: - Free sv_name as pointed by Bin - Replace satp-mode with boolean properties as suggested by Andrew - Removed RB from Atish as the patch considerably changed v2: - Use error_setg + return as suggested by Alistair - Add RB from Atish - Fixed checkpatch issues missed in v1 - Replaced Ludovic email address with the rivos one Alexandre Ghiti (5): riscv: Pass Object to register_cpu_props instead of DeviceState riscv: Change type of valid_vm_1_10_[32|64] to bool riscv: Allow user to set the satp mode riscv: Introduce satp mode hw capabilities riscv: Correctly set the device-tree entry 'mmu-type' hw/riscv/virt.c | 19 ++-- target/riscv/cpu.c | 251 +++++++++++++++++++++++++++++++++++++++++++-- target/riscv/cpu.h | 23 +++++ target/riscv/csr.c | 29 +++--- 4 files changed, 291 insertions(+), 31 deletions(-) -- 2.37.2 From MAILER-DAEMON Tue Jan 31 08:40:18 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMqry-0003MZ-KK for mharc-qemu-riscv@gnu.org; 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[2.7.42.160]) by smtp.gmail.com with ESMTPSA id m3-20020a056000180300b002755e301eeasm14834867wrh.100.2023.01.31.05.40.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 05:40:09 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Bin Meng Subject: [PATCH v9 1/5] riscv: Pass Object to register_cpu_props instead of DeviceState Date: Tue, 31 Jan 2023 14:39:02 +0100 Message-Id: <20230131133906.1956228-2-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230131133906.1956228-1-alexghiti@rivosinc.com> References: <20230131133906.1956228-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x432.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 13:40:14 -0000 One can extract the DeviceState pointer from the Object pointer, so pass the Object for future commits to access other fields of Object. No functional changes intended. Signed-off-by: Alexandre Ghiti Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Reviewed-by: Andrew Jones Reviewed-by: Bin Meng --- target/riscv/cpu.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cc75ca7667..7181b34f86 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -200,7 +200,7 @@ static const char * const riscv_intr_names[] = { "reserved" }; -static void register_cpu_props(DeviceState *dev); +static void register_cpu_props(Object *obj); const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { @@ -238,7 +238,7 @@ static void riscv_any_cpu_init(Object *obj) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif set_priv_version(env, PRIV_VERSION_1_12_0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); } #if defined(TARGET_RISCV64) @@ -247,7 +247,7 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -280,7 +280,7 @@ static void rv128_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -290,7 +290,7 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); } @@ -343,7 +343,7 @@ static void riscv_host_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, 0); #endif - register_cpu_props(DEVICE(obj)); + register_cpu_props(obj); } #endif @@ -1083,9 +1083,10 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_END_OF_LIST(), }; -static void register_cpu_props(DeviceState *dev) +static void register_cpu_props(Object *obj) { Property *prop; + DeviceState *dev = DEVICE(obj); for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); -- 2.37.2 From MAILER-DAEMON Tue Jan 31 08:41:22 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMqsy-0003To-V4 for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 08:41:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMqst-0003TQ-Cz for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 08:41:16 -0500 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMqsq-000690-Dd for qemu-riscv@nongnu.org; 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[2.7.42.160]) by smtp.gmail.com with ESMTPSA id q17-20020a05600c46d100b003dc530186e1sm9930680wmo.45.2023.01.31.05.41.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 05:41:10 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Bin Meng Subject: [PATCH v9 2/5] riscv: Change type of valid_vm_1_10_[32|64] to bool Date: Tue, 31 Jan 2023 14:39:03 +0100 Message-Id: <20230131133906.1956228-3-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230131133906.1956228-1-alexghiti@rivosinc.com> References: <20230131133906.1956228-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x32e.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 13:41:18 -0000 This array is actually used as a boolean so swap its current char type to a boolean and at the same time, change the type of validate_vm to bool since it returns valid_vm_1_10_[32|64]. Suggested-by: Andrew Jones Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/csr.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0db2c233e5..6b157806a5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1117,16 +1117,16 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; static const target_ulong vsip_writable_mask = MIP_VSSIP; -static const char valid_vm_1_10_32[16] = { - [VM_1_10_MBARE] = 1, - [VM_1_10_SV32] = 1 +static const bool valid_vm_1_10_32[16] = { + [VM_1_10_MBARE] = true, + [VM_1_10_SV32] = true }; -static const char valid_vm_1_10_64[16] = { - [VM_1_10_MBARE] = 1, - [VM_1_10_SV39] = 1, - [VM_1_10_SV48] = 1, - [VM_1_10_SV57] = 1 +static const bool valid_vm_1_10_64[16] = { + [VM_1_10_MBARE] = true, + [VM_1_10_SV39] = true, + [VM_1_10_SV48] = true, + [VM_1_10_SV57] = true }; /* Machine Information Registers */ @@ -1209,7 +1209,7 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } -static int validate_vm(CPURISCVState *env, target_ulong vm) +static bool validate_vm(CPURISCVState *env, target_ulong vm) { if (riscv_cpu_mxl(env) == MXL_RV32) { return valid_vm_1_10_32[vm & 0xf]; @@ -2648,7 +2648,8 @@ static RISCVException read_satp(CPURISCVState *env, int csrno, static RISCVException write_satp(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong vm, mask; + target_ulong mask; + bool vm; if (!riscv_feature(env, RISCV_FEATURE_MMU)) { return RISCV_EXCP_NONE; -- 2.37.2 From MAILER-DAEMON Tue Jan 31 08:42:17 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMqtt-0003Zd-1I for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 08:42:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMqtr-0003ZU-JJ for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 08:42:15 -0500 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMqtp-0006Hm-AR for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 08:42:15 -0500 Received: by mail-wm1-x332.google.com with SMTP id m16-20020a05600c3b1000b003dc4050c94aso7801268wms.4 for ; Tue, 31 Jan 2023 05:42:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/xWI81SB82ol0jqat49BKKkw/QWECDCIZK34P0AOPDY=; b=2qkqGvDbenczEGG0DoMmxmGpa/G1hjy6XPsgiAEN9KLXnMFdw0lIxqrxMJL7HXxneD 9AKIzfa75Xhi8jTvR6oJYle03PNbMrwAIcefFZeXl0ZfgOhEwxDp+WSPquOVMOIOm7/9 wH5+TL87aPL5VrTtnsC0pZbqFpGY4vufA4dVYocl/ZGIV3DCes0uILGzJgW3o6HrQhd7 f/nd7SWhXWCurc8KN06W2J03aySLwZcwIY8v96inlya+7Km+e6DfKT9/m+yhGjI8fntN DUVaI4C3VQk6KwBHJm4L69+yIjWTMivdwuLUAqRKei9nFhKoTBK4LSqx5hAdfKhJ9XYx UXMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/xWI81SB82ol0jqat49BKKkw/QWECDCIZK34P0AOPDY=; b=U2DW1NjhDEIRw1mK1/J1rvscenFsQ5lorhcCFcLJLX092t/q+pwd22tXaDMEbgdZSJ fhDKJjtPGJoCVIU1oitIkhRQjHBv10fS3I5rLg0NVQIrMQyIr/8+DLVTg+WjlGt3Ef3f eBZ/h59Fy6QiJFpnkZFC50zcWAv43ugJxZ4LxI/ehoH8SaSjk3idvflcAa5jKl1YIJbI E3Hzi9F/GMRue0x+FSzPJMMzohHfxbWTzMtlrXiDlGLJeO/zHbT2Iv1zs/1lEySZeifP p/H3mRtVpA+BHD93U/9G2KYHcDbHVezonmBs5yexVpqSAuELypE1mckuRsI5jfsXvuEK zx7w== X-Gm-Message-State: AO0yUKV6kbSXpJkRrTQUoASl3wmC+gSw5dTHnqGQVkUHo5TiDuVM0X23 VLyGXyAFs03ABsHiEvqYwQnZbA== X-Google-Smtp-Source: AK7set9R5GvHOxAGra/GqnbrijAvtZPDrUeiu02fnemnV9zxkrkpbGH5ZxA0RkG7VkVYPXDcDIocxg== X-Received: by 2002:a05:600c:548c:b0:3dc:5390:6499 with SMTP id iv12-20020a05600c548c00b003dc53906499mr3662861wmb.1.1675172531676; Tue, 31 Jan 2023 05:42:11 -0800 (PST) Received: from alex-rivos.ba.rivosinc.com (lfbn-lyo-1-450-160.w2-7.abo.wanadoo.fr. [2.7.42.160]) by smtp.gmail.com with ESMTPSA id j15-20020a5d452f000000b002be505ab59asm14740250wra.97.2023.01.31.05.42.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 05:42:11 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Ludovic Henry Subject: [PATCH v9 3/5] riscv: Allow user to set the satp mode Date: Tue, 31 Jan 2023 14:39:04 +0100 Message-Id: <20230131133906.1956228-4-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230131133906.1956228-1-alexghiti@rivosinc.com> References: <20230131133906.1956228-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x332.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 13:42:15 -0000 RISC-V specifies multiple sizes for addressable memory and Linux probes for the machine's support at startup via the satp CSR register (done in csr.c:validate_vm). As per the specification, sv64 must support sv57, which in turn must support sv48...etc. So we can restrict machine support by simply setting the "highest" supported mode and the bare mode is always supported. You can set the satp mode using the new properties "sv32", "sv39", "sv48", "sv57" and "sv64" as follows: -cpu rv64,sv57=on # Linux will boot using sv57 scheme -cpu rv64,sv39=on # Linux will boot using sv39 scheme -cpu rv64,sv57=off # Linux will boot using sv48 scheme -cpu rv64 # Linux will boot using sv57 scheme by default We take the highest level set by the user: -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme We make sure that invalid configurations are rejected: -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are # enabled We accept "redundant" configurations: -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme And contradictory configurations: -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme Co-Developed-by: Ludovic Henry Signed-off-by: Ludovic Henry Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 207 +++++++++++++++++++++++++++++++++++++++++++++ target/riscv/cpu.h | 19 +++++ target/riscv/csr.c | 12 ++- 3 files changed, 231 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7181b34f86..3a7a1746aa 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -27,6 +27,7 @@ #include "time_helper.h" #include "exec/exec-all.h" #include "qapi/error.h" +#include "qapi/visitor.h" #include "qemu/error-report.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" @@ -229,6 +230,81 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) env->vext_ver = vext_ver; } +static uint8_t satp_mode_from_str(const char *satp_mode_str) +{ + if (!strncmp(satp_mode_str, "mbare", 5)) { + return VM_1_10_MBARE; + } + + if (!strncmp(satp_mode_str, "sv32", 4)) { + return VM_1_10_SV32; + } + + if (!strncmp(satp_mode_str, "sv39", 4)) { + return VM_1_10_SV39; + } + + if (!strncmp(satp_mode_str, "sv48", 4)) { + return VM_1_10_SV48; + } + + if (!strncmp(satp_mode_str, "sv57", 4)) { + return VM_1_10_SV57; + } + + if (!strncmp(satp_mode_str, "sv64", 4)) { + return VM_1_10_SV64; + } + + g_assert_not_reached(); +} + +uint8_t satp_mode_max_from_map(uint32_t map) +{ + /* map here has at least one bit set, so no problem with clz */ + return 31 - __builtin_clz(map); +} + +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) +{ + if (is_32_bit) { + switch (satp_mode) { + case VM_1_10_SV32: + return "sv32"; + case VM_1_10_MBARE: + return "none"; + } + } else { + switch (satp_mode) { + case VM_1_10_SV64: + return "sv64"; + case VM_1_10_SV57: + return "sv57"; + case VM_1_10_SV48: + return "sv48"; + case VM_1_10_SV39: + return "sv39"; + case VM_1_10_MBARE: + return "none"; + } + } + + g_assert_not_reached(); +} + +/* Sets the satp mode to the max supported */ +static void set_satp_mode_default_map(RISCVCPU *cpu) +{ + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; + + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { + cpu->cfg.satp_mode.map |= + (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); + } else { + cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); + } +} + static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; @@ -619,6 +695,83 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) } } +static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) +{ + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; + uint8_t satp_mode_max; + + if (cpu->cfg.satp_mode.map == 0) { + if (cpu->cfg.satp_mode.init == 0) { + /* If unset by the user, we fallback to the default satp mode. */ + set_satp_mode_default_map(cpu); + } else { + /* + * Find the lowest level that was disabled and then enable the + * first valid level below which can be found in + * valid_vm_1_10_32/64. + */ + for (int i = 1; i < 16; ++i) { + if ((cpu->cfg.satp_mode.init & (1 << i)) && valid_vm[i]) { + for (int j = i - 1; j >= 0; --j) { + if (valid_vm[j]) { + cpu->cfg.satp_mode.map |= (1 << j); + break; + } + } + break; + } + } + } + } + + /* Make sure the configuration asked is supported by qemu */ + for (int i = 0; i < 16; ++i) { + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { + error_setg(errp, "satp_mode %s is not valid", + satp_mode_str(i, rv32)); + return; + } + } + + /* + * Make sure the user did not ask for an invalid configuration as per + * the specification. + */ + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); + + if (!rv32) { + for (int i = satp_mode_max - 1; i >= 0; --i) { + if (!(cpu->cfg.satp_mode.map & (1 << i)) && + (cpu->cfg.satp_mode.init & (1 << i)) && + valid_vm[i]) { + error_setg(errp, "cannot disable %s satp mode if %s " + "is enabled", satp_mode_str(i, false), + satp_mode_str(satp_mode_max, false)); + return; + } + } + } + + /* Finally expand the map so that all valid modes are set */ + for (int i = satp_mode_max - 1; i >= 0; --i) { + if (valid_vm[i]) { + cpu->cfg.satp_mode.map |= (1 << i); + } + } +} + +static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) +{ + Error *local_err = NULL; + + riscv_cpu_satp_mode_finalize(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } +} + static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -919,6 +1072,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } #endif + riscv_cpu_finalize_features(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + riscv_cpu_register_gdb_regs_for_features(cs); qemu_init_vcpu(cs); @@ -927,6 +1086,52 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) mcc->parent_realize(dev, errp); } +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVSATPMap *satp_map = opaque; + uint8_t satp = satp_mode_from_str(name); + bool value; + + value = satp_map->map & (1 << satp); + + visit_type_bool(v, name, &value, errp); +} + +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVSATPMap *satp_map = opaque; + uint8_t satp = satp_mode_from_str(name); + bool value; + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + satp_map->map = deposit32(satp_map->map, satp, 1, value); + satp_map->init |= 1 << satp; +} + +static void riscv_add_satp_mode_properties(Object *obj) +{ + RISCVCPU *cpu = RISCV_CPU(obj); + + if (cpu->env.misa_mxl == MXL_RV32) { + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + } else { + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); + } +} + #ifndef CONFIG_USER_ONLY static void riscv_cpu_set_irq(void *opaque, int irq, int level) { @@ -1091,6 +1296,8 @@ static void register_cpu_props(Object *obj) for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } + + riscv_add_satp_mode_properties(obj); } static Property riscv_cpu_properties[] = { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f5609b62a2..e37177db5c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -27,6 +27,7 @@ #include "qom/object.h" #include "qemu/int128.h" #include "cpu_bits.h" +#include "qapi/qapi-types-common.h" #define TCG_GUEST_DEFAULT_MO 0 @@ -413,6 +414,17 @@ struct RISCVCPUClass { ResettablePhases parent_phases; }; +/* + * map is a 16-bit bitmap: the most significant set bit in map is the maximum + * satp mode that is supported. + * + * init is a 16-bit bitmap used to make sure the user selected a correct + * configuration as per the specification. + */ +typedef struct { + uint16_t map, init; +} RISCVSATPMap; + struct RISCVCPUConfig { bool ext_i; bool ext_e; @@ -488,6 +500,8 @@ struct RISCVCPUConfig { bool debug; bool short_isa_string; + + RISCVSATPMap satp_mode; }; typedef struct RISCVCPUConfig RISCVCPUConfig; @@ -794,9 +808,14 @@ enum riscv_pmu_event_idx { /* CSR function table */ extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; +extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; + void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); +uint8_t satp_mode_max_from_map(uint32_t map); +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); + #endif /* RISCV_CPU_H */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6b157806a5..f9eff3f1e3 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1117,12 +1117,12 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; static const target_ulong vsip_writable_mask = MIP_VSSIP; -static const bool valid_vm_1_10_32[16] = { +const bool valid_vm_1_10_32[16] = { [VM_1_10_MBARE] = true, [VM_1_10_SV32] = true }; -static const bool valid_vm_1_10_64[16] = { +const bool valid_vm_1_10_64[16] = { [VM_1_10_MBARE] = true, [VM_1_10_SV39] = true, [VM_1_10_SV48] = true, @@ -1211,11 +1211,9 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, static bool validate_vm(CPURISCVState *env, target_ulong vm) { - if (riscv_cpu_mxl(env) == MXL_RV32) { - return valid_vm_1_10_32[vm & 0xf]; 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[2.7.42.160]) by smtp.gmail.com with ESMTPSA id z14-20020a5d4d0e000000b002bde537721dsm14674268wrt.20.2023.01.31.05.43.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 05:43:12 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti Subject: [PATCH v9 4/5] riscv: Introduce satp mode hw capabilities Date: Tue, 31 Jan 2023 14:39:05 +0100 Message-Id: <20230131133906.1956228-5-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230131133906.1956228-1-alexghiti@rivosinc.com> References: <20230131133906.1956228-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x435.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 13:43:16 -0000 Currently, the max satp mode is set with the only constraint that it must be implemented in QEMU, i.e. set in valid_vm_1_10_[32|64]. But we actually need to add another level of constraint: what the hw is actually capable of, because currently, a linux booting on a sifive-u54 boots in sv57 mode which is incompatible with the cpu's sv39 max capability. So add a new bitmap to RISCVSATPMap which contains this capability and initialize it in every XXX_cpu_init. Finally: - valid_vm_1_10_[32|64] constrains which satp mode the CPU can use - the CPU hw capabilities constrains what the user may select - the user's selection then constrains what's available to the guest OS. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones --- target/riscv/cpu.c | 79 +++++++++++++++++++++++++++++++--------------- target/riscv/cpu.h | 8 +++-- 2 files changed, 60 insertions(+), 27 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3a7a1746aa..6dd76355ec 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -292,26 +292,36 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) g_assert_not_reached(); } -/* Sets the satp mode to the max supported */ -static void set_satp_mode_default_map(RISCVCPU *cpu) +static void set_satp_mode_max_supported(RISCVCPU *cpu, + uint8_t satp_mode) { bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { - cpu->cfg.satp_mode.map |= - (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); - } else { - cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); + for (int i = 0; i <= satp_mode; ++i) { + if (valid_vm[i]) { + cpu->cfg.satp_mode.supported |= (1 << i); + } } } +/* Set the satp mode to the max supported */ +static void set_satp_mode_default_map(RISCVCPU *cpu) +{ + cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; +} + static void riscv_any_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + #if defined(TARGET_RISCV32) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_satp_mode_max_supported(cpu, VM_1_10_SV32); #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_satp_mode_max_supported(cpu, VM_1_10_SV57); #endif set_priv_version(env, PRIV_VERSION_1_12_0); register_cpu_props(obj); @@ -321,18 +331,24 @@ static void riscv_any_cpu_init(Object *obj) static void rv64_base_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); + set_satp_mode_max_supported(cpu, VM_1_10_SV57); } static void rv64_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); + set_satp_mode_max_supported(cpu, VM_1_10_SV39); } static void rv64_sifive_e_cpu_init(Object *obj) @@ -343,6 +359,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); } static void rv128_base_cpu_init(Object *obj) @@ -354,28 +371,36 @@ static void rv128_base_cpu_init(Object *obj) exit(EXIT_FAILURE); } CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); + set_satp_mode_max_supported(cpu, VM_1_10_SV57); } #else static void rv32_base_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ set_priv_version(env, PRIV_VERSION_1_12_0); + set_satp_mode_max_supported(cpu, VM_1_10_SV32); } static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); + set_satp_mode_max_supported(cpu, VM_1_10_SV32); } static void rv32_sifive_e_cpu_init(Object *obj) @@ -386,6 +411,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); } static void rv32_ibex_cpu_init(Object *obj) @@ -396,6 +422,7 @@ static void rv32_ibex_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_11_0); cpu->cfg.mmu = false; + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); cpu->cfg.epmp = true; } @@ -407,6 +434,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); cpu->cfg.mmu = false; + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); } #endif @@ -698,8 +726,9 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) { bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; - const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; - uint8_t satp_mode_max; + uint8_t satp_mode_map_max; + uint8_t satp_mode_supported_max = + satp_mode_max_from_map(cpu->cfg.satp_mode.supported); if (cpu->cfg.satp_mode.map == 0) { if (cpu->cfg.satp_mode.init == 0) { @@ -712,9 +741,10 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) * valid_vm_1_10_32/64. */ for (int i = 1; i < 16; ++i) { - if ((cpu->cfg.satp_mode.init & (1 << i)) && valid_vm[i]) { + if ((cpu->cfg.satp_mode.init & (1 << i)) && + (cpu->cfg.satp_mode.supported & (1 << i))) { for (int j = i - 1; j >= 0; --j) { - if (valid_vm[j]) { + if (cpu->cfg.satp_mode.supported & (1 << j)) { cpu->cfg.satp_mode.map |= (1 << j); break; } @@ -725,37 +755,36 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) } } - /* Make sure the configuration asked is supported by qemu */ - for (int i = 0; i < 16; ++i) { - if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { - error_setg(errp, "satp_mode %s is not valid", - satp_mode_str(i, rv32)); - return; - } + satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); + + /* Make sure the user asked for a supported configuration (HW and qemu) */ + if (satp_mode_map_max > satp_mode_supported_max) { + error_setg(errp, "satp_mode %s is higher than hw max capability %s", + satp_mode_str(satp_mode_map_max, rv32), + satp_mode_str(satp_mode_supported_max, rv32)); + return; } /* * Make sure the user did not ask for an invalid configuration as per * the specification. */ - satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); - if (!rv32) { - for (int i = satp_mode_max - 1; i >= 0; --i) { + for (int i = satp_mode_map_max - 1; i >= 0; --i) { if (!(cpu->cfg.satp_mode.map & (1 << i)) && (cpu->cfg.satp_mode.init & (1 << i)) && - valid_vm[i]) { + (cpu->cfg.satp_mode.supported & (1 << i))) { error_setg(errp, "cannot disable %s satp mode if %s " "is enabled", satp_mode_str(i, false), - satp_mode_str(satp_mode_max, false)); + satp_mode_str(satp_mode_map_max, false)); return; } } } /* Finally expand the map so that all valid modes are set */ - for (int i = satp_mode_max - 1; i >= 0; --i) { - if (valid_vm[i]) { + for (int i = satp_mode_map_max - 1; i >= 0; --i) { + if (cpu->cfg.satp_mode.supported & (1 << i)) { cpu->cfg.satp_mode.map |= (1 << i); } } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e37177db5c..b591122099 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -416,13 +416,17 @@ struct RISCVCPUClass { /* * map is a 16-bit bitmap: the most significant set bit in map is the maximum - * satp mode that is supported. + * satp mode that is supported. It may be chosen by the user and must respect + * what qemu implements (valid_1_10_32/64) and what the hw is capable of + * (supported bitmap below). * * init is a 16-bit bitmap used to make sure the user selected a correct * configuration as per the specification. + * + * supported is a 16-bit bitmap used to reflect the hw capabilities. */ typedef struct { - uint16_t map, init; + uint16_t map, init, supported; } RISCVSATPMap; struct RISCVCPUConfig { -- 2.37.2 From MAILER-DAEMON Tue Jan 31 08:44:19 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMqvr-00047X-3S for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 08:44:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMqvp-00047D-TR for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 08:44:17 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMqvn-0006VA-72 for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 08:44:17 -0500 Received: by mail-wm1-x32a.google.com with SMTP id j32-20020a05600c1c2000b003dc4fd6e61dso5637974wms.5 for ; Tue, 31 Jan 2023 05:44:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KnBnWPYZTJbtqglsFebcan2CK1/moGM7upa/HPAcASY=; b=s87HJBFMwu70JeiT/b45Ow0Qn3rHu7bS7vFRw+vffUis2sgQLkD+oCVOfdv8D+geiP VbzIKHNznO1fMXLxedThqw33tg/MAU0tdQj9emshENFZ17zRwd9oAKQ8yxnc/kArFA8Y 1x3PdoBOWCMTalFQSYgCFqVf8FZDJfKGdaxfkoVMjbItJYHtU5NxQnipTm+M+YTkKpSB wDHOeGPbzSsg4Kj7J15OIr/zbHPhIjWOuoF4xam+0+ma7hANb6wD0kvU6Z5jXUjWYvK1 k/U5bHe/Nf6l5kMv1ix0B7tteGv5jZKhWfQtf+BCQbysnFLKz0on7jVVoNU8AjrpHy0R C55Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KnBnWPYZTJbtqglsFebcan2CK1/moGM7upa/HPAcASY=; b=X4kksN09Ccz4YlQoV7iuOcC4qKP0FmBPHuftBN/px5NsDVOQ26rPcMf7MOr7RC/38X dpI3U/iIEBDAbSHvaG7BS1vNggo95ZsFESdpQGnNRW3OecAYNcq1xWPXmiXrDtDeEEQ6 B5OrvrBcdx1zt1m6Ka562mMsA0Ct39VzFJovLXh6ueFOoqiV0HArbq1iSfr+7+vb+EP0 w5pY6dCpuMRf/yWrulfn8wT+ZVHwHHLiXSTI/fAO99iGcn1UbpYIVMFSH/XnuDD4bGWy WE/oYQDO3kQRG81B4vlZZ9wzHtxdL7OORcTly/3ardMdGKoyaNUE4RNjN1Fm9Nz/IjX/ F75Q== X-Gm-Message-State: AFqh2kotojeOS7DqKyt4Vm2iRjtltrlSmDDXjZe1eeFX2Kz2gy09MtSC kcQKr1rnJ5SvYSZfgul0KD0Ywg== X-Google-Smtp-Source: AMrXdXvSi4cR1fwWVRlWrtR2Q9AZ1HH7nA3Hr2AuyvmfwS2+JHt/p8biQlRTFnpAOHejUIjQKGDyxg== X-Received: by 2002:a05:600c:4f96:b0:3db:2dbb:d70e with SMTP id n22-20020a05600c4f9600b003db2dbbd70emr42419610wmq.6.1675172653566; Tue, 31 Jan 2023 05:44:13 -0800 (PST) Received: from alex-rivos.ba.rivosinc.com (lfbn-lyo-1-450-160.w2-7.abo.wanadoo.fr. [2.7.42.160]) by smtp.gmail.com with ESMTPSA id i19-20020a05600c2d9300b003dc4fd6e624sm9127246wmg.19.2023.01.31.05.44.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 05:44:13 -0800 (PST) From: Alexandre Ghiti To: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Alexandre Ghiti , Bin Meng Subject: [PATCH v9 5/5] riscv: Correctly set the device-tree entry 'mmu-type' Date: Tue, 31 Jan 2023 14:39:06 +0100 Message-Id: <20230131133906.1956228-6-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230131133906.1956228-1-alexghiti@rivosinc.com> References: <20230131133906.1956228-1-alexghiti@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=alexghiti@rivosinc.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 13:44:18 -0000 The 'mmu-type' should reflect what the hardware is capable of so use the new satp_mode field in RISCVCPUConfig to do that. Signed-off-by: Alexandre Ghiti Reviewed-by: Andrew Jones Reviewed-by: Alistair Francis Reviewed-by: Bin Meng --- hw/riscv/virt.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 94ff2a1584..48d034a5f7 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -228,7 +228,8 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, int cpu; uint32_t cpu_phandle; MachineState *mc = MACHINE(s); - char *name, *cpu_name, *core_name, *intc_name; + uint8_t satp_mode_max; + char *name, *cpu_name, *core_name, *intc_name, *sv_name; for (cpu = s->soc[socket].num_harts - 1; cpu >= 0; cpu--) { cpu_phandle = (*phandle)++; @@ -236,14 +237,14 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, int socket, cpu_name = g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(mc->fdt, cpu_name); - if (riscv_feature(&s->soc[socket].harts[cpu].env, - RISCV_FEATURE_MMU)) { - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", - (is_32_bit) ? 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=alexghiti@rivosinc.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 13:53:13 -0000 Hi Bin, On Mon, Jan 30, 2023 at 5:22 AM Bin Meng wrote: > > On Thu, Jan 26, 2023 at 12:23 AM Alexandre Ghiti wrote: > > > > RISC-V specifies multiple sizes for addressable memory and Linux probes for > > the machine's support at startup via the satp CSR register (done in > > csr.c:validate_vm). > > > > As per the specification, sv64 must support sv57, which in turn must > > support sv48...etc. So we can restrict machine support by simply setting the > > "highest" supported mode and the bare mode is always supported. > > > > You can set the satp mode using the new properties "sv32", "sv39", "sv48", > > "sv57" and "sv64" as follows: > > -cpu rv64,sv57=on # Linux will boot using sv57 scheme > > -cpu rv64,sv39=on # Linux will boot using sv39 scheme > > -cpu rv64,sv57=off # Linux will boot using sv48 scheme > > -cpu rv64 # Linux will boot using sv57 scheme by default > > > > We take the highest level set by the user: > > -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme > > > > We make sure that invalid configurations are rejected: > > -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are > > # enabled > > > > We accept "redundant" configurations: > > -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme > > > > And contradictory configurations: > > -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme > > > > Co-Developed-by: Ludovic Henry > > Signed-off-by: Ludovic Henry > > Signed-off-by: Alexandre Ghiti > > --- > > target/riscv/cpu.c | 206 +++++++++++++++++++++++++++++++++++++++++++++ > > target/riscv/cpu.h | 19 +++++ > > target/riscv/csr.c | 12 ++- > > 3 files changed, 230 insertions(+), 7 deletions(-) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 7181b34f86..54494a72be 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -27,6 +27,7 @@ > > #include "time_helper.h" > > #include "exec/exec-all.h" > > #include "qapi/error.h" > > +#include "qapi/visitor.h" > > #include "qemu/error-report.h" > > #include "hw/qdev-properties.h" > > #include "migration/vmstate.h" > > @@ -229,6 +230,81 @@ static void set_vext_version(CPURISCVState *env, int vext_ver) > > env->vext_ver = vext_ver; > > } > > > > +static uint8_t satp_mode_from_str(const char *satp_mode_str) > > +{ > > + if (!strncmp(satp_mode_str, "mbare", 5)) { > > + return VM_1_10_MBARE; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv32", 4)) { > > + return VM_1_10_SV32; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv39", 4)) { > > + return VM_1_10_SV39; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv48", 4)) { > > + return VM_1_10_SV48; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv57", 4)) { > > + return VM_1_10_SV57; > > + } > > + > > + if (!strncmp(satp_mode_str, "sv64", 4)) { > > + return VM_1_10_SV64; > > + } > > + > > + g_assert_not_reached(); > > +} > > + > > +uint8_t satp_mode_max_from_map(uint32_t map) > > +{ > > + /* map here has at least one bit set, so no problem with clz */ > > + return 31 - __builtin_clz(map); > > +} > > + > > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > > +{ > > + if (is_32_bit) { > > + switch (satp_mode) { > > + case VM_1_10_SV32: > > + return "sv32"; > > + case VM_1_10_MBARE: > > + return "none"; > > + } > > + } else { > > + switch (satp_mode) { > > + case VM_1_10_SV64: > > + return "sv64"; > > + case VM_1_10_SV57: > > + return "sv57"; > > + case VM_1_10_SV48: > > + return "sv48"; > > + case VM_1_10_SV39: > > + return "sv39"; > > + case VM_1_10_MBARE: > > + return "none"; > > + } > > + } > > + > > + g_assert_not_reached(); > > +} > > + > > +/* Sets the satp mode to the max supported */ > > +static void set_satp_mode_default(RISCVCPU *cpu) > > This function is better named as set_satp_mode_default_map > Indeed, fixed in v9. > > +{ > > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > > + > > + if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > > + cpu->cfg.satp_mode.map |= > > + (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); > > + } else { > > + cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > > + } > > I believe the "mbare" bit should always be set, so this can be: > > cpu->cfg.satp_mode.map = 1 << satp_mode_from_str("mbare"); > if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > cpu->cfg.satp_mode.map |= > (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); Actually, at the end of riscv_cpu_satp_mode_finalize, the map is "expanded" so that all supported modes are set in the bitmap. > > > +} > > + > > static void riscv_any_cpu_init(Object *obj) > > { > > CPURISCVState *env = &RISCV_CPU(obj)->env; > > @@ -619,6 +695,82 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > > } > > } > > > > +static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > > +{ > > + bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > > + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > > + uint8_t satp_mode_max; > > + > > + if (cpu->cfg.satp_mode.map == 0) { > > + if (cpu->cfg.satp_mode.init == 0) { > > + /* If unset by the user, we fallback to the default satp mode. */ > > + set_satp_mode_default(cpu); > > + } else { > > + /* > > + * Find the lowest level that was disabled and then enable the > > + * first valid level below which can be found in > > + * valid_vm_1_10_32/64. > > + */ > > + for (int i = 1; i < 16; ++i) { > > + if ((cpu->cfg.satp_mode.init & (1 << i)) && > > + valid_vm[i]) { > > + for (int j = i - 1; j >= 0; --j) { > > + if (valid_vm[j]) { > > + cpu->cfg.satp_mode.map |= (1 << j); > > + break; > > + } > > + } > > + break; > > + } > > + } > > + } > > + } > > + > > + /* Make sure the configuration asked is supported by qemu */ > > + for (int i = 0; i < 16; ++i) { > > + if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > > + error_setg(errp, "satp_mode %s is not valid", > > + satp_mode_str(i, rv32)); > > + return; > > + } > > + } > > + > > + /* > > + * Make sure the user did not ask for an invalid configuration as per > > + * the specification. > > + */ > > + satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > > + > > + if (!rv32) { > > + for (int i = satp_mode_max - 1; i >= 0; --i) { > > + if (!(cpu->cfg.satp_mode.map & (1 << i)) && > > + (cpu->cfg.satp_mode.init & (1 << i)) && > > + valid_vm[i]) { > > + error_setg(errp, "cannot disable %s satp mode if %s " > > + "is enabled", satp_mode_str(i, false), > > + satp_mode_str(satp_mode_max, false)); > > + return; > > + } > > + } > > + } > > + > > + /* Finally expand the map so that all valid modes are set */ > > + for (int i = satp_mode_max - 1; i >= 0; --i) { > > + cpu->cfg.satp_mode.map |= (1 << i); > > This blindly expands the map regardless whether it's a valid mode. Oh, indeed, good catch, fixed in v9. > > > + } > > +} > > + > > +static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) > > +{ > > + Error *local_err = NULL; > > + > > + riscv_cpu_satp_mode_finalize(cpu, &local_err); > > + if (local_err != NULL) { > > + error_propagate(errp, local_err); > > + return; > > + } > > +} > > + > > static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > { > > CPUState *cs = CPU(dev); > > @@ -919,6 +1071,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > } > > #endif > > > > + riscv_cpu_finalize_features(cpu, &local_err); > > + if (local_err != NULL) { > > + error_propagate(errp, local_err); > > + return; > > + } > > + > > riscv_cpu_register_gdb_regs_for_features(cs); > > > > qemu_init_vcpu(cs); > > @@ -927,6 +1085,52 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) > > mcc->parent_realize(dev, errp); > > } > > > > +static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, > > + void *opaque, Error **errp) > > nits: should align to ( Ok > > > +{ > > + RISCVSATPMap *satp_map = opaque; > > + uint8_t satp = satp_mode_from_str(name); > > + bool value; > > + > > + value = (satp_map->map & (1 << satp)); > > nits: remove the outer () Ok > > > + > > + visit_type_bool(v, name, &value, errp); > > +} > > + > > +static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, > > + void *opaque, Error **errp) > > ditto Ok > > > +{ > > + RISCVSATPMap *satp_map = opaque; > > + uint8_t satp = satp_mode_from_str(name); > > + bool value; > > + > > + if (!visit_type_bool(v, name, &value, errp)) { > > + return; > > + } > > + > > + satp_map->map = deposit32(satp_map->map, satp, 1, value); > > + satp_map->init |= 1 << satp; > > +} > > + > > +static void riscv_add_satp_mode_properties(Object *obj) > > +{ > > + RISCVCPU *cpu = RISCV_CPU(obj); > > + > > + if (cpu->env.misa_mxl == MXL_RV32) { > > + object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + } else { > > + object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, > > + cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); > > + } > > +} > > + > > #ifndef CONFIG_USER_ONLY > > static void riscv_cpu_set_irq(void *opaque, int irq, int level) > > { > > @@ -1091,6 +1295,8 @@ static void register_cpu_props(Object *obj) > > for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > > qdev_property_add_static(dev, prop); > > } > > + > > + riscv_add_satp_mode_properties(obj); > > } > > > > static Property riscv_cpu_properties[] = { > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > > index f5609b62a2..e37177db5c 100644 > > --- a/target/riscv/cpu.h > > +++ b/target/riscv/cpu.h > > @@ -27,6 +27,7 @@ > > #include "qom/object.h" > > #include "qemu/int128.h" > > #include "cpu_bits.h" > > +#include "qapi/qapi-types-common.h" > > > > #define TCG_GUEST_DEFAULT_MO 0 > > > > @@ -413,6 +414,17 @@ struct RISCVCPUClass { > > ResettablePhases parent_phases; > > }; > > > > +/* > > + * map is a 16-bit bitmap: the most significant set bit in map is the maximum > > + * satp mode that is supported. > > + * > > + * init is a 16-bit bitmap used to make sure the user selected a correct > > + * configuration as per the specification. > > + */ > > +typedef struct { > > + uint16_t map, init; > > +} RISCVSATPMap; > > + > > struct RISCVCPUConfig { > > bool ext_i; > > bool ext_e; > > @@ -488,6 +500,8 @@ struct RISCVCPUConfig { > > bool debug; > > > > bool short_isa_string; > > + > > + RISCVSATPMap satp_mode; > > }; > > > > typedef struct RISCVCPUConfig RISCVCPUConfig; > > @@ -794,9 +808,14 @@ enum riscv_pmu_event_idx { > > /* CSR function table */ > > extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; > > > > +extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; > > + > > void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); > > void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); > > > > void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); > > > > +uint8_t satp_mode_max_from_map(uint32_t map); > > +const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); > > + > > #endif /* RISCV_CPU_H */ > > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > > index 6b157806a5..3c02055825 100644 > > --- a/target/riscv/csr.c > > +++ b/target/riscv/csr.c > > @@ -1117,12 +1117,12 @@ static const target_ulong hip_writable_mask = MIP_VSSIP; > > static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP; > > static const target_ulong vsip_writable_mask = MIP_VSSIP; > > > > -static const bool valid_vm_1_10_32[16] = { > > +const bool valid_vm_1_10_32[16] = { > > [VM_1_10_MBARE] = true, > > [VM_1_10_SV32] = true > > }; > > > > -static const bool valid_vm_1_10_64[16] = { > > +const bool valid_vm_1_10_64[16] = { > > [VM_1_10_MBARE] = true, > > [VM_1_10_SV39] = true, > > [VM_1_10_SV48] = true, > > @@ -1211,11 +1211,9 @@ static RISCVException read_mstatus(CPURISCVState *env, int csrno, > > > > static bool validate_vm(CPURISCVState *env, target_ulong vm) > > { > > - if (riscv_cpu_mxl(env) == MXL_RV32) { > > - return valid_vm_1_10_32[vm & 0xf]; > > - } else { > > - return valid_vm_1_10_64[vm & 0xf]; > > - } > > + RISCVCPU *cpu = RISCV_CPU(env_cpu(env)); > > + > > + return ((vm & 0xf) <= satp_mode_max_from_map(cpu->cfg.satp_mode.map)); > > nits: remove the outer () Ok > > > } > > > > static RISCVException write_mstatus(CPURISCVState *env, int csrno, > > -- > > Regards, > Bin Thanks! Alex From MAILER-DAEMON Tue Jan 31 12:10:17 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMu99-0000nq-SE for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 12:10:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMu95-0000mu-5i; Tue, 31 Jan 2023 12:10:12 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMu92-0006By-Oo; Tue, 31 Jan 2023 12:10:10 -0500 Received: by mail-ej1-x62f.google.com with SMTP id me3so43626842ejb.7; Tue, 31 Jan 2023 09:10:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=3QpPB5j2/Lw1un26Dww9vvsqU+Ums661g1jLauN9JaQ=; b=iPIh/TcPu+Z2eyAo/pn3MR9axm015bx5K4AoxGwMwPfK2WzgSNWc+0vqw0/TsUbM7f diqMx0jB1CudBGYr+2DsaHHdaWm50SxcykEm+UzhHsFMEhR5K3Kq1D62V1B7/WTENyYb oVKAfIEblt4LS2AM7A2mXpAM74WvmzqcGcGV5tL4w9AGItWNip13+VuVbSaBzDmMNFUq rZrXPoBZ4soqwOaLq2mZ9GkO40mW4dy9SBSCyMTMFuVbe9O63NST3rHYQn/shwZFwNGk 395ZBi9X9JweHopIG0n9JKOpsNxqxvjaDlu+ADNFKeKUG8cHp0F6nu59QGBw3mPROMhT ebug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=3QpPB5j2/Lw1un26Dww9vvsqU+Ums661g1jLauN9JaQ=; b=SsfxGd7g14JA+vAGWhqxX1nXqXLzlxEx1rxYBJ6bTCdixdY7peP81rYSbPhMKCbaaA ZhtQp9NSh5+lmRBqYyQAryO/KsUlFUsMQeDpfGhTei7xqecIHEfUjpWHSO43mMgfxEkx 074dhllfS8HFWBWWKjbs3XaPC5nZtYFlU6J2HP7EUZA6WYrO28NAEvzI2mOEUvY4NtSD TB6cIgx45m1Rl2LtcIXkLiQOOlvozMr9JfYMq/kIwIIgCWV8wV7UDx5PRJ94GeXNdXNz be8u3vwB1jfBFDhuHHZ0XR+UPKdFdLclIKITiHKT5K2K7PodPXca8anTPVEuhUrLJiN4 hzuQ== X-Gm-Message-State: AO0yUKWEIUpD1+EEbj0uu13vjsC7Ao3nfHAchAkYwCDOdQA6GAu+xZ5W ZIbzmJh0dP01020gPse5O5Ui40yYB1DVgmv7 X-Google-Smtp-Source: AK7set/hKr869VhUSa13uybFj0Jqv9orBJoTclA78GjpjuFHoG6CPQbVjU9TBYfkFyAuSM9OoOgbWw== X-Received: by 2002:a17:906:ad87:b0:885:5231:359c with SMTP id la7-20020a170906ad8700b008855231359cmr11735951ejb.5.1675185003641; Tue, 31 Jan 2023 09:10:03 -0800 (PST) Received: from localhost.localdomain ([80.211.22.60]) by smtp.googlemail.com with ESMTPSA id d13-20020a170906344d00b0088385cd6166sm5495806ejb.195.2023.01.31.09.10.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 09:10:02 -0800 (PST) From: Sergey Matyukevich To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Sergey Matyukevich Subject: [PATCH v2] target/riscv: set tval for triggered watchpoints Date: Tue, 31 Jan 2023 20:09:55 +0300 Message-Id: <20230131170955.752743-1-geomatsi@gmail.com> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=geomatsi@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 17:10:13 -0000 From: Sergey Matyukevich According to priviledged spec, if [sm]tval is written with a nonzero value when a breakpoint exception occurs, then [sm]tval will contain the faulting virtual address. Set tval to hit address when breakpoint exception is triggered by hardware watchpoint. Signed-off-by: Sergey Matyukevich --- v1 -> v2 - do not set tval blindly for every breakpoint exception, handle current specific case under consideration target/riscv/cpu_helper.c | 6 ++++++ target/riscv/debug.c | 1 - 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 9a28816521..f1a0c65ad3 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1641,6 +1641,12 @@ void riscv_cpu_do_interrupt(CPUState *cs) case RISCV_EXCP_VIRT_INSTRUCTION_FAULT: tval = env->bins; break; + case RISCV_EXCP_BREAKPOINT: + if (cs->watchpoint_hit) { + tval = cs->watchpoint_hit->hitaddr; + cs->watchpoint_hit = NULL; + } + break; default: break; } diff --git a/target/riscv/debug.c b/target/riscv/debug.c index bf4840a6a3..b091293069 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -761,7 +761,6 @@ void riscv_cpu_debug_excp_handler(CPUState *cs) if (cs->watchpoint_hit) { if (cs->watchpoint_hit->flags & BP_CPU) { - cs->watchpoint_hit = NULL; do_trigger_action(env, DBG_ACTION_BP); } } else { -- 2.39.0 From MAILER-DAEMON Tue Jan 31 13:02:33 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMuxj-0007PZ-Ve for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 13:02:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMuxM-0007Bm-9U for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 13:02:08 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMuxK-0000mC-Bu for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 13:02:08 -0500 Received: by mail-wr1-x431.google.com with SMTP id h12so15006389wrv.10 for ; Tue, 31 Jan 2023 10:02:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; 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Tue, 31 Jan 2023 10:02:04 -0800 (PST) MIME-Version: 1.0 References: <20230124195945.181842-1-christoph.muellner@vrull.eu> <20230124195945.181842-10-christoph.muellner@vrull.eu> <3d864ae7-5430-8db9-f91c-fd24f428b04d@linaro.org> In-Reply-To: <3d864ae7-5430-8db9-f91c-fd24f428b04d@linaro.org> From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Tue, 31 Jan 2023 19:01:51 +0100 Message-ID: Subject: Re: [PATCH v3 09/14] RISC-V: Adding T-Head MemIdx extension To: Richard Henderson Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Palmer Dabbelt , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 18:02:16 -0000 On Tue, Jan 24, 2023 at 10:21 PM Richard Henderson wrote: > > On 1/24/23 09:59, Christoph Muellner wrote: > > +/* XTheadMemIdx */ > > + > > +/* > > + * Load with memop from indexed address and add (imm5 << imm2) to rs1. > > + * If !preinc, then the load address is rs1. > > + * If preinc, then the load address is rs1 + (imm5) << imm2). > > + */ > > +static bool gen_load_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop, > > + bool preinc) > > +{ > > + TCGv rd = dest_gpr(ctx, a->rd); > > + TCGv addr = get_address(ctx, a->rs1, preinc ? a->imm5 << a->imm2 : 0); > > + > > + tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); > > + addr = get_address(ctx, a->rs1, !preinc ? a->imm5 << a->imm2 : 0); > > First, you're leaking the previous 'addr' temporary. Indeed! The real question is of course, why we call get_address() twice... Fixed in v4. > Second, get_address may make modifications to 'addr' which you don't want to write back. Fixed in v4. > Third, you are not checking for rd != rs1. Fixed in v4. > > I think what you want is > > int imm = a->imm5 << a->imm2; > TCGv addr = get_address(ctx, a->rs1, preinc ? imm : 0); > TCGv rd = dest_gpr(ctx, a->rd); > TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE); > > tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); > tcg_gen_addi_tl(rs1, rs1, imm); > gen_set_gpr(ctx, a->rd, rd); > gen_set_gpr(ctx, a->rs1, rs1); Yes (plus the check for rd != rs1). Fixed in v4. Thank you! > > > r~ From MAILER-DAEMON Tue Jan 31 13:02:33 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMuxl-0007RA-4q for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 13:02:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMuxM-0007Bk-92 for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 13:02:08 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMuxI-0000m0-UY for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 13:02:08 -0500 Received: by mail-wm1-x32a.google.com with SMTP id c4-20020a1c3504000000b003d9e2f72093so13086863wma.1 for ; Tue, 31 Jan 2023 10:02:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=ibROdXvGInj/QQaIg5EL6BOybdUZjsL0Y8bNeX1NCnw=; b=nzxljNvFn31nUcfwKRVoPFJu+xodrF/OixQiN+timH2hR1p34KjULmh/ehowIGB756 VSTRStEvTQhGnRc2Q/KGY4/UWyUXIdZfJC7jevgA5xZNpbdT7Zu/ai4Xt7V6zZqK4ARl DNTwbcri5F6+IIyYdRiQMAt1VI6BnbH8RnipFp6WnPxEfnyFFr3Au5P+M8E51gn6te3i cYS21qu/J85QKBOL7UHKflj1xssdzQ8y/mzSOAm/u7DxJWhNN6mbRK5fFBtxcR1h+cl8 fqDPCiyjPP/c+eXSdn6YMghIU9LooZHZCqy3zT+WT+4+9EADxY/dFwsukZTlIpYtNhDH R5Jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=ibROdXvGInj/QQaIg5EL6BOybdUZjsL0Y8bNeX1NCnw=; b=4Owx53u46W6tI04RykZ49WwN/8kdz2R3a4RpRJFVuyh92snf5rDjaFu6Uv1iPoqhfx Px7pYjZ8edh/afUQeS/OCS+m3tk4ISUYv4PID6iO6EX+kP5u3uXc1J1mwJfTUuq2C5l2 tInEczgGsUOxa0TDmCyJ/BFyqsz61voZA+LVP+hTUvedJHVM+AoWPSWm56vSc+iThGoD pcY1lPcV359RqqPlgJzY232h4iYfp/UgPWoOLcXpfbANfEAAT4SWwbujMf6mkobZ5Blf 20oTmDSA9vi8lg7ab9nL0x5l0B//+4InHLMUIujAO+7FEIkBHSmcGw9xx99pwcgubN6t oQ4Q== X-Gm-Message-State: AO0yUKVx+aVAoSNM9UOYGHGjAVYjcmiJT4+6pbmMnWaT5TgCRfrbEX2x RRFshXurJ1VrVZYgNjO1t66I/p+b9mCFWzGm X-Google-Smtp-Source: AK7set/DbKIoVn0Owmhcw2uPYVA3qVc2BB0Yx15VIOM5V61qYIHcbAzK4ttlXwhNrwKa03KXsrb6wg== X-Received: by 2002:a05:600c:54e5:b0:3dc:4f2c:c856 with SMTP id jb5-20020a05600c54e500b003dc4f2cc856mr12827581wmb.32.1675188122352; Tue, 31 Jan 2023 10:02:02 -0800 (PST) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id c17-20020adffb11000000b002bc8130cca7sm15453146wrr.23.2023.01.31.10.02.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 10:02:01 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v4 00/14] Add support for the T-Head vendor extensions Date: Tue, 31 Jan 2023 19:01:44 +0100 Message-Id: <20230131180158.2471047-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=christoph.muellner@vrull.eu; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 18:02:16 -0000 From: Christoph Müllner This series introduces support for the T-Head vendor extensions, which are implemented e.g. in the XuanTie C906 and XuanTie C910: * XTheadBa * XTheadBb * XTheadBs * XTheadCmo * XTheadCondMov * XTheadFMemIdx * XTheadFmv * XTheadMac * XTheadMemIdx * XTheadMemPair * XTheadSync The xthead* extensions are documented here: https://github.com/T-head-Semi/thead-extension-spec/releases/latest The "th." instruction prefix prevents future conflicts with standard extensions and has been documentented in the RISC-V toolchain conventions: https://github.com/riscv-non-isa/riscv-toolchain-conventions Note, that the T-Head vendor extensions do not contain all vendor-specific functionality of the T-Head SoCs (e.g. no vendor-specific CSRs are included). Instead the extensions cover coherent functionality, that is exposed to S and U mode. To enable the extensions above, the following two methods are possible: * add the extension to the arch string E.g. QEMU_CPU="any,xtheadcmo=true,xtheadsync=true" * implicitly select the extensions via CPU selection E.g. QEMU_CPU="thead-c906" Major changes in v2: - Add ISA_EXT_DATA_ENTRY()s - Use single decoder for XThead extensions - Simplify a lot of translation functions - Fix RV32 behaviour - Added XTheadFmv - Addressed all comments of v1 Major changes in v3: - Drop XMAE patch - Rename priv level test macros Changes in v4: - Address review comments from Richard Henderson Christoph Müllner (14): RISC-V: Adding XTheadCmo ISA extension RISC-V: Adding XTheadSync ISA extension RISC-V: Adding XTheadBa ISA extension RISC-V: Adding XTheadBb ISA extension RISC-V: Adding XTheadBs ISA extension RISC-V: Adding XTheadCondMov ISA extension RISC-V: Adding T-Head multiply-accumulate instructions RISC-V: Adding T-Head MemPair extension RISC-V: Adding T-Head MemIdx extension RISC-V: Adding T-Head FMemIdx extension RISC-V: Set minimum priv version for Zfh to 1.11 RISC-V: Add initial support for T-Head C906 RISC-V: Adding XTheadFmv ISA extension target/riscv: add a MAINTAINERS entry for XThead* extension support MAINTAINERS | 8 + target/riscv/cpu.c | 55 +- target/riscv/cpu.h | 12 + target/riscv/cpu_vendorid.h | 6 + target/riscv/helper.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 1100 ++++++++++++++++++++ target/riscv/meson.build | 1 + target/riscv/op_helper.c | 6 + target/riscv/translate.c | 31 + target/riscv/xthead.decode | 185 ++++ 10 files changed, 1404 insertions(+), 1 deletion(-) create mode 100644 target/riscv/cpu_vendorid.h create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc create mode 100644 target/riscv/xthead.decode -- 2.39.1 From MAILER-DAEMON Tue Jan 31 13:02:42 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMuxt-0007VG-Gd for mharc-qemu-riscv@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=christoph.muellner@vrull.eu; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 18:02:22 -0000 On Tue, Jan 24, 2023 at 10:26 PM Richard Henderson wrote: > > On 1/24/23 09:59, Christoph Muellner wrote: > > +++ b/target/riscv/cpu.h > > @@ -27,6 +27,7 @@ > > #include "qom/object.h" > > #include "qemu/int128.h" > > #include "cpu_bits.h" > > +#include "cpu_vendorid.h" > > I don't see that this ID is required for all users of riscv/cpu.h. > This include should be limited to cpu.c. Fixed in v4. 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id c17-20020adffb11000000b002bc8130cca7sm15453146wrr.23.2023.01.31.10.02.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 10:02:12 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v4 04/14] RISC-V: Adding XTheadBb ISA extension Date: Tue, 31 Jan 2023 19:01:48 +0100 Message-Id: <20230131180158.2471047-5-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131180158.2471047-1-christoph.muellner@vrull.eu> References: <20230131180158.2471047-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 18:02:30 -0000 From: Christoph Müllner This patch adds support for the XTheadBb ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Split XtheadB* extension into individual commits - Make implementation compatible with RV32. - Use single decoder for XThead extensions target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 124 +++++++++++++++++++++ target/riscv/translate.c | 4 +- target/riscv/xthead.decode | 20 ++++ 5 files changed, 149 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index dd5ff82f22..def27a53f2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -110,6 +110,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), + ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), @@ -1092,6 +1093,7 @@ static Property riscv_cpu_extensions[] = { /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), + DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f1f7795bd5..be86c2fb95 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -474,6 +474,7 @@ struct RISCVCPUConfig { /* Vendor-specific custom extensions */ bool ext_xtheadba; + bool ext_xtheadbb; bool ext_xtheadcmo; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index a6fb8132a8..ebfab90dd9 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -22,6 +22,12 @@ } \ } while (0) +#define REQUIRE_XTHEADBB(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadbb) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADCMO(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadcmo) { \ return false; \ @@ -67,6 +73,124 @@ GEN_TRANS_TH_ADDSL(1) GEN_TRANS_TH_ADDSL(2) GEN_TRANS_TH_ADDSL(3) +/* XTheadBb */ + +/* th.srri is an alternate encoding for rori (from Zbb) */ +static bool trans_th_srri(DisasContext *ctx, arg_th_srri * a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE, + tcg_gen_rotri_tl, gen_roriw, NULL); +} + +/* th.srriw is an alternate encoding for roriw (from Zbb) */ +static bool trans_th_srriw(DisasContext *ctx, arg_th_srriw *a) +{ + REQUIRE_XTHEADBB(ctx); + REQUIRE_64BIT(ctx); + ctx->ol = MXL_RV32; + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL); +} + +/* th.ext and th.extu perform signed/unsigned bitfield extraction */ +static bool gen_th_bfextract(DisasContext *ctx, arg_th_bfext *a, + void (*f)(TCGv, TCGv, unsigned int, unsigned int)) +{ + TCGv dest = dest_gpr(ctx, a->rd); + TCGv source = get_gpr(ctx, a->rs1, EXT_ZERO); + + if (a->lsb <= a->msb) { + f(dest, source, a->lsb, a->msb - a->lsb + 1); + gen_set_gpr(ctx, a->rd, dest); + } + return true; +} + +static bool trans_th_ext(DisasContext *ctx, arg_th_ext *a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_th_bfextract(ctx, a, tcg_gen_sextract_tl); +} + +static bool trans_th_extu(DisasContext *ctx, arg_th_extu *a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_th_bfextract(ctx, a, tcg_gen_extract_tl); +} + +/* th.ff0: find first zero (clz on an inverted input) */ +static bool gen_th_ff0(DisasContext *ctx, arg_th_ff0 *a, DisasExtend ext) +{ + TCGv dest = dest_gpr(ctx, a->rd); + TCGv src1 = get_gpr(ctx, a->rs1, ext); + + int olen = get_olen(ctx); + TCGv t = tcg_temp_new(); + + tcg_gen_not_tl(t, src1); + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + gen_clzw(dest, t); + } else { + g_assert_not_reached(); + } + } else { + gen_clz(dest, t); + } + + tcg_temp_free(t); + gen_set_gpr(ctx, a->rd, dest); + + return true; +} + +static bool trans_th_ff0(DisasContext *ctx, arg_th_ff0 *a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_th_ff0(ctx, a, EXT_NONE); +} + +/* th.ff1 is an alternate encoding for clz (from Zbb) */ +static bool trans_th_ff1(DisasContext *ctx, arg_th_ff1 *a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw); +} + +static void gen_th_revw(TCGv ret, TCGv arg1) +{ + tcg_gen_bswap32_tl(ret, arg1, TCG_BSWAP_OS); +} + +/* th.rev is an alternate encoding for the RV64 rev8 (from Zbb) */ +static bool trans_th_rev(DisasContext *ctx, arg_th_rev *a) +{ + REQUIRE_XTHEADBB(ctx); + + return gen_unary_per_ol(ctx, a, EXT_NONE, tcg_gen_bswap_tl, gen_th_revw); +} + +/* th.revw is a sign-extended byte-swap of the lower word */ +static bool trans_th_revw(DisasContext *ctx, arg_th_revw *a) +{ + REQUIRE_XTHEADBB(ctx); + REQUIRE_64BIT(ctx); + return gen_unary(ctx, a, EXT_NONE, gen_th_revw); +} + +/* th.tstnbz is equivalent to an orc.b (from Zbb) with inverted result */ +static void gen_th_tstnbz(TCGv ret, TCGv source1) +{ + gen_orc_b(ret, source1); + tcg_gen_not_tl(ret, ret); +} + +static bool trans_th_tstnbz(DisasContext *ctx, arg_th_tstnbz *a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_unary(ctx, a, EXT_ZERO, gen_th_tstnbz); +} + /* XTheadCmo */ static inline int priv_level(DisasContext *ctx) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 4683562ecf..387ef0ad8b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -132,8 +132,8 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { - return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadcmo || - ctx->cfg_ptr->ext_xtheadsync; + return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || + ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index b149f13018..8cd140891b 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -13,14 +13,23 @@ %rd 7:5 %rs1 15:5 %rs2 20:5 +%sh5 20:5 +%sh6 20:6 # Argument sets &r rd rs1 rs2 !extern +&r2 rd rs1 !extern +&shift shamt rs1 rd !extern +&th_bfext msb lsb rs1 rd # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd +@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd +@th_bfext msb:6 lsb:6 ..... ... ..... ....... &th_bfext %rs1 %rd +@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd +@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd # XTheadBa # Instead of defining a new encoding, we simply use the decoder to @@ -38,6 +47,17 @@ th_addsl1 0000001 ..... ..... 001 ..... 0001011 @r th_addsl2 0000010 ..... ..... 001 ..... 0001011 @r th_addsl3 0000011 ..... ..... 001 ..... 0001011 @r +# XTheadBb +th_ext ...... ...... ..... 010 ..... 0001011 @th_bfext +th_extu ...... ...... ..... 011 ..... 0001011 @th_bfext +th_ff0 1000010 00000 ..... 001 ..... 0001011 @r2 +th_ff1 1000011 00000 ..... 001 ..... 0001011 @r2 +th_srri 000100 ...... ..... 001 ..... 0001011 @sh6 +th_srriw 0001010 ..... ..... 001 ..... 0001011 @sh5 +th_rev 1000001 00000 ..... 001 ..... 0001011 @r2 +th_revw 1001000 00000 ..... 001 ..... 0001011 @r2 +th_tstnbz 1000000 00000 ..... 001 ..... 0001011 @r2 + # XTheadCmo th_dcache_call 0000000 00001 00000 000 00000 0001011 th_dcache_ciall 0000000 00011 00000 000 00000 0001011 -- 2.39.1 From MAILER-DAEMON Tue Jan 31 13:02:51 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMuy2-0007gi-VK for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id c17-20020adffb11000000b002bc8130cca7sm15453146wrr.23.2023.01.31.10.02.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 10:02:16 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v4 07/14] RISC-V: Adding T-Head multiply-accumulate instructions Date: Tue, 31 Jan 2023 19:01:51 +0100 Message-Id: <20230131180158.2471047-8-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131180158.2471047-1-christoph.muellner@vrull.eu> References: <20230131180158.2471047-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 18:02:30 -0000 From: Christoph Müllner This patch adds support for the T-Head MAC instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 83 ++++++++++++++++++++++ target/riscv/translate.c | 3 +- target/riscv/xthead.decode | 8 +++ 5 files changed, 96 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 13b065bc68..88da4de14d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), + ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), }; @@ -1099,6 +1100,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), + DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a313e025e7..830b20558c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -478,6 +478,7 @@ struct RISCVCPUConfig { bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadcondmov; + bool ext_xtheadmac; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index 089b51f468..31a4034927 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -46,6 +46,12 @@ } \ } while (0) +#define REQUIRE_XTHEADMAC(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadmac) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADSYNC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadsync) { \ return false; \ @@ -299,6 +305,83 @@ static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a) return gen_th_condmove(ctx, a, TCG_COND_NE); } +/* XTheadMac */ + +static bool gen_th_mac(DisasContext *ctx, arg_r *a, + void (*accumulate_func)(TCGv, TCGv, TCGv), + void (*extend_operand_func)(TCGv, TCGv)) +{ + TCGv dest = dest_gpr(ctx, a->rd); + TCGv src0 = get_gpr(ctx, a->rd, EXT_NONE); + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); + TCGv tmp = tcg_temp_new(); + + if (extend_operand_func) { + TCGv tmp2 = tcg_temp_new(); + extend_operand_func(tmp, src1); + extend_operand_func(tmp2, src2); + tcg_gen_mul_tl(tmp, tmp, tmp2); + tcg_temp_free(tmp2); + } else { + tcg_gen_mul_tl(tmp, src1, src2); + } + + accumulate_func(dest, src0, tmp); + gen_set_gpr(ctx, a->rd, dest); + tcg_temp_free(tmp); + + return true; +} + +/* th.mula: "rd = rd + rs1 * rs2" */ +static bool trans_th_mula(DisasContext *ctx, arg_th_mula *a) +{ + REQUIRE_XTHEADMAC(ctx); + return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL); +} + +/* th.mulah: "rd = sext.w(rd + sext.w(rs1[15:0]) * sext.w(rs2[15:0]))" */ +static bool trans_th_mulah(DisasContext *ctx, arg_th_mulah *a) +{ + REQUIRE_XTHEADMAC(ctx); + ctx->ol = MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_add_tl, tcg_gen_ext16s_tl); +} + +/* th.mulaw: "rd = sext.w(rd + rs1 * rs2)" */ +static bool trans_th_mulaw(DisasContext *ctx, arg_th_mulaw *a) +{ + REQUIRE_XTHEADMAC(ctx); + REQUIRE_64BIT(ctx); + ctx->ol = MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL); +} + +/* th.muls: "rd = rd - rs1 * rs2" */ +static bool trans_th_muls(DisasContext *ctx, arg_th_muls *a) +{ + REQUIRE_XTHEADMAC(ctx); + return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); +} + +/* th.mulsh: "rd = sext.w(rd - sext.w(rs1[15:0]) * sext.w(rs2[15:0]))" */ +static bool trans_th_mulsh(DisasContext *ctx, arg_th_mulsh *a) +{ + REQUIRE_XTHEADMAC(ctx); + ctx->ol = MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_sub_tl, tcg_gen_ext16s_tl); +} + +/* th.mulsw: "rd = sext.w(rd - rs1 * rs2)" */ +static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a) +{ + REQUIRE_XTHEADMAC(ctx); + REQUIRE_64BIT(ctx); + ctx->ol = MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); +} + /* XTheadSync */ static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 4f4c09cd68..e5a57a8516 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -134,7 +134,8 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || - ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac || + ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index a8ebd8a18b..696de6cecf 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -88,6 +88,14 @@ th_l2cache_iall 0000000 10110 00000 000 00000 0001011 th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r +# XTheadMac +th_mula 00100 00 ..... ..... 001 ..... 0001011 @r +th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r +th_mulaw 00100 10 ..... ..... 001 ..... 0001011 @r +th_muls 00100 01 ..... ..... 001 ..... 0001011 @r +th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r +th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r + # XTheadSync th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s th_sync 0000000 11000 00000 000 00000 0001011 -- 2.39.1 From MAILER-DAEMON Tue Jan 31 13:02:56 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMuy4-0007hZ-1A for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id c17-20020adffb11000000b002bc8130cca7sm15453146wrr.23.2023.01.31.10.02.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 10:02:10 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v4 03/14] RISC-V: Adding XTheadBa ISA extension Date: Tue, 31 Jan 2023 19:01:47 +0100 Message-Id: <20230131180158.2471047-4-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131180158.2471047-1-christoph.muellner@vrull.eu> References: <20230131180158.2471047-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 18:02:30 -0000 From: Christoph Müllner This patch adds support for the XTheadBa ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Split XtheadB* extension into individual commits - Use single decoder for XThead extensions target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 39 ++++++++++++++++++++++ target/riscv/translate.c | 3 +- target/riscv/xthead.decode | 22 ++++++++++++ 5 files changed, 66 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f76639845d..dd5ff82f22 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -109,6 +109,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), @@ -1090,6 +1091,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), /* Vendor-specific custom extensions */ + DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ea00586436..f1f7795bd5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -473,6 +473,7 @@ struct RISCVCPUConfig { uint64_t mimpid; /* Vendor-specific custom extensions */ + bool ext_xtheadba; bool ext_xtheadcmo; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index f35bf6ea89..a6fb8132a8 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -16,6 +16,12 @@ * this program. If not, see . */ +#define REQUIRE_XTHEADBA(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadba) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADCMO(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadcmo) { \ return false; \ @@ -28,6 +34,39 @@ } \ } while (0) +/* XTheadBa */ + +/* + * th.addsl is similar to sh[123]add (from Zba), but not an + * alternative encoding: while sh[123] applies the shift to rs1, + * th.addsl shifts rs2. + */ + +#define GEN_TH_ADDSL(SHAMT) \ +static void gen_th_addsl##SHAMT(TCGv ret, TCGv arg1, TCGv arg2) \ +{ \ + TCGv t = tcg_temp_new(); \ + tcg_gen_shli_tl(t, arg2, SHAMT); \ + tcg_gen_add_tl(ret, t, arg1); \ + tcg_temp_free(t); \ +} + +GEN_TH_ADDSL(1) +GEN_TH_ADDSL(2) +GEN_TH_ADDSL(3) + +#define GEN_TRANS_TH_ADDSL(SHAMT) \ +static bool trans_th_addsl##SHAMT(DisasContext *ctx, \ + arg_th_addsl##SHAMT * a) \ +{ \ + REQUIRE_XTHEADBA(ctx); \ + return gen_arith(ctx, a, EXT_NONE, gen_th_addsl##SHAMT, NULL); \ +} + +GEN_TRANS_TH_ADDSL(1) +GEN_TRANS_TH_ADDSL(2) +GEN_TRANS_TH_ADDSL(3) + /* XTheadCmo */ static inline int priv_level(DisasContext *ctx) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0657a4bea2..4683562ecf 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -132,7 +132,8 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { - return ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; + return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadcmo || + ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 1d86f3a012..b149f13018 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -2,6 +2,7 @@ # Translation routines for the instructions of the XThead* ISA extensions # # Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu +# Dr. Philipp Tomsich, philipp.tomsich@vrull.eu # # SPDX-License-Identifier: LGPL-2.1-or-later # @@ -9,12 +10,33 @@ # https://github.com/T-head-Semi/thead-extension-spec/releases/latest # Fields: +%rd 7:5 %rs1 15:5 %rs2 20:5 +# Argument sets +&r rd rs1 rs2 !extern + # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 +@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd + +# XTheadBa +# Instead of defining a new encoding, we simply use the decoder to +# extract the imm[0:1] field and dispatch to separate translation +# functions (mirroring the `sh[123]add` instructions from Zba and +# the regular RVI `add` instruction. +# +# The only difference between sh[123]add and addsl is that the shift +# is applied to rs1 (for addsl) instead of rs2 (for sh[123]add). +# +# Note that shift-by-0 is a valid operation according to the manual. +# This will be equivalent to a regular add. +add 0000000 ..... ..... 001 ..... 0001011 @r +th_addsl1 0000001 ..... ..... 001 ..... 0001011 @r +th_addsl2 0000010 ..... ..... 001 ..... 0001011 @r +th_addsl3 0000011 ..... ..... 001 ..... 0001011 @r # XTheadCmo th_dcache_call 0000000 00001 00000 000 00000 0001011 -- 2.39.1 From MAILER-DAEMON Tue Jan 31 13:03:10 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMuy8-0007jK-Jg for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id c17-20020adffb11000000b002bc8130cca7sm15453146wrr.23.2023.01.31.10.02.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 10:02:14 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v4 06/14] RISC-V: Adding XTheadCondMov ISA extension Date: Tue, 31 Jan 2023 19:01:50 +0100 Message-Id: <20230131180158.2471047-7-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131180158.2471047-1-christoph.muellner@vrull.eu> References: <20230131180158.2471047-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 18:02:28 -0000 From: Christoph Müllner This patch adds support for the XTheadCondMov ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Fix invalid use of register from dest_gpr() - Use single decoder for XThead extensions target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 35 ++++++++++++++++++++++ target/riscv/translate.c | 2 +- target/riscv/xthead.decode | 4 +++ 5 files changed, 43 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c541924214..13b065bc68 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -113,6 +113,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), + ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), }; @@ -1097,6 +1098,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), + DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 876eaebd0e..a313e025e7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -477,6 +477,7 @@ struct RISCVCPUConfig { bool ext_xtheadbb; bool ext_xtheadbs; bool ext_xtheadcmo; + bool ext_xtheadcondmov; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index bc1605445d..089b51f468 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -40,6 +40,12 @@ } \ } while (0) +#define REQUIRE_XTHEADCONDMOV(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadcondmov) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADSYNC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadsync) { \ return false; \ @@ -264,6 +270,35 @@ NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +/* XTheadCondMov */ + +static bool gen_th_condmove(DisasContext *ctx, arg_r *a, TCGCond cond) +{ + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); + TCGv old = get_gpr(ctx, a->rd, EXT_NONE); + TCGv dest = dest_gpr(ctx, a->rd); + + tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, old); + + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +/* th.mveqz: "if (rs2 == 0) rd = rs1;" */ +static bool trans_th_mveqz(DisasContext *ctx, arg_th_mveqz *a) +{ + REQUIRE_XTHEADCONDMOV(ctx); + return gen_th_condmove(ctx, a, TCG_COND_EQ); +} + +/* th.mvnez: "if (rs2 != 0) rd = rs1;" */ +static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a) +{ + REQUIRE_XTHEADCONDMOV(ctx); + return gen_th_condmove(ctx, a, TCG_COND_NE); +} + /* XTheadSync */ static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 880324e617..4f4c09cd68 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -134,7 +134,7 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || - ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 8494805611..a8ebd8a18b 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -84,6 +84,10 @@ th_l2cache_call 0000000 10101 00000 000 00000 0001011 th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 th_l2cache_iall 0000000 10110 00000 000 00000 0001011 +# XTheadCondMov +th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r +th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r + # XTheadSync th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s th_sync 0000000 11000 00000 000 00000 0001011 -- 2.39.1 From MAILER-DAEMON Tue Jan 31 13:03:11 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMuyM-0007lA-4q for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id c17-20020adffb11000000b002bc8130cca7sm15453146wrr.23.2023.01.31.10.02.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 10:02:13 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v4 05/14] RISC-V: Adding XTheadBs ISA extension Date: Tue, 31 Jan 2023 19:01:49 +0100 Message-Id: <20230131180158.2471047-6-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131180158.2471047-1-christoph.muellner@vrull.eu> References: <20230131180158.2471047-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 18:02:30 -0000 From: Christoph Müllner This patch adds support for the XTheadBs ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Split XtheadB* extension into individual commits - Use single decoder for XThead extensions target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 15 +++++++++++++++ target/riscv/translate.c | 3 ++- target/riscv/xthead.decode | 3 +++ 5 files changed, 23 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index def27a53f2..c541924214 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -111,6 +111,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), + ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), @@ -1094,6 +1095,7 @@ static Property riscv_cpu_extensions[] = { /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), + DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index be86c2fb95..876eaebd0e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -475,6 +475,7 @@ struct RISCVCPUConfig { /* Vendor-specific custom extensions */ bool ext_xtheadba; bool ext_xtheadbb; + bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index ebfab90dd9..bc1605445d 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -28,6 +28,12 @@ } \ } while (0) +#define REQUIRE_XTHEADBS(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadbs) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADCMO(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadcmo) { \ return false; \ @@ -191,6 +197,15 @@ static bool trans_th_tstnbz(DisasContext *ctx, arg_th_tstnbz *a) return gen_unary(ctx, a, EXT_ZERO, gen_th_tstnbz); } +/* XTheadBs */ + +/* th.tst is an alternate encoding for bexti (from Zbs) */ +static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a) +{ + REQUIRE_XTHEADBS(ctx); + return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext); +} + /* XTheadCmo */ static inline int priv_level(DisasContext *ctx) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 387ef0ad8b..880324e617 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -133,7 +133,8 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || - ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || + ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 8cd140891b..8494805611 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -58,6 +58,9 @@ th_rev 1000001 00000 ..... 001 ..... 0001011 @r2 th_revw 1001000 00000 ..... 001 ..... 0001011 @r2 th_tstnbz 1000000 00000 ..... 001 ..... 0001011 @r2 +# XTheadBs +th_tst 100010 ...... ..... 001 ..... 0001011 @sh6 + # XTheadCmo th_dcache_call 0000000 00001 00000 000 00000 0001011 th_dcache_ciall 0000000 00011 00000 000 00000 0001011 -- 2.39.1 From MAILER-DAEMON Tue Jan 31 13:03:59 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMuz9-0000GR-2k for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 13:03:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMuxS-0007FW-QR for qemu-riscv@nongnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id c17-20020adffb11000000b002bc8130cca7sm15453146wrr.23.2023.01.31.10.02.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 10:02:08 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v4 02/14] RISC-V: Adding XTheadSync ISA extension Date: Tue, 31 Jan 2023 19:01:46 +0100 Message-Id: <20230131180158.2471047-3-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131180158.2471047-1-christoph.muellner@vrull.eu> References: <20230131180158.2471047-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 18:02:25 -0000 From: Christoph Müllner This patch adds support for the XTheadSync ISA extension. The patch uses the T-Head specific decoder and translation. The implementation introduces a helper to execute synchronization tasks: helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use helper to synchronize CPUs and perform TLB flushes - Change implemenation to follow latest spec update - Use single decoder for XThead extensions Changes in v3: - Adjust for renamed REQUIRE_PRIV_* test macros Changes in v4: - Drop decode_save_opc() in trans_th_sfence_vmas() target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/helper.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 85 ++++++++++++++++++++++ target/riscv/op_helper.c | 6 ++ target/riscv/translate.c | 2 +- target/riscv/xthead.decode | 9 +++ 7 files changed, 105 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6ea61e5b22..f76639845d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -110,6 +110,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), + ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), }; @@ -1090,6 +1091,7 @@ static Property riscv_cpu_extensions[] = { /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), + DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), /* These are experimental so mark with 'x-' */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d3ebc6f112..ea00586436 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -474,6 +474,7 @@ struct RISCVCPUConfig { /* Vendor-specific custom extensions */ bool ext_xtheadcmo; + bool ext_xtheadsync; bool ext_XVentanaCondOps; uint8_t pmu_num; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 58a30f03d6..0497370afd 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -109,6 +109,7 @@ DEF_HELPER_1(sret, tl, env) DEF_HELPER_1(mret, tl, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(tlb_flush, void, env) +DEF_HELPER_1(tlb_flush_all, void, env) /* Native Debug */ DEF_HELPER_1(itrigger_match, void, env) #endif diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index 24acaf188c..f35bf6ea89 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -22,6 +22,12 @@ } \ } while (0) +#define REQUIRE_XTHEADSYNC(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadsync) { \ + return false; \ + } \ +} while (0) + /* XTheadCmo */ static inline int priv_level(DisasContext *ctx) @@ -79,3 +85,82 @@ NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU) NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) + +/* XTheadSync */ + +static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a) +{ + (void) a; + REQUIRE_XTHEADSYNC(ctx); + +#ifndef CONFIG_USER_ONLY + REQUIRE_PRIV_MS(ctx); + gen_helper_tlb_flush_all(cpu_env); + return true; +#else + return false; +#endif +} + +#ifndef CONFIG_USER_ONLY +static void gen_th_sync_local(DisasContext *ctx) +{ + /* + * Emulate out-of-order barriers with pipeline flush + * by exiting the translation block. + */ + gen_set_pc_imm(ctx, ctx->pc_succ_insn); + tcg_gen_exit_tb(NULL, 0); + ctx->base.is_jmp = DISAS_NORETURN; +} +#endif + +static bool trans_th_sync(DisasContext *ctx, arg_th_sync *a) +{ + (void) a; + REQUIRE_XTHEADSYNC(ctx); + +#ifndef CONFIG_USER_ONLY + REQUIRE_PRIV_MSU(ctx); + + /* + * th.sync is an out-of-order barrier. + */ + gen_th_sync_local(ctx); + + return true; +#else + return false; +#endif +} + +static bool trans_th_sync_i(DisasContext *ctx, arg_th_sync_i *a) +{ + (void) a; + REQUIRE_XTHEADSYNC(ctx); + +#ifndef CONFIG_USER_ONLY + REQUIRE_PRIV_MSU(ctx); + + /* + * th.sync.i is th.sync plus pipeline flush. + */ + gen_th_sync_local(ctx); + + return true; +#else + return false; +#endif +} + +static bool trans_th_sync_is(DisasContext *ctx, arg_th_sync_is *a) +{ + /* This instruction has the same behaviour like th.sync.i. */ + return trans_th_sync_i(ctx, a); +} + +static bool trans_th_sync_s(DisasContext *ctx, arg_th_sync_s *a) +{ + /* This instruction has the same behaviour like th.sync. */ + return trans_th_sync(ctx, a); +} diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 878bcb03b8..48f918b71b 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -258,6 +258,12 @@ void helper_tlb_flush(CPURISCVState *env) } } +void helper_tlb_flush_all(CPURISCVState *env) +{ + CPUState *cs = env_cpu(env); + tlb_flush_all_cpus_synced(cs); +} + void helper_hyp_tlb_flush(CPURISCVState *env) { CPUState *cs = env_cpu(env); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1e29ac9886..0657a4bea2 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -132,7 +132,7 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { - return ctx->cfg_ptr->ext_xtheadcmo; + return ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 30533a66f5..1d86f3a012 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -10,9 +10,11 @@ # Fields: %rs1 15:5 +%rs2 20:5 # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 +@rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 # XTheadCmo th_dcache_call 0000000 00001 00000 000 00000 0001011 @@ -36,3 +38,10 @@ th_icache_iva 0000001 10000 ..... 000 00000 0001011 @sfence_vm th_l2cache_call 0000000 10101 00000 000 00000 0001011 th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 th_l2cache_iall 0000000 10110 00000 000 00000 0001011 + +# XTheadSync +th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s +th_sync 0000000 11000 00000 000 00000 0001011 +th_sync_i 0000000 11010 00000 000 00000 0001011 +th_sync_is 0000000 11011 00000 000 00000 0001011 +th_sync_s 0000000 11001 00000 000 00000 0001011 -- 2.39.1 From MAILER-DAEMON Tue Jan 31 13:04:01 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMuzB-0000KW-El for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id c17-20020adffb11000000b002bc8130cca7sm15453146wrr.23.2023.01.31.10.02.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 10:02:25 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v4 14/14] target/riscv: add a MAINTAINERS entry for XThead* extension support Date: Tue, 31 Jan 2023 19:01:58 +0100 Message-Id: <20230131180158.2471047-15-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131180158.2471047-1-christoph.muellner@vrull.eu> References: <20230131180158.2471047-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 18:02:32 -0000 From: Christoph Müllner The XThead* extensions are maintained by T-Head and VRULL. Adding a point of contact from both companies. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c581c11a64..9dc0a2954e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -295,6 +295,14 @@ F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux-user/host/riscv64/ +RISC-V XThead* extensions +M: Christoph Muellner +M: LIU Zhiwei +L: qemu-riscv@nongnu.org +S: Supported +F: target/riscv/insn_trans/trans_xthead.c.inc +F: target/riscv/xthead*.decode + RISC-V XVentanaCondOps extension M: Philipp Tomsich L: qemu-riscv@nongnu.org -- 2.39.1 From MAILER-DAEMON Tue Jan 31 13:04:04 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMuzE-0000TK-G8 for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 13:04:04 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMuxQ-0007CR-5R for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 13:02:15 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMuxM-0000mq-RH for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 13:02:11 -0500 Received: by mail-wm1-x331.google.com with SMTP id k16so10964529wms.2 for ; Tue, 31 Jan 2023 10:02:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UIMc0yh6nW6tPabnRz0gkGn0xHCplcfPWfd18Srv1EY=; b=lqyWxB7xHKkbQouksGPnQTT2BRQnj07ZMfxDaLOO4HCnGB/x9XbGRI/SK7J2FdLKKV oll7tg+IGWGFjZQQBACJ1+9mLzc30roriyBHUKAvD2sPmu9h014oTPYPIYGrbh+jgFTc FbOsxsxvfNAvRLIAIE9SPuogdJLy0ueD8PIY3FQZ4IwilduYrPdElzQfQcDwWbjReMht MKu8jPP0EuKpQYSdImx+4oIUrvoxDKlHDzfippwSdj1QRXGf1/dK/meFUU7TiuiTeYh3 sX/fIRBgPnydlok2W4VBh3Kr3E6Y895PLFtkt6h1nUIMgxYvR8dVyTCtT7fJLwLVfMbc S/sA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UIMc0yh6nW6tPabnRz0gkGn0xHCplcfPWfd18Srv1EY=; b=IZQZih9QDFG0M9Nbup374hSmy0RvvK/2cgyBLx3ZmMEXfK8P8hIAxDWOQujjptia/K t9PxrTVKKJTRGzGrLcpV3HWgj/0cBLRFJft+aR0sQ3sFIMpoj3Caggh/OVa31ax7Y/x8 KMmc2i5tTMUEQkOyWpkcxXnvT2p1mHnPQ05JymrFYeF6GJ6J+BtwwXcPOHgK0E/KUnTv NrcgQ3geq3IA79Kx49HOs+FUaFQzQPO6D1rafp560xp8ganZ0EuLdeQ8ZMMxUYXvingT bbdlz+RDvt/zuzEh9LFKnqCcP8r05SWPWFM87eypgSjpwXeB0SreKacp67Z4HKz0NswI 7trw== X-Gm-Message-State: AO0yUKXVPmpVquX+A8RVIilThI8hQ90CvFl1+T/Mp/3rvVV3ZQWrnrJi 8Ql45PbzGh6mcjEvh1EIAy4El+n9dEfhEnQa X-Google-Smtp-Source: AK7set+yr0Q+ljRMv0Njvc4qTUkCv8TMxTEf4yz19sWty0DLrkhrG2BG5pmUbj/PjJ1hdK6mCvBHnQ== X-Received: by 2002:a05:600c:21a:b0:3dc:57e8:1d1c with SMTP id 26-20020a05600c021a00b003dc57e81d1cmr10499744wmi.9.1675188126563; Tue, 31 Jan 2023 10:02:06 -0800 (PST) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id c17-20020adffb11000000b002bc8130cca7sm15453146wrr.23.2023.01.31.10.02.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 10:02:04 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v4 01/14] RISC-V: Adding XTheadCmo ISA extension Date: Tue, 31 Jan 2023 19:01:45 +0100 Message-Id: <20230131180158.2471047-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131180158.2471047-1-christoph.muellner@vrull.eu> References: <20230131180158.2471047-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=christoph.muellner@vrull.eu; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 18:02:22 -0000 From: Christoph Müllner This patch adds support for the XTheadCmo ISA extension. To avoid interfering with standard extensions, decoder and translation are in its own xthead* specific files. Future patches should be able to easily add additional T-Head extension. The implementation does not have much functionality (besides accepting the instructions and not qualifying them as illegal instructions if the hart executes in the required privilege level for the instruction), as QEMU does not model CPU caches and instructions are documented to not raise any exceptions. Co-developed-by: LIU Zhiwei Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Explicit test for PRV_U - Encapsule access to env-priv in inline function - Use single decoder for XThead extensions Changes in v3: - Appling mask TB_FLAGS_PRIV_MMU_MASK to use of ctx->mem_idx - Removing code from test macro REQUIRE_PRIV_MSU() - Removing PRV_H from test macro REQUIRE_PRIV_MS() - Remove unrelated clean-up - Reorder decoder includes Changes in v4: - Reorder decoder includes target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 81 ++++++++++++++++++++++ target/riscv/meson.build | 1 + target/riscv/translate.c | 8 +++ target/riscv/xthead.decode | 38 ++++++++++ 6 files changed, 131 insertions(+) create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc create mode 100644 target/riscv/xthead.decode diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 14a7027095..6ea61e5b22 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -109,6 +109,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), }; @@ -1088,6 +1089,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), /* Vendor-specific custom extensions */ + DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), /* These are experimental so mark with 'x-' */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bcf0826753..d3ebc6f112 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -473,6 +473,7 @@ struct RISCVCPUConfig { uint64_t mimpid; /* Vendor-specific custom extensions */ + bool ext_xtheadcmo; bool ext_XVentanaCondOps; uint8_t pmu_num; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc new file mode 100644 index 0000000000..24acaf188c --- /dev/null +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -0,0 +1,81 @@ +/* + * RISC-V translation routines for the T-Head vendor extensions (xthead*). + * + * Copyright (c) 2022 VRULL GmbH. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#define REQUIRE_XTHEADCMO(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadcmo) { \ + return false; \ + } \ +} while (0) + +/* XTheadCmo */ + +static inline int priv_level(DisasContext *ctx) +{ +#ifdef CONFIG_USER_ONLY + return PRV_U; +#else + /* Priv level is part of mem_idx. */ + return ctx->mem_idx & TB_FLAGS_PRIV_MMU_MASK; +#endif +} + +/* Test if priv level is M, S, or U (cannot fail). */ +#define REQUIRE_PRIV_MSU(ctx) + +/* Test if priv level is M or S. */ +#define REQUIRE_PRIV_MS(ctx) \ +do { \ + int priv = priv_level(ctx); \ + if (!(priv == PRV_M || \ + priv == PRV_S)) { \ + return false; \ + } \ +} while (0) + +#define NOP_PRIVCHECK(insn, extcheck, privcheck) \ +static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn * a) \ +{ \ + (void) a; \ + extcheck(ctx); \ + privcheck(ctx); \ + return true; \ +} + +NOP_PRIVCHECK(th_dcache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cpa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU) +NOP_PRIVCHECK(th_dcache_civa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU) +NOP_PRIVCHECK(th_dcache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU) +NOP_PRIVCHECK(th_dcache_csw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cisw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_isw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cpal1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cval1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) + +NOP_PRIVCHECK(th_icache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_icache_ialls, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_icache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU) + +NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) diff --git a/target/riscv/meson.build b/target/riscv/meson.build index ba25164d74..5dee37a242 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -2,6 +2,7 @@ gen = [ decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']), decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'), + decodetree.process('xthead.decode', extra_args: '--static-decode=decode_xthead'), decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'), ] diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 01cc30a365..1e29ac9886 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -130,6 +130,11 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) return true; } +static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) +{ + return ctx->cfg_ptr->ext_xtheadcmo; +} + #define MATERIALISE_EXT_PREDICATE(ext) \ static bool has_ ## ext ## _p(DisasContext *ctx) \ { \ @@ -1080,6 +1085,8 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_rvk.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" +#include "decode-xthead.c.inc" +#include "insn_trans/trans_xthead.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" /* Include the auto-generated decoder for 16 bit insn */ @@ -1106,6 +1113,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) bool (*decode_func)(DisasContext *, uint32_t); } decoders[] = { { always_true_p, decode_insn32 }, + { has_xthead_p, decode_xthead }, { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, }; diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode new file mode 100644 index 0000000000..30533a66f5 --- /dev/null +++ b/target/riscv/xthead.decode @@ -0,0 +1,38 @@ +# +# Translation routines for the instructions of the XThead* ISA extensions +# +# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# The documentation of the ISA extensions can be found here: +# https://github.com/T-head-Semi/thead-extension-spec/releases/latest + +# Fields: +%rs1 15:5 + +# Formats +@sfence_vm ....... ..... ..... ... ..... ....... %rs1 + +# XTheadCmo +th_dcache_call 0000000 00001 00000 000 00000 0001011 +th_dcache_ciall 0000000 00011 00000 000 00000 0001011 +th_dcache_iall 0000000 00010 00000 000 00000 0001011 +th_dcache_cpa 0000001 01001 ..... 000 00000 0001011 @sfence_vm +th_dcache_cipa 0000001 01011 ..... 000 00000 0001011 @sfence_vm +th_dcache_ipa 0000001 01010 ..... 000 00000 0001011 @sfence_vm +th_dcache_cva 0000001 00101 ..... 000 00000 0001011 @sfence_vm +th_dcache_civa 0000001 00111 ..... 000 00000 0001011 @sfence_vm +th_dcache_iva 0000001 00110 ..... 000 00000 0001011 @sfence_vm +th_dcache_csw 0000001 00001 ..... 000 00000 0001011 @sfence_vm +th_dcache_cisw 0000001 00011 ..... 000 00000 0001011 @sfence_vm +th_dcache_isw 0000001 00010 ..... 000 00000 0001011 @sfence_vm +th_dcache_cpal1 0000001 01000 ..... 000 00000 0001011 @sfence_vm +th_dcache_cval1 0000001 00100 ..... 000 00000 0001011 @sfence_vm +th_icache_iall 0000000 10000 00000 000 00000 0001011 +th_icache_ialls 0000000 10001 00000 000 00000 0001011 +th_icache_ipa 0000001 11000 ..... 000 00000 0001011 @sfence_vm +th_icache_iva 0000001 10000 ..... 000 00000 0001011 @sfence_vm +th_l2cache_call 0000000 10101 00000 000 00000 0001011 +th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 +th_l2cache_iall 0000000 10110 00000 000 00000 0001011 -- 2.39.1 From MAILER-DAEMON Tue Jan 31 13:04:05 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMuzF-0000Xl-JV for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id c17-20020adffb11000000b002bc8130cca7sm15453146wrr.23.2023.01.31.10.02.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 10:02:18 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v4 09/14] RISC-V: Adding T-Head MemIdx extension Date: Tue, 31 Jan 2023 19:01:53 +0100 Message-Id: <20230131180158.2471047-10-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131180158.2471047-1-christoph.muellner@vrull.eu> References: <20230131180158.2471047-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 18:02:31 -0000 From: Christoph Müllner This patch adds support for the T-Head MemIdx instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions - Avoid signed-bitfield-extraction by using signed immediate field imm5 - Use get_address() to calculate addresses - Introduce helper get_th_address_indexed for rs1+(rs2<cfg_ptr->ext_xtheadmemidx) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADMEMPAIR(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadmempair) { \ return false; \ @@ -64,6 +70,30 @@ } \ } while (0) +/* + * Calculate and return the address for indexed mem operations: + * If !zext_offs, then the address is rs1 + (rs2 << imm2). + * If zext_offs, then the address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static TCGv get_th_address_indexed(DisasContext *ctx, int rs1, int rs2, + int imm2, bool zext_offs) +{ + TCGv src2 = get_gpr(ctx, rs2, EXT_NONE); + TCGv offs = tcg_temp_new(); + + if (zext_offs) { + tcg_gen_extract_tl(offs, src2, 0, 32); + tcg_gen_shli_tl(offs, offs, imm2); + } else { + tcg_gen_shli_tl(offs, src2, imm2); + } + + TCGv addr = get_address_indexed(ctx, rs1, offs); + + tcg_temp_free(offs); + return addr; +} + /* XTheadBa */ /* @@ -388,6 +418,363 @@ static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a) return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); } +/* XTheadMemIdx */ + +/* + * Load with memop from indexed address and add (imm5 << imm2) to rs1. + * If !preinc, then the load address is rs1. + * If preinc, then the load address is rs1 + (imm5) << imm2). + */ +static bool gen_load_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop, + bool preinc) +{ + if (a->rs1 == a->rd) { + return false; + } + + int imm = a->imm5 << a->imm2; + TCGv addr = get_address(ctx, a->rs1, preinc ? imm : 0); + TCGv rd = dest_gpr(ctx, a->rd); + TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE); + + tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); + tcg_gen_addi_tl(rs1, rs1, imm); + gen_set_gpr(ctx, a->rd, rd); + gen_set_gpr(ctx, a->rs1, rs1); + + tcg_temp_free(addr); + return true; +} + +/* + * Store with memop to indexed address and add (imm5 << imm2) to rs1. + * If !preinc, then the store address is rs1. + * If preinc, then the store address is rs1 + (imm5) << imm2). + */ +static bool gen_store_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop, + bool preinc) +{ + int imm = a->imm5 << a->imm2; + TCGv addr = get_address(ctx, a->rs1, preinc ? imm : 0); + TCGv data = get_gpr(ctx, a->rd, EXT_NONE); + TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE); + + tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); + tcg_gen_addi_tl(rs1, rs1, imm); + gen_set_gpr(ctx, a->rs1, rs1); + + tcg_temp_free(addr); + return true; +} + +static bool trans_th_ldia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_inc(ctx, a, MO_TESQ, false); +} + +static bool trans_th_ldib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_inc(ctx, a, MO_TESQ, true); +} + +static bool trans_th_lwia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TESL, false); +} + +static bool trans_th_lwib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TESL, true); +} + +static bool trans_th_lwuia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_inc(ctx, a, MO_TEUL, false); +} + +static bool trans_th_lwuib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_inc(ctx, a, MO_TEUL, true); +} + +static bool trans_th_lhia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TESW, false); +} + +static bool trans_th_lhib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TESW, true); +} + +static bool trans_th_lhuia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TEUW, false); +} + +static bool trans_th_lhuib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TEUW, true); +} + +static bool trans_th_lbia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_SB, false); +} + +static bool trans_th_lbib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_SB, true); +} + +static bool trans_th_lbuia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_UB, false); +} + +static bool trans_th_lbuib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_UB, true); +} + +static bool trans_th_sdia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_store_inc(ctx, a, MO_TESQ, false); +} + +static bool trans_th_sdib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_store_inc(ctx, a, MO_TESQ, true); +} + +static bool trans_th_swia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_TESL, false); +} + +static bool trans_th_swib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_TESL, true); +} + +static bool trans_th_shia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_TESW, false); +} + +static bool trans_th_shib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_TESW, true); +} + +static bool trans_th_sbia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_SB, false); +} + +static bool trans_th_sbib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_SB, true); +} + +/* + * Load with memop from indexed address. + * If !zext_offs, then address is rs1 + (rs2 << imm2). + * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static bool gen_load_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop, + bool zext_offs) +{ + TCGv rd = dest_gpr(ctx, a->rd); + TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs); + + tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); + gen_set_gpr(ctx, a->rd, rd); + + return true; +} + +/* + * Store with memop to indexed address. + * If !zext_offs, then address is rs1 + (rs2 << imm2). + * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static bool gen_store_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop, + bool zext_offs) +{ + TCGv data = get_gpr(ctx, a->rd, EXT_NONE); + TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs); + + tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); + + return true; +} + +static bool trans_th_lrd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_idx(ctx, a, MO_TESQ, false); +} + +static bool trans_th_lrw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TESL, false); +} + +static bool trans_th_lrwu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_idx(ctx, a, MO_TEUL, false); +} + +static bool trans_th_lrh(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TESW, false); +} + +static bool trans_th_lrhu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TEUW, false); +} + +static bool trans_th_lrb(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_SB, false); +} + +static bool trans_th_lrbu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_UB, false); +} + +static bool trans_th_srd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_store_idx(ctx, a, MO_TESQ, false); +} + +static bool trans_th_srw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_TESL, false); +} + +static bool trans_th_srh(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_TESW, false); +} + +static bool trans_th_srb(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_SB, false); +} +static bool trans_th_lurd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_idx(ctx, a, MO_TESQ, true); +} + +static bool trans_th_lurw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TESL, true); +} + +static bool trans_th_lurwu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_idx(ctx, a, MO_TEUL, true); +} + +static bool trans_th_lurh(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TESW, true); +} + +static bool trans_th_lurhu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TEUW, true); +} + +static bool trans_th_lurb(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_SB, true); +} + +static bool trans_th_lurbu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_UB, true); +} + +static bool trans_th_surd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_store_idx(ctx, a, MO_TESQ, true); +} + +static bool trans_th_surw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_TESL, true); +} + +static bool trans_th_surh(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_TESW, true); +} + +static bool trans_th_surb(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_SB, true); +} + /* XTheadMemPair */ static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f383e69db3..a979d43a6a 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -135,7 +135,8 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac || - ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempair || + ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ @@ -597,6 +598,24 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm) return addr; } +/* Compute a canonical address from a register plus reg offset. */ +static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) +{ + TCGv addr = temp_new(ctx); + TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); + + tcg_gen_add_tl(addr, src1, offs); + if (ctx->pm_mask_enabled) { + tcg_gen_andc_tl(addr, addr, pm_mask); + } else if (get_xl(ctx) == MXL_RV32) { + tcg_gen_ext32u_tl(addr, addr); + } + if (ctx->pm_base_enabled) { + tcg_gen_or_tl(addr, addr, pm_base); + } + return addr; +} + #ifndef CONFIG_USER_ONLY /* The states of mstatus_fs are: * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index ff2a83b56d..69e40f22dc 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -17,8 +17,10 @@ %rd2 20:5 %rs2 20:5 %sh5 20:5 +%imm5 20:s5 %sh6 20:6 %sh2 25:2 +%imm2 25:2 # Argument sets &r rd rs1 rs2 !extern @@ -26,6 +28,8 @@ &shift shamt rs1 rd !extern &th_bfext msb lsb rs1 rd &th_pair rd1 rs rd2 sh2 +&th_memidx rd rs1 rs2 imm2 +&th_meminc rd rs1 imm5 imm2 # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @@ -36,6 +40,8 @@ @sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd @sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd @th_pair ..... .. ..... ..... ... ..... ....... &th_pair %rd1 %rs %rd2 %sh2 +@th_memidx ..... .. ..... ..... ... ..... ....... &th_memidx %rd %rs1 %rs2 %imm2 +@th_meminc ..... .. ..... ..... ... ..... ....... &th_meminc %rd %rs1 %imm5 %imm2 # XTheadBa # Instead of defining a new encoding, we simply use the decoder to @@ -102,6 +108,54 @@ th_muls 00100 01 ..... ..... 001 ..... 0001011 @r th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r +# XTheadMemIdx +th_ldia 01111 .. ..... ..... 100 ..... 0001011 @th_meminc +th_ldib 01101 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lwia 01011 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lwib 01001 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lwuia 11011 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lwuib 11001 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lhia 00111 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lhib 00101 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lhuia 10111 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lhuib 10101 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lbia 00011 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lbib 00001 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lbuia 10011 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lbuib 10001 .. ..... ..... 100 ..... 0001011 @th_meminc +th_sdia 01111 .. ..... ..... 101 ..... 0001011 @th_meminc +th_sdib 01101 .. ..... ..... 101 ..... 0001011 @th_meminc +th_swia 01011 .. ..... ..... 101 ..... 0001011 @th_meminc +th_swib 01001 .. ..... ..... 101 ..... 0001011 @th_meminc +th_shia 00111 .. ..... ..... 101 ..... 0001011 @th_meminc +th_shib 00101 .. ..... ..... 101 ..... 0001011 @th_meminc +th_sbia 00011 .. ..... ..... 101 ..... 0001011 @th_meminc +th_sbib 00001 .. ..... ..... 101 ..... 0001011 @th_meminc + +th_lrd 01100 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrw 01000 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrwu 11000 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrh 00100 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrhu 10100 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrb 00000 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrbu 10000 .. ..... ..... 100 ..... 0001011 @th_memidx +th_srd 01100 .. ..... ..... 101 ..... 0001011 @th_memidx +th_srw 01000 .. ..... ..... 101 ..... 0001011 @th_memidx +th_srh 00100 .. ..... ..... 101 ..... 0001011 @th_memidx +th_srb 00000 .. ..... ..... 101 ..... 0001011 @th_memidx + +th_lurd 01110 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurw 01010 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurwu 11010 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurh 00110 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurhu 10110 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurb 00010 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurbu 10010 .. ..... ..... 100 ..... 0001011 @th_memidx +th_surd 01110 .. ..... ..... 101 ..... 0001011 @th_memidx +th_surw 01010 .. ..... ..... 101 ..... 0001011 @th_memidx +th_surh 00110 .. ..... ..... 101 ..... 0001011 @th_memidx +th_surb 00010 .. ..... ..... 101 ..... 0001011 @th_memidx + # XTheadMemPair th_ldd 11111 .. ..... ..... 100 ..... 0001011 @th_pair th_lwd 11100 .. ..... ..... 100 ..... 0001011 @th_pair -- 2.39.1 From MAILER-DAEMON Tue Jan 31 13:04:06 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMuzG-0000b5-GU for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id c17-20020adffb11000000b002bc8130cca7sm15453146wrr.23.2023.01.31.10.02.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 10:02:24 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v4 13/14] RISC-V: Adding XTheadFmv ISA extension Date: Tue, 31 Jan 2023 19:01:57 +0100 Message-Id: <20230131180158.2471047-14-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131180158.2471047-1-christoph.muellner@vrull.eu> References: <20230131180158.2471047-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 18:02:32 -0000 From: Christoph Müllner This patch adds support for the XTheadFmv ISA extension. The patch uses the T-Head specific decoder and translation. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 45 ++++++++++++++++++++++ target/riscv/translate.c | 6 +-- target/riscv/xthead.decode | 4 ++ 5 files changed, 55 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8cbc5c9c1b..0dd2f0c753 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -116,6 +116,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), + ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv), ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx), ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), @@ -1134,6 +1135,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), + DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 60478f4a9c..7128438d8e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -480,6 +480,7 @@ struct RISCVCPUConfig { bool ext_xtheadcmo; bool ext_xtheadcondmov; bool ext_xtheadfmemidx; + bool ext_xtheadfmv; bool ext_xtheadmac; bool ext_xtheadmemidx; bool ext_xtheadmempair; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index 0e77275457..5f327d1bdf 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -52,6 +52,12 @@ } \ } while (0) +#define REQUIRE_XTHEADFMV(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadfmv) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADMAC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadmac) { \ return false; \ @@ -449,6 +455,45 @@ static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a) return gen_fstore_idx(ctx, a, MO_TEUL, true); } +/* XTheadFmv */ + +static bool trans_th_fmv_hw_x(DisasContext *ctx, arg_th_fmv_hw_x *a) +{ + REQUIRE_XTHEADFMV(ctx); + REQUIRE_32BIT(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO); + TCGv_i64 t1 = tcg_temp_new_i64(); + + tcg_gen_extu_tl_i64(t1, src1); + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], t1, 32, 32); + tcg_temp_free_i64(t1); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_th_fmv_x_hw(DisasContext *ctx, arg_th_fmv_x_hw *a) +{ + REQUIRE_XTHEADFMV(ctx); + REQUIRE_32BIT(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + TCGv dst; + TCGv_i64 t1; + + dst = dest_gpr(ctx, a->rd); + t1 = tcg_temp_new_i64(); + + tcg_gen_extract_i64(t1, cpu_fpr[a->rs1], 32, 32); + tcg_gen_trunc_i64_tl(dst, t1); + gen_set_gpr(ctx, a->rd, dst); + tcg_temp_free_i64(t1); + mark_fs_dirty(ctx); + return true; +} + /* XTheadMac */ static bool gen_th_mac(DisasContext *ctx, arg_r *a, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 216eaf9d12..182649dcb6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -135,9 +135,9 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadcondmov || - ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadmac || - ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempair || - ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv || + ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx || + ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 81daf1d694..d1d104bcf2 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -110,6 +110,10 @@ th_fsrw 01000 .. ..... ..... 111 ..... 0001011 @th_memidx th_fsurd 01110 .. ..... ..... 111 ..... 0001011 @th_memidx th_fsurw 01010 .. ..... ..... 111 ..... 0001011 @th_memidx +# XTheadFmv +th_fmv_hw_x 1010000 00000 ..... 001 ..... 0001011 @r2 +th_fmv_x_hw 1100000 00000 ..... 001 ..... 0001011 @r2 + # XTheadMac th_mula 00100 00 ..... ..... 001 ..... 0001011 @r th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r -- 2.39.1 From MAILER-DAEMON Tue Jan 31 13:04:07 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMuzG-0000bn-Ro for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id c17-20020adffb11000000b002bc8130cca7sm15453146wrr.23.2023.01.31.10.02.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 10:02:22 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v4 12/14] RISC-V: Add initial support for T-Head C906 Date: Tue, 31 Jan 2023 19:01:56 +0100 Message-Id: <20230131180158.2471047-13-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131180158.2471047-1-christoph.muellner@vrull.eu> References: <20230131180158.2471047-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 18:02:32 -0000 From: Christoph Müllner This patch adds the T-Head C906 to the list of known CPUs. Selecting this CPUs will automatically enable the available ISA extensions of the CPUs (incl. vendor extensions). Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Drop C910 as it does not differ from C906 - Set priv version to 1.11 (new fmin/fmax behaviour) Changes in v3: - Removed setting dropped 'xtheadxmae' extension Changes in v4: - Inlcude cpu_vendorid.h in cpu.c instead cpu.h target/riscv/cpu.c | 31 +++++++++++++++++++++++++++++++ target/riscv/cpu.h | 1 + target/riscv/cpu_vendorid.h | 6 ++++++ 3 files changed, 38 insertions(+) create mode 100644 target/riscv/cpu_vendorid.h diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3078556f1b..8cbc5c9c1b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -22,6 +22,7 @@ #include "qemu/ctype.h" #include "qemu/log.h" #include "cpu.h" +#include "cpu_vendorid.h" #include "pmu.h" #include "internals.h" #include "time_helper.h" @@ -281,6 +282,35 @@ static void rv64_sifive_e_cpu_init(Object *obj) cpu->cfg.mmu = false; } +static void rv64_thead_c906_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_priv_version(env, PRIV_VERSION_1_11_0); + + cpu->cfg.ext_g = true; + cpu->cfg.ext_c = true; + cpu->cfg.ext_u = true; + cpu->cfg.ext_s = true; + cpu->cfg.ext_icsr = true; + cpu->cfg.ext_zfh = true; + cpu->cfg.mmu = true; + cpu->cfg.ext_xtheadba = true; + cpu->cfg.ext_xtheadbb = true; + cpu->cfg.ext_xtheadbs = true; + cpu->cfg.ext_xtheadcmo = true; + cpu->cfg.ext_xtheadcondmov = true; + cpu->cfg.ext_xtheadfmemidx = true; + cpu->cfg.ext_xtheadmac = true; + cpu->cfg.ext_xtheadmemidx = true; + cpu->cfg.ext_xtheadmempair = true; + cpu->cfg.ext_xtheadsync = true; + + cpu->cfg.mvendorid = THEAD_VENDOR_ID; +} + static void rv128_base_cpu_init(Object *obj) { if (qemu_tcg_mttcg_enabled()) { @@ -1371,6 +1401,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), #endif }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5cc3011529..60478f4a9c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -53,6 +53,7 @@ #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") #if defined(TARGET_RISCV32) diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h new file mode 100644 index 0000000000..a5aa249bc9 --- /dev/null +++ b/target/riscv/cpu_vendorid.h @@ -0,0 +1,6 @@ +#ifndef TARGET_RISCV_CPU_VENDORID_H +#define TARGET_RISCV_CPU_VENDORID_H + +#define THEAD_VENDOR_ID 0x5b7 + +#endif /* TARGET_RISCV_CPU_VENDORID_H */ -- 2.39.1 From MAILER-DAEMON Tue Jan 31 13:03:58 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMuz8-0000Ct-CP for mharc-qemu-riscv@gnu.org; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=christoph.muellner@vrull.eu; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 18:02:16 -0000 X-List-Received-Date: Tue, 31 Jan 2023 18:02:16 -0000 On Tue, Jan 24, 2023 at 9:44 PM Richard Henderson wrote: > > On 1/24/23 09:59, Christoph Muellner wrote: > > +static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop, > > + int shamt) > > +{ > > + TCGv rd1 = dest_gpr(ctx, a->rd1); > > + TCGv rd2 = dest_gpr(ctx, a->rd2); > > + TCGv addr1 = tcg_temp_new(); > > + TCGv addr2 = tcg_temp_new(); > > + > > + addr1 = get_address(ctx, a->rs, a->sh2 << shamt); > > + if ((memop & MO_SIZE) == MO_64) { > > + addr2 = get_address(ctx, a->rs, 8 + (a->sh2 << shamt)); > > + } else { > > + addr2 = get_address(ctx, a->rs, 4 + (a->sh2 << shamt)); > > + } > > + > > + tcg_gen_qemu_ld_tl(rd1, addr1, ctx->mem_idx, memop); > > + tcg_gen_qemu_ld_tl(rd2, addr2, ctx->mem_idx, memop); > > + gen_set_gpr(ctx, a->rd1, rd1); > > + gen_set_gpr(ctx, a->rd2, rd2); > > Since dest_gpr may return cpu_gpr[n], this may update the rd1 before recognizing the > exception that the second load may generate. Is that correct? Solved in v4 by using temporaries. > > The manual says that rd1, rd2, and rs1 must not be the same, but you do not check this. Fixed in v4. Thank you! > > > r~ From MAILER-DAEMON Tue Jan 31 13:04:09 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMuzI-0000jL-Lk for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 13:04:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMuxc-0007Ix-1P for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 13:02:29 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMuxa-0000oQ-4q for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 13:02:23 -0500 Received: by mail-wr1-x433.google.com with SMTP id q10so15026388wrm.4 for ; Tue, 31 Jan 2023 10:02:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pWqiQmxEYgFVykkitVPcIYmqXWBkHI2uvRpg+RKj4QY=; b=eGB7MYtSy5s/HhKkBrWNWIKOOHCqJqZMAage2/woJ32Rk7kyYuU0tO82mHLSYPWwq9 c4Os2VBG1krk8J6OQpfwgdd+yCp3I08eKzH+hltxtKeYpFEeVYlLnEjRoqi/d5oIWBGY +6tRtu/DVP+J+JFTIubeqMXav+j2wJMmjTEFwzfYpo+jhfiMWtWB9FP6je5Y9UNbwT0j uVeKxZggOtpfaGNGyuzTSD9FbZ6X9TtrHT51FaecQBcRD1iEqYLZNg3tSSRCL80hCkd3 LsjHUGmYAWpfb+pKopm3jyDKvRJKgw0uKfiME6PcYmKwBH3sPUO3FTkyj3kjzLc6vLG2 nYnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pWqiQmxEYgFVykkitVPcIYmqXWBkHI2uvRpg+RKj4QY=; b=NyB2Zp1JkjmRLvfBuv8P8nTgvY/bVfxf141t8kRNW/tnuA06VHfIInI9piJIzDWUDX EjFP4pbKSgFE4Srflmq7G/aMgNIK3gePdoeWyw6Q6zKwRhAttp3tXoeDxXM7rjPUyGU7 c95bF/HpxxB0n08FNn77zwinSvqt9r8Fab5YXyFIUIcf1GHzPk0jti2s7q8a9ostxh3X CNUY5nqFpHyu+HEeUlFMfWebwzjukQFHGYJpZgEnKfbbJC0FzId2LpWklDd2bsSi1twW NLWgowkTQk8W3dO/5I5GNeG0HPxIA80zkPiXFJq7ymOI6Mbxo1lZBx/KHs9Qx/O1P2YU ++Cg== X-Gm-Message-State: AO0yUKUwNfytXEeRB5bKd4OVZRYl6kdm9H0FxqdjXZZNSxGuRmwETA9i gKOHKEmWpnCLx67FH7/1dHGAW7CQN+utokbV X-Google-Smtp-Source: AK7set/Ch/tLGffDEr5/Voz80QtXvlztn9B/jcPclTyY01rfLfEIA4yEWOLpP4RVOs7SxZEZ0RQmRg== X-Received: by 2002:a05:6000:184a:b0:2bd:fb81:6317 with SMTP id c10-20020a056000184a00b002bdfb816317mr63887wri.33.1675188140857; Tue, 31 Jan 2023 10:02:20 -0800 (PST) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id c17-20020adffb11000000b002bc8130cca7sm15453146wrr.23.2023.01.31.10.02.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 10:02:20 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v4 10/14] RISC-V: Adding T-Head FMemIdx extension Date: Tue, 31 Jan 2023 19:01:54 +0100 Message-Id: <20230131180158.2471047-11-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131180158.2471047-1-christoph.muellner@vrull.eu> References: <20230131180158.2471047-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 18:02:31 -0000 X-List-Received-Date: Tue, 31 Jan 2023 18:02:31 -0000 From: Christoph Müllner This patch adds support for the T-Head FMemIdx instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions - Use get_th_address_indexed for address calculations target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 108 +++++++++++++++++++++ target/riscv/translate.c | 3 +- target/riscv/xthead.decode | 10 ++ 5 files changed, 123 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2d5a0881f1..5679e2cb83 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), + ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx), ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), @@ -1102,6 +1103,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), + DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d776fea760..5cc3011529 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -478,6 +478,7 @@ struct RISCVCPUConfig { bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadcondmov; + bool ext_xtheadfmemidx; bool ext_xtheadmac; bool ext_xtheadmemidx; bool ext_xtheadmempair; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index 4f56032903..0e77275457 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -46,6 +46,12 @@ } \ } while (0) +#define REQUIRE_XTHEADFMEMIDX(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadfmemidx) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADMAC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadmac) { \ return false; \ @@ -341,6 +347,108 @@ static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a) return gen_th_condmove(ctx, a, TCG_COND_NE); } +/* XTheadFMem */ + +/* + * Load 64-bit float from indexed address. + * If !zext_offs, then address is rs1 + (rs2 << imm2). + * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static bool gen_fload_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop, + bool zext_offs) +{ + TCGv_i64 rd = cpu_fpr[a->rd]; + TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs); + + tcg_gen_qemu_ld_i64(rd, addr, ctx->mem_idx, memop); + if ((memop & MO_SIZE) == MO_32) { + gen_nanbox_s(rd, rd); + } + + mark_fs_dirty(ctx); + return true; +} + +/* + * Store 64-bit float to indexed address. + * If !zext_offs, then address is rs1 + (rs2 << imm2). + * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static bool gen_fstore_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop, + bool zext_offs) +{ + TCGv_i64 rd = cpu_fpr[a->rd]; + TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs); + + tcg_gen_qemu_st_i64(rd, addr, ctx->mem_idx, memop); + + return true; +} + +static bool trans_th_flrd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + return gen_fload_idx(ctx, a, MO_TEUQ, false); +} + +static bool trans_th_flrw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + return gen_fload_idx(ctx, a, MO_TEUL, false); +} + +static bool trans_th_flurd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + return gen_fload_idx(ctx, a, MO_TEUQ, true); +} + +static bool trans_th_flurw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + return gen_fload_idx(ctx, a, MO_TEUL, true); +} + +static bool trans_th_fsrd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + return gen_fstore_idx(ctx, a, MO_TEUQ, false); +} + +static bool trans_th_fsrw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + return gen_fstore_idx(ctx, a, MO_TEUL, false); +} + +static bool trans_th_fsurd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + return gen_fstore_idx(ctx, a, MO_TEUQ, true); +} + +static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + return gen_fstore_idx(ctx, a, MO_TEUL, true); +} + /* XTheadMac */ static bool gen_th_mac(DisasContext *ctx, arg_r *a, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a979d43a6a..216eaf9d12 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -134,7 +134,8 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || - ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac || + ctx->cfg_ptr->ext_xtheadcondmov || + ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; } diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 69e40f22dc..81daf1d694 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -100,6 +100,16 @@ th_l2cache_iall 0000000 10110 00000 000 00000 0001011 th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r +# XTheadFMemIdx +th_flrd 01100 .. ..... ..... 110 ..... 0001011 @th_memidx +th_flrw 01000 .. ..... ..... 110 ..... 0001011 @th_memidx +th_flurd 01110 .. ..... ..... 110 ..... 0001011 @th_memidx +th_flurw 01010 .. ..... ..... 110 ..... 0001011 @th_memidx +th_fsrd 01100 .. ..... ..... 111 ..... 0001011 @th_memidx +th_fsrw 01000 .. ..... ..... 111 ..... 0001011 @th_memidx +th_fsurd 01110 .. ..... ..... 111 ..... 0001011 @th_memidx +th_fsurw 01010 .. ..... ..... 111 ..... 0001011 @th_memidx + # XTheadMac th_mula 00100 00 ..... ..... 001 ..... 0001011 @r th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r -- 2.39.1 From MAILER-DAEMON Tue Jan 31 13:04:09 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMuzJ-0000k4-8J for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id c17-20020adffb11000000b002bc8130cca7sm15453146wrr.23.2023.01.31.10.02.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 10:02:21 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v4 11/14] RISC-V: Set minimum priv version for Zfh to 1.11 Date: Tue, 31 Jan 2023 19:01:55 +0100 Message-Id: <20230131180158.2471047-12-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131180158.2471047-1-christoph.muellner@vrull.eu> References: <20230131180158.2471047-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 18:02:32 -0000 From: Christoph Müllner There are no differences for floating point instructions in priv version 1.11 and 1.12. There is also no dependency for Zfh to priv version 1.12. Therefore allow Zfh to be enabled for priv version 1.11. Acked-by: Alistair Francis Signed-off-by: Christoph Müllner --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5679e2cb83..3078556f1b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -77,7 +77,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), - ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), + ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh), ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), -- 2.39.1 From MAILER-DAEMON Tue Jan 31 13:04:08 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMuzI-0000hB-2q for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 13:04:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMuxZ-0007Ht-UD for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 13:02:24 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMuxX-0000qC-VW for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 13:02:21 -0500 Received: by mail-wr1-x432.google.com with SMTP id t7so6663820wrp.5 for ; Tue, 31 Jan 2023 10:02:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+v+3DzugFhYK9QbvpJ4xOXwLupsOh+txSzLTfWODoL0=; b=PEbo8btA/GXpJPvsef4XTldgVi9pk/aeIP8ZsUSrfGdOMBwSOlVmL8hE6vGJVyPHI1 J2s/UszCygixxaV1sRfbU2f1JfkIApx/ORlPTSEPQMHDl/0+68mDe+1mGhjw/fPSHnBY K7e6CBpiqTlVtQLblJjkNghFbkiNpFw7hsuaPzAq3T6+pFpCgooM0FIQeVV71PlxZ+Un hbeioHtVRs9kvtYYOUOjnvHvtGKOevuR1eCPhyLYzC9C13epvyEdrCMrk+L+E4w4rTav /yt0xwLmKkXnTyT/L3j4T1lZV0D7R36BhynOOYaNarOw7agGt1y4UC2k35rrXByqi+eD bdKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+v+3DzugFhYK9QbvpJ4xOXwLupsOh+txSzLTfWODoL0=; b=3JQzeyMnXXOhHlp3kOaqNdA1yBiSMQWqoQG9O7C/lv22P8W93c3lFM5lLiskyblL+H 5++p2nCNw0ap7/j/ZMeXnPVmflJA+FZ5bW/Mj/X8jzH69djQP6Z2TlICyV0C6JFc6lOr B+hhQqTtXgnmQxx9/DIJY4V7g1CTI+7mkK9MhhwtrtfpGFSQpHHx7poNN6kYgb539M9u qMhdp25rEhRNCLlWOhyO8V53lj1k65NiBqtztHvDiwNnibTIu3Dcopb600NtvcK40Pk/ NmKOVqoLQbrDrusBy45XgRm7UbMCGgfXEkB7q+HNGVAqavvhJVGPKQxGvOJZk/gupvdy Dp/A== X-Gm-Message-State: AO0yUKVxrae3F9BwmxFF5xd+1rx7NeZPwTSvZrMF6cpwkjaRy9X19e4X hQDzIrjevcN3RIA72gDhUNLxz6Evt3x8iNtp X-Google-Smtp-Source: AK7set8V2jSdI4yUEVKZDA4JBFmJYGrpnPd+FqaasvXibOEtklkgfSdT2kMgBKAn6fVdvfS3Kd+kJQ== X-Received: by 2002:adf:dbc3:0:b0:2bf:eb0e:cccc with SMTP id e3-20020adfdbc3000000b002bfeb0eccccmr8130168wrj.43.1675188137794; Tue, 31 Jan 2023 10:02:17 -0800 (PST) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id c17-20020adffb11000000b002bc8130cca7sm15453146wrr.23.2023.01.31.10.02.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 10:02:17 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v4 08/14] RISC-V: Adding T-Head MemPair extension Date: Tue, 31 Jan 2023 19:01:52 +0100 Message-Id: <20230131180158.2471047-9-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131180158.2471047-1-christoph.muellner@vrull.eu> References: <20230131180158.2471047-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 18:02:30 -0000 X-List-Received-Date: Tue, 31 Jan 2023 18:02:30 -0000 From: Christoph Müllner This patch adds support for the T-Head MemPair instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions - Use get_address() to calculate addresses Changes in v4: - Don't translate in case of overlapping registers - Use temporaries to avoid unexpected behaviour in case of exceptions - There have also been clarifications in the specification target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 98 ++++++++++++++++++++++ target/riscv/translate.c | 2 +- target/riscv/xthead.decode | 13 +++ 5 files changed, 115 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 88da4de14d..b7047d139d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -115,6 +115,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), + ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), }; @@ -1101,6 +1102,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), + DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 830b20558c..38e80d44d5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -479,6 +479,7 @@ struct RISCVCPUConfig { bool ext_xtheadcmo; bool ext_xtheadcondmov; bool ext_xtheadmac; + bool ext_xtheadmempair; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index 31a4034927..059c6529f3 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -52,6 +52,12 @@ } \ } while (0) +#define REQUIRE_XTHEADMEMPAIR(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadmempair) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADSYNC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadsync) { \ return false; \ @@ -382,6 +388,98 @@ static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a) return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); } +/* XTheadMemPair */ + +static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop, + int shamt) +{ + if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) { + return false; + } + + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + TCGv addr1 = tcg_temp_new(); + TCGv addr2 = tcg_temp_new(); + + addr1 = get_address(ctx, a->rs, a->sh2 << shamt); + if ((memop & MO_SIZE) == MO_64) { + addr2 = get_address(ctx, a->rs, 8 + (a->sh2 << shamt)); + } else { + addr2 = get_address(ctx, a->rs, 4 + (a->sh2 << shamt)); + } + + tcg_gen_qemu_ld_tl(t1, addr1, ctx->mem_idx, memop); + tcg_gen_qemu_ld_tl(t2, addr2, ctx->mem_idx, memop); + gen_set_gpr(ctx, a->rd1, t1); + gen_set_gpr(ctx, a->rd2, t2); + + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(addr1); + tcg_temp_free(addr2); + return true; +} + +static bool trans_th_ldd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + REQUIRE_64BIT(ctx); + return gen_loadpair_tl(ctx, a, MO_TESQ, 4); +} + +static bool trans_th_lwd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + return gen_loadpair_tl(ctx, a, MO_TESL, 3); +} + +static bool trans_th_lwud(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + return gen_loadpair_tl(ctx, a, MO_TEUL, 3); +} + +static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop, + int shamt) +{ + if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) { + return false; + } + + TCGv data1 = get_gpr(ctx, a->rd1, EXT_NONE); + TCGv data2 = get_gpr(ctx, a->rd2, EXT_NONE); + TCGv addr1 = tcg_temp_new(); + TCGv addr2 = tcg_temp_new(); + + addr1 = get_address(ctx, a->rs, a->sh2 << shamt); + if ((memop & MO_SIZE) == MO_64) { + addr2 = get_address(ctx, a->rs, 8 + (a->sh2 << shamt)); + } else { + addr2 = get_address(ctx, a->rs, 4 + (a->sh2 << shamt)); + } + + tcg_gen_qemu_st_tl(data1, addr1, ctx->mem_idx, memop); + tcg_gen_qemu_st_tl(data2, addr2, ctx->mem_idx, memop); + + tcg_temp_free(addr1); + tcg_temp_free(addr2); + return true; +} + +static bool trans_th_sdd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + REQUIRE_64BIT(ctx); + return gen_storepair_tl(ctx, a, MO_TESQ, 4); +} + +static bool trans_th_swd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + return gen_storepair_tl(ctx, a, MO_TESL, 3); +} + /* XTheadSync */ static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e5a57a8516..f383e69db3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -135,7 +135,7 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac || - ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 696de6cecf..ff2a83b56d 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -11,16 +11,21 @@ # Fields: %rd 7:5 +%rd1 7:5 +%rs 15:5 %rs1 15:5 +%rd2 20:5 %rs2 20:5 %sh5 20:5 %sh6 20:6 +%sh2 25:2 # Argument sets &r rd rs1 rs2 !extern &r2 rd rs1 !extern &shift shamt rs1 rd !extern &th_bfext msb lsb rs1 rd +&th_pair rd1 rs rd2 sh2 # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @@ -30,6 +35,7 @@ @th_bfext msb:6 lsb:6 ..... ... ..... ....... &th_bfext %rs1 %rd @sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd @sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd +@th_pair ..... .. ..... ..... ... ..... ....... &th_pair %rd1 %rs %rd2 %sh2 # XTheadBa # Instead of defining a new encoding, we simply use the decoder to @@ -96,6 +102,13 @@ th_muls 00100 01 ..... ..... 001 ..... 0001011 @r th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r +# XTheadMemPair +th_ldd 11111 .. ..... ..... 100 ..... 0001011 @th_pair +th_lwd 11100 .. ..... ..... 100 ..... 0001011 @th_pair +th_lwud 11110 .. ..... ..... 100 ..... 0001011 @th_pair +th_sdd 11111 .. ..... ..... 101 ..... 0001011 @th_pair +th_swd 11100 .. ..... ..... 101 ..... 0001011 @th_pair + # XTheadSync th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s th_sync 0000000 11000 00000 000 00000 0001011 -- 2.39.1 From MAILER-DAEMON Tue Jan 31 13:23:28 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMvI0-0004p0-QI for mharc-qemu-riscv@gnu.org; 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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id w127-20020a628285000000b005939fe1719fsm6278982pfd.39.2023.01.31.10.23.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 31 Jan 2023 10:23:23 -0800 (PST) Message-ID: <1cf43062-1e18-b7aa-8c85-f1b0afe27708@linaro.org> Date: Tue, 31 Jan 2023 08:23:19 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH v4 08/14] RISC-V: Adding T-Head MemPair extension Content-Language: en-US To: Christoph Muellner , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=c3=bcbner?= , Palmer Dabbelt , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu References: <20230131180158.2471047-1-christoph.muellner@vrull.eu> <20230131180158.2471047-9-christoph.muellner@vrull.eu> From: Richard Henderson In-Reply-To: <20230131180158.2471047-9-christoph.muellner@vrull.eu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 18:23:27 -0000 On 1/31/23 08:01, Christoph Muellner wrote: > + if ((memop & MO_SIZE) == MO_64) { > + addr2 = get_address(ctx, a->rs, 8 + (a->sh2 << shamt)); > + } else { > + addr2 = get_address(ctx, a->rs, 4 + (a->sh2 << shamt)); > + } Use memop_size(memop) instead. Otherwise, Reviewed-by: Richard Henderson r~ From MAILER-DAEMON Tue Jan 31 15:10:18 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMwxO-00051x-M7 for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 15:10:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMwxL-00051O-Na for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 15:10:15 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMwxJ-0000yh-E8 for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 15:10:15 -0500 Received: by mail-wm1-x334.google.com with SMTP id m5-20020a05600c4f4500b003db03b2559eso11531706wmq.5 for ; Tue, 31 Jan 2023 12:10:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:from:to:cc:subject:date:message-id:reply-to; bh=374h9EgviB07TZ//uSp3PBuOnSQUohPKvT41Rszmal0=; b=leA9Ml4uGQn0XdlMA1Kp+XZJxMyJ+oJHmcyyFTqPAQiMAYAbSbj8rq9Fxp2n7Lb6jY rGgpqRqDJz5Y2Jdhl0ulc46A7gq+jdyXWDl20xhLj1NqdcgiWemfqahcQ8OvTKAbekO7 z0+/IkCR9moo/qcjZLGzHpOTAikeaY4OxQz0WDZqD9qw9Yvt8YeNcJojZOYT4i3WNk8X H1PiTw8NT4S9FeTlkkP5yOp7pIWpegAg95SAz9m3/2CuZfkBd3eWQNV35uByTYhiyiov MJnaefCpmUA+Ih41s8+f9uYoXSJZe5Rg58Pv6PATkfP4YSH5ts9QMzMqyCxDBQ3F7iTz lsFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=374h9EgviB07TZ//uSp3PBuOnSQUohPKvT41Rszmal0=; b=rsKxL/CTS4OX9KdTv7q0sn1vha3gkeRz5tMsmhnnMO+588EhKTVYXk6/MZbkV2UaPx 292rUQiIoItG7XynczkiKqe1fyEcqLbRCvhupRlOXbJKnaxTRXi9j3rDmZ0DsgWJ9fmS aCivpSzebvkqC0aIuUBfOiAwSAzaFcpMvx+Lupzc9jk65cBGdHScungv0mZ+JJLQC1Bb VkmToaEfuS599JtE3BOOoIIhA3Tu8+JL4Lf6z9ywy0Qh94dKkAihl1QKENqG62HxU0Et cXrV94typZaILYLWlSq50FeWTuxtQm4E/EyjPvrJF55MZtewi0N6VJL7Bv0ZB1oPJ0Do Hk1A== X-Gm-Message-State: AFqh2kosIoWAj/1wWmi+atzJxA42GvxWfL0oS2Wpjz5QZewBjfzGVLlm pXIQ1rbW2ET9vxrXGakxvR3fBHdSt4TCW438pYYbSw== X-Google-Smtp-Source: AMrXdXtdrKtspysonVQI8QcHaopj4bQfALxzaTVRER5vnllS6Fz2rc9CwVXfs5/G6CEo3Tdon3kr4g2Oyg6cDlSfeJI= X-Received: by 2002:a05:600c:358e:b0:3d0:1489:78c4 with SMTP id p14-20020a05600c358e00b003d0148978c4mr3400814wmq.167.1675195811270; Tue, 31 Jan 2023 12:10:11 -0800 (PST) MIME-Version: 1.0 References: <20230131180158.2471047-1-christoph.muellner@vrull.eu> <20230131180158.2471047-9-christoph.muellner@vrull.eu> <1cf43062-1e18-b7aa-8c85-f1b0afe27708@linaro.org> In-Reply-To: <1cf43062-1e18-b7aa-8c85-f1b0afe27708@linaro.org> From: =?UTF-8?Q?Christoph_M=C3=BCllner?= Date: Tue, 31 Jan 2023 21:09:58 +0100 Message-ID: Subject: Re: [PATCH v4 08/14] RISC-V: Adding T-Head MemPair extension To: Richard Henderson Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?Q?Heiko_St=C3=BCbner?= , Palmer Dabbelt , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=christoph.muellner@vrull.eu; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 20:10:16 -0000 On Tue, Jan 31, 2023 at 7:23 PM Richard Henderson wrote: > > On 1/31/23 08:01, Christoph Muellner wrote: > > + if ((memop & MO_SIZE) == MO_64) { > > + addr2 = get_address(ctx, a->rs, 8 + (a->sh2 << shamt)); > > + } else { > > + addr2 = get_address(ctx, a->rs, 4 + (a->sh2 << shamt)); > > + } > > Use memop_size(memop) instead. Will be part of v5 (will be sent in a couple of minutes). I have also added a "int imm = a->sh2 << shamt;". > > Otherwise, > Reviewed-by: Richard Henderson Thanks for the review! > > > r~ From MAILER-DAEMON Tue Jan 31 15:20:23 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMx79-0006kD-L9 for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 15:20:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMx78-0006jg-BN for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 15:20:22 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMx75-0002i2-Rq for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 15:20:21 -0500 Received: by mail-wr1-x434.google.com with SMTP id t18so15381862wro.1 for ; Tue, 31 Jan 2023 12:20:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=9lo2K6GQSn2b50esA2/wF8fWoSdV5uNQzm7zIK6gS7A=; b=N0o1V+d9l/rFdInUTnB/gVGHS5U1OU9v4E1C/i2OmVmlw/pAwgDdjI7otUNQ8wT5tH KbEFSl+ngJ8b8leINdy3o49lCfZzAdQnkJ0ThOzFmHrgiVQ1ouVZxJuMNQiTkeCDUL0T qOcbemp5jQ0fI7Oy28CGj1U5NrJjHkZzbHZoIUevSEtq/HCk6Z0pVRoYAk028hk00qLx L4uuD9Iuo3EhqSW28Jt4ksirEpMMmU/LHPKMz73vNn4GoaXvcEKJ/deyoOOWgSeOmB2U BZXEUCbIEl5hpLIS6ZYJqxNBpW4hOi9hFcK+2Bkbmeb+jsJcu27hS43VUmUsTxeWwujU 4KnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=9lo2K6GQSn2b50esA2/wF8fWoSdV5uNQzm7zIK6gS7A=; b=emMMV/o0eQKP2lMhGALyZkiI1htdLVWub+08MBrg+fllpLjSomS8tkXo57C+vYM5GQ 6hpD8GcfHw1CtlbukJam3Xdr4osnvF82x1tLoKVK0j+QFMusNHcs8ypMst616ByPTbgg Fk2AUDRRsZVikfULQz1sblzRMqukzQscnwx5ieYX99pKGxa73/xURyZPStn6+NSr0vey tQg2+iDJKdEJAbzKkggm5VNvHOWy/W1L302Y7hye6KcBFTpHR+3mJLagiWF7v+udOMD0 ++J9Lgr9UAwsgRcy0l9b82CiP4rwN02NjEjl1seEnGnC0kMfbmvEdrRGCdLB2iYNEVBt oV9A== X-Gm-Message-State: AO0yUKU1AJZgNrzBjMq2fuJm42JBPKZ04w5r+vinOijRB9Oho7lOMG1w 4kmlb1rtW1t6HtSNyPIZuhMAQ8eIj62FaiEn X-Google-Smtp-Source: AK7set8/gJH9TBdlmv9Sn+CMed9Jfew4Op53Qk6INDv4ykz6JFEf5RYzw5eF7wdILFuk6bPa7fChQA== X-Received: by 2002:a5d:6645:0:b0:2bd:ee0c:26a3 with SMTP id f5-20020a5d6645000000b002bdee0c26a3mr4133292wrw.8.1675196416488; Tue, 31 Jan 2023 12:20:16 -0800 (PST) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:15 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 00/14] Add support for the T-Head vendor extensions Date: Tue, 31 Jan 2023 21:19:59 +0100 Message-Id: <20230131202013.2541053-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 20:20:22 -0000 From: Christoph Müllner This series introduces support for the T-Head vendor extensions, which are implemented e.g. in the XuanTie C906 and XuanTie C910: * XTheadBa * XTheadBb * XTheadBs * XTheadCmo * XTheadCondMov * XTheadFMemIdx * XTheadFmv * XTheadMac * XTheadMemIdx * XTheadMemPair * XTheadSync The xthead* extensions are documented here: https://github.com/T-head-Semi/thead-extension-spec/releases/latest The "th." instruction prefix prevents future conflicts with standard extensions and has been documentented in the RISC-V toolchain conventions: https://github.com/riscv-non-isa/riscv-toolchain-conventions Note, that the T-Head vendor extensions do not contain all vendor-specific functionality of the T-Head SoCs (e.g. no vendor-specific CSRs are included). Instead the extensions cover coherent functionality, that is exposed to S and U mode. To enable the extensions above, the following two methods are possible: * add the extension to the arch string E.g. QEMU_CPU="any,xtheadcmo=true,xtheadsync=true" * implicitly select the extensions via CPU selection E.g. QEMU_CPU="thead-c906" Major changes in v2: - Add ISA_EXT_DATA_ENTRY()s - Use single decoder for XThead extensions - Simplify a lot of translation functions - Fix RV32 behaviour - Added XTheadFmv - Addressed all comments of v1 Major changes in v3: - Drop XMAE patch - Rename priv level test macros Changes in v4: - Address review comments from Richard Henderson Changes in v5: - Remove hard coded constants from gen_*pair_tl() Christoph Müllner (14): RISC-V: Adding XTheadCmo ISA extension RISC-V: Adding XTheadSync ISA extension RISC-V: Adding XTheadBa ISA extension RISC-V: Adding XTheadBb ISA extension RISC-V: Adding XTheadBs ISA extension RISC-V: Adding XTheadCondMov ISA extension RISC-V: Adding T-Head multiply-accumulate instructions RISC-V: Adding T-Head MemPair extension RISC-V: Adding T-Head MemIdx extension RISC-V: Adding T-Head FMemIdx extension RISC-V: Set minimum priv version for Zfh to 1.11 RISC-V: Add initial support for T-Head C906 RISC-V: Adding XTheadFmv ISA extension target/riscv: add a MAINTAINERS entry for XThead* extension support MAINTAINERS | 8 + target/riscv/cpu.c | 55 +- target/riscv/cpu.h | 12 + target/riscv/cpu_vendorid.h | 6 + target/riscv/helper.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 1094 ++++++++++++++++++++ target/riscv/meson.build | 1 + target/riscv/op_helper.c | 6 + target/riscv/translate.c | 31 + target/riscv/xthead.decode | 185 ++++ 10 files changed, 1398 insertions(+), 1 deletion(-) create mode 100644 target/riscv/cpu_vendorid.h create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc create mode 100644 target/riscv/xthead.decode -- 2.39.1 From MAILER-DAEMON Tue Jan 31 15:20:25 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMx7B-0006lQ-Pv for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 15:20:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMx7A-0006kd-5o for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 15:20:24 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMx76-0002io-C3 for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 15:20:23 -0500 Received: by mail-wr1-x435.google.com with SMTP id m7so15349084wru.8 for ; Tue, 31 Jan 2023 12:20:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UIMc0yh6nW6tPabnRz0gkGn0xHCplcfPWfd18Srv1EY=; b=QYn/YpvVHYyT1BPfyo8SQiVCWbAYXVm8uWeS6/ZFJ6GEl6EtopkvGXzz/YHyA5ck1K xg5KNWajEATBB+pThWirLHedtO8moMYAHypOKRkNFUOA87gbz3XqXPjKOIJteqIV8gjT wnLFL7BPdpRgXynhKzChnT9GoM7vToLmY2jxgJT2eaHFjVfFEsgUF32vshSPaRsrSkxk cMgZFqUXkXNa+yi41up9AnGGS4es8Z/B/y/eCsqFSVBGjo3zbbGs6tnStSnVHM/OZ48C J4vtkoNkRMxuD27wQk95K6KAk2qSViyvEV3spv8CBbUS3MqMTBgSXe4jq0PLlse5/aTb A0pw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UIMc0yh6nW6tPabnRz0gkGn0xHCplcfPWfd18Srv1EY=; b=8RWVMxKEdzImQMwAKkkDpCF7ZwyNJP3LqO8CijMoeGfPWpQBlbgzXwX4nBc9R+GOf0 xWjC8NneHJE0iHwFrIPeFOzUH5vqhDSYu/xBQZ8Ui1IIBo9Yr+W3a9v52zqRvKeYORH9 VDlYwaI7XK6JKRlZQHkjF2BqFZrqN1esEikI8MRX2H1PAw2DY31e9+5yjl5bay73O7IO MV5/qfk4s4gA3wjuDRRj/3rMACSFFBrLJzR+sJQt71eHEMtDdqPspEdcCW533ZL5gPvW wZOg/1kDM7P9akXGBc3Z5eMu+vum5SR8f7a2BabjTjpmk5TZhsByK/coIrvysl8/35At AKwQ== X-Gm-Message-State: AO0yUKXouo3Zfy1XyT0ijIBwfD8UOOctKrox5pxD2xt10y3mCNENwEjS HzYHHdwYiaJBD6wwhwpo6joSRmeGT5dV/3ce X-Google-Smtp-Source: AK7set9+rnZw3lr7AAR8L5ga+c1w2grYjWW83nXaonox5qjASLBXL20HLGKBsRohM/ydVx+bD+D+kQ== X-Received: by 2002:a5d:5958:0:b0:2bf:ee58:72ae with SMTP id e24-20020a5d5958000000b002bfee5872aemr239811wri.50.1675196418407; Tue, 31 Jan 2023 12:20:18 -0800 (PST) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:17 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 01/14] RISC-V: Adding XTheadCmo ISA extension Date: Tue, 31 Jan 2023 21:20:00 +0100 Message-Id: <20230131202013.2541053-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 20:20:24 -0000 From: Christoph Müllner This patch adds support for the XTheadCmo ISA extension. To avoid interfering with standard extensions, decoder and translation are in its own xthead* specific files. Future patches should be able to easily add additional T-Head extension. The implementation does not have much functionality (besides accepting the instructions and not qualifying them as illegal instructions if the hart executes in the required privilege level for the instruction), as QEMU does not model CPU caches and instructions are documented to not raise any exceptions. Co-developed-by: LIU Zhiwei Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Explicit test for PRV_U - Encapsule access to env-priv in inline function - Use single decoder for XThead extensions Changes in v3: - Appling mask TB_FLAGS_PRIV_MMU_MASK to use of ctx->mem_idx - Removing code from test macro REQUIRE_PRIV_MSU() - Removing PRV_H from test macro REQUIRE_PRIV_MS() - Remove unrelated clean-up - Reorder decoder includes Changes in v4: - Reorder decoder includes target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 81 ++++++++++++++++++++++ target/riscv/meson.build | 1 + target/riscv/translate.c | 8 +++ target/riscv/xthead.decode | 38 ++++++++++ 6 files changed, 131 insertions(+) create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc create mode 100644 target/riscv/xthead.decode diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 14a7027095..6ea61e5b22 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -109,6 +109,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), }; @@ -1088,6 +1089,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), /* Vendor-specific custom extensions */ + DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), /* These are experimental so mark with 'x-' */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bcf0826753..d3ebc6f112 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -473,6 +473,7 @@ struct RISCVCPUConfig { uint64_t mimpid; /* Vendor-specific custom extensions */ + bool ext_xtheadcmo; bool ext_XVentanaCondOps; uint8_t pmu_num; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc new file mode 100644 index 0000000000..24acaf188c --- /dev/null +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -0,0 +1,81 @@ +/* + * RISC-V translation routines for the T-Head vendor extensions (xthead*). + * + * Copyright (c) 2022 VRULL GmbH. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#define REQUIRE_XTHEADCMO(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadcmo) { \ + return false; \ + } \ +} while (0) + +/* XTheadCmo */ + +static inline int priv_level(DisasContext *ctx) +{ +#ifdef CONFIG_USER_ONLY + return PRV_U; +#else + /* Priv level is part of mem_idx. */ + return ctx->mem_idx & TB_FLAGS_PRIV_MMU_MASK; +#endif +} + +/* Test if priv level is M, S, or U (cannot fail). */ +#define REQUIRE_PRIV_MSU(ctx) + +/* Test if priv level is M or S. */ +#define REQUIRE_PRIV_MS(ctx) \ +do { \ + int priv = priv_level(ctx); \ + if (!(priv == PRV_M || \ + priv == PRV_S)) { \ + return false; \ + } \ +} while (0) + +#define NOP_PRIVCHECK(insn, extcheck, privcheck) \ +static bool trans_ ## insn(DisasContext *ctx, arg_ ## insn * a) \ +{ \ + (void) a; \ + extcheck(ctx); \ + privcheck(ctx); \ + return true; \ +} + +NOP_PRIVCHECK(th_dcache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cpa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU) +NOP_PRIVCHECK(th_dcache_civa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU) +NOP_PRIVCHECK(th_dcache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU) +NOP_PRIVCHECK(th_dcache_csw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cisw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_isw, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cpal1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_dcache_cval1, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) + +NOP_PRIVCHECK(th_icache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_icache_ialls, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_icache_ipa, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU) + +NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) diff --git a/target/riscv/meson.build b/target/riscv/meson.build index ba25164d74..5dee37a242 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -2,6 +2,7 @@ gen = [ decodetree.process('insn16.decode', extra_args: ['--static-decode=decode_insn16', '--insnwidth=16']), decodetree.process('insn32.decode', extra_args: '--static-decode=decode_insn32'), + decodetree.process('xthead.decode', extra_args: '--static-decode=decode_xthead'), decodetree.process('XVentanaCondOps.decode', extra_args: '--static-decode=decode_XVentanaCodeOps'), ] diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 01cc30a365..1e29ac9886 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -130,6 +130,11 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) return true; } +static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) +{ + return ctx->cfg_ptr->ext_xtheadcmo; +} + #define MATERIALISE_EXT_PREDICATE(ext) \ static bool has_ ## ext ## _p(DisasContext *ctx) \ { \ @@ -1080,6 +1085,8 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc) #include "insn_trans/trans_rvk.c.inc" #include "insn_trans/trans_privileged.c.inc" #include "insn_trans/trans_svinval.c.inc" +#include "decode-xthead.c.inc" +#include "insn_trans/trans_xthead.c.inc" #include "insn_trans/trans_xventanacondops.c.inc" /* Include the auto-generated decoder for 16 bit insn */ @@ -1106,6 +1113,7 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode) bool (*decode_func)(DisasContext *, uint32_t); } decoders[] = { { always_true_p, decode_insn32 }, + { has_xthead_p, decode_xthead }, { has_XVentanaCondOps_p, decode_XVentanaCodeOps }, }; diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode new file mode 100644 index 0000000000..30533a66f5 --- /dev/null +++ b/target/riscv/xthead.decode @@ -0,0 +1,38 @@ +# +# Translation routines for the instructions of the XThead* ISA extensions +# +# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu +# +# SPDX-License-Identifier: LGPL-2.1-or-later +# +# The documentation of the ISA extensions can be found here: +# https://github.com/T-head-Semi/thead-extension-spec/releases/latest + +# Fields: +%rs1 15:5 + +# Formats +@sfence_vm ....... ..... ..... ... ..... ....... %rs1 + +# XTheadCmo +th_dcache_call 0000000 00001 00000 000 00000 0001011 +th_dcache_ciall 0000000 00011 00000 000 00000 0001011 +th_dcache_iall 0000000 00010 00000 000 00000 0001011 +th_dcache_cpa 0000001 01001 ..... 000 00000 0001011 @sfence_vm +th_dcache_cipa 0000001 01011 ..... 000 00000 0001011 @sfence_vm +th_dcache_ipa 0000001 01010 ..... 000 00000 0001011 @sfence_vm +th_dcache_cva 0000001 00101 ..... 000 00000 0001011 @sfence_vm +th_dcache_civa 0000001 00111 ..... 000 00000 0001011 @sfence_vm +th_dcache_iva 0000001 00110 ..... 000 00000 0001011 @sfence_vm +th_dcache_csw 0000001 00001 ..... 000 00000 0001011 @sfence_vm +th_dcache_cisw 0000001 00011 ..... 000 00000 0001011 @sfence_vm +th_dcache_isw 0000001 00010 ..... 000 00000 0001011 @sfence_vm +th_dcache_cpal1 0000001 01000 ..... 000 00000 0001011 @sfence_vm +th_dcache_cval1 0000001 00100 ..... 000 00000 0001011 @sfence_vm +th_icache_iall 0000000 10000 00000 000 00000 0001011 +th_icache_ialls 0000000 10001 00000 000 00000 0001011 +th_icache_ipa 0000001 11000 ..... 000 00000 0001011 @sfence_vm +th_icache_iva 0000001 10000 ..... 000 00000 0001011 @sfence_vm +th_l2cache_call 0000000 10101 00000 000 00000 0001011 +th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 +th_l2cache_iall 0000000 10110 00000 000 00000 0001011 -- 2.39.1 From MAILER-DAEMON Tue Jan 31 15:20:26 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMx7C-0006lw-6Y for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:19 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 02/14] RISC-V: Adding XTheadSync ISA extension Date: Tue, 31 Jan 2023 21:20:01 +0100 Message-Id: <20230131202013.2541053-3-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 20:20:24 -0000 From: Christoph Müllner This patch adds support for the XTheadSync ISA extension. The patch uses the T-Head specific decoder and translation. The implementation introduces a helper to execute synchronization tasks: helper_tlb_flush_all() performs a synchronized TLB flush on all CPUs. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use helper to synchronize CPUs and perform TLB flushes - Change implemenation to follow latest spec update - Use single decoder for XThead extensions Changes in v3: - Adjust for renamed REQUIRE_PRIV_* test macros Changes in v4: - Drop decode_save_opc() in trans_th_sfence_vmas() target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/helper.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 85 ++++++++++++++++++++++ target/riscv/op_helper.c | 6 ++ target/riscv/translate.c | 2 +- target/riscv/xthead.decode | 9 +++ 7 files changed, 105 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6ea61e5b22..f76639845d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -110,6 +110,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), + ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), }; @@ -1090,6 +1091,7 @@ static Property riscv_cpu_extensions[] = { /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), + DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), /* These are experimental so mark with 'x-' */ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d3ebc6f112..ea00586436 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -474,6 +474,7 @@ struct RISCVCPUConfig { /* Vendor-specific custom extensions */ bool ext_xtheadcmo; + bool ext_xtheadsync; bool ext_XVentanaCondOps; uint8_t pmu_num; diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 58a30f03d6..0497370afd 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -109,6 +109,7 @@ DEF_HELPER_1(sret, tl, env) DEF_HELPER_1(mret, tl, env) DEF_HELPER_1(wfi, void, env) DEF_HELPER_1(tlb_flush, void, env) +DEF_HELPER_1(tlb_flush_all, void, env) /* Native Debug */ DEF_HELPER_1(itrigger_match, void, env) #endif diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index 24acaf188c..f35bf6ea89 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -22,6 +22,12 @@ } \ } while (0) +#define REQUIRE_XTHEADSYNC(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadsync) { \ + return false; \ + } \ +} while (0) + /* XTheadCmo */ static inline int priv_level(DisasContext *ctx) @@ -79,3 +85,82 @@ NOP_PRIVCHECK(th_icache_iva, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MSU) NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) + +/* XTheadSync */ + +static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a) +{ + (void) a; + REQUIRE_XTHEADSYNC(ctx); + +#ifndef CONFIG_USER_ONLY + REQUIRE_PRIV_MS(ctx); + gen_helper_tlb_flush_all(cpu_env); + return true; +#else + return false; +#endif +} + +#ifndef CONFIG_USER_ONLY +static void gen_th_sync_local(DisasContext *ctx) +{ + /* + * Emulate out-of-order barriers with pipeline flush + * by exiting the translation block. + */ + gen_set_pc_imm(ctx, ctx->pc_succ_insn); + tcg_gen_exit_tb(NULL, 0); + ctx->base.is_jmp = DISAS_NORETURN; +} +#endif + +static bool trans_th_sync(DisasContext *ctx, arg_th_sync *a) +{ + (void) a; + REQUIRE_XTHEADSYNC(ctx); + +#ifndef CONFIG_USER_ONLY + REQUIRE_PRIV_MSU(ctx); + + /* + * th.sync is an out-of-order barrier. + */ + gen_th_sync_local(ctx); + + return true; +#else + return false; +#endif +} + +static bool trans_th_sync_i(DisasContext *ctx, arg_th_sync_i *a) +{ + (void) a; + REQUIRE_XTHEADSYNC(ctx); + +#ifndef CONFIG_USER_ONLY + REQUIRE_PRIV_MSU(ctx); + + /* + * th.sync.i is th.sync plus pipeline flush. + */ + gen_th_sync_local(ctx); + + return true; +#else + return false; +#endif +} + +static bool trans_th_sync_is(DisasContext *ctx, arg_th_sync_is *a) +{ + /* This instruction has the same behaviour like th.sync.i. */ + return trans_th_sync_i(ctx, a); +} + +static bool trans_th_sync_s(DisasContext *ctx, arg_th_sync_s *a) +{ + /* This instruction has the same behaviour like th.sync. */ + return trans_th_sync(ctx, a); +} diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 878bcb03b8..48f918b71b 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -258,6 +258,12 @@ void helper_tlb_flush(CPURISCVState *env) } } +void helper_tlb_flush_all(CPURISCVState *env) +{ + CPUState *cs = env_cpu(env); + tlb_flush_all_cpus_synced(cs); +} + void helper_hyp_tlb_flush(CPURISCVState *env) { CPUState *cs = env_cpu(env); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 1e29ac9886..0657a4bea2 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -132,7 +132,7 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { - return ctx->cfg_ptr->ext_xtheadcmo; + return ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 30533a66f5..1d86f3a012 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -10,9 +10,11 @@ # Fields: %rs1 15:5 +%rs2 20:5 # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 +@rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 # XTheadCmo th_dcache_call 0000000 00001 00000 000 00000 0001011 @@ -36,3 +38,10 @@ th_icache_iva 0000001 10000 ..... 000 00000 0001011 @sfence_vm th_l2cache_call 0000000 10101 00000 000 00000 0001011 th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 th_l2cache_iall 0000000 10110 00000 000 00000 0001011 + +# XTheadSync +th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s +th_sync 0000000 11000 00000 000 00000 0001011 +th_sync_i 0000000 11010 00000 000 00000 0001011 +th_sync_is 0000000 11011 00000 000 00000 0001011 +th_sync_s 0000000 11001 00000 000 00000 0001011 -- 2.39.1 From MAILER-DAEMON Tue Jan 31 15:20:27 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMx7D-0006ms-67 for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:20 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 03/14] RISC-V: Adding XTheadBa ISA extension Date: Tue, 31 Jan 2023 21:20:02 +0100 Message-Id: <20230131202013.2541053-4-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 20:20:25 -0000 From: Christoph Müllner This patch adds support for the XTheadBa ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Split XtheadB* extension into individual commits - Use single decoder for XThead extensions target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 39 ++++++++++++++++++++++ target/riscv/translate.c | 3 +- target/riscv/xthead.decode | 22 ++++++++++++ 5 files changed, 66 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f76639845d..dd5ff82f22 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -109,6 +109,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), @@ -1090,6 +1091,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), /* Vendor-specific custom extensions */ + DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ea00586436..f1f7795bd5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -473,6 +473,7 @@ struct RISCVCPUConfig { uint64_t mimpid; /* Vendor-specific custom extensions */ + bool ext_xtheadba; bool ext_xtheadcmo; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index f35bf6ea89..a6fb8132a8 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -16,6 +16,12 @@ * this program. If not, see . */ +#define REQUIRE_XTHEADBA(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadba) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADCMO(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadcmo) { \ return false; \ @@ -28,6 +34,39 @@ } \ } while (0) +/* XTheadBa */ + +/* + * th.addsl is similar to sh[123]add (from Zba), but not an + * alternative encoding: while sh[123] applies the shift to rs1, + * th.addsl shifts rs2. + */ + +#define GEN_TH_ADDSL(SHAMT) \ +static void gen_th_addsl##SHAMT(TCGv ret, TCGv arg1, TCGv arg2) \ +{ \ + TCGv t = tcg_temp_new(); \ + tcg_gen_shli_tl(t, arg2, SHAMT); \ + tcg_gen_add_tl(ret, t, arg1); \ + tcg_temp_free(t); \ +} + +GEN_TH_ADDSL(1) +GEN_TH_ADDSL(2) +GEN_TH_ADDSL(3) + +#define GEN_TRANS_TH_ADDSL(SHAMT) \ +static bool trans_th_addsl##SHAMT(DisasContext *ctx, \ + arg_th_addsl##SHAMT * a) \ +{ \ + REQUIRE_XTHEADBA(ctx); \ + return gen_arith(ctx, a, EXT_NONE, gen_th_addsl##SHAMT, NULL); \ +} + +GEN_TRANS_TH_ADDSL(1) +GEN_TRANS_TH_ADDSL(2) +GEN_TRANS_TH_ADDSL(3) + /* XTheadCmo */ static inline int priv_level(DisasContext *ctx) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0657a4bea2..4683562ecf 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -132,7 +132,8 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { - return ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; + return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadcmo || + ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 1d86f3a012..b149f13018 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -2,6 +2,7 @@ # Translation routines for the instructions of the XThead* ISA extensions # # Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu +# Dr. Philipp Tomsich, philipp.tomsich@vrull.eu # # SPDX-License-Identifier: LGPL-2.1-or-later # @@ -9,12 +10,33 @@ # https://github.com/T-head-Semi/thead-extension-spec/releases/latest # Fields: +%rd 7:5 %rs1 15:5 %rs2 20:5 +# Argument sets +&r rd rs1 rs2 !extern + # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 +@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd + +# XTheadBa +# Instead of defining a new encoding, we simply use the decoder to +# extract the imm[0:1] field and dispatch to separate translation +# functions (mirroring the `sh[123]add` instructions from Zba and +# the regular RVI `add` instruction. +# +# The only difference between sh[123]add and addsl is that the shift +# is applied to rs1 (for addsl) instead of rs2 (for sh[123]add). +# +# Note that shift-by-0 is a valid operation according to the manual. +# This will be equivalent to a regular add. +add 0000000 ..... ..... 001 ..... 0001011 @r +th_addsl1 0000001 ..... ..... 001 ..... 0001011 @r +th_addsl2 0000010 ..... ..... 001 ..... 0001011 @r +th_addsl3 0000011 ..... ..... 001 ..... 0001011 @r # XTheadCmo th_dcache_call 0000000 00001 00000 000 00000 0001011 -- 2.39.1 From MAILER-DAEMON Tue Jan 31 15:20:28 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMx7E-0006nb-OD for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:22 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 04/14] RISC-V: Adding XTheadBb ISA extension Date: Tue, 31 Jan 2023 21:20:03 +0100 Message-Id: <20230131202013.2541053-5-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=christoph.muellner@vrull.eu; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 20:20:27 -0000 From: Christoph Müllner This patch adds support for the XTheadBb ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Split XtheadB* extension into individual commits - Make implementation compatible with RV32. - Use single decoder for XThead extensions target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 124 +++++++++++++++++++++ target/riscv/translate.c | 4 +- target/riscv/xthead.decode | 20 ++++ 5 files changed, 149 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index dd5ff82f22..def27a53f2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -110,6 +110,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), + ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), @@ -1092,6 +1093,7 @@ static Property riscv_cpu_extensions[] = { /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), + DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index f1f7795bd5..be86c2fb95 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -474,6 +474,7 @@ struct RISCVCPUConfig { /* Vendor-specific custom extensions */ bool ext_xtheadba; + bool ext_xtheadbb; bool ext_xtheadcmo; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index a6fb8132a8..ebfab90dd9 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -22,6 +22,12 @@ } \ } while (0) +#define REQUIRE_XTHEADBB(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadbb) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADCMO(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadcmo) { \ return false; \ @@ -67,6 +73,124 @@ GEN_TRANS_TH_ADDSL(1) GEN_TRANS_TH_ADDSL(2) GEN_TRANS_TH_ADDSL(3) +/* XTheadBb */ + +/* th.srri is an alternate encoding for rori (from Zbb) */ +static bool trans_th_srri(DisasContext *ctx, arg_th_srri * a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_shift_imm_fn_per_ol(ctx, a, EXT_NONE, + tcg_gen_rotri_tl, gen_roriw, NULL); +} + +/* th.srriw is an alternate encoding for roriw (from Zbb) */ +static bool trans_th_srriw(DisasContext *ctx, arg_th_srriw *a) +{ + REQUIRE_XTHEADBB(ctx); + REQUIRE_64BIT(ctx); + ctx->ol = MXL_RV32; + return gen_shift_imm_fn(ctx, a, EXT_NONE, gen_roriw, NULL); +} + +/* th.ext and th.extu perform signed/unsigned bitfield extraction */ +static bool gen_th_bfextract(DisasContext *ctx, arg_th_bfext *a, + void (*f)(TCGv, TCGv, unsigned int, unsigned int)) +{ + TCGv dest = dest_gpr(ctx, a->rd); + TCGv source = get_gpr(ctx, a->rs1, EXT_ZERO); + + if (a->lsb <= a->msb) { + f(dest, source, a->lsb, a->msb - a->lsb + 1); + gen_set_gpr(ctx, a->rd, dest); + } + return true; +} + +static bool trans_th_ext(DisasContext *ctx, arg_th_ext *a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_th_bfextract(ctx, a, tcg_gen_sextract_tl); +} + +static bool trans_th_extu(DisasContext *ctx, arg_th_extu *a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_th_bfextract(ctx, a, tcg_gen_extract_tl); +} + +/* th.ff0: find first zero (clz on an inverted input) */ +static bool gen_th_ff0(DisasContext *ctx, arg_th_ff0 *a, DisasExtend ext) +{ + TCGv dest = dest_gpr(ctx, a->rd); + TCGv src1 = get_gpr(ctx, a->rs1, ext); + + int olen = get_olen(ctx); + TCGv t = tcg_temp_new(); + + tcg_gen_not_tl(t, src1); + if (olen != TARGET_LONG_BITS) { + if (olen == 32) { + gen_clzw(dest, t); + } else { + g_assert_not_reached(); + } + } else { + gen_clz(dest, t); + } + + tcg_temp_free(t); + gen_set_gpr(ctx, a->rd, dest); + + return true; +} + +static bool trans_th_ff0(DisasContext *ctx, arg_th_ff0 *a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_th_ff0(ctx, a, EXT_NONE); +} + +/* th.ff1 is an alternate encoding for clz (from Zbb) */ +static bool trans_th_ff1(DisasContext *ctx, arg_th_ff1 *a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_unary_per_ol(ctx, a, EXT_NONE, gen_clz, gen_clzw); +} + +static void gen_th_revw(TCGv ret, TCGv arg1) +{ + tcg_gen_bswap32_tl(ret, arg1, TCG_BSWAP_OS); +} + +/* th.rev is an alternate encoding for the RV64 rev8 (from Zbb) */ +static bool trans_th_rev(DisasContext *ctx, arg_th_rev *a) +{ + REQUIRE_XTHEADBB(ctx); + + return gen_unary_per_ol(ctx, a, EXT_NONE, tcg_gen_bswap_tl, gen_th_revw); +} + +/* th.revw is a sign-extended byte-swap of the lower word */ +static bool trans_th_revw(DisasContext *ctx, arg_th_revw *a) +{ + REQUIRE_XTHEADBB(ctx); + REQUIRE_64BIT(ctx); + return gen_unary(ctx, a, EXT_NONE, gen_th_revw); +} + +/* th.tstnbz is equivalent to an orc.b (from Zbb) with inverted result */ +static void gen_th_tstnbz(TCGv ret, TCGv source1) +{ + gen_orc_b(ret, source1); + tcg_gen_not_tl(ret, ret); +} + +static bool trans_th_tstnbz(DisasContext *ctx, arg_th_tstnbz *a) +{ + REQUIRE_XTHEADBB(ctx); + return gen_unary(ctx, a, EXT_ZERO, gen_th_tstnbz); +} + /* XTheadCmo */ static inline int priv_level(DisasContext *ctx) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 4683562ecf..387ef0ad8b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -132,8 +132,8 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { - return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadcmo || - ctx->cfg_ptr->ext_xtheadsync; + return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || + ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index b149f13018..8cd140891b 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -13,14 +13,23 @@ %rd 7:5 %rs1 15:5 %rs2 20:5 +%sh5 20:5 +%sh6 20:6 # Argument sets &r rd rs1 rs2 !extern +&r2 rd rs1 !extern +&shift shamt rs1 rd !extern +&th_bfext msb lsb rs1 rd # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1 @r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd +@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd +@th_bfext msb:6 lsb:6 ..... ... ..... ....... &th_bfext %rs1 %rd +@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd +@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd # XTheadBa # Instead of defining a new encoding, we simply use the decoder to @@ -38,6 +47,17 @@ th_addsl1 0000001 ..... ..... 001 ..... 0001011 @r th_addsl2 0000010 ..... ..... 001 ..... 0001011 @r th_addsl3 0000011 ..... ..... 001 ..... 0001011 @r +# XTheadBb +th_ext ...... ...... ..... 010 ..... 0001011 @th_bfext +th_extu ...... ...... ..... 011 ..... 0001011 @th_bfext +th_ff0 1000010 00000 ..... 001 ..... 0001011 @r2 +th_ff1 1000011 00000 ..... 001 ..... 0001011 @r2 +th_srri 000100 ...... ..... 001 ..... 0001011 @sh6 +th_srriw 0001010 ..... ..... 001 ..... 0001011 @sh5 +th_rev 1000001 00000 ..... 001 ..... 0001011 @r2 +th_revw 1001000 00000 ..... 001 ..... 0001011 @r2 +th_tstnbz 1000000 00000 ..... 001 ..... 0001011 @r2 + # XTheadCmo th_dcache_call 0000000 00001 00000 000 00000 0001011 th_dcache_ciall 0000000 00011 00000 000 00000 0001011 -- 2.39.1 From MAILER-DAEMON Tue Jan 31 15:20:29 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMx7E-0006nq-Ti for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:24 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 05/14] RISC-V: Adding XTheadBs ISA extension Date: Tue, 31 Jan 2023 21:20:04 +0100 Message-Id: <20230131202013.2541053-6-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 20:20:28 -0000 From: Christoph Müllner This patch adds support for the XTheadBs ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Split XtheadB* extension into individual commits - Use single decoder for XThead extensions target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 15 +++++++++++++++ target/riscv/translate.c | 3 ++- target/riscv/xthead.decode | 3 +++ 5 files changed, 23 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index def27a53f2..c541924214 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -111,6 +111,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), + ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), @@ -1094,6 +1095,7 @@ static Property riscv_cpu_extensions[] = { /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), + DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index be86c2fb95..876eaebd0e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -475,6 +475,7 @@ struct RISCVCPUConfig { /* Vendor-specific custom extensions */ bool ext_xtheadba; bool ext_xtheadbb; + bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index ebfab90dd9..bc1605445d 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -28,6 +28,12 @@ } \ } while (0) +#define REQUIRE_XTHEADBS(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadbs) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADCMO(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadcmo) { \ return false; \ @@ -191,6 +197,15 @@ static bool trans_th_tstnbz(DisasContext *ctx, arg_th_tstnbz *a) return gen_unary(ctx, a, EXT_ZERO, gen_th_tstnbz); } +/* XTheadBs */ + +/* th.tst is an alternate encoding for bexti (from Zbs) */ +static bool trans_th_tst(DisasContext *ctx, arg_th_tst *a) +{ + REQUIRE_XTHEADBS(ctx); + return gen_shift_imm_tl(ctx, a, EXT_NONE, gen_bext); +} + /* XTheadCmo */ static inline int priv_level(DisasContext *ctx) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 387ef0ad8b..880324e617 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -133,7 +133,8 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__))) static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || - ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || + ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 8cd140891b..8494805611 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -58,6 +58,9 @@ th_rev 1000001 00000 ..... 001 ..... 0001011 @r2 th_revw 1001000 00000 ..... 001 ..... 0001011 @r2 th_tstnbz 1000000 00000 ..... 001 ..... 0001011 @r2 +# XTheadBs +th_tst 100010 ...... ..... 001 ..... 0001011 @sh6 + # XTheadCmo th_dcache_call 0000000 00001 00000 000 00000 0001011 th_dcache_ciall 0000000 00011 00000 000 00000 0001011 -- 2.39.1 From MAILER-DAEMON Tue Jan 31 15:20:31 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMx7H-0006p9-GM for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 15:20:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMx7G-0006oj-Ap for qemu-riscv@nongnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:25 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 06/14] RISC-V: Adding XTheadCondMov ISA extension Date: Tue, 31 Jan 2023 21:20:05 +0100 Message-Id: <20230131202013.2541053-7-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 20:20:30 -0000 From: Christoph Müllner This patch adds support for the XTheadCondMov ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Fix invalid use of register from dest_gpr() - Use single decoder for XThead extensions target/riscv/cpu.c | 2 ++ target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 35 ++++++++++++++++++++++ target/riscv/translate.c | 2 +- target/riscv/xthead.decode | 4 +++ 5 files changed, 43 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c541924214..13b065bc68 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -113,6 +113,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), + ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), }; @@ -1097,6 +1098,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), + DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 876eaebd0e..a313e025e7 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -477,6 +477,7 @@ struct RISCVCPUConfig { bool ext_xtheadbb; bool ext_xtheadbs; bool ext_xtheadcmo; + bool ext_xtheadcondmov; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index bc1605445d..089b51f468 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -40,6 +40,12 @@ } \ } while (0) +#define REQUIRE_XTHEADCONDMOV(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadcondmov) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADSYNC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadsync) { \ return false; \ @@ -264,6 +270,35 @@ NOP_PRIVCHECK(th_l2cache_call, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) NOP_PRIVCHECK(th_l2cache_ciall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) NOP_PRIVCHECK(th_l2cache_iall, REQUIRE_XTHEADCMO, REQUIRE_PRIV_MS) +/* XTheadCondMov */ + +static bool gen_th_condmove(DisasContext *ctx, arg_r *a, TCGCond cond) +{ + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); + TCGv old = get_gpr(ctx, a->rd, EXT_NONE); + TCGv dest = dest_gpr(ctx, a->rd); + + tcg_gen_movcond_tl(cond, dest, src2, ctx->zero, src1, old); + + gen_set_gpr(ctx, a->rd, dest); + return true; +} + +/* th.mveqz: "if (rs2 == 0) rd = rs1;" */ +static bool trans_th_mveqz(DisasContext *ctx, arg_th_mveqz *a) +{ + REQUIRE_XTHEADCONDMOV(ctx); + return gen_th_condmove(ctx, a, TCG_COND_EQ); +} + +/* th.mvnez: "if (rs2 != 0) rd = rs1;" */ +static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a) +{ + REQUIRE_XTHEADCONDMOV(ctx); + return gen_th_condmove(ctx, a, TCG_COND_NE); +} + /* XTheadSync */ static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 880324e617..4f4c09cd68 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -134,7 +134,7 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || - ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 8494805611..a8ebd8a18b 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -84,6 +84,10 @@ th_l2cache_call 0000000 10101 00000 000 00000 0001011 th_l2cache_ciall 0000000 10111 00000 000 00000 0001011 th_l2cache_iall 0000000 10110 00000 000 00000 0001011 +# XTheadCondMov +th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r +th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r + # XTheadSync th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s th_sync 0000000 11000 00000 000 00000 0001011 -- 2.39.1 From MAILER-DAEMON Tue Jan 31 15:20:34 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMx7K-0006qW-6y for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:27 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 07/14] RISC-V: Adding T-Head multiply-accumulate instructions Date: Tue, 31 Jan 2023 21:20:06 +0100 Message-Id: <20230131202013.2541053-8-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 20:20:32 -0000 From: Christoph Müllner This patch adds support for the T-Head MAC instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 83 ++++++++++++++++++++++ target/riscv/translate.c | 3 +- target/riscv/xthead.decode | 8 +++ 5 files changed, 96 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 13b065bc68..88da4de14d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), + ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), }; @@ -1099,6 +1100,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), + DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a313e025e7..830b20558c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -478,6 +478,7 @@ struct RISCVCPUConfig { bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadcondmov; + bool ext_xtheadmac; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index 089b51f468..31a4034927 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -46,6 +46,12 @@ } \ } while (0) +#define REQUIRE_XTHEADMAC(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadmac) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADSYNC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadsync) { \ return false; \ @@ -299,6 +305,83 @@ static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a) return gen_th_condmove(ctx, a, TCG_COND_NE); } +/* XTheadMac */ + +static bool gen_th_mac(DisasContext *ctx, arg_r *a, + void (*accumulate_func)(TCGv, TCGv, TCGv), + void (*extend_operand_func)(TCGv, TCGv)) +{ + TCGv dest = dest_gpr(ctx, a->rd); + TCGv src0 = get_gpr(ctx, a->rd, EXT_NONE); + TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE); + TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE); + TCGv tmp = tcg_temp_new(); + + if (extend_operand_func) { + TCGv tmp2 = tcg_temp_new(); + extend_operand_func(tmp, src1); + extend_operand_func(tmp2, src2); + tcg_gen_mul_tl(tmp, tmp, tmp2); + tcg_temp_free(tmp2); + } else { + tcg_gen_mul_tl(tmp, src1, src2); + } + + accumulate_func(dest, src0, tmp); + gen_set_gpr(ctx, a->rd, dest); + tcg_temp_free(tmp); + + return true; +} + +/* th.mula: "rd = rd + rs1 * rs2" */ +static bool trans_th_mula(DisasContext *ctx, arg_th_mula *a) +{ + REQUIRE_XTHEADMAC(ctx); + return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL); +} + +/* th.mulah: "rd = sext.w(rd + sext.w(rs1[15:0]) * sext.w(rs2[15:0]))" */ +static bool trans_th_mulah(DisasContext *ctx, arg_th_mulah *a) +{ + REQUIRE_XTHEADMAC(ctx); + ctx->ol = MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_add_tl, tcg_gen_ext16s_tl); +} + +/* th.mulaw: "rd = sext.w(rd + rs1 * rs2)" */ +static bool trans_th_mulaw(DisasContext *ctx, arg_th_mulaw *a) +{ + REQUIRE_XTHEADMAC(ctx); + REQUIRE_64BIT(ctx); + ctx->ol = MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_add_tl, NULL); +} + +/* th.muls: "rd = rd - rs1 * rs2" */ +static bool trans_th_muls(DisasContext *ctx, arg_th_muls *a) +{ + REQUIRE_XTHEADMAC(ctx); + return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); +} + +/* th.mulsh: "rd = sext.w(rd - sext.w(rs1[15:0]) * sext.w(rs2[15:0]))" */ +static bool trans_th_mulsh(DisasContext *ctx, arg_th_mulsh *a) +{ + REQUIRE_XTHEADMAC(ctx); + ctx->ol = MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_sub_tl, tcg_gen_ext16s_tl); +} + +/* th.mulsw: "rd = sext.w(rd - rs1 * rs2)" */ +static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a) +{ + REQUIRE_XTHEADMAC(ctx); + REQUIRE_64BIT(ctx); + ctx->ol = MXL_RV32; + return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); +} + /* XTheadSync */ static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 4f4c09cd68..e5a57a8516 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -134,7 +134,8 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || - ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac || + ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index a8ebd8a18b..696de6cecf 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -88,6 +88,14 @@ th_l2cache_iall 0000000 10110 00000 000 00000 0001011 th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r +# XTheadMac +th_mula 00100 00 ..... ..... 001 ..... 0001011 @r +th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r +th_mulaw 00100 10 ..... ..... 001 ..... 0001011 @r +th_muls 00100 01 ..... ..... 001 ..... 0001011 @r +th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r +th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r + # XTheadSync th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s th_sync 0000000 11000 00000 000 00000 0001011 -- 2.39.1 From MAILER-DAEMON Tue Jan 31 15:20:36 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMx7M-0006rW-Cj for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:29 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 08/14] RISC-V: Adding T-Head MemPair extension Date: Tue, 31 Jan 2023 21:20:07 +0100 Message-Id: <20230131202013.2541053-9-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 20:20:34 -0000 From: Christoph Müllner This patch adds support for the T-Head MemPair instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions - Use get_address() to calculate addresses Changes in v4: - Don't translate in case of overlapping registers - Use temporaries to avoid unexpected behaviour in case of exceptions - There have also been clarifications in the specification Changes in v5: - Use memop_size() instead of hard coded constants target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 92 ++++++++++++++++++++++ target/riscv/translate.c | 2 +- target/riscv/xthead.decode | 13 +++ 5 files changed, 109 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 88da4de14d..b7047d139d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -115,6 +115,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), + ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), }; @@ -1101,6 +1102,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), + DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 830b20558c..38e80d44d5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -479,6 +479,7 @@ struct RISCVCPUConfig { bool ext_xtheadcmo; bool ext_xtheadcondmov; bool ext_xtheadmac; + bool ext_xtheadmempair; bool ext_xtheadsync; bool ext_XVentanaCondOps; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index 31a4034927..f1bd0dbad5 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -52,6 +52,12 @@ } \ } while (0) +#define REQUIRE_XTHEADMEMPAIR(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadmempair) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADSYNC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadsync) { \ return false; \ @@ -382,6 +388,92 @@ static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a) return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); } +/* XTheadMemPair */ + +static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop, + int shamt) +{ + if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) { + return false; + } + + TCGv t1 = tcg_temp_new(); + TCGv t2 = tcg_temp_new(); + TCGv addr1 = tcg_temp_new(); + TCGv addr2 = tcg_temp_new(); + int imm = a->sh2 << shamt; + + addr1 = get_address(ctx, a->rs, imm); + addr2 = get_address(ctx, a->rs, memop_size(memop) + imm); + + tcg_gen_qemu_ld_tl(t1, addr1, ctx->mem_idx, memop); + tcg_gen_qemu_ld_tl(t2, addr2, ctx->mem_idx, memop); + gen_set_gpr(ctx, a->rd1, t1); + gen_set_gpr(ctx, a->rd2, t2); + + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(addr1); + tcg_temp_free(addr2); + return true; +} + +static bool trans_th_ldd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + REQUIRE_64BIT(ctx); + return gen_loadpair_tl(ctx, a, MO_TESQ, 4); +} + +static bool trans_th_lwd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + return gen_loadpair_tl(ctx, a, MO_TESL, 3); +} + +static bool trans_th_lwud(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + return gen_loadpair_tl(ctx, a, MO_TEUL, 3); +} + +static bool gen_storepair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop, + int shamt) +{ + if (a->rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) { + return false; + } + + TCGv data1 = get_gpr(ctx, a->rd1, EXT_NONE); + TCGv data2 = get_gpr(ctx, a->rd2, EXT_NONE); + TCGv addr1 = tcg_temp_new(); + TCGv addr2 = tcg_temp_new(); + int imm = a->sh2 << shamt; + + addr1 = get_address(ctx, a->rs, imm); + addr2 = get_address(ctx, a->rs, memop_size(memop) + imm); + + tcg_gen_qemu_st_tl(data1, addr1, ctx->mem_idx, memop); + tcg_gen_qemu_st_tl(data2, addr2, ctx->mem_idx, memop); + + tcg_temp_free(addr1); + tcg_temp_free(addr2); + return true; +} + +static bool trans_th_sdd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + REQUIRE_64BIT(ctx); + return gen_storepair_tl(ctx, a, MO_TESQ, 4); +} + +static bool trans_th_swd(DisasContext *ctx, arg_th_pair *a) +{ + REQUIRE_XTHEADMEMPAIR(ctx); + return gen_storepair_tl(ctx, a, MO_TESL, 3); +} + /* XTheadSync */ static bool trans_th_sfence_vmas(DisasContext *ctx, arg_th_sfence_vmas *a) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e5a57a8516..f383e69db3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -135,7 +135,7 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac || - ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 696de6cecf..ff2a83b56d 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -11,16 +11,21 @@ # Fields: %rd 7:5 +%rd1 7:5 +%rs 15:5 %rs1 15:5 +%rd2 20:5 %rs2 20:5 %sh5 20:5 %sh6 20:6 +%sh2 25:2 # Argument sets &r rd rs1 rs2 !extern &r2 rd rs1 !extern &shift shamt rs1 rd !extern &th_bfext msb lsb rs1 rd +&th_pair rd1 rs rd2 sh2 # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @@ -30,6 +35,7 @@ @th_bfext msb:6 lsb:6 ..... ... ..... ....... &th_bfext %rs1 %rd @sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd @sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd +@th_pair ..... .. ..... ..... ... ..... ....... &th_pair %rd1 %rs %rd2 %sh2 # XTheadBa # Instead of defining a new encoding, we simply use the decoder to @@ -96,6 +102,13 @@ th_muls 00100 01 ..... ..... 001 ..... 0001011 @r th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r +# XTheadMemPair +th_ldd 11111 .. ..... ..... 100 ..... 0001011 @th_pair +th_lwd 11100 .. ..... ..... 100 ..... 0001011 @th_pair +th_lwud 11110 .. ..... ..... 100 ..... 0001011 @th_pair +th_sdd 11111 .. ..... ..... 101 ..... 0001011 @th_pair +th_swd 11100 .. ..... ..... 101 ..... 0001011 @th_pair + # XTheadSync th_sfence_vmas 0000010 ..... ..... 000 00000 0001011 @rs2_s th_sync 0000000 11000 00000 000 00000 0001011 -- 2.39.1 From MAILER-DAEMON Tue Jan 31 15:20:37 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMx7N-0006sH-Hi for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:30 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 09/14] RISC-V: Adding T-Head MemIdx extension Date: Tue, 31 Jan 2023 21:20:08 +0100 Message-Id: <20230131202013.2541053-10-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 20:20:35 -0000 From: Christoph Müllner This patch adds support for the T-Head MemIdx instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions - Avoid signed-bitfield-extraction by using signed immediate field imm5 - Use get_address() to calculate addresses - Introduce helper get_th_address_indexed for rs1+(rs2<cfg_ptr->ext_xtheadmemidx) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADMEMPAIR(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadmempair) { \ return false; \ @@ -64,6 +70,30 @@ } \ } while (0) +/* + * Calculate and return the address for indexed mem operations: + * If !zext_offs, then the address is rs1 + (rs2 << imm2). + * If zext_offs, then the address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static TCGv get_th_address_indexed(DisasContext *ctx, int rs1, int rs2, + int imm2, bool zext_offs) +{ + TCGv src2 = get_gpr(ctx, rs2, EXT_NONE); + TCGv offs = tcg_temp_new(); + + if (zext_offs) { + tcg_gen_extract_tl(offs, src2, 0, 32); + tcg_gen_shli_tl(offs, offs, imm2); + } else { + tcg_gen_shli_tl(offs, src2, imm2); + } + + TCGv addr = get_address_indexed(ctx, rs1, offs); + + tcg_temp_free(offs); + return addr; +} + /* XTheadBa */ /* @@ -388,6 +418,363 @@ static bool trans_th_mulsw(DisasContext *ctx, arg_th_mulsw *a) return gen_th_mac(ctx, a, tcg_gen_sub_tl, NULL); } +/* XTheadMemIdx */ + +/* + * Load with memop from indexed address and add (imm5 << imm2) to rs1. + * If !preinc, then the load address is rs1. + * If preinc, then the load address is rs1 + (imm5) << imm2). + */ +static bool gen_load_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop, + bool preinc) +{ + if (a->rs1 == a->rd) { + return false; + } + + int imm = a->imm5 << a->imm2; + TCGv addr = get_address(ctx, a->rs1, preinc ? imm : 0); + TCGv rd = dest_gpr(ctx, a->rd); + TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE); + + tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); + tcg_gen_addi_tl(rs1, rs1, imm); + gen_set_gpr(ctx, a->rd, rd); + gen_set_gpr(ctx, a->rs1, rs1); + + tcg_temp_free(addr); + return true; +} + +/* + * Store with memop to indexed address and add (imm5 << imm2) to rs1. + * If !preinc, then the store address is rs1. + * If preinc, then the store address is rs1 + (imm5) << imm2). + */ +static bool gen_store_inc(DisasContext *ctx, arg_th_meminc *a, MemOp memop, + bool preinc) +{ + int imm = a->imm5 << a->imm2; + TCGv addr = get_address(ctx, a->rs1, preinc ? imm : 0); + TCGv data = get_gpr(ctx, a->rd, EXT_NONE); + TCGv rs1 = get_gpr(ctx, a->rs1, EXT_NONE); + + tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); + tcg_gen_addi_tl(rs1, rs1, imm); + gen_set_gpr(ctx, a->rs1, rs1); + + tcg_temp_free(addr); + return true; +} + +static bool trans_th_ldia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_inc(ctx, a, MO_TESQ, false); +} + +static bool trans_th_ldib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_inc(ctx, a, MO_TESQ, true); +} + +static bool trans_th_lwia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TESL, false); +} + +static bool trans_th_lwib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TESL, true); +} + +static bool trans_th_lwuia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_inc(ctx, a, MO_TEUL, false); +} + +static bool trans_th_lwuib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_inc(ctx, a, MO_TEUL, true); +} + +static bool trans_th_lhia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TESW, false); +} + +static bool trans_th_lhib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TESW, true); +} + +static bool trans_th_lhuia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TEUW, false); +} + +static bool trans_th_lhuib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_TEUW, true); +} + +static bool trans_th_lbia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_SB, false); +} + +static bool trans_th_lbib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_SB, true); +} + +static bool trans_th_lbuia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_UB, false); +} + +static bool trans_th_lbuib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_inc(ctx, a, MO_UB, true); +} + +static bool trans_th_sdia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_store_inc(ctx, a, MO_TESQ, false); +} + +static bool trans_th_sdib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_store_inc(ctx, a, MO_TESQ, true); +} + +static bool trans_th_swia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_TESL, false); +} + +static bool trans_th_swib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_TESL, true); +} + +static bool trans_th_shia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_TESW, false); +} + +static bool trans_th_shib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_TESW, true); +} + +static bool trans_th_sbia(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_SB, false); +} + +static bool trans_th_sbib(DisasContext *ctx, arg_th_meminc *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_inc(ctx, a, MO_SB, true); +} + +/* + * Load with memop from indexed address. + * If !zext_offs, then address is rs1 + (rs2 << imm2). + * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static bool gen_load_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop, + bool zext_offs) +{ + TCGv rd = dest_gpr(ctx, a->rd); + TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs); + + tcg_gen_qemu_ld_tl(rd, addr, ctx->mem_idx, memop); + gen_set_gpr(ctx, a->rd, rd); + + return true; +} + +/* + * Store with memop to indexed address. + * If !zext_offs, then address is rs1 + (rs2 << imm2). + * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static bool gen_store_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop, + bool zext_offs) +{ + TCGv data = get_gpr(ctx, a->rd, EXT_NONE); + TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs); + + tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop); + + return true; +} + +static bool trans_th_lrd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_idx(ctx, a, MO_TESQ, false); +} + +static bool trans_th_lrw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TESL, false); +} + +static bool trans_th_lrwu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_idx(ctx, a, MO_TEUL, false); +} + +static bool trans_th_lrh(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TESW, false); +} + +static bool trans_th_lrhu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TEUW, false); +} + +static bool trans_th_lrb(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_SB, false); +} + +static bool trans_th_lrbu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_UB, false); +} + +static bool trans_th_srd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_store_idx(ctx, a, MO_TESQ, false); +} + +static bool trans_th_srw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_TESL, false); +} + +static bool trans_th_srh(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_TESW, false); +} + +static bool trans_th_srb(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_SB, false); +} +static bool trans_th_lurd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_idx(ctx, a, MO_TESQ, true); +} + +static bool trans_th_lurw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TESL, true); +} + +static bool trans_th_lurwu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_load_idx(ctx, a, MO_TEUL, true); +} + +static bool trans_th_lurh(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TESW, true); +} + +static bool trans_th_lurhu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_TEUW, true); +} + +static bool trans_th_lurb(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_SB, true); +} + +static bool trans_th_lurbu(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_load_idx(ctx, a, MO_UB, true); +} + +static bool trans_th_surd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + REQUIRE_64BIT(ctx); + return gen_store_idx(ctx, a, MO_TESQ, true); +} + +static bool trans_th_surw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_TESL, true); +} + +static bool trans_th_surh(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_TESW, true); +} + +static bool trans_th_surb(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADMEMIDX(ctx); + return gen_store_idx(ctx, a, MO_SB, true); +} + /* XTheadMemPair */ static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp memop, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f383e69db3..a979d43a6a 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -135,7 +135,8 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac || - ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempair || + ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ @@ -597,6 +598,24 @@ static TCGv get_address(DisasContext *ctx, int rs1, int imm) return addr; } +/* Compute a canonical address from a register plus reg offset. */ +static TCGv get_address_indexed(DisasContext *ctx, int rs1, TCGv offs) +{ + TCGv addr = temp_new(ctx); + TCGv src1 = get_gpr(ctx, rs1, EXT_NONE); + + tcg_gen_add_tl(addr, src1, offs); + if (ctx->pm_mask_enabled) { + tcg_gen_andc_tl(addr, addr, pm_mask); + } else if (get_xl(ctx) == MXL_RV32) { + tcg_gen_ext32u_tl(addr, addr); + } + if (ctx->pm_base_enabled) { + tcg_gen_or_tl(addr, addr, pm_base); + } + return addr; +} + #ifndef CONFIG_USER_ONLY /* The states of mstatus_fs are: * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index ff2a83b56d..69e40f22dc 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -17,8 +17,10 @@ %rd2 20:5 %rs2 20:5 %sh5 20:5 +%imm5 20:s5 %sh6 20:6 %sh2 25:2 +%imm2 25:2 # Argument sets &r rd rs1 rs2 !extern @@ -26,6 +28,8 @@ &shift shamt rs1 rd !extern &th_bfext msb lsb rs1 rd &th_pair rd1 rs rd2 sh2 +&th_memidx rd rs1 rs2 imm2 +&th_meminc rd rs1 imm5 imm2 # Formats @sfence_vm ....... ..... ..... ... ..... ....... %rs1 @@ -36,6 +40,8 @@ @sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd @sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd @th_pair ..... .. ..... ..... ... ..... ....... &th_pair %rd1 %rs %rd2 %sh2 +@th_memidx ..... .. ..... ..... ... ..... ....... &th_memidx %rd %rs1 %rs2 %imm2 +@th_meminc ..... .. ..... ..... ... ..... ....... &th_meminc %rd %rs1 %imm5 %imm2 # XTheadBa # Instead of defining a new encoding, we simply use the decoder to @@ -102,6 +108,54 @@ th_muls 00100 01 ..... ..... 001 ..... 0001011 @r th_mulsh 00101 01 ..... ..... 001 ..... 0001011 @r th_mulsw 00100 11 ..... ..... 001 ..... 0001011 @r +# XTheadMemIdx +th_ldia 01111 .. ..... ..... 100 ..... 0001011 @th_meminc +th_ldib 01101 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lwia 01011 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lwib 01001 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lwuia 11011 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lwuib 11001 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lhia 00111 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lhib 00101 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lhuia 10111 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lhuib 10101 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lbia 00011 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lbib 00001 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lbuia 10011 .. ..... ..... 100 ..... 0001011 @th_meminc +th_lbuib 10001 .. ..... ..... 100 ..... 0001011 @th_meminc +th_sdia 01111 .. ..... ..... 101 ..... 0001011 @th_meminc +th_sdib 01101 .. ..... ..... 101 ..... 0001011 @th_meminc +th_swia 01011 .. ..... ..... 101 ..... 0001011 @th_meminc +th_swib 01001 .. ..... ..... 101 ..... 0001011 @th_meminc +th_shia 00111 .. ..... ..... 101 ..... 0001011 @th_meminc +th_shib 00101 .. ..... ..... 101 ..... 0001011 @th_meminc +th_sbia 00011 .. ..... ..... 101 ..... 0001011 @th_meminc +th_sbib 00001 .. ..... ..... 101 ..... 0001011 @th_meminc + +th_lrd 01100 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrw 01000 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrwu 11000 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrh 00100 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrhu 10100 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrb 00000 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lrbu 10000 .. ..... ..... 100 ..... 0001011 @th_memidx +th_srd 01100 .. ..... ..... 101 ..... 0001011 @th_memidx +th_srw 01000 .. ..... ..... 101 ..... 0001011 @th_memidx +th_srh 00100 .. ..... ..... 101 ..... 0001011 @th_memidx +th_srb 00000 .. ..... ..... 101 ..... 0001011 @th_memidx + +th_lurd 01110 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurw 01010 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurwu 11010 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurh 00110 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurhu 10110 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurb 00010 .. ..... ..... 100 ..... 0001011 @th_memidx +th_lurbu 10010 .. ..... ..... 100 ..... 0001011 @th_memidx +th_surd 01110 .. ..... ..... 101 ..... 0001011 @th_memidx +th_surw 01010 .. ..... ..... 101 ..... 0001011 @th_memidx +th_surh 00110 .. ..... ..... 101 ..... 0001011 @th_memidx +th_surb 00010 .. ..... ..... 101 ..... 0001011 @th_memidx + # XTheadMemPair th_ldd 11111 .. ..... ..... 100 ..... 0001011 @th_pair th_lwd 11100 .. ..... ..... 100 ..... 0001011 @th_pair -- 2.39.1 From MAILER-DAEMON Tue Jan 31 15:20:41 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMx7R-0006uL-PB for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:32 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 10/14] RISC-V: Adding T-Head FMemIdx extension Date: Tue, 31 Jan 2023 21:20:09 +0100 Message-Id: <20230131202013.2541053-11-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=christoph.muellner@vrull.eu; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 20:20:37 -0000 From: Christoph Müllner This patch adds support for the T-Head FMemIdx instructions. The patch uses the T-Head specific decoder and translation. Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Add ISA_EXT_DATA_ENTRY() - Use single decoder for XThead extensions - Use get_th_address_indexed for address calculations target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 108 +++++++++++++++++++++ target/riscv/translate.c | 3 +- target/riscv/xthead.decode | 10 ++ 5 files changed, 123 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2d5a0881f1..5679e2cb83 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -114,6 +114,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), + ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx), ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), @@ -1102,6 +1103,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), + DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d776fea760..5cc3011529 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -478,6 +478,7 @@ struct RISCVCPUConfig { bool ext_xtheadbs; bool ext_xtheadcmo; bool ext_xtheadcondmov; + bool ext_xtheadfmemidx; bool ext_xtheadmac; bool ext_xtheadmemidx; bool ext_xtheadmempair; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index 8167de0393..37373732f6 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -46,6 +46,12 @@ } \ } while (0) +#define REQUIRE_XTHEADFMEMIDX(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadfmemidx) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADMAC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadmac) { \ return false; \ @@ -341,6 +347,108 @@ static bool trans_th_mvnez(DisasContext *ctx, arg_th_mveqz *a) return gen_th_condmove(ctx, a, TCG_COND_NE); } +/* XTheadFMem */ + +/* + * Load 64-bit float from indexed address. + * If !zext_offs, then address is rs1 + (rs2 << imm2). + * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static bool gen_fload_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop, + bool zext_offs) +{ + TCGv_i64 rd = cpu_fpr[a->rd]; + TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs); + + tcg_gen_qemu_ld_i64(rd, addr, ctx->mem_idx, memop); + if ((memop & MO_SIZE) == MO_32) { + gen_nanbox_s(rd, rd); + } + + mark_fs_dirty(ctx); + return true; +} + +/* + * Store 64-bit float to indexed address. + * If !zext_offs, then address is rs1 + (rs2 << imm2). + * If zext_offs, then address is rs1 + (zext(rs2[31:0]) << imm2). + */ +static bool gen_fstore_idx(DisasContext *ctx, arg_th_memidx *a, MemOp memop, + bool zext_offs) +{ + TCGv_i64 rd = cpu_fpr[a->rd]; + TCGv addr = get_th_address_indexed(ctx, a->rs1, a->rs2, a->imm2, zext_offs); + + tcg_gen_qemu_st_i64(rd, addr, ctx->mem_idx, memop); + + return true; +} + +static bool trans_th_flrd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + return gen_fload_idx(ctx, a, MO_TEUQ, false); +} + +static bool trans_th_flrw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + return gen_fload_idx(ctx, a, MO_TEUL, false); +} + +static bool trans_th_flurd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + return gen_fload_idx(ctx, a, MO_TEUQ, true); +} + +static bool trans_th_flurw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + return gen_fload_idx(ctx, a, MO_TEUL, true); +} + +static bool trans_th_fsrd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + return gen_fstore_idx(ctx, a, MO_TEUQ, false); +} + +static bool trans_th_fsrw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + return gen_fstore_idx(ctx, a, MO_TEUL, false); +} + +static bool trans_th_fsurd(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + return gen_fstore_idx(ctx, a, MO_TEUQ, true); +} + +static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a) +{ + REQUIRE_XTHEADFMEMIDX(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVF); + return gen_fstore_idx(ctx, a, MO_TEUL, true); +} + /* XTheadMac */ static bool gen_th_mac(DisasContext *ctx, arg_r *a, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index a979d43a6a..216eaf9d12 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -134,7 +134,8 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) { return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || - ctx->cfg_ptr->ext_xtheadcondmov || ctx->cfg_ptr->ext_xtheadmac || + ctx->cfg_ptr->ext_xtheadcondmov || + ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; } diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 69e40f22dc..81daf1d694 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -100,6 +100,16 @@ th_l2cache_iall 0000000 10110 00000 000 00000 0001011 th_mveqz 0100000 ..... ..... 001 ..... 0001011 @r th_mvnez 0100001 ..... ..... 001 ..... 0001011 @r +# XTheadFMemIdx +th_flrd 01100 .. ..... ..... 110 ..... 0001011 @th_memidx +th_flrw 01000 .. ..... ..... 110 ..... 0001011 @th_memidx +th_flurd 01110 .. ..... ..... 110 ..... 0001011 @th_memidx +th_flurw 01010 .. ..... ..... 110 ..... 0001011 @th_memidx +th_fsrd 01100 .. ..... ..... 111 ..... 0001011 @th_memidx +th_fsrw 01000 .. ..... ..... 111 ..... 0001011 @th_memidx +th_fsurd 01110 .. ..... ..... 111 ..... 0001011 @th_memidx +th_fsurw 01010 .. ..... ..... 111 ..... 0001011 @th_memidx + # XTheadMac th_mula 00100 00 ..... ..... 001 ..... 0001011 @r th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r -- 2.39.1 From MAILER-DAEMON Tue Jan 31 15:20:43 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMx7T-0006vA-9k for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:35 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 12/14] RISC-V: Add initial support for T-Head C906 Date: Tue, 31 Jan 2023 21:20:11 +0100 Message-Id: <20230131202013.2541053-13-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 20:20:42 -0000 From: Christoph Müllner This patch adds the T-Head C906 to the list of known CPUs. Selecting this CPUs will automatically enable the available ISA extensions of the CPUs (incl. vendor extensions). Co-developed-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- Changes in v2: - Drop C910 as it does not differ from C906 - Set priv version to 1.11 (new fmin/fmax behaviour) Changes in v3: - Removed setting dropped 'xtheadxmae' extension Changes in v4: - Inlcude cpu_vendorid.h in cpu.c instead cpu.h target/riscv/cpu.c | 31 +++++++++++++++++++++++++++++++ target/riscv/cpu.h | 1 + target/riscv/cpu_vendorid.h | 6 ++++++ 3 files changed, 38 insertions(+) create mode 100644 target/riscv/cpu_vendorid.h diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3078556f1b..8cbc5c9c1b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -22,6 +22,7 @@ #include "qemu/ctype.h" #include "qemu/log.h" #include "cpu.h" +#include "cpu_vendorid.h" #include "pmu.h" #include "internals.h" #include "time_helper.h" @@ -281,6 +282,35 @@ static void rv64_sifive_e_cpu_init(Object *obj) cpu->cfg.mmu = false; } +static void rv64_thead_c906_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + + set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_priv_version(env, PRIV_VERSION_1_11_0); + + cpu->cfg.ext_g = true; + cpu->cfg.ext_c = true; + cpu->cfg.ext_u = true; + cpu->cfg.ext_s = true; + cpu->cfg.ext_icsr = true; + cpu->cfg.ext_zfh = true; + cpu->cfg.mmu = true; + cpu->cfg.ext_xtheadba = true; + cpu->cfg.ext_xtheadbb = true; + cpu->cfg.ext_xtheadbs = true; + cpu->cfg.ext_xtheadcmo = true; + cpu->cfg.ext_xtheadcondmov = true; + cpu->cfg.ext_xtheadfmemidx = true; + cpu->cfg.ext_xtheadmac = true; + cpu->cfg.ext_xtheadmemidx = true; + cpu->cfg.ext_xtheadmempair = true; + cpu->cfg.ext_xtheadsync = true; + + cpu->cfg.mvendorid = THEAD_VENDOR_ID; +} + static void rv128_base_cpu_init(Object *obj) { if (qemu_tcg_mttcg_enabled()) { @@ -1371,6 +1401,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), #endif }; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 5cc3011529..60478f4a9c 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -53,6 +53,7 @@ #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") #if defined(TARGET_RISCV32) diff --git a/target/riscv/cpu_vendorid.h b/target/riscv/cpu_vendorid.h new file mode 100644 index 0000000000..a5aa249bc9 --- /dev/null +++ b/target/riscv/cpu_vendorid.h @@ -0,0 +1,6 @@ +#ifndef TARGET_RISCV_CPU_VENDORID_H +#define TARGET_RISCV_CPU_VENDORID_H + +#define THEAD_VENDOR_ID 0x5b7 + +#endif /* TARGET_RISCV_CPU_VENDORID_H */ -- 2.39.1 From MAILER-DAEMON Tue Jan 31 15:20:49 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMx7X-0006zU-BN for mharc-qemu-riscv@gnu.org; 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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:34 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 11/14] RISC-V: Set minimum priv version for Zfh to 1.11 Date: Tue, 31 Jan 2023 21:20:10 +0100 Message-Id: <20230131202013.2541053-12-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=christoph.muellner@vrull.eu; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 20:20:41 -0000 From: Christoph Müllner There are no differences for floating point instructions in priv version 1.11 and 1.12. There is also no dependency for Zfh to priv version 1.12. Therefore allow Zfh to be enabled for priv version 1.11. Acked-by: Alistair Francis Signed-off-by: Christoph Müllner --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5679e2cb83..3078556f1b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -77,7 +77,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), - ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), + ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh), ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), -- 2.39.1 From MAILER-DAEMON Tue Jan 31 15:20:54 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMx7c-000731-UC for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 15:20:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMx7T-0006v8-3U for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 15:20:43 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMx7Q-0002pK-Ue for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 15:20:42 -0500 Received: by mail-wr1-x435.google.com with SMTP id m14so14890620wrg.13 for ; Tue, 31 Jan 2023 12:20:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ztCilUCc1TA2sITRxRLcH39NMH4uHHWLjoD1hpEHldM=; b=VPxikWJqZJrtBu1Pos5YXivoQ3Xgu7Re4C9is/oYEsPM/TuZz+8ousjy56t6V25hbL fArTHYMIbsBs7q7zBNllWB6BGu0DEf4c8FfEmEF65Rb2stOauC0i77CBLEQL91yejsBr +d1EYpN5k0yqFRLicyOiJMkoWMjHpNZrcPGPko3Zh8cSJHT07hn6DvV4h+z7FP7d5obn IfjR/hp8uudQMhdePhL9Pv4FbBwdrzz4pX9yDS8uHxIn9l1FhaGcrLSUuiPravT3jtV/ ADSgz05fIzyr8U5a/3OZvQpHADHcU7jOdR/+xitTfQkbxQ1c+QHslvrh1Qd7KCg4yLT+ q3DA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ztCilUCc1TA2sITRxRLcH39NMH4uHHWLjoD1hpEHldM=; b=SivFkD4ZWjI+59WS1dekoN+1pqs+n2V2uaKf0o26LDEC0cdPIZnsple9G6Dvq4Z/BT ttAeVjOpzsRGcqr4VByQO4Cn07Kw5CJyxiG1TalHqfSIRkZ+jDSjKSXK56KoRcE7EDcd 0yGh1uCC3vzqu+Ax3oDUp8RhOqeeNfSL9t+r3o6E93A8g2PnjsupQmaS+JPiJ/RtMBZy Bj01vC7ZfZ2SG6iP4ZjrS431LnN5cYolMjdQ2HOkF24+Ddcy2Lk5s+wJU6B6aGqfGLNz L3SUX0RzKHztQjqbkpdO1q2td5ORfkaFvwTruDrJA0Dx84OltsZukl0l2eAdH4bYcHzN ebdA== X-Gm-Message-State: AO0yUKVXDn2TfJmO4jvvKDNqumOVe4lngGlEHQtpZYLj+nYOKAJ8AJOI W9r+5xqQPKdONi38D2jcDCAYekd8Q73cLMc+ X-Google-Smtp-Source: AK7set+a6yEvzExo1SdzDHufeAJy4by1vPJVgdgY/Fh+K5S3L2JevVysEz+HD+1iBVRBo+3OdxRGQw== X-Received: by 2002:a5d:6501:0:b0:2c2:de2b:e7cd with SMTP id x1-20020a5d6501000000b002c2de2be7cdmr290196wru.50.1675196439782; Tue, 31 Jan 2023 12:20:39 -0800 (PST) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:38 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 14/14] target/riscv: add a MAINTAINERS entry for XThead* extension support Date: Tue, 31 Jan 2023 21:20:13 +0100 Message-Id: <20230131202013.2541053-15-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=christoph.muellner@vrull.eu; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 20:20:43 -0000 From: Christoph Müllner The XThead* extensions are maintained by T-Head and VRULL. Adding a point of contact from both companies. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index c581c11a64..9dc0a2954e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -295,6 +295,14 @@ F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux-user/host/riscv64/ +RISC-V XThead* extensions +M: Christoph Muellner +M: LIU Zhiwei +L: qemu-riscv@nongnu.org +S: Supported +F: target/riscv/insn_trans/trans_xthead.c.inc +F: target/riscv/xthead*.decode + RISC-V XVentanaCondOps extension M: Philipp Tomsich L: qemu-riscv@nongnu.org -- 2.39.1 From MAILER-DAEMON Tue Jan 31 15:20:55 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pMx7e-00073W-Ud for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 15:20:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pMx7T-0006vD-9L for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 15:20:43 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pMx7Q-0002vK-4P for qemu-riscv@nongnu.org; Tue, 31 Jan 2023 15:20:43 -0500 Received: by mail-wm1-x329.google.com with SMTP id bg26so5369872wmb.0 for ; Tue, 31 Jan 2023 12:20:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=566M9qySxN23A71+uLC8/2FZUCFdWIxzeit6Cy0IHpE=; b=JmrILXtOD9SHgJ6R3EqpNLtq+ZJkzZ9HChifdx1XAaURYdVPHSmgHwfwcf7DG6v6XV 7jmd7eXHZdAFUCAd6XCJ88fhUhVxg4mXRudbkVXsC5l7w3n30Wo7Jq4dxG/zs3qK30hU OvWbGGZ8LLBmIG4tyXstL/M59vFTypga8eQLWuLTdLylRkDwNp4QgOfARA1KHQ70gwcb XNcQm9s+KmRt7TOXkdO5/LoBUqL1GF3UIhoRaTmAgggAa0Sfu/wvJd5bASOkmdtD8yTR ez0LEsUSrs2XPVAPhaWDxSgtN7mU9AfOonIKEe5CVfDJIFQX5gtEtIzGc7/VRA2mIUC8 EpIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=566M9qySxN23A71+uLC8/2FZUCFdWIxzeit6Cy0IHpE=; b=kvIkL94SGdLPteCnmXGySv/rT5TaHFpCh/1eLhWqutR5ToQY6mgBYe3uP5/PehU3P5 3YuHgKyk+2QtR44X62/QKoP5JRE6Y5Deeql15Nl3/xP0ljRa7M1fGsbwXaYq4N7kkvYW qbpcs1RWue3dOVp3IUcTC7D4hv1fwFlojlJtpintAIvwW1ABsoYyalLgdTSTBgOpFhg3 OsxOY7JqDCuej3DP7PsCxJjB3XPza6JIqgZqq/EP0UbMa1rdLBybrkLDaRjOI9y5hLxx kX5tb08+JT+mA7mgP1qoGHbINPVj6mqhp+0aJirP1NphKChpOWO7zITIjc5Anle26U+O uYKQ== X-Gm-Message-State: AFqh2kr7aXHsGuxgfUhq12r19P7zNhTsUgor8FJ4QM9NxeEPWQPIRGc4 MaJKD1d7XP/zrU2gv4TK0Tx+q7F+XxXNVtW4 X-Google-Smtp-Source: AMrXdXvk4HQimGZ0PYNsLjHeA06UIiAXs6S98MNkgVYFNZ+h233NCyhKpJsHV54z30JaDQsZvPvDNw== X-Received: by 2002:a05:600c:3495:b0:3db:a3a:4594 with SMTP id a21-20020a05600c349500b003db0a3a4594mr57673839wmq.28.1675196438062; Tue, 31 Jan 2023 12:20:38 -0800 (PST) Received: from beast.fritz.box (62-178-148-172.cable.dynamic.surfer.at. [62.178.148.172]) by smtp.gmail.com with ESMTPSA id v2-20020adfe282000000b002bdec340a1csm15391977wri.110.2023.01.31.12.20.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Jan 2023 12:20:37 -0800 (PST) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?UTF-8?q?Heiko=20St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH v5 13/14] RISC-V: Adding XTheadFmv ISA extension Date: Tue, 31 Jan 2023 21:20:12 +0100 Message-Id: <20230131202013.2541053-14-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230131202013.2541053-1-christoph.muellner@vrull.eu> References: <20230131202013.2541053-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=christoph.muellner@vrull.eu; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Jan 2023 20:20:43 -0000 From: Christoph Müllner This patch adds support for the XTheadFmv ISA extension. The patch uses the T-Head specific decoder and translation. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Signed-off-by: Christoph Müllner --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 1 + target/riscv/insn_trans/trans_xthead.c.inc | 45 ++++++++++++++++++++++ target/riscv/translate.c | 6 +-- target/riscv/xthead.decode | 4 ++ 5 files changed, 55 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8cbc5c9c1b..0dd2f0c753 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -116,6 +116,7 @@ static const struct isa_ext_data isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), + ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv), ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx), ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), @@ -1134,6 +1135,7 @@ static Property riscv_cpu_extensions[] = { DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), + DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 60478f4a9c..7128438d8e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -480,6 +480,7 @@ struct RISCVCPUConfig { bool ext_xtheadcmo; bool ext_xtheadcondmov; bool ext_xtheadfmemidx; + bool ext_xtheadfmv; bool ext_xtheadmac; bool ext_xtheadmemidx; bool ext_xtheadmempair; diff --git a/target/riscv/insn_trans/trans_xthead.c.inc b/target/riscv/insn_trans/trans_xthead.c.inc index 37373732f6..be87c34f56 100644 --- a/target/riscv/insn_trans/trans_xthead.c.inc +++ b/target/riscv/insn_trans/trans_xthead.c.inc @@ -52,6 +52,12 @@ } \ } while (0) +#define REQUIRE_XTHEADFMV(ctx) do { \ + if (!ctx->cfg_ptr->ext_xtheadfmv) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_XTHEADMAC(ctx) do { \ if (!ctx->cfg_ptr->ext_xtheadmac) { \ return false; \ @@ -449,6 +455,45 @@ static bool trans_th_fsurw(DisasContext *ctx, arg_th_memidx *a) return gen_fstore_idx(ctx, a, MO_TEUL, true); } +/* XTheadFmv */ + +static bool trans_th_fmv_hw_x(DisasContext *ctx, arg_th_fmv_hw_x *a) +{ + REQUIRE_XTHEADFMV(ctx); + REQUIRE_32BIT(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + + TCGv src1 = get_gpr(ctx, a->rs1, EXT_ZERO); + TCGv_i64 t1 = tcg_temp_new_i64(); + + tcg_gen_extu_tl_i64(t1, src1); + tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rd], t1, 32, 32); + tcg_temp_free_i64(t1); + mark_fs_dirty(ctx); + return true; +} + +static bool trans_th_fmv_x_hw(DisasContext *ctx, arg_th_fmv_x_hw *a) +{ + REQUIRE_XTHEADFMV(ctx); + REQUIRE_32BIT(ctx); + REQUIRE_FPU; + REQUIRE_EXT(ctx, RVD); + TCGv dst; + TCGv_i64 t1; + + dst = dest_gpr(ctx, a->rd); + t1 = tcg_temp_new_i64(); + + tcg_gen_extract_i64(t1, cpu_fpr[a->rs1], 32, 32); + tcg_gen_trunc_i64_tl(dst, t1); + gen_set_gpr(ctx, a->rd, dst); + tcg_temp_free_i64(t1); + mark_fs_dirty(ctx); + return true; +} + /* XTheadMac */ static bool gen_th_mac(DisasContext *ctx, arg_r *a, diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 216eaf9d12..182649dcb6 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -135,9 +135,9 @@ static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__))) return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadbb || ctx->cfg_ptr->ext_xtheadbs || ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadcondmov || - ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadmac || - ctx->cfg_ptr->ext_xtheadmemidx || ctx->cfg_ptr->ext_xtheadmempair || - ctx->cfg_ptr->ext_xtheadsync; + ctx->cfg_ptr->ext_xtheadfmemidx || ctx->cfg_ptr->ext_xtheadfmv || + ctx->cfg_ptr->ext_xtheadmac || ctx->cfg_ptr->ext_xtheadmemidx || + ctx->cfg_ptr->ext_xtheadmempair || ctx->cfg_ptr->ext_xtheadsync; } #define MATERIALISE_EXT_PREDICATE(ext) \ diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode index 81daf1d694..d1d104bcf2 100644 --- a/target/riscv/xthead.decode +++ b/target/riscv/xthead.decode @@ -110,6 +110,10 @@ th_fsrw 01000 .. ..... ..... 111 ..... 0001011 @th_memidx th_fsurd 01110 .. ..... ..... 111 ..... 0001011 @th_memidx th_fsurw 01010 .. ..... ..... 111 ..... 0001011 @th_memidx +# XTheadFmv +th_fmv_hw_x 1010000 00000 ..... 001 ..... 0001011 @r2 +th_fmv_x_hw 1100000 00000 ..... 001 ..... 0001011 @r2 + # XTheadMac th_mula 00100 00 ..... ..... 001 ..... 0001011 @r th_mulah 00101 00 ..... ..... 001 ..... 0001011 @r -- 2.39.1 From MAILER-DAEMON Tue Jan 31 19:16:59 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pN0o7-0007OX-FD for mharc-qemu-riscv@gnu.org; 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charset="UTF-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2607:f8b0:4864:20::a2e; envelope-from=alistair23@gmail.com; helo=mail-vk1-xa2e.google.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Feb 2023 00:16:52 -0000 On Fri, Jan 20, 2023 at 7:38 AM Daniel Henrique Barboza wrote: > > load_elf_ram_sym() will sign-extend 32 bit addresses. If a 32 bit > QEMU guest happens to be running in a hypervisor that are using 64 > bits to encode its address, kernel_entry can be padded with '1's > and create problems [1]. > > Use a translate_fn() callback to be called by load_elf_ram_sym() and > return only the 32 bits address if we're running a 32 bit CPU. > > [1] https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02281.html > > Suggested-by: Philippe Mathieu-Daud=C3=A9 > Suggested-by: Bin Meng > Reviewed-by: Philippe Mathieu-Daud=C3=A9 > Signed-off-by: Daniel Henrique Barboza > --- > hw/riscv/boot.c | 20 +++++++++++++++++++- > hw/riscv/microchip_pfsoc.c | 3 ++- > hw/riscv/opentitan.c | 3 ++- > hw/riscv/sifive_e.c | 3 ++- > hw/riscv/sifive_u.c | 3 ++- > hw/riscv/spike.c | 3 ++- > hw/riscv/virt.c | 3 ++- > include/hw/riscv/boot.h | 1 + > 8 files changed, 32 insertions(+), 7 deletions(-) > > diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c > index 2594276223..46fc7adccf 100644 > --- a/hw/riscv/boot.c > +++ b/hw/riscv/boot.c > @@ -173,7 +173,24 @@ target_ulong riscv_load_firmware(const char *firmwar= e_filename, > exit(1); > } > > +static uint64_t translate_kernel_address(void *opaque, uint64_t addr) > +{ > + RISCVHartArrayState *harts =3D opaque; > + > + if (riscv_is_32bit(harts)) { > + /* > + * For 32 bit CPUs, kernel_load_base is sign-extended > + * (i.e. it can be padded with '1's) by load_elf(). > + * Remove the sign extension by truncating to 32-bit. > + */ > + return extract64(addr, 0, 32); > + } > + > + return addr; So.... After all that, this doesn't actually mask pentry from load_elf_ram_sym(), so it doesn't help. > +} > + > target_ulong riscv_load_kernel(MachineState *machine, > + RISCVHartArrayState *harts, > target_ulong kernel_start_addr, > symbol_fn_t sym_cb) > { > @@ -189,7 +206,8 @@ target_ulong riscv_load_kernel(MachineState *machine, > * the (expected) load address load address. This allows kernels to = have > * separate SBI and ELF entry points (used by FreeBSD, for example). > */ > - if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, > + if (load_elf_ram_sym(kernel_filename, NULL, > + translate_kernel_address, harts, > NULL, &kernel_load_base, NULL, NULL, 0, > EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { I think we just need to add the mask here Alistair > return kernel_load_base; > diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c > index 82ae5e7023..bdefeb3cbb 100644 > --- a/hw/riscv/microchip_pfsoc.c > +++ b/hw/riscv/microchip_pfsoc.c > @@ -629,7 +629,8 @@ static void microchip_icicle_kit_machine_init(Machine= State *machine) > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpu= s, > firmware_end_ad= dr); > > - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, N= ULL); > + kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, > + kernel_start_addr, NULL); > > if (machine->initrd_filename) { > riscv_load_initrd(machine, kernel_entry); > diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c > index 64d5d435b9..2731138c41 100644 > --- a/hw/riscv/opentitan.c > +++ b/hw/riscv/opentitan.c > @@ -101,7 +101,8 @@ static void opentitan_board_init(MachineState *machin= e) > } > > if (machine->kernel_filename) { > - riscv_load_kernel(machine, memmap[IBEX_DEV_RAM].base, NULL); > + riscv_load_kernel(machine, &s->soc.cpus, > + memmap[IBEX_DEV_RAM].base, NULL); > } > } > > diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c > index 3e3f4b0088..1a7d381514 100644 > --- a/hw/riscv/sifive_e.c > +++ b/hw/riscv/sifive_e.c > @@ -114,7 +114,8 @@ static void sifive_e_machine_init(MachineState *machi= ne) > memmap[SIFIVE_E_DEV_MROM].base, &address_space= _memory); > > if (machine->kernel_filename) { > - riscv_load_kernel(machine, memmap[SIFIVE_E_DEV_DTIM].base, NULL)= ; > + riscv_load_kernel(machine, &s->soc.cpus, > + memmap[SIFIVE_E_DEV_DTIM].base, NULL); > } > } > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index 2fb6ee231f..83dfe09877 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -598,7 +598,8 @@ static void sifive_u_machine_init(MachineState *machi= ne) > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc.u_cpu= s, > firmware_end_ad= dr); > > - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, N= ULL); > + kernel_entry =3D riscv_load_kernel(machine, &s->soc.u_cpus, > + kernel_start_addr, NULL); > > if (machine->initrd_filename) { > riscv_load_initrd(machine, kernel_entry); > diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c > index badc11ec43..2bcc50d90d 100644 > --- a/hw/riscv/spike.c > +++ b/hw/riscv/spike.c > @@ -305,7 +305,8 @@ static void spike_board_init(MachineState *machine) > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], > firmware_end_ad= dr); > > - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, > + kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], > + kernel_start_addr, > htif_symbol_callback); > > if (machine->initrd_filename) { > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c > index 4a11b4b010..ac173a6ed6 100644 > --- a/hw/riscv/virt.c > +++ b/hw/riscv/virt.c > @@ -1274,7 +1274,8 @@ static void virt_machine_done(Notifier *notifier, v= oid *data) > kernel_start_addr =3D riscv_calc_kernel_start_addr(&s->soc[0], > firmware_end_ad= dr); > > - kernel_entry =3D riscv_load_kernel(machine, kernel_start_addr, N= ULL); > + kernel_entry =3D riscv_load_kernel(machine, &s->soc[0], > + kernel_start_addr, NULL); > > if (machine->initrd_filename) { > riscv_load_initrd(machine, kernel_entry); > diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h > index f94653a09b..105706bf25 100644 > --- a/include/hw/riscv/boot.h > +++ b/include/hw/riscv/boot.h > @@ -44,6 +44,7 @@ target_ulong riscv_load_firmware(const char *firmware_f= ilename, > hwaddr firmware_load_addr, > symbol_fn_t sym_cb); > target_ulong riscv_load_kernel(MachineState *machine, > + RISCVHartArrayState *harts, > target_ulong firmware_end_addr, > symbol_fn_t sym_cb); > void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry); > -- > 2.39.0 > > From MAILER-DAEMON Tue Jan 31 23:11:40 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pN4TD-00089S-Rb for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 23:11:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pN4TB-00086J-MH; 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charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Feb 2023 04:11:37 -0000 On Wed, Feb 1, 2023 at 1:35 AM Sergey Matyukevich wrote: > > From: Sergey Matyukevich > > According to priviledged spec, if [sm]tval is written with a nonzero typo: privileged > value when a breakpoint exception occurs, then [sm]tval will contain > the faulting virtual address. Set tval to hit address when breakpoint > exception is triggered by hardware watchpoint. > > Signed-off-by: Sergey Matyukevich > > --- > > v1 -> v2 > - do not set tval blindly for every breakpoint exception, > handle current specific case under consideration > > target/riscv/cpu_helper.c | 6 ++++++ > target/riscv/debug.c | 1 - > 2 files changed, 6 insertions(+), 1 deletion(-) > Reviewed-by: Bin Meng From MAILER-DAEMON Tue Jan 31 23:17:33 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pN4Yv-0008SG-FW for mharc-qemu-riscv@gnu.org; Tue, 31 Jan 2023 23:17:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pN4Yn-0008My-Gr; Tue, 31 Jan 2023 23:17:26 -0500 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pN4Ym-0001u5-1i; Tue, 31 Jan 2023 23:17:25 -0500 Received: by mail-ej1-x630.google.com with SMTP id dr8so26166539ejc.12; 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Tue, 31 Jan 2023 20:17:20 -0800 (PST) MIME-Version: 1.0 References: <20230131133906.1956228-1-alexghiti@rivosinc.com> <20230131133906.1956228-4-alexghiti@rivosinc.com> In-Reply-To: <20230131133906.1956228-4-alexghiti@rivosinc.com> From: Bin Meng Date: Wed, 1 Feb 2023 12:17:09 +0800 Message-ID: Subject: Re: [PATCH v9 3/5] riscv: Allow user to set the satp mode To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Ludovic Henry Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Feb 2023 04:17:29 -0000 On Tue, Jan 31, 2023 at 11:13 PM Alexandre Ghiti wrote: > > RISC-V specifies multiple sizes for addressable memory and Linux probes for > the machine's support at startup via the satp CSR register (done in > csr.c:validate_vm). > > As per the specification, sv64 must support sv57, which in turn must > support sv48...etc. So we can restrict machine support by simply setting the > "highest" supported mode and the bare mode is always supported. > > You can set the satp mode using the new properties "sv32", "sv39", "sv48", > "sv57" and "sv64" as follows: > -cpu rv64,sv57=on # Linux will boot using sv57 scheme > -cpu rv64,sv39=on # Linux will boot using sv39 scheme > -cpu rv64,sv57=off # Linux will boot using sv48 scheme > -cpu rv64 # Linux will boot using sv57 scheme by default > > We take the highest level set by the user: > -cpu rv64,sv48=on,sv57=on # Linux will boot using sv57 scheme > > We make sure that invalid configurations are rejected: > -cpu rv64,sv39=off,sv48=on # sv39 must be supported if higher modes are > # enabled > > We accept "redundant" configurations: > -cpu rv64,sv48=on,sv57=off # Linux will boot using sv48 scheme > > And contradictory configurations: > -cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme > > Co-Developed-by: Ludovic Henry > Signed-off-by: Ludovic Henry > Signed-off-by: Alexandre Ghiti > Reviewed-by: Andrew Jones > --- > target/riscv/cpu.c | 207 +++++++++++++++++++++++++++++++++++++++++++++ > target/riscv/cpu.h | 19 +++++ > target/riscv/csr.c | 12 ++- > 3 files changed, 231 insertions(+), 7 deletions(-) > Reviewed-by: Bin Meng From MAILER-DAEMON Tue Jan 31 23:21:28 2023 Received: from list by lists.gnu.org with archive (Exim 4.90_1) id 1pN4ci-0001sb-Bh for mharc-qemu-riscv@gnu.org; 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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=cc:to:subject:message-id:date:from:in-reply-to:references :mime-version:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=D2bJpswGWFGivZbzenz2EjWLjQyLi9lBUp76P5kXRKQ=; b=eEOGSehttx0PoAfN4HoLwlcN2WGkAKoz0GxLsMlXl5y329X9FzpYpR7IwYn7tai6X3 Zwpbg+AOkSRIL0zxhnFN0m/N29Cw5mgc9gnGZqUMqVzjCT+QYNsMPBTn3nVd3fR26CFR 9Yr6MpORGTuYnr7QGvET5RJtjmDsjGz5m6hbHW/EGl++23PkzAQaHVt/NSHnZIBlPX0d +DPos1npJsEgK3C+JNhEGymFcxr11aXDfiwo4BXhUOTn5B80Z3e0AosaE2TJGMlsd2+x ysMLmFDWlcAdIXZdg1fM9dwJiFToE/nuSactBbYvn7Vw66JGIVAFVk2XR5xU+uryipxn bdlQ== X-Gm-Message-State: AO0yUKU7pjSoAozii679iQsOojY0J1A9nI+zxF11E9yd1EE42H0aDECP VlHpn8WIqAid8yMUJ0KwPHyvPhtMiNltuI/z/0o= X-Google-Smtp-Source: AK7set+NzYphreaaPb2/8/L2ZPrCjDuAOYGpGdE7vUn2WIBS/b2+J1JFFcAMobD4J3oikqDTLKB+Blkz7WfdncsE1XQ= X-Received: by 2002:a17:906:7e44:b0:7c0:beef:79e2 with SMTP id z4-20020a1709067e4400b007c0beef79e2mr248535ejr.148.1675225282965; Tue, 31 Jan 2023 20:21:22 -0800 (PST) MIME-Version: 1.0 References: <20230131133906.1956228-1-alexghiti@rivosinc.com> <20230131133906.1956228-5-alexghiti@rivosinc.com> In-Reply-To: <20230131133906.1956228-5-alexghiti@rivosinc.com> From: Bin Meng Date: Wed, 1 Feb 2023 12:21:11 +0800 Message-ID: Subject: Re: [PATCH v9 4/5] riscv: Introduce satp mode hw capabilities To: Alexandre Ghiti Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Andrew Jones , Frank Chang , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Content-Type: text/plain; charset="UTF-8" Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 01 Feb 2023 04:21:27 -0000 On Tue, Jan 31, 2023 at 10:41 PM Alexandre Ghiti wrote: > > Currently, the max satp mode is set with the only constraint that it must be > implemented in QEMU, i.e. set in valid_vm_1_10_[32|64]. > > But we actually need to add another level of constraint: what the hw is > actually capable of, because currently, a linux booting on a sifive-u54 > boots in sv57 mode which is incompatible with the cpu's sv39 max > capability. > > So add a new bitmap to RISCVSATPMap which contains this capability and > initialize it in every XXX_cpu_init. > > Finally: > - valid_vm_1_10_[32|64] constrains which satp mode the CPU can use > - the CPU hw capabilities constrains what the user may select > - the user's selection then constrains what's available to the guest > OS. > > Signed-off-by: Alexandre Ghiti > Reviewed-by: Andrew Jones > --- > target/riscv/cpu.c | 79 +++++++++++++++++++++++++++++++--------------- > target/riscv/cpu.h | 8 +++-- > 2 files changed, 60 insertions(+), 27 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 3a7a1746aa..6dd76355ec 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -292,26 +292,36 @@ const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) > g_assert_not_reached(); > } > > -/* Sets the satp mode to the max supported */ > -static void set_satp_mode_default_map(RISCVCPU *cpu) > +static void set_satp_mode_max_supported(RISCVCPU *cpu, > + uint8_t satp_mode) > { > bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > + const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > > - if (riscv_feature(&cpu->env, RISCV_FEATURE_MMU)) { > - cpu->cfg.satp_mode.map |= > - (1 << satp_mode_from_str(rv32 ? "sv32" : "sv57")); > - } else { > - cpu->cfg.satp_mode.map |= (1 << satp_mode_from_str("mbare")); > + for (int i = 0; i <= satp_mode; ++i) { > + if (valid_vm[i]) { > + cpu->cfg.satp_mode.supported |= (1 << i); > + } > } > } > > +/* Set the satp mode to the max supported */ > +static void set_satp_mode_default_map(RISCVCPU *cpu) > +{ > + cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; > +} > + > static void riscv_any_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > #if defined(TARGET_RISCV32) > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > + set_satp_mode_max_supported(cpu, VM_1_10_SV32); > #elif defined(TARGET_RISCV64) > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); > + set_satp_mode_max_supported(cpu, VM_1_10_SV57); > #endif > set_priv_version(env, PRIV_VERSION_1_12_0); > register_cpu_props(obj); > @@ -321,18 +331,24 @@ static void riscv_any_cpu_init(Object *obj) > static void rv64_base_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > /* We set this in the realise function */ > set_misa(env, MXL_RV64, 0); > register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > + set_satp_mode_max_supported(cpu, VM_1_10_SV57); > } > > static void rv64_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > + set_satp_mode_max_supported(cpu, VM_1_10_SV39); > } > > static void rv64_sifive_e_cpu_init(Object *obj) > @@ -343,6 +359,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) > set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > } > > static void rv128_base_cpu_init(Object *obj) > @@ -354,28 +371,36 @@ static void rv128_base_cpu_init(Object *obj) > exit(EXIT_FAILURE); > } > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); nits: for consistency with other cpu_init, needs a blank line after this > /* We set this in the realise function */ > set_misa(env, MXL_RV128, 0); > register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > + set_satp_mode_max_supported(cpu, VM_1_10_SV57); > } > #else > static void rv32_base_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > /* We set this in the realise function */ > set_misa(env, MXL_RV32, 0); > register_cpu_props(obj); > /* Set latest version of privileged specification */ > set_priv_version(env, PRIV_VERSION_1_12_0); > + set_satp_mode_max_supported(cpu, VM_1_10_SV32); > } > > static void rv32_sifive_u_cpu_init(Object *obj) > { > CPURISCVState *env = &RISCV_CPU(obj)->env; > + RISCVCPU *cpu = RISCV_CPU(obj); > + > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > + set_satp_mode_max_supported(cpu, VM_1_10_SV32); > } > > static void rv32_sifive_e_cpu_init(Object *obj) > @@ -386,6 +411,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > } > > static void rv32_ibex_cpu_init(Object *obj) > @@ -396,6 +422,7 @@ static void rv32_ibex_cpu_init(Object *obj) > set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_11_0); > cpu->cfg.mmu = false; > + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > cpu->cfg.epmp = true; > } > > @@ -407,6 +434,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) > set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); > set_priv_version(env, PRIV_VERSION_1_10_0); > cpu->cfg.mmu = false; > + set_satp_mode_max_supported(cpu, VM_1_10_MBARE); > } > #endif > > @@ -698,8 +726,9 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) > static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > { > bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; > - const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; > - uint8_t satp_mode_max; > + uint8_t satp_mode_map_max; > + uint8_t satp_mode_supported_max = > + satp_mode_max_from_map(cpu->cfg.satp_mode.supported); > > if (cpu->cfg.satp_mode.map == 0) { > if (cpu->cfg.satp_mode.init == 0) { > @@ -712,9 +741,10 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > * valid_vm_1_10_32/64. > */ > for (int i = 1; i < 16; ++i) { > - if ((cpu->cfg.satp_mode.init & (1 << i)) && valid_vm[i]) { > + if ((cpu->cfg.satp_mode.init & (1 << i)) && > + (cpu->cfg.satp_mode.supported & (1 << i))) { > for (int j = i - 1; j >= 0; --j) { > - if (valid_vm[j]) { > + if (cpu->cfg.satp_mode.supported & (1 << j)) { > cpu->cfg.satp_mode.map |= (1 << j); > break; > } > @@ -725,37 +755,36 @@ static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) > } > } > > - /* Make sure the configuration asked is supported by qemu */ > - for (int i = 0; i < 16; ++i) { > - if ((cpu->cfg.satp_mode.map & (1 << i)) && !valid_vm[i]) { > - error_setg(errp, "satp_mode %s is not valid", > - satp_mode_str(i, rv32)); > - return; > - } > + satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > + > + /* Make sure the user asked for a supported configuration (HW and qemu) */ > + if (satp_mode_map_max > satp_mode_supported_max) { > + error_setg(errp, "satp_mode %s is higher than hw max capability %s", > + satp_mode_str(satp_mode_map_max, rv32), > + satp_mode_str(satp_mode_supported_max, rv32)); > + return; > } > > /* > * Make sure the user did not ask for an invalid configuration as per > * the specification. > */ > - satp_mode_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); > - > if (!rv32) { > - for (int i = satp_mode_max - 1; i >= 0; --i) { > + for (int i = satp_mode_map_max - 1; i >= 0; --i) { > if (!(cpu->cfg.satp_mode.map & (1 << i)) && > (cpu->cfg.satp_mode.init & (1 << i)) && > - valid_vm[i]) { > + (cpu->cfg.satp_mode.supported & (1 << i))) { > error_setg(errp, "cannot disable %s satp mode if %s " > "is enabled", satp_mode_str(i, false), > - satp_mode_str(satp_mode_max, false)); > + satp_mode_str(satp_mode_map_max, false)); > return; > } > } > } > > /* Finally expand the map so that all valid modes are set */ > - for (int i = satp_mode_max - 1; i >= 0; --i) { > - if (valid_vm[i]) { > + for (int i = satp_mode_map_max - 1; i >= 0; --i) { > + if (cpu->cfg.satp_mode.supported & (1 << i)) { > cpu->cfg.satp_mode.map |= (1 << i); > } > } > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index e37177db5c..b591122099 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -416,13 +416,17 @@ struct RISCVCPUClass { > > /* > * map is a 16-bit bitmap: the most significant set bit in map is the maximum > - * satp mode that is supported. > + * satp mode that is supported. It may be chosen by the user and must respect > + * what qemu implements (valid_1_10_32/64) and what the hw is capable of > + * (supported bitmap below). > * > * init is a 16-bit bitmap used to make sure the user selected a correct > * configuration as per the specification. > + * > + * supported is a 16-bit bitmap used to reflect the hw capabilities. > */ > typedef struct { > - uint16_t map, init; > + uint16_t map, init, supported; > } RISCVSATPMap; > > struct RISCVCPUConfig { > -- Otherwise, Reviewed-by: Bin Meng