[Savannah-hackers] savannah.gnu.org: submission of vhdl-posix: POSIX for VHDL

[mvo]

A package was submitted to savannah.gnu.org.
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Marius Vollmer <address@hidden> described the package as follows:
License: lgpl
Other License: 
Package: vhdl-posix: POSIX for VHDL
System name: vhdl-posix
This package does NOT want to apply for inclusion in the GNU project

This project aims to provides support for accessing POSIX features
from VHDL.  VHDL is a special purpose language based on ADA that has,
in addition to normal sequential language features, support for
describing concurrent processes and static connection structures
between these processes.

Besides describing hardware, VHDL is also used to write programs that
test this hardware.  While VHDL has all that is necessary for
describing hardware (well, it lacks good abstraction facilities...),
it lacks useful interfaces to the operating system that could be of
use in test programs, or for other parts of a simulation that aren\'t
intended to model hardware.

This is where this project wants to help out.  Having access to POSIX
features from VHDL would allow one to write VHDL programs that
implement network serves or clients, inspect their environment,
perform more advanced I/O (i.e. with binary files), or do some form of
OS process management.

One application would be to start an external program that implements
part of the simulation (for example, a instruction level simulator for
a microcontroller in a larger system) and communicate with it using
sockets.  Another example would be to connect GDB to a simulated
processor via GDB\'s remote protocol.


VHDL itself does not yet offer any features for interfacing with
foreign code, but most implementations of VHDL have support for this,
each in its own incompatible form.  Thus, this project will be
important in providing the non-portable busy-work needed to present a
portable POSIX interface to VHDL code.

The aim is to implement a general framework that allows the
specification of ferign functions at a high level, and to
automatically generate the glue code for the individual VHDL
implementations from this.