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qemu-riscv (date)
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Last Modified: Sun Jul 31 2022 00:35:01 -0400
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July 31, 2022
Re: [PATCH v11 1/6] target/riscv: Add sscofpmf extension support
,
Atish Kumar Patra
,
00:35
Re: [PATCH v11 1/6] target/riscv: Add sscofpmf extension support
,
Rahul Pathak
,
00:11
July 29, 2022
Re: [PATCH v3 03/11] goldfish_rtc: Add big-endian property
,
Richard Henderson
,
19:39
[PATCH v3 03/11] goldfish_rtc: Add big-endian property
,
Stafford Horne
,
19:06
Re: [PATCH v6 3/5] target/riscv: smstateen check for fcsr
,
Mayuresh Chitale
,
08:29
July 28, 2022
Re: [PATCH v3 1/5] device_tree: add qemu_fdt_setprop_strings() helper
,
Ben Dooks
,
06:41
Re: [PATCH v3 1/5] device_tree: add qemu_fdt_setprop_strings() helper
,
Andrew Jones
,
05:22
Re: [PATCH v6 3/5] target/riscv: smstateen check for fcsr
,
Ben Dooks
,
04:10
Re: [PATCH v6 2/5] target/riscv: smstateen check for h/senvcfg
,
Weiwei Li
,
04:00
Re: [PATCH v6 3/5] target/riscv: smstateen check for fcsr
,
Weiwei Li
,
03:38
Re: [PATCH v6 2/5] target/riscv: smstateen check for h/senvcfg
,
Mayuresh Chitale
,
02:41
Re: [PATCH v6 3/5] target/riscv: smstateen check for fcsr
,
Mayuresh Chitale
,
02:16
Re: fu740 target
,
Alistair Francis
,
02:14
Re: [PATCH v6 1/5] target/riscv: Add smstateen support
,
Mayuresh Chitale
,
01:40
July 27, 2022
Re: [PATCH v11 2/6] target/riscv: Simplify counter predicate function
,
Weiwei Li
,
20:56
Re: [PATCH v11 5/6] target/riscv: Update the privilege field for sscofpmf CSRs
,
Atish Kumar Patra
,
18:51
Re: add qemu_fdt_setprop_strings() and use it in most places
,
Ben Dooks
,
18:48
[PATCH v3 5/5] hw/arm: change to use qemu_fdt_setprop_strings()
,
Ben Dooks
,
18:39
[PATCH v3 2/5] hw/riscv: use qemu_fdt_setprop_strings() for string arrays
,
Ben Dooks
,
18:39
[PATCH v3 3/5] hw/core: use qemu_fdt_setprop_strings()
,
Ben Dooks
,
18:39
[PATCH v3 1/5] device_tree: add qemu_fdt_setprop_strings() helper
,
Ben Dooks
,
18:39
[PATCH v3 4/5] hw/mips: use qemu_fdt_setprop_strings()
,
Ben Dooks
,
18:39
add qemu_fdt_setprop_strings() and use it in most places
,
Ben Dooks
,
18:39
Re: [PATCH v11 2/6] target/riscv: Simplify counter predicate function
,
Atish Kumar Patra
,
17:40
Re: [PATCH v11 1/6] target/riscv: Add sscofpmf extension support
,
Atish Kumar Patra
,
17:33
Re: [PATCH] hw/intc: sifive_plic: Fix multi-socket plic configuraiton
,
Atish Kumar Patra
,
15:01
Re: fu740 target
,
Ben Dooks
,
11:26
Re: [PATCH] target/riscv: Ensure opcode is saved for every instruction
,
Richard Henderson
,
10:58
Re: fu740 target
,
Bin Meng
,
10:51
Re: fu740 target
,
Bin Meng
,
10:38
fu740 target
,
Ben Dooks
,
10:20
Re: [PATCH] hw/intc: sifive_plic: Fix multi-socket plic configuraiton
,
Alistair Francis
,
08:23
Re: [PATCH v11 2/6] target/riscv: Simplify counter predicate function
,
Weiwei Li
,
04:34
Re: [PATCH v11 5/6] target/riscv: Update the privilege field for sscofpmf CSRs
,
Weiwei Li
,
04:26
Re: [PATCH v11 6/6] target/riscv: Remove additional priv version check for mcountinhibit
,
Weiwei Li
,
04:23
Re: [PATCH v11 1/6] target/riscv: Add sscofpmf extension support
,
Weiwei Li
,
04:12
Re: [PATCH v11 4/6] hw/riscv: virt: Add PMU DT node to the device tree
,
Atish Kumar Patra
,
03:50
Re: [PATCH] hw/intc: sifive_plic: Fix multi-socket plic configuraiton
,
Alistair Francis
,
03:39
Re: [PATCH v11 4/6] hw/riscv: virt: Add PMU DT node to the device tree
,
Sunil V L
,
03:27
[PATCH v11 6/6] target/riscv: Remove additional priv version check for mcountinhibit
,
Atish Patra
,
02:49
[PATCH v11 5/6] target/riscv: Update the privilege field for sscofpmf CSRs
,
Atish Patra
,
02:49
[PATCH v11 4/6] hw/riscv: virt: Add PMU DT node to the device tree
,
Atish Patra
,
02:49
[PATCH v11 1/6] target/riscv: Add sscofpmf extension support
,
Atish Patra
,
02:49
[PATCH v11 2/6] target/riscv: Simplify counter predicate function
,
Atish Patra
,
02:49
[PATCH v11 3/6] target/riscv: Add few cache related PMU events
,
Atish Patra
,
02:49
[PATCH v11 0/6] Improve PMU support
,
Atish Patra
,
02:49
Re: [PATCH] target/riscv: Ensure opcode is saved for every instruction
,
Anup Patel
,
00:06
July 26, 2022
Re: [PATCH] target/riscv: Ensure opcode is saved for every instruction
,
Richard Henderson
,
23:55
[PATCH] target/riscv: Ensure opcode is saved for every instruction
,
Anup Patel
,
23:26
Re: [PATCH] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3~31{h}
,
Weiwei Li
,
21:52
Re: [PATCH] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3~31{h}
,
Atish Patra
,
19:34
Re: [PATCH v10 04/12] target/riscv: pmu: Make number of counters configurable
,
Atish Patra
,
18:20
Re: [PATCH v10 11/12] hw/riscv: virt: Add PMU DT node to the device tree
,
Atish Patra
,
17:51
Re: [PATCH v6 1/3] hw/intc: Move mtimer/mtimecmp to aclint
,
Atish Patra
,
01:44
July 25, 2022
Re: How to read RISC-V mcycle CSR from Linux userspace app?
,
Bin Meng
,
21:20
Re: [PATCH] hw/intc: sifive_plic: Fix multi-socket plic configuraiton
,
Atish Kumar Patra
,
18:31
How to read RISC-V mcycle CSR from Linux userspace app?
,
Maxim Blinov
,
12:58
Re: [PATCH] target/riscv: Support SW update of PTE A/D bits and Ssptwad extension
,
Jim Shu
,
11:23
Re: [PATCH v6 3/5] target/riscv: smstateen check for fcsr
,
Weiwei Li
,
03:24
Re: [PATCH v6 1/5] target/riscv: Add smstateen support
,
Weiwei Li
,
03:11
Re: [PATCH v5 0/1] target/riscv: Add Zihintpause support
,
Alistair Francis
,
00:39
July 24, 2022
[PATCH v5 1/1] target/riscv: Add Zihintpause support
,
Dao Lu
,
23:47
[PATCH v5 0/1] target/riscv: Add Zihintpause support
,
Dao Lu
,
23:47
Re: [PATCH] hw/intc: sifive_plic: Fix multi-socket plic configuraiton
,
Alistair Francis
,
21:14
Re: [PATCH v6 3/5] target/riscv: smstateen check for fcsr
,
Mayuresh Chitale
,
11:49
Re: [PATCH v6 1/5] target/riscv: Add smstateen support
,
Mayuresh Chitale
,
11:40
July 23, 2022
Re: [PATCH v6 1/3] hw/intc: Move mtimer/mtimecmp to aclint
,
Andrew Jones
,
05:43
[PATCH] hw/intc: sifive_plic: Fix multi-socket plic configuraiton
,
Atish Patra
,
05:04
July 21, 2022
Re: [PATCH v6 5/5] target/riscv: smstateen knobs
,
Weiwei Li
,
21:47
Re: [PATCH v6 4/5] target/riscv: smstateen check for AIA/IMSIC
,
Weiwei Li
,
21:45
Re: [PATCH v6 3/5] target/riscv: smstateen check for fcsr
,
Weiwei Li
,
21:42
[PATCH v6 3/3] target/riscv: Add vstimecmp support
,
Atish Patra
,
21:01
[PATCH v6 2/3] target/riscv: Add stimecmp support
,
Atish Patra
,
21:01
[PATCH v6 1/3] hw/intc: Move mtimer/mtimecmp to aclint
,
Atish Patra
,
21:01
[PATCH v6 0/3] Implement Sstc extension
,
Atish Patra
,
21:01
Re: [PATCH v6 2/5] target/riscv: smstateen check for h/senvcfg
,
Weiwei Li
,
20:45
Re: [PATCH v6 1/5] target/riscv: Add smstateen support
,
Weiwei Li
,
20:31
Re: [PATCH v4 1/1] target/riscv: Add Zihintpause support
,
Dao Lu
,
13:19
[PATCH v6 4/5] target/riscv: smstateen check for AIA/IMSIC
,
Mayuresh Chitale
,
11:32
[PATCH v6 5/5] target/riscv: smstateen knobs
,
Mayuresh Chitale
,
11:32
[PATCH v6 3/5] target/riscv: smstateen check for fcsr
,
Mayuresh Chitale
,
11:32
[PATCH v6 2/5] target/riscv: smstateen check for h/senvcfg
,
Mayuresh Chitale
,
11:32
[PATCH v6 1/5] target/riscv: Add smstateen support
,
Mayuresh Chitale
,
11:32
[PATCH v6 0/5] RISC-V Smstateen support
,
Mayuresh Chitale
,
11:32
Re: [PATCH v4 1/1] target/riscv: Add Zihintpause support
,
Alistair Francis
,
01:31
Re: [PATCH v4 1/1] target/riscv: Add Zihintpause support
,
Alistair Francis
,
01:02
Re: [PATCH] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3~31{h}
,
Alistair Francis
,
00:32
July 20, 2022
Re: [PATCH qemu v6 00/10] Add mask agnostic behavior for rvv instructions
,
Alistair Francis
,
22:31
Re: [PATCH qemu v6 10/10] target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask agnostic behavior
,
Alistair Francis
,
20:24
Re: [PATCH qemu v6 09/10] target/riscv: rvv: Add mask agnostic for vector permutation instructions
,
Alistair Francis
,
20:24
Re: [PATCH qemu v6 08/10] target/riscv: rvv: Add mask agnostic for vector mask instructions
,
Alistair Francis
,
20:23
Re: [PATCH qemu v6 07/10] target/riscv: rvv: Add mask agnostic for vector floating-point instructions
,
Alistair Francis
,
20:21
Re: [PATCH qemu v6 06/10] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions
,
Alistair Francis
,
20:20
Re: [PATCH qemu v6 05/10] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions
,
Alistair Francis
,
20:17
Re: [PATCH qemu v6 04/10] target/riscv: rvv: Add mask agnostic for vector integer shift instructions
,
Alistair Francis
,
20:14
Re: [PATCH qemu v6 03/10] target/riscv: rvv: Add mask agnostic for vx instructions
,
Alistair Francis
,
20:12
Re: [PATCH qemu v6 02/10] target/riscv: rvv: Add mask agnostic for vector load / store instructions
,
Alistair Francis
,
20:11
Re: [PATCH qemu v6 01/10] target/riscv: rvv: Add mask agnostic for vv instructions
,
Alistair Francis
,
20:09
Re: [PATCH v5 2/3] target/riscv: Add stimecmp support
,
Alistair Francis
,
20:05
Re: [PATCH v5 2/3] target/riscv: Add stimecmp support
,
Atish Patra
,
15:32
Re: [PATCH] target/riscv: Support SW update of PTE A/D bits and Ssptwad extension
,
Alistair Francis
,
01:30
July 19, 2022
Re: [PATCH] target/riscv: Support SW update of PTE A/D bits and Ssptwad extension
,
Anup Patel
,
23:52
Re: [PATCH] target/riscv: Support SW update of PTE A/D bits and Ssptwad extension
,
Jim Shu
,
19:33
Re: [PATCH] docs: List kvm as a supported accelerator on RISC-V
,
Thomas Huth
,
04:39
Re: [PATCH 1/1] target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V
,
Alistair Francis
,
03:06
Re: [PATCH] roms/opensbi: Upgrade from v1.0 to v1.1
,
Alistair Francis
,
02:56
Re: [PATCH 1/1] target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V
,
Alistair Francis
,
02:56
Re: [PATCH] roms/opensbi: Upgrade from v1.0 to v1.1
,
Alistair Francis
,
02:52
July 18, 2022
Re: [RFC PATCH v5 1/4] target/riscv: Add smstateen support
,
Weiwei Li
,
21:03
Re: [PATCH V3 0/6] Improve the U/S/H extension related check
,
Alistair Francis
,
20:24
Re: [PATCH V3 5/6] target/riscv: Fix checks in hmode/hmode32
,
Alistair Francis
,
19:10
Re: [PATCH v4 1/1] target/riscv: Add Zihintpause support
,
Dao Lu
,
14:01
Re: [RFC PATCH v5 1/4] target/riscv: Add smstateen support
,
Mayuresh Chitale
,
11:38
Re: [PATCH V3 6/6] target/riscv: Simplify the check in hmode to resue the check in riscv_csrrw_check
,
Weiwei Li
,
10:31
Re: [PATCH V3 6/6] target/riscv: Simplify the check in hmode to resue the check in riscv_csrrw_check
,
Andrew Jones
,
09:47
[PATCH V3 2/6] target/riscv: H extension depends on I extension
,
Weiwei Li
,
09:10
[PATCH V3 6/6] target/riscv: Simplify the check in hmode to resue the check in riscv_csrrw_check
,
Weiwei Li
,
09:10
[PATCH V3 3/6] target/riscv: Fix checkpatch warning may triggered in csr_ops table
,
Weiwei Li
,
09:10
[PATCH V3 1/6] target/riscv: Add check for supported privilege mode combinations
,
Weiwei Li
,
09:10
[PATCH V3 5/6] target/riscv: Fix checks in hmode/hmode32
,
Weiwei Li
,
09:10
[PATCH V3 4/6] target/riscv: Add check for csrs existed with U extension
,
Weiwei Li
,
09:10
[PATCH V3 0/6] Improve the U/S/H extension related check
,
Weiwei Li
,
09:10
Re: [PATCH v2 1/6] target/riscv: add check for supported privilege modes conbinations
,
Weiwei Li
,
07:36
Re: [PATCH v2 4/6] target/riscv: add check for csrs existed with U extension
,
Andrew Jones
,
05:50
Re: [PATCH v2 6/6] target/riscv: simplify the check in hmode to resue the check in riscv_csrrw_check
,
Andrew Jones
,
05:37
Re: [PATCH v2 5/6] target/riscv: fix checks in hmode/hmode32
,
Andrew Jones
,
05:26
Re: [PATCH v2 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table
,
Andrew Jones
,
05:12
Re: [PATCH v2 2/6] target/riscv: H extension depends on I extension
,
Andrew Jones
,
05:05
Re: [PATCH v2 1/6] target/riscv: add check for supported privilege modes conbinations
,
Andrew Jones
,
05:02
Re: [PATCH] target/riscv: Support SW update of PTE A/D bits and Ssptwad extension
,
Anup Patel
,
00:04
July 17, 2022
[PATCH] target/riscv: Support SW update of PTE A/D bits and Ssptwad extension
,
Jim Shu
,
23:53
Re: [PATCH v2 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table
,
Alistair Francis
,
21:48
Re: [PATCH v10 08/12] target/riscv: Add sscofpmf extension support
,
Alistair Francis
,
21:24
Re: [PATCH] RISC-V: Allow both Zmmul and M
,
Alistair Francis
,
21:20
Re: [PATCH] RISC-V: Allow both Zmmul and M
,
Alistair Francis
,
20:44
[PATCH 0/1] Fix pointer masking functionality for RISC-V
,
Alexey Baturo
,
06:16
[PATCH 1/1] target/riscv: Fix typo and restore Pointer Masking functionality for RISC-V
,
Alexey Baturo
,
06:16
July 14, 2022
[PATCH] RISC-V: Allow both Zmmul and M
,
Palmer Dabbelt
,
14:06
Re: [PATCH v10 12/12] target/riscv: Update the privilege field for sscofpmf CSRs
,
Heiko Stübner
,
06:29
Re: [PATCH v10 11/12] hw/riscv: virt: Add PMU DT node to the device tree
,
Heiko Stübner
,
06:27
Re: [PATCH v10 10/12] target/riscv: Add few cache related PMU events
,
Heiko Stübner
,
05:55
Re: [PATCH v10 09/12] target/riscv: Simplify counter predicate function
,
Heiko Stübner
,
05:55
Re: [PATCH v10 08/12] target/riscv: Add sscofpmf extension support
,
Heiko Stübner
,
05:54
July 13, 2022
[PATCH] roms/opensbi: Upgrade from v1.0 to v1.1
,
Bin Meng
,
05:06
July 12, 2022
[PATCH v2 6/6] target/riscv: simplify the check in hmode to resue the check in riscv_csrrw_check
,
Weiwei Li
,
02:33
[PATCH v2 2/6] target/riscv: H extension depends on I extension
,
Weiwei Li
,
02:33
[PATCH v2 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table
,
Weiwei Li
,
02:33
[PATCH v2 1/6] target/riscv: add check for supported privilege modes conbinations
,
Weiwei Li
,
02:33
[PATCH v2 4/6] target/riscv: add check for csrs existed with U extension
,
Weiwei Li
,
02:33
[PATCH v2 5/6] target/riscv: fix checks in hmode/hmode32
,
Weiwei Li
,
02:33
[PATCH v2 0/6] Improve the U/S/H extension related check
,
Weiwei Li
,
02:33
Re: [PATCH] target/riscv: move zmmul out of the experimental properties
,
Alistair Francis
,
01:37
Re: [PATCH] target/riscv: move zmmul out of the experimental properties
,
Alistair Francis
,
01:18
Re: [PATCH v2] target/riscv: fix shifts shamt value for rv128c
,
Alistair Francis
,
01:10
July 11, 2022
Re: [PATCH v2] target/riscv: fix shifts shamt value for rv128c
,
Richard Henderson
,
23:47
Re: [PATCH v2] target/riscv: fix shifts shamt value for rv128c
,
Frédéric Pétrot
,
15:55
Re: [PATCH v2] target/riscv: fix shifts shamt value for rv128c
,
Richard Henderson
,
12:12
Re: [PATCH 5/6] target/riscv: fix checks in hmode/hmode32
,
Weiwei Li
,
08:45
Re: [PATCH 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table
,
Weiwei Li
,
08:41
Re: [PATCH 1/2] util/log: Add vu to dump content of vector unit
,
Víctor Colombo
,
07:54
Re: [PATCH 1/2] util/log: Add vu to dump content of vector unit
,
Frank Chang
,
04:15
Re: [PATCH 2/2] target/riscv: Auto set elen from vector extension by default
,
Frank Chang
,
04:13
Re: [PATCH qemu v6 00/10] Add mask agnostic behavior for rvv instructions
,
eop Chen
,
03:07
Re: [PATCH 6/6] target/riscv: simplify the check in hmode to resue the check in riscv_csrrw_check
,
Alistair Francis
,
02:50
Re: [PATCH 5/6] target/riscv: fix checks in hmode/hmode32
,
Alistair Francis
,
02:47
Re: [PATCH 4/6] target/riscv: add check for csrs existed with U extension
,
Alistair Francis
,
02:43
Re: [PATCH 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table
,
Alistair Francis
,
02:41
Re: [PATCH 2/6] target/riscv: H extension depends on I extension
,
Alistair Francis
,
01:30
Re: [PATCH 1/6] target/riscv: add check for supported privilege modes conbinations
,
Alistair Francis
,
01:29
July 10, 2022
Re: [PATCH v2] target/riscv: fix shifts shamt value for rv128c
,
Weiwei Li
,
08:36
[PATCH v2] target/riscv: fix shifts shamt value for rv128c
,
Frédéric Pétrot
,
07:05
[PATCH] target/riscv: move zmmul out of the experimental properties
,
Weiwei Li
,
06:16
[PATCH 3/6] target/riscv: fix checkpatch warning may triggered in csr_ops table
,
Weiwei Li
,
04:24
[PATCH 6/6] target/riscv: simplify the check in hmode to resue the check in riscv_csrrw_check
,
Weiwei Li
,
04:24
[PATCH 0/6] Improve the U/S/H extension related check
,
Weiwei Li
,
04:24
[PATCH 4/6] target/riscv: add check for csrs existed with U extension
,
Weiwei Li
,
04:24
[PATCH 2/6] target/riscv: H extension depends on I extension
,
Weiwei Li
,
04:24
[PATCH 5/6] target/riscv: fix checks in hmode/hmode32
,
Weiwei Li
,
04:24
[PATCH 1/6] target/riscv: add check for supported privilege modes conbinations
,
Weiwei Li
,
04:24
July 09, 2022
Re: [PATCH] target/riscv: fix right shifts shamt value for rv128c
,
Frédéric Pétrot
,
18:24
Re: [PATCH 2/2] target/riscv: Auto set elen from vector extension by default
,
Weiwei Li
,
05:54
Re: [PATCH 1/2] target/riscv: Lower bound of VLEN is 32, and check VLEN >= ELEN
,
Weiwei Li
,
05:48
Re: [PATCH 2/2] target/riscv: Implement dump content of vector register
,
Weiwei Li
,
05:10
Re: [PATCH] target/riscv: fix right shifts shamt value for rv128c
,
Weiwei Li
,
04:53
Re: [PATCH 1/2] target/riscv: Lower bound of VLEN is 32, and check VLEN >= ELEN
,
Weiwei Li
,
04:31
Re: [PATCH 2/2] target/riscv: Auto set elen from vector extension by default
,
Weiwei Li
,
04:12
July 08, 2022
[PATCH] target/riscv: fix right shifts shamt value for rv128c
,
Frédéric Pétrot
,
11:01
[PATCH 2/2] target/riscv: Implement dump content of vector register
,
Kito Cheng
,
04:57
[PATCH 1/2] util/log: Add vu to dump content of vector unit
,
Kito Cheng
,
04:57
[PATCH 2/2] target/riscv: Auto set elen from vector extension by default
,
Kito Cheng
,
03:39
[PATCH 1/2] target/riscv: Lower bound of VLEN is 32, and check VLEN >= ELEN
,
Kito Cheng
,
03:39
July 07, 2022
Re: [RFC PATCH v5 1/4] target/riscv: Add smstateen support
,
Weiwei Li
,
19:45
Re: [RFC PATCH v5 2/4] target/riscv: smstateen check for h/senvcfg
,
Weiwei Li
,
19:36
Re: [RFC PATCH v5 2/4] target/riscv: smstateen check for h/senvcfg
,
Mayuresh Chitale
,
13:20
Re: [RFC PATCH v5 1/4] target/riscv: Add smstateen support
,
Mayuresh Chitale
,
12:53
Re: [RFC PATCH v5 4/4] target/riscv: smstateen check for AIA/IMSIC
,
Mayuresh Chitale
,
12:22
Re: [RFC PATCH v5 3/4] target/riscv: smstateen check for fcsr
,
Mayuresh Chitale
,
12:12
Re: [RFC PATCH v5 1/4] target/riscv: Add smstateen support
,
Mayuresh Chitale
,
11:42
July 06, 2022
Re: [PATCH v2 00/18] Make block-backend-io.h API more consistent
,
Hanna Reitz
,
05:46
Re: [PATCH v2 17/18] block: Reorganize some declarations in block-backend-io.h
,
Hanna Reitz
,
05:26
Re: [PATCH v2 01/18] block: Make blk_{pread,pwrite}() return 0 on success
,
Hanna Reitz
,
04:37
July 05, 2022
[PATCH v4 0/1] target/riscv: Add Zihintpause support
,
Dao Lu
,
13:49
[PATCH v4 1/1] target/riscv: Add Zihintpause support
,
Dao Lu
,
13:49
[PATCH v2 18/18] block: Remove remaining unused symbols in coroutines.h
,
Alberto Faria
,
12:18
[PATCH v2 16/18] block: Add blk_co_truncate()
,
Alberto Faria
,
12:17
[PATCH v2 17/18] block: Reorganize some declarations in block-backend-io.h
,
Alberto Faria
,
12:17
[PATCH v2 15/18] block: Add blk_co_ioctl()
,
Alberto Faria
,
12:17
[PATCH v2 14/18] block: Implement blk_flush() using generated_co_wrapper
,
Alberto Faria
,
12:17
[PATCH v2 13/18] block: Implement blk_pdiscard() using generated_co_wrapper
,
Alberto Faria
,
12:17
[PATCH v2 12/18] block: Implement blk_pwrite_zeroes() using generated_co_wrapper
,
Alberto Faria
,
12:17
[PATCH v2 11/18] block: Add blk_co_pwrite_compressed()
,
Alberto Faria
,
12:17
[PATCH v2 09/18] block: Export blk_pwritev_part() in block-backend-io.h
,
Alberto Faria
,
12:17
[PATCH v2 10/18] block: Change blk_pwrite_compressed() param order
,
Alberto Faria
,
12:16
[PATCH v2 08/18] block: Add blk_[co_]preadv_part()
,
Alberto Faria
,
12:16
[PATCH v2 07/18] block: Add blk_{preadv,pwritev}()
,
Alberto Faria
,
12:16
[PATCH v2 06/18] block: Implement blk_{pread, pwrite}() using generated_co_wrapper
,
Alberto Faria
,
12:16
[PATCH v2 05/18] block: Make blk_co_pwrite() take a const buffer
,
Alberto Faria
,
12:16
[PATCH v2 04/18] block: Make 'bytes' param of blk_{pread, pwrite}() an int64_t
,
Alberto Faria
,
12:16
[PATCH v2 03/18] block: Change blk_{pread,pwrite}() param order
,
Alberto Faria
,
12:16
[PATCH v2 02/18] block: Add a 'flags' param to blk_pread()
,
Alberto Faria
,
12:16
[PATCH v2 01/18] block: Make blk_{pread, pwrite}() return 0 on success
,
Alberto Faria
,
12:15
[PATCH v2 00/18] Make block-backend-io.h API more consistent
,
Alberto Faria
,
12:15
Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
,
Jason A. Donenfeld
,
09:36
Re: [PATCH v10 09/12] target/riscv: Simplify counter predicate function
,
Weiwei Li
,
04:41
Re: [PATCH v10 04/12] target/riscv: pmu: Make number of counters configurable
,
Weiwei Li
,
04:17
Re: [PATCH v10 09/12] target/riscv: Simplify counter predicate function
,
Atish Kumar Patra
,
04:01
Re: [PATCH v10 04/12] target/riscv: pmu: Make number of counters configurable
,
Atish Kumar Patra
,
03:51
Re: [PATCH v10 08/12] target/riscv: Add sscofpmf extension support
,
Weiwei Li
,
03:49
Re: [PATCH v10 05/12] target/riscv: Implement mcountinhibit CSR
,
Atish Kumar Patra
,
03:47
Re: [PATCH v10 08/12] target/riscv: Add sscofpmf extension support
,
Atish Kumar Patra
,
03:37
Re: [PATCH v9 0/2] QEMU RISC-V nested virtualization fixes
,
Alistair Francis
,
01:38
July 04, 2022
Re: [PATCH v10 08/12] target/riscv: Add sscofpmf extension support
,
Weiwei Li
,
21:30
Re: [PATCH v10 04/12] target/riscv: pmu: Make number of counters configurable
,
Weiwei Li
,
20:38
Re: [PATCH v10 08/12] target/riscv: Add sscofpmf extension support
,
Weiwei Li
,
20:31
Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
,
Stafford Horne
,
16:48
Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
,
Stafford Horne
,
16:48
Re: [PATCH 01/18] block: Make blk_{pread, pwrite}() return 0 on success
,
Alberto Faria
,
12:21
Re: [PATCH v10 05/12] target/riscv: Implement mcountinhibit CSR
,
Weiwei Li
,
11:31
Re: [PATCH v10 04/12] target/riscv: pmu: Make number of counters configurable
,
Weiwei Li
,
11:26
Re: [PATCH 03/18] block: Change blk_{pread,pwrite}() param order
,
Hanna Reitz
,
11:21
Re: [PATCH v10 09/12] target/riscv: Simplify counter predicate function
,
Weiwei Li
,
11:19
Re: [PATCH 02/18] block: Add a 'flags' param to blk_pread()
,
Hanna Reitz
,
10:04
Re: [PATCH 01/18] block: Make blk_{pread,pwrite}() return 0 on success
,
Hanna Reitz
,
09:52
Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
,
Laurent Vivier
,
06:23
Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
,
Richard Henderson
,
06:21
Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
,
Laurent Vivier
,
06:16
Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
,
Richard Henderson
,
06:00
[PATCH v2 03/11] goldfish_rtc: Add endianness property
,
Stafford Horne
,
02:05
July 03, 2022
Re: [PATCH v2 03/11] goldfish_rtc: Add endianness property
,
Anup Patel
,
22:50
Re: [PATCH v9 1/2] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
dramforever
,
22:36
Re: [PATCH v9 1/2] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()
,
Alistair Francis
,
22:17
Re: [PATCH 00/18] Make block-backend-io.h API more consistent
,
Alberto Faria
,
18:22
July 02, 2022
Re: [PATCH 00/18] Make block-backend-io.h API more consistent
,
Paolo Bonzini
,
10:12
[PATCH] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3~31{h}
,
Weiwei Li
,
09:42
Re:[RFC PATCH v5 1/4] target/riscv: Add smstateen support
,
angell1518
,
06:35
Re:[RFC PATCH v5 2/4] target/riscv: smstateen check for h/senvcfg
,
angell1518
,
06:34
Re: [PATCH 1/2] target/riscv: Fixup MSECCFG minimum priv check
,
Alistair Francis
,
02:54
July 01, 2022
Re: [PATCH 2/2] target/riscv: Ibex: Support priv version 1.11
,
Bin Meng
,
08:33
Re: [PATCH 1/2] target/riscv: Fixup MSECCFG minimum priv check
,
Bin Meng
,
08:33
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