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[avr-libc-commit] [2108] 2010-03-22 Eric B.
|
From: |
Eric Weddington |
|
Subject: |
[avr-libc-commit] [2108] 2010-03-22 Eric B. |
|
Date: |
Tue, 23 Mar 2010 02:55:55 +0000 |
Revision: 2108
http://svn.sv.gnu.org/viewvc/?view=rev&root=avr-libc&revision=2108
Author: arcanum
Date: 2010-03-23 02:55:54 +0000 (Tue, 23 Mar 2010)
Log Message:
-----------
2010-03-22 Eric B. Weddington <address@hidden>
* include/avr/iox64a1u.h: New file.
Modified Paths:
--------------
trunk/avr-libc/ChangeLog
Added Paths:
-----------
trunk/avr-libc/include/avr/iox64a1u.h
Modified: trunk/avr-libc/ChangeLog
===================================================================
--- trunk/avr-libc/ChangeLog 2010-03-20 18:00:47 UTC (rev 2107)
+++ trunk/avr-libc/ChangeLog 2010-03-23 02:55:54 UTC (rev 2108)
@@ -1,3 +1,7 @@
+2010-03-22 Eric B. Weddington <address@hidden>
+
+ * include/avr/iox64a1u.h: New file.
+
2010-03-20 Eric B. Weddington <address@hidden>
* include/avr/fuse.h: Add definition of FUSES for XMEGA devices.
Added: trunk/avr-libc/include/avr/iox64a1u.h
===================================================================
--- trunk/avr-libc/include/avr/iox64a1u.h (rev 0)
+++ trunk/avr-libc/include/avr/iox64a1u.h 2010-03-23 02:55:54 UTC (rev
2108)
@@ -0,0 +1,7551 @@
+/* Copyright (c) 2010 Atmel Corporation
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+
+ * Neither the name of the copyright holders nor the names of
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE. */
+
+/* $Id$ */
+
+/* avr/iox64a1u.h - definitions for ATxmega64A1U */
+
+/* This file should only be included from <avr/io.h>, never directly. */
+
+#ifndef _AVR_IO_H_
+# error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+# define _AVR_IOXXX_H_ "iox64a1u.h"
+#else
+# error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_ATxmega64A1U_H_
+#define _AVR_ATxmega64A1U_H_ 1
+
+
+/* Ungrouped common registers */
+#define GPIOR0 _SFR_MEM8(0x0000) /* General Purpose IO Register 0 */
+#define GPIOR1 _SFR_MEM8(0x0001) /* General Purpose IO Register 1 */
+#define GPIOR2 _SFR_MEM8(0x0002) /* General Purpose IO Register 2 */
+#define GPIOR3 _SFR_MEM8(0x0003) /* General Purpose IO Register 3 */
+#define GPIOR4 _SFR_MEM8(0x0004) /* General Purpose IO Register 4 */
+#define GPIOR5 _SFR_MEM8(0x0005) /* General Purpose IO Register 5 */
+#define GPIOR6 _SFR_MEM8(0x0006) /* General Purpose IO Register 6 */
+#define GPIOR7 _SFR_MEM8(0x0007) /* General Purpose IO Register 7 */
+#define GPIOR8 _SFR_MEM8(0x0008) /* General Purpose IO Register 8 */
+#define GPIOR9 _SFR_MEM8(0x0009) /* General Purpose IO Register 9 */
+#define GPIORA _SFR_MEM8(0x000A) /* General Purpose IO Register 10 */
+#define GPIORB _SFR_MEM8(0x000B) /* General Purpose IO Register 11 */
+#define GPIORC _SFR_MEM8(0x000C) /* General Purpose IO Register 12 */
+#define GPIORD _SFR_MEM8(0x000D) /* General Purpose IO Register 13 */
+#define GPIORE _SFR_MEM8(0x000E) /* General Purpose IO Register 14 */
+#define GPIORF _SFR_MEM8(0x000F) /* General Purpose IO Register 15 */
+
+#define CCP _SFR_MEM8(0x0034) /* Configuration Change Protection */
+#define RAMPD _SFR_MEM8(0x0038) /* Ramp D */
+#define RAMPX _SFR_MEM8(0x0039) /* Ramp X */
+#define RAMPY _SFR_MEM8(0x003A) /* Ramp Y */
+#define RAMPZ _SFR_MEM8(0x003B) /* Ramp Z */
+#define EIND _SFR_MEM8(0x003C) /* Extended Indirect Jump */
+#define SPL _SFR_MEM8(0x003D) /* Stack Pointer Low */
+#define SPH _SFR_MEM8(0x003E) /* Stack Pointer High */
+#define SREG _SFR_MEM8(0x003F) /* Status Register */
+
+
+/* C Language Only */
+#if !defined (__ASSEMBLER__)
+
+#include <stdint.h>
+
+typedef volatile uint8_t register8_t;
+typedef volatile uint16_t register16_t;
+typedef volatile uint32_t register32_t;
+
+
+#ifdef _WORDREGISTER
+#undef _WORDREGISTER
+#endif
+#define _WORDREGISTER(regname) \
+ __extension__ union \
+ { \
+ register16_t regname; \
+ struct \
+ { \
+ register8_t regname ## L; \
+ register8_t regname ## H; \
+ }; \
+ }
+
+#ifdef _DWORDREGISTER
+#undef _DWORDREGISTER
+#endif
+#define _DWORDREGISTER(regname) \
+ __extension__ union \
+ { \
+ register32_t regname; \
+ struct \
+ { \
+ register8_t regname ## 0; \
+ register8_t regname ## 1; \
+ register8_t regname ## 2; \
+ register8_t regname ## 3; \
+ }; \
+ }
+
+
+/*
+==========================================================================
+IO Module Structures
+==========================================================================
+*/
+
+
+/*
+--------------------------------------------------------------------------
+VPORT - Virtual Ports
+--------------------------------------------------------------------------
+*/
+
+/* Virtual Port */
+typedef struct VPORT_struct
+{
+ register8_t DIR; /* I/O Port Data Direction */
+ register8_t OUT; /* I/O Port Output */
+ register8_t IN; /* I/O Port Input */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+} VPORT_t;
+
+
+/*
+--------------------------------------------------------------------------
+XOCD - On-Chip Debug System
+--------------------------------------------------------------------------
+*/
+
+/* On-Chip Debug System */
+typedef struct OCD_struct
+{
+ register8_t OCDR0; /* OCD Register 0 */
+ register8_t OCDR1; /* OCD Register 1 */
+} OCD_t;
+
+
+/* CCP signatures */
+typedef enum CCP_enum
+{
+ CCP_SPM_gc = (0x9D<<0), /* SPM Instruction Protection */
+ CCP_IOREG_gc = (0xD8<<0), /* IO Register Protection */
+} CCP_t;
+
+
+/*
+--------------------------------------------------------------------------
+CLK - Clock System
+--------------------------------------------------------------------------
+*/
+
+/* Clock System */
+typedef struct CLK_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t PSCTRL; /* Prescaler Control Register */
+ register8_t LOCK; /* Lock register */
+ register8_t RTCCTRL; /* RTC Control Register */
+ register8_t USBCTRL; /* USB Control Register */
+} CLK_t;
+
+/*
+--------------------------------------------------------------------------
+CLK - Clock System
+--------------------------------------------------------------------------
+*/
+
+/* Power Reduction */
+typedef struct PR_struct
+{
+ register8_t PRGEN; /* General Power Reduction */
+ register8_t PRPA; /* Power Reduction Port A */
+ register8_t PRPB; /* Power Reduction Port B */
+ register8_t PRPC; /* Power Reduction Port C */
+ register8_t PRPD; /* Power Reduction Port D */
+ register8_t PRPE; /* Power Reduction Port E */
+ register8_t PRPF; /* Power Reduction Port F */
+} PR_t;
+
+/* System Clock Selection */
+typedef enum CLK_SCLKSEL_enum
+{
+ CLK_SCLKSEL_RC2M_gc = (0x00<<0), /* Internal 2 MHz RC Oscillator */
+ CLK_SCLKSEL_RC32M_gc = (0x01<<0), /* Internal 32 MHz RC Oscillator */
+ CLK_SCLKSEL_RC32K_gc = (0x02<<0), /* Internal 32.768 kHz RC Oscillator */
+ CLK_SCLKSEL_XOSC_gc = (0x03<<0), /* External Crystal Oscillator or Clock
*/
+ CLK_SCLKSEL_PLL_gc = (0x04<<0), /* Phase Locked Loop */
+} CLK_SCLKSEL_t;
+
+/* Prescaler A Division Factor */
+typedef enum CLK_PSADIV_enum
+{
+ CLK_PSADIV_1_gc = (0x00<<2), /* Divide by 1 */
+ CLK_PSADIV_2_gc = (0x01<<2), /* Divide by 2 */
+ CLK_PSADIV_4_gc = (0x03<<2), /* Divide by 4 */
+ CLK_PSADIV_8_gc = (0x05<<2), /* Divide by 8 */
+ CLK_PSADIV_16_gc = (0x07<<2), /* Divide by 16 */
+ CLK_PSADIV_32_gc = (0x09<<2), /* Divide by 32 */
+ CLK_PSADIV_64_gc = (0x0B<<2), /* Divide by 64 */
+ CLK_PSADIV_128_gc = (0x0D<<2), /* Divide by 128 */
+ CLK_PSADIV_256_gc = (0x0F<<2), /* Divide by 256 */
+ CLK_PSADIV_512_gc = (0x11<<2), /* Divide by 512 */
+} CLK_PSADIV_t;
+
+/* Prescaler B and C Division Factor */
+typedef enum CLK_PSBCDIV_enum
+{
+ CLK_PSBCDIV_1_1_gc = (0x00<<0), /* Divide B by 1 and C by 1 */
+ CLK_PSBCDIV_1_2_gc = (0x01<<0), /* Divide B by 1 and C by 2 */
+ CLK_PSBCDIV_4_1_gc = (0x02<<0), /* Divide B by 4 and C by 1 */
+ CLK_PSBCDIV_2_2_gc = (0x03<<0), /* Divide B by 2 and C by 2 */
+} CLK_PSBCDIV_t;
+
+/* RTC Clock Source */
+typedef enum CLK_RTCSRC_enum
+{
+ CLK_RTCSRC_ULP_gc = (0x00<<1), /* 1.024 kHz from internal 32kHz ULP */
+ CLK_RTCSRC_TOSC_gc = (0x01<<1), /* 1.024 kHz from 32.768 kHz crystal
oscillator on TOSC */
+ CLK_RTCSRC_RCOSC_gc = (0x02<<1), /* 1.024 kHz from internal 32.768 kHz RC
oscillator */
+ CLK_RTCSRC_TOSC32_gc = (0x05<<1), /* 32.768 kHz from 32.768 kHz crystal
oscillator on TOSC */
+ CLK_RTCSRC_RCOSC32_gc = (0x06<<1), /* 32.768 kHz from internal 32.768 kHz
RC oscillator */
+ CLK_RTCSRC_EXTCLK_gc = (0x07<<1), /* External Clock from TOSC1 */
+} CLK_RTCSRC_t;
+
+/* USB Prescaler Division Factor */
+typedef enum CLK_USBPSDIV_enum
+{
+ CLK_USBPSDIV_1_gc = (0x00<<3), /* Divide by 1 */
+ CLK_USBPSDIV_2_gc = (0x01<<3), /* Divide by 2 */
+ CLK_USBPSDIV_4_gc = (0x02<<3), /* Divide by 4 */
+ CLK_USBPSDIV_8_gc = (0x03<<3), /* Divide by 8 */
+ CLK_USBPSDIV_16_gc = (0x04<<3), /* Divide by 16 */
+ CLK_USBPSDIV_32_gc = (0x05<<3), /* Divide by 32 */
+} CLK_USBPSDIV_t;
+
+/* USB Clock Source */
+typedef enum CLK_USBSRC_enum
+{
+ CLK_USBSRC_PLL_gc = (0x00<<1), /* PLL */
+} CLK_USBSRC_t;
+
+
+/*
+--------------------------------------------------------------------------
+SLEEP - Sleep Controller
+--------------------------------------------------------------------------
+*/
+
+/* Sleep Controller */
+typedef struct SLEEP_struct
+{
+ register8_t CTRL; /* Control Register */
+} SLEEP_t;
+
+/* Sleep Mode */
+typedef enum SLEEP_SMODE_enum
+{
+ SLEEP_SMODE_IDLE_gc = (0x00<<1), /* Idle mode */
+ SLEEP_SMODE_PDOWN_gc = (0x02<<1), /* Power-down Mode */
+ SLEEP_SMODE_PSAVE_gc = (0x03<<1), /* Power-save Mode */
+ SLEEP_SMODE_STDBY_gc = (0x06<<1), /* Standby Mode */
+ SLEEP_SMODE_ESTDBY_gc = (0x07<<1), /* Extended Standby Mode */
+} SLEEP_SMODE_t;
+
+
+/*
+--------------------------------------------------------------------------
+OSC - Oscillator
+--------------------------------------------------------------------------
+*/
+
+/* Oscillator */
+typedef struct OSC_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t XOSCCTRL; /* External Oscillator Control Register */
+ register8_t XOSCFAIL; /* Oscillator Failure Detection Register */
+ register8_t RC32KCAL; /* 32.768 kHz Internal Oscillator Calibration
Register */
+ register8_t PLLCTRL; /* PLL Control REgister */
+ register8_t DFLLCTRL; /* DFLL Control Register */
+} OSC_t;
+
+/* Oscillator Frequency Range */
+typedef enum OSC_FRQRANGE_enum
+{
+ OSC_FRQRANGE_04TO2_gc = (0x00<<6), /* 0.4 - 2 MHz */
+ OSC_FRQRANGE_2TO9_gc = (0x01<<6), /* 2 - 9 MHz */
+ OSC_FRQRANGE_9TO12_gc = (0x02<<6), /* 9 - 12 MHz */
+ OSC_FRQRANGE_12TO16_gc = (0x03<<6), /* 12 - 16 MHz */
+} OSC_FRQRANGE_t;
+
+/* External Oscillator Selection and Startup Time */
+typedef enum OSC_XOSCSEL_enum
+{
+ OSC_XOSCSEL_EXTCLK_gc = (0x00<<0), /* External Clock - 6 CLK */
+ OSC_XOSCSEL_32KHz_gc = (0x02<<0), /* 32.768 kHz TOSC - 32K CLK */
+ OSC_XOSCSEL_XTAL_256CLK_gc = (0x03<<0), /* 0.4-16 MHz XTAL - 256 CLK */
+ OSC_XOSCSEL_XTAL_1KCLK_gc = (0x07<<0), /* 0.4-16 MHz XTAL - 1K CLK */
+ OSC_XOSCSEL_XTAL_16KCLK_gc = (0x0B<<0), /* 0.4-16 MHz XTAL - 16K CLK */
+} OSC_XOSCSEL_t;
+
+/* PLL Clock Source */
+typedef enum OSC_PLLSRC_enum
+{
+ OSC_PLLSRC_RC2M_gc = (0x00<<6), /* Internal 2 MHz RC Oscillator */
+ OSC_PLLSRC_RC32M_gc = (0x02<<6), /* Internal 32 MHz RC Oscillator */
+ OSC_PLLSRC_XOSC_gc = (0x03<<6), /* External Oscillator */
+} OSC_PLLSRC_t;
+
+/* 32 MHz Calibration Reference */
+typedef enum OSC_RC32MCREF_enum
+{
+ OSC_RC32MCREF_RC32K_gc = (0x00<<1), /* Internal 32.768 kHz RC Oscillator
*/
+ OSC_RC32MCREF_XOSC32_gc = (0x01<<1), /* External 32.768 kHz Crystal
Oscillator */
+} OSC_RC32MCREF_t;
+
+
+/*
+--------------------------------------------------------------------------
+DFLL - DFLL
+--------------------------------------------------------------------------
+*/
+
+/* DFLL */
+typedef struct DFLL_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t reserved_0x01;
+ register8_t CALA; /* Calibration Register A */
+ register8_t CALB; /* Calibration Register B */
+ register8_t COMP0; /* Oscillator Compare Register 0 */
+ register8_t COMP1; /* Oscillator Compare Register 1 */
+ register8_t COMP2; /* Oscillator Compare Register 2 */
+ register8_t reserved_0x07;
+} DFLL_t;
+
+
+/*
+--------------------------------------------------------------------------
+RST - Reset
+--------------------------------------------------------------------------
+*/
+
+/* Reset */
+typedef struct RST_struct
+{
+ register8_t STATUS; /* Status Register */
+ register8_t CTRL; /* Control Register */
+} RST_t;
+
+
+/*
+--------------------------------------------------------------------------
+WDT - Watch-Dog Timer
+--------------------------------------------------------------------------
+*/
+
+/* Watch-Dog Timer */
+typedef struct WDT_struct
+{
+ register8_t CTRL; /* Control */
+ register8_t WINCTRL; /* Windowed Mode Control */
+ register8_t STATUS; /* Status */
+} WDT_t;
+
+/* Period setting */
+typedef enum WDT_PER_enum
+{
+ WDT_PER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
+ WDT_PER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
+ WDT_PER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
+ WDT_PER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
+ WDT_PER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
+ WDT_PER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
+ WDT_PER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
+ WDT_PER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
+ WDT_PER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
+ WDT_PER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
+ WDT_PER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
+} WDT_PER_t;
+
+/* Closed window period */
+typedef enum WDT_WPER_enum
+{
+ WDT_WPER_8CLK_gc = (0x00<<2), /* 8 cycles (8ms @ 3.3V) */
+ WDT_WPER_16CLK_gc = (0x01<<2), /* 16 cycles (16ms @ 3.3V) */
+ WDT_WPER_32CLK_gc = (0x02<<2), /* 32 cycles (32ms @ 3.3V) */
+ WDT_WPER_64CLK_gc = (0x03<<2), /* 64 cycles (64ms @ 3.3V) */
+ WDT_WPER_125CLK_gc = (0x04<<2), /* 125 cycles (0.125s @ 3.3V) */
+ WDT_WPER_250CLK_gc = (0x05<<2), /* 250 cycles (0.25s @ 3.3V) */
+ WDT_WPER_500CLK_gc = (0x06<<2), /* 500 cycles (0.5s @ 3.3V) */
+ WDT_WPER_1KCLK_gc = (0x07<<2), /* 1K cycles (1s @ 3.3V) */
+ WDT_WPER_2KCLK_gc = (0x08<<2), /* 2K cycles (2s @ 3.3V) */
+ WDT_WPER_4KCLK_gc = (0x09<<2), /* 4K cycles (4s @ 3.3V) */
+ WDT_WPER_8KCLK_gc = (0x0A<<2), /* 8K cycles (8s @ 3.3V) */
+} WDT_WPER_t;
+
+
+/*
+--------------------------------------------------------------------------
+MCU - MCU Control
+--------------------------------------------------------------------------
+*/
+
+/* MCU Control */
+typedef struct MCU_struct
+{
+ register8_t DEVID0; /* Device ID byte 0 */
+ register8_t DEVID1; /* Device ID byte 1 */
+ register8_t DEVID2; /* Device ID byte 2 */
+ register8_t REVID; /* Revision ID */
+ register8_t JTAGUID; /* JTAG User ID */
+ register8_t reserved_0x05;
+ register8_t MCUCR; /* MCU Control */
+ register8_t ANAINIT; /* Analog Startup Delay */
+ register8_t EVSYSLOCK; /* Event System Lock */
+ register8_t AWEXLOCK; /* AWEX Lock */
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+} MCU_t;
+
+
+/*
+--------------------------------------------------------------------------
+PMIC - Programmable Multi-level Interrupt Controller
+--------------------------------------------------------------------------
+*/
+
+/* Programmable Multi-level Interrupt Controller */
+typedef struct PMIC_struct
+{
+ register8_t STATUS; /* Status Register */
+ register8_t INTPRI; /* Interrupt Priority */
+ register8_t CTRL; /* Control Register */
+} PMIC_t;
+
+
+/*
+--------------------------------------------------------------------------
+PORTCFG - Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* I/O port Configuration */
+typedef struct PORTCFG_struct
+{
+ register8_t MPCMASK; /* Multi-pin Configuration Mask */
+ register8_t reserved_0x01;
+ register8_t VPCTRLA; /* Virtual Port Control Register A */
+ register8_t VPCTRLB; /* Virtual Port Control Register B */
+ register8_t CLKEVOUT; /* Clock and Event Out Register */
+} PORTCFG_t;
+
+/* Virtual Port Mapping */
+typedef enum PORTCFG_VP02MAP_enum
+{
+ PORTCFG_VP02MAP_PORTA_gc = (0x00<<0), /* Mapped To PORTA */
+ PORTCFG_VP02MAP_PORTB_gc = (0x01<<0), /* Mapped To PORTB */
+ PORTCFG_VP02MAP_PORTC_gc = (0x02<<0), /* Mapped To PORTC */
+ PORTCFG_VP02MAP_PORTD_gc = (0x03<<0), /* Mapped To PORTD */
+ PORTCFG_VP02MAP_PORTE_gc = (0x04<<0), /* Mapped To PORTE */
+ PORTCFG_VP02MAP_PORTF_gc = (0x05<<0), /* Mapped To PORTF */
+ PORTCFG_VP02MAP_PORTG_gc = (0x06<<0), /* Mapped To PORTG */
+ PORTCFG_VP02MAP_PORTH_gc = (0x07<<0), /* Mapped To PORTH */
+ PORTCFG_VP02MAP_PORTJ_gc = (0x08<<0), /* Mapped To PORTJ */
+ PORTCFG_VP02MAP_PORTK_gc = (0x09<<0), /* Mapped To PORTK */
+ PORTCFG_VP02MAP_PORTL_gc = (0x0A<<0), /* Mapped To PORTL */
+ PORTCFG_VP02MAP_PORTM_gc = (0x0B<<0), /* Mapped To PORTM */
+ PORTCFG_VP02MAP_PORTN_gc = (0x0C<<0), /* Mapped To PORTN */
+ PORTCFG_VP02MAP_PORTP_gc = (0x0D<<0), /* Mapped To PORTP */
+ PORTCFG_VP02MAP_PORTQ_gc = (0x0E<<0), /* Mapped To PORTQ */
+ PORTCFG_VP02MAP_PORTR_gc = (0x0F<<0), /* Mapped To PORTR */
+} PORTCFG_VP02MAP_t;
+
+/* Virtual Port Mapping */
+typedef enum PORTCFG_VP13MAP_enum
+{
+ PORTCFG_VP13MAP_PORTA_gc = (0x00<<4), /* Mapped To PORTA */
+ PORTCFG_VP13MAP_PORTB_gc = (0x01<<4), /* Mapped To PORTB */
+ PORTCFG_VP13MAP_PORTC_gc = (0x02<<4), /* Mapped To PORTC */
+ PORTCFG_VP13MAP_PORTD_gc = (0x03<<4), /* Mapped To PORTD */
+ PORTCFG_VP13MAP_PORTE_gc = (0x04<<4), /* Mapped To PORTE */
+ PORTCFG_VP13MAP_PORTF_gc = (0x05<<4), /* Mapped To PORTF */
+ PORTCFG_VP13MAP_PORTG_gc = (0x06<<4), /* Mapped To PORTG */
+ PORTCFG_VP13MAP_PORTH_gc = (0x07<<4), /* Mapped To PORTH */
+ PORTCFG_VP13MAP_PORTJ_gc = (0x08<<4), /* Mapped To PORTJ */
+ PORTCFG_VP13MAP_PORTK_gc = (0x09<<4), /* Mapped To PORTK */
+ PORTCFG_VP13MAP_PORTL_gc = (0x0A<<4), /* Mapped To PORTL */
+ PORTCFG_VP13MAP_PORTM_gc = (0x0B<<4), /* Mapped To PORTM */
+ PORTCFG_VP13MAP_PORTN_gc = (0x0C<<4), /* Mapped To PORTN */
+ PORTCFG_VP13MAP_PORTP_gc = (0x0D<<4), /* Mapped To PORTP */
+ PORTCFG_VP13MAP_PORTQ_gc = (0x0E<<4), /* Mapped To PORTQ */
+ PORTCFG_VP13MAP_PORTR_gc = (0x0F<<4), /* Mapped To PORTR */
+} PORTCFG_VP13MAP_t;
+
+/* System Clock Output Port */
+typedef enum PORTCFG_CLKOUT_enum
+{
+ PORTCFG_CLKOUT_OFF_gc = (0x00<<0), /* System Clock Output Disabled */
+ PORTCFG_CLKOUT_PC7_gc = (0x01<<0), /* System Clock Output on Port C pin 7
*/
+ PORTCFG_CLKOUT_PD7_gc = (0x02<<0), /* System Clock Output on Port D pin 7
*/
+ PORTCFG_CLKOUT_PE7_gc = (0x03<<0), /* System Clock Output on Port E pin 7
*/
+} PORTCFG_CLKOUT_t;
+
+/* Peripheral Clock Output Select */
+typedef enum PORTCFG_CLKOUTSEL_enum
+{
+ PORTCFG_CLKOUTSEL_CLK1X_gc = (0x00<<2), /* 1x Peripheral Clock Output to
pin */
+ PORTCFG_CLKOUTSEL_CLK2X_gc = (0x01<<2), /* 2x Peripheral Clock Output to
pin */
+ PORTCFG_CLKOUTSEL_CLK4X_gc = (0x02<<2), /* 4x Peripheral Clock Output to
pin */
+} PORTCFG_CLKOUTSEL_t;
+
+/* Event Output Port */
+typedef enum PORTCFG_EVOUT_enum
+{
+ PORTCFG_EVOUT_OFF_gc = (0x00<<4), /* Event Output Disabled */
+ PORTCFG_EVOUT_PC7_gc = (0x01<<4), /* Event Channel 7 Output on Port C pin
7 */
+ PORTCFG_EVOUT_PD7_gc = (0x02<<4), /* Event Channel 7 Output on Port D pin
7 */
+ PORTCFG_EVOUT_PE7_gc = (0x03<<4), /* Event Channel 7 Output on Port E pin
7 */
+} PORTCFG_EVOUT_t;
+
+
+/*
+--------------------------------------------------------------------------
+AES - AES Module
+--------------------------------------------------------------------------
+*/
+
+/* AES Module */
+typedef struct AES_struct
+{
+ register8_t CTRL; /* AES Control Register */
+ register8_t STATUS; /* AES Status Register */
+ register8_t STATE; /* AES State Register */
+ register8_t KEY; /* AES Key Register */
+ register8_t INTCTRL; /* AES Interrupt Control Register */
+} AES_t;
+
+/* Interrupt level */
+typedef enum AES_INTLVL_enum
+{
+ AES_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ AES_INTLVL_LO_gc = (0x01<<0), /* Low Level */
+ AES_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ AES_INTLVL_HI_gc = (0x03<<0), /* High Level */
+} AES_INTLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+CRC - Cyclic Redundancy Checker
+--------------------------------------------------------------------------
+*/
+
+/* Cyclic Redundancy Checker */
+typedef struct CRC_struct
+{
+ register8_t CTRL; /* CRC Control Register */
+ register8_t STATUS; /* CRC Status Register */
+ register8_t DATAIN; /* CRC Data Input */
+ register8_t CHECKSUM0; /* CRC Checksum byte 0 */
+ register8_t CHECKSUM1; /* CRC Checksum byte 1 */
+ register8_t CHECKSUM2; /* CRC Checksum byte 2 */
+ register8_t CHECKSUM3; /* CRC Checksum byte 3 */
+} CRC_t;
+
+/* CRC Reset */
+typedef enum CRC_RESET_enum
+{
+ CRC_RESET_NO_gc = (0x00<<6), /* No Reset */
+ CRC_RESET_RESET0_gc = (0x02<<6), /* Reset CRC with CHECKSUM to all zeros
*/
+ CRC_RESET_RESET1_gc = (0x03<<6), /* Reset CRC with CHECKSUM to all ones */
+} CRC_RESET_t;
+
+/* CRC Input Source */
+typedef enum CRC_SOURCE_enum
+{
+ CRC_SOURCE_DISABLE_gc = (0x00<<0), /* CRC Disabled */
+ CRC_SOURCE_IO_gc = (0x01<<0), /* I/O Interface */
+ CRC_SOURCE_FLASH_gc = (0x02<<0), /* Flash */
+ CRC_SOURCE_DMAC0_gc = (0x04<<0), /* DMAC Channel 0 */
+ CRC_SOURCE_DMAC1_gc = (0x05<<0), /* DMAC Channel 1 */
+ CRC_SOURCE_DMAC2_gc = (0x06<<0), /* DMAC Channel 2 */
+ CRC_SOURCE_DMAC3_gc = (0x07<<0), /* DMAC Channel 3 */
+} CRC_SOURCE_t;
+
+
+/*
+--------------------------------------------------------------------------
+DMA - DMA Controller
+--------------------------------------------------------------------------
+*/
+
+/* DMA Channel */
+typedef struct DMA_CH_struct
+{
+ register8_t CTRLA; /* Channel Control */
+ register8_t CTRLB; /* Channel Control */
+ register8_t ADDRCTRL; /* Address Control */
+ register8_t TRIGSRC; /* Channel Trigger Source */
+ _WORDREGISTER(TRFCNT); /* Channel Block Transfer Count */
+ register8_t REPCNT; /* Channel Repeat Count */
+ register8_t reserved_0x07;
+ register8_t SRCADDR0; /* Channel Source Address 0 */
+ register8_t SRCADDR1; /* Channel Source Address 1 */
+ register8_t SRCADDR2; /* Channel Source Address 2 */
+ register8_t reserved_0x0B;
+ register8_t DESTADDR0; /* Channel Destination Address 0 */
+ register8_t DESTADDR1; /* Channel Destination Address 1 */
+ register8_t DESTADDR2; /* Channel Destination Address 2 */
+ register8_t reserved_0x0F;
+} DMA_CH_t;
+
+/*
+--------------------------------------------------------------------------
+DMA - DMA Controller
+--------------------------------------------------------------------------
+*/
+
+/* DMA Controller */
+typedef struct DMA_struct
+{
+ register8_t CTRL; /* Control */
+ register8_t reserved_0x01;
+ register8_t reserved_0x02;
+ register8_t INTFLAGS; /* Transfer Interrupt Status */
+ register8_t STATUS; /* Status */
+ register8_t reserved_0x05;
+ _WORDREGISTER(TEMP); /* Temporary Register For 16/24-bit Access */
+ register8_t reserved_0x08;
+ register8_t reserved_0x09;
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+ register8_t reserved_0x0C;
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ DMA_CH_t CH0; /* DMA Channel 0 */
+ DMA_CH_t CH1; /* DMA Channel 1 */
+ DMA_CH_t CH2; /* DMA Channel 2 */
+ DMA_CH_t CH3; /* DMA Channel 3 */
+} DMA_t;
+
+/* Burst mode */
+typedef enum DMA_CH_BURSTLEN_enum
+{
+ DMA_CH_BURSTLEN_1BYTE_gc = (0x00<<0), /* 1-byte burst mode */
+ DMA_CH_BURSTLEN_2BYTE_gc = (0x01<<0), /* 2-byte burst mode */
+ DMA_CH_BURSTLEN_4BYTE_gc = (0x02<<0), /* 4-byte burst mode */
+ DMA_CH_BURSTLEN_8BYTE_gc = (0x03<<0), /* 8-byte burst mode */
+} DMA_CH_BURSTLEN_t;
+
+/* Source address reload mode */
+typedef enum DMA_CH_SRCRELOAD_enum
+{
+ DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6), /* No reload */
+ DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6), /* Reload at end of block */
+ DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6), /* Reload at end of burst */
+ DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6), /* Reload at end of
transaction */
+} DMA_CH_SRCRELOAD_t;
+
+/* Source addressing mode */
+typedef enum DMA_CH_SRCDIR_enum
+{
+ DMA_CH_SRCDIR_FIXED_gc = (0x00<<4), /* Fixed */
+ DMA_CH_SRCDIR_INC_gc = (0x01<<4), /* Increment */
+ DMA_CH_SRCDIR_DEC_gc = (0x02<<4), /* Decrement */
+} DMA_CH_SRCDIR_t;
+
+/* Destination adress reload mode */
+typedef enum DMA_CH_DESTRELOAD_enum
+{
+ DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2), /* No reload */
+ DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2), /* Reload at end of block */
+ DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2), /* Reload at end of burst */
+ DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), /* Reload at end of
transaction */
+} DMA_CH_DESTRELOAD_t;
+
+/* Destination adressing mode */
+typedef enum DMA_CH_DESTDIR_enum
+{
+ DMA_CH_DESTDIR_FIXED_gc = (0x00<<0), /* Fixed */
+ DMA_CH_DESTDIR_INC_gc = (0x01<<0), /* Increment */
+ DMA_CH_DESTDIR_DEC_gc = (0x02<<0), /* Decrement */
+} DMA_CH_DESTDIR_t;
+
+/* Transfer trigger source */
+typedef enum DMA_CH_TRIGSRC_enum
+{
+ DMA_CH_TRIGSRC_OFF_gc = (0x00<<0), /* Off software triggers only */
+ DMA_CH_TRIGSRC_EVSYS_CH0_gc = (0x01<<0), /* Event System Channel 0 */
+ DMA_CH_TRIGSRC_EVSYS_CH1_gc = (0x02<<0), /* Event System Channel 1 */
+ DMA_CH_TRIGSRC_EVSYS_CH2_gc = (0x03<<0), /* Event System Channel 2 */
+ DMA_CH_TRIGSRC_ADCA_CH0_gc = (0x10<<0), /* ADCA Channel 0 */
+ DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0), /* ADCA Channel 1 */
+ DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0), /* ADCA Channel 2 */
+ DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0), /* ADCA Channel 3 */
+ DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0), /* ADCA Channel 0,1,2,3 combined
*/
+ DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0), /* DACA Channel 0 */
+ DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0), /* DACA Channel 1 */
+ DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0), /* ADCB Channel 0 */
+ DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0), /* ADCB Channel 1 */
+ DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0), /* ADCB Channel 2 */
+ DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0), /* ADCB Channel 3 */
+ DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0), /* ADCB Channel 0,1,2,3 combined
*/
+ DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0), /* DACB Channel 0 */
+ DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0), /* DACB Channel 1 */
+ DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0), /* Timer/Counter C0 Overflow */
+ DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0), /* Timer/Counter C0 Error */
+ DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), /* Timer/Counter C0 Compare or
Capture A */
+ DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0), /* Timer/Counter C0 Compare or
Capture B */
+ DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0), /* Timer/Counter C0 Compare or
Capture C */
+ DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0), /* Timer/Counter C0 Compare or
Capture D */
+ DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0), /* Timer/Counter C1 Overflow */
+ DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0), /* Timer/Counter C1 Error */
+ DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0), /* Timer/Counter C1 Compare or
Capture A */
+ DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0), /* Timer/Counter C1 Compare or
Capture B */
+ DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0), /* SPI C Transfer Complete */
+ DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0), /* USART C0 Receive Complete */
+ DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0), /* USART C0 Data Register
Empty */
+ DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0), /* USART C1 Receive Complete */
+ DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0), /* USART C1 Data Register
Empty */
+ DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0), /* Timer/Counter D0 Overflow */
+ DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0), /* Timer/Counter D0 Error */
+ DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0), /* Timer/Counter D0 Compare or
Capture A */
+ DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0), /* Timer/Counter D0 Compare or
Capture B */
+ DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0), /* Timer/Counter D0 Compare or
Capture C */
+ DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0), /* Timer/Counter D0 Compare or
Capture D */
+ DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0), /* Timer/Counter D1 Overflow */
+ DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0), /* Timer/Counter D1 Error */
+ DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0), /* Timer/Counter D1 Compare or
Capture A */
+ DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0), /* Timer/Counter D1 Compare or
Capture B */
+ DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0), /* SPI D Transfer Complete */
+ DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0), /* USART D0 Receive Complete */
+ DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0), /* USART D0 Data Register
Empty */
+ DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0), /* USART D1 Receive Complete */
+ DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0), /* USART D1 Data Register
Empty */
+ DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0), /* Timer/Counter E0 Overflow */
+ DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0), /* Timer/Counter E0 Error */
+ DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0), /* Timer/Counter E0 Compare or
Capture A */
+ DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0), /* Timer/Counter E0 Compare or
Capture B */
+ DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0), /* Timer/Counter E0 Compare or
Capture C */
+ DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), /* Timer/Counter E0 Compare or
Capture D */
+ DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0), /* Timer/Counter E1 Overflow */
+ DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0), /* Timer/Counter E1 Error */
+ DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0), /* Timer/Counter E1 Compare or
Capture A */
+ DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0), /* Timer/Counter E1 Compare or
Capture B */
+ DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0), /* SPI E Transfer Complete */
+ DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), /* USART E0 Receive Complete */
+ DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0), /* USART E0 Data Register
Empty */
+ DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0), /* USART E1 Receive Complete */
+ DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0), /* USART E1 Data Register
Empty */
+ DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0), /* Timer/Counter F0 Overflow */
+ DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0), /* Timer/Counter F0 Error */
+ DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0), /* Timer/Counter F0 Compare or
Capture A */
+ DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0), /* Timer/Counter F0 Compare or
Capture B */
+ DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0), /* Timer/Counter F0 Compare or
Capture C */
+ DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0), /* Timer/Counter F0 Compare or
Capture D */
+ DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0), /* Timer/Counter F1 Overflow */
+ DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0), /* Timer/Counter F1 Error */
+ DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0), /* Timer/Counter F1 Compare or
Capture A */
+ DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0), /* Timer/Counter F1 Compare or
Capture B */
+ DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0), /* SPI F Transfer Complete */
+ DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0), /* USART F0 Receive Complete */
+ DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0), /* USART F0 Data Register
Empty */
+ DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0), /* USART F1 Receive Complete */
+ DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0), /* USART F1 Data Register
Empty */
+} DMA_CH_TRIGSRC_t;
+
+/* Double buffering mode */
+typedef enum DMA_DBUFMODE_enum
+{
+ DMA_DBUFMODE_DISABLED_gc = (0x00<<2), /* Double buffering disabled */
+ DMA_DBUFMODE_CH01_gc = (0x01<<2), /* Double buffering enabled on channel
0/1 */
+ DMA_DBUFMODE_CH23_gc = (0x02<<2), /* Double buffering enabled on channel
2/3 */
+ DMA_DBUFMODE_CH01CH23_gc = (0x03<<2), /* Double buffering enabled on ch.
0/1 and ch. 2/3 */
+} DMA_DBUFMODE_t;
+
+/* Priority mode */
+typedef enum DMA_PRIMODE_enum
+{
+ DMA_PRIMODE_RR0123_gc = (0x00<<0), /* Round Robin */
+ DMA_PRIMODE_CH0RR123_gc = (0x01<<0), /* Channel 0 > Round Robin on
channel 1/2/3 */
+ DMA_PRIMODE_CH01RR23_gc = (0x02<<0), /* Channel 0 > channel 1 > Round
Robin on channel 2/3 */
+ DMA_PRIMODE_CH0123_gc = (0x03<<0), /* Channel 0 > channel 1 > channel 2 >
channel 3 */
+} DMA_PRIMODE_t;
+
+/* Interrupt level */
+typedef enum DMA_CH_ERRINTLVL_enum
+{
+ DMA_CH_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
+ DMA_CH_ERRINTLVL_LO_gc = (0x01<<2), /* Low level */
+ DMA_CH_ERRINTLVL_MED_gc = (0x02<<2), /* Medium level */
+ DMA_CH_ERRINTLVL_HI_gc = (0x03<<2), /* High level */
+} DMA_CH_ERRINTLVL_t;
+
+/* Interrupt level */
+typedef enum DMA_CH_TRNINTLVL_enum
+{
+ DMA_CH_TRNINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ DMA_CH_TRNINTLVL_LO_gc = (0x01<<0), /* Low level */
+ DMA_CH_TRNINTLVL_MED_gc = (0x02<<0), /* Medium level */
+ DMA_CH_TRNINTLVL_HI_gc = (0x03<<0), /* High level */
+} DMA_CH_TRNINTLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+EVSYS - Event System
+--------------------------------------------------------------------------
+*/
+
+/* Event System */
+typedef struct EVSYS_struct
+{
+ register8_t CH0MUX; /* Event Channel 0 Multiplexer */
+ register8_t CH1MUX; /* Event Channel 1 Multiplexer */
+ register8_t CH2MUX; /* Event Channel 2 Multiplexer */
+ register8_t CH3MUX; /* Event Channel 3 Multiplexer */
+ register8_t CH4MUX; /* Event Channel 4 Multiplexer */
+ register8_t CH5MUX; /* Event Channel 5 Multiplexer */
+ register8_t CH6MUX; /* Event Channel 6 Multiplexer */
+ register8_t CH7MUX; /* Event Channel 7 Multiplexer */
+ register8_t CH0CTRL; /* Channel 0 Control Register */
+ register8_t CH1CTRL; /* Channel 1 Control Register */
+ register8_t CH2CTRL; /* Channel 2 Control Register */
+ register8_t CH3CTRL; /* Channel 3 Control Register */
+ register8_t CH4CTRL; /* Channel 4 Control Register */
+ register8_t CH5CTRL; /* Channel 5 Control Register */
+ register8_t CH6CTRL; /* Channel 6 Control Register */
+ register8_t CH7CTRL; /* Channel 7 Control Register */
+ register8_t STROBE; /* Event Strobe */
+ register8_t DATA; /* Event Data */
+} EVSYS_t;
+
+/* Quadrature Decoder Index Recognition Mode */
+typedef enum EVSYS_QDIRM_enum
+{
+ EVSYS_QDIRM_00_gc = (0x00<<5), /* QDPH0 = 0, QDPH90 = 0 */
+ EVSYS_QDIRM_01_gc = (0x01<<5), /* QDPH0 = 0, QDPH90 = 1 */
+ EVSYS_QDIRM_10_gc = (0x02<<5), /* QDPH0 = 1, QDPH90 = 0 */
+ EVSYS_QDIRM_11_gc = (0x03<<5), /* QDPH0 = 1, QDPH90 = 1 */
+} EVSYS_QDIRM_t;
+
+/* Digital filter coefficient */
+typedef enum EVSYS_DIGFILT_enum
+{
+ EVSYS_DIGFILT_1SAMPLE_gc = (0x00<<0), /* 1 SAMPLE */
+ EVSYS_DIGFILT_2SAMPLES_gc = (0x01<<0), /* 2 SAMPLES */
+ EVSYS_DIGFILT_3SAMPLES_gc = (0x02<<0), /* 3 SAMPLES */
+ EVSYS_DIGFILT_4SAMPLES_gc = (0x03<<0), /* 4 SAMPLES */
+ EVSYS_DIGFILT_5SAMPLES_gc = (0x04<<0), /* 5 SAMPLES */
+ EVSYS_DIGFILT_6SAMPLES_gc = (0x05<<0), /* 6 SAMPLES */
+ EVSYS_DIGFILT_7SAMPLES_gc = (0x06<<0), /* 7 SAMPLES */
+ EVSYS_DIGFILT_8SAMPLES_gc = (0x07<<0), /* 8 SAMPLES */
+} EVSYS_DIGFILT_t;
+
+/* Event Channel multiplexer input selection */
+typedef enum EVSYS_CHMUX_enum
+{
+ EVSYS_CHMUX_OFF_gc = (0x00<<0), /* Off */
+ EVSYS_CHMUX_RTC_OVF_gc = (0x08<<0), /* RTC Overflow */
+ EVSYS_CHMUX_RTC_CMP_gc = (0x09<<0), /* RTC Compare Match */
+ EVSYS_CHMUX_USB_gc = (0x0A<<0), /* USB Setup, SOF, CRC error and UNF/OVF
*/
+ EVSYS_CHMUX_ACA_CH0_gc = (0x10<<0), /* Analog Comparator A Channel 0 */
+ EVSYS_CHMUX_ACA_CH1_gc = (0x11<<0), /* Analog Comparator A Channel 1 */
+ EVSYS_CHMUX_ACA_WIN_gc = (0x12<<0), /* Analog Comparator A Window */
+ EVSYS_CHMUX_ACB_CH0_gc = (0x13<<0), /* Analog Comparator B Channel 0 */
+ EVSYS_CHMUX_ACB_CH1_gc = (0x14<<0), /* Analog Comparator B Channel 1 */
+ EVSYS_CHMUX_ACB_WIN_gc = (0x15<<0), /* Analog Comparator B Window */
+ EVSYS_CHMUX_ADCA_CH0_gc = (0x20<<0), /* ADC A Channel 0 */
+ EVSYS_CHMUX_ADCA_CH1_gc = (0x21<<0), /* ADC A Channel 1 */
+ EVSYS_CHMUX_ADCA_CH2_gc = (0x22<<0), /* ADC A Channel 2 */
+ EVSYS_CHMUX_ADCA_CH3_gc = (0x23<<0), /* ADC A Channel 3 */
+ EVSYS_CHMUX_ADCB_CH0_gc = (0x24<<0), /* ADC B Channel 0 */
+ EVSYS_CHMUX_ADCB_CH1_gc = (0x25<<0), /* ADC B Channel 1 */
+ EVSYS_CHMUX_ADCB_CH2_gc = (0x26<<0), /* ADC B Channel 2 */
+ EVSYS_CHMUX_ADCB_CH3_gc = (0x27<<0), /* ADC B Channel 3 */
+ EVSYS_CHMUX_PORTA_PIN0_gc = (0x50<<0), /* Port A, Pin0 */
+ EVSYS_CHMUX_PORTA_PIN1_gc = (0x51<<0), /* Port A, Pin1 */
+ EVSYS_CHMUX_PORTA_PIN2_gc = (0x52<<0), /* Port A, Pin2 */
+ EVSYS_CHMUX_PORTA_PIN3_gc = (0x53<<0), /* Port A, Pin3 */
+ EVSYS_CHMUX_PORTA_PIN4_gc = (0x54<<0), /* Port A, Pin4 */
+ EVSYS_CHMUX_PORTA_PIN5_gc = (0x55<<0), /* Port A, Pin5 */
+ EVSYS_CHMUX_PORTA_PIN6_gc = (0x56<<0), /* Port A, Pin6 */
+ EVSYS_CHMUX_PORTA_PIN7_gc = (0x57<<0), /* Port A, Pin7 */
+ EVSYS_CHMUX_PORTB_PIN0_gc = (0x58<<0), /* Port B, Pin0 */
+ EVSYS_CHMUX_PORTB_PIN1_gc = (0x59<<0), /* Port B, Pin1 */
+ EVSYS_CHMUX_PORTB_PIN2_gc = (0x5A<<0), /* Port B, Pin2 */
+ EVSYS_CHMUX_PORTB_PIN3_gc = (0x5B<<0), /* Port B, Pin3 */
+ EVSYS_CHMUX_PORTB_PIN4_gc = (0x5C<<0), /* Port B, Pin4 */
+ EVSYS_CHMUX_PORTB_PIN5_gc = (0x5D<<0), /* Port B, Pin5 */
+ EVSYS_CHMUX_PORTB_PIN6_gc = (0x5E<<0), /* Port B, Pin6 */
+ EVSYS_CHMUX_PORTB_PIN7_gc = (0x5F<<0), /* Port B, Pin7 */
+ EVSYS_CHMUX_PORTC_PIN0_gc = (0x60<<0), /* Port C, Pin0 */
+ EVSYS_CHMUX_PORTC_PIN1_gc = (0x61<<0), /* Port C, Pin1 */
+ EVSYS_CHMUX_PORTC_PIN2_gc = (0x62<<0), /* Port C, Pin2 */
+ EVSYS_CHMUX_PORTC_PIN3_gc = (0x63<<0), /* Port C, Pin3 */
+ EVSYS_CHMUX_PORTC_PIN4_gc = (0x64<<0), /* Port C, Pin4 */
+ EVSYS_CHMUX_PORTC_PIN5_gc = (0x65<<0), /* Port C, Pin5 */
+ EVSYS_CHMUX_PORTC_PIN6_gc = (0x66<<0), /* Port C, Pin6 */
+ EVSYS_CHMUX_PORTC_PIN7_gc = (0x67<<0), /* Port C, Pin7 */
+ EVSYS_CHMUX_PORTD_PIN0_gc = (0x68<<0), /* Port D, Pin0 */
+ EVSYS_CHMUX_PORTD_PIN1_gc = (0x69<<0), /* Port D, Pin1 */
+ EVSYS_CHMUX_PORTD_PIN2_gc = (0x6A<<0), /* Port D, Pin2 */
+ EVSYS_CHMUX_PORTD_PIN3_gc = (0x6B<<0), /* Port D, Pin3 */
+ EVSYS_CHMUX_PORTD_PIN4_gc = (0x6C<<0), /* Port D, Pin4 */
+ EVSYS_CHMUX_PORTD_PIN5_gc = (0x6D<<0), /* Port D, Pin5 */
+ EVSYS_CHMUX_PORTD_PIN6_gc = (0x6E<<0), /* Port D, Pin6 */
+ EVSYS_CHMUX_PORTD_PIN7_gc = (0x6F<<0), /* Port D, Pin7 */
+ EVSYS_CHMUX_PORTE_PIN0_gc = (0x70<<0), /* Port E, Pin0 */
+ EVSYS_CHMUX_PORTE_PIN1_gc = (0x71<<0), /* Port E, Pin1 */
+ EVSYS_CHMUX_PORTE_PIN2_gc = (0x72<<0), /* Port E, Pin2 */
+ EVSYS_CHMUX_PORTE_PIN3_gc = (0x73<<0), /* Port E, Pin3 */
+ EVSYS_CHMUX_PORTE_PIN4_gc = (0x74<<0), /* Port E, Pin4 */
+ EVSYS_CHMUX_PORTE_PIN5_gc = (0x75<<0), /* Port E, Pin5 */
+ EVSYS_CHMUX_PORTE_PIN6_gc = (0x76<<0), /* Port E, Pin6 */
+ EVSYS_CHMUX_PORTE_PIN7_gc = (0x77<<0), /* Port E, Pin7 */
+ EVSYS_CHMUX_PORTF_PIN0_gc = (0x78<<0), /* Port F, Pin0 */
+ EVSYS_CHMUX_PORTF_PIN1_gc = (0x79<<0), /* Port F, Pin1 */
+ EVSYS_CHMUX_PORTF_PIN2_gc = (0x7A<<0), /* Port F, Pin2 */
+ EVSYS_CHMUX_PORTF_PIN3_gc = (0x7B<<0), /* Port F, Pin3 */
+ EVSYS_CHMUX_PORTF_PIN4_gc = (0x7C<<0), /* Port F, Pin4 */
+ EVSYS_CHMUX_PORTF_PIN5_gc = (0x7D<<0), /* Port F, Pin5 */
+ EVSYS_CHMUX_PORTF_PIN6_gc = (0x7E<<0), /* Port F, Pin6 */
+ EVSYS_CHMUX_PORTF_PIN7_gc = (0x7F<<0), /* Port F, Pin7 */
+ EVSYS_CHMUX_PRESCALER_1_gc = (0x80<<0), /* Prescaler, divide by 1 */
+ EVSYS_CHMUX_PRESCALER_2_gc = (0x81<<0), /* Prescaler, divide by 2 */
+ EVSYS_CHMUX_PRESCALER_4_gc = (0x82<<0), /* Prescaler, divide by 4 */
+ EVSYS_CHMUX_PRESCALER_8_gc = (0x83<<0), /* Prescaler, divide by 8 */
+ EVSYS_CHMUX_PRESCALER_16_gc = (0x84<<0), /* Prescaler, divide by 16 */
+ EVSYS_CHMUX_PRESCALER_32_gc = (0x85<<0), /* Prescaler, divide by 32 */
+ EVSYS_CHMUX_PRESCALER_64_gc = (0x86<<0), /* Prescaler, divide by 64 */
+ EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0), /* Prescaler, divide by 128 */
+ EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0), /* Prescaler, divide by 256 */
+ EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0), /* Prescaler, divide by 512 */
+ EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0), /* Prescaler, divide by 1024 */
+ EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0), /* Prescaler, divide by 2048 */
+ EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0), /* Prescaler, divide by 4096 */
+ EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0), /* Prescaler, divide by 8192 */
+ EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0), /* Prescaler, divide by 16384
*/
+ EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0), /* Prescaler, divide by 32768
*/
+ EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0), /* Timer/Counter C0 Overflow */
+ EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0), /* Timer/Counter C0 Error */
+ EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0), /* Timer/Counter C0 Compare or
Capture A */
+ EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0), /* Timer/Counter C0 Compare or
Capture B */
+ EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0), /* Timer/Counter C0 Compare or
Capture C */
+ EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0), /* Timer/Counter C0 Compare or
Capture D */
+ EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0), /* Timer/Counter C1 Overflow */
+ EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0), /* Timer/Counter C1 Error */
+ EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0), /* Timer/Counter C1 Compare or
Capture A */
+ EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0), /* Timer/Counter C1 Compare or
Capture B */
+ EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0), /* Timer/Counter D0 Overflow */
+ EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0), /* Timer/Counter D0 Error */
+ EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0), /* Timer/Counter D0 Compare or
Capture A */
+ EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0), /* Timer/Counter D0 Compare or
Capture B */
+ EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0), /* Timer/Counter D0 Compare or
Capture C */
+ EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0), /* Timer/Counter D0 Compare or
Capture D */
+ EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0), /* Timer/Counter D1 Overflow */
+ EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0), /* Timer/Counter D1 Error */
+ EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0), /* Timer/Counter D1 Compare or
Capture A */
+ EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0), /* Timer/Counter D1 Compare or
Capture B */
+ EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0), /* Timer/Counter E0 Overflow */
+ EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0), /* Timer/Counter E0 Error */
+ EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0), /* Timer/Counter E0 Compare or
Capture A */
+ EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0), /* Timer/Counter E0 Compare or
Capture B */
+ EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0), /* Timer/Counter E0 Compare or
Capture C */
+ EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0), /* Timer/Counter E0 Compare or
Capture D */
+ EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0), /* Timer/Counter E1 Overflow */
+ EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0), /* Timer/Counter E1 Error */
+ EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0), /* Timer/Counter E1 Compare or
Capture A */
+ EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0), /* Timer/Counter E1 Compare or
Capture B */
+ EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0), /* Timer/Counter F0 Overflow */
+ EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0), /* Timer/Counter F0 Error */
+ EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0), /* Timer/Counter F0 Compare or
Capture A */
+ EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0), /* Timer/Counter F0 Compare or
Capture B */
+ EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0), /* Timer/Counter F0 Compare or
Capture C */
+ EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0), /* Timer/Counter F0 Compare or
Capture D */
+ EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0), /* Timer/Counter F1 Overflow */
+ EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0), /* Timer/Counter F1 Error */
+ EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0), /* Timer/Counter F1 Compare or
Capture A */
+ EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0), /* Timer/Counter F1 Compare or
Capture B */
+} EVSYS_CHMUX_t;
+
+
+/*
+--------------------------------------------------------------------------
+NVM - Non Volatile Memory Controller
+--------------------------------------------------------------------------
+*/
+
+/* Non-volatile Memory Controller */
+typedef struct NVM_struct
+{
+ register8_t ADDR0; /* Address Register 0 */
+ register8_t ADDR1; /* Address Register 1 */
+ register8_t ADDR2; /* Address Register 2 */
+ register8_t reserved_0x03;
+ register8_t DATA0; /* Data Register 0 */
+ register8_t DATA1; /* Data Register 1 */
+ register8_t DATA2; /* Data Register 2 */
+ register8_t reserved_0x07;
+ register8_t reserved_0x08;
+ register8_t reserved_0x09;
+ register8_t CMD; /* Command */
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t INTCTRL; /* Interrupt Control */
+ register8_t reserved_0x0E;
+ register8_t STATUS; /* Status */
+ register8_t LOCKBITS; /* Lock Bits */
+} NVM_t;
+
+/* NVM Command */
+typedef enum NVM_CMD_enum
+{
+ NVM_CMD_NO_OPERATION_gc = (0x00<<0), /* Noop/Ordinary LPM */
+ NVM_CMD_READ_CALIB_ROW_gc = (0x02<<0), /* Read calibration row */
+ NVM_CMD_READ_USER_SIG_ROW_gc = (0x03<<0), /* Read user signature row */
+ NVM_CMD_READ_EEPROM_gc = (0x06<<0), /* Read EEPROM */
+ NVM_CMD_READ_FUSES_gc = (0x07<<0), /* Read fuse byte */
+ NVM_CMD_WRITE_LOCK_BITS_gc = (0x08<<0), /* Write lock bits */
+ NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0), /* Erase user signature row */
+ NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0), /* Write user signature row */
+ NVM_CMD_ERASE_APP_gc = (0x20<<0), /* Erase Application Section */
+ NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0), /* Erase Application Section page
*/
+ NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0), /* Load Flash page buffer */
+ NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0), /* Write Application Section page
*/
+ NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0), /* Erase-and-write
Application Section page */
+ NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0), /* Erase/flush Flash page
buffer */
+ NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0), /* Erase Boot Section page */
+ NVM_CMD_ERASE_FLASH_PAGE_gc = (0x2B<<0), /* Erase Flash Page */
+ NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0), /* Write Boot Section page */
+ NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0), /* Erase-and-write Boot
Section page */
+ NVM_CMD_WRITE_FLASH_PAGE_gc = (0x2E<<0), /* Write Flash Page */
+ NVM_CMD_ERASE_WRITE_FLASH_PAGE_gc = (0x2F<<0), /* Erase-and-write Flash
Page */
+ NVM_CMD_ERASE_EEPROM_gc = (0x30<<0), /* Erase EEPROM */
+ NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0), /* Erase EEPROM page */
+ NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0), /* Load EEPROM page buffer */
+ NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0), /* Write EEPROM page */
+ NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0), /* Erase-and-write EEPROM
page */
+ NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0), /* Erase/flush EEPROM page
buffer */
+ NVM_CMD_APP_CRC_gc = (0x38<<0), /* Generate Application section CRC */
+ NVM_CMD_BOOT_CRC_gc = (0x39<<0), /* Generate Boot Section CRC */
+ NVM_CMD_CHIP_ERASE_gc = (0x40<<0), /* Erase Chip */
+ NVM_CMD_READ_NVM_gc = (0x43<<0), /* Read NVM */
+ NVM_CMD_WRITE_FUSE_gc = (0x4C<<0), /* Write Fuse byte */
+ NVM_CMD_ERASE_BOOT_gc = (0x68<<0), /* Erase Boot Section */
+ NVM_CMD_FLASH_RANGE_CRC_gc = (0x78<<0), /* Generate Flash Range CRC */
+} NVM_CMD_t;
+
+/* SPM ready interrupt level */
+typedef enum NVM_SPMLVL_enum
+{
+ NVM_SPMLVL_OFF_gc = (0x00<<2), /* Interrupt disabled */
+ NVM_SPMLVL_LO_gc = (0x01<<2), /* Low level */
+ NVM_SPMLVL_MED_gc = (0x02<<2), /* Medium level */
+ NVM_SPMLVL_HI_gc = (0x03<<2), /* High level */
+} NVM_SPMLVL_t;
+
+/* EEPROM ready interrupt level */
+typedef enum NVM_EELVL_enum
+{
+ NVM_EELVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ NVM_EELVL_LO_gc = (0x01<<0), /* Low level */
+ NVM_EELVL_MED_gc = (0x02<<0), /* Medium level */
+ NVM_EELVL_HI_gc = (0x03<<0), /* High level */
+} NVM_EELVL_t;
+
+/* Boot lock bits - boot setcion */
+typedef enum NVM_BLBB_enum
+{
+ NVM_BLBB_NOLOCK_gc = (0x03<<6), /* No locks */
+ NVM_BLBB_WLOCK_gc = (0x02<<6), /* Write not allowed */
+ NVM_BLBB_RLOCK_gc = (0x01<<6), /* Read not allowed */
+ NVM_BLBB_RWLOCK_gc = (0x00<<6), /* Read and write not allowed */
+} NVM_BLBB_t;
+
+/* Boot lock bits - application section */
+typedef enum NVM_BLBA_enum
+{
+ NVM_BLBA_NOLOCK_gc = (0x03<<4), /* No locks */
+ NVM_BLBA_WLOCK_gc = (0x02<<4), /* Write not allowed */
+ NVM_BLBA_RLOCK_gc = (0x01<<4), /* Read not allowed */
+ NVM_BLBA_RWLOCK_gc = (0x00<<4), /* Read and write not allowed */
+} NVM_BLBA_t;
+
+/* Boot lock bits - application table section */
+typedef enum NVM_BLBAT_enum
+{
+ NVM_BLBAT_NOLOCK_gc = (0x03<<2), /* No locks */
+ NVM_BLBAT_WLOCK_gc = (0x02<<2), /* Write not allowed */
+ NVM_BLBAT_RLOCK_gc = (0x01<<2), /* Read not allowed */
+ NVM_BLBAT_RWLOCK_gc = (0x00<<2), /* Read and write not allowed */
+} NVM_BLBAT_t;
+
+/* Lock bits */
+typedef enum NVM_LB_enum
+{
+ NVM_LB_NOLOCK_gc = (0x03<<0), /* No locks */
+ NVM_LB_WLOCK_gc = (0x02<<0), /* Write not allowed */
+ NVM_LB_RWLOCK_gc = (0x00<<0), /* Read and write not allowed */
+} NVM_LB_t;
+
+
+/*
+--------------------------------------------------------------------------
+ADC - Analog/Digital Converter
+--------------------------------------------------------------------------
+*/
+
+/* ADC Channel */
+typedef struct ADC_CH_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t MUXCTRL; /* MUX Control */
+ register8_t INTCTRL; /* Channel Interrupt Control */
+ register8_t INTFLAGS; /* Interrupt Flags */
+ _WORDREGISTER(RES); /* Channel Result */
+ register8_t reserved_0x7;
+} ADC_CH_t;
+
+/*
+--------------------------------------------------------------------------
+ADC - Analog/Digital Converter
+--------------------------------------------------------------------------
+*/
+
+/* Analog-to-Digital Converter */
+typedef struct ADC_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t REFCTRL; /* Reference Control */
+ register8_t EVCTRL; /* Event Control */
+ register8_t PRESCALER; /* Clock Prescaler */
+ register8_t reserved_0x05;
+ register8_t INTFLAGS; /* Interrupt Flags */
+ register8_t TEMP; /* Temporary register */
+ register8_t reserved_0x08;
+ register8_t reserved_0x09;
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+ _WORDREGISTER(CAL); /* Calibration Value */
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ _WORDREGISTER(CH0RES); /* Channel 0 Result */
+ _WORDREGISTER(CH1RES); /* Channel 1 Result */
+ _WORDREGISTER(CH2RES); /* Channel 2 Result */
+ _WORDREGISTER(CH3RES); /* Channel 3 Result */
+ _WORDREGISTER(CMP); /* Compare Value */
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ ADC_CH_t CH0; /* ADC Channel 0 */
+ ADC_CH_t CH1; /* ADC Channel 1 */
+ ADC_CH_t CH2; /* ADC Channel 2 */
+ ADC_CH_t CH3; /* ADC Channel 3 */
+} ADC_t;
+
+/* Positive input multiplexer selection */
+typedef enum ADC_CH_MUXPOS_enum
+{
+ ADC_CH_MUXPOS_PIN0_gc = (0x00<<3), /* Input pin 0 */
+ ADC_CH_MUXPOS_PIN1_gc = (0x01<<3), /* Input pin 1 */
+ ADC_CH_MUXPOS_PIN2_gc = (0x02<<3), /* Input pin 2 */
+ ADC_CH_MUXPOS_PIN3_gc = (0x03<<3), /* Input pin 3 */
+ ADC_CH_MUXPOS_PIN4_gc = (0x04<<3), /* Input pin 4 */
+ ADC_CH_MUXPOS_PIN5_gc = (0x05<<3), /* Input pin 5 */
+ ADC_CH_MUXPOS_PIN6_gc = (0x06<<3), /* Input pin 6 */
+ ADC_CH_MUXPOS_PIN7_gc = (0x07<<3), /* Input pin 7 */
+ ADC_CH_MUXPOS_PIN8_gc = (0x08<<3), /* Input pin 8 */
+ ADC_CH_MUXPOS_PIN9_gc = (0x09<<3), /* Input pin 9 */
+ ADC_CH_MUXPOS_PIN10_gc = (0x0A<<3), /* Input pin 10 */
+ ADC_CH_MUXPOS_PIN11_gc = (0x0B<<3), /* Input pin 11 */
+ ADC_CH_MUXPOS_PIN12_gc = (0x0C<<3), /* Input pin 12 */
+ ADC_CH_MUXPOS_PIN13_gc = (0x0D<<3), /* Input pin 13 */
+ ADC_CH_MUXPOS_PIN14_gc = (0x0E<<3), /* Input pin 14 */
+ ADC_CH_MUXPOS_PIN15_gc = (0x0F<<3), /* Input pin 15 */
+} ADC_CH_MUXPOS_t;
+
+/* Internal input multiplexer selections */
+typedef enum ADC_CH_MUXINT_enum
+{
+ ADC_CH_MUXINT_TEMP_gc = (0x00<<3), /* Temperature Reference */
+ ADC_CH_MUXINT_BANDGAP_gc = (0x01<<3), /* Bandgap Reference */
+ ADC_CH_MUXINT_SCALEDVCC_gc = (0x02<<3), /* 1/10 scaled VCC */
+ ADC_CH_MUXINT_DAC_gc = (0x03<<3), /* DAC output */
+} ADC_CH_MUXINT_t;
+
+/* Negative input multiplexer selection */
+typedef enum ADC_CH_MUXNEG_enum
+{
+ ADC_CH_MUXNEG_PIN0_gc = (0x00<<0), /* Input pin 0 */
+ ADC_CH_MUXNEG_PIN1_gc = (0x01<<0), /* Input pin 1 */
+ ADC_CH_MUXNEG_PIN2_gc = (0x02<<0), /* Input pin 2 */
+ ADC_CH_MUXNEG_PIN3_gc = (0x03<<0), /* Input pin 3 */
+ ADC_CH_MUXNEG_PIN4_gc = (0x00<<0), /* Input pin 4 */
+ ADC_CH_MUXNEG_PIN5_gc = (0x01<<0), /* Input pin 5 */
+ ADC_CH_MUXNEG_PIN6_gc = (0x02<<0), /* Input pin 6 */
+ ADC_CH_MUXNEG_PIN7_gc = (0x03<<0), /* Input pin 7 */
+} ADC_CH_MUXNEG_t;
+
+/* Input mode */
+typedef enum ADC_CH_INPUTMODE_enum
+{
+ ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0), /* Internal inputs, no gain */
+ ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0), /* Single-ended input, no
gain */
+ ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0), /* Differential input, no gain */
+ ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0), /* Differential input, with
gain */
+} ADC_CH_INPUTMODE_t;
+
+/* Gain factor */
+typedef enum ADC_CH_GAIN_enum
+{
+ ADC_CH_GAIN_1X_gc = (0x00<<2), /* 1x gain */
+ ADC_CH_GAIN_2X_gc = (0x01<<2), /* 2x gain */
+ ADC_CH_GAIN_4X_gc = (0x02<<2), /* 4x gain */
+ ADC_CH_GAIN_8X_gc = (0x03<<2), /* 8x gain */
+ ADC_CH_GAIN_16X_gc = (0x04<<2), /* 16x gain */
+ ADC_CH_GAIN_32X_gc = (0x05<<2), /* 32x gain */
+ ADC_CH_GAIN_64X_gc = (0x06<<2), /* 64x gain */
+ ADC_CH_GAIN_128X_gc = (0x07<<2), /* 128x gain */
+} ADC_CH_GAIN_t;
+
+/* Conversion result resolution */
+typedef enum ADC_RESOLUTION_enum
+{
+ ADC_RESOLUTION_12BIT_gc = (0x00<<1), /* 12-bit right-adjusted result */
+ ADC_RESOLUTION_8BIT_gc = (0x02<<1), /* 8-bit right-adjusted result */
+ ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1), /* 12-bit left-adjusted result */
+} ADC_RESOLUTION_t;
+
+/* Current Limitation Mode */
+typedef enum ADC_CURRENT_enum
+{
+ ADC_CURRENT_NO_gc = (0x00<<5), /* No Current Reduction */
+ ADC_CURRENT_SMALL_gc = (0x01<<5), /* 10% current reduction */
+ ADC_CURRENT_MEDIUM_gc = (0x02<<5), /* 20% current reduction */
+ ADC_CURRENT_LARGE_gc = (0x03<<5), /* 30% current reduction */
+} ADC_CURRENT_t;
+
+/* Voltage reference selection */
+typedef enum ADC_REFSEL_enum
+{
+ ADC_REFSEL_INT1V_gc = (0x00<<4), /* Internal 1V */
+ ADC_REFSEL_VCC_gc = (0x01<<4), /* Internal VCC / 1.6 */
+ ADC_REFSEL_AREFA_gc = (0x02<<4), /* External reference on PORT A */
+ ADC_REFSEL_AREFB_gc = (0x03<<4), /* External reference on PORT B */
+ ADC_REFSEL_VCCDIV2_gc = (0x04<<4), /* Internal VCC / 2 */
+} ADC_REFSEL_t;
+
+/* Channel sweep selection */
+typedef enum ADC_SWEEP_enum
+{
+ ADC_SWEEP_0_gc = (0x00<<6), /* ADC Channel 0 */
+ ADC_SWEEP_01_gc = (0x01<<6), /* ADC Channel 0,1 */
+ ADC_SWEEP_012_gc = (0x02<<6), /* ADC Channel 0,1,2 */
+ ADC_SWEEP_0123_gc = (0x03<<6), /* ADC Channel 0,1,2,3 */
+} ADC_SWEEP_t;
+
+/* Event channel input selection */
+typedef enum ADC_EVSEL_enum
+{
+ ADC_EVSEL_0123_gc = (0x00<<3), /* Event Channel 0,1,2,3 */
+ ADC_EVSEL_1234_gc = (0x01<<3), /* Event Channel 1,2,3,4 */
+ ADC_EVSEL_2345_gc = (0x02<<3), /* Event Channel 2,3,4,5 */
+ ADC_EVSEL_3456_gc = (0x03<<3), /* Event Channel 3,4,5,6 */
+ ADC_EVSEL_4567_gc = (0x04<<3), /* Event Channel 4,5,6,7 */
+ ADC_EVSEL_567_gc = (0x05<<3), /* Event Channel 5,6,7 */
+ ADC_EVSEL_67_gc = (0x06<<3), /* Event Channel 6,7 */
+ ADC_EVSEL_7_gc = (0x07<<3), /* Event Channel 7 */
+} ADC_EVSEL_t;
+
+/* Event action selection */
+typedef enum ADC_EVACT_enum
+{
+ ADC_EVACT_NONE_gc = (0x00<<0), /* No event action */
+ ADC_EVACT_CH0_gc = (0x01<<0), /* First event triggers channel 0 */
+ ADC_EVACT_CH01_gc = (0x02<<0), /* First two events trigger channel 0,1 */
+ ADC_EVACT_CH012_gc = (0x03<<0), /* First three events trigger channel
0,1,2 */
+ ADC_EVACT_CH0123_gc = (0x04<<0), /* Events trigger channel 0,1,2,3 */
+ ADC_EVACT_SWEEP_gc = (0x05<<0), /* First event triggers sweep */
+ ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0), /* First event triggers synchronized
sweep */
+} ADC_EVACT_t;
+
+/* Interupt mode */
+typedef enum ADC_CH_INTMODE_enum
+{
+ ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2), /* Interrupt on conversion
complete */
+ ADC_CH_INTMODE_BELOW_gc = (0x01<<2), /* Interrupt on result below compare
value */
+ ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), /* Interrupt on result above compare
value */
+} ADC_CH_INTMODE_t;
+
+/* Interrupt level */
+typedef enum ADC_CH_INTLVL_enum
+{
+ ADC_CH_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ ADC_CH_INTLVL_LO_gc = (0x01<<0), /* Low level */
+ ADC_CH_INTLVL_MED_gc = (0x02<<0), /* Medium level */
+ ADC_CH_INTLVL_HI_gc = (0x03<<0), /* High level */
+} ADC_CH_INTLVL_t;
+
+/* DMA request selection */
+typedef enum ADC_DMASEL_enum
+{
+ ADC_DMASEL_OFF_gc = (0x00<<6), /* Combined DMA request OFF */
+ ADC_DMASEL_CH01_gc = (0x01<<6), /* ADC Channel 0 or 1 */
+ ADC_DMASEL_CH012_gc = (0x02<<6), /* ADC Channel 0 or 1 or 2 */
+ ADC_DMASEL_CH0123_gc = (0x03<<6), /* ADC Channel 0 or 1 or 2 or 3 */
+} ADC_DMASEL_t;
+
+/* Clock prescaler */
+typedef enum ADC_PRESCALER_enum
+{
+ ADC_PRESCALER_DIV4_gc = (0x00<<0), /* Divide clock by 4 */
+ ADC_PRESCALER_DIV8_gc = (0x01<<0), /* Divide clock by 8 */
+ ADC_PRESCALER_DIV16_gc = (0x02<<0), /* Divide clock by 16 */
+ ADC_PRESCALER_DIV32_gc = (0x03<<0), /* Divide clock by 32 */
+ ADC_PRESCALER_DIV64_gc = (0x04<<0), /* Divide clock by 64 */
+ ADC_PRESCALER_DIV128_gc = (0x05<<0), /* Divide clock by 128 */
+ ADC_PRESCALER_DIV256_gc = (0x06<<0), /* Divide clock by 256 */
+ ADC_PRESCALER_DIV512_gc = (0x07<<0), /* Divide clock by 512 */
+} ADC_PRESCALER_t;
+
+
+/*
+--------------------------------------------------------------------------
+DAC - Digital/Analog Converter
+--------------------------------------------------------------------------
+*/
+
+/* Digital-to-Analog Converter */
+typedef struct DAC_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control Register C */
+ register8_t EVCTRL; /* Event Input Control */
+ register8_t TIMCTRL; /* Timing Control */
+ register8_t STATUS; /* Status */
+ register8_t reserved_0x06;
+ register8_t reserved_0x07;
+ register8_t CH0GAINCAL; /* Gain Calibration */
+ register8_t CH0OFFSETCAL; /* Offset Calibration */
+ register8_t CH1GAINCAL; /* Gain Calibration */
+ register8_t CH1OFFSETCAL; /* Offset Calibration */
+ register8_t reserved_0x0C;
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ register8_t reserved_0x10;
+ register8_t reserved_0x11;
+ register8_t reserved_0x12;
+ register8_t reserved_0x13;
+ register8_t reserved_0x14;
+ register8_t reserved_0x15;
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ _WORDREGISTER(CH0DATA); /* Channel 0 Data */
+ _WORDREGISTER(CH1DATA); /* Channel 1 Data */
+} DAC_t;
+
+/* Output channel selection */
+typedef enum DAC_CHSEL_enum
+{
+ DAC_CHSEL_SINGLE_gc = (0x00<<5), /* Single channel operation (Channel 0
only) */
+ DAC_CHSEL_SINGLE1_gc = (0x01<<5), /* Single channel operation (Channel 1
only) */
+ DAC_CHSEL_DUAL_gc = (0x02<<5), /* Dual channel operation (Channel 0 and
channel 1) */
+} DAC_CHSEL_t;
+
+/* Reference voltage selection */
+typedef enum DAC_REFSEL_enum
+{
+ DAC_REFSEL_INT1V_gc = (0x00<<3), /* Internal 1V */
+ DAC_REFSEL_AVCC_gc = (0x01<<3), /* Analog supply voltage */
+ DAC_REFSEL_AREFA_gc = (0x02<<3), /* External reference on AREF on PORTA */
+ DAC_REFSEL_AREFB_gc = (0x03<<3), /* External reference on AREF on PORTB */
+} DAC_REFSEL_t;
+
+/* Event channel selection */
+typedef enum DAC_EVSEL_enum
+{
+ DAC_EVSEL_0_gc = (0x00<<0), /* Event Channel 0 */
+ DAC_EVSEL_1_gc = (0x01<<0), /* Event Channel 1 */
+ DAC_EVSEL_2_gc = (0x02<<0), /* Event Channel 2 */
+ DAC_EVSEL_3_gc = (0x03<<0), /* Event Channel 3 */
+ DAC_EVSEL_4_gc = (0x04<<0), /* Event Channel 4 */
+ DAC_EVSEL_5_gc = (0x05<<0), /* Event Channel 5 */
+ DAC_EVSEL_6_gc = (0x06<<0), /* Event Channel 6 */
+ DAC_EVSEL_7_gc = (0x07<<0), /* Event Channel 7 */
+} DAC_EVSEL_t;
+
+/* Conversion interval */
+typedef enum DAC_CONINTVAL_enum
+{
+ DAC_CONINTVAL_1CLK_gc = (0x00<<4), /* 1 CLK / 2 CLK in S/H mode */
+ DAC_CONINTVAL_2CLK_gc = (0x01<<4), /* 2 CLK / 3 CLK in S/H mode */
+ DAC_CONINTVAL_4CLK_gc = (0x02<<4), /* 4 CLK / 6 CLK in S/H mode */
+ DAC_CONINTVAL_8CLK_gc = (0x03<<4), /* 8 CLK / 12 CLK in S/H mode */
+ DAC_CONINTVAL_16CLK_gc = (0x04<<4), /* 16 CLK / 24 CLK in S/H mode */
+ DAC_CONINTVAL_32CLK_gc = (0x05<<4), /* 32 CLK / 48 CLK in S/H mode */
+ DAC_CONINTVAL_64CLK_gc = (0x06<<4), /* 64 CLK / 96 CLK in S/H mode */
+ DAC_CONINTVAL_128CLK_gc = (0x07<<4), /* 128 CLK / 192 CLK in S/H mode */
+} DAC_CONINTVAL_t;
+
+/* Refresh rate */
+typedef enum DAC_REFRESH_enum
+{
+ DAC_REFRESH_16CLK_gc = (0x00<<0), /* 16 CLK */
+ DAC_REFRESH_32CLK_gc = (0x01<<0), /* 32 CLK */
+ DAC_REFRESH_64CLK_gc = (0x02<<0), /* 64 CLK */
+ DAC_REFRESH_128CLK_gc = (0x03<<0), /* 128 CLK */
+ DAC_REFRESH_256CLK_gc = (0x04<<0), /* 256 CLK */
+ DAC_REFRESH_512CLK_gc = (0x05<<0), /* 512 CLK */
+ DAC_REFRESH_1024CLK_gc = (0x06<<0), /* 1024 CLK */
+ DAC_REFRESH_2048CLK_gc = (0x07<<0), /* 2048 CLK */
+ DAC_REFRESH_4086CLK_gc = (0x08<<0), /* 4096 CLK */
+ DAC_REFRESH_8192CLK_gc = (0x09<<0), /* 8192 CLK */
+ DAC_REFRESH_16384CLK_gc = (0x0A<<0), /* 16384 CLK */
+ DAC_REFRESH_32768CLK_gc = (0x0B<<0), /* 32768 CLK */
+ DAC_REFRESH_65536CLK_gc = (0x0C<<0), /* 65536 CLK */
+ DAC_REFRESH_OFF_gc = (0x0F<<0), /* Auto refresh OFF */
+} DAC_REFRESH_t;
+
+
+/*
+--------------------------------------------------------------------------
+AC - Analog Comparator
+--------------------------------------------------------------------------
+*/
+
+/* Analog Comparator */
+typedef struct AC_struct
+{
+ register8_t AC0CTRL; /* Analog Comparator 0 Control */
+ register8_t AC1CTRL; /* Analog Comparator 1 Control */
+ register8_t AC0MUXCTRL; /* Analog Comparator 0 MUX Control */
+ register8_t AC1MUXCTRL; /* Analog Comparator 1 MUX Control */
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t WINCTRL; /* Window Mode Control */
+ register8_t STATUS; /* Status */
+} AC_t;
+
+/* Interrupt mode */
+typedef enum AC_INTMODE_enum
+{
+ AC_INTMODE_BOTHEDGES_gc = (0x00<<6), /* Interrupt on both edges */
+ AC_INTMODE_FALLING_gc = (0x02<<6), /* Interrupt on falling edge */
+ AC_INTMODE_RISING_gc = (0x03<<6), /* Interrupt on rising edge */
+} AC_INTMODE_t;
+
+/* Interrupt level */
+typedef enum AC_INTLVL_enum
+{
+ AC_INTLVL_OFF_gc = (0x00<<4), /* Interrupt disabled */
+ AC_INTLVL_LO_gc = (0x01<<4), /* Low level */
+ AC_INTLVL_MED_gc = (0x02<<4), /* Medium level */
+ AC_INTLVL_HI_gc = (0x03<<4), /* High level */
+} AC_INTLVL_t;
+
+/* Hysteresis mode selection */
+typedef enum AC_HYSMODE_enum
+{
+ AC_HYSMODE_NO_gc = (0x00<<1), /* No hysteresis */
+ AC_HYSMODE_SMALL_gc = (0x01<<1), /* Small hysteresis */
+ AC_HYSMODE_LARGE_gc = (0x02<<1), /* Large hysteresis */
+} AC_HYSMODE_t;
+
+/* Positive input multiplexer selection */
+typedef enum AC_MUXPOS_enum
+{
+ AC_MUXPOS_PIN0_gc = (0x00<<3), /* Pin 0 */
+ AC_MUXPOS_PIN1_gc = (0x01<<3), /* Pin 1 */
+ AC_MUXPOS_PIN2_gc = (0x02<<3), /* Pin 2 */
+ AC_MUXPOS_PIN3_gc = (0x03<<3), /* Pin 3 */
+ AC_MUXPOS_PIN4_gc = (0x04<<3), /* Pin 4 */
+ AC_MUXPOS_PIN5_gc = (0x05<<3), /* Pin 5 */
+ AC_MUXPOS_PIN6_gc = (0x06<<3), /* Pin 6 */
+ AC_MUXPOS_DAC_gc = (0x07<<3), /* DAC output */
+} AC_MUXPOS_t;
+
+/* Negative input multiplexer selection */
+typedef enum AC_MUXNEG_enum
+{
+ AC_MUXNEG_PIN0_gc = (0x00<<0), /* Pin 0 */
+ AC_MUXNEG_PIN1_gc = (0x01<<0), /* Pin 1 */
+ AC_MUXNEG_PIN3_gc = (0x02<<0), /* Pin 3 */
+ AC_MUXNEG_PIN5_gc = (0x03<<0), /* Pin 5 */
+ AC_MUXNEG_PIN7_gc = (0x04<<0), /* Pin 7 */
+ AC_MUXNEG_DAC_gc = (0x05<<0), /* DAC output */
+ AC_MUXNEG_BANDGAP_gc = (0x06<<0), /* Bandgap Reference */
+ AC_MUXNEG_SCALER_gc = (0x07<<0), /* Internal voltage scaler */
+} AC_MUXNEG_t;
+
+/* Windows interrupt mode */
+typedef enum AC_WINTMODE_enum
+{
+ AC_WINTMODE_ABOVE_gc = (0x00<<2), /* Interrupt on above window */
+ AC_WINTMODE_INSIDE_gc = (0x01<<2), /* Interrupt on inside window */
+ AC_WINTMODE_BELOW_gc = (0x02<<2), /* Interrupt on below window */
+ AC_WINTMODE_OUTSIDE_gc = (0x03<<2), /* Interrupt on outside window */
+} AC_WINTMODE_t;
+
+/* Window interrupt level */
+typedef enum AC_WINTLVL_enum
+{
+ AC_WINTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ AC_WINTLVL_LO_gc = (0x01<<0), /* Low priority */
+ AC_WINTLVL_MED_gc = (0x02<<0), /* Medium priority */
+ AC_WINTLVL_HI_gc = (0x03<<0), /* High priority */
+} AC_WINTLVL_t;
+
+/* Window mode state */
+typedef enum AC_WSTATE_enum
+{
+ AC_WSTATE_ABOVE_gc = (0x00<<6), /* Signal above window */
+ AC_WSTATE_INSIDE_gc = (0x01<<6), /* Signal inside window */
+ AC_WSTATE_BELOW_gc = (0x02<<6), /* Signal below window */
+} AC_WSTATE_t;
+
+
+/*
+--------------------------------------------------------------------------
+RTC - Real-Time Clounter
+--------------------------------------------------------------------------
+*/
+
+/* Real-Time Counter */
+typedef struct RTC_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t INTCTRL; /* Interrupt Control Register */
+ register8_t INTFLAGS; /* Interrupt Flags */
+ register8_t TEMP; /* Temporary register */
+ register8_t reserved_0x05;
+ register8_t reserved_0x06;
+ register8_t reserved_0x07;
+ _WORDREGISTER(CNT); /* Count Register */
+ _WORDREGISTER(PER); /* Period Register */
+ _WORDREGISTER(COMP); /* Compare Register */
+} RTC_t;
+
+/* Prescaler Factor */
+typedef enum RTC_PRESCALER_enum
+{
+ RTC_PRESCALER_OFF_gc = (0x00<<0), /* RTC Off */
+ RTC_PRESCALER_DIV1_gc = (0x01<<0), /* RTC Clock */
+ RTC_PRESCALER_DIV2_gc = (0x02<<0), /* RTC Clock / 2 */
+ RTC_PRESCALER_DIV8_gc = (0x03<<0), /* RTC Clock / 8 */
+ RTC_PRESCALER_DIV16_gc = (0x04<<0), /* RTC Clock / 16 */
+ RTC_PRESCALER_DIV64_gc = (0x05<<0), /* RTC Clock / 64 */
+ RTC_PRESCALER_DIV256_gc = (0x06<<0), /* RTC Clock / 256 */
+ RTC_PRESCALER_DIV1024_gc = (0x07<<0), /* RTC Clock / 1024 */
+} RTC_PRESCALER_t;
+
+/* Compare Interrupt level */
+typedef enum RTC_COMPINTLVL_enum
+{
+ RTC_COMPINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ RTC_COMPINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ RTC_COMPINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ RTC_COMPINTLVL_HI_gc = (0x03<<2), /* High Level */
+} RTC_COMPINTLVL_t;
+
+/* Overflow Interrupt level */
+typedef enum RTC_OVFINTLVL_enum
+{
+ RTC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ RTC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ RTC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ RTC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
+} RTC_OVFINTLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+EBI - External Bus Interface
+--------------------------------------------------------------------------
+*/
+
+/* EBI Chip Select Module */
+typedef struct EBI_CS_struct
+{
+ register8_t CTRLA; /* Chip Select Control Register A */
+ register8_t CTRLB; /* Chip Select Control Register B */
+ _WORDREGISTER(BASEADDR); /* Chip Select Base Address */
+} EBI_CS_t;
+
+/*
+--------------------------------------------------------------------------
+EBI - External Bus Interface
+--------------------------------------------------------------------------
+*/
+
+/* External Bus Interface */
+typedef struct EBI_struct
+{
+ register8_t CTRL; /* Control */
+ register8_t SDRAMCTRLA; /* SDRAM Control Register A */
+ register8_t reserved_0x02;
+ register8_t reserved_0x03;
+ _WORDREGISTER(REFRESH); /* SDRAM Refresh Period */
+ _WORDREGISTER(INITDLY); /* SDRAM Initialization Delay */
+ register8_t SDRAMCTRLB; /* SDRAM Control Register B */
+ register8_t SDRAMCTRLC; /* SDRAM Control Register C */
+ register8_t reserved_0x0A;
+ register8_t reserved_0x0B;
+ register8_t reserved_0x0C;
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ EBI_CS_t CS0; /* Chip Select 0 */
+ EBI_CS_t CS1; /* Chip Select 1 */
+ EBI_CS_t CS2; /* Chip Select 2 */
+ EBI_CS_t CS3; /* Chip Select 3 */
+} EBI_t;
+
+/* Chip Select adress space */
+typedef enum EBI_CS_ASPACE_enum
+{
+ EBI_CS_ASPACE_256B_gc = (0x00<<2), /* 256 bytes */
+ EBI_CS_ASPACE_512B_gc = (0x01<<2), /* 512 bytes */
+ EBI_CS_ASPACE_1KB_gc = (0x02<<2), /* 1K bytes */
+ EBI_CS_ASPACE_2KB_gc = (0x03<<2), /* 2K bytes */
+ EBI_CS_ASPACE_4KB_gc = (0x04<<2), /* 4K bytes */
+ EBI_CS_ASPACE_8KB_gc = (0x05<<2), /* 8K bytes */
+ EBI_CS_ASPACE_16KB_gc = (0x06<<2), /* 16K bytes */
+ EBI_CS_ASPACE_32KB_gc = (0x07<<2), /* 32K bytes */
+ EBI_CS_ASPACE_64KB_gc = (0x08<<2), /* 64K bytes */
+ EBI_CS_ASPACE_128KB_gc = (0x09<<2), /* 128K bytes */
+ EBI_CS_ASPACE_256KB_gc = (0x0A<<2), /* 256K bytes */
+ EBI_CS_ASPACE_512KB_gc = (0x0B<<2), /* 512K bytes */
+ EBI_CS_ASPACE_1MB_gc = (0x0C<<2), /* 1M bytes */
+ EBI_CS_ASPACE_2MB_gc = (0x0D<<2), /* 2M bytes */
+ EBI_CS_ASPACE_4MB_gc = (0x0E<<2), /* 4M bytes */
+ EBI_CS_ASPACE_8MB_gc = (0x0F<<2), /* 8M bytes */
+ EBI_CS_ASPACE_16M_gc = (0x10<<2), /* 16M bytes */
+} EBI_CS_ASPACE_t;
+
+/* */
+typedef enum EBI_CS_SRWS_enum
+{
+ EBI_CS_SRWS_0CLK_gc = (0x00<<0), /* 0 cycles */
+ EBI_CS_SRWS_1CLK_gc = (0x01<<0), /* 1 cycle */
+ EBI_CS_SRWS_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_CS_SRWS_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_CS_SRWS_4CLK_gc = (0x04<<0), /* 4 cycles */
+ EBI_CS_SRWS_5CLK_gc = (0x05<<0), /* 5 cycle */
+ EBI_CS_SRWS_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_CS_SRWS_7CLK_gc = (0x07<<0), /* 7 cycles */
+} EBI_CS_SRWS_t;
+
+/* Chip Select address mode */
+typedef enum EBI_CS_MODE_enum
+{
+ EBI_CS_MODE_DISABLED_gc = (0x00<<0), /* Chip Select Disabled */
+ EBI_CS_MODE_SRAM_gc = (0x01<<0), /* Chip Select in SRAM mode */
+ EBI_CS_MODE_LPC_gc = (0x02<<0), /* Chip Select in SRAM LPC mode */
+ EBI_CS_MODE_SDRAM_gc = (0x03<<0), /* Chip Select in SDRAM mode */
+} EBI_CS_MODE_t;
+
+/* Chip Select SDRAM mode */
+typedef enum EBI_CS_SDMODE_enum
+{
+ EBI_CS_SDMODE_NORMAL_gc = (0x00<<0), /* Normal mode */
+ EBI_CS_SDMODE_LOAD_gc = (0x01<<0), /* Load Mode Register command mode */
+} EBI_CS_SDMODE_t;
+
+/* */
+typedef enum EBI_SDDATAW_enum
+{
+ EBI_SDDATAW_4BIT_gc = (0x00<<6), /* 4-bit data bus */
+ EBI_SDDATAW_8BIT_gc = (0x01<<6), /* 8-bit data bus */
+} EBI_SDDATAW_t;
+
+/* */
+typedef enum EBI_LPCMODE_enum
+{
+ EBI_LPCMODE_ALE1_gc = (0x00<<4), /* Data muxed with addr byte 0 */
+ EBI_LPCMODE_ALE12_gc = (0x02<<4), /* Data muxed with addr byte 0 and 1 */
+} EBI_LPCMODE_t;
+
+/* */
+typedef enum EBI_SRMODE_enum
+{
+ EBI_SRMODE_ALE1_gc = (0x00<<2), /* Addr byte 0 muxed with 1 */
+ EBI_SRMODE_ALE2_gc = (0x01<<2), /* Addr byte 0 muxed with 2 */
+ EBI_SRMODE_ALE12_gc = (0x02<<2), /* Addr byte 0 muxed with 1 and 2 */
+ EBI_SRMODE_NOALE_gc = (0x03<<2), /* No addr muxing */
+} EBI_SRMODE_t;
+
+/* */
+typedef enum EBI_IFMODE_enum
+{
+ EBI_IFMODE_DISABLED_gc = (0x00<<0), /* EBI Disabled */
+ EBI_IFMODE_3PORT_gc = (0x01<<0), /* 3-port mode */
+ EBI_IFMODE_4PORT_gc = (0x02<<0), /* 4-port mode */
+ EBI_IFMODE_2PORT_gc = (0x03<<0), /* 2-port mode */
+} EBI_IFMODE_t;
+
+/* */
+typedef enum EBI_SDCOL_enum
+{
+ EBI_SDCOL_8BIT_gc = (0x00<<0), /* 8 column bits */
+ EBI_SDCOL_9BIT_gc = (0x01<<0), /* 9 column bits */
+ EBI_SDCOL_10BIT_gc = (0x02<<0), /* 10 column bits */
+ EBI_SDCOL_11BIT_gc = (0x03<<0), /* 11 column bits */
+} EBI_SDCOL_t;
+
+/* */
+typedef enum EBI_MRDLY_enum
+{
+ EBI_MRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
+ EBI_MRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
+ EBI_MRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
+ EBI_MRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
+} EBI_MRDLY_t;
+
+/* */
+typedef enum EBI_ROWCYCDLY_enum
+{
+ EBI_ROWCYCDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
+ EBI_ROWCYCDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
+ EBI_ROWCYCDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
+ EBI_ROWCYCDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
+ EBI_ROWCYCDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
+ EBI_ROWCYCDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
+ EBI_ROWCYCDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
+ EBI_ROWCYCDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
+} EBI_ROWCYCDLY_t;
+
+/* */
+typedef enum EBI_RPDLY_enum
+{
+ EBI_RPDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
+ EBI_RPDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
+ EBI_RPDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_RPDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_RPDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
+ EBI_RPDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
+ EBI_RPDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_RPDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
+} EBI_RPDLY_t;
+
+/* */
+typedef enum EBI_WRDLY_enum
+{
+ EBI_WRDLY_0CLK_gc = (0x00<<6), /* 0 cycles */
+ EBI_WRDLY_1CLK_gc = (0x01<<6), /* 1 cycle */
+ EBI_WRDLY_2CLK_gc = (0x02<<6), /* 2 cycles */
+ EBI_WRDLY_3CLK_gc = (0x03<<6), /* 3 cycles */
+} EBI_WRDLY_t;
+
+/* */
+typedef enum EBI_ESRDLY_enum
+{
+ EBI_ESRDLY_0CLK_gc = (0x00<<3), /* 0 cycles */
+ EBI_ESRDLY_1CLK_gc = (0x01<<3), /* 1 cycle */
+ EBI_ESRDLY_2CLK_gc = (0x02<<3), /* 2 cycles */
+ EBI_ESRDLY_3CLK_gc = (0x03<<3), /* 3 cycles */
+ EBI_ESRDLY_4CLK_gc = (0x04<<3), /* 4 cycles */
+ EBI_ESRDLY_5CLK_gc = (0x05<<3), /* 5 cycle */
+ EBI_ESRDLY_6CLK_gc = (0x06<<3), /* 6 cycles */
+ EBI_ESRDLY_7CLK_gc = (0x07<<3), /* 7 cycles */
+} EBI_ESRDLY_t;
+
+/* */
+typedef enum EBI_ROWCOLDLY_enum
+{
+ EBI_ROWCOLDLY_0CLK_gc = (0x00<<0), /* 0 cycles */
+ EBI_ROWCOLDLY_1CLK_gc = (0x01<<0), /* 1 cycle */
+ EBI_ROWCOLDLY_2CLK_gc = (0x02<<0), /* 2 cycles */
+ EBI_ROWCOLDLY_3CLK_gc = (0x03<<0), /* 3 cycles */
+ EBI_ROWCOLDLY_4CLK_gc = (0x04<<0), /* 4 cycles */
+ EBI_ROWCOLDLY_5CLK_gc = (0x05<<0), /* 5 cycle */
+ EBI_ROWCOLDLY_6CLK_gc = (0x06<<0), /* 6 cycles */
+ EBI_ROWCOLDLY_7CLK_gc = (0x07<<0), /* 7 cycles */
+} EBI_ROWCOLDLY_t;
+
+
+/*
+--------------------------------------------------------------------------
+TWI - Two-Wire Interface
+--------------------------------------------------------------------------
+*/
+
+/* */
+typedef struct TWI_MASTER_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control Register C */
+ register8_t STATUS; /* Status Register */
+ register8_t BAUD; /* Baurd Rate Control Register */
+ register8_t ADDR; /* Address Register */
+ register8_t DATA; /* Data Register */
+} TWI_MASTER_t;
+
+/*
+--------------------------------------------------------------------------
+TWI - Two-Wire Interface
+--------------------------------------------------------------------------
+*/
+
+/* */
+typedef struct TWI_SLAVE_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t STATUS; /* Status Register */
+ register8_t ADDR; /* Address Register */
+ register8_t DATA; /* Data Register */
+ register8_t ADDRMASK; /* Address Mask Register */
+} TWI_SLAVE_t;
+
+/*
+--------------------------------------------------------------------------
+TWI - Two-Wire Interface
+--------------------------------------------------------------------------
+*/
+
+/* Two-Wire Interface */
+typedef struct TWI_struct
+{
+ register8_t CTRL; /* TWI Common Control Register */
+ TWI_MASTER_t MASTER; /* TWI master module */
+ TWI_SLAVE_t SLAVE; /* TWI slave module */
+} TWI_t;
+
+/* Master Interrupt Level */
+typedef enum TWI_MASTER_INTLVL_enum
+{
+ TWI_MASTER_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
+ TWI_MASTER_INTLVL_LO_gc = (0x01<<6), /* Low Level */
+ TWI_MASTER_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
+ TWI_MASTER_INTLVL_HI_gc = (0x03<<6), /* High Level */
+} TWI_MASTER_INTLVL_t;
+
+/* Inactive Timeout */
+typedef enum TWI_MASTER_TIMEOUT_enum
+{
+ TWI_MASTER_TIMEOUT_DISABLED_gc = (0x00<<2), /* Bus Timeout Disabled */
+ TWI_MASTER_TIMEOUT_50US_gc = (0x01<<2), /* 50 Microseconds */
+ TWI_MASTER_TIMEOUT_100US_gc = (0x02<<2), /* 100 Microseconds */
+ TWI_MASTER_TIMEOUT_200US_gc = (0x03<<2), /* 200 Microseconds */
+} TWI_MASTER_TIMEOUT_t;
+
+/* Master Command */
+typedef enum TWI_MASTER_CMD_enum
+{
+ TWI_MASTER_CMD_NOACT_gc = (0x00<<0), /* No Action */
+ TWI_MASTER_CMD_REPSTART_gc = (0x01<<0), /* Issue Repeated Start Condition
*/
+ TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0), /* Receive or Transmit Data */
+ TWI_MASTER_CMD_STOP_gc = (0x03<<0), /* Issue Stop Condition */
+} TWI_MASTER_CMD_t;
+
+/* Master Bus State */
+typedef enum TWI_MASTER_BUSSTATE_enum
+{
+ TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0), /* Unknown Bus State */
+ TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0), /* Bus is Idle */
+ TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0), /* This Module Controls The Bus
*/
+ TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0), /* The Bus is Busy */
+} TWI_MASTER_BUSSTATE_t;
+
+/* Slave Interrupt Level */
+typedef enum TWI_SLAVE_INTLVL_enum
+{
+ TWI_SLAVE_INTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
+ TWI_SLAVE_INTLVL_LO_gc = (0x01<<6), /* Low Level */
+ TWI_SLAVE_INTLVL_MED_gc = (0x02<<6), /* Medium Level */
+ TWI_SLAVE_INTLVL_HI_gc = (0x03<<6), /* High Level */
+} TWI_SLAVE_INTLVL_t;
+
+/* Slave Command */
+typedef enum TWI_SLAVE_CMD_enum
+{
+ TWI_SLAVE_CMD_NOACT_gc = (0x00<<0), /* No Action */
+ TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0), /* Used To Complete a Transaction
*/
+ TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), /* Used in Response to
Address/Data Interrupt */
+} TWI_SLAVE_CMD_t;
+
+
+/*
+--------------------------------------------------------------------------
+USB - USB Module
+--------------------------------------------------------------------------
+*/
+
+/* USB Endpoint */
+typedef struct USB_EP_struct
+{
+ register8_t STATUS; /* Endpoint Status */
+ register8_t CTRL; /* Endpoint Control */
+ register8_t CNTL; /* USB Endpoint Counter Low Byte */
+ register8_t CNTH; /* USB Endpoint Counter High Byte */
+ register8_t DATAPTRL; /* Data Pointer Low Byte */
+ register8_t DATAPTRH; /* Data Pointer High Byte */
+ register8_t AUXDATAL; /* Auxiliary Data Low Byte */
+ register8_t AUXDATAH; /* Auxiliary Data High Byte */
+} USB_EP_t;
+
+/*
+--------------------------------------------------------------------------
+USB - USB Module
+--------------------------------------------------------------------------
+*/
+
+/* USB Endpoint table */
+typedef struct USB_EP_TABLE_struct
+{
+ USB_EP_t EP0OUT; /* USB Endpoint 0 Output */
+ USB_EP_t EP0IN; /* USB Endpoint 0 Input */
+ USB_EP_t EP1OUT; /* USB Endpoint 1 Output */
+ USB_EP_t EP1IN; /* USB Endpoint 1 Input */
+ USB_EP_t EP2OUT; /* USB Endpoint 2 Output */
+ USB_EP_t EP2IN; /* USB Endpoint 2 Input */
+ USB_EP_t EP3OUT; /* USB Endpoint 3 Output */
+ USB_EP_t EP3IN; /* USB Endpoint 3 Input */
+ USB_EP_t EP4OUT; /* USB Endpoint 4 Output */
+ USB_EP_t EP4IN; /* USB Endpoint 4 Input */
+ USB_EP_t EP5OUT; /* USB Endpoint 5 Output */
+ USB_EP_t EP5IN; /* USB Endpoint 5 Input */
+ USB_EP_t EP6OUT; /* USB Endpoint 6 Output */
+ USB_EP_t EP6IN; /* USB Endpoint 6 Input */
+ USB_EP_t EP7OUT; /* USB Endpoint 7 Output */
+ USB_EP_t EP7IN; /* USB Endpoint 7 Input */
+ USB_EP_t EP8OUT; /* USB Endpoint 8 Output */
+ USB_EP_t EP8IN; /* USB Endpoint 8 Input */
+ USB_EP_t EP9OUT; /* USB Endpoint 9 Output */
+ USB_EP_t EP9IN; /* USB Endpoint 9 Input */
+ USB_EP_t EP10OUT; /* USB Endpoint 10 Output */
+ USB_EP_t EP10IN; /* USB Endpoint 10 Input */
+ USB_EP_t EP11OUT; /* USB Endpoint 11 Output */
+ USB_EP_t EP11IN; /* USB Endpoint 11 Input */
+ USB_EP_t EP12OUT; /* USB Endpoint 12 Output */
+ USB_EP_t EP12IN; /* USB Endpoint 12 Input */
+ USB_EP_t EP13OUT; /* USB Endpoint 13 Output */
+ USB_EP_t EP13IN; /* USB Endpoint 13 Input */
+ USB_EP_t EP14OUT; /* USB Endpoint 14 Output */
+ USB_EP_t EP14IN; /* USB Endpoint 14 Input */
+ USB_EP_t EP15OUT; /* USB Endpoint 15 Output */
+ USB_EP_t EP15IN; /* USB Endpoint 15 Input */
+ register8_t FRAMENUML; /* Frame Number Low Byte */
+ register8_t FRAMENUMH; /* Frame Number High Byte */
+} USB_EP_TABLE_t;
+
+/*
+--------------------------------------------------------------------------
+USB - USB Module
+--------------------------------------------------------------------------
+*/
+
+/* USB Module */
+typedef struct USB_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t STATUS; /* Status Register */
+ register8_t ADDR; /* Address Register */
+ register8_t FIFOWP; /* FIFO Write Pointer Register */
+ register8_t FIFORP; /* FIFO Read Pointer Register */
+ _WORDREGISTER(EPPTR); /* Endpoint Configuration Table Pointer */
+ register8_t INTCTRLA; /* Interrupt Control Register A */
+ register8_t INTCTRLB; /* Interrupt Control Register B */
+ register8_t INTFLAGSACLR; /* Clear Interrupt Flag Register A */
+ register8_t INTFLAGSASET; /* Set Interrupt Flag Register A */
+ register8_t INTFLAGSBCLR; /* Clear Interrupt Flag Register B */
+ register8_t INTFLAGSBSET; /* Set Interrupt Flag Register B */
+ register8_t reserved_0x0E;
+ register8_t reserved_0x0F;
+ register8_t reserved_0x10;
+ register8_t reserved_0x11;
+ register8_t reserved_0x12;
+ register8_t reserved_0x13;
+ register8_t reserved_0x14;
+ register8_t reserved_0x15;
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ register8_t reserved_0x18;
+ register8_t reserved_0x19;
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ register8_t reserved_0x20;
+ register8_t reserved_0x21;
+ register8_t reserved_0x22;
+ register8_t reserved_0x23;
+ register8_t reserved_0x24;
+ register8_t reserved_0x25;
+ register8_t reserved_0x26;
+ register8_t reserved_0x27;
+ register8_t reserved_0x28;
+ register8_t reserved_0x29;
+ register8_t reserved_0x2A;
+ register8_t reserved_0x2B;
+ register8_t reserved_0x2C;
+ register8_t reserved_0x2D;
+ register8_t reserved_0x2E;
+ register8_t reserved_0x2F;
+ register8_t reserved_0x30;
+ register8_t reserved_0x31;
+ register8_t reserved_0x32;
+ register8_t reserved_0x33;
+ register8_t reserved_0x34;
+ register8_t reserved_0x35;
+ register8_t reserved_0x36;
+ register8_t reserved_0x37;
+ register8_t reserved_0x38;
+ register8_t reserved_0x39;
+ register8_t CAL0; /* Calibration Byte 0 */
+ register8_t CAL1; /* Calibration Byte 1 */
+} USB_t;
+
+/* USB Endpoint Type */
+typedef enum USB_EP_TYPE_enum
+{
+ USB_EP_TYPE_DISABLE_gc = (0x00<<6), /* Endpoint Disabled */
+ USB_EP_TYPE_CONTROL_gc = (0x01<<6), /* Control */
+ USB_EP_TYPE_BULK_gc = (0x02<<6), /* Bulk/Interrupt */
+ USB_EP_TYPE_ISOCHRONOUS_gc = (0x03<<6), /* Isochronous */
+} USB_EP_TYPE_t;
+
+/* USB Endpoint Buffer Size */
+typedef enum USB_EP_SIZE_enum
+{
+ USB_EP_SIZE_8_gc = (0x00<<0), /* 8 bytes buffer size */
+ USB_EP_SIZE_16_gc = (0x01<<0), /* 16 bytes buffer size */
+ USB_EP_SIZE_32_gc = (0x02<<0), /* 32 bytes buffer size */
+ USB_EP_SIZE_64_gc = (0x03<<0), /* 64 bytes buffer size */
+ USB_EP_SIZE_128_gc = (0x04<<0), /* 128 bytes buffer size */
+ USB_EP_SIZE_256_gc = (0x05<<0), /* 256 bytes buffer size */
+ USB_EP_SIZE_512_gc = (0x06<<0), /* 512 bytes buffer size */
+ USB_EP_SIZE_1023_gc = (0x07<<0), /* 1023 bytes buffer size */
+} USB_EP_SIZE_t;
+
+/* Interrupt level */
+typedef enum USB_INTLVL_enum
+{
+ USB_INTLVL_OFF_gc = (0x00<<0), /* Interrupt disabled */
+ USB_INTLVL_LO_gc = (0x01<<0), /* Low Level */
+ USB_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ USB_INTLVL_HI_gc = (0x03<<0), /* High Level */
+} USB_INTLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+PORT - I/O Port Configuration
+--------------------------------------------------------------------------
+*/
+
+/* I/O Ports */
+typedef struct PORT_struct
+{
+ register8_t DIR; /* I/O Port Data Direction */
+ register8_t DIRSET; /* I/O Port Data Direction Set */
+ register8_t DIRCLR; /* I/O Port Data Direction Clear */
+ register8_t DIRTGL; /* I/O Port Data Direction Toggle */
+ register8_t OUT; /* I/O Port Output */
+ register8_t OUTSET; /* I/O Port Output Set */
+ register8_t OUTCLR; /* I/O Port Output Clear */
+ register8_t OUTTGL; /* I/O Port Output Toggle */
+ register8_t IN; /* I/O port Input */
+ register8_t INTCTRL; /* Interrupt Control Register */
+ register8_t INT0MASK; /* Port Interrupt 0 Mask */
+ register8_t INT1MASK; /* Port Interrupt 1 Mask */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0F;
+ register8_t PIN0CTRL; /* Pin 0 Control Register */
+ register8_t PIN1CTRL; /* Pin 1 Control Register */
+ register8_t PIN2CTRL; /* Pin 2 Control Register */
+ register8_t PIN3CTRL; /* Pin 3 Control Register */
+ register8_t PIN4CTRL; /* Pin 4 Control Register */
+ register8_t PIN5CTRL; /* Pin 5 Control Register */
+ register8_t PIN6CTRL; /* Pin 6 Control Register */
+ register8_t PIN7CTRL; /* Pin 7 Control Register */
+} PORT_t;
+
+/* Port Interrupt 0 Level */
+typedef enum PORT_INT0LVL_enum
+{
+ PORT_INT0LVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ PORT_INT0LVL_LO_gc = (0x01<<0), /* Low Level */
+ PORT_INT0LVL_MED_gc = (0x02<<0), /* Medium Level */
+ PORT_INT0LVL_HI_gc = (0x03<<0), /* High Level */
+} PORT_INT0LVL_t;
+
+/* Port Interrupt 1 Level */
+typedef enum PORT_INT1LVL_enum
+{
+ PORT_INT1LVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ PORT_INT1LVL_LO_gc = (0x01<<2), /* Low Level */
+ PORT_INT1LVL_MED_gc = (0x02<<2), /* Medium Level */
+ PORT_INT1LVL_HI_gc = (0x03<<2), /* High Level */
+} PORT_INT1LVL_t;
+
+/* Output/Pull Configuration */
+typedef enum PORT_OPC_enum
+{
+ PORT_OPC_TOTEM_gc = (0x00<<3), /* Totempole */
+ PORT_OPC_BUSKEEPER_gc = (0x01<<3), /* Totempole w/ Bus keeper on Input
and Output */
+ PORT_OPC_PULLDOWN_gc = (0x02<<3), /* Totempole w/ Pull-down on Input */
+ PORT_OPC_PULLUP_gc = (0x03<<3), /* Totempole w/ Pull-up on Input */
+ PORT_OPC_WIREDOR_gc = (0x04<<3), /* Wired OR */
+ PORT_OPC_WIREDAND_gc = (0x05<<3), /* Wired AND */
+ PORT_OPC_WIREDORPULL_gc = (0x06<<3), /* Wired OR w/ Pull-down */
+ PORT_OPC_WIREDANDPULL_gc = (0x07<<3), /* Wired AND w/ Pull-up */
+} PORT_OPC_t;
+
+/* Input/Sense Configuration */
+typedef enum PORT_ISC_enum
+{
+ PORT_ISC_BOTHEDGES_gc = (0x00<<0), /* Sense Both Edges */
+ PORT_ISC_RISING_gc = (0x01<<0), /* Sense Rising Edge */
+ PORT_ISC_FALLING_gc = (0x02<<0), /* Sense Falling Edge */
+ PORT_ISC_LEVEL_gc = (0x03<<0), /* Sense Level (Transparent For Events) */
+ PORT_ISC_INPUT_DISABLE_gc = (0x07<<0), /* Disable Digital Input Buffer */
+} PORT_ISC_t;
+
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* 16-bit Timer/Counter 0 */
+typedef struct TC0_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control register C */
+ register8_t CTRLD; /* Control Register D */
+ register8_t CTRLE; /* Control Register E */
+ register8_t reserved_0x05;
+ register8_t INTCTRLA; /* Interrupt Control Register A */
+ register8_t INTCTRLB; /* Interrupt Control Register B */
+ register8_t CTRLFCLR; /* Control Register F Clear */
+ register8_t CTRLFSET; /* Control Register F Set */
+ register8_t CTRLGCLR; /* Control Register G Clear */
+ register8_t CTRLGSET; /* Control Register G Set */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t TEMP; /* Temporary Register For 16-bit Access */
+ register8_t reserved_0x10;
+ register8_t reserved_0x11;
+ register8_t reserved_0x12;
+ register8_t reserved_0x13;
+ register8_t reserved_0x14;
+ register8_t reserved_0x15;
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ register8_t reserved_0x18;
+ register8_t reserved_0x19;
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ _WORDREGISTER(CNT); /* Count */
+ register8_t reserved_0x22;
+ register8_t reserved_0x23;
+ register8_t reserved_0x24;
+ register8_t reserved_0x25;
+ _WORDREGISTER(PER); /* Period */
+ _WORDREGISTER(CCA); /* Compare or Capture A */
+ _WORDREGISTER(CCB); /* Compare or Capture B */
+ _WORDREGISTER(CCC); /* Compare or Capture C */
+ _WORDREGISTER(CCD); /* Compare or Capture D */
+ register8_t reserved_0x30;
+ register8_t reserved_0x31;
+ register8_t reserved_0x32;
+ register8_t reserved_0x33;
+ register8_t reserved_0x34;
+ register8_t reserved_0x35;
+ _WORDREGISTER(PERBUF); /* Period Buffer */
+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
+ _WORDREGISTER(CCCBUF); /* Compare Or Capture C Buffer */
+ _WORDREGISTER(CCDBUF); /* Compare Or Capture D Buffer */
+} TC0_t;
+
+/*
+--------------------------------------------------------------------------
+TC - 16-bit Timer/Counter With PWM
+--------------------------------------------------------------------------
+*/
+
+/* 16-bit Timer/Counter 1 */
+typedef struct TC1_struct
+{
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control register C */
+ register8_t CTRLD; /* Control Register D */
+ register8_t CTRLE; /* Control Register E */
+ register8_t reserved_0x05;
+ register8_t INTCTRLA; /* Interrupt Control Register A */
+ register8_t INTCTRLB; /* Interrupt Control Register B */
+ register8_t CTRLFCLR; /* Control Register F Clear */
+ register8_t CTRLFSET; /* Control Register F Set */
+ register8_t CTRLGCLR; /* Control Register G Clear */
+ register8_t CTRLGSET; /* Control Register G Set */
+ register8_t INTFLAGS; /* Interrupt Flag Register */
+ register8_t reserved_0x0D;
+ register8_t reserved_0x0E;
+ register8_t TEMP; /* Temporary Register For 16-bit Access */
+ register8_t reserved_0x10;
+ register8_t reserved_0x11;
+ register8_t reserved_0x12;
+ register8_t reserved_0x13;
+ register8_t reserved_0x14;
+ register8_t reserved_0x15;
+ register8_t reserved_0x16;
+ register8_t reserved_0x17;
+ register8_t reserved_0x18;
+ register8_t reserved_0x19;
+ register8_t reserved_0x1A;
+ register8_t reserved_0x1B;
+ register8_t reserved_0x1C;
+ register8_t reserved_0x1D;
+ register8_t reserved_0x1E;
+ register8_t reserved_0x1F;
+ _WORDREGISTER(CNT); /* Count */
+ register8_t reserved_0x22;
+ register8_t reserved_0x23;
+ register8_t reserved_0x24;
+ register8_t reserved_0x25;
+ _WORDREGISTER(PER); /* Period */
+ _WORDREGISTER(CCA); /* Compare or Capture A */
+ _WORDREGISTER(CCB); /* Compare or Capture B */
+ register8_t reserved_0x2C;
+ register8_t reserved_0x2D;
+ register8_t reserved_0x2E;
+ register8_t reserved_0x2F;
+ register8_t reserved_0x30;
+ register8_t reserved_0x31;
+ register8_t reserved_0x32;
+ register8_t reserved_0x33;
+ register8_t reserved_0x34;
+ register8_t reserved_0x35;
+ _WORDREGISTER(PERBUF); /* Period Buffer */
+ _WORDREGISTER(CCABUF); /* Compare Or Capture A Buffer */
+ _WORDREGISTER(CCBBUF); /* Compare Or Capture B Buffer */
+} TC1_t;
+
+/* Clock Selection */
+typedef enum TC_CLKSEL_enum
+{
+ TC_CLKSEL_OFF_gc = (0x00<<0), /* Timer Off */
+ TC_CLKSEL_DIV1_gc = (0x01<<0), /* System Clock */
+ TC_CLKSEL_DIV2_gc = (0x02<<0), /* System Clock / 2 */
+ TC_CLKSEL_DIV4_gc = (0x03<<0), /* System Clock / 4 */
+ TC_CLKSEL_DIV8_gc = (0x04<<0), /* System Clock / 8 */
+ TC_CLKSEL_DIV64_gc = (0x05<<0), /* System Clock / 64 */
+ TC_CLKSEL_DIV256_gc = (0x06<<0), /* System Clock / 256 */
+ TC_CLKSEL_DIV1024_gc = (0x07<<0), /* System Clock / 1024 */
+ TC_CLKSEL_EVCH0_gc = (0x08<<0), /* Event Channel 0 */
+ TC_CLKSEL_EVCH1_gc = (0x09<<0), /* Event Channel 1 */
+ TC_CLKSEL_EVCH2_gc = (0x0A<<0), /* Event Channel 2 */
+ TC_CLKSEL_EVCH3_gc = (0x0B<<0), /* Event Channel 3 */
+ TC_CLKSEL_EVCH4_gc = (0x0C<<0), /* Event Channel 4 */
+ TC_CLKSEL_EVCH5_gc = (0x0D<<0), /* Event Channel 5 */
+ TC_CLKSEL_EVCH6_gc = (0x0E<<0), /* Event Channel 6 */
+ TC_CLKSEL_EVCH7_gc = (0x0F<<0), /* Event Channel 7 */
+} TC_CLKSEL_t;
+
+/* Waveform Generation Mode */
+typedef enum TC_WGMODE_enum
+{
+ TC_WGMODE_NORMAL_gc = (0x00<<0), /* Normal Mode */
+ TC_WGMODE_FRQ_gc = (0x01<<0), /* Frequency Generation Mode */
+ TC_WGMODE_SS_gc = (0x03<<0), /* Single Slope */
+ TC_WGMODE_DS_T_gc = (0x05<<0), /* Dual Slope, Update on TOP */
+ TC_WGMODE_DS_TB_gc = (0x06<<0), /* Dual Slope, Update on TOP and BOTTOM */
+ TC_WGMODE_DS_B_gc = (0x07<<0), /* Dual Slope, Update on BOTTOM */
+} TC_WGMODE_t;
+
+/* Event Action */
+typedef enum TC_EVACT_enum
+{
+ TC_EVACT_OFF_gc = (0x00<<5), /* No Event Action */
+ TC_EVACT_CAPT_gc = (0x01<<5), /* Input Capture */
+ TC_EVACT_UPDOWN_gc = (0x02<<5), /* Externally Controlled Up/Down Count */
+ TC_EVACT_QDEC_gc = (0x03<<5), /* Quadrature Decode */
+ TC_EVACT_RESTART_gc = (0x04<<5), /* Restart */
+ TC_EVACT_FRQ_gc = (0x05<<5), /* Frequency Capture */
+ TC_EVACT_PW_gc = (0x06<<5), /* Pulse-width Capture */
+} TC_EVACT_t;
+
+/* Event Selection */
+typedef enum TC_EVSEL_enum
+{
+ TC_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
+ TC_EVSEL_CH0_gc = (0x08<<0), /* Event Channel 0 */
+ TC_EVSEL_CH1_gc = (0x09<<0), /* Event Channel 1 */
+ TC_EVSEL_CH2_gc = (0x0A<<0), /* Event Channel 2 */
+ TC_EVSEL_CH3_gc = (0x0B<<0), /* Event Channel 3 */
+ TC_EVSEL_CH4_gc = (0x0C<<0), /* Event Channel 4 */
+ TC_EVSEL_CH5_gc = (0x0D<<0), /* Event Channel 5 */
+ TC_EVSEL_CH6_gc = (0x0E<<0), /* Event Channel 6 */
+ TC_EVSEL_CH7_gc = (0x0F<<0), /* Event Channel 7 */
+} TC_EVSEL_t;
+
+/* Error Interrupt Level */
+typedef enum TC_ERRINTLVL_enum
+{
+ TC_ERRINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ TC_ERRINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ TC_ERRINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ TC_ERRINTLVL_HI_gc = (0x03<<2), /* High Level */
+} TC_ERRINTLVL_t;
+
+/* Overflow Interrupt Level */
+typedef enum TC_OVFINTLVL_enum
+{
+ TC_OVFINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ TC_OVFINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ TC_OVFINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ TC_OVFINTLVL_HI_gc = (0x03<<0), /* High Level */
+} TC_OVFINTLVL_t;
+
+/* Compare or Capture D Interrupt Level */
+typedef enum TC_CCDINTLVL_enum
+{
+ TC_CCDINTLVL_OFF_gc = (0x00<<6), /* Interrupt Disabled */
+ TC_CCDINTLVL_LO_gc = (0x01<<6), /* Low Level */
+ TC_CCDINTLVL_MED_gc = (0x02<<6), /* Medium Level */
+ TC_CCDINTLVL_HI_gc = (0x03<<6), /* High Level */
+} TC_CCDINTLVL_t;
+
+/* Compare or Capture C Interrupt Level */
+typedef enum TC_CCCINTLVL_enum
+{
+ TC_CCCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
+ TC_CCCINTLVL_LO_gc = (0x01<<4), /* Low Level */
+ TC_CCCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
+ TC_CCCINTLVL_HI_gc = (0x03<<4), /* High Level */
+} TC_CCCINTLVL_t;
+
+/* Compare or Capture B Interrupt Level */
+typedef enum TC_CCBINTLVL_enum
+{
+ TC_CCBINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ TC_CCBINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ TC_CCBINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ TC_CCBINTLVL_HI_gc = (0x03<<2), /* High Level */
+} TC_CCBINTLVL_t;
+
+/* Compare or Capture A Interrupt Level */
+typedef enum TC_CCAINTLVL_enum
+{
+ TC_CCAINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ TC_CCAINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ TC_CCAINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ TC_CCAINTLVL_HI_gc = (0x03<<0), /* High Level */
+} TC_CCAINTLVL_t;
+
+/* Timer/Counter Command */
+typedef enum TC_CMD_enum
+{
+ TC_CMD_NONE_gc = (0x00<<2), /* No Command */
+ TC_CMD_UPDATE_gc = (0x01<<2), /* Force Update */
+ TC_CMD_RESTART_gc = (0x02<<2), /* Force Restart */
+ TC_CMD_RESET_gc = (0x03<<2), /* Force Hard Reset */
+} TC_CMD_t;
+
+
+/*
+--------------------------------------------------------------------------
+AWEX - Timer/Counter Advanced Waveform Extension
+--------------------------------------------------------------------------
+*/
+
+/* Advanced Waveform Extension */
+typedef struct AWEX_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t reserved_0x01;
+ register8_t FDEMASK; /* Fault Detection Event Mask */
+ register8_t FDCTRL; /* Fault Detection Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t reserved_0x05;
+ register8_t DTBOTH; /* Dead Time Both Sides */
+ register8_t DTBOTHBUF; /* Dead Time Both Sides Buffer */
+ register8_t DTLS; /* Dead Time Low Side */
+ register8_t DTHS; /* Dead Time High Side */
+ register8_t DTLSBUF; /* Dead Time Low Side Buffer */
+ register8_t DTHSBUF; /* Dead Time High Side Buffer */
+ register8_t OUTOVEN; /* Output Override Enable */
+} AWEX_t;
+
+/* Fault Detect Action */
+typedef enum AWEX_FDACT_enum
+{
+ AWEX_FDACT_NONE_gc = (0x00<<0), /* No Fault Protection */
+ AWEX_FDACT_CLEAROE_gc = (0x01<<0), /* Clear Output Enable Bits */
+ AWEX_FDACT_CLEARDIR_gc = (0x03<<0), /* Clear I/O Port Direction Bits */
+} AWEX_FDACT_t;
+
+
+/*
+--------------------------------------------------------------------------
+HIRES - Timer/Counter High-Resolution Extension
+--------------------------------------------------------------------------
+*/
+
+/* High-Resolution Extension */
+typedef struct HIRES_struct
+{
+ register8_t CTRLA; /* Control Register */
+} HIRES_t;
+
+/* High Resolution Enable */
+typedef enum HIRES_HREN_enum
+{
+ HIRES_HREN_NONE_gc = (0x00<<0), /* No Fault Protection */
+ HIRES_HREN_TC0_gc = (0x01<<0), /* Enable High Resolution on Timer/Counter
0 */
+ HIRES_HREN_TC1_gc = (0x02<<0), /* Enable High Resolution on Timer/Counter
1 */
+ HIRES_HREN_BOTH_gc = (0x03<<0), /* Enable High Resolution both
Timer/Counters */
+} HIRES_HREN_t;
+
+
+/*
+--------------------------------------------------------------------------
+USART - Universal Asynchronous Receiver-Transmitter
+--------------------------------------------------------------------------
+*/
+
+/* Universal Synchronous/Asynchronous Receiver/Transmitter */
+typedef struct USART_struct
+{
+ register8_t DATA; /* Data Register */
+ register8_t STATUS; /* Status Register */
+ register8_t reserved_0x02;
+ register8_t CTRLA; /* Control Register A */
+ register8_t CTRLB; /* Control Register B */
+ register8_t CTRLC; /* Control Register C */
+ register8_t BAUDCTRLA; /* Baud Rate Control Register A */
+ register8_t BAUDCTRLB; /* Baud Rate Control Register B */
+} USART_t;
+
+/* Receive Complete Interrupt level */
+typedef enum USART_RXCINTLVL_enum
+{
+ USART_RXCINTLVL_OFF_gc = (0x00<<4), /* Interrupt Disabled */
+ USART_RXCINTLVL_LO_gc = (0x01<<4), /* Low Level */
+ USART_RXCINTLVL_MED_gc = (0x02<<4), /* Medium Level */
+ USART_RXCINTLVL_HI_gc = (0x03<<4), /* High Level */
+} USART_RXCINTLVL_t;
+
+/* Transmit Complete Interrupt level */
+typedef enum USART_TXCINTLVL_enum
+{
+ USART_TXCINTLVL_OFF_gc = (0x00<<2), /* Interrupt Disabled */
+ USART_TXCINTLVL_LO_gc = (0x01<<2), /* Low Level */
+ USART_TXCINTLVL_MED_gc = (0x02<<2), /* Medium Level */
+ USART_TXCINTLVL_HI_gc = (0x03<<2), /* High Level */
+} USART_TXCINTLVL_t;
+
+/* Data Register Empty Interrupt level */
+typedef enum USART_DREINTLVL_enum
+{
+ USART_DREINTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ USART_DREINTLVL_LO_gc = (0x01<<0), /* Low Level */
+ USART_DREINTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ USART_DREINTLVL_HI_gc = (0x03<<0), /* High Level */
+} USART_DREINTLVL_t;
+
+/* Character Size */
+typedef enum USART_CHSIZE_enum
+{
+ USART_CHSIZE_5BIT_gc = (0x00<<0), /* Character size: 5 bit */
+ USART_CHSIZE_6BIT_gc = (0x01<<0), /* Character size: 6 bit */
+ USART_CHSIZE_7BIT_gc = (0x02<<0), /* Character size: 7 bit */
+ USART_CHSIZE_8BIT_gc = (0x03<<0), /* Character size: 8 bit */
+ USART_CHSIZE_9BIT_gc = (0x07<<0), /* Character size: 9 bit */
+} USART_CHSIZE_t;
+
+/* Communication Mode */
+typedef enum USART_CMODE_enum
+{
+ USART_CMODE_ASYNCHRONOUS_gc = (0x00<<6), /* Asynchronous Mode */
+ USART_CMODE_SYNCHRONOUS_gc = (0x01<<6), /* Synchronous Mode */
+ USART_CMODE_IRDA_gc = (0x02<<6), /* IrDA Mode */
+ USART_CMODE_MSPI_gc = (0x03<<6), /* Master SPI Mode */
+} USART_CMODE_t;
+
+/* Parity Mode */
+typedef enum USART_PMODE_enum
+{
+ USART_PMODE_DISABLED_gc = (0x00<<4), /* No Parity */
+ USART_PMODE_EVEN_gc = (0x02<<4), /* Even Parity */
+ USART_PMODE_ODD_gc = (0x03<<4), /* Odd Parity */
+} USART_PMODE_t;
+
+
+/*
+--------------------------------------------------------------------------
+SPI - Serial Peripheral Interface
+--------------------------------------------------------------------------
+*/
+
+/* Serial Peripheral Interface */
+typedef struct SPI_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t INTCTRL; /* Interrupt Control Register */
+ register8_t STATUS; /* Status Register */
+ register8_t DATA; /* Data Register */
+} SPI_t;
+
+/* SPI Mode */
+typedef enum SPI_MODE_enum
+{
+ SPI_MODE_0_gc = (0x00<<2), /* SPI Mode 0 */
+ SPI_MODE_1_gc = (0x01<<2), /* SPI Mode 1 */
+ SPI_MODE_2_gc = (0x02<<2), /* SPI Mode 2 */
+ SPI_MODE_3_gc = (0x03<<2), /* SPI Mode 3 */
+} SPI_MODE_t;
+
+/* Prescaler setting */
+typedef enum SPI_PRESCALER_enum
+{
+ SPI_PRESCALER_DIV4_gc = (0x00<<0), /* System Clock / 4 */
+ SPI_PRESCALER_DIV16_gc = (0x01<<0), /* System Clock / 16 */
+ SPI_PRESCALER_DIV64_gc = (0x02<<0), /* System Clock / 64 */
+ SPI_PRESCALER_DIV128_gc = (0x03<<0), /* System Clock / 128 */
+} SPI_PRESCALER_t;
+
+/* Interrupt level */
+typedef enum SPI_INTLVL_enum
+{
+ SPI_INTLVL_OFF_gc = (0x00<<0), /* Interrupt Disabled */
+ SPI_INTLVL_LO_gc = (0x01<<0), /* Low Level */
+ SPI_INTLVL_MED_gc = (0x02<<0), /* Medium Level */
+ SPI_INTLVL_HI_gc = (0x03<<0), /* High Level */
+} SPI_INTLVL_t;
+
+
+/*
+--------------------------------------------------------------------------
+IRCOM - IR Communication Module
+--------------------------------------------------------------------------
+*/
+
+/* IR Communication Module */
+typedef struct IRCOM_struct
+{
+ register8_t CTRL; /* Control Register */
+ register8_t TXPLCTRL; /* IrDA Transmitter Pulse Length Control Register */
+ register8_t RXPLCTRL; /* IrDA Receiver Pulse Length Control Register */
+} IRCOM_t;
+
+/* Event channel selection */
+typedef enum IRDA_EVSEL_enum
+{
+ IRDA_EVSEL_OFF_gc = (0x00<<0), /* No Event Source */
+ IRDA_EVSEL_0_gc = (0x08<<0), /* Event Channel 0 */
+ IRDA_EVSEL_1_gc = (0x09<<0), /* Event Channel 1 */
+ IRDA_EVSEL_2_gc = (0x0A<<0), /* Event Channel 2 */
+ IRDA_EVSEL_3_gc = (0x0B<<0), /* Event Channel 3 */
+ IRDA_EVSEL_4_gc = (0x0C<<0), /* Event Channel 4 */
+ IRDA_EVSEL_5_gc = (0x0D<<0), /* Event Channel 5 */
+ IRDA_EVSEL_6_gc = (0x0E<<0), /* Event Channel 6 */
+ IRDA_EVSEL_7_gc = (0x0F<<0), /* Event Channel 7 */
+} IRDA_EVSEL_t;
+
+
+/*
+--------------------------------------------------------------------------
+PRESC - Prescaler
+--------------------------------------------------------------------------
+*/
+
+/* Prescaler */
+typedef struct PRESC_struct
+{
+ register8_t PRESCALER; /* Control Register */
+} PRESC_t;
+
+
+
+/*
+==========================================================================
+IO Module Instances. Mapped to memory.
+==========================================================================
+*/
+
+#define GPIO (*(GPIO_t *) 0x0000) /* General Purpose IO Registers */
+#define VPORT0 (*(VPORT_t *) 0x0010) /* Virtual Port 0 */
+#define VPORT1 (*(VPORT_t *) 0x0014) /* Virtual Port 1 */
+#define VPORT2 (*(VPORT_t *) 0x0018) /* Virtual Port 2 */
+#define VPORT3 (*(VPORT_t *) 0x001C) /* Virtual Port 3 */
+#define OCD (*(OCD_t *) 0x002E) /* On-Chip Debug System */
+#define CPU (*(CPU_t *) 0x0030) /* CPU Registers */
+#define CLK (*(CLK_t *) 0x0040) /* Clock System */
+#define SLEEP (*(SLEEP_t *) 0x0048) /* Sleep Controller */
+#define OSC (*(OSC_t *) 0x0050) /* Oscillator Control */
+#define DFLLRC32M (*(DFLL_t *) 0x0060) /* DFLL for 32MHz RC Oscillator */
+#define DFLLRC2M (*(DFLL_t *) 0x0068) /* DFLL for 2MHz RC Oscillator */
+#define PR (*(PR_t *) 0x0070) /* Power Reduction */
+#define RST (*(RST_t *) 0x0078) /* Reset Controller */
+#define WDT (*(WDT_t *) 0x0080) /* Watch-Dog Timer */
+#define MCU (*(MCU_t *) 0x0090) /* MCU Control */
+#define PMIC (*(PMIC_t *) 0x00A0) /* Programmable Interrupt Controller */
+#define PORTCFG (*(PORTCFG_t *) 0x00B0) /* Port Configuration */
+#define AES (*(AES_t *) 0x00C0) /* AES Crypto Module */
+#define CRC (*(CRC_t *) 0x00D0) /* CRC Module */
+#define DMA (*(DMA_t *) 0x0100) /* DMA Controller */
+#define EVSYS (*(EVSYS_t *) 0x0180) /* Event System */
+#define NVM (*(NVM_t *) 0x01C0) /* Non Volatile Memory Controller */
+#define ADCA (*(ADC_t *) 0x0200) /* Analog to Digital Converter A */
+#define ADCB (*(ADC_t *) 0x0240) /* Analog to Digital Converter B */
+#define DACA (*(DAC_t *) 0x0300) /* Digital to Analog Converter A */
+#define DACB (*(DAC_t *) 0x0320) /* Digital to Analog Converter B */
+#define ACA (*(AC_t *) 0x0380) /* Analog Comparator A */
+#define ACB (*(AC_t *) 0x0390) /* Analog Comparator B */
+#define RTC (*(RTC_t *) 0x0400) /* Real-Time Counter */
+#define EBI (*(EBI_t *) 0x0440) /* External Bus Interface */
+#define TWIC (*(TWI_t *) 0x0480) /* Two-Wire Interface C */
+#define TWID (*(TWI_t *) 0x0490) /* Two-Wire Interface D */
+#define TWIE (*(TWI_t *) 0x04A0) /* Two-Wire Interface E */
+#define TWIF (*(TWI_t *) 0x04B0) /* Two-Wire Interface F */
+#define USB (*(USB_t *) 0x04C0) /* Universal Serial Bus Module */
+#define PORTA (*(PORT_t *) 0x0600) /* Port A */
+#define PORTB (*(PORT_t *) 0x0620) /* Port B */
+#define PORTC (*(PORT_t *) 0x0640) /* Port C */
+#define PORTD (*(PORT_t *) 0x0660) /* Port D */
+#define PORTE (*(PORT_t *) 0x0680) /* Port E */
+#define PORTF (*(PORT_t *) 0x06A0) /* Port F */
+#define PORTH (*(PORT_t *) 0x06E0) /* Port H */
+#define PORTJ (*(PORT_t *) 0x0700) /* Port J */
+#define PORTK (*(PORT_t *) 0x0720) /* Port K */
+#define PORTQ (*(PORT_t *) 0x07C0) /* Port Q */
+#define PORTR (*(PORT_t *) 0x07E0) /* Port R */
+#define TCC0 (*(TC0_t *) 0x0800) /* Timer/Counter C0 */
+#define TCC1 (*(TC1_t *) 0x0840) /* Timer/Counter C1 */
+#define AWEXC (*(AWEX_t *) 0x0880) /* Advanced Waveform Extension C */
+#define HIRESC (*(HIRES_t *) 0x0890) /* High-Resolution Extension C */
+#define USARTC0 (*(USART_t *) 0x08A0) /* Universal Asynchronous
Receiver-Transmitter C0 */
+#define USARTC1 (*(USART_t *) 0x08B0) /* Universal Asynchronous
Receiver-Transmitter C1 */
+#define SPIC (*(SPI_t *) 0x08C0) /* Serial Peripheral Interface C */
+#define IRCOM (*(IRCOM_t *) 0x08F8) /* IR Communication Module */
+#define TCD0 (*(TC0_t *) 0x0900) /* Timer/Counter D0 */
+#define TCD1 (*(TC1_t *) 0x0940) /* Timer/Counter D1 */
+#define HIRESD (*(HIRES_t *) 0x0990) /* High-Resolution Extension D */
+#define USARTD0 (*(USART_t *) 0x09A0) /* Universal Asynchronous
Receiver-Transmitter D0 */
+#define USARTD1 (*(USART_t *) 0x09B0) /* Universal Asynchronous
Receiver-Transmitter D1 */
+#define SPID (*(SPI_t *) 0x09C0) /* Serial Peripheral Interface D */
+#define TCE0 (*(TC0_t *) 0x0A00) /* Timer/Counter E0 */
+#define TCE1 (*(TC1_t *) 0x0A40) /* Timer/Counter E1 */
+#define AWEXE (*(AWEX_t *) 0x0A80) /* Advanced Waveform Extension E */
+#define HIRESE (*(HIRES_t *) 0x0A90) /* High-Resolution Extension E */
+#define USARTE0 (*(USART_t *) 0x0AA0) /* Universal Asynchronous
Receiver-Transmitter E0 */
+#define USARTE1 (*(USART_t *) 0x0AB0) /* Universal Asynchronous
Receiver-Transmitter E1 */
+#define SPIE (*(SPI_t *) 0x0AC0) /* Serial Peripheral Interface E */
+#define TCF0 (*(TC0_t *) 0x0B00) /* Timer/Counter F0 */
+#define TCF1 (*(TC1_t *) 0x0B40) /* Timer/Counter F1 */
+#define HIRESF (*(HIRES_t *) 0x0B90) /* High-Resolution Extension F */
+#define USARTF0 (*(USART_t *) 0x0BA0) /* Universal Asynchronous
Receiver-Transmitter F0 */
+#define USARTF1 (*(USART_t *) 0x0BB0) /* Universal Asynchronous
Receiver-Transmitter F1 */
+#define SPIF (*(SPI_t *) 0x0BC0) /* Serial Peripheral Interface F */
+
+
+#endif /* !defined (__ASSEMBLER__) */
+
+
+/* ========== Flattened fully qualified IO register names ========== */
+
+/* GPIO - General Purpose IO Registers */
+#define GPIO_GPIOR0 _SFR_MEM8(0x0000)
+#define GPIO_GPIOR1 _SFR_MEM8(0x0001)
+#define GPIO_GPIOR2 _SFR_MEM8(0x0002)
+#define GPIO_GPIOR3 _SFR_MEM8(0x0003)
+#define GPIO_GPIOR4 _SFR_MEM8(0x0004)
+#define GPIO_GPIOR5 _SFR_MEM8(0x0005)
+#define GPIO_GPIOR6 _SFR_MEM8(0x0006)
+#define GPIO_GPIOR7 _SFR_MEM8(0x0007)
+#define GPIO_GPIOR8 _SFR_MEM8(0x0008)
+#define GPIO_GPIOR9 _SFR_MEM8(0x0009)
+#define GPIO_GPIORA _SFR_MEM8(0x000A)
+#define GPIO_GPIORB _SFR_MEM8(0x000B)
+#define GPIO_GPIORC _SFR_MEM8(0x000C)
+#define GPIO_GPIORD _SFR_MEM8(0x000D)
+#define GPIO_GPIORE _SFR_MEM8(0x000E)
+#define GPIO_GPIORF _SFR_MEM8(0x000F)
+
+/* VPORT0 - Virtual Port 0 */
+#define VPORT0_DIR _SFR_MEM8(0x0010)
+#define VPORT0_OUT _SFR_MEM8(0x0011)
+#define VPORT0_IN _SFR_MEM8(0x0012)
+#define VPORT0_INTFLAGS _SFR_MEM8(0x0013)
+
+/* VPORT1 - Virtual Port 1 */
+#define VPORT1_DIR _SFR_MEM8(0x0014)
+#define VPORT1_OUT _SFR_MEM8(0x0015)
+#define VPORT1_IN _SFR_MEM8(0x0016)
+#define VPORT1_INTFLAGS _SFR_MEM8(0x0017)
+
+/* VPORT2 - Virtual Port 2 */
+#define VPORT2_DIR _SFR_MEM8(0x0018)
+#define VPORT2_OUT _SFR_MEM8(0x0019)
+#define VPORT2_IN _SFR_MEM8(0x001A)
+#define VPORT2_INTFLAGS _SFR_MEM8(0x001B)
+
+/* VPORT3 - Virtual Port 3 */
+#define VPORT3_DIR _SFR_MEM8(0x001C)
+#define VPORT3_OUT _SFR_MEM8(0x001D)
+#define VPORT3_IN _SFR_MEM8(0x001E)
+#define VPORT3_INTFLAGS _SFR_MEM8(0x001F)
+
+/* OCD - On-Chip Debug System */
+#define OCD_OCDR0 _SFR_MEM8(0x002E)
+#define OCD_OCDR1 _SFR_MEM8(0x002F)
+
+/* CPU - CPU Registers */
+#define CPU_CCP _SFR_MEM8(0x0034)
+#define CPU_RAMPD _SFR_MEM8(0x0038)
+#define CPU_RAMPX _SFR_MEM8(0x0039)
+#define CPU_RAMPY _SFR_MEM8(0x003A)
+#define CPU_RAMPZ _SFR_MEM8(0x003B)
+#define CPU_EIND _SFR_MEM8(0x003C)
+#define CPU_SPL _SFR_MEM8(0x003D)
+#define CPU_SPH _SFR_MEM8(0x003E)
+#define CPU_SREG _SFR_MEM8(0x003F)
+
+/* CLK - Clock System */
+#define CLK_CTRL _SFR_MEM8(0x0040)
+#define CLK_PSCTRL _SFR_MEM8(0x0041)
+#define CLK_LOCK _SFR_MEM8(0x0042)
+#define CLK_RTCCTRL _SFR_MEM8(0x0043)
+#define CLK_USBCTRL _SFR_MEM8(0x0044)
+
+/* SLEEP - Sleep Controller */
+#define SLEEP_CTRL _SFR_MEM8(0x0048)
+
+/* OSC - Oscillator Control */
+#define OSC_CTRL _SFR_MEM8(0x0050)
+#define OSC_STATUS _SFR_MEM8(0x0051)
+#define OSC_XOSCCTRL _SFR_MEM8(0x0052)
+#define OSC_XOSCFAIL _SFR_MEM8(0x005F)
+#define OSC_RC32KCAL _SFR_MEM8(0x0054)
+#define OSC_PLLCTRL _SFR_MEM8(0x0055)
+#define OSC_DFLLCTRL _SFR_MEM8(0x0056)
+
+/* DFLLRC32M - DFLL for 32MHz RC Oscillator */
+#define DFLLRC32M_CTRL _SFR_MEM8(0x0060)
+#define DFLLRC32M_CALA _SFR_MEM8(0x0062)
+#define DFLLRC32M_CALB _SFR_MEM8(0x0063)
+#define DFLLRC32M_COMP0 _SFR_MEM8(0x0064)
+#define DFLLRC32M_COMP1 _SFR_MEM8(0x0065)
+#define DFLLRC32M_COMP2 _SFR_MEM8(0x0066)
+
+/* DFLLRC2M - DFLL for 2MHz RC Oscillator */
+#define DFLLRC2M_CTRL _SFR_MEM8(0x0068)
+#define DFLLRC2M_CALA _SFR_MEM8(0x006A)
+#define DFLLRC2M_CALB _SFR_MEM8(0x006B)
+#define DFLLRC2M_COMP0 _SFR_MEM8(0x006C)
+#define DFLLRC2M_COMP1 _SFR_MEM8(0x006D)
+#define DFLLRC2M_COMP2 _SFR_MEM8(0x006E)
+
+/* PR - Power Reduction */
+#define PR_PRGEN _SFR_MEM8(0x0070)
+#define PR_PRPA _SFR_MEM8(0x0071)
+#define PR_PRPB _SFR_MEM8(0x0072)
+#define PR_PRPC _SFR_MEM8(0x0073)
+#define PR_PRPD _SFR_MEM8(0x0074)
+#define PR_PRPE _SFR_MEM8(0x0075)
+#define PR_PRPF _SFR_MEM8(0x0076)
+
+/* RST - Reset Controller */
+#define RST_STATUS _SFR_MEM8(0x0078)
+#define RST_CTRL _SFR_MEM8(0x0079)
+
+/* WDT - Watch-Dog Timer */
+#define WDT_CTRL _SFR_MEM8(0x0080)
+#define WDT_WINCTRL _SFR_MEM8(0x0081)
+#define WDT_STATUS _SFR_MEM8(0x0082)
+
+/* MCU - MCU Control */
+#define MCU_DEVID0 _SFR_MEM8(0x0090)
+#define MCU_DEVID1 _SFR_MEM8(0x0091)
+#define MCU_DEVID2 _SFR_MEM8(0x0092)
+#define MCU_REVID _SFR_MEM8(0x0093)
+#define MCU_JTAGUID _SFR_MEM8(0x0094)
+#define MCU_MCUCR _SFR_MEM8(0x0096)
+#define MCU_ANAINIT _SFR_MEM8(0x0097)
+#define MCU_EVSYSLOCK _SFR_MEM8(0x0098)
+#define MCU_AWEXLOCK _SFR_MEM8(0x0099)
+
+/* PMIC - Programmable Interrupt Controller */
+#define PMIC_STATUS _SFR_MEM8(0x00A0)
+#define PMIC_INTPRI _SFR_MEM8(0x00A1)
+#define PMIC_CTRL _SFR_MEM8(0x00A2)
+
+/* PORTCFG - Port Configuration */
+#define PORTCFG_MPCMASK _SFR_MEM8(0x00B0)
+#define PORTCFG_VPCTRLA _SFR_MEM8(0x00B2)
+#define PORTCFG_VPCTRLB _SFR_MEM8(0x00B3)
+#define PORTCFG_CLKEVOUT _SFR_MEM8(0x00B4)
+
+/* AES - AES Crypto Module */
+#define AES_CTRL _SFR_MEM8(0x00C0)
+#define AES_STATUS _SFR_MEM8(0x00C1)
+#define AES_STATE _SFR_MEM8(0x00C2)
+#define AES_KEY _SFR_MEM8(0x00C3)
+#define AES_INTCTRL _SFR_MEM8(0x00C4)
+
+/* CRC - CRC Module */
+#define CRC_CTRL _SFR_MEM8(0x00D0)
+#define CRC_STATUS _SFR_MEM8(0x00D1)
+#define CRC_DATAIN _SFR_MEM8(0x00D3)
+#define CRC_CHECKSUM0 _SFR_MEM8(0x00D4)
+#define CRC_CHECKSUM1 _SFR_MEM8(0x00D5)
+#define CRC_CHECKSUM2 _SFR_MEM8(0x00D6)
+#define CRC_CHECKSUM3 _SFR_MEM8(0x00D7)
+
+/* DMA - DMA Controller */
+#define DMA_CTRL _SFR_MEM8(0x0100)
+#define DMA_INTFLAGS _SFR_MEM8(0x0103)
+#define DMA_STATUS _SFR_MEM8(0x0104)
+#define DMA_TEMP _SFR_MEM16(0x0106)
+#define DMA_CH0_CTRLA _SFR_MEM8(0x0110)
+#define DMA_CH0_CTRLB _SFR_MEM8(0x0111)
+#define DMA_CH0_ADDRCTRL _SFR_MEM8(0x0112)
+#define DMA_CH0_TRIGSRC _SFR_MEM8(0x0113)
+#define DMA_CH0_TRFCNT _SFR_MEM16(0x0114)
+#define DMA_CH0_REPCNT _SFR_MEM8(0x0116)
+#define DMA_CH0_SRCADDR0 _SFR_MEM8(0x0118)
+#define DMA_CH0_SRCADDR1 _SFR_MEM8(0x0119)
+#define DMA_CH0_SRCADDR2 _SFR_MEM8(0x011A)
+#define DMA_CH0_DESTADDR0 _SFR_MEM8(0x011C)
+#define DMA_CH0_DESTADDR1 _SFR_MEM8(0x011D)
+#define DMA_CH0_DESTADDR2 _SFR_MEM8(0x011E)
+#define DMA_CH1_CTRLA _SFR_MEM8(0x0120)
+#define DMA_CH1_CTRLB _SFR_MEM8(0x0121)
+#define DMA_CH1_ADDRCTRL _SFR_MEM8(0x0122)
+#define DMA_CH1_TRIGSRC _SFR_MEM8(0x0123)
+#define DMA_CH1_TRFCNT _SFR_MEM16(0x0124)
+#define DMA_CH1_REPCNT _SFR_MEM8(0x0126)
+#define DMA_CH1_SRCADDR0 _SFR_MEM8(0x0128)
+#define DMA_CH1_SRCADDR1 _SFR_MEM8(0x0129)
+#define DMA_CH1_SRCADDR2 _SFR_MEM8(0x012A)
+#define DMA_CH1_DESTADDR0 _SFR_MEM8(0x012C)
+#define DMA_CH1_DESTADDR1 _SFR_MEM8(0x012D)
+#define DMA_CH1_DESTADDR2 _SFR_MEM8(0x012E)
+#define DMA_CH2_CTRLA _SFR_MEM8(0x0130)
+#define DMA_CH2_CTRLB _SFR_MEM8(0x0131)
+#define DMA_CH2_ADDRCTRL _SFR_MEM8(0x0132)
+#define DMA_CH2_TRIGSRC _SFR_MEM8(0x0133)
+#define DMA_CH2_TRFCNT _SFR_MEM16(0x0134)
+#define DMA_CH2_REPCNT _SFR_MEM8(0x0136)
+#define DMA_CH2_SRCADDR0 _SFR_MEM8(0x0138)
+#define DMA_CH2_SRCADDR1 _SFR_MEM8(0x0139)
+#define DMA_CH2_SRCADDR2 _SFR_MEM8(0x013A)
+#define DMA_CH2_DESTADDR0 _SFR_MEM8(0x013C)
+#define DMA_CH2_DESTADDR1 _SFR_MEM8(0x013D)
+#define DMA_CH2_DESTADDR2 _SFR_MEM8(0x013E)
+#define DMA_CH3_CTRLA _SFR_MEM8(0x0140)
+#define DMA_CH3_CTRLB _SFR_MEM8(0x0141)
+#define DMA_CH3_ADDRCTRL _SFR_MEM8(0x0142)
+#define DMA_CH3_TRIGSRC _SFR_MEM8(0x0143)
+#define DMA_CH3_TRFCNT _SFR_MEM16(0x0144)
+#define DMA_CH3_REPCNT _SFR_MEM8(0x0146)
+#define DMA_CH3_SRCADDR0 _SFR_MEM8(0x0148)
+#define DMA_CH3_SRCADDR1 _SFR_MEM8(0x0149)
+#define DMA_CH3_SRCADDR2 _SFR_MEM8(0x014A)
+#define DMA_CH3_DESTADDR0 _SFR_MEM8(0x014C)
+#define DMA_CH3_DESTADDR1 _SFR_MEM8(0x014D)
+#define DMA_CH3_DESTADDR2 _SFR_MEM8(0x014E)
+
+/* EVSYS - Event System */
+#define EVSYS_CH0MUX _SFR_MEM8(0x0180)
+#define EVSYS_CH1MUX _SFR_MEM8(0x0181)
+#define EVSYS_CH2MUX _SFR_MEM8(0x0182)
+#define EVSYS_CH3MUX _SFR_MEM8(0x0183)
+#define EVSYS_CH4MUX _SFR_MEM8(0x0184)
+#define EVSYS_CH5MUX _SFR_MEM8(0x0185)
+#define EVSYS_CH6MUX _SFR_MEM8(0x0186)
+#define EVSYS_CH7MUX _SFR_MEM8(0x0187)
+#define EVSYS_CH0CTRL _SFR_MEM8(0x0188)
+#define EVSYS_CH1CTRL _SFR_MEM8(0x0189)
+#define EVSYS_CH2CTRL _SFR_MEM8(0x018A)
+#define EVSYS_CH3CTRL _SFR_MEM8(0x018B)
+#define EVSYS_CH4CTRL _SFR_MEM8(0x018C)
+#define EVSYS_CH5CTRL _SFR_MEM8(0x018D)
+#define EVSYS_CH6CTRL _SFR_MEM8(0x018E)
+#define EVSYS_CH7CTRL _SFR_MEM8(0x018F)
+#define EVSYS_STROBE _SFR_MEM8(0x0190)
+#define EVSYS_DATA _SFR_MEM8(0x0191)
+
+/* NVM - Non Volatile Memory Controller */
+#define NVM_ADDR0 _SFR_MEM8(0x01C0)
+#define NVM_ADDR1 _SFR_MEM8(0x01C1)
+#define NVM_ADDR2 _SFR_MEM8(0x01C2)
+#define NVM_DATA0 _SFR_MEM8(0x01C4)
+#define NVM_DATA1 _SFR_MEM8(0x01C5)
+#define NVM_DATA2 _SFR_MEM8(0x01C6)
+#define NVM_CMD _SFR_MEM8(0x01CA)
+#define NVM_CTRLA _SFR_MEM8(0x01CB)
+#define NVM_CTRLB _SFR_MEM8(0x01CC)
+#define NVM_INTCTRL _SFR_MEM8(0x01CD)
+#define NVM_STATUS _SFR_MEM8(0x01CF)
+#define NVM_LOCKBITS _SFR_MEM8(0x01D0)
+
+/* ADCA - Analog to Digital Converter A */
+#define ADCA_CTRLA _SFR_MEM8(0x0200)
+#define ADCA_CTRLB _SFR_MEM8(0x0201)
+#define ADCA_REFCTRL _SFR_MEM8(0x0202)
+#define ADCA_EVCTRL _SFR_MEM8(0x0203)
+#define ADCA_PRESCALER _SFR_MEM8(0x0204)
+#define ADCA_INTFLAGS _SFR_MEM8(0x0206)
+#define ADCA_TEMP _SFR_MEM8(0x0207)
+#define ADCA_CAL _SFR_MEM16(0x020C)
+#define ADCA_CH0RES _SFR_MEM16(0x0210)
+#define ADCA_CH1RES _SFR_MEM16(0x0212)
+#define ADCA_CH2RES _SFR_MEM16(0x0214)
+#define ADCA_CH3RES _SFR_MEM16(0x0216)
+#define ADCA_CMP _SFR_MEM16(0x0218)
+#define ADCA_CH0_CTRL _SFR_MEM8(0x0220)
+#define ADCA_CH0_MUXCTRL _SFR_MEM8(0x0221)
+#define ADCA_CH0_INTCTRL _SFR_MEM8(0x0222)
+#define ADCA_CH0_INTFLAGS _SFR_MEM8(0x0223)
+#define ADCA_CH0_RES _SFR_MEM16(0x0224)
+#define ADCA_CH1_CTRL _SFR_MEM8(0x0228)
+#define ADCA_CH1_MUXCTRL _SFR_MEM8(0x0229)
+#define ADCA_CH1_INTCTRL _SFR_MEM8(0x022A)
+#define ADCA_CH1_INTFLAGS _SFR_MEM8(0x022B)
+#define ADCA_CH1_RES _SFR_MEM16(0x022C)
+#define ADCA_CH2_CTRL _SFR_MEM8(0x0230)
+#define ADCA_CH2_MUXCTRL _SFR_MEM8(0x0231)
+#define ADCA_CH2_INTCTRL _SFR_MEM8(0x0232)
+#define ADCA_CH2_INTFLAGS _SFR_MEM8(0x0233)
+#define ADCA_CH2_RES _SFR_MEM16(0x0234)
+#define ADCA_CH3_CTRL _SFR_MEM8(0x0238)
+#define ADCA_CH3_MUXCTRL _SFR_MEM8(0x0239)
+#define ADCA_CH3_INTCTRL _SFR_MEM8(0x023A)
+#define ADCA_CH3_INTFLAGS _SFR_MEM8(0x023B)
+#define ADCA_CH3_RES _SFR_MEM16(0x023C)
+
+/* ADCB - Analog to Digital Converter B */
+#define ADCB_CTRLA _SFR_MEM8(0x0240)
+#define ADCB_CTRLB _SFR_MEM8(0x0241)
+#define ADCB_REFCTRL _SFR_MEM8(0x0242)
+#define ADCB_EVCTRL _SFR_MEM8(0x0243)
+#define ADCB_PRESCALER _SFR_MEM8(0x0244)
+#define ADCB_INTFLAGS _SFR_MEM8(0x0246)
+#define ADCB_TEMP _SFR_MEM8(0x0247)
+#define ADCB_CAL _SFR_MEM16(0x024C)
+#define ADCB_CH0RES _SFR_MEM16(0x0250)
+#define ADCB_CH1RES _SFR_MEM16(0x0252)
+#define ADCB_CH2RES _SFR_MEM16(0x0254)
+#define ADCB_CH3RES _SFR_MEM16(0x0256)
+#define ADCB_CMP _SFR_MEM16(0x0258)
+#define ADCB_CH0_CTRL _SFR_MEM8(0x0260)
+#define ADCB_CH0_MUXCTRL _SFR_MEM8(0x0261)
+#define ADCB_CH0_INTCTRL _SFR_MEM8(0x0262)
+#define ADCB_CH0_INTFLAGS _SFR_MEM8(0x0263)
+#define ADCB_CH0_RES _SFR_MEM16(0x0264)
+#define ADCB_CH1_CTRL _SFR_MEM8(0x0268)
+#define ADCB_CH1_MUXCTRL _SFR_MEM8(0x0269)
+#define ADCB_CH1_INTCTRL _SFR_MEM8(0x026A)
+#define ADCB_CH1_INTFLAGS _SFR_MEM8(0x026B)
+#define ADCB_CH1_RES _SFR_MEM16(0x026C)
+#define ADCB_CH2_CTRL _SFR_MEM8(0x0270)
+#define ADCB_CH2_MUXCTRL _SFR_MEM8(0x0271)
+#define ADCB_CH2_INTCTRL _SFR_MEM8(0x0272)
+#define ADCB_CH2_INTFLAGS _SFR_MEM8(0x0273)
+#define ADCB_CH2_RES _SFR_MEM16(0x0274)
+#define ADCB_CH3_CTRL _SFR_MEM8(0x0278)
+#define ADCB_CH3_MUXCTRL _SFR_MEM8(0x0279)
+#define ADCB_CH3_INTCTRL _SFR_MEM8(0x027A)
+#define ADCB_CH3_INTFLAGS _SFR_MEM8(0x027B)
+#define ADCB_CH3_RES _SFR_MEM16(0x027C)
+
+/* DACA - Digital to Analog Converter A */
+#define DACA_CTRLA _SFR_MEM8(0x0300)
+#define DACA_CTRLB _SFR_MEM8(0x0301)
+#define DACA_CTRLC _SFR_MEM8(0x0302)
+#define DACA_EVCTRL _SFR_MEM8(0x0303)
+#define DACA_TIMCTRL _SFR_MEM8(0x0304)
+#define DACA_STATUS _SFR_MEM8(0x0305)
+#define DACA_CH0GAINCAL _SFR_MEM8(0x0308)
+#define DACA_CH0OFFSETCAL _SFR_MEM8(0x0309)
+#define DACA_CH1GAINCAL _SFR_MEM8(0x030A)
+#define DACA_CH1OFFSETCAL _SFR_MEM8(0x030B)
+#define DACA_CH0DATA _SFR_MEM16(0x0318)
+#define DACA_CH1DATA _SFR_MEM16(0x031A)
+
+/* DACB - Digital to Analog Converter B */
+#define DACB_CTRLA _SFR_MEM8(0x0320)
+#define DACB_CTRLB _SFR_MEM8(0x0321)
+#define DACB_CTRLC _SFR_MEM8(0x0322)
+#define DACB_EVCTRL _SFR_MEM8(0x0323)
+#define DACB_TIMCTRL _SFR_MEM8(0x0324)
+#define DACB_STATUS _SFR_MEM8(0x0325)
+#define DACB_CH0GAINCAL _SFR_MEM8(0x0328)
+#define DACB_CH0OFFSETCAL _SFR_MEM8(0x0329)
+#define DACB_CH1GAINCAL _SFR_MEM8(0x032A)
+#define DACB_CH1OFFSETCAL _SFR_MEM8(0x032B)
+#define DACB_CH0DATA _SFR_MEM16(0x0338)
+#define DACB_CH1DATA _SFR_MEM16(0x033A)
+
+/* ACA - Analog Comparator A */
+#define ACA_AC0CTRL _SFR_MEM8(0x0380)
+#define ACA_AC1CTRL _SFR_MEM8(0x0381)
+#define ACA_AC0MUXCTRL _SFR_MEM8(0x0382)
+#define ACA_AC1MUXCTRL _SFR_MEM8(0x0383)
+#define ACA_CTRLA _SFR_MEM8(0x0384)
+#define ACA_CTRLB _SFR_MEM8(0x0385)
+#define ACA_WINCTRL _SFR_MEM8(0x0386)
+#define ACA_STATUS _SFR_MEM8(0x0387)
+
+/* ACB - Analog Comparator B */
+#define ACB_AC0CTRL _SFR_MEM8(0x0390)
+#define ACB_AC1CTRL _SFR_MEM8(0x0391)
+#define ACB_AC0MUXCTRL _SFR_MEM8(0x0392)
+#define ACB_AC1MUXCTRL _SFR_MEM8(0x0393)
+#define ACB_CTRLA _SFR_MEM8(0x0394)
+#define ACB_CTRLB _SFR_MEM8(0x0395)
+#define ACB_WINCTRL _SFR_MEM8(0x0396)
+#define ACB_STATUS _SFR_MEM8(0x0397)
+
+/* RTC - Real-Time Counter */
+#define RTC_CTRL _SFR_MEM8(0x0400)
+#define RTC_STATUS _SFR_MEM8(0x0401)
+#define RTC_INTCTRL _SFR_MEM8(0x0402)
+#define RTC_INTFLAGS _SFR_MEM8(0x0403)
+#define RTC_TEMP _SFR_MEM8(0x0404)
+#define RTC_CNT _SFR_MEM16(0x0408)
+#define RTC_PER _SFR_MEM16(0x040A)
+#define RTC_COMP _SFR_MEM16(0x040C)
+
+/* EBI - External Bus Interface */
+#define EBI_CTRL _SFR_MEM8(0x0440)
+#define EBI_SDRAMCTRLA _SFR_MEM8(0x0441)
+#define EBI_REFRESH _SFR_MEM16(0x0444)
+#define EBI_INITDLY _SFR_MEM16(0x0446)
+#define EBI_SDRAMCTRLB _SFR_MEM8(0x0448)
+#define EBI_SDRAMCTRLC _SFR_MEM8(0x0449)
+#define EBI_CS0_CTRLA _SFR_MEM8(0x0450)
+#define EBI_CS0_CTRLB _SFR_MEM8(0x0451)
+#define EBI_CS0_BASEADDR _SFR_MEM16(0x0452)
+#define EBI_CS1_CTRLA _SFR_MEM8(0x0454)
+#define EBI_CS1_CTRLB _SFR_MEM8(0x0455)
+#define EBI_CS1_BASEADDR _SFR_MEM16(0x0456)
+#define EBI_CS2_CTRLA _SFR_MEM8(0x0458)
+#define EBI_CS2_CTRLB _SFR_MEM8(0x0459)
+#define EBI_CS2_BASEADDR _SFR_MEM16(0x045A)
+#define EBI_CS3_CTRLA _SFR_MEM8(0x045C)
+#define EBI_CS3_CTRLB _SFR_MEM8(0x045D)
+#define EBI_CS3_BASEADDR _SFR_MEM16(0x045E)
+
+/* TWIC - Two-Wire Interface C */
+#define TWIC_CTRL _SFR_MEM8(0x0480)
+#define TWIC_MASTER_CTRLA _SFR_MEM8(0x0481)
+#define TWIC_MASTER_CTRLB _SFR_MEM8(0x0482)
+#define TWIC_MASTER_CTRLC _SFR_MEM8(0x0483)
+#define TWIC_MASTER_STATUS _SFR_MEM8(0x0484)
+#define TWIC_MASTER_BAUD _SFR_MEM8(0x0485)
+#define TWIC_MASTER_ADDR _SFR_MEM8(0x0486)
+#define TWIC_MASTER_DATA _SFR_MEM8(0x0487)
+#define TWIC_SLAVE_CTRLA _SFR_MEM8(0x0488)
+#define TWIC_SLAVE_CTRLB _SFR_MEM8(0x0489)
+#define TWIC_SLAVE_STATUS _SFR_MEM8(0x048A)
+#define TWIC_SLAVE_ADDR _SFR_MEM8(0x048B)
+#define TWIC_SLAVE_DATA _SFR_MEM8(0x048C)
+#define TWIC_SLAVE_ADDRMASK _SFR_MEM8(0x048D)
+
+/* TWID - Two-Wire Interface D */
+#define TWID_CTRL _SFR_MEM8(0x0490)
+#define TWID_MASTER_CTRLA _SFR_MEM8(0x0491)
+#define TWID_MASTER_CTRLB _SFR_MEM8(0x0492)
+#define TWID_MASTER_CTRLC _SFR_MEM8(0x0493)
+#define TWID_MASTER_STATUS _SFR_MEM8(0x0494)
+#define TWID_MASTER_BAUD _SFR_MEM8(0x0495)
+#define TWID_MASTER_ADDR _SFR_MEM8(0x0496)
+#define TWID_MASTER_DATA _SFR_MEM8(0x0497)
+#define TWID_SLAVE_CTRLA _SFR_MEM8(0x0498)
+#define TWID_SLAVE_CTRLB _SFR_MEM8(0x0499)
+#define TWID_SLAVE_STATUS _SFR_MEM8(0x049A)
+#define TWID_SLAVE_ADDR _SFR_MEM8(0x049B)
+#define TWID_SLAVE_DATA _SFR_MEM8(0x049C)
+#define TWID_SLAVE_ADDRMASK _SFR_MEM8(0x049D)
+
+/* TWIE - Two-Wire Interface E */
+#define TWIE_CTRL _SFR_MEM8(0x04A0)
+#define TWIE_MASTER_CTRLA _SFR_MEM8(0x04A1)
+#define TWIE_MASTER_CTRLB _SFR_MEM8(0x04A2)
+#define TWIE_MASTER_CTRLC _SFR_MEM8(0x04A3)
+#define TWIE_MASTER_STATUS _SFR_MEM8(0x04A4)
+#define TWIE_MASTER_BAUD _SFR_MEM8(0x04A5)
+#define TWIE_MASTER_ADDR _SFR_MEM8(0x04A6)
+#define TWIE_MASTER_DATA _SFR_MEM8(0x04A7)
+#define TWIE_SLAVE_CTRLA _SFR_MEM8(0x04A8)
+#define TWIE_SLAVE_CTRLB _SFR_MEM8(0x04A9)
+#define TWIE_SLAVE_STATUS _SFR_MEM8(0x04AA)
+#define TWIE_SLAVE_ADDR _SFR_MEM8(0x04AB)
+#define TWIE_SLAVE_DATA _SFR_MEM8(0x04AC)
+#define TWIE_SLAVE_ADDRMASK _SFR_MEM8(0x04AD)
+
+/* TWIF - Two-Wire Interface F */
+#define TWIF_CTRL _SFR_MEM8(0x04B0)
+#define TWIF_MASTER_CTRLA _SFR_MEM8(0x04B1)
+#define TWIF_MASTER_CTRLB _SFR_MEM8(0x04B2)
+#define TWIF_MASTER_CTRLC _SFR_MEM8(0x04B3)
+#define TWIF_MASTER_STATUS _SFR_MEM8(0x04B4)
+#define TWIF_MASTER_BAUD _SFR_MEM8(0x04B5)
+#define TWIF_MASTER_ADDR _SFR_MEM8(0x04B6)
+#define TWIF_MASTER_DATA _SFR_MEM8(0x04B7)
+#define TWIF_SLAVE_CTRLA _SFR_MEM8(0x04B8)
+#define TWIF_SLAVE_CTRLB _SFR_MEM8(0x04B9)
+#define TWIF_SLAVE_STATUS _SFR_MEM8(0x04BA)
+#define TWIF_SLAVE_ADDR _SFR_MEM8(0x04BB)
+#define TWIF_SLAVE_DATA _SFR_MEM8(0x04BC)
+#define TWIF_SLAVE_ADDRMASK _SFR_MEM8(0x04BD)
+
+/* USB - Universal Serial Bus Module */
+#define USB_CTRLA _SFR_MEM8(0x04C0)
+#define USB_CTRLB _SFR_MEM8(0x04C1)
+#define USB_STATUS _SFR_MEM8(0x04C2)
+#define USB_ADDR _SFR_MEM8(0x04C3)
+#define USB_FIFOWP _SFR_MEM8(0x04C4)
+#define USB_FIFORP _SFR_MEM8(0x04C5)
+#define USB_EPPTR _SFR_MEM16(0x04C6)
+#define USB_INTCTRLA _SFR_MEM8(0x04C8)
+#define USB_INTCTRLB _SFR_MEM8(0x04C9)
+#define USB_INTFLAGSACLR _SFR_MEM8(0x04CA)
+#define USB_INTFLAGSASET _SFR_MEM8(0x04CB)
+#define USB_INTFLAGSBCLR _SFR_MEM8(0x04CC)
+#define USB_INTFLAGSBSET _SFR_MEM8(0x04CD)
+#define USB_CAL0 _SFR_MEM8(0x04FA)
+#define USB_CAL1 _SFR_MEM8(0x04FB)
+
+/* PORTA - Port A */
+#define PORTA_DIR _SFR_MEM8(0x0600)
+#define PORTA_DIRSET _SFR_MEM8(0x0601)
+#define PORTA_DIRCLR _SFR_MEM8(0x0602)
+#define PORTA_DIRTGL _SFR_MEM8(0x0603)
+#define PORTA_OUT _SFR_MEM8(0x0604)
+#define PORTA_OUTSET _SFR_MEM8(0x0605)
+#define PORTA_OUTCLR _SFR_MEM8(0x0606)
+#define PORTA_OUTTGL _SFR_MEM8(0x0607)
+#define PORTA_IN _SFR_MEM8(0x0608)
+#define PORTA_INTCTRL _SFR_MEM8(0x0609)
+#define PORTA_INT0MASK _SFR_MEM8(0x060A)
+#define PORTA_INT1MASK _SFR_MEM8(0x060B)
+#define PORTA_INTFLAGS _SFR_MEM8(0x060C)
+#define PORTA_PIN0CTRL _SFR_MEM8(0x0610)
+#define PORTA_PIN1CTRL _SFR_MEM8(0x0611)
+#define PORTA_PIN2CTRL _SFR_MEM8(0x0612)
+#define PORTA_PIN3CTRL _SFR_MEM8(0x0613)
+#define PORTA_PIN4CTRL _SFR_MEM8(0x0614)
+#define PORTA_PIN5CTRL _SFR_MEM8(0x0615)
+#define PORTA_PIN6CTRL _SFR_MEM8(0x0616)
+#define PORTA_PIN7CTRL _SFR_MEM8(0x0617)
+
+/* PORTB - Port B */
+#define PORTB_DIR _SFR_MEM8(0x0620)
+#define PORTB_DIRSET _SFR_MEM8(0x0621)
+#define PORTB_DIRCLR _SFR_MEM8(0x0622)
+#define PORTB_DIRTGL _SFR_MEM8(0x0623)
+#define PORTB_OUT _SFR_MEM8(0x0624)
+#define PORTB_OUTSET _SFR_MEM8(0x0625)
+#define PORTB_OUTCLR _SFR_MEM8(0x0626)
+#define PORTB_OUTTGL _SFR_MEM8(0x0627)
+#define PORTB_IN _SFR_MEM8(0x0628)
+#define PORTB_INTCTRL _SFR_MEM8(0x0629)
+#define PORTB_INT0MASK _SFR_MEM8(0x062A)
+#define PORTB_INT1MASK _SFR_MEM8(0x062B)
+#define PORTB_INTFLAGS _SFR_MEM8(0x062C)
+#define PORTB_PIN0CTRL _SFR_MEM8(0x0630)
+#define PORTB_PIN1CTRL _SFR_MEM8(0x0631)
+#define PORTB_PIN2CTRL _SFR_MEM8(0x0632)
+#define PORTB_PIN3CTRL _SFR_MEM8(0x0633)
+#define PORTB_PIN4CTRL _SFR_MEM8(0x0634)
+#define PORTB_PIN5CTRL _SFR_MEM8(0x0635)
+#define PORTB_PIN6CTRL _SFR_MEM8(0x0636)
+#define PORTB_PIN7CTRL _SFR_MEM8(0x0637)
+
+/* PORTC - Port C */
+#define PORTC_DIR _SFR_MEM8(0x0640)
+#define PORTC_DIRSET _SFR_MEM8(0x0641)
+#define PORTC_DIRCLR _SFR_MEM8(0x0642)
+#define PORTC_DIRTGL _SFR_MEM8(0x0643)
+#define PORTC_OUT _SFR_MEM8(0x0644)
+#define PORTC_OUTSET _SFR_MEM8(0x0645)
+#define PORTC_OUTCLR _SFR_MEM8(0x0646)
+#define PORTC_OUTTGL _SFR_MEM8(0x0647)
+#define PORTC_IN _SFR_MEM8(0x0648)
+#define PORTC_INTCTRL _SFR_MEM8(0x0649)
+#define PORTC_INT0MASK _SFR_MEM8(0x064A)
+#define PORTC_INT1MASK _SFR_MEM8(0x064B)
+#define PORTC_INTFLAGS _SFR_MEM8(0x064C)
+#define PORTC_PIN0CTRL _SFR_MEM8(0x0650)
+#define PORTC_PIN1CTRL _SFR_MEM8(0x0651)
+#define PORTC_PIN2CTRL _SFR_MEM8(0x0652)
+#define PORTC_PIN3CTRL _SFR_MEM8(0x0653)
+#define PORTC_PIN4CTRL _SFR_MEM8(0x0654)
+#define PORTC_PIN5CTRL _SFR_MEM8(0x0655)
+#define PORTC_PIN6CTRL _SFR_MEM8(0x0656)
+#define PORTC_PIN7CTRL _SFR_MEM8(0x0657)
+
+/* PORTD - Port D */
+#define PORTD_DIR _SFR_MEM8(0x0660)
+#define PORTD_DIRSET _SFR_MEM8(0x0661)
+#define PORTD_DIRCLR _SFR_MEM8(0x0662)
+#define PORTD_DIRTGL _SFR_MEM8(0x0663)
+#define PORTD_OUT _SFR_MEM8(0x0664)
+#define PORTD_OUTSET _SFR_MEM8(0x0665)
+#define PORTD_OUTCLR _SFR_MEM8(0x0666)
+#define PORTD_OUTTGL _SFR_MEM8(0x0667)
+#define PORTD_IN _SFR_MEM8(0x0668)
+#define PORTD_INTCTRL _SFR_MEM8(0x0669)
+#define PORTD_INT0MASK _SFR_MEM8(0x066A)
+#define PORTD_INT1MASK _SFR_MEM8(0x066B)
+#define PORTD_INTFLAGS _SFR_MEM8(0x066C)
+#define PORTD_PIN0CTRL _SFR_MEM8(0x0670)
+#define PORTD_PIN1CTRL _SFR_MEM8(0x0671)
+#define PORTD_PIN2CTRL _SFR_MEM8(0x0672)
+#define PORTD_PIN3CTRL _SFR_MEM8(0x0673)
+#define PORTD_PIN4CTRL _SFR_MEM8(0x0674)
+#define PORTD_PIN5CTRL _SFR_MEM8(0x0675)
+#define PORTD_PIN6CTRL _SFR_MEM8(0x0676)
+#define PORTD_PIN7CTRL _SFR_MEM8(0x0677)
+
+/* PORTE - Port E */
+#define PORTE_DIR _SFR_MEM8(0x0680)
+#define PORTE_DIRSET _SFR_MEM8(0x0681)
+#define PORTE_DIRCLR _SFR_MEM8(0x0682)
+#define PORTE_DIRTGL _SFR_MEM8(0x0683)
+#define PORTE_OUT _SFR_MEM8(0x0684)
+#define PORTE_OUTSET _SFR_MEM8(0x0685)
+#define PORTE_OUTCLR _SFR_MEM8(0x0686)
+#define PORTE_OUTTGL _SFR_MEM8(0x0687)
+#define PORTE_IN _SFR_MEM8(0x0688)
+#define PORTE_INTCTRL _SFR_MEM8(0x0689)
+#define PORTE_INT0MASK _SFR_MEM8(0x068A)
+#define PORTE_INT1MASK _SFR_MEM8(0x068B)
+#define PORTE_INTFLAGS _SFR_MEM8(0x068C)
+#define PORTE_PIN0CTRL _SFR_MEM8(0x0690)
+#define PORTE_PIN1CTRL _SFR_MEM8(0x0691)
+#define PORTE_PIN2CTRL _SFR_MEM8(0x0692)
+#define PORTE_PIN3CTRL _SFR_MEM8(0x0693)
+#define PORTE_PIN4CTRL _SFR_MEM8(0x0694)
+#define PORTE_PIN5CTRL _SFR_MEM8(0x0695)
+#define PORTE_PIN6CTRL _SFR_MEM8(0x0696)
+#define PORTE_PIN7CTRL _SFR_MEM8(0x0697)
+
+/* PORTF - Port F */
+#define PORTF_DIR _SFR_MEM8(0x06A0)
+#define PORTF_DIRSET _SFR_MEM8(0x06A1)
+#define PORTF_DIRCLR _SFR_MEM8(0x06A2)
+#define PORTF_DIRTGL _SFR_MEM8(0x06A3)
+#define PORTF_OUT _SFR_MEM8(0x06A4)
+#define PORTF_OUTSET _SFR_MEM8(0x06A5)
+#define PORTF_OUTCLR _SFR_MEM8(0x06A6)
+#define PORTF_OUTTGL _SFR_MEM8(0x06A7)
+#define PORTF_IN _SFR_MEM8(0x06A8)
+#define PORTF_INTCTRL _SFR_MEM8(0x06A9)
+#define PORTF_INT0MASK _SFR_MEM8(0x06AA)
+#define PORTF_INT1MASK _SFR_MEM8(0x06AB)
+#define PORTF_INTFLAGS _SFR_MEM8(0x06AC)
+#define PORTF_PIN0CTRL _SFR_MEM8(0x06B0)
+#define PORTF_PIN1CTRL _SFR_MEM8(0x06B1)
+#define PORTF_PIN2CTRL _SFR_MEM8(0x06B2)
+#define PORTF_PIN3CTRL _SFR_MEM8(0x06B3)
+#define PORTF_PIN4CTRL _SFR_MEM8(0x06B4)
+#define PORTF_PIN5CTRL _SFR_MEM8(0x06B5)
+#define PORTF_PIN6CTRL _SFR_MEM8(0x06B6)
+#define PORTF_PIN7CTRL _SFR_MEM8(0x06B7)
+
+/* PORTH - Port H */
+#define PORTH_DIR _SFR_MEM8(0x06E0)
+#define PORTH_DIRSET _SFR_MEM8(0x06E1)
+#define PORTH_DIRCLR _SFR_MEM8(0x06E2)
+#define PORTH_DIRTGL _SFR_MEM8(0x06E3)
+#define PORTH_OUT _SFR_MEM8(0x06E4)
+#define PORTH_OUTSET _SFR_MEM8(0x06E5)
+#define PORTH_OUTCLR _SFR_MEM8(0x06E6)
+#define PORTH_OUTTGL _SFR_MEM8(0x06E7)
+#define PORTH_IN _SFR_MEM8(0x06E8)
+#define PORTH_INTCTRL _SFR_MEM8(0x06E9)
+#define PORTH_INT0MASK _SFR_MEM8(0x06EA)
+#define PORTH_INT1MASK _SFR_MEM8(0x06EB)
+#define PORTH_INTFLAGS _SFR_MEM8(0x06EC)
+#define PORTH_PIN0CTRL _SFR_MEM8(0x06F0)
+#define PORTH_PIN1CTRL _SFR_MEM8(0x06F1)
+#define PORTH_PIN2CTRL _SFR_MEM8(0x06F2)
+#define PORTH_PIN3CTRL _SFR_MEM8(0x06F3)
+#define PORTH_PIN4CTRL _SFR_MEM8(0x06F4)
+#define PORTH_PIN5CTRL _SFR_MEM8(0x06F5)
+#define PORTH_PIN6CTRL _SFR_MEM8(0x06F6)
+#define PORTH_PIN7CTRL _SFR_MEM8(0x06F7)
+
+/* PORTJ - Port J */
+#define PORTJ_DIR _SFR_MEM8(0x0700)
+#define PORTJ_DIRSET _SFR_MEM8(0x0701)
+#define PORTJ_DIRCLR _SFR_MEM8(0x0702)
+#define PORTJ_DIRTGL _SFR_MEM8(0x0703)
+#define PORTJ_OUT _SFR_MEM8(0x0704)
+#define PORTJ_OUTSET _SFR_MEM8(0x0705)
+#define PORTJ_OUTCLR _SFR_MEM8(0x0706)
+#define PORTJ_OUTTGL _SFR_MEM8(0x0707)
+#define PORTJ_IN _SFR_MEM8(0x0708)
+#define PORTJ_INTCTRL _SFR_MEM8(0x0709)
+#define PORTJ_INT0MASK _SFR_MEM8(0x070A)
+#define PORTJ_INT1MASK _SFR_MEM8(0x070B)
+#define PORTJ_INTFLAGS _SFR_MEM8(0x070C)
+#define PORTJ_PIN0CTRL _SFR_MEM8(0x0710)
+#define PORTJ_PIN1CTRL _SFR_MEM8(0x0711)
+#define PORTJ_PIN2CTRL _SFR_MEM8(0x0712)
+#define PORTJ_PIN3CTRL _SFR_MEM8(0x0713)
+#define PORTJ_PIN4CTRL _SFR_MEM8(0x0714)
+#define PORTJ_PIN5CTRL _SFR_MEM8(0x0715)
+#define PORTJ_PIN6CTRL _SFR_MEM8(0x0716)
+#define PORTJ_PIN7CTRL _SFR_MEM8(0x0717)
+
+/* PORTK - Port K */
+#define PORTK_DIR _SFR_MEM8(0x0720)
+#define PORTK_DIRSET _SFR_MEM8(0x0721)
+#define PORTK_DIRCLR _SFR_MEM8(0x0722)
+#define PORTK_DIRTGL _SFR_MEM8(0x0723)
+#define PORTK_OUT _SFR_MEM8(0x0724)
+#define PORTK_OUTSET _SFR_MEM8(0x0725)
+#define PORTK_OUTCLR _SFR_MEM8(0x0726)
+#define PORTK_OUTTGL _SFR_MEM8(0x0727)
+#define PORTK_IN _SFR_MEM8(0x0728)
+#define PORTK_INTCTRL _SFR_MEM8(0x0729)
+#define PORTK_INT0MASK _SFR_MEM8(0x072A)
+#define PORTK_INT1MASK _SFR_MEM8(0x072B)
+#define PORTK_INTFLAGS _SFR_MEM8(0x072C)
+#define PORTK_PIN0CTRL _SFR_MEM8(0x0730)
+#define PORTK_PIN1CTRL _SFR_MEM8(0x0731)
+#define PORTK_PIN2CTRL _SFR_MEM8(0x0732)
+#define PORTK_PIN3CTRL _SFR_MEM8(0x0733)
+#define PORTK_PIN4CTRL _SFR_MEM8(0x0734)
+#define PORTK_PIN5CTRL _SFR_MEM8(0x0735)
+#define PORTK_PIN6CTRL _SFR_MEM8(0x0736)
+#define PORTK_PIN7CTRL _SFR_MEM8(0x0737)
+
+/* PORTQ - Port Q */
+#define PORTQ_DIR _SFR_MEM8(0x07C0)
+#define PORTQ_DIRSET _SFR_MEM8(0x07C1)
+#define PORTQ_DIRCLR _SFR_MEM8(0x07C2)
+#define PORTQ_DIRTGL _SFR_MEM8(0x07C3)
+#define PORTQ_OUT _SFR_MEM8(0x07C4)
+#define PORTQ_OUTSET _SFR_MEM8(0x07C5)
+#define PORTQ_OUTCLR _SFR_MEM8(0x07C6)
+#define PORTQ_OUTTGL _SFR_MEM8(0x07C7)
+#define PORTQ_IN _SFR_MEM8(0x07C8)
+#define PORTQ_INTCTRL _SFR_MEM8(0x07C9)
+#define PORTQ_INT0MASK _SFR_MEM8(0x07CA)
+#define PORTQ_INT1MASK _SFR_MEM8(0x07CB)
+#define PORTQ_INTFLAGS _SFR_MEM8(0x07CC)
+#define PORTQ_PIN0CTRL _SFR_MEM8(0x07D0)
+#define PORTQ_PIN1CTRL _SFR_MEM8(0x07D1)
+#define PORTQ_PIN2CTRL _SFR_MEM8(0x07D2)
+#define PORTQ_PIN3CTRL _SFR_MEM8(0x07D3)
+#define PORTQ_PIN4CTRL _SFR_MEM8(0x07D4)
+#define PORTQ_PIN5CTRL _SFR_MEM8(0x07D5)
+#define PORTQ_PIN6CTRL _SFR_MEM8(0x07D6)
+#define PORTQ_PIN7CTRL _SFR_MEM8(0x07D7)
+
+/* PORTR - Port R */
+#define PORTR_DIR _SFR_MEM8(0x07E0)
+#define PORTR_DIRSET _SFR_MEM8(0x07E1)
+#define PORTR_DIRCLR _SFR_MEM8(0x07E2)
+#define PORTR_DIRTGL _SFR_MEM8(0x07E3)
+#define PORTR_OUT _SFR_MEM8(0x07E4)
+#define PORTR_OUTSET _SFR_MEM8(0x07E5)
+#define PORTR_OUTCLR _SFR_MEM8(0x07E6)
+#define PORTR_OUTTGL _SFR_MEM8(0x07E7)
+#define PORTR_IN _SFR_MEM8(0x07E8)
+#define PORTR_INTCTRL _SFR_MEM8(0x07E9)
+#define PORTR_INT0MASK _SFR_MEM8(0x07EA)
+#define PORTR_INT1MASK _SFR_MEM8(0x07EB)
+#define PORTR_INTFLAGS _SFR_MEM8(0x07EC)
+#define PORTR_PIN0CTRL _SFR_MEM8(0x07F0)
+#define PORTR_PIN1CTRL _SFR_MEM8(0x07F1)
+#define PORTR_PIN2CTRL _SFR_MEM8(0x07F2)
+#define PORTR_PIN3CTRL _SFR_MEM8(0x07F3)
+#define PORTR_PIN4CTRL _SFR_MEM8(0x07F4)
+#define PORTR_PIN5CTRL _SFR_MEM8(0x07F5)
+#define PORTR_PIN6CTRL _SFR_MEM8(0x07F6)
+#define PORTR_PIN7CTRL _SFR_MEM8(0x07F7)
+
+/* TCC0 - Timer/Counter C0 */
+#define TCC0_CTRLA _SFR_MEM8(0x0800)
+#define TCC0_CTRLB _SFR_MEM8(0x0801)
+#define TCC0_CTRLC _SFR_MEM8(0x0802)
+#define TCC0_CTRLD _SFR_MEM8(0x0803)
+#define TCC0_CTRLE _SFR_MEM8(0x0804)
+#define TCC0_INTCTRLA _SFR_MEM8(0x0806)
+#define TCC0_INTCTRLB _SFR_MEM8(0x0807)
+#define TCC0_CTRLFCLR _SFR_MEM8(0x0808)
+#define TCC0_CTRLFSET _SFR_MEM8(0x0809)
+#define TCC0_CTRLGCLR _SFR_MEM8(0x080A)
+#define TCC0_CTRLGSET _SFR_MEM8(0x080B)
+#define TCC0_INTFLAGS _SFR_MEM8(0x080C)
+#define TCC0_TEMP _SFR_MEM8(0x080F)
+#define TCC0_CNT _SFR_MEM16(0x0820)
+#define TCC0_PER _SFR_MEM16(0x0826)
+#define TCC0_CCA _SFR_MEM16(0x0828)
+#define TCC0_CCB _SFR_MEM16(0x082A)
+#define TCC0_CCC _SFR_MEM16(0x082C)
+#define TCC0_CCD _SFR_MEM16(0x082E)
+#define TCC0_PERBUF _SFR_MEM16(0x0836)
+#define TCC0_CCABUF _SFR_MEM16(0x0838)
+#define TCC0_CCBBUF _SFR_MEM16(0x083A)
+#define TCC0_CCCBUF _SFR_MEM16(0x083C)
+#define TCC0_CCDBUF _SFR_MEM16(0x083E)
+
+/* TCC1 - Timer/Counter C1 */
+#define TCC1_CTRLA _SFR_MEM8(0x0840)
+#define TCC1_CTRLB _SFR_MEM8(0x0841)
+#define TCC1_CTRLC _SFR_MEM8(0x0842)
+#define TCC1_CTRLD _SFR_MEM8(0x0843)
+#define TCC1_CTRLE _SFR_MEM8(0x0844)
+#define TCC1_INTCTRLA _SFR_MEM8(0x0846)
+#define TCC1_INTCTRLB _SFR_MEM8(0x0847)
+#define TCC1_CTRLFCLR _SFR_MEM8(0x0848)
+#define TCC1_CTRLFSET _SFR_MEM8(0x0849)
+#define TCC1_CTRLGCLR _SFR_MEM8(0x084A)
+#define TCC1_CTRLGSET _SFR_MEM8(0x084B)
+#define TCC1_INTFLAGS _SFR_MEM8(0x084C)
+#define TCC1_TEMP _SFR_MEM8(0x084F)
+#define TCC1_CNT _SFR_MEM16(0x0860)
+#define TCC1_PER _SFR_MEM16(0x0866)
+#define TCC1_CCA _SFR_MEM16(0x0868)
+#define TCC1_CCB _SFR_MEM16(0x086A)
+#define TCC1_PERBUF _SFR_MEM16(0x0876)
+#define TCC1_CCABUF _SFR_MEM16(0x0878)
+#define TCC1_CCBBUF _SFR_MEM16(0x087A)
+
+/* AWEXC - Advanced Waveform Extension C */
+#define AWEXC_CTRL _SFR_MEM8(0x0880)
+#define AWEXC_FDEMASK _SFR_MEM8(0x0882)
+#define AWEXC_FDCTRL _SFR_MEM8(0x0883)
+#define AWEXC_STATUS _SFR_MEM8(0x0884)
+#define AWEXC_DTBOTH _SFR_MEM8(0x0886)
+#define AWEXC_DTBOTHBUF _SFR_MEM8(0x0887)
+#define AWEXC_DTLS _SFR_MEM8(0x0888)
+#define AWEXC_DTHS _SFR_MEM8(0x0889)
+#define AWEXC_DTLSBUF _SFR_MEM8(0x088A)
+#define AWEXC_DTHSBUF _SFR_MEM8(0x088B)
+#define AWEXC_OUTOVEN _SFR_MEM8(0x088C)
+
+/* HIRESC - High-Resolution Extension C */
+#define HIRESC_CTRLA _SFR_MEM8(0x0890)
+
+/* USARTC0 - Universal Asynchronous Receiver-Transmitter C0 */
+#define USARTC0_DATA _SFR_MEM8(0x08A0)
+#define USARTC0_STATUS _SFR_MEM8(0x08A1)
+#define USARTC0_CTRLA _SFR_MEM8(0x08A3)
+#define USARTC0_CTRLB _SFR_MEM8(0x08A4)
+#define USARTC0_CTRLC _SFR_MEM8(0x08A5)
+#define USARTC0_BAUDCTRLA _SFR_MEM8(0x08A6)
+#define USARTC0_BAUDCTRLB _SFR_MEM8(0x08A7)
+
+/* USARTC1 - Universal Asynchronous Receiver-Transmitter C1 */
+#define USARTC1_DATA _SFR_MEM8(0x08B0)
+#define USARTC1_STATUS _SFR_MEM8(0x08B1)
+#define USARTC1_CTRLA _SFR_MEM8(0x08B3)
+#define USARTC1_CTRLB _SFR_MEM8(0x08B4)
+#define USARTC1_CTRLC _SFR_MEM8(0x08B5)
+#define USARTC1_BAUDCTRLA _SFR_MEM8(0x08B6)
+#define USARTC1_BAUDCTRLB _SFR_MEM8(0x08B7)
+
+/* SPIC - Serial Peripheral Interface C */
+#define SPIC_CTRL _SFR_MEM8(0x08C0)
+#define SPIC_INTCTRL _SFR_MEM8(0x08C1)
+#define SPIC_STATUS _SFR_MEM8(0x08C2)
+#define SPIC_DATA _SFR_MEM8(0x08C3)
+
+/* IRCOM - IR Communication Module */
+#define IRCOM_CTRL _SFR_MEM8(0x08F8)
+#define IRCOM_TXPLCTRL _SFR_MEM8(0x08F9)
+#define IRCOM_RXPLCTRL _SFR_MEM8(0x08FA)
+
+/* TCD0 - Timer/Counter D0 */
+#define TCD0_CTRLA _SFR_MEM8(0x0900)
+#define TCD0_CTRLB _SFR_MEM8(0x0901)
+#define TCD0_CTRLC _SFR_MEM8(0x0902)
+#define TCD0_CTRLD _SFR_MEM8(0x0903)
+#define TCD0_CTRLE _SFR_MEM8(0x0904)
+#define TCD0_INTCTRLA _SFR_MEM8(0x0906)
+#define TCD0_INTCTRLB _SFR_MEM8(0x0907)
+#define TCD0_CTRLFCLR _SFR_MEM8(0x0908)
+#define TCD0_CTRLFSET _SFR_MEM8(0x0909)
+#define TCD0_CTRLGCLR _SFR_MEM8(0x090A)
+#define TCD0_CTRLGSET _SFR_MEM8(0x090B)
+#define TCD0_INTFLAGS _SFR_MEM8(0x090C)
+#define TCD0_TEMP _SFR_MEM8(0x090F)
+#define TCD0_CNT _SFR_MEM16(0x0920)
+#define TCD0_PER _SFR_MEM16(0x0926)
+#define TCD0_CCA _SFR_MEM16(0x0928)
+#define TCD0_CCB _SFR_MEM16(0x092A)
+#define TCD0_CCC _SFR_MEM16(0x092C)
+#define TCD0_CCD _SFR_MEM16(0x092E)
+#define TCD0_PERBUF _SFR_MEM16(0x0936)
+#define TCD0_CCABUF _SFR_MEM16(0x0938)
+#define TCD0_CCBBUF _SFR_MEM16(0x093A)
+#define TCD0_CCCBUF _SFR_MEM16(0x093C)
+#define TCD0_CCDBUF _SFR_MEM16(0x093E)
+
+/* TCD1 - Timer/Counter D1 */
+#define TCD1_CTRLA _SFR_MEM8(0x0940)
+#define TCD1_CTRLB _SFR_MEM8(0x0941)
+#define TCD1_CTRLC _SFR_MEM8(0x0942)
+#define TCD1_CTRLD _SFR_MEM8(0x0943)
+#define TCD1_CTRLE _SFR_MEM8(0x0944)
+#define TCD1_INTCTRLA _SFR_MEM8(0x0946)
+#define TCD1_INTCTRLB _SFR_MEM8(0x0947)
+#define TCD1_CTRLFCLR _SFR_MEM8(0x0948)
+#define TCD1_CTRLFSET _SFR_MEM8(0x0949)
+#define TCD1_CTRLGCLR _SFR_MEM8(0x094A)
+#define TCD1_CTRLGSET _SFR_MEM8(0x094B)
+#define TCD1_INTFLAGS _SFR_MEM8(0x094C)
+#define TCD1_TEMP _SFR_MEM8(0x094F)
+#define TCD1_CNT _SFR_MEM16(0x0960)
+#define TCD1_PER _SFR_MEM16(0x0966)
+#define TCD1_CCA _SFR_MEM16(0x0968)
+#define TCD1_CCB _SFR_MEM16(0x096A)
+#define TCD1_PERBUF _SFR_MEM16(0x0976)
+#define TCD1_CCABUF _SFR_MEM16(0x0978)
+#define TCD1_CCBBUF _SFR_MEM16(0x097A)
+
+/* HIRESD - High-Resolution Extension D */
+#define HIRESD_CTRLA _SFR_MEM8(0x0990)
+
+/* USARTD0 - Universal Asynchronous Receiver-Transmitter D0 */
+#define USARTD0_DATA _SFR_MEM8(0x09A0)
+#define USARTD0_STATUS _SFR_MEM8(0x09A1)
+#define USARTD0_CTRLA _SFR_MEM8(0x09A3)
+#define USARTD0_CTRLB _SFR_MEM8(0x09A4)
+#define USARTD0_CTRLC _SFR_MEM8(0x09A5)
+#define USARTD0_BAUDCTRLA _SFR_MEM8(0x09A6)
+#define USARTD0_BAUDCTRLB _SFR_MEM8(0x09A7)
+
+/* USARTD1 - Universal Asynchronous Receiver-Transmitter D1 */
+#define USARTD1_DATA _SFR_MEM8(0x09B0)
+#define USARTD1_STATUS _SFR_MEM8(0x09B1)
+#define USARTD1_CTRLA _SFR_MEM8(0x09B3)
+#define USARTD1_CTRLB _SFR_MEM8(0x09B4)
+#define USARTD1_CTRLC _SFR_MEM8(0x09B5)
+#define USARTD1_BAUDCTRLA _SFR_MEM8(0x09B6)
+#define USARTD1_BAUDCTRLB _SFR_MEM8(0x09B7)
+
+/* SPID - Serial Peripheral Interface D */
+#define SPID_CTRL _SFR_MEM8(0x09C0)
+#define SPID_INTCTRL _SFR_MEM8(0x09C1)
+#define SPID_STATUS _SFR_MEM8(0x09C2)
+#define SPID_DATA _SFR_MEM8(0x09C3)
+
+/* TCE0 - Timer/Counter E0 */
+#define TCE0_CTRLA _SFR_MEM8(0x0A00)
+#define TCE0_CTRLB _SFR_MEM8(0x0A01)
+#define TCE0_CTRLC _SFR_MEM8(0x0A02)
+#define TCE0_CTRLD _SFR_MEM8(0x0A03)
+#define TCE0_CTRLE _SFR_MEM8(0x0A04)
+#define TCE0_INTCTRLA _SFR_MEM8(0x0A06)
+#define TCE0_INTCTRLB _SFR_MEM8(0x0A07)
+#define TCE0_CTRLFCLR _SFR_MEM8(0x0A08)
+#define TCE0_CTRLFSET _SFR_MEM8(0x0A09)
+#define TCE0_CTRLGCLR _SFR_MEM8(0x0A0A)
+#define TCE0_CTRLGSET _SFR_MEM8(0x0A0B)
+#define TCE0_INTFLAGS _SFR_MEM8(0x0A0C)
+#define TCE0_TEMP _SFR_MEM8(0x0A0F)
+#define TCE0_CNT _SFR_MEM16(0x0A20)
+#define TCE0_PER _SFR_MEM16(0x0A26)
+#define TCE0_CCA _SFR_MEM16(0x0A28)
+#define TCE0_CCB _SFR_MEM16(0x0A2A)
+#define TCE0_CCC _SFR_MEM16(0x0A2C)
+#define TCE0_CCD _SFR_MEM16(0x0A2E)
+#define TCE0_PERBUF _SFR_MEM16(0x0A36)
+#define TCE0_CCABUF _SFR_MEM16(0x0A38)
+#define TCE0_CCBBUF _SFR_MEM16(0x0A3A)
+#define TCE0_CCCBUF _SFR_MEM16(0x0A3C)
+#define TCE0_CCDBUF _SFR_MEM16(0x0A3E)
+
+/* TCE1 - Timer/Counter E1 */
+#define TCE1_CTRLA _SFR_MEM8(0x0A40)
+#define TCE1_CTRLB _SFR_MEM8(0x0A41)
+#define TCE1_CTRLC _SFR_MEM8(0x0A42)
+#define TCE1_CTRLD _SFR_MEM8(0x0A43)
+#define TCE1_CTRLE _SFR_MEM8(0x0A44)
+#define TCE1_INTCTRLA _SFR_MEM8(0x0A46)
+#define TCE1_INTCTRLB _SFR_MEM8(0x0A47)
+#define TCE1_CTRLFCLR _SFR_MEM8(0x0A48)
+#define TCE1_CTRLFSET _SFR_MEM8(0x0A49)
+#define TCE1_CTRLGCLR _SFR_MEM8(0x0A4A)
+#define TCE1_CTRLGSET _SFR_MEM8(0x0A4B)
+#define TCE1_INTFLAGS _SFR_MEM8(0x0A4C)
+#define TCE1_TEMP _SFR_MEM8(0x0A4F)
+#define TCE1_CNT _SFR_MEM16(0x0A60)
+#define TCE1_PER _SFR_MEM16(0x0A66)
+#define TCE1_CCA _SFR_MEM16(0x0A68)
+#define TCE1_CCB _SFR_MEM16(0x0A6A)
+#define TCE1_PERBUF _SFR_MEM16(0x0A76)
+#define TCE1_CCABUF _SFR_MEM16(0x0A78)
+#define TCE1_CCBBUF _SFR_MEM16(0x0A7A)
+
+/* AWEXE - Advanced Waveform Extension E */
+#define AWEXE_CTRL _SFR_MEM8(0x0A80)
+#define AWEXE_FDEMASK _SFR_MEM8(0x0A82)
+#define AWEXE_FDCTRL _SFR_MEM8(0x0A83)
+#define AWEXE_STATUS _SFR_MEM8(0x0A84)
+#define AWEXE_DTBOTH _SFR_MEM8(0x0A86)
+#define AWEXE_DTBOTHBUF _SFR_MEM8(0x0A87)
+#define AWEXE_DTLS _SFR_MEM8(0x0A88)
+#define AWEXE_DTHS _SFR_MEM8(0x0A89)
+#define AWEXE_DTLSBUF _SFR_MEM8(0x0A8A)
+#define AWEXE_DTHSBUF _SFR_MEM8(0x0A8B)
+#define AWEXE_OUTOVEN _SFR_MEM8(0x0A8C)
+
+/* HIRESE - High-Resolution Extension E */
+#define HIRESE_CTRLA _SFR_MEM8(0x0A90)
+
+/* USARTE0 - Universal Asynchronous Receiver-Transmitter E0 */
+#define USARTE0_DATA _SFR_MEM8(0x0AA0)
+#define USARTE0_STATUS _SFR_MEM8(0x0AA1)
+#define USARTE0_CTRLA _SFR_MEM8(0x0AA3)
+#define USARTE0_CTRLB _SFR_MEM8(0x0AA4)
+#define USARTE0_CTRLC _SFR_MEM8(0x0AA5)
+#define USARTE0_BAUDCTRLA _SFR_MEM8(0x0AA6)
+#define USARTE0_BAUDCTRLB _SFR_MEM8(0x0AA7)
+
+/* USARTE1 - Universal Asynchronous Receiver-Transmitter E1 */
+#define USARTE1_DATA _SFR_MEM8(0x0AB0)
+#define USARTE1_STATUS _SFR_MEM8(0x0AB1)
+#define USARTE1_CTRLA _SFR_MEM8(0x0AB3)
+#define USARTE1_CTRLB _SFR_MEM8(0x0AB4)
+#define USARTE1_CTRLC _SFR_MEM8(0x0AB5)
+#define USARTE1_BAUDCTRLA _SFR_MEM8(0x0AB6)
+#define USARTE1_BAUDCTRLB _SFR_MEM8(0x0AB7)
+
+/* SPIE - Serial Peripheral Interface E */
+#define SPIE_CTRL _SFR_MEM8(0x0AC0)
+#define SPIE_INTCTRL _SFR_MEM8(0x0AC1)
+#define SPIE_STATUS _SFR_MEM8(0x0AC2)
+#define SPIE_DATA _SFR_MEM8(0x0AC3)
+
+/* TCF0 - Timer/Counter F0 */
+#define TCF0_CTRLA _SFR_MEM8(0x0B00)
+#define TCF0_CTRLB _SFR_MEM8(0x0B01)
+#define TCF0_CTRLC _SFR_MEM8(0x0B02)
+#define TCF0_CTRLD _SFR_MEM8(0x0B03)
+#define TCF0_CTRLE _SFR_MEM8(0x0B04)
+#define TCF0_INTCTRLA _SFR_MEM8(0x0B06)
+#define TCF0_INTCTRLB _SFR_MEM8(0x0B07)
+#define TCF0_CTRLFCLR _SFR_MEM8(0x0B08)
+#define TCF0_CTRLFSET _SFR_MEM8(0x0B09)
+#define TCF0_CTRLGCLR _SFR_MEM8(0x0B0A)
+#define TCF0_CTRLGSET _SFR_MEM8(0x0B0B)
+#define TCF0_INTFLAGS _SFR_MEM8(0x0B0C)
+#define TCF0_TEMP _SFR_MEM8(0x0B0F)
+#define TCF0_CNT _SFR_MEM16(0x0B20)
+#define TCF0_PER _SFR_MEM16(0x0B26)
+#define TCF0_CCA _SFR_MEM16(0x0B28)
+#define TCF0_CCB _SFR_MEM16(0x0B2A)
+#define TCF0_CCC _SFR_MEM16(0x0B2C)
+#define TCF0_CCD _SFR_MEM16(0x0B2E)
+#define TCF0_PERBUF _SFR_MEM16(0x0B36)
+#define TCF0_CCABUF _SFR_MEM16(0x0B38)
+#define TCF0_CCBBUF _SFR_MEM16(0x0B3A)
+#define TCF0_CCCBUF _SFR_MEM16(0x0B3C)
+#define TCF0_CCDBUF _SFR_MEM16(0x0B3E)
+
+/* TCF1 - Timer/Counter F1 */
+#define TCF1_CTRLA _SFR_MEM8(0x0B40)
+#define TCF1_CTRLB _SFR_MEM8(0x0B41)
+#define TCF1_CTRLC _SFR_MEM8(0x0B42)
+#define TCF1_CTRLD _SFR_MEM8(0x0B43)
+#define TCF1_CTRLE _SFR_MEM8(0x0B44)
+#define TCF1_INTCTRLA _SFR_MEM8(0x0B46)
+#define TCF1_INTCTRLB _SFR_MEM8(0x0B47)
+#define TCF1_CTRLFCLR _SFR_MEM8(0x0B48)
+#define TCF1_CTRLFSET _SFR_MEM8(0x0B49)
+#define TCF1_CTRLGCLR _SFR_MEM8(0x0B4A)
+#define TCF1_CTRLGSET _SFR_MEM8(0x0B4B)
+#define TCF1_INTFLAGS _SFR_MEM8(0x0B4C)
+#define TCF1_TEMP _SFR_MEM8(0x0B4F)
+#define TCF1_CNT _SFR_MEM16(0x0B60)
+#define TCF1_PER _SFR_MEM16(0x0B66)
+#define TCF1_CCA _SFR_MEM16(0x0B68)
+#define TCF1_CCB _SFR_MEM16(0x0B6A)
+#define TCF1_PERBUF _SFR_MEM16(0x0B76)
+#define TCF1_CCABUF _SFR_MEM16(0x0B78)
+#define TCF1_CCBBUF _SFR_MEM16(0x0B7A)
+
+/* HIRESF - High-Resolution Extension F */
+#define HIRESF_CTRLA _SFR_MEM8(0x0B90)
+
+/* USARTF0 - Universal Asynchronous Receiver-Transmitter F0 */
+#define USARTF0_DATA _SFR_MEM8(0x0BA0)
+#define USARTF0_STATUS _SFR_MEM8(0x0BA1)
+#define USARTF0_CTRLA _SFR_MEM8(0x0BA3)
+#define USARTF0_CTRLB _SFR_MEM8(0x0BA4)
+#define USARTF0_CTRLC _SFR_MEM8(0x0BA5)
+#define USARTF0_BAUDCTRLA _SFR_MEM8(0x0BA6)
+#define USARTF0_BAUDCTRLB _SFR_MEM8(0x0BA7)
+
+/* USARTF1 - Universal Asynchronous Receiver-Transmitter F1 */
+#define USARTF1_DATA _SFR_MEM8(0x0BB0)
+#define USARTF1_STATUS _SFR_MEM8(0x0BB1)
+#define USARTF1_CTRLA _SFR_MEM8(0x0BB3)
+#define USARTF1_CTRLB _SFR_MEM8(0x0BB4)
+#define USARTF1_CTRLC _SFR_MEM8(0x0BB5)
+#define USARTF1_BAUDCTRLA _SFR_MEM8(0x0BB6)
+#define USARTF1_BAUDCTRLB _SFR_MEM8(0x0BB7)
+
+/* SPIF - Serial Peripheral Interface F */
+#define SPIF_CTRL _SFR_MEM8(0x0BC0)
+#define SPIF_INTCTRL _SFR_MEM8(0x0BC1)
+#define SPIF_STATUS _SFR_MEM8(0x0BC2)
+#define SPIF_DATA _SFR_MEM8(0x0BC3)
+
+
+
+/*================== Bitfield Definitions ================== */
+
+/* VPORT - Virtual Ports */
+/* VPORT.INTFLAGS bit masks and bit positions */
+#define VPORT_INT1IF_bm 0x02 /* Port Interrupt 1 Flag bit mask. */
+#define VPORT_INT1IF_bp 1 /* Port Interrupt 1 Flag bit position. */
+
+#define VPORT_INT0IF_bm 0x01 /* Port Interrupt 0 Flag bit mask. */
+#define VPORT_INT0IF_bp 0 /* Port Interrupt 0 Flag bit position. */
+
+
+/* XOCD - On-Chip Debug System */
+/* OCD.OCDR1 bit masks and bit positions */
+#define OCD_OCDRD_bm 0x01 /* OCDR Dirty bit mask. */
+#define OCD_OCDRD_bp 0 /* OCDR Dirty bit position. */
+
+
+/* CPU - CPU */
+/* CPU.CCP bit masks and bit positions */
+#define CPU_CCP_gm 0xFF /* CCP signature group mask. */
+#define CPU_CCP_gp 0 /* CCP signature group position. */
+#define CPU_CCP0_bm (1<<0) /* CCP signature bit 0 mask. */
+#define CPU_CCP0_bp 0 /* CCP signature bit 0 position. */
+#define CPU_CCP1_bm (1<<1) /* CCP signature bit 1 mask. */
+#define CPU_CCP1_bp 1 /* CCP signature bit 1 position. */
+#define CPU_CCP2_bm (1<<2) /* CCP signature bit 2 mask. */
+#define CPU_CCP2_bp 2 /* CCP signature bit 2 position. */
+#define CPU_CCP3_bm (1<<3) /* CCP signature bit 3 mask. */
+#define CPU_CCP3_bp 3 /* CCP signature bit 3 position. */
+#define CPU_CCP4_bm (1<<4) /* CCP signature bit 4 mask. */
+#define CPU_CCP4_bp 4 /* CCP signature bit 4 position. */
+#define CPU_CCP5_bm (1<<5) /* CCP signature bit 5 mask. */
+#define CPU_CCP5_bp 5 /* CCP signature bit 5 position. */
+#define CPU_CCP6_bm (1<<6) /* CCP signature bit 6 mask. */
+#define CPU_CCP6_bp 6 /* CCP signature bit 6 position. */
+#define CPU_CCP7_bm (1<<7) /* CCP signature bit 7 mask. */
+#define CPU_CCP7_bp 7 /* CCP signature bit 7 position. */
+
+
+/* CPU.SREG bit masks and bit positions */
+#define CPU_I_bm 0x80 /* Global Interrupt Enable Flag bit mask. */
+#define CPU_I_bp 7 /* Global Interrupt Enable Flag bit position. */
+
+#define CPU_T_bm 0x40 /* Transfer Bit bit mask. */
+#define CPU_T_bp 6 /* Transfer Bit bit position. */
+
+#define CPU_H_bm 0x20 /* Half Carry Flag bit mask. */
+#define CPU_H_bp 5 /* Half Carry Flag bit position. */
+
+#define CPU_S_bm 0x10 /* N Exclusive Or V Flag bit mask. */
+#define CPU_S_bp 4 /* N Exclusive Or V Flag bit position. */
+
+#define CPU_V_bm 0x08 /* Two's Complement Overflow Flag bit mask. */
+#define CPU_V_bp 3 /* Two's Complement Overflow Flag bit position. */
+
+#define CPU_N_bm 0x04 /* Negative Flag bit mask. */
+#define CPU_N_bp 2 /* Negative Flag bit position. */
+
+#define CPU_Z_bm 0x02 /* Zero Flag bit mask. */
+#define CPU_Z_bp 1 /* Zero Flag bit position. */
+
+#define CPU_C_bm 0x01 /* Carry Flag bit mask. */
+#define CPU_C_bp 0 /* Carry Flag bit position. */
+
+
+/* CLK - Clock System */
+/* CLK.CTRL bit masks and bit positions */
+#define CLK_SCLKSEL_gm 0x07 /* System Clock Selection group mask. */
+#define CLK_SCLKSEL_gp 0 /* System Clock Selection group position. */
+#define CLK_SCLKSEL0_bm (1<<0) /* System Clock Selection bit 0 mask. */
+#define CLK_SCLKSEL0_bp 0 /* System Clock Selection bit 0 position. */
+#define CLK_SCLKSEL1_bm (1<<1) /* System Clock Selection bit 1 mask. */
+#define CLK_SCLKSEL1_bp 1 /* System Clock Selection bit 1 position. */
+#define CLK_SCLKSEL2_bm (1<<2) /* System Clock Selection bit 2 mask. */
@@ Diff output truncated at 153600 characters. @@
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- [avr-libc-commit] [2108] 2010-03-22 Eric B.,
Eric Weddington <=