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Re: LOGID 193153: Power-elf problems - IBM PowerPC 440 Star IP
|
From: |
Duncan Irving |
|
Subject: |
Re: LOGID 193153: Power-elf problems - IBM PowerPC 440 Star IP |
|
Date: |
Thu, 12 Feb 2004 15:09:34 -0500 |
|
User-agent: |
Mozilla/5.0 (X11; U; Linux i686; en-US; rv:1.4) Gecko/20030624 Netscape/7.1 |
Problem was found with version of GNU assembler , I was using version
2.14 package and had the problem described below, I fetched version
2.13 and all compiles properly now!
I was using the package GNU assembler listed below on Linux RH 7.2 and I
could not compile the tlbwe or tlbre PowerPC booke instructions.
> powerpc-elf-as -version
GNU assembler 2.14 20030612
Copyright 2002 Free Software Foundation, Inc.
This program is free software; you may redistribute it under the terms of
the GNU General Public License. This program has absolutely no warranty.
This assembler was configured for a target of `powerpc-elf'.
I've attached the failing source code for debuging version 2.14
Thanks,
Duncan Irving
--
Senior Silicon Verification Engineer
Seaway Networks
One Chrysalis Way, Suite 300
Ottawa, Ontario, K2G 6P9
Tel: 613-723-9161 ext 4063
Fax: 613-723-8244
address@hidden wrote:
Dear Duncan Irving,
We received email regarding "Power-elf problems - IBM PowerPC 440 Star IP
A log has been opened for your issue and assigned to a Support Center Engr.
The LOGID of this call is LOGID : 193153
For future support requests, please open your call by using
"Enter A Call" at http://solvnet.synopsys.com/EnterACall.
"Enter A Call" is the fastest way to get support for new requests.
__________________________
When corresponding with the Synopsys Support Center (address@hidden) about this
issue, please include the LOGID number in the subject line.
Example:
Subject: LOGID XXXXXX : testcase included
Regards,
Abra Lusk
Synopsys Support Center (North America)
Web: http://www.synopsys.com/support/support.html (for FASTEST response!)
Phone : 800-245-8005, 650-584-4200
Email : address@hidden
Have you used SolvNET, our on-line knowledgebase ?
http://www.synopsys.com/ Click on SolvNET
From: "Dwight Eddy" <address@hidden>
To: "Support_Center_HLD" <address@hidden>
Subject: FW: Power-elf problems
Date: Thu, 12 Feb 2004 11:02:09 -0500
1.
Please open a new support call for Duncan Irving
at Seaway Networks. He is using the DW_IBM440 Verification IP
on Linux RH 7.2 and can not compile has assembler code.
Please contact Duncan directly and copy me on all email
Thanks, your quick attention will be appreciated. He
tried to contact me while I have been traveling.
---------------
Dwight Eddy Synopsys
Staff Application Consultant 377 Simarano Drive
Verification Specialist Suite 300
Tel: 508-263-8094 Marlborough, Ma 01752
Fax: 508-263-8090 email: address@hidden
Cell: 603-785-8160 http://www.synopsys.com
Ottawa: 613-221-8621 http://solvnet.synopsys.com
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Web Support : http://solvnet.synopsys.com/EnterACall
Support Center : (800) 245-8005 or address@hidden
--=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
-----Original Message-----
From: Duncan Irving [mailto:address@hidden
Sent: Wednesday, February 11, 2004 10:22 AM
To: address@hidden
Subject: Power-elf problems
Dwight,
Thanks for your help in getting the simulation's started, I'm now
executing the testcases provided with the PowerPC core kit, I would like
to add some of my own testcase and I'm trying to follow the power-elf
compile options but I'm getting the following problems, I'm wondering if
you could provide me with some help to resolve these?
These errors occurred on one of the testcases provide in the kit? So I
don't think it's a coding issue, could it be a tool/OS issue?
Any help would be greatly appreciated, Thanks,
Duncan
powerpc-elf-as -als=PPC440.dcba.7.1.4.o.lst -m booke -I. -o
PPC440.dcba.7.1.4.o PPC440.dcba.7.1.4.s
./sysini.s: Assembler messages:
./sysini.s:578: Error: junk at end of line: `r0,r5,0'
./sysini.s:796: Error: junk at end of line: `r4,r3,0'
./sysini.s:797: Error: junk at end of line: `r5,r3,1'
./sysini.s:798: Error: junk at end of line: `r6,r3,2'
PPC440.dcba.7.1.4.s:50: Error: junk at end of line: `r12,r11,0'
PPC440.dcba.7.1.4.s:52: Error: junk at end of line: `r12,r11,1'
PPC440.dcba.7.1.4.s:54: Error: junk at end of line: `r12,r11,2'
PPC440.dcba.1.1.4.s:99: Error: junk at end of line: `r4,r3,0'
PPC440.dcba.1.1.4.s:99: Error: junk at end of line: `r5,r3,1'
PPC440.dcba.1.1.4.s:99: Error: junk at end of line: `r6,r3,2'
PPC440.dcba.1.1.4.s:99: Error: junk at end of line: `r4,r3,0'
PPC440.dcba.1.1.4.s:99: Error: junk at end of line: `r5,r3,1'
PPC440.dcba.1.1.4.s:99: Error: junk at end of line: `r6,r3,2'
2. Power-elf problems
From: "Duncan Irving" <address@hidden>
To: <address@hidden>
Subject: Power-elf problems
Date: Wed, 11 Feb 2004 10:22:16 -0500
Dwight,
Thanks for your help in getting the simulation's started, I'm now
executing the testcases provided with the PowerPC core kit, I would like
to add some of my own testcase and I'm trying to follow the power-elf
compile options but I'm getting the following problems, I'm wondering if
you could provide me with some help to resolve these?
These errors occurred on one of the testcases provide in the kit? So I
don't think it's a coding issue, could it be a tool/OS issue?
Any help would be greatly appreciated, Thanks,
Duncan
powerpc-elf-as -als=PPC440.dcba.7.1.4.o.lst -m booke -I. -o
PPC440.dcba.7.1.4.o PPC440.dcba.7.1.4.s
./sysini.s: Assembler messages:
./sysini.s:578: Error: junk at end of line: `r0,r5,0'
./sysini.s:796: Error: junk at end of line: `r4,r3,0'
./sysini.s:797: Error: junk at end of line: `r5,r3,1'
./sysini.s:798: Error: junk at end of line: `r6,r3,2'
PPC440.dcba.7.1.4.s:50: Error: junk at end of line: `r12,r11,0'
PPC440.dcba.7.1.4.s:52: Error: junk at end of line: `r12,r11,1'
PPC440.dcba.7.1.4.s:54: Error: junk at end of line: `r12,r11,2'
PPC440.dcba.1.1.4.s:99: Error: junk at end of line: `r4,r3,0'
PPC440.dcba.1.1.4.s:99: Error: junk at end of line: `r5,r3,1'
PPC440.dcba.1.1.4.s:99: Error: junk at end of line: `r6,r3,2'
PPC440.dcba.1.1.4.s:99: Error: junk at end of line: `r4,r3,0'
PPC440.dcba.1.1.4.s:99: Error: junk at end of line: `r5,r3,1'
PPC440.dcba.1.1.4.s:99: Error: junk at end of line: `r6,r3,2'
#
# **************************************************************************
#
# Copyright (c) International Business Machines Corporation, 2002.
#
# This file contains trade secrets and other proprietary and confidential
# information of International Business Machines Corporation which are
# protected by copyright and other intellectual property rights and shall
# not be reproduced, transferred to other documents, disclosed to others,
# or used for any purpose except as specifically authorized in writing by
# International Business Machines Corporation. This notice must be
# contained as part of this text at all times.
#
# **************************************************************************
#
# Start-up function for an embedded environment
# The size of this program is approximately 400 bytes plus wee need to
allocate interrupt handlers
# ie., another 4096 bytes. So, the initial page size should be 5 KB
.file "sysini.s"
#------------------------------------------------------------------------------#
# Macros for use in testcases
#
#------------------------------------------------------------------------------#
.macro EPILOG # sets pass and fail detection
values for testfixture
pass:
.p2alignl 4,0x60000000
b S12345 # Success: Branch around
NOPs...
nop # Move away one cache line...
nop # .
S12345:
# Set up entry 1 in TLB # Modify to map tlb(1)
addi r3,r0,0x0001 # tlb entry number
addis r4,r0,0x0000
ori r4,r4,0x0250 # EPN = '00000Xs', V=1(Valid),
TM=0 (Normal mode??), Size=1MB
addis r5,r0,0x0000
ori r5,r5,0x0000 # RPN = '00000Xs', 6'b0, ERPN
= 4'b0000
addi r6,r0,0x083f # 16'b0, U0-U3=0,
WIMGE=5b'10000, 1'b0, UX/UW/UR/SX/SW/SR = 0x3f (enabled)
tlbwe r4,r3,0 # Write word 0 of TLB Entry
tlbwe r5,r3,1 # Write word 1 of TLB Entry
tlbwe r6,r3,2 # Write word 2 of TLB Entry
isync
addis r2,r0,0xC00D # Load SPRG3 and DBDR with
0xC00DF00D...
ori r2,r2,0xF00D # .
ori r7,r0,0x0010 # .
stwx r2,r0,r7 # .
mtspr SPRG3,r2 # .
mtspr DBDR,r2 # .
b setepidb # Setup Debug and wait for
JTAG to take control...
ERROR:
# Set up entry 1 in TLB # Modify to map tlb(1)
addi r3,r0,0x0001 # tlb entry number
addis r4,r0,0x0000
ori r4,r4,0x0250 # EPN = '00000Xs', V=1(Valid),
TM=0 (Normal mode??), Size=1MB
addis r5,r0,0x0000
ori r5,r5,0x0000 # RPN = '00000Xs', 6'b0, ERPN
= 4'b0000
addi r6,r0,0x083f # 16'b0, U0-U3=0,
WIMGE=5b'10000, 1'b0, UX/UW/UR/SX/SW/SR = 0x3f (enabled)
tlbwe r4,r3,0 # Write word 0 of TLB Entry
tlbwe r5,r3,1 # Write word 1 of TLB Entry
tlbwe r6,r3,2 # Write word 2 of TLB Entry
isync
addis r2,r0,0xDEAD # Failure: Load SPRG3 and DBDR
with 0xDEADBEEF...
ori r2,r2,0xBEEF # .
ori r7,r0,0x0010 # .
stwx r2,r0,r7 # .
mtspr SPRG3,r2 # .
mtspr DBDR,r2 # .
setepidb:
addi 2,0,0x0000 # Make sure all Debug Events
are off...
mtspr DBCR0,r2
addi r2,r0,0xFFFFFFFF # Reset the DBSR...
mtspr DBSR,r2 # .
addis r2,r0,0x8004 # Put JTAG in External Mode,
freeze timers...
mtspr DBCR0,r2
addis r2,r0,0x0810 # Force unconditional,
imprecise Debug Event...
mtspr DBSRS,r2 # .
.p2alignl 4,0x60000000
b $ # Loop and wait for JTAG to
take control...
nop
nop
nop
nop
nop
nop
nop
.p2alignl 4,0x60000000
.endm
.macro FAILTEST # Used by unexpected interrupt
routines to fail the testcase
addis r2,r0,0xDEAD # Failure: Load SPRG3 and DBDR
with 0xDEADBEEF...
ori r2,r2,0xBEEF # .
mtspr SPRG3,r2 # .
mtspr DBDR,r2 # .
addi r2,r0,0x0000 # Make sure all Debug Events
are off...
mtspr DBCR0,r2
addi r2,r0,0xFFFFFFFF # Reset the DBSR...
mtspr DBSR,r2 # .
addis r2,r0,0x8004 # Put JTAG in External Mode,
freeze timers...
mtspr DBCR0,r2
addis r2,r0,0x0810 # Force unconditional,
imprecise Debug Event...
mtspr DBSRS,r2 # .
b $ # Loop and wait for JTAG to
take control...
.endm
#============= Instructions not supported by assembler codes as macros
==========================
.macro DCCCI RA,RB
.long 0x7c000000 | (\RA<<16) | (\RB<<11) | (454<<1)
.endm
.macro DLMZB RA,RS,RB
.long 0x7c000000 | (\RS<<21) | (\RA<<16) | (\RB<<11) | (78<<1)
.endm
.macro DLMZBDOT RA,RS,RB
.long 0x7c000000 | (\RS<<21) | (\RA<<16) | (\RB<<11) | (78<<1) | 1
.endm
.macro ICCCI RA,RB
.long 0x7c000000 | (\RA<<16) | (\RB<<11) | (966<<1)
.endm
.macro ICREAD RA,RB
.long 0x7c000000 | (\RA<<16) | (\RB<<11) | (998<<1)
.endm
.macro ISEL RT,RA,RB,CRb
.long 0x7c000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (\CRb<<6) | (15<<1)
.endm
.macro DCREAD RT,RA,RB
.long 0x7C000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (486<<1)
.endm
.macro RFMCI
.long 0x4c000000 | (38<<1)
.endm
.macro TLBSX RT,RA,RB
.long 0x7C000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (914<<1)
.endm
.macro TLBSXDOT RT,RA,RB
.long 0x7C000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (914<<1) | 1
.endm
.macro MACCHW RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (172<<1)
.endm
.macro MACCHWDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (172<<1) | 1
.endm
.macro MACCHWO RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (172<<1)
.endm
.macro MACCHWODOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (172<<1) | 1
.endm
.macro MACCHWS RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (236<<1)
.endm
.macro MACCHWSDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (236<<1) | 1
.endm
.macro MACCHWSO RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (236<<1)
.endm
.macro MACCHWSODOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (236<<1) | 1
.endm
.macro MACCHWSU RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (204<<1)
.endm
.macro MACCHWSUDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (204<<1) | 1
.endm
.macro MACCHWSUO RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (204<<1)
.endm
.macro MACCHWSUODOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (204<<1) | 1
.endm
.macro MACCHWU RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (140<<1)
.endm
.macro MACCHWUDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (140<<1) | 1
.endm
.macro MACCHWUO RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (140<<1)
.endm
.macro MACCHWUODOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (140<<1) | 1
.endm
.macro MACHHW RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (44<<1)
.endm
.macro MACHHWDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (44<<1) | 1
.endm
.macro MACHHWO RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (44<<1)
.endm
.macro MACHHWODOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (44<<1) | 1
.endm
.macro MACHHWS RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (108<<1)
.endm
.macro MACHHWSDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (108<<1) | 1
.endm
.macro MACHHWSO RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (108<<1)
.endm
.macro MACHHWSODOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (108<<1) | 1
.endm
.macro MACHHWSU RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (76<<1)
.endm
.macro MACHHWSUDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (76<<1) | 1
.endm
.macro MACHHWSUO RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (76<<1)
.endm
.macro MACHHWSUODOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (76<<1) | 1
.endm
.macro MACHHWU RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (12<<1)
.endm
.macro MACHHWUDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (12<<1) | 1
.endm
.macro MACHHWUO RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (12<<1)
.endm
.macro MACHHWUODOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (12<<1) | 1
.endm
.macro MACLHW RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (428<<1)
.endm
.macro MACLHWDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (428<<1) | 1
.endm
.macro MACLHWO RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (428<<1)
.endm
.macro MACLHWODOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (428<<1) | 1
.endm
.macro MACLHWS RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (492<<1)
.endm
.macro MACLHWSDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (492<<1) | 1
.endm
.macro MACLHWSO RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (492<<1)
.endm
.macro MACLHWSODOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (492<<1) | 1
.endm
.macro MACLHWSU RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (460<<1)
.endm
.macro MACLHWSUDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (460<<1) | 1
.endm
.macro MACLHWSUO RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (460<<1)
.endm
.macro MACLHWSUODOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (460<<1) | 1
.endm
.macro MACLHWU RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (396<<1)
.endm
.macro MACLHWUDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (396<<1) | 1
.endm
.macro MACLHWUO RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (396<<1)
.endm
.macro MACLHWUODOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (396<<1) | 1
.endm
.macro MULHHW RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (40<<1)
.endm
.macro MULHHWDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (40<<1) | 1
.endm
.macro MULHHWU RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (8<<1)
.endm
.macro MULHHWUDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (8<<1) | 1
.endm
.macro MULCHW RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (168<<1)
.endm
.macro MULCHWDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (168<<1) | 1
.endm
.macro MULCHWU RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (136<<1)
.endm
.macro MULCHWUDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (136<<1) | 1
.endm
.macro MULLHW RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (424<<1)
.endm
.macro MULLHWDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (424<<1) | 1
.endm
.macro MULLHWU RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (392<<1)
.endm
.macro MULLHWUDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (392<<1) | 1
.endm
.macro NMACCHW RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (174<<1)
.endm
.macro NMACCHWDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (174<<1) | 1
.endm
.macro NMACCHWO RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (174<<1)
.endm
.macro NMACCHWODOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (174<<1) | 1
.endm
.macro NMACCHWS RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (238<<1)
.endm
.macro NMACCHWSDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (238<<1) | 1
.endm
.macro NMACCHWSO RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (238<<1)
.endm
.macro NMACCHWSODOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (238<<1) | 1
.endm
.macro NMACHHW RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (46<<1)
.endm
.macro NMACHHWDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (46<<1) | 1
.endm
.macro NMACHHWO RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (46<<1)
.endm
.macro NMACHHWODOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (46<<1) | 1
.endm
.macro NMACHHWS RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (110<<1)
.endm
.macro NMACHHWSDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (110<<1) | 1
.endm
.macro NMACHHWSO RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (110<<1)
.endm
.macro NMACHHWSODOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (110<<1) | 1
.endm
.macro NMACLHW RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (430<<1)
.endm
.macro NMACLHWDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (430<<1) | 1
.endm
.macro NMACLHWO RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (430<<1)
.endm
.macro NMACLHWODOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (430<<1) | 1
.endm
.macro NMACLHWS RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (494<<1)
.endm
.macro NMACLHWSDOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (494<<1) | 1
.endm
.macro NMACLHWSO RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (494<<1)
.endm
.macro NMACLHWSODOT RT,RA,RB
.long 0x10000000 | (\RT<<21) | (\RA<<16) | (\RB<<11) | (1<<10) | (494<<1) | 1
.endm
#------------------------------------------------------------------------------#
# END OF MACRO DEFINITIONS
#
#------------------------------------------------------------------------------#
#------------------------------------------------------------------------------#
# General Purpose Registers...
#
#------------------------------------------------------------------------------#
.set r0,0
.set r1,1
.set r2,2
.set r3,3
.set r4,4
.set r5,5
.set r6,6
.set r7,7
.set r8,8
.set r9,9
.set r10,10
.set r11,11
.set r12,12
.set r13,13
.set r14,14
.set r15,15
.set r16,16
.set r17,17
.set r18,18
.set r19,19
.set r20,20
.set r21,21
.set r22,22
.set r23,23
.set r24,24
.set r25,25
.set r26,26
.set r27,27
.set r28,28
.set r29,29
.set r30,30
.set r31,31
#------------------------------------------------------------------------------#
# Special Purpose Registers...
#
#------------------------------------------------------------------------------#
.set XER,0x0001 # Fixed Point Exception
Register
.set LR,0x0008 # Link Register
.set CTR,0x0009 # Count Register
.set DEC,0x0016 # DECrementer
.set SRR0,0x001A # Save/Restore Register 0
.set SRR1,0x001B # Save/Restore Register 1
.set PID,0x0030 # Processor ID Register
.set DECAR,0x0036 # DECrementer Auto Reload
.set CSRR0,0x003A # Critical Save/Restore
Register 0
.set CSRR1,0x003B # Critical Save/Restore
Register 1
.set DEAR,0x003D # Data Error Address Register
NEWADDR
.set ESR,0x003E # Error Syndrome Register
NEWADDR
.set IVPR,0x003F # Interrupt Vector Prefix
Register
.set USPRG0,0x0100 # User Special Purpose Reg
General 0
.set SPRG4,0x0104 # SPR General 4
.set SPRG5,0x0105 # SPR General 5
.set SPRG6,0x0106 # SPR General 6
.set SPRG7,0x0107 # SPR General 7
.set TBL,0x010C # Time Base Low (Read)
.set TBU,0x010D # Time Base High (Read)
.set SPRG0,0x0110 # SPR General 0
.set SPRG1,0x0111 # SPR General 1
.set SPRG2,0x0112 # SPR General 2
.set SPRG3,0x0113 # SPR General 3
.set SPRG4W,0x0114 # Special Purpose Reg General
4 (Write)
.set SPRG5W,0x0115 # Special Purpose Reg General
4 (Write)
.set SPRG6W,0x0116 # Special Purpose Reg General
4 (Write)
.set SPRG7W,0x0117 # Special Purpose Reg General
4 (Write)
.set TBLW,0x011C # Time Base Low (Write)
.set TBUW,0x011D # Time Base High (Write)
.set PIR,0x011E # Processor Identification
Register
.set PVR,0x011F # Processor Version Register
.set DBSR,0x0130 # Debug Status Register
.set DBCR0,0x0134 # Debug Control Register 0
.set DBCR1,0x0135 # Debug Control Register 1
.set DBCR2,0x0136 # Debug Control Register 2
.set IAC1,0x0138 # Instruction Address Compare
Register 1
.set IAC2,0x0139 # Instruction Address Compare
Register 2
.set IAC3,0x013A # Instruction Address Compare
Register 3
.set IAC4,0x013B # Instruction Address Compare
Register 4
.set DAC1,0x013C # Data Address Compare
Register 1
.set DAC2,0x013D # Data Address Compare
Register 2
.set DVC1,0x013E # Data Value Compare Register 1
.set DVC2,0x013F # Data Value Compare Register 2
.set TSR,0x0150 # Timer Status Register
.set TCR,0x0154 # Timer Control Register
.set IVOR0,0x0190 # Interrupt Vector Offset
Register 0
.set IVOR1,0x0191 # Interrupt Vector Offset
Register 1
.set IVOR2,0x0192 # Interrupt Vector Offset
Register 2
.set IVOR3,0x0193 # Interrupt Vector Offset
Register 3
.set IVOR4,0x0194 # Interrupt Vector Offset
Register 4
.set IVOR5,0x0195 # Interrupt Vector Offset
Register 5
.set IVOR6,0x0196 # Interrupt Vector Offset
Register 6
.set IVOR7,0x0197 # Interrupt Vector Offset
Register 7
.set IVOR8,0x0198 # Interrupt Vector Offset
Register 8
.set IVOR9,0x0199 # Interrupt Vector Offset
Register 9
.set IVOR10,0x019A # Interrupt Vector Offset
Register 10
.set IVOR11,0x019B # Interrupt Vector Offset
Register 11
.set IVOR12,0x019C # Interrupt Vector Offset
Register 12
.set IVOR13,0x019D # Interrupt Vector Offset
Register 13
.set IVOR14,0x019E # Interrupt Vector Offset
Register 14
.set IVOR15,0x019F # Interrupt Vector Offset
Register 15
.set MCSRR0,0x23A # Machine Check Save Restore
Register 0
.set MCSRR1,0x23B # Machine Check Save Restroe
Register 1
.set MCSR,0x23C # Machine Check Status Register
.set DBSRS,0x0330 # Debug Status Register (Set
Address)
.set TSRS,0x0350 # Timer Status Register (Set
Address)
.set INV0,0x0370 # Instruction cache Normal
Victim 0
.set INV1,0x0371 # Instruction cache Normal
Victim 1
.set INV2,0x0372 # Instruction cache Normal
Victim 2
.set INV3,0x0373 # Instruction cache Normal
Victim 3
.set ITV0,0x0374 # Instruction cache Transient
Victim 0
.set ITV1,0x0375 # Instruction cache Transient
Victim 1
.set ITV2,0x0376 # Instruction cache Transient
Victim 2
.set ITV3,0x0377 # Instruction cache Transient
Victim 3
.set CCR1,0x0378 # Core Configuration Register 1
.set DNV0,0x0390 # Data cache Normal Victim 0
.set DNV1,0x0391 # Data cache Normal Victim 1
.set DNV2,0x0392 # Data cache Normal Victim 2
.set DNV3,0x0393 # Data cache Normal Victim 3
.set DTV0,0x0394 # Data cache Transient Victim 0
.set DTV1,0x0395 # Data cache Transient Victim 1
.set DTV2,0x0396 # Data cache Transient Victim 2
.set DTV3,0x0397 # Data cache Transient Victim 3
.set DVLIM,0x0398 # Data Cache Victim Limit
.set IVLIM,0x0399 # Instruction Cache Victim
Limit
.set DCDBTRL,0x039C # Data Cache Debug Tag Reg Low
.set DCDBTRH,0x039D # Data Cache Debug Tag Reg High
.set ICDBTRL,0x039E # Instruction Cache Debug Tag
Reg Low
.set ICDBTRH,0x039F # Instruction Cache Debug Tag
Reg High
.set MMUCR,0x03B2 # MMU Control Register
.set CCR0,0x03B3 # Core Configuration Register
.set TIAR,0x03D0 # Trace Instruction Address
Register
.set TCTR,0x03D1 # Trace Count Register
.set TLR,0x03D2 # Trace Link Register
.set ICDBDR,0x03D3 # I-Cache Debug Data Register
.set CDBCR,0x03D7 # Cache Debug Control Register
.set PIT,0x03DB # Programmable Interval Timer
Register
.set TBHI,0x03DC # Time Base High Register
.set TBLO,0x03DD # Time Base Low Register
.set DBCR,0x03F2 # Debug Control Register
.set DBDR,0x03F3 # Debug Data Register
# Testbench Registers
.set DCR_CREG_ADDR,0x00F0
.set JTAG_CREG_ADDR,0x0030
.set JTAG_DREG_ADDR,0x0040
.set CLK_ON_PERIOD,0x0001
.set CLK_OFF_PERIOD,0x0002
.set READ_JTAG_FIFO,0x0004
.set BYPASS,0x0006
.include "intr_handlers.s"
.section .control, "aw"
.globl _start
.p2alignl 2, 0x60000000
_start:
.global sysini_PR
sysini_PR:
# SYSINI INITIALIZATION =======================================================
mfspr r3,DBSR # get DBSR into R3 -- contains
MRR (most recent reset) field in bits [2:3]
mtspr DBDR,r3 # put the value of DBSR into
the DBDR so it can be read by JTAG
# UTLB Invalidation code:
addi r0,r0,0
mtcrf 0xFF,r0 #init condition register with
contents of GPR0 (should be '0')
ba initutlb # branch to initialize UTLB
(not a conditional branch)
initutlb:
addi r5,r0,63 # skipping init utlb entry 0
mtspr CTR,r5
mtmsr r0 # Not enough distance between
the mtctr and the bdnz
nop # Use nops to fill DISS and
PDCD until mtmsr confirms in IWB
nop # mtmsr causes context
synchronization
nop
nop
nop
nop
.p2alignl 4, 0x60000000
addi r5,r0,0x0001 # begin at TLB entry 1 (with
Seamless, entry in UTLB is still boot code)
invalidate_TLB:
tlbwe r0,r5,0 # Set Valid bit (and all
others)=0
addi r5,r5,1 # increment entry number
bc 16,0,invalidate_TLB
###############################################################################
# Setup Initial Boot ROM TLB Entry as cachable
###############################################################################
addi r0,r0,0x0000
mtspr PID,r0 # TID =0x00
mtspr MMUCR,r0
# Set up entry 0 in TLB # Modify to map tlb(0)
addi r3,r0,0x0000 # tlb entry number
addis r4,r0,0xfff0
ori r4,r4,0x0250 # EPN = 'FFF00Xs', V=1(Valid),
TM=0 (Normal mode??), Size=1MB
addis r5,r0,0xfff0
ori r5,r5,0x0000 # RPN = 'FFF00Xs', 6'b0, ERPN
= 4'b0000
addi r6,r0,0x083f # 16'b0, U0-U3=0,
WIMGE=5b'10000, 1'b0, UX/UW/UR/SX/SW/SR = 0x3f (enabled)
bl mttlb
init_GPR:
# Init GPRs
addi r0,r0,0x0000
addi r1,r0,0x0000
addi r2,r0,0x0000
addi r3,r0,0x0000
addi r4,r0,0x0000
addi r5,r0,0x0000
addi r6,r0,0x0000
addi r7,r0,0x0000
addi r8,r0,0x0000
addi r9,r0,0x0000
addi r10,r0,0x0000
addi r11,r0,0x0000
addi r12,r0,0x0000
addi r13,r0,0x0000
addi r14,r0,0x0000
addi r15,r0,0x0000
addi r16,r0,0x0000
addi r17,r0,0x0000
addi r18,r0,0x0000
addi r19,r0,0x0000
addi r20,r0,0x0000
addi r21,r0,0x0000
addi r22,r0,0x0000
addi r23,r0,0x0000
addi r24,r0,0x0000
addi r25,r0,0x0000
addi r26,r0,0x0000
addi r27,r0,0x0000
addi r28,r0,0x0000
addi r29,r0,0x0000
addi r30,r0,0x0000
addi r31,r0,0x0000
mtspr PID,r0 # TID =0x00
mtspr MMUCR,r0
# clear CCR0 but set bits 17:18 (GICBT:GDCBT)
addi r5,r0,0x6000
mtspr CCR0,r5
# Invalidate caches
ICCCI r0,r0
DCCCI r0,r0
# Zero out the Victim registers
mtspr INV0,r0
mtspr INV1,r0
mtspr INV2,r0
mtspr INV3,r0
mtspr ITV0,r0
mtspr ITV1,r0
mtspr ITV2,r0
mtspr ITV3,r0
# Set small D-cache Normal Victim values to max, Leave Transient such that
there is overlap
addis r5,r0,0x3F3F
ori r5,r5,0x3F3F
mtspr DNV0,r5
mtspr DNV1,r5
mtspr DNV2,r5
mtspr DNV3,r5
mtspr DTV0,r0
mtspr DTV1,r0
mtspr DTV2,r0
mtspr DTV3,r0
# Initialize the I-cache Victim Limit registers
addis r5,r0,0x0001 # TOOR (2:9)=0, TCEILING
(13:20) = 63
ori r5,r5,0xf800 # NFLOOR (24:31) = 0
mtspr IVLIM,r5
# Initialize the D-cache Victim Limit registers
addis r5,r0,0x0001 # TOOR (2:9)=0, TCEILING
(13:20) = 63
ori r5,r5,0xf83C # NFLOOR (24:31) = 60
mtspr DVLIM,r5
# initialize ITLB and DTLB
isync
###############################################################################
# Setting IVPR
addis r4,0,address@hidden
mtspr IVPR,r4
# Setting IVOR0 register, interrupt vector for Critical Input
ori r4,r0,address@hidden
mtspr IVOR0,r4
# Setting IVOR1 register, Interrupt vector for Machine Check
ori r4,r0,address@hidden
mtspr IVOR1,r4
# Setting IVOR2 register, Interrupt vector for Data Storage
ori r4,r0,address@hidden
mtspr IVOR2,r4
# Setting IVOR3 register, Interrupt vector for Instruction Storage
ori r4,r0,address@hidden
mtspr IVOR3,r4
# Setting IVOR4 register, Interrupt vector for External Input
ori r4,r0,address@hidden
mtspr IVOR4,r4
# Setting IVOR5 register, Interrupt vector for Alignment
ori r4,r0,address@hidden
mtspr IVOR5,r4
# Setting IVOR6 register, Interrupt vector for Program
ori r4,r0,address@hidden
mtspr IVOR6,r4
# Setting IVOR7 register, Interrupt vector for FP unavailable
ori r4,r0,address@hidden
mtspr IVOR7,r4
# Setting IVOR8 register, Interrupt vector for System Call
ori r4,r0,address@hidden
mtspr IVOR8,r4
# Setting IVOR9 register, Interrupt vector for APU unavailable
ori r4,r0,address@hidden
mtspr IVOR9,r4
# Setting IVOR10 register, Interrupt vector for Decrementer
ori r4,r0,address@hidden
mtspr IVOR10,r4
# Setting IVOR11 register, Interrupt vector for Fixed Interval Timer
ori r4,r0,address@hidden
mtspr IVOR11,r4
# Setting IVOR12 register, Interrupt vector for Watchdog Timer
ori r4,r0,address@hidden
mtspr IVOR12,r4
# Setting IVOR13 register, Interrupt vector for DTLB miss
ori r4,r0,address@hidden
mtspr IVOR13,r4
# Setting IVOR14 register, Interrupt vector for ITLB miss
ori r4,r0,address@hidden
mtspr IVOR14,r4
# Setting IVOR15 register, Interrupt vector for Debug
ori r4,r0,address@hidden
mtspr IVOR15,r4
# Clear CTR to avoid X's on predict w/CTR as condition
mtspr CTR,r0
# clear XER
mtspr XER,r0
mcrxr 0
###############################################################################
# CLEAR OUT GPRs used above =========================================
ZeroRegs:
addi r3,r0,0x0000
addi r4,r0,0x0000
addi r5,r0,0x0000
addi r6,r0,0x0000
# PUNCH IT, CHEWIE ! --------------------------------------------------
ba _testcase_start
nop
nop
###############################################################################
# TLB setup function
###############################################################################
#!-------------------------------------------------------------------------------
#! Function: mttlb
#! Description: write 3 tlb entries
#!
#! MTTLB, entry, ws0_val, ws1_val, ws2_val
#! assumption : pid is already loaded from the STID field
#! of the MMUCR, not from the value of the TLB Word0.
#! the MMUCR must be setup prior to calling this function
#! defaults pid_val =0, mmucr_val=0
#! r3 entry (0-63)
#! r4 ws0_val
#! r5 ws1_val
#! r6 ws2_val
#!
#! Input:
#! Output: none
#!-------------------------------------------------------------------------------
.p2alignl 4, 0x60000000
.global mttlb
mttlb:
tlbwe r4,r3,0 # Write word 0 of TLB Entry
tlbwe r5,r3,1 # Write word 1 of TLB Entry
tlbwe r6,r3,2 # Write word 2 of TLB Entry
bclr 20,0
.size mttlb,.-mttlb
###############################################################################
# Reset vector for PowerPC embedded
###############################################################################
.section .reset_vec, "wa"
.global sys_reset
sys_reset :
nop
nop
nop
ba _start
#.end
## **************************************************************************
##
## Copyright (c) International Business Machines Corporation, 2002.
##
## This file contains trade secrets and other proprietary and confidential
## information of International Business Machines Corporation which are
## protected by copyright and other intellectual property rights and shall
## not be reproduced, transferred to other documents, disclosed to others,
## or used for any purpose except as specifically authorized in writing by
## International Business Machines Corporation. This notice must be
## contained as part of this text at all times.
##
## **************************************************************************
##
## This test verifies that the DCBA instruction is a NOP
##
##**************************************************************************
.file "PPC440.dcba.1.1.4.s" # Change this name to your
test name
.include "sysini.s" # Always include sysini.s
.global _testcase_start # This makes the address of
the code segment globally accessible
.text # This is a text type section
meaning the compiler fills nops for unused space
.p2alignl 4,0x60000000
_testcase_start: # The label that gives the
address for the code segment
#####################
# #
# CODE START #
# #
#####################
xor r0,r0,r0 # Zero r0
mtspr XER,r0 # Set XER to known state
mtcrf 0xff,r0 # Set CR to known state
addis r3,r0,address@hidden # GPR 3 will contain the data segment
address
ori r3,r3,address@hidden # .
addis r4,r0,address@hidden # GPR 4 will contain the code
segment address
ori r4,r4,address@hidden # .
#@& TESTCASE BEGINS:
# In addition to TLB entry 0 set up by Sysini, we need to set up
# TLB entry 2 for non-cacheable access with same RPN but different EPN.
addi r11,r0,0x0002 # set up TLB entry 2
mtspr PID,r0 # Process ID 0
addis r12,r0,0xeff0 # EPN = 'EFFXs', V=1, TS=0,
Size=1MB
ori r12,r12,0x0250 # .
mtspr MMUCR,r0 # clear MMUCR
tlbwe r12,r11,0 # write TLB word 0
addis r12,r0,0xfff0 # RPN = 'FFFXs', 6'b0,
ERPN=4'b0
tlbwe r12,r11,1 # write TLB word 1
addi r12,r0,0x043f # 16'b0, U0-U3=0,
WIMGE=5b'01000, 1'b0, UX/UW/UR/SX/SW/SR = 0x3f (enabled)
tlbwe r12,r11,2 # write TLB word 2
isync # context sync
# Clear the D-Cache
DCCCI 0,0
addis r13,r0,0x0001 # clear bits [26:31] (normal
floor values)
ori r13,r13,0xf800 # of DVLM. This will enable
all 16 of the
mtspr DVLIM,r13 # normal victim counters for
the entire 64
# entries of each DCA element.
# This also sets up the DVLIM reg with the Transient Floor set to 0 and the
# Transient Ceiling set to 63 to allow the entire cache to be used.
# Set up the Normal Victim registers to the incremented values
addis r6,r0,0x0104
ori r6,r6,0x070a
mtspr DNV0,r6
addis r7,r0,0x0d10
ori r7,r7,0x1316
mtspr DNV1,r7
addis r8,r0,0x191c
ori r8,r8,0x1f22
mtspr DNV2,r8
addis r9,r0,0x2528
ori r9,r9,0x2b2e
mtspr DNV3,r9
# 16 load words: each loads a cache line
addi r5,r3,Table1
addi r11,r0,0x0010 # touch 16 lines
mtspr CTR,r11
loop1:
lwz r12,0(r5)
addi r5,r5,0x0020 # point to next line
bc 16,0,loop1 # branch back till counter is
zero
msync
isync
# 16 lines of store words (16x8=128 words) (non-cacheable)
addis r3,r0,0xefff
ori r3,r3,0x0000
addi r5,r3,Table1
addi r10,r3,Table2
addi r11,r0,128 # load decimal 128 into r11
mtspr CTR,r11
loop2:
lwz r12,0(r10)
stw r12,0(r5)
addi r5,r5,0x0004 # point to next word
addi r10,r10,0x0004 # point to next word
bc 16,0,loop2 # branch back till counter is
zero
msync
isync
# Verify data is stored
addi r11,r3,Table1
lwz r12,0(r11) # load and check data
addis r13,r0,0x5010 # expected data
ori r13,r13,0x5010 # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0x2577 # expected data
ori r13,r13,0x2577 # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0x2222 # expected data
ori r13,r13,0x2222 # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0xaaaa # expected data
ori r13,r13,0xaaaa # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0x2211 # expected data
ori r13,r13,0x2211 # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0x1f72 # expected data
ori r13,r13,0x1f72 # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0xcfcf # expected data
ori r13,r13,0xcfcf # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0xfcfc # expected data
ori r13,r13,0xfcfc # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0xbbaa # expected data
ori r13,r13,0xbbaa # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0x99aa # expected data
ori r13,r13,0x99aa # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0x3344 # expected data
ori r13,r13,0x3344 # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0x4499 # expected data
ori r13,r13,0x4499 # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0x1010 # expected data
ori r13,r13,0x1010 # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0x2525 # expected data
ori r13,r13,0x2525 # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0x8888 # expected data
ori r13,r13,0x8888 # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0xbbbb # expected data
ori r13,r13,0xbbbb # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
msync
isync
# Verify correct data is in cache (choose few random locations)
# Check that valid bit is set and no dirty bits are set
addi r11,r0,0x0200 # Bank 0, subbank 0, index 01
msync
DCREAD r13,r0,r11
addis r12,r0,0x3d40
ori r12,r12,0x5010
cmp 0,0,r13,r12 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r15,r0,0x0080
mfspr r14,DCDBTRH
and r14,r14,r15 # filter bit 24
cmpi 0,0,r14,0x0080 # see if the V bit is ON, (bit
24)
bcl 4,2,ERROR # fail if not equal
addi r16,r0,0x00f0
mfspr r17,DCDBTRL
and r17,r17,r16 # filter bits 24-27
cmpi 0,0,r17,0x0000 # see if no dirty bits are set
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x1ea0 # Bank 1, subbank 1, index 10
msync
DCREAD r13,r0,r11
addis r12,r0,0x3d40
ori r12,r12,0x1f72
cmp 0,0,r13,r12 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r15,r0,0x0080
mfspr r14,DCDBTRH
and r14,r14,r15 # filter bit 24
cmpi 0,0,r14,0x0080 # see if the V bit is ON, (bit
24)
bcl 4,2,ERROR # fail if not equal
addi r16,r0,0x00f0
mfspr r17,DCDBTRL
and r17,r17,r16 # filter bits 24-27
cmpi 0,0,r17,0x0000 # see if no dirty bits are set
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x1ea0 # Bank 2, subbank 2, index 1F
msync
DCREAD r13,r0,r11
addis r12,r0,0x3d40
ori r12,r12,0x3344
cmp 0,0,r13,r12 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r15,r0,0x0080
mfspr r14,DCDBTRH
and r14,r14,r15 # filter bit 24
cmpi 0,0,r14,0x0080 # see if the V bit is ON, (bit
24)
bcl 4,2,ERROR # fail if not equal
addi r16,r0,0x00f0
mfspr r17,DCDBTRL
and r17,r17,r16 # filter bits 24-27
cmpi 0,0,r17,0x0000 # see if no dirty bits are set
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x1ea0 # Bank 3, subbank 3, index 2E
msync
DCREAD r13,r0,r11
addis r12,r0,0x3d40
ori r12,r12,0xbbbb
cmp 0,0,r13,r12 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r15,r0,0x0080
mfspr r14,DCDBTRH
and r14,r14,r15 # filter bit 24
cmpi 0,0,r14,0x0080 # see if the V bit is ON, (bit
24)
bcl 4,2,ERROR # fail if not equal
addi r16,r0,0x00f0
mfspr r17,DCDBTRL
and r17,r17,r16 # filter bits 24-27
cmpi 0,0,r17,0x0000 # see if no dirty bits are set
bcl 4,2,ERROR # fail if not equal
# 16 dcba to non-cacheable Hit
addi r5,r3,Table1
addi r11,r0,0x0010
mtspr CTR,r11
loop3:
dcba 0,r5
addi r5,r5,0x0020 # point to next line
bc 16,0,loop3
# 16 dcba to cacheable Hit
addis r3,r0,0xffff
ori r3,r3,0x0000
addi r5,r3,Table1
addi r11,r0,0x0010
mtspr CTR,r11
loop4:
dcba 0,r5
addi r5,r5,0x0020 # point to next line
bc 16,0,loop4
# Verify correct data is still in the cache (choose few random locations)
# Check that valid bit is set and no dirty bits are set
addi r11,r0,0x0200 # Bank 0, subbank 0, index 01
msync
DCREAD r13,r0,r11
addis r12,r0,0x3d40
ori r12,r12,0x5010
cmp 0,0,r13,r12 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r15,r0,0x0080
mfspr r14,DCDBTRH
and r14,r14,r15 # filter bit 24
cmpi 0,0,r14,0x0080 # see if the V bit is ON, (bit
24)
bcl 4,2,ERROR # fail if not equal
addi r16,r0,0x00f0
mfspr r17,DCDBTRL
and r17,r17,r16 # filter bits 24-27
cmpi 0,0,r17,0x0000 # see if no dirty bits are set
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x1ea0 # Bank 1, subbank 1, index 10
msync
DCREAD r13,r0,r11
addis r12,r0,0x3d40
ori r12,r12,0x1f72
cmp 0,0,r13,r12 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r15,r0,0x0080
mfspr r14,DCDBTRH
and r14,r14,r15 # filter bit 24
cmpi 0,0,r14,0x0080 # see if the V bit is ON, (bit
24)
bcl 4,2,ERROR # fail if not equal
addi r16,r0,0x00f0
mfspr r17,DCDBTRL
and r17,r17,r16 # filter bits 24-27
cmpi 0,0,r17,0x0000 # see if no dirty bits are set
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x1ea0 # Bank 2, subbank 2, index 1F
msync
DCREAD r13,r0,r11
addis r12,r0,0x3d40
ori r12,r12,0x3344
cmp 0,0,r13,r12 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r15,r0,0x0080
mfspr r14,DCDBTRH
and r14,r14,r15 # filter bit 24
cmpi 0,0,r14,0x0080 # see if the V bit is ON, (bit
24)
bcl 4,2,ERROR # fail if not equal
addi r16,r0,0x00f0
mfspr r17,DCDBTRL
and r17,r17,r16 # filter bits 24-27
cmpi 0,0,r17,0x0000 # see if no dirty bits are set
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x1ea0 # Bank 3, subbank 3, index 2E
msync
DCREAD r13,r0,r11
addis r12,r0,0x3d40
ori r12,r12,0xbbbb
cmp 0,0,r13,r12 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r15,r0,0x0080
mfspr r14,DCDBTRH
and r14,r14,r15 # filter bit 24
cmpi 0,0,r14,0x0080 # see if the V bit is ON, (bit
24)
bcl 4,2,ERROR # fail if not equal
addi r16,r0,0x00f0
mfspr r17,DCDBTRL
and r17,r17,r16 # filter bits 24-27
cmpi 0,0,r17,0x0000 # see if no dirty bits are set
bcl 4,2,ERROR # fail if not equal
# 16 lines of load word (non-cacheable)
# Verify data is loaded
addis r3,r0,0xefff
ori r3,r3,0x0000
addi r11,r3,Table1
lwz r12,0(r11) # load and check data
addis r13,r0,0x5010 # expected data
ori r13,r13,0x5010 # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0x2577 # expected data
ori r13,r13,0x2577 # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0x2222 # expected data
ori r13,r13,0x2222 # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0xaaaa # expected data
ori r13,r13,0xaaaa # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0x2211 # expected data
ori r13,r13,0x2211 # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0x1f72 # expected data
ori r13,r13,0x1f72 # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0xcfcf # expected data
ori r13,r13,0xcfcf # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0xfcfc # expected data
ori r13,r13,0xfcfc # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0xbbaa # expected data
ori r13,r13,0xbbaa # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0x99aa # expected data
ori r13,r13,0x99aa # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0x3344 # expected data
ori r13,r13,0x3344 # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0x4499 # expected data
ori r13,r13,0x4499 # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0x1010 # expected data
ori r13,r13,0x1010 # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0x2525 # expected data
ori r13,r13,0x2525 # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0x8888 # expected data
ori r13,r13,0x8888 # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x0020 # point to next line
lwz r12,0(r11) # load and check data
addis r13,r0,0xbbbb # expected data
ori r13,r13,0xbbbb # .
cmp 0,0,r12,r13 # Are they equal?
bcl 4,2,ERROR # fail if not equal
msync
isync
# Clear the D-Cache
DCCCI 0,0
# Set up the Normal Victim registers to the incremented values
addis r6,r0,0x0104
ori r6,r6,0x070a
mtspr DNV0,r6
addis r7,r0,0x0d10
ori r7,r7,0x1316
mtspr DNV1,r7
addis r8,r0,0x191c
ori r8,r8,0x1f22
mtspr DNV2,r8
addis r9,r0,0x2528
ori r9,r9,0x2b2e
mtspr DNV3,r9
# 16 dcba to cacheable miss
addis r3,r0,0xffff
ori r3,r3,0x0000
addi r5,r3,Table2
addi r11,r0,0x0010
mtspr CTR,r11
loop5:
dcba 0,r5
addi r5,r5,0x0020 # point to next line
bc 16,0,loop5
# 16 dcba to non-cacheable miss
addis r3,r0,0xefff
ori r3,r3,0x0000
addi r5,r3,Table2
addi r11,r0,0x0010
mtspr CTR,r11
loop6:
dcba 0,r5
addi r5,r5,0x0020 # point to next line
bc 16,0,loop6
# Verify the Valid bit is reset for each line
addi r11,r0,0x0200 # Bank 0, subbank 0, index 01
msync
DCREAD r13,r0,r11
nop
nop
nop
nop
nop
nop
nop
addis r15,r0,0xffff
ori r15,r15,0xff7f
mfspr r14,DCDBTRH
or r14,r14,r15 # filter bit 24
cmp 0,0,r14,r15 # see if the V bit is OFF,
(bit 24)
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x1ea0 # Bank 1, subbank 1, index 10
msync
DCREAD r13,r0,r11
nop
nop
nop
nop
nop
nop
nop
addis r15,r0,0xffff
ori r15,r15,0xff7f
mfspr r14,DCDBTRH
or r14,r14,r15 # filter bit 24
cmp 0,0,r14,r15 # see if the V bit is OFF,
(bit 24)
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x1ea0 # Bank 2, subbank 2, index 1F
msync
DCREAD r13,r0,r11
nop
nop
nop
nop
nop
nop
nop
addis r15,r0,0xffff
ori r15,r15,0xff7f
mfspr r14,DCDBTRH
or r14,r14,r15 # filter bit 24
cmp 0,0,r14,r15 # see if the V bit is OFF,
(bit 24)
bcl 4,2,ERROR # fail if not equal
addi r11,r11,0x1ea0 # Bank 3, subbank 3, index 2E
msync
DCREAD r13,r0,r11
nop
nop
nop
nop
nop
nop
nop
addis r15,r0,0xffff
ori r15,r15,0xff7f
mfspr r14,DCDBTRH
or r14,r14,r15 # filter bit 24
cmp 0,0,r14,r15 # see if the V bit is OFF,
(bit 24)
bcl 4,2,ERROR # fail if not equal
# ***** End of test ******
EPILOG
#------------------------------------------------------------------------------#
# Data Area... #
#------------------------------------------------------------------------------#
.data
.global PPC440.dcba.1.1.4_data_RW
PPC440.dcba.1.1.4_data_RW:
# data area
#==============================================================================#
# Random data for the test #
#==============================================================================#
Table1.d:
# first line:
.long 0x3D405010, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 2-nd line:
.long 0x3D402577, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 3-rd line:
.long 0x3D402222, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 4-th line:
.long 0x3D40aaaa, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 5-th line:
.long 0x3D402211, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 6-th line:
.long 0x3D401f72, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 7-th line:
.long 0x3D40cfcf, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 8-th line:
.long 0x3D40fcfc, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 9-th line:
.long 0x3D40bbaa, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 10-th line:
.long 0x3D4099aa, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 11-th line:
.long 0x3D403344, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 12-th line:
.long 0x3D404499, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 13-th line:
.long 0x3D401010, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 14-th line:
.long 0x3D402525, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 15-th line:
.long 0x3D408888, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 16-th line:
.long 0x3D40bbbb, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
Table2.d:
# first line:
.long 0x50105010, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 2-nd line:
.long 0x25772577, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 3-rd line:
.long 0x22222222, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 4-th line:
.long 0xaaaaaaaa, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 5-th line:
.long 0x22112211, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 6-th line:
.long 0x1f721f72, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 7-th line:
.long 0xcfcfcfcf, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 8-th line:
.long 0xfcfcfcfc, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 9-th line:
.long 0xbbaabbaa, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 10-th line:
.long 0x99aa99aa, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 11-th line:
.long 0x33443344, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 12-th line:
.long 0x44994499, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 13-th line:
.long 0x10101010, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 14-th line:
.long 0x25252525, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 15-th line:
.long 0x88888888, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
# 16-th line:
.long 0xbbbbbbbb, 0x60000000, 0x60000000, 0x60000000
.long 0x60000000, 0x60000000, 0x60000000, 0x4e800020
#Generate offsets for data
.set Table1,Table1.d-PPC440.dcba.1.1.4_data_RW
.set Table2,Table2.d-PPC440.dcba.1.1.4_data_RW
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