[Bug binutils/19921] enable specification of data width when writing verilog hex format

[donatokava at gmail dot com]

https://sourceware.org/bugzilla/show_bug.cgi?id=19921

Donato Kava <donatokava at gmail dot com> changed:

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                 CC|                            |donatokava at gmail dot com

--- Comment #9 from Donato Kava <donatokava at gmail dot com> ---
Adding a comment here to ask if someone could actually work on this bug. 
I reported it on the RISC-V tools github here.

https://github.com/riscv/riscv-tools/issues/168#issuecomment-358165027

When I first reported it was assumed it would have been fixed and pushed
upstream by now. Apparently we were wrong and now someone else also wants the
same functionality and  found my original report. 

Can someone please fix this? This functionality is useful for bare metal RISC-V
Verilog processors.

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