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[Bug binutils/19921] enable specification of data width when writing ver
From: |
jamey.hicks at gmail dot com |
Subject: |
[Bug binutils/19921] enable specification of data width when writing verilog hex format |
Date: |
Tue, 14 May 2019 12:19:52 +0000 |
https://sourceware.org/bugzilla/show_bug.cgi?id=19921
--- Comment #12 from Jamey Hicks <jamey.hicks at gmail dot com> ---
Thank you, Nick!
On Tue, May 14, 2019 at 5:51 AM nickc at redhat dot com <
address@hidden> wrote:
> https://sourceware.org/bugzilla/show_bug.cgi?id=19921
>
> Nick Clifton <nickc at redhat dot com> changed:
>
> What |Removed |Added
>
> ----------------------------------------------------------------------------
> Status|NEW |RESOLVED
> Resolution|--- |FIXED
>
> --- Comment #11 from Nick Clifton <nickc at redhat dot com> ---
> (In reply to Donato Kava from comment #9)
> > Adding a comment here to ask if someone could actually work on this bug.
>
> Well nobody else seems to want to fix the testsuite problems, so I have
> gone ahead and done so myself. A little bit of code tidying as well,
> and the patch is now in.
>
> Cheers
> Nick
>
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