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Re: [Discuss-gnuradio] USRP Rev4 FX2 firmware question. InitializingFIF


From: Jeff Brower
Subject: Re: [Discuss-gnuradio] USRP Rev4 FX2 firmware question. InitializingFIFOs ?
Date: Sat, 21 Mar 2009 03:27:55 -0600 (CST)
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Ryan-

> I have been working on modifications to the USRP board so that I can pass
> a gating signal through the basic RX daughterboard to gate signal
> collection for a pulsed radar application. This is somewhat working, but I
> am having problems with data alignment when stopping and starting the
> system. It appears that the FX2 chip does not clear its fifo when
> stopping/starting the system. There seems to be an arbitrary number of
> data samples left in the buffers when I restart the system, and this
> causes sample 0 to appear at sample X. Is there a function I can call to
> manually wipe the FX2 fifos and ensure that they are empty when starting
> the system? If not, what do I need to do to resolve this; possibly
> customize the firmware (this looks like a headache)?
>
> The FPGA modifications appear to work as expected. These buffers are
> definitely zeroed upon restart. I have verified most of this by routing
> important signals through the headers on the dboards to a logic analyzer.
> Everything looks pretty good from the FPGA's perspective.

In DSP based radar related systems I've worked on, gating typically occurs as 
close as possible to the data acq side,
rather than close to the CPU or intermediate data transfer circuitry.  Can't 
you zero ADC input inside the FPGA on the
alignment that you need and basically let the system "push zeros" during the 
off time?  Or some way that avoids
stopping/starting the USB chip?  Once you stop/start the USB chip I would think 
there are driver issues to worry about
also -- and if you migrate to USRP2, then same thing, except with the GbE PHY.

Maybe I mis-understand your objectives; one reason for a full system stop would 
be power consumption.  Is that an issue?

-Jeff





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