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From: | 周亮 |
Subject: | [Discuss-gnuradio] problem of compiling FPGA bin files. |
Date: | Tue, 1 Dec 2009 21:36:53 +0800 |
Hi, I tried to use Xilinx ISE 11.1 to open project "usrp2/fpga/top/u2_fpga/u2_fpga.ise".There are some files missing,such as"fifo_generator_4_1.v" . And there are errors when implement design... ============================================== ERROR:ConstraintSystem:59 - Constraint <NET "adc_a[0]" LOC = "A14" ;> [u2_fpga.ucf(1)]: NET "adc_a[0]" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ... ERROR:ConstraintSystem:59 - Constraint <NET "clk_muxed" TNM_NET = "clk_muxed";> [u2_fpga.ucf(216)]: NET "clk_muxed" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ... ERROR:ConstraintSystem:59 - Constraint <NET "ser_t<15>" IOSTANDARD = LVCMOS25 |> [u2_fpga.ucf(336)]: NET "ser_t<15>" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ... ERROR:ConstraintSystem:59 - Constraint <DRIVE = 12 |> [u2_fpga.ucf(336)]: NET "ser_t<15>" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ... ERROR:ConstraintSystem:59 - Constraint <SLEW = FAST ;> [u2_fpga.ucf(336)]: NET "ser_t<15>" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ========================================= How could I fix it?? Thanks! Liang 使用Messenger保护盾2.0,支持多账号登录! 现在就下载! |
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