[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: sym to verilog-ams
From: |
karl |
Subject: |
Re: sym to verilog-ams |
Date: |
Tue, 5 Apr 2022 17:15:56 +0200 (CEST) |
Karl:
> Al Davis:
> > On Sun, 3 Apr 2022 13:14:57 +0200 (CEST)
> > karl@aspodata.se wrote:
> > > Can one have mult. identical modules or must a converter output
> > > just one ?
> >
> > Officially, yes, but you need to provide some way to select which one
> > you want. This is commonly done to implement things like "binning" and
> > the "level" parameter.
> >
> > One way to select is `ifdef . I won't discuss this one further because
> > it is familiar to everyone.
> ...
>
> I think I prefer the `ifdef version since that would work out of the
> box.
By second thought, the same thing is needed for sch files also.
Regards,
/Karl Hammar
- Re: sym to verilog-ams, (continued)
Re: sym to verilog-ams, al davis, 2022/04/04
Re: sym to verilog-ams, al davis, 2022/04/04
- Re: sym to verilog-ams, karl, 2022/04/05
- Re: sym to verilog-ams,
karl <=
- attributes, possible interface, Felix Salfelder, 2022/04/18
- Re: attributes, possible interface, al davis, 2022/04/18
- Re: attributes, possible interface, Felix Salfelder, 2022/04/19
- Re: attributes, possible interface, al davis, 2022/04/19
- Re: attributes, possible interface, Felix Salfelder, 2022/04/20
- Re: attributes, possible interface, correction, Felix Salfelder, 2022/04/20