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[Guile-commits] 256/437: X86: %r12 may be used as an index register.
From: |
Andy Wingo |
Subject: |
[Guile-commits] 256/437: X86: %r12 may be used as an index register. |
Date: |
Mon, 2 Jul 2018 05:14:32 -0400 (EDT) |
wingo pushed a commit to branch lightning
in repository guile.
commit 1bd169cfa34d1ec3a956e6656dbe1179dac6815f
Author: pcpa <address@hidden>
Date: Mon Sep 30 13:30:21 2013 -0300
X86: %r12 may be used as an index register.
* lib/jit_x86-cpu.c: Correct not properly tested case of using
%r12 as index register, what was causing an invalid assertion.
%r12 is mapped to the "extra" JIT_R3 register, and test cases
only test "standard" lightning registers.
---
ChangeLog | 7 +++++++
lib/jit_x86-cpu.c | 3 ++-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/ChangeLog b/ChangeLog
index 80e14b3..60851b3 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,10 @@
+2013-10-30 Paulo Andrade <address@hidden>
+
+ * lib/jit_x86-cpu.c: Correct not properly tested case of using
+ %r12 as index register, what was causing an invalid assertion.
+ %r12 is mapped to the "extra" JIT_R3 register, and test cases
+ only test "standard" lightning registers.
+
2013-10-28 Paulo Andrade <address@hidden>
* lib/jit_ia64.c: Minor change to force collecting the maximum
diff --git a/lib/jit_x86-cpu.c b/lib/jit_x86-cpu.c
index afc83d2..4cf16c1 100644
--- a/lib/jit_x86-cpu.c
+++ b/lib/jit_x86-cpu.c
@@ -61,6 +61,7 @@
# define _R14_REGNO 14
# define _R15_REGNO 15
# define r7(reg) (reg & 7)
+# define r8(reg) (reg & 15)
# define _SCL1 0x00
# define _SCL2 0x01
# define _SCL4 0x02
@@ -701,7 +702,7 @@ _rx(jit_state_t *_jit, jit_int32_t rd, jit_int32_t md,
sib(ms, r7(ri), 0x05);
ii(md);
}
- else if (r7(ri) != _RSP_REGNO) {
+ else if (r8(ri) != _RSP_REGNO) {
if (md == 0 && r7(rb) != _RBP_REGNO) {
mrm(0x00, r7(rd), 0x04);
sib(ms, r7(ri), r7(rb));
- [Guile-commits] 221/437: Correct build and pass all tests on Solaris Sparc., (continued)
- [Guile-commits] 221/437: Correct build and pass all tests on Solaris Sparc., Andy Wingo, 2018/07/02
- [Guile-commits] 228/437: Properly check tests output., Andy Wingo, 2018/07/02
- [Guile-commits] 186/437: Add code to release all memory used by the jit state., Andy Wingo, 2018/07/02
- [Guile-commits] 137/437: Make mips backend compile on a qemu image., Andy Wingo, 2018/07/02
- [Guile-commits] 222/437: Correct build and pass all tests on Solaris x86., Andy Wingo, 2018/07/02
- [Guile-commits] 219/437: Remove redundancy in the hppa cache synchronization code., Andy Wingo, 2018/07/02
- [Guile-commits] 245/437: S390X: Correct values of float registers saved on stack., Andy Wingo, 2018/07/02
- [Guile-commits] 224/437: Correct mips o32 abi that was broken when adding n32 abi support., Andy Wingo, 2018/07/02
- [Guile-commits] 230/437: New s390x port built on the hercules emulator and fedora 16 image., Andy Wingo, 2018/07/02
- [Guile-commits] 234/437: GNU lightning 2.0.0 release, Andy Wingo, 2018/07/02
- [Guile-commits] 256/437: X86: %r12 may be used as an index register.,
Andy Wingo <=
- [Guile-commits] 229/437: Do not assume cast of nan or inf double to float always work., Andy Wingo, 2018/07/02
- [Guile-commits] 231/437: Cosmetic removal of white spaces in end of lines., Andy Wingo, 2018/07/02
- [Guile-commits] 232/437: Correct off by one bug on s390x subi., Andy Wingo, 2018/07/02
- [Guile-commits] 123/437: Revert change aliasing jit_movi_p to jit_movi_ul., Andy Wingo, 2018/07/02
- [Guile-commits] 248/437: Correct wrong example and mt unsafe code in the arm backend., Andy Wingo, 2018/07/02
- [Guile-commits] 236/437: Correct build and make check on gcc111 - AIX 7.1., Andy Wingo, 2018/07/02
- [Guile-commits] 237/437: Correct build and check on NetBSD amd64., Andy Wingo, 2018/07/02
- [Guile-commits] 213/437: Finish Itanium port, correcting remaining failing test cases., Andy Wingo, 2018/07/02
- [Guile-commits] 253/437: IA64: Correct some wrong checks value range checks., Andy Wingo, 2018/07/02
- [Guile-commits] 254/437: ARM: Correct build when disassembler is disabled., Andy Wingo, 2018/07/02