Re: Dependencies of dependencies across make implementations.

[Philip Guenther]

On Sat, May 23, 2009 at 12:49 PM, sarah fox <address@hidden> wrote:
> $ cat Makefile
>
> all: file
>
> file.c: file.h
>        @:
...
> The theory is that editing file.h will cause file.c to be recompiled due to 
> the
> dependency chain file.o -> file.c -> file.h.
...
> GNU make does not:
>
> $ make
> cc -o file.o -c file.c
> cc -o file file.o
> $ touch file.h
> $ make
> $
>
> Is there a method to make GNU make behave "correctly" without
> introducing GNU make specific syntax?

What problem are you trying to solve?

Do the contents of file.c *really* depend on file.h?  I.e., if file.h
changes, do you actually have to regenerate file.c based on the new
file.h?  If the answer is "yes", then you need to fix the "file.c:
file.h" rule so that it actually updates file.c.  Once you do that,
it'll work just fine.

However, it's more likely that the answer is "no, but file.c #includes
file.h".  If file.c doesn't really depend on file.h, then don't lie**
to make!  If file.c #includes file.h, then the *real* dependency is
"file.o: file.h".  Delete your incorrect "file.c: file.h" rule
completely and simply declare the correct dependency, either by this:

# no commands here!
file.o: file.h

OR by editing the existing file.o:file.c rule like this:

file.o: file.c file.h
       cc -o file.o -c file.c


...and then go back and look at a few existing makefiles to learn how
to use automatic variables and built-in rules to simplify things.


Philip Guenther


** don't worry, programs don't feel badly about being lied to; their
revenge will be perfectly emotionless, as they do exactly what you
tell them to...