How to recompile only the changed files

[Kevin]

Hi, 

I have a question on how to recompile the changed files only without compiling the untouched ones.

The
following is a "Makefile" that works well in Cygwin. The only thing is
it re-compiles everything when I typed in "make", even I didn't change
anything in SOURCES.

My question is how to avoid recompiling the whole project. Maybe it needs only a simple correction, but what it is?

I am still new to GNU make, and I am not sure where the problem is, so I paste the whole Makefile here. Two included files are also attached.

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>

include Makefile.lwip
include Makefile.adapter

COMPILER=powerpc-eabi-gcc
ARCHIVER=powerpc-eabi-ar
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=

RELEASEDIR=../../../lib
INCLUDEDIR=../../xapp1026__working/raw/ml403/ppc405_0/include

INCLUDES=-I${INCLUDEDIR} -I$(LWIP_DIR)/src/include -I$(LWIP_DIR)/src/include/ipv4 -I$(PORT)/include

OUTPUT_DIR = $(CURDIR)
SOURCES = $(LWIP_SRCS) $(ADAPTER_SRCS)

EXPORT_INCLUDE_FILES =  $(LWIP_DIR)/src/include/ipv4/lwip \

            $(LWIP_DIR)/src/include/lwip \
            $(LWIP_DIR)/src/include/netif \
            contrib/ports/xilinx/include/netif \
            contrib/ports/xilinx/include/arch \
            contrib/ports/xilinx/include/lwipopts.h

MAKEFILE_DEPEND= ./Makefile ./Makefile.lwip ./Makefile.adapter               
DEPENDS = $(SOURCES:%.c=$(OUTPUT_DIR)/depend/%.d)


libs: liblwip4.a
    
clean:
    @echo "clean target for lwip"

    -rm -rf obj

liblwip4.a: obj_dir print_msg_lwip_base $(LWIP_OBJS) print_msg_lwip_adapter $(ADAPTER_OBJS)
#liblwip4.a: $(DEPENDS) print_msg_lwip_base print_msg_lwip_adapter 
    @echo "Creating archive $@"

    $(ARCHIVER) rc $@ obj/*.o

obj_dir:
    @if [ ! -d "obj" ] ;    \
    then  \
      mkdir -p obj; \
    fi
    
print_msg_lwip_base:
    @echo "Compiling lwIP with $(GCC_COMPILER)"

print_msg_lwip_adapter:
    @echo "Compiling lwIP adapter for Xilinx MAC:"

.c.o:
    @echo "Compiling $<"
    $(GCC_COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) -c $< -o obj/$(@F)


$(OUTPUT_DIR)/objs/%.o : %.c  $(MAKEFILE_DEPEND)
    @echo "Compiling: " $<
    @if [ ! -d "$(OUTPUT_DIR)/objs" ] ;    \
    then  \
      mkdir -p $(OUTPUT_DIR)/objs; \
    fi

    @$(GCC_COMPILER) -c $(CFLAGS) $< $(INCLUDES) -o $@

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Thank you very much!

Regards,
Kevin

Makefile.lwip
Description: Binary data

Makefile.adapter
Description: Binary data