Re: How to recompile only the changed files

[Philip Guenther]

[Quoted from direct email with permission]

On Sat, Jun 20, 2009 at 8:32 AM, Kevin <address@hidden> wrote:
> I change the rule as this:
>
> $(OUTPUT_DIR)/obj/%.o : %.c
>     @echo "Compiling: " $<
>     @powerpc-eabi-gcc $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) 
> -c $< -o $@
>
> But make complains:
>
> Compiling lwIP with powerpc-eabi-gcc
> make: gcc: Command not found
>
> I use "powerpc-eabi-gcc", why make looks for "gcc" ? Is this something 
> related to "$(OUTPUT_DIR)/obj/%.o : %.c" vs. ".c.o"?
> What's the differences between these two?

The problem is that you still have some places in your Makefile where
you tell 'make' one thing but then do another.  For example, your
original Makefiles set variables that grind down to something like
these:
----
LWIP_DIR = lwip-1.3.0
LWIP_SRCS = $(LWIP_DIR)/src/core/init.c \
                        $(LWIP_DIR)/more/files/here/etc
...
LWIP_OBJS = $(LWIP_SRCS:%.c=%.o)
----

Okay, so LWIP_OBJS contains paths that are below lwip-1.3.0/ and *NOT*
below obj/

Then:
----
liblwip4.a: obj_dir print_msg_lwip_base $(LWIP_OBJS)
print_msg_lwip_adapter $(ADAPTER_OBJS)
        @echo "Creating archive $@"
        $(ARCHIVER) rc $@ obj/*.o
----

That says to make, "liblwip4.a is built from
lwip-1.3.0/src/core/init.o and a bunch of other files below
lwip-1.3.0/", but that's NOT TRUE!  It's *really* built from
obj/init.o and similar paths below obj/

So, fix your LWIP_OBJS definition so that it actually contains the
correct paths.  For example, this might work for LWIP_OBJS:
  LWIP_OBJS = $(addprefix obj/,$(notdir $(LWIP_SRCS)))

but stop and read each command and variable assignment carefully and
think about what it contains.


Now, about your question about why make didn't find the rule that you
had written.  The answer should be obvious now: it wasn't looking for
it.  You told make to build lwip-1.3.0/src/core/init.o, so it looked
for a rule to do that.  Your new, corrected rule, is for object files
under obj/, so it obviously doesn't apply, so make eventually fell
back to the built-in rule for building .o files from .c files, which
uses $(CC) as the compiler.  Make sense?


Philip Guenther