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[PATCH 59/62] target/arm: Fix fault reporting in get_phys_addr_lpae
From: |
Richard Henderson |
Subject: |
[PATCH 59/62] target/arm: Fix fault reporting in get_phys_addr_lpae |
Date: |
Sun, 3 Jul 2022 13:54:16 +0530 |
Always overriding fi->type was incorrect, as we would not
properly propagate the fault type from S1_ptw_translate,
or arm_ldq_ptw. Simplify things by providing a new label
for reporting a translation fault. For other faults, store
into fi directly.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/ptw.c | 31 +++++++++++++------------------
1 file changed, 13 insertions(+), 18 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index a3f063e0bc..678ad2ac0c 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1012,8 +1012,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t
address,
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
{
ARMCPU *cpu = env_archcpu(env);
- /* Read an LPAE long-descriptor translation table. */
- ARMFaultType fault_type = ARMFault_Translation;
uint32_t level;
ARMVAParameters param;
uint64_t ttbr;
@@ -1051,8 +1049,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t
address,
* so our choice is to always raise the fault.
*/
if (param.tsz_oob) {
- fault_type = ARMFault_Translation;
- goto do_fault;
+ goto do_translation_fault;
}
addrsize = 64 - 8 * param.tbi;
@@ -1089,8 +1086,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t
address,
addrsize - inputsize);
if (-top_bits != param.select) {
/* The gap between the two regions is a Translation fault */
- fault_type = ARMFault_Translation;
- goto do_fault;
+ goto do_translation_fault;
}
}
@@ -1122,7 +1118,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t
address,
* Translation table walk disabled => Translation fault on TLB miss
* Note: This is always 0 on 64-bit EL2 and EL3.
*/
- goto do_fault;
+ goto do_translation_fault;
}
if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) {
@@ -1153,8 +1149,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t
address,
if (param.ds && stride == 9 && sl2) {
if (sl0 != 0) {
level = 0;
- fault_type = ARMFault_Translation;
- goto do_fault;
+ goto do_translation_fault;
}
startlevel = -1;
} else if (!aarch64 || stride == 9) {
@@ -1173,8 +1168,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t
address,
ok = check_s2_mmu_setup(cpu, aarch64, startlevel,
inputsize, stride, outputsize);
if (!ok) {
- fault_type = ARMFault_Translation;
- goto do_fault;
+ goto do_translation_fault;
}
level = startlevel;
}
@@ -1196,7 +1190,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t
address,
descaddr |= extract64(ttbr, 2, 4) << 48;
} else if (descaddr >> outputsize) {
level = 0;
- fault_type = ARMFault_AddressSize;
+ fi->type = ARMFault_AddressSize;
goto do_fault;
}
@@ -1246,7 +1240,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t
address,
if (!(descriptor & 1) || (!(descriptor & 2) && (level == 3))) {
/* Invalid, or the Reserved level 3 encoding */
- goto do_fault;
+ goto do_translation_fault;
}
descaddr = descriptor & descaddrmask;
@@ -1264,7 +1258,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t
address,
descaddr |= extract64(descriptor, 12, 4) << 48;
}
} else if (descaddr >> outputsize) {
- fault_type = ARMFault_AddressSize;
+ fi->type = ARMFault_AddressSize;
goto do_fault;
}
@@ -1321,9 +1315,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t
address,
* Here descaddr is the final physical address, and attributes
* are all in attrs.
*/
- fault_type = ARMFault_AccessFlag;
if ((attrs & (1 << 8)) == 0) {
/* Access flag */
+ fi->type = ARMFault_AccessFlag;
goto do_fault;
}
@@ -1340,8 +1334,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t
address,
result->prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
}
- fault_type = ARMFault_Permission;
if (!(result->prot & (1 << access_type))) {
+ fi->type = ARMFault_Permission;
goto do_fault;
}
@@ -1385,8 +1379,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t
address,
result->page_size = page_size;
return false;
-do_fault:
- fi->type = fault_type;
+ do_translation_fault:
+ fi->type = ARMFault_Translation;
+ do_fault:
fi->level = level;
/* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2. */
fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_Stage2 ||
--
2.34.1
- [PATCH 49/62] target/arm: Use bool consistently for get_phys_addr subroutines, (continued)
- [PATCH 49/62] target/arm: Use bool consistently for get_phys_addr subroutines, Richard Henderson, 2022/07/03
- [PATCH 50/62] target/arm: Only use ARMMMUIdx_Stage1* for two-stage translation, Richard Henderson, 2022/07/03
- [PATCH 51/62] target/arm: Add ptw_idx argument to S1_ptw_translate, Richard Henderson, 2022/07/03
- [PATCH 53/62] target/arm: Extract HA and HD in aa64_va_parameters, Richard Henderson, 2022/07/03
- [PATCH 52/62] target/arm: Add isar predicates for FEAT_HAFDBS, Richard Henderson, 2022/07/03
- [PATCH 54/62] target/arm: Split out S1TranslateResult type, Richard Henderson, 2022/07/03
- [PATCH 55/62] target/arm: Move be test for regime into S1TranslateResult, Richard Henderson, 2022/07/03
- [PATCH 56/62] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw, Richard Henderson, 2022/07/03
- [PATCH 57/62] target/arm: Add ARMFault_UnsuppAtomicUpdate, Richard Henderson, 2022/07/03
- [PATCH 58/62] target/arm: Remove loop from get_phys_addr_lpae, Richard Henderson, 2022/07/03
- [PATCH 59/62] target/arm: Fix fault reporting in get_phys_addr_lpae,
Richard Henderson <=
- [PATCH 61/62] target/arm: Consider GP an attribute in get_phys_addr_lpae, Richard Henderson, 2022/07/03
- [PATCH 60/62] target/arm: Don't shift attrs in get_phys_addr_lpae, Richard Henderson, 2022/07/03
- [PATCH 62/62] target/arm: Implement FEAT_HAFDBS, Richard Henderson, 2022/07/03
- Re: [PATCH 00/62] target/arm: Implement FEAT_HAFDBS, Peter Maydell, 2022/07/04