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[PULL 09/20] target/arm: Don't corrupt high half of PMOVSR when cycle co
From: |
Richard Henderson |
Subject: |
[PULL 09/20] target/arm: Don't corrupt high half of PMOVSR when cycle counter overflows |
Date: |
Wed, 14 Sep 2022 12:52:06 +0100 |
From: Peter Maydell <peter.maydell@linaro.org>
When the cycle counter overflows, we are intended to set bit 31 in PMOVSR
to indicate this. However a missing ULL suffix means that we end up
setting all of bits 63-31. Fix the bug.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220822132358.3524971-2-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 7ff03f1a4b..e4824e01b8 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1186,7 +1186,7 @@ static void pmccntr_op_start(CPUARMState *env)
uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \
1ull << 63 : 1ull << 31;
if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) {
- env->cp15.c9_pmovsr |= (1 << 31);
+ env->cp15.c9_pmovsr |= (1ULL << 31);
pmu_update_irq(env);
}
--
2.34.1
- [PULL 06/20] target/arm: Implement ID_DFR1, (continued)
- [PULL 06/20] target/arm: Implement ID_DFR1, Richard Henderson, 2022/09/14
- [PULL 08/20] target/arm: Add missing space in comment, Richard Henderson, 2022/09/14
- [PULL 13/20] target/arm: Honour MDCR_EL2.HPMD in Secure EL2, Richard Henderson, 2022/09/14
- [PULL 12/20] target/arm: Ignore PMCR.D when PMCR.LC is set, Richard Henderson, 2022/09/14
- [PULL 16/20] target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits, Richard Henderson, 2022/09/14
- [PULL 14/20] target/arm: Detect overflow when calculating next PMU interrupt, Richard Henderson, 2022/09/14
- [PULL 15/20] target/arm: Rename pmu_8_n feature test functions, Richard Henderson, 2022/09/14
- [PULL 17/20] target/arm: Support 64-bit event counters for FEAT_PMUv3p5, Richard Henderson, 2022/09/14
- [PULL 07/20] target/arm: Advertise FEAT_ETS for '-cpu max', Richard Henderson, 2022/09/14
- [PULL 20/20] target/arm: Make boards pass base address to armv7m_load_kernel(), Richard Henderson, 2022/09/14
- [PULL 09/20] target/arm: Don't corrupt high half of PMOVSR when cycle counter overflows,
Richard Henderson <=
- [PULL 18/20] target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max', Richard Henderson, 2022/09/14
- [PULL 11/20] target/arm: Don't mishandle count when enabling or disabling PMU counters, Richard Henderson, 2022/09/14
- [PULL 10/20] target/arm: Correct value returned by pmu_counter_mask(), Richard Henderson, 2022/09/14
- [PULL 19/20] target/arm: Remove useless TARGET_BIG_ENDIAN check in armv7m_load_kernel(), Richard Henderson, 2022/09/14
- Re: [PULL 00/20] target-arm.next patch queue, Stefan Hajnoczi, 2022/09/17