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Re: [PATCH 07/14] target/arm: Honour SDCR.TDCC and SCR.TERR in AArch32 E
From: |
Alex Bennée |
Subject: |
Re: [PATCH 07/14] target/arm: Honour SDCR.TDCC and SCR.TERR in AArch32 EL3 non-Monitor modes |
Date: |
Wed, 05 Feb 2025 14:40:47 +0000 |
User-agent: |
mu4e 1.12.8; emacs 29.4 |
Peter Maydell <peter.maydell@linaro.org> writes:
> There are not many traps in AArch32 which should trap to Monitor
> mode, but these trap bits should trap not just lower ELs to Monitor
> mode but also the non-Monitor modes running at EL3 (i.e. Secure
> System, Secure Undef, etc).
>
> We get this wrong because the relevant access functions implement the
> AArch64-style logic of
> if (el < 3 && trap_bit_set) {
> return CP_ACCESS_TRAP_EL3;
> }
> which won't trap the non-Monitor modes at EL3.
>
> Correct this error by using arm_is_el3_or_mon() instead, which
> returns true when the CPU is at AArch64 EL3 or AArch32 Monitor mode.
> (Since the new callsites are compiled also for the linux-user mode,
> we need to provide a dummy implementation for CONFIG_USER_ONLY.)
>
> This affects only:
> * trapping of ERRIDR via SCR.TERR
> * trapping of the debug channel registers via SDCR.TDCC
> * trapping of GICv3 registers via SCR.IRQ and SCR.FIQ
> (which we already used arm_is_el3_or_mon() for)
>
> This patch changes the handling of SCR.TERR and SDCR.TDCC. This
> patch only changes guest-visible behaviour for "-cpu max" on
> the qemu-system-arm binary, because SCR.TERR
> and SDCR.TDCC (and indeed the entire SDCR register) only arrived
> in Armv8, and the only guest CPU we support which has any v8
> features and also starts in AArch32 EL3 is the 32-bit 'max'.
>
> Other uses of CP_ACCESS_TRAP_EL3 don't need changing:
>
> * uses in code paths that can't happen when EL3 is AArch32:
> access_trap_aa32s_el1, cpacr_access, cptr_access, nsacr_access
> * uses which are in accessfns for AArch64-only registers:
> gt_stimer_access, gt_cntpoff_access, access_hxen, access_tpidr2,
> access_smpri, access_smprimap, access_lor_ns, access_pauth,
> access_mte, access_tfsr_el2, access_scxtnum, access_fgt
> * trap bits which exist only in the AArch64 version of the
> trap register, not the AArch32 one:
> access_tpm, pmreg_access, access_dbgvcr32, access_tdra,
> access_tda, access_tdosa (TPM, TDA and TDOSA exist only in
> MDCR_EL3, not in SDCR, and we enforce this in sdcr_write())
>
> Cc: qemu-stable@nongnu.org
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
--
Alex Bennée
Virtualisation Tech Lead @ Linaro
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