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[PATCH v5 08/16] target/microblaze: Set MO_TE once in do_load() / do_sto
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v5 08/16] target/microblaze: Set MO_TE once in do_load() / do_store() |
Date: |
Thu, 6 Feb 2025 14:10:44 +0100 |
All callers of do_load() / do_store() set MO_TE flag.
Set it once in the callees.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/translate.c | 36 +++++++++++++++++++----------------
1 file changed, 20 insertions(+), 16 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 86efabb83b5..0d51b2c468c 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -713,6 +713,8 @@ static bool do_load(DisasContext *dc, int rd, TCGv addr,
MemOp mop,
{
MemOp size = mop & MO_SIZE;
+ mop |= MO_TE;
+
/*
* When doing reverse accesses we need to do two things.
*
@@ -780,13 +782,13 @@ static bool trans_lbui(DisasContext *dc, arg_typeb *arg)
static bool trans_lhu(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
+ return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
}
static bool trans_lhur(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true);
+ return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, true);
}
static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
@@ -798,26 +800,26 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false);
+ return do_load(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_lhui(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
- return do_load(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
+ return do_load(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
}
static bool trans_lw(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
+ return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
}
static bool trans_lwr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true);
+ return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, true);
}
static bool trans_lwea(DisasContext *dc, arg_typea *arg)
@@ -829,14 +831,14 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
- return do_load(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false);
+ return do_load(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_lwi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
- return do_load(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
+ return do_load(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
}
static bool trans_lwx(DisasContext *dc, arg_typea *arg)
@@ -863,6 +865,8 @@ static bool do_store(DisasContext *dc, int rd, TCGv addr,
MemOp mop,
{
MemOp size = mop & MO_SIZE;
+ mop |= MO_TE;
+
/*
* When doing reverse accesses we need to do two things.
*
@@ -930,13 +934,13 @@ static bool trans_sbi(DisasContext *dc, arg_typeb *arg)
static bool trans_sh(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
+ return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
}
static bool trans_shr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, true);
+ return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, true);
}
static bool trans_shea(DisasContext *dc, arg_typea *arg)
@@ -948,26 +952,26 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TE | MO_UW, MMU_NOMMU_IDX, false);
+ return do_store(dc, arg->rd, addr, MO_UW, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_shi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
- return do_store(dc, arg->rd, addr, MO_TE | MO_UW, dc->mem_index, false);
+ return do_store(dc, arg->rd, addr, MO_UW, dc->mem_index, false);
}
static bool trans_sw(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
+ return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
}
static bool trans_swr(DisasContext *dc, arg_typea *arg)
{
TCGv addr = compute_ldst_addr_typea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, true);
+ return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, true);
}
static bool trans_swea(DisasContext *dc, arg_typea *arg)
@@ -979,14 +983,14 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg)
return true;
#else
TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb);
- return do_store(dc, arg->rd, addr, MO_TE | MO_UL, MMU_NOMMU_IDX, false);
+ return do_store(dc, arg->rd, addr, MO_UL, MMU_NOMMU_IDX, false);
#endif
}
static bool trans_swi(DisasContext *dc, arg_typeb *arg)
{
TCGv addr = compute_ldst_addr_typeb(dc, arg->ra, arg->imm);
- return do_store(dc, arg->rd, addr, MO_TE | MO_UL, dc->mem_index, false);
+ return do_store(dc, arg->rd, addr, MO_UL, dc->mem_index, false);
}
static bool trans_swx(DisasContext *dc, arg_typea *arg)
--
2.47.1
- [PATCH v5 00/16] hw/microblaze: Allow running cross-endian vCPUs, Philippe Mathieu-Daudé, 2025/02/06
- [PATCH v5 01/16] hw/intc/xilinx_intc: Make device endianness configurable, Philippe Mathieu-Daudé, 2025/02/06
- [PATCH v5 02/16] hw/net/xilinx_ethlite: Make device endianness configurable, Philippe Mathieu-Daudé, 2025/02/06
- [PATCH v5 03/16] hw/timer/xilinx_timer: Make device endianness configurable, Philippe Mathieu-Daudé, 2025/02/06
- [PATCH v5 04/16] hw/char/xilinx_uartlite: Make device endianness configurable, Philippe Mathieu-Daudé, 2025/02/06
- [PATCH v5 05/16] hw/ssi/xilinx_spi: Make device endianness configurable, Philippe Mathieu-Daudé, 2025/02/06
- [PATCH v5 06/16] hw/arm/xlnx-zynqmp: Use &error_abort for programming errors, Philippe Mathieu-Daudé, 2025/02/06
- [PATCH v5 07/16] target/microblaze: Explode MO_TExx -> MO_TE | MO_xx, Philippe Mathieu-Daudé, 2025/02/06
- [PATCH v5 08/16] target/microblaze: Set MO_TE once in do_load() / do_store(),
Philippe Mathieu-Daudé <=
- [PATCH v5 09/16] target/microblaze: Introduce mo_endian() helper, Philippe Mathieu-Daudé, 2025/02/06
- [PATCH v5 10/16] target/microblaze: Consider endianness while translating code, Philippe Mathieu-Daudé, 2025/02/06
- [PATCH v5 11/16] hw/microblaze: Support various endianness for s3adsp1800 machines, Philippe Mathieu-Daudé, 2025/02/06
- Re: [PATCH v5 11/16] hw/microblaze: Support various endianness for s3adsp1800 machines, Daniel P . Berrangé, 2025/02/06
- Re: [PATCH v5 11/16] hw/microblaze: Support various endianness for s3adsp1800 machines, Philippe Mathieu-Daudé, 2025/02/06
- Re: [PATCH v5 11/16] hw/microblaze: Support various endianness for s3adsp1800 machines, Daniel P . Berrangé, 2025/02/06
- Re: [PATCH v5 11/16] hw/microblaze: Support various endianness for s3adsp1800 machines, Philippe Mathieu-Daudé, 2025/02/06
- Re: [PATCH v5 11/16] hw/microblaze: Support various endianness for s3adsp1800 machines, Thomas Huth, 2025/02/06
- Re: [PATCH v5 11/16] hw/microblaze: Support various endianness for s3adsp1800 machines, Daniel P . Berrangé, 2025/02/06
- Re: [PATCH v5 11/16] hw/microblaze: Support various endianness for s3adsp1800 machines, Philippe Mathieu-Daudé, 2025/02/06