[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 2/5] hw/i386/intel-iommu: Migrate to 3-phase reset
From: |
Eric Auger |
Subject: |
[PATCH 2/5] hw/i386/intel-iommu: Migrate to 3-phase reset |
Date: |
Thu, 6 Feb 2025 15:21:53 +0100 |
Currently the IOMMU may be reset before the devices
it protects. For example this happens with virtio-net.
Let's use 3-phase reset mechanism and reset the IOMMU on
exit phase instead.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
hw/i386/intel_iommu.c | 8 +++++---
hw/i386/trace-events | 1 +
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index f366c223d0..21a8bf45f8 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -4697,10 +4697,11 @@ static void vtd_init(IntelIOMMUState *s)
/* Should not reset address_spaces when reset because devices will still use
* the address space they got at first (won't ask the bus again).
*/
-static void vtd_reset(DeviceState *dev)
+static void vtd_reset_exit(Object *obj, ResetType type)
{
- IntelIOMMUState *s = INTEL_IOMMU_DEVICE(dev);
+ IntelIOMMUState *s = INTEL_IOMMU_DEVICE(obj);
+ trace_vtd_reset_exit();
vtd_init(s);
vtd_address_space_refresh_all(s);
}
@@ -4864,8 +4865,9 @@ static void vtd_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
X86IOMMUClass *x86_class = X86_IOMMU_DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
- device_class_set_legacy_reset(dc, vtd_reset);
+ rc->phases.exit = vtd_reset_exit;
dc->vmsd = &vtd_vmstate;
device_class_set_props(dc, vtd_properties);
dc->hotpluggable = false;
diff --git a/hw/i386/trace-events b/hw/i386/trace-events
index 53c02d7ac8..ac9e1a10aa 100644
--- a/hw/i386/trace-events
+++ b/hw/i386/trace-events
@@ -68,6 +68,7 @@ vtd_frr_new(int index, uint64_t hi, uint64_t lo) "index %d
high 0x%"PRIx64" low
vtd_warn_invalid_qi_tail(uint16_t tail) "tail 0x%"PRIx16
vtd_warn_ir_vector(uint16_t sid, int index, int vec, int target) "sid
0x%"PRIx16" index %d vec %d (should be: %d)"
vtd_warn_ir_trigger(uint16_t sid, int index, int trig, int target) "sid
0x%"PRIx16" index %d trigger %d (should be: %d)"
+vtd_reset_exit(void) ""
# amd_iommu.c
amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at addr
0x%"PRIx64" + offset 0x%"PRIx32
--
2.47.1
- [PATCH 0/5] Fix vIOMMU reset order, Eric Auger, 2025/02/06
- [PATCH 1/5] hw/virtio/virtio-iommu: Migrate to 3-phase reset, Eric Auger, 2025/02/06
- [PATCH 2/5] hw/i386/intel-iommu: Migrate to 3-phase reset,
Eric Auger <=
- [PATCH 3/5] hw/i386/intel_iommu: Tear down address spaces before IOMMU reset, Eric Auger, 2025/02/06
- [PATCH 4/5] hw/arm/smmuv3: Move reset to exit phase, Eric Auger, 2025/02/06
- Re: [PATCH 4/5] hw/arm/smmuv3: Move reset to exit phase, Peter Maydell, 2025/02/07
- Re: [PATCH 4/5] hw/arm/smmuv3: Move reset to exit phase, Eric Auger, 2025/02/07
- Re: [PATCH 4/5] hw/arm/smmuv3: Move reset to exit phase, Peter Maydell, 2025/02/07
- Re: [PATCH 4/5] hw/arm/smmuv3: Move reset to exit phase, Peter Xu, 2025/02/07
- Re: [PATCH 4/5] hw/arm/smmuv3: Move reset to exit phase, Peter Maydell, 2025/02/07
- Re: [PATCH 4/5] hw/arm/smmuv3: Move reset to exit phase, Eric Auger, 2025/02/10