Re: [PATCH v5 11/16] hw/microblaze: Support various endianness for s3adsp1800 machines

[Max Filippov]

On Thu, Feb 6, 2025 at 7:04 AM Philippe Mathieu-Daudé <philmd@linaro.org> wrote:
> On 6/2/25 15:31, Daniel P. Berrangé wrote:
> > We would pick an arbitrary endianness of our choosing
> > I guess. How does this work in physical machines ? Is
> > the choice of endianess a firmware setting, or a choice
> > by the vendor when manufacturing in some way ?
>
> Like MIPS*, SH4* and Xtensa*, it is a jumper on the board
> (wired to a CPU pin which is sampled once at cold reset).

This is not exactly the case for xtensa. Each xtensa CPU is either
big- or little-endian and it's a static property of the CPU
configuration. On physical machines it's either fixed (e.g. if
the CPU is a part of an ASIC), or it's a part of a bitstream that
gets loaded into an FPGA and there may be a selector for one
of the bitstreams in the onboard FLASH. In either case there's
normally no board-level switch for the CPU endianness.

Also big- and little-endian instruction encodings are different on
otherwise identical xtensa CPUs.

-- 
Thanks.
-- Max