[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 13/61] target/arm: Add ZT0
From: |
Richard Henderson |
Subject: |
[PATCH 13/61] target/arm: Add ZT0 |
Date: |
Thu, 6 Feb 2025 11:56:27 -0800 |
This is a 512-bit array introduced with SME2.
Save it only when ZA is in use.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/cpu.h | 3 +++
target/arm/machine.c | 21 +++++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 938c990854..091a517a93 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -734,6 +734,9 @@ typedef struct CPUArchState {
uint64_t scxtnum_el[4];
struct {
+ /* SME2 ZT0 -- 512 bit array, with data ordered like ARMVectorReg. */
+ uint64_t zt0[512 / 64] QEMU_ALIGNED(16);
+
/*
* SME ZA storage -- 256 x 256 byte array, with bytes in host
* word order, as we do with vfp.zregs[]. This corresponds to
diff --git a/target/arm/machine.c b/target/arm/machine.c
index d41da414b3..416fe1b7be 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -320,6 +320,26 @@ static const VMStateDescription vmstate_za = {
VMSTATE_END_OF_LIST()
}
};
+
+static bool zt0_needed(void *opaque)
+{
+ ARMCPU *cpu = opaque;
+
+ return za_needed(cpu) && cpu_isar_feature(aa64_sme2, cpu);
+}
+
+static const VMStateDescription vmstate_zt0 = {
+ .name = "cpu/zt0",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = zt0_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT64_ARRAY(env.za_state.zt0, ARMCPU,
+ ARRAY_SIZE(((CPUARMState *)0)->za_state.zt0)),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
#endif /* AARCH64 */
static bool serror_needed(void *opaque)
@@ -1104,6 +1124,7 @@ const VMStateDescription vmstate_arm_cpu = {
#ifdef TARGET_AARCH64
&vmstate_sve,
&vmstate_za,
+ &vmstate_zt0,
#endif
&vmstate_serror,
&vmstate_irq_line_state,
--
2.43.0
- [PATCH 09/61] target/arm: Introduce FPST_ZA, FPST_ZA_F16, (continued)
- [PATCH 09/61] target/arm: Introduce FPST_ZA, FPST_ZA_F16, Richard Henderson, 2025/02/06
- [PATCH 02/61] tcg: Add dbase argument to do_dup, Richard Henderson, 2025/02/06
- [PATCH 03/61] tcg: Add dbase argument to expand_clr, Richard Henderson, 2025/02/06
- [PATCH 04/61] tcg: Add base arguments to check_overlap_[234], Richard Henderson, 2025/02/06
- [PATCH 07/61] tcg: Split out tcg_gen_gvec_mov_var, Richard Henderson, 2025/02/06
- [PATCH 10/61] target/arm: Use FPST_ZA for sme_fmopa_[hsd], Richard Henderson, 2025/02/06
- [PATCH 14/61] target/arm: Add zt0_excp_el to DisasContext, Richard Henderson, 2025/02/06
- [PATCH 12/61] target/arm: Add isar_feature_aa64_sme2*, Richard Henderson, 2025/02/06
- [PATCH 17/61] target/arm: Implement SME2 MOVT, Richard Henderson, 2025/02/06
- [PATCH 11/61] target/arm: Rename zarray to za_state.za, Richard Henderson, 2025/02/06
- [PATCH 13/61] target/arm: Add ZT0,
Richard Henderson <=
- [PATCH 16/61] target/arm: Implement SME2 LDR/STR ZT0, Richard Henderson, 2025/02/06
- [PATCH 15/61] target/arm: Implement SME2 ZERO ZT0, Richard Henderson, 2025/02/06
- [PATCH 21/61] target/arm: Split out get_zarray, Richard Henderson, 2025/02/06
- [PATCH 20/61] target/arm: Implement SME2 MOVA to/from tile, multiple registers, Richard Henderson, 2025/02/06
- [PATCH 19/61] target/arm: Rename MOVA for translate, Richard Henderson, 2025/02/06
- [PATCH 22/61] target/arm: Implement SME2 MOVA to/from array, multiple registers, Richard Henderson, 2025/02/06
- [PATCH 24/61] target/arm: Implement SME2 SMOPS, UMOPS (2-way), Richard Henderson, 2025/02/06
- [PATCH 26/61] target/arm: Implement SME2 Multiple and Single SVE Destructive, Richard Henderson, 2025/02/06
- [PATCH 31/61] target/arm: Implement SME2 FMLAL, BFMLAL, Richard Henderson, 2025/02/06
- [PATCH 29/61] target/arm: Implement SME2 ADD/SUB (array results, multiple vectors), Richard Henderson, 2025/02/06