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[PATCH 17/61] target/arm: Implement SME2 MOVT
From: |
Richard Henderson |
Subject: |
[PATCH 17/61] target/arm: Implement SME2 MOVT |
Date: |
Thu, 6 Feb 2025 11:56:31 -0800 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/tcg/translate-sme.c | 13 +++++++++++++
target/arm/tcg/sme.decode | 5 +++++
2 files changed, 18 insertions(+)
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
index 8b0a33e2ae..13314c5cd7 100644
--- a/target/arm/tcg/translate-sme.c
+++ b/target/arm/tcg/translate-sme.c
@@ -210,6 +210,19 @@ static bool trans_MOVA(DisasContext *s, arg_MOVA *a)
return true;
}
+static bool do_movt(DisasContext *s, arg_MOVT_rzt *a,
+ void (*func)(TCGv_i64, TCGv_ptr, tcg_target_long))
+{
+ if (sme2_zt0_enabled_check(s)) {
+ func(cpu_reg(s, a->rt), tcg_env,
+ offsetof(CPUARMState, za_state.zt0) + a->off * 8);
+ }
+ return true;
+}
+
+TRANS_FEAT(MOVT_rzt, aa64_sme2, do_movt, a, tcg_gen_ld_i64)
+TRANS_FEAT(MOVT_ztr, aa64_sme2, do_movt, a, tcg_gen_st_i64)
+
static bool trans_LDST1(DisasContext *s, arg_LDST1 *a)
{
typedef void GenLdSt1(TCGv_env, TCGv_ptr, TCGv_ptr, TCGv, TCGv_i32);
diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode
index cef49c3b29..83ca6a9104 100644
--- a/target/arm/tcg/sme.decode
+++ b/target/arm/tcg/sme.decode
@@ -39,6 +39,11 @@ MOVA 11000000 esz:2 00001 0 v:1 .. pg:3 0
za_imm:4 zr:5 \
MOVA 11000000 11 00001 1 v:1 .. pg:3 0 za_imm:4 zr:5 \
&mova to_vec=1 rs=%mova_rs esz=4
+### SME Move into/from ZT0
+
+MOVT_rzt 1100 0000 0100 1100 0 off:3 00 11111 rt:5
+MOVT_ztr 1100 0000 0100 1110 0 off:3 00 11111 rt:5
+
### SME Memory
&ldst esz rs pg rn rm za_imm v:bool st:bool
--
2.43.0
- [PATCH 06/61] tcg: Split out tcg_gen_gvec_3_var, (continued)
- [PATCH 06/61] tcg: Split out tcg_gen_gvec_3_var, Richard Henderson, 2025/02/06
- [PATCH 08/61] tcg: Split out tcg_gen_gvec_{add,sub}_var, Richard Henderson, 2025/02/06
- [PATCH 09/61] target/arm: Introduce FPST_ZA, FPST_ZA_F16, Richard Henderson, 2025/02/06
- [PATCH 02/61] tcg: Add dbase argument to do_dup, Richard Henderson, 2025/02/06
- [PATCH 03/61] tcg: Add dbase argument to expand_clr, Richard Henderson, 2025/02/06
- [PATCH 04/61] tcg: Add base arguments to check_overlap_[234], Richard Henderson, 2025/02/06
- [PATCH 07/61] tcg: Split out tcg_gen_gvec_mov_var, Richard Henderson, 2025/02/06
- [PATCH 10/61] target/arm: Use FPST_ZA for sme_fmopa_[hsd], Richard Henderson, 2025/02/06
- [PATCH 14/61] target/arm: Add zt0_excp_el to DisasContext, Richard Henderson, 2025/02/06
- [PATCH 12/61] target/arm: Add isar_feature_aa64_sme2*, Richard Henderson, 2025/02/06
- [PATCH 17/61] target/arm: Implement SME2 MOVT,
Richard Henderson <=
- [PATCH 11/61] target/arm: Rename zarray to za_state.za, Richard Henderson, 2025/02/06
- [PATCH 13/61] target/arm: Add ZT0, Richard Henderson, 2025/02/06
- [PATCH 16/61] target/arm: Implement SME2 LDR/STR ZT0, Richard Henderson, 2025/02/06
- [PATCH 15/61] target/arm: Implement SME2 ZERO ZT0, Richard Henderson, 2025/02/06
- [PATCH 21/61] target/arm: Split out get_zarray, Richard Henderson, 2025/02/06
- [PATCH 20/61] target/arm: Implement SME2 MOVA to/from tile, multiple registers, Richard Henderson, 2025/02/06
- [PATCH 19/61] target/arm: Rename MOVA for translate, Richard Henderson, 2025/02/06
- [PATCH 22/61] target/arm: Implement SME2 MOVA to/from array, multiple registers, Richard Henderson, 2025/02/06
- [PATCH 24/61] target/arm: Implement SME2 SMOPS, UMOPS (2-way), Richard Henderson, 2025/02/06
- [PATCH 26/61] target/arm: Implement SME2 Multiple and Single SVE Destructive, Richard Henderson, 2025/02/06