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Re: [PATCH v4 15/17] hw/arm: Add NPCM8XX SoC
From: |
Peter Maydell |
Subject: |
Re: [PATCH v4 15/17] hw/arm: Add NPCM8XX SoC |
Date: |
Mon, 10 Feb 2025 14:52:37 +0000 |
On Thu, 6 Feb 2025 at 22:12, Hao Wu <wuhaotsh@google.com> wrote:
>
> Signed-off-by: Hao Wu <wuhaotsh@google.com>
> ---
> configs/devices/aarch64-softmmu/default.mak | 1 +
> hw/arm/Kconfig | 13 +
> hw/arm/meson.build | 1 +
> hw/arm/npcm8xx.c | 804 ++++++++++++++++++++
> include/hw/arm/npcm8xx.h | 107 +++
> 5 files changed, 926 insertions(+)
> create mode 100644 hw/arm/npcm8xx.c
> create mode 100644 include/hw/arm/npcm8xx.h
> +static void npcm8xx_init_fuses(NPCM8xxState *s)
> +{
> + NPCM8xxClass *nc = NPCM8XX_GET_CLASS(s);
> + uint32_t value;
> +
> + /*
> + * The initial mask of disabled modules indicates the chip derivative
> (e.g.
> + * NPCM750 or NPCM730).
> + */
> + value = tswap32(nc->disabled_modules);
> + npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE,
> + sizeof(value));
> +}
We're trying to get rid of tswap32() uses. Compare
npcm7xx_init_fuses(), which does
value = cpu_to_le32(nc->disabled_modules);
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- [PATCH v4 08/17] hw/misc: Store DRAM size in NPCM8XX GCR Module, (continued)
- [PATCH v4 08/17] hw/misc: Store DRAM size in NPCM8XX GCR Module, Hao Wu, 2025/02/06
- [PATCH v4 12/17] hw/misc: Add nr_regs and cold_reset_values to NPCM CLK, Hao Wu, 2025/02/06
- [PATCH v4 11/17] hw/misc: Move NPCM7XX CLK to NPCM CLK, Hao Wu, 2025/02/06
- [PATCH v4 14/17] hw/net: Add NPCM8XX PCS Module, Hao Wu, 2025/02/06
- [PATCH v4 13/17] hw/misc: Support NPCM8XX CLK Module Registers, Hao Wu, 2025/02/06
- [PATCH v4 17/17] docs/system/arm: Add Description for NPCM8XX SoC, Hao Wu, 2025/02/06
- [PATCH v4 16/17] hw/arm: Add NPCM845 Evaluation board, Hao Wu, 2025/02/06
- [PATCH v4 15/17] hw/arm: Add NPCM8XX SoC, Hao Wu, 2025/02/06
- Re: [PATCH v4 00/17] hw/arm: Add NPCM8XX Support, Peter Maydell, 2025/02/17