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Re: [PATCH v2 08/69] target/arm: Adjust FP behaviour for FPCR.AH = 1
From: |
Peter Maydell |
Subject: |
Re: [PATCH v2 08/69] target/arm: Adjust FP behaviour for FPCR.AH = 1 |
Date: |
Tue, 11 Feb 2025 13:17:25 +0000 |
On Sat, 1 Feb 2025 at 16:40, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> When FPCR.AH is set, various behaviours of AArch64 floating point
> operations which are controlled by softfloat config settings change:
> * tininess and ftz detection before/after rounding
> * NaN propagation order
> * result of 0 * Inf + NaN
> * default NaN value
>
> When the guest changes the value of the AH bit, switch these config
> settings on the fp_status_a64 and fp_status_f16_a64 float_status
> fields.
>
> This requires us to make the arm_set_default_fp_behaviours() function
> global, since we now need to call it from cpu.c and vfp_helper.c; we
> move it to vfp_helper.c so it can be next to the new
> arm_set_ah_fp_behaviours().
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
This turns out to need this tweak folding in to avoid compile
failures on the kvm-only config:
#include "exec/helper-proto.h"
#include "internals.h"
#include "cpu-features.h"
+#include "fpu/softfloat.h"
#ifdef CONFIG_TCG
#include "qemu/log.h"
-#include "fpu/softfloat.h"
#endif
(Once this has landed I'm tempted to clean up vfp_helper.c
so that e.g. the tcg-only parts get moved into tcg/ rather
than almost all of the file being inside an ifdef.)
-- PMM
- [PATCH v2 01/69] target/i386: Do not raise Invalid for 0 * Inf + QNaN, (continued)
- [PATCH v2 01/69] target/i386: Do not raise Invalid for 0 * Inf + QNaN, Peter Maydell, 2025/02/01
- [PATCH v2 02/69] tests/tcg/x86_64/fma: Test some x86 fused-multiply-add cases, Peter Maydell, 2025/02/01
- [PATCH v2 03/69] fpu: Add float_class_denormal, Peter Maydell, 2025/02/01
- [PATCH v2 05/69] fpu: allow flushing of output denormals to be after rounding, Peter Maydell, 2025/02/01
- [PATCH v2 06/69] target/arm: Define FPCR AH, FIZ, NEP bits, Peter Maydell, 2025/02/01
- [PATCH v2 04/69] fpu: Implement float_flag_input_denormal_used, Peter Maydell, 2025/02/01
- [PATCH v2 11/69] target/arm: Set up float_status to use for FPCR.AH=1 behaviour, Peter Maydell, 2025/02/01
- [PATCH v2 07/69] target/arm: Implement FPCR.FIZ handling, Peter Maydell, 2025/02/01
- [PATCH v2 14/69] target/arm: Use FPST_FPCR_AH for BFMLAL*, BFMLSL* insns, Peter Maydell, 2025/02/01
- [PATCH v2 08/69] target/arm: Adjust FP behaviour for FPCR.AH = 1, Peter Maydell, 2025/02/01
- Re: [PATCH v2 08/69] target/arm: Adjust FP behaviour for FPCR.AH = 1,
Peter Maydell <=
- [PATCH v2 09/69] target/arm: Adjust exception flag handling for AH = 1, Peter Maydell, 2025/02/01
- [PATCH v2 10/69] target/arm: Add FPCR.AH to tbflags, Peter Maydell, 2025/02/01
- [PATCH v2 13/69] target/arm: Use FPST_FPCR_AH for BFCVT* insns, Peter Maydell, 2025/02/01
- [PATCH v2 19/69] target/arm: Handle FPCR.NEP for 1-input scalar operations, Peter Maydell, 2025/02/01
- [PATCH v2 17/69] target/arm: Handle FPCR.NEP for 3-input scalar operations, Peter Maydell, 2025/02/01
- [PATCH v2 16/69] target/arm: Define and use new write_fp_*reg_merging() functions, Peter Maydell, 2025/02/01
- [PATCH v2 15/69] target/arm: Add FPCR.NEP to TBFLAGS, Peter Maydell, 2025/02/01
- [PATCH v2 12/69] target/arm: Use FPST_FPCR_AH for FRECPE, FRECPS, FRECPX, FRSQRTE, FRSQRTS, Peter Maydell, 2025/02/01
- [PATCH v2 18/69] target/arm: Handle FPCR.NEP for BFCVT scalar, Peter Maydell, 2025/02/01
- [PATCH v2 21/69] target/arm: Handle FPCR.NEP for scalar FABS and FNEG, Peter Maydell, 2025/02/01