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[PATCH v3 14/28] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1
From: |
Jamin Lin |
Subject: |
[PATCH v3 14/28] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions |
Date: |
Thu, 13 Feb 2025 11:35:17 +0800 |
Added new definitions for AST2700_A1_SILICON_REV and AST2750_A1_SILICON_REV to
identify the A1 silicon revisions.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
---
hw/misc/aspeed_scu.c | 2 ++
include/hw/misc/aspeed_scu.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c
index bac1441b06..2d9fe78926 100644
--- a/hw/misc/aspeed_scu.c
+++ b/hw/misc/aspeed_scu.c
@@ -559,6 +559,8 @@ static uint32_t aspeed_silicon_revs[] = {
AST2700_A0_SILICON_REV,
AST2720_A0_SILICON_REV,
AST2750_A0_SILICON_REV,
+ AST2700_A1_SILICON_REV,
+ AST2750_A1_SILICON_REV,
};
bool is_supported_silicon_rev(uint32_t silicon_rev)
diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
index 356be95e45..684b48b722 100644
--- a/include/hw/misc/aspeed_scu.h
+++ b/include/hw/misc/aspeed_scu.h
@@ -54,6 +54,8 @@ struct AspeedSCUState {
#define AST2700_A0_SILICON_REV 0x06000103U
#define AST2720_A0_SILICON_REV 0x06000203U
#define AST2750_A0_SILICON_REV 0x06000003U
+#define AST2700_A1_SILICON_REV 0x06010103U
+#define AST2750_A1_SILICON_REV 0x06010003U
#define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04)
--
2.34.1
- Re: [PATCH v3 08/28] hw/intc/aspeed: Add support for multiple output pins in INTC, (continued)
- [PATCH v3 11/28] hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication, Jamin Lin, 2025/02/12
- [PATCH v3 10/28] hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address, Jamin Lin, 2025/02/12
- [PATCH v3 12/28] hw/intc/aspeed: Add Support for Multi-Output IRQ Handling, Jamin Lin, 2025/02/12
- [PATCH v3 13/28] hw/intc/aspeed: Add Support for AST2700 INTCIO Controller, Jamin Lin, 2025/02/12
- [PATCH v3 14/28] hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions,
Jamin Lin <=
- [PATCH v3 15/28] hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AST2700, Jamin Lin, 2025/02/12
- [PATCH v3 16/28] hw/arm/aspeed_ast27x0.c Support AST2700 A1 GIC Interrupt Mapping, Jamin Lin, 2025/02/12
- [PATCH v3 17/28] hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1, Jamin Lin, 2025/02/12
- [PATCH v3 19/28] hw/misc/aspeed_hace: Fix coding style, Jamin Lin, 2025/02/12
- [PATCH v3 18/28] hw/arm/aspeed: Add SoC and Machine Support for AST2700 A1, Jamin Lin, 2025/02/12