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[PATCH v2 5/7] qpci_device_enable: Allow for command bits hardwired to 0
From: |
Lev Kujawski |
Subject: |
[PATCH v2 5/7] qpci_device_enable: Allow for command bits hardwired to 0 |
Date: |
Thu, 7 Jul 2022 03:11:38 +0000 |
Devices like the PIIX3/4 IDE controller do not support certain modes
of operation, such as memory space accesses, and indicate this lack of
support by hardwiring the applicable bits to zero. Extend the QEMU
PCI device testing framework to accommodate such devices.
* tests/qtest/libqos/pci.h: Add the command_disabled word to indicate
bits hardwired to 0.
* tests/qtest/libqos/pci.c: Verify that hardwired bits are actually
hardwired.
Signed-off-by: Lev Kujawski <lkujaw@member.fsf.org>
---
tests/qtest/libqos/pci.c | 13 +++++++------
tests/qtest/libqos/pci.h | 1 +
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/tests/qtest/libqos/pci.c b/tests/qtest/libqos/pci.c
index b23d72346b..4f3d28d8d9 100644
--- a/tests/qtest/libqos/pci.c
+++ b/tests/qtest/libqos/pci.c
@@ -220,18 +220,19 @@ int qpci_secondary_buses_init(QPCIBus *bus)
void qpci_device_enable(QPCIDevice *dev)
{
- uint16_t cmd;
+ const uint16_t enable_bits =
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+ uint16_t cmd, new_cmd;
/* FIXME -- does this need to be a bus callout? */
cmd = qpci_config_readw(dev, PCI_COMMAND);
- cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+ cmd |= enable_bits;
qpci_config_writew(dev, PCI_COMMAND, cmd);
/* Verify the bits are now set. */
- cmd = qpci_config_readw(dev, PCI_COMMAND);
- g_assert_cmphex(cmd & PCI_COMMAND_IO, ==, PCI_COMMAND_IO);
- g_assert_cmphex(cmd & PCI_COMMAND_MEMORY, ==, PCI_COMMAND_MEMORY);
- g_assert_cmphex(cmd & PCI_COMMAND_MASTER, ==, PCI_COMMAND_MASTER);
+ new_cmd = qpci_config_readw(dev, PCI_COMMAND);
+ new_cmd &= enable_bits;
+ g_assert_cmphex(new_cmd, ==, enable_bits & ~dev->command_disabled);
}
/**
diff --git a/tests/qtest/libqos/pci.h b/tests/qtest/libqos/pci.h
index 8389614523..eaedb98588 100644
--- a/tests/qtest/libqos/pci.h
+++ b/tests/qtest/libqos/pci.h
@@ -68,6 +68,7 @@ struct QPCIDevice
bool msix_enabled;
QPCIBar msix_table_bar, msix_pba_bar;
uint64_t msix_table_off, msix_pba_off;
+ uint16_t command_disabled;
};
struct QPCIAddress {
--
2.34.1
- [PATCH v2 1/7] piix_ide_reset: Use pci_set_* functions instead of direct access, Lev Kujawski, 2022/07/06
- [PATCH v2 3/7] hw/ide/core: Clear LBA and drive bits for EXECUTE DEVICE DIAGNOSTIC, Lev Kujawski, 2022/07/06
- [PATCH v2 2/7] tests/qtest/ide-test.c: Create disk image for use as a secondary, Lev Kujawski, 2022/07/06
- [PATCH v2 4/7] tests/qtest/ide-test: Verify that DIAGNOSTIC clears DEV to zero, Lev Kujawski, 2022/07/06
- [PATCH v2 5/7] qpci_device_enable: Allow for command bits hardwired to 0,
Lev Kujawski <=
- [PATCH v2 6/7] hw/ide/piix: Ignore writes of hardwired PCI command register bits, Lev Kujawski, 2022/07/06
- [PATCH v2 7/7] hw/ide/core.c: Implement ATA INITIALIZE_DEVICE_PARAMETERS command, Lev Kujawski, 2022/07/06