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[PATCH v2 6/7] hw/ide/piix: Ignore writes of hardwired PCI command regis
From: |
Lev Kujawski |
Subject: |
[PATCH v2 6/7] hw/ide/piix: Ignore writes of hardwired PCI command register bits |
Date: |
Thu, 7 Jul 2022 03:11:39 +0000 |
One method to enable PCI bus mastering for IDE controllers, often used
by x86 firmware, is to write 0x7 to the PCI command register. Neither
the PIIX3 specification nor actual hardware (a Tyan S1686D system)
permit modification of the Memory Space Enable (MSE) bit, 1, and thus
the command register would be left in an unspecified state without
this patch.
* hw/ide/piix.c
a) Add a reference to the PIIX4 data sheet.
b) Mask the MSE bit using the QEMU PCI device wmask field.
* tests/qtest/ide-test.c
Use the command_disabled field of the QPCIDevice testing model to
indicate that PCI_COMMAND_MEMORY is hardwired in the PIIX3/4 IDE
controller.
Signed-off-by: Lev Kujawski <lkujaw@member.fsf.org>
---
hw/ide/piix.c | 15 +++++++++++++++
tests/qtest/ide-test.c | 1 +
2 files changed, 16 insertions(+)
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
index de1f4f0efb..64620c5778 100644
--- a/hw/ide/piix.c
+++ b/hw/ide/piix.c
@@ -25,6 +25,8 @@
* References:
* [1] 82371FB (PIIX) AND 82371SB (PIIX3) PCI ISA IDE XCELERATOR,
* 290550-002, Intel Corporation, April 1997.
+ * [2] 82371AB PCI-TO-ISA / IDE XCELERATOR (PIIX4), 290562-001,
+ * Intel Corporation, April 1997.
*/
#include "qemu/osdep.h"
@@ -160,6 +162,19 @@ static void pci_piix_ide_realize(PCIDevice *dev, Error
**errp)
uint8_t *pci_conf = dev->config;
int rc;
+ /*
+ * Mask all IDE PCI command register bits except for Bus Master
+ * Function Enable (bit 2) and I/O Space Enable (bit 1), as the
+ * remainder are hardwired to 0 [1, p.48] [2, p.89-90].
+ *
+ * NOTE: According to the PIIX3 datasheet [1], the Memory Space
+ * Enable (MSE bit) is hardwired to 1, but this is contradicted by
+ * actual PIIX3 hardware, the datasheet itself (viz., Default
+ * Value: 0000h), and the PIIX4 datasheet [2].
+ */
+ pci_set_word(dev->wmask + PCI_COMMAND,
+ PCI_COMMAND_MASTER | PCI_COMMAND_IO);
+
pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode
bmdma_setup_bar(d);
diff --git a/tests/qtest/ide-test.c b/tests/qtest/ide-test.c
index dfcf59cee8..728e8ce00f 100644
--- a/tests/qtest/ide-test.c
+++ b/tests/qtest/ide-test.c
@@ -176,6 +176,7 @@ static QPCIDevice *get_pci_device(QTestState *qts, QPCIBar
*bmdma_bar,
*ide_bar = qpci_legacy_iomap(dev, IDE_BASE);
+ dev->command_disabled = PCI_COMMAND_MEMORY;
qpci_device_enable(dev);
return dev;
--
2.34.1
- [PATCH v2 1/7] piix_ide_reset: Use pci_set_* functions instead of direct access, Lev Kujawski, 2022/07/06
- [PATCH v2 3/7] hw/ide/core: Clear LBA and drive bits for EXECUTE DEVICE DIAGNOSTIC, Lev Kujawski, 2022/07/06
- [PATCH v2 2/7] tests/qtest/ide-test.c: Create disk image for use as a secondary, Lev Kujawski, 2022/07/06
- [PATCH v2 4/7] tests/qtest/ide-test: Verify that DIAGNOSTIC clears DEV to zero, Lev Kujawski, 2022/07/06
- [PATCH v2 5/7] qpci_device_enable: Allow for command bits hardwired to 0, Lev Kujawski, 2022/07/06
- [PATCH v2 6/7] hw/ide/piix: Ignore writes of hardwired PCI command register bits,
Lev Kujawski <=
- [PATCH v2 7/7] hw/ide/core.c: Implement ATA INITIALIZE_DEVICE_PARAMETERS command, Lev Kujawski, 2022/07/06