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[Qemu-commits] [qemu/qemu] 2958e5: gicv3: fix ICH_MISR's LRENP computati
From: |
Richard Henderson |
Subject: |
[Qemu-commits] [qemu/qemu] 2958e5: gicv3: fix ICH_MISR's LRENP computation |
Date: |
Tue, 07 Dec 2021 11:03:35 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 2958e5150dfa297dd5a51fe57a29156b8744f07f
https://github.com/qemu/qemu/commit/2958e5150dfa297dd5a51fe57a29156b8744f07f
Author: Damien Hedde <damien.hedde@greensocs.com>
Date: 2021-12-07 (Tue, 07 Dec 2021)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
gicv3: fix ICH_MISR's LRENP computation
According to the "Arm Generic Interrupt Controller Architecture
Specification GIC architecture version 3 and 4" (version G: page 345
for aarch64 or 509 for aarch32):
LRENP bit of ICH_MISR is set when ICH_HCR.LRENPIE==1 and
ICH_HCR.EOIcount is non-zero.
When only LRENPIE was set (and EOI count was zero), the LRENP bit was
wrongly set and MISR value was wrong.
As an additional consequence, if an hypervisor set ICH_HCR.LRENPIE,
the maintenance interrupt was constantly fired. It happens since patch
9cee1efe92 ("hw/intc: Set GIC maintenance interrupt level to only 0 or 1")
which fixed another bug about maintenance interrupt (most significant
bits of misr, including this one, were ignored in the interrupt trigger).
Fixes: 83f036fe3d ("hw/intc/arm_gicv3: Add accessors for ICH_ system registers")
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20211207094427.3473-1-damien.hedde@greensocs.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: a216e7cf119c91ffdf5931834a1a030ebea40d70
https://github.com/qemu/qemu/commit/a216e7cf119c91ffdf5931834a1a030ebea40d70
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2021-12-07 (Tue, 07 Dec 2021)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
Merge tag 'pull-target-arm-20211207' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Fix calculation of ICH_MISR_EL2.LRENP to avoid incorrect generation
of maintenance interrupts
# gpg: Signature made Tue 07 Dec 2021 09:18:50 AM PST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
* tag 'pull-target-arm-20211207' of
https://git.linaro.org/people/pmaydell/qemu-arm:
gicv3: fix ICH_MISR's LRENP computation
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/92ac58e34c00...a216e7cf119c