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[Qemu-commits] [qemu/qemu] 2fa22a: hw: m25p80: add WP# pin and SRWD bit
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From: |
Richard Henderson |
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Subject: |
[Qemu-commits] [qemu/qemu] 2fa22a: hw: m25p80: add WP# pin and SRWD bit for write pro... |
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Date: |
Thu, 30 Jun 2022 18:28:16 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 2fa22a0f60f98739c4b3534d91826b68a51195ad
https://github.com/qemu/qemu/commit/2fa22a0f60f98739c4b3534d91826b68a51195ad
Author: Iris Chen <irischenlj@gmail.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/block/m25p80.c
Log Message:
-----------
hw: m25p80: add WP# pin and SRWD bit for write protection
Signed-off-by: Iris Chen <irischenlj@gmail.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-Id: <20220621202427.2680413-1-irischenlj@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 1de51272bf7f71ccf4b1503f5b1018ca6d429675
https://github.com/qemu/qemu/commit/1de51272bf7f71ccf4b1503f5b1018ca6d429675
Author: Iris Chen <irischenlj@fb.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M tests/qtest/aspeed_smc-test.c
Log Message:
-----------
hw: m25p80: add tests for write protect (WP# and SRWD bit)
Signed-off-by: Iris Chen <irischenlj@fb.com>
Message-Id: <20220624183016.2125264-1-irischenlj@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 346160cbf2af4d946fd6cf84ef1f4fc5f1a422af
https://github.com/qemu/qemu/commit/346160cbf2af4d946fd6cf84ef1f4fc5f1a422af
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
aspeed: Set the dram container at the SoC level
Currently, the Aspeed machines allocate a ram container region in
which the machine ram region is mapped. See commit ad1a9782186d
("aspeed: add a RAM memory region container"). An extra region is
mapped after ram in the ram container to catch invalid access done by
FW. That's how FW determines the size of ram. See commit ebe31c0a8ef7
("aspeed: add a max_ram_size property to the memory controller").
Let's move all the logic under the SoC where it should be. It will
also ease the work on multi SoC support.
Reviewed-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20220623202123.3972977-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 673a6d16ee1baa671f4e59a65cb7327b76df64ec
https://github.com/qemu/qemu/commit/673a6d16ee1baa671f4e59a65cb7327b76df64ec
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/misc/aspeed_scu.c
M hw/misc/trace-events
Log Message:
-----------
aspeed/scu: Add trace events for read ops
Reviewed-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20220628154740.1117349-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 6743af9b10cca1a436d8cfc6a15a15fa5de2b1fd
https://github.com/qemu/qemu/commit/6743af9b10cca1a436d8cfc6a15a15fa5de2b1fd
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/i2c/aspeed_i2c.c
Log Message:
-----------
aspeed/i2c: Change trace event for NORMAL_STOP states
Using a 'stop' string seems more appropriate than 'normal'.
Reviewed-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20220628154740.1117349-3-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 0dbf6dc5766837c3d398c2d9f1d1695f4782fd77
https://github.com/qemu/qemu/commit/0dbf6dc5766837c3d398c2d9f1d1695f4782fd77
Author: Joel Stanley <joel@jms.id.au>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/misc/aspeed_hace.c
Log Message:
-----------
aspeed/hace: Accumulative mode supported
While the HMAC mode is not modelled, the accumulative mode is.
Accumulative mode is enabled by setting one of the bits in the HMAC
engine command mode part of the register, so fix the unimplemented check
to only look at the upper of the two bits.
Fixes: 5cd7d8564a8b ("aspeed/hace: Support AST2600 HACE")
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220627100816.125956-1-joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 75dbf30be85f5163814b61aae87f93898d5fc53d
https://github.com/qemu/qemu/commit/75dbf30be85f5163814b61aae87f93898d5fc53d
Author: Cédric Le Goater <clg@kaod.org>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/ssi/aspeed_smc.c
Log Message:
-----------
aspeed/smc: Fix potential overflow
Coverity warns that "ssi_transfer(s->spi, 0U) << 8 * i" might overflow
because the expression is evaluated using 32-bit arithmetic and then
used in a context expecting a uint64_t.
Fixes: Coverity CID 1487244
Message-Id: <20220628165512.1133590-1-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: e37976d733f75eab74018e6632f29c0335a4ddcd
https://github.com/qemu/qemu/commit/e37976d733f75eab74018e6632f29c0335a4ddcd
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
Log Message:
-----------
aspeed: Set CPU memory property explicitly
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20220624003701.1363500-2-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 4dd9d55416695b651d8146e057acff8954bc203d
https://github.com/qemu/qemu/commit/4dd9d55416695b651d8146e057acff8954bc203d
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
aspeed: Add memory property to Aspeed SoC
Multi-SoC machines can use this property to specify a memory container
for each SoC. Single SoC machines will just specify get_system_memory().
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220624003701.1363500-3-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 5bfcbda70deffa64e80a011f31e0be7116cb1a66
https://github.com/qemu/qemu/commit/5bfcbda70deffa64e80a011f31e0be7116cb1a66
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
aspeed: Remove usage of sysbus_mmio_map
sysbus_mmio_map maps devices into "get_system_memory()".
With the new SoC memory attribute, we want to make sure that each device is
mapped into the SoC memory.
In single SoC machines, the SoC memory is the same as "get_system_memory()",
but in multi SoC machines it will be different.
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220624003701.1363500-4-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 80beb0856780394d73f7a3b5b7c76d78d05084ae
https://github.com/qemu/qemu/commit/80beb0856780394d73f7a3b5b7c76d78d05084ae
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
aspeed: Map unimplemented devices in SoC memory
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220624003701.1363500-5-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 85f0e0c3a1ced258ca9b984202a94cc82e7f757c
https://github.com/qemu/qemu/commit/85f0e0c3a1ced258ca9b984202a94cc82e7f757c
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/arm/aspeed_ast2600.c
Log Message:
-----------
aspeed: Remove use of qemu_get_cpu
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220624003701.1363500-6-pdel@fb.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: fb6b3c8d902ff0fd499bb995c0932cb59a5f1f44
https://github.com/qemu/qemu/commit/fb6b3c8d902ff0fd499bb995c0932cb59a5f1f44
Author: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: add support for the Qualcomm DC-SCM v1 board
Add qcom-dc-scm-v1 board support.
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220627154703.148943-2-quic_jaehyoo@quicinc.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: ece4cccd67749e9b0955159b89b48f645a6c5847
https://github.com/qemu/qemu/commit/ece4cccd67749e9b0955159b89b48f645a6c5847
Author: Graeme Gregory <quic_ggregory@quicinc.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: add Qualcomm Firework BMC machine
Add base for Qualcomm Firework BMC machine.
Signed-off-by: Graeme Gregory <quic_ggregory@quicinc.com>
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220627154703.148943-3-quic_jaehyoo@quicinc.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: dd0b3271e55d4017fd6cd6b4feb4da6ea6c5d1d7
https://github.com/qemu/qemu/commit/dd0b3271e55d4017fd6cd6b4feb4da6ea6c5d1d7
Author: Maheswara Kurapati <quic_mkurapat@quicinc.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/i2c/pmbus_device.c
Log Message:
-----------
hw/i2c: pmbus: Page #255 is valid page for read requests.
Current implementation of the pmbus core driver treats the read request
for page 255 as invalid request and sets the invalid command bit (bit 7)
in the STATUS_CML register. As per the PMBus specification it is a valid
request.
Refer to the PMBus specification, revision 1.3.1, section 11.10 PAGE,
on the page 58:
"Setting the PAGE to FFh means that all subsequent comands are to be
applied to all outputs.
Some commands, such as READ_TEMPERATURE, may use a common sensor but
be available on all pages of a device. Such implementations are the
decision of each device manufacturer or are specified in a PMBus
Application Profile. Consult the manufacturer's documents or the
Application Profile Specification as needed."
For e.g.,
The VOUT_MODE is a valid command for page 255 for maxim 31785 device.
refer to Table 1. PMBus Command Codes on page 14 in the datasheet.
https://datasheets.maximintegrated.com/en/ds/MAX31785.pdf
Fixes: 38870253f1d1 ("hw/i2c: pmbus: fix error returns and guard against out of
range accesses")
Signed-off-by: Maheswara Kurapati <quic_mkurapat@quicinc.com>
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Reviewed-by: Titus Rwantare <titusr@google.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220627154703.148943-4-quic_jaehyoo@quicinc.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 6236548284b3e1376984e3979f745daced546124
https://github.com/qemu/qemu/commit/6236548284b3e1376984e3979f745daced546124
Author: Maheswara Kurapati <quic_mkurapat@quicinc.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/sensor/Kconfig
A hw/sensor/max31785.c
M hw/sensor/meson.build
Log Message:
-----------
hw/sensor: add Maxim MAX31785 device
MAX31785 is a PMBus compliant 6-Channel fan controller. It supports 6 fan
channels, 11 temperature sensors, and 6-Channel ADC to measure the remote
voltages. Datasheet can be found here:
https://datasheets.maximintegrated.com/en/ds/MAX31785.pdf
This initial version of the driver has skeleton and support for the
fan channels. Requests for temperature sensors, and ADC Channels the
are serviced with the default values as per the datasheet. No additional
instrumentation is done. NV Log feature is not supported.
Signed-off-by: Maheswara Kurapati <quic_mkurapat@quicinc.com>
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220627154703.148943-5-quic_jaehyoo@quicinc.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 2a75e8c390c7e4fd071f51e688524c3dd8014f64
https://github.com/qemu/qemu/commit/2a75e8c390c7e4fd071f51e688524c3dd8014f64
Author: Maheswara Kurapati <quic_mkurapat@quicinc.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/arm/Kconfig
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: Add MAX31785 Fan controllers
Add MAX31785 fan controllers in machines so that the Linux driver
populates the sysfs interface.
Firework has two MAX31785 Fan controllers at 0x52, and 0x54 on bus 9.
Witherspoon has one at 0x52 on bus 3.
Rainier has one at 0x52 on bus 7.
Signed-off-by: Maheswara Kurapati <quic_mkurapat@quicinc.com>
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220627154703.148943-6-quic_jaehyoo@quicinc.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: cfc68f163992fe175d9ea58c247d1a7210613a66
https://github.com/qemu/qemu/commit/cfc68f163992fe175d9ea58c247d1a7210613a66
Author: Maheswara Kurapati <quic_mkurapat@quicinc.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: firework: Add Thermal Diodes
Add Thermal Diodes for Firework machine.
Signed-off-by: Maheswara Kurapati <quic_mkurapat@quicinc.com>
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220627154703.148943-7-quic_jaehyoo@quicinc.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 2a7a5d5cc40d736eb11baef43bd7ee2ebcb5582c
https://github.com/qemu/qemu/commit/2a7a5d5cc40d736eb11baef43bd7ee2ebcb5582c
Author: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: firework: add I2C MUXes for VR channels
Add 2-level cascaded I2C MUXes for SOC VR channels into the Firework
machine.
Signed-off-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220627154703.148943-8-quic_jaehyoo@quicinc.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: ceb3ff0e802bf7e373b1dbcff51541eefff25513
https://github.com/qemu/qemu/commit/ceb3ff0e802bf7e373b1dbcff51541eefff25513
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/i2c/aspeed_i2c.c
Log Message:
-----------
hw/i2c/aspeed: Fix R_I2CD_FUN_CTRL reference
Very minor, doesn't effect functionality, but this is supposed to be
R_I2CC_FUN_CTRL (new-mode, not old-mode).
Fixes: ba2cccd64e9 ("aspeed: i2c: Add new mode support")
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20220630045133.32251-2-me@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: b582b7a191f23c3f862c3b3aef96d6136508c07f
https://github.com/qemu/qemu/commit/b582b7a191f23c3f862c3b3aef96d6136508c07f
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/i2c/aspeed_i2c.c
Log Message:
-----------
hw/i2c/aspeed: Fix DMA len write-enable bit handling
I noticed i2c rx transfers were getting shortened to "1" on Zephyr. It
seems to be because the Zephyr i2c driver sets the RX DMA len with the
RX field write-enable bit set (bit 31) to avoid a read-modify-write. [1]
/* 0x1C : I2CM Master DMA Transfer Length Register */
I think we should be checking the write-enable bits on the incoming
value, not checking the register array. I'm not sure we're even writing
the write-enable bits to the register array, actually.
[1]
https://github.com/AspeedTech-BMC/zephyr/blob/db3dbcc9c52e67a47180890ac938ed380b33f91c/drivers/i2c/i2c_aspeed.c#L145-L148
Fixes: ba2cccd64e90f34 ("aspeed: i2c: Add new mode support")
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20220630045133.32251-3-me@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 0c0f1bee6a24cf36a019aefa26d849480a31c746
https://github.com/qemu/qemu/commit/0c0f1bee6a24cf36a019aefa26d849480a31c746
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/i2c/aspeed_i2c.c
Log Message:
-----------
hw/i2c/aspeed: Fix MASTER_EN missing error message
aspeed_i2c_bus_is_master is checking if master mode is enabled in the I2C
bus controller's function-control register, not that slave mode is enabled
or something. The error here is that the guest is trying to trigger an I2C
master mode command while master mode is not enabled.
Fixes: ba2cccd64e90f342 ("aspeed: i2c: Add new mode support")
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20220630045133.32251-4-me@pjd.dev>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 37fa5ca42623ef08ac99c8d927b6a3af0c76dc7b
https://github.com/qemu/qemu/commit/37fa5ca42623ef08ac99c8d927b6a3af0c76dc7b
Author: Klaus Jensen <k.jensen@samsung.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/i2c/core.c
M include/hw/i2c/i2c.h
Log Message:
-----------
hw/i2c: support multiple masters
Allow slaves to master the bus by registering a bottom halve. If the bus
is busy, the bottom half is queued up. When a slave has succesfully
mastered the bus, the bottom half is scheduled.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
[ clg : - fixed typos in commit log ]
Message-Id: <20220601210831.67259-4-its@irrelevant.dk>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220630045133.32251-5-me@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a78e9839ae5eb0b95d9db8dd672e2977d2831605
https://github.com/qemu/qemu/commit/a78e9839ae5eb0b95d9db8dd672e2977d2831605
Author: Klaus Jensen <k.jensen@samsung.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/arm/pxa2xx.c
M hw/display/sii9022.c
M hw/display/ssd0303.c
M hw/i2c/core.c
M hw/i2c/smbus_slave.c
M hw/i2c/trace-events
M hw/nvram/eeprom_at24c.c
M hw/sensor/lsm303dlhc_mag.c
M include/hw/i2c/i2c.h
Log Message:
-----------
hw/i2c: add asynchronous send
Add an asynchronous version of i2c_send() that requires the slave to
explicitly acknowledge on the bus with i2c_ack().
The current master must use the new i2c_start_send_async() to indicate
that it wants to do an asynchronous transfer. This allows the i2c core
to check if the target slave supports this or not. This approach relies
on adding a new enum i2c_event member, which is why a bunch of other
devices needs changes in their event handling switches.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
Message-Id: <20220601210831.67259-5-its@irrelevant.dk>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220630045133.32251-6-me@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: a8d48f59cd021b25359cc48cb8a897de7802f422
https://github.com/qemu/qemu/commit/a8d48f59cd021b25359cc48cb8a897de7802f422
Author: Klaus Jensen <k.jensen@samsung.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/i2c/aspeed_i2c.c
M include/hw/i2c/aspeed_i2c.h
Log Message:
-----------
hw/i2c/aspeed: add slave device in old register mode
Add slave mode functionality for the Aspeed I2C controller in old
register mode. This is implemented by realizing an I2C slave device
owned by the I2C controller and attached to its own bus.
The I2C slave device only implements asynchronous sends on the bus, so
slaves not supporting that will not be able to communicate with it.
Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
[ clg: checkpatch fixes ]
Message-Id: <20220601210831.67259-6-its@irrelevant.dk>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220630045133.32251-7-me@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 1c5d909f882ebd666224e3e1338a87616ebce4ed
https://github.com/qemu/qemu/commit/1c5d909f882ebd666224e3e1338a87616ebce4ed
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/i2c/aspeed_i2c.c
M include/hw/i2c/aspeed_i2c.h
Log Message:
-----------
hw/i2c/aspeed: Add new-registers DMA slave mode RX support
This commit adds support for DMA RX in slave mode while using the new
register set in the AST2600 and AST1030. This patch also pretty much
assumes packet mode is enabled, I'm not sure if this will work in DMA
step mode.
This is particularly useful for testing IPMB exchanges between Zephyr
and external devices, which requires multi-master I2C support and DMA in
the new register mode, because the Zephyr drivers from Aspeed use DMA in
the new mode by default. The Zephyr drivers are also using packet mode.
The typical sequence of events for receiving data in DMA slave + packet
mode is that the Zephyr firmware will configure the slave address
register with an address to receive on and configure the bus's function
control register to enable master mode and slave mode simultaneously at
startup, before any transfers are initiated.
RX DMA is enabled in the slave mode command register, and the slave RX
DMA buffer address and slave RX DMA buffer length are set. TX DMA is not
covered in this patch.
When the Aspeed I2C controller receives data from some other I2C master,
it will reset the I2CS_DMA_LEN RX_LEN value to zero, then buffer
incoming data in the RX DMA buffer while incrementing the I2CC_DMA_ADDR
address counter and decrementing the I2CC_DMA_LEN counter. It will also
update the I2CS_DMA_LEN RX_LEN value along the way.
Once all the data has been received, the bus controller will raise an
interrupt indicating a packet command was completed, the slave address
matched, a normal stop condition was seen, and the transfer was an RX
operation.
If the master sent a NACK instead of a normal stop condition, or the
transfer timed out, then a slightly different set of interrupt status
values would be set. Those conditions are not handled in this commit.
The Zephyr firmware then collects data from the RX DMA buffer and clears
the status register by writing the PKT_MODE_EN bit to the status
register. In packet mode, clearing the packet mode interrupt enable bit
also clears most of the other interrupt bits automatically (except for a
few bits above it).
Note: if the master transmit or receive functions were in use
simultaneously with the slave mode receive functionality, then the
master mode functions may have raised the interrupt line for the bus
before the DMA slave transfer is complete. It's important to have the
slave's interrupt status register clear throughout the receive
operation, and if the slave attempts to raise the interrupt before the
master interrupt status is cleared, then it needs to re-raise the
interrupt once the master interrupt status is cleared. (And vice-versa).
That's why in this commit, when the master interrupt status is cleared
and the interrupt line is lowered, we call the slave interrupt _raise_
function, to see if the interrupt was pending. (And again, vice-versa).
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Message-Id: <20220630045133.32251-8-me@pjd.dev>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: 55c57023b740c29151d42600af9ac43ba00e56cc
https://github.com/qemu/qemu/commit/55c57023b740c29151d42600af9ac43ba00e56cc
Author: Peter Delevoryas <pdel@fb.com>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
A hw/misc/aspeed_peci.c
M hw/misc/meson.build
M hw/misc/trace-events
M include/hw/arm/aspeed_soc.h
A include/hw/misc/aspeed_peci.h
Log Message:
-----------
hw/misc/aspeed: Add PECI controller
This introduces a really basic PECI controller that responses to
commands by always setting the response code to success and then raising
an interrupt to indicate the command is done. This helps avoid getting
hit with constant errors if the driver continuously attempts to send a
command and keeps timing out.
The AST2400 and AST2500 only included registers up to 0x5C, not 0xFC.
They supported PECI 1.1, 2.0, and 3.0. The AST2600 and AST1030 support
PECI 4.0, which includes more read/write buffer registers from 0x80 to
0xFC to support 64-byte mode.
This patch doesn't attempt to handle that, or to create a different
version of the controller for the different generations, since it's only
implementing functionality that is common to all generations.
The basic sequence of events is that the firmware will read and write to
various registers and then trigger a command by setting the FIRE bit in
the command register (similar to the I2C controller).
Then the firmware waits for an interrupt from the PECI controller,
expecting the interrupt status register to be filled in with info on
what happened. If the command was transmitted and received successfully,
then response codes from the host CPU will be found in the data buffer
registers.
Signed-off-by: Peter Delevoryas <pdel@fb.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220630045133.32251-12-me@pjd.dev>
[ clg: s/sysbus_mmio_map/aspeed_mmio_map/ ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Commit: d495e432c04a6394126c35cf96517749708b410f
https://github.com/qemu/qemu/commit/d495e432c04a6394126c35cf96517749708b410f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-06-30 (Thu, 30 Jun 2022)
Changed paths:
M hw/arm/Kconfig
M hw/arm/aspeed.c
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_soc.c
M hw/arm/pxa2xx.c
M hw/block/m25p80.c
M hw/display/sii9022.c
M hw/display/ssd0303.c
M hw/i2c/aspeed_i2c.c
M hw/i2c/core.c
M hw/i2c/pmbus_device.c
M hw/i2c/smbus_slave.c
M hw/i2c/trace-events
M hw/misc/aspeed_hace.c
A hw/misc/aspeed_peci.c
M hw/misc/aspeed_scu.c
M hw/misc/meson.build
M hw/misc/trace-events
M hw/nvram/eeprom_at24c.c
M hw/sensor/Kconfig
M hw/sensor/lsm303dlhc_mag.c
A hw/sensor/max31785.c
M hw/sensor/meson.build
M hw/ssi/aspeed_smc.c
M include/hw/arm/aspeed_soc.h
M include/hw/i2c/aspeed_i2c.h
M include/hw/i2c/i2c.h
A include/hw/misc/aspeed_peci.h
M tests/qtest/aspeed_smc-test.c
Log Message:
-----------
Merge tag 'pull-aspeed-20220630' of https://github.com/legoater/qemu into
staging
aspeed queue:
* m25p80 improvements (Iris)
* Code cleanup in preparation of multi SoC machine (Peter)
* New MAX31785 model (Mahesh)
* New Qualcomm machines (Jae and Graeme)
* Core I2C slave mode (Klaus)
* Aspeed I2C slave mode for old and new register interface (Peter and Klaus)
* New Aspeed PECI model (Peter)
* Various small fixes
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# gpg: Signature made Thu 30 Jun 2022 01:04:12 PM +0530
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20220630' of https://github.com/legoater/qemu: (27 commits)
hw/misc/aspeed: Add PECI controller
hw/i2c/aspeed: Add new-registers DMA slave mode RX support
hw/i2c/aspeed: add slave device in old register mode
hw/i2c: add asynchronous send
hw/i2c: support multiple masters
hw/i2c/aspeed: Fix MASTER_EN missing error message
hw/i2c/aspeed: Fix DMA len write-enable bit handling
hw/i2c/aspeed: Fix R_I2CD_FUN_CTRL reference
hw/arm/aspeed: firework: add I2C MUXes for VR channels
hw/arm/aspeed: firework: Add Thermal Diodes
hw/arm/aspeed: Add MAX31785 Fan controllers
hw/sensor: add Maxim MAX31785 device
hw/i2c: pmbus: Page #255 is valid page for read requests.
hw/arm/aspeed: add Qualcomm Firework BMC machine
hw/arm/aspeed: add support for the Qualcomm DC-SCM v1 board
aspeed: Remove use of qemu_get_cpu
aspeed: Map unimplemented devices in SoC memory
aspeed: Remove usage of sysbus_mmio_map
aspeed: Add memory property to Aspeed SoC
aspeed: Set CPU memory property explicitly
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/621745c4f349...d495e432c04a