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[Qemu-commits] [qemu/qemu] 7a867d: target/arm: Handle SME in aarch64_cpu
From: |
Richard Henderson |
Subject: |
[Qemu-commits] [qemu/qemu] 7a867d: target/arm: Handle SME in aarch64_cpu_dump_state |
Date: |
Mon, 11 Jul 2022 19:16:10 -0700 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 7a867dd57a480998361f5cc61ce83f342a020b0e
https://github.com/qemu/qemu/commit/7a867dd57a480998361f5cc61ce83f342a020b0e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Handle SME in aarch64_cpu_dump_state
Dump SVCR, plus use the correct access check for Streaming Mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e67cd1cac26181873496e5fb2464dbeb038e0fcd
https://github.com/qemu/qemu/commit/e67cd1cac26181873496e5fb2464dbeb038e0fcd
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/meson.build
A target/arm/sme.decode
M target/arm/translate-a64.c
M target/arm/translate-a64.h
A target/arm/translate-sme.c
Log Message:
-----------
target/arm: Add infrastructure for disas_sme
This includes the build rules for the decoder, and the
new file for translation, but excludes any instructions.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 75fe83564a2e41ac4bfcee72b1d9a590ddd46ebe
https://github.com/qemu/qemu/commit/75fe83564a2e41ac4bfcee72b1d9a590ddd46ebe
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/meson.build
A target/arm/sme-fa64.decode
M target/arm/translate-a64.c
M target/arm/translate-vfp.c
M target/arm/translate.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Trap non-streaming usage when Streaming SVE is active
This new behaviour is in the ARM pseudocode function
AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32
via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which
the trap would be delivered is in AArch64 mode.
Given that ARMv9 drops support for AArch32 outside EL0, the trap EL
detection ought to be trivially true, but the pseudocode still contains
a number of conditions, and QEMU has not yet committed to dropping A32
support for EL[12] when v9 features are present.
Since the computation of SME_TRAP_NONSTREAMING is necessarily different
for the two modes, we might as well preserve bits within TBFLAG_ANY and
allocate separate bits within TBFLAG_A32 and TBFLAG_A64 instead.
Note that DDI0616A.a has typos for bits [22:21] of LD1RO in the table
of instructions illegal in streaming mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7160c8c55acfa1f1acfb376c4d03f3580e192e6b
https://github.com/qemu/qemu/commit/7160c8c55acfa1f1acfb376c4d03f3580e192e6b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/sme-fa64.decode
M target/arm/translate-sve.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Mark ADR as non-streaming
Mark ADR as a non-streaming instruction, which should trap
if full a64 support is not enabled in streaming mode.
Removing entries from sme-fa64.decode is an easy way to see
what remains to be done.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 39001c6b9bc71320b76d708e6a12f77432a283ab
https://github.com/qemu/qemu/commit/39001c6b9bc71320b76d708e6a12f77432a283ab
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/sme-fa64.decode
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Mark RDFFR, WRFFR, SETFFR as non-streaming
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ca363d233f67e5bbbb41d0aefcbf130d04e750e9
https://github.com/qemu/qemu/commit/ca363d233f67e5bbbb41d0aefcbf130d04e750e9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/sme-fa64.decode
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streaming
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4464ee363441d686487aa641d0110348c8283dda
https://github.com/qemu/qemu/commit/4464ee363441d686487aa641d0110348c8283dda
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/sme-fa64.decode
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Mark PMULL, FMMLA as non-streaming
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7272e98a748041118437c8aedcdd4f68838d4869
https://github.com/qemu/qemu/commit/7272e98a748041118437c8aedcdd4f68838d4869
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/sme-fa64.decode
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Mark FTSMUL, FTMAD, FADDA as non-streaming
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d79f3d5f2ffa15a107f75f74d320c10bf045a4d3
https://github.com/qemu/qemu/commit/d79f3d5f2ffa15a107f75f74d320c10bf045a4d3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/sme-fa64.decode
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Mark SMMLA, UMMLA, USMMLA as non-streaming
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 46feb3615106ac9257ce040cfff9543fb1da9ff6
https://github.com/qemu/qemu/commit/46feb3615106ac9257ce040cfff9543fb1da9ff6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/sme-fa64.decode
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Mark string/histo/crypto as non-streaming
Mark these as non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 765ff97df3411522641d27401845a097f0c07422
https://github.com/qemu/qemu/commit/765ff97df3411522641d27401845a097f0c07422
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/sme-fa64.decode
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Mark gather/scatter load/store as non-streaming
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e1d1a64326634a3bd4c4e93ffeea1c970bb152ff
https://github.com/qemu/qemu/commit/e1d1a64326634a3bd4c4e93ffeea1c970bb152ff
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/sme-fa64.decode
M target/arm/sve.decode
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Mark gather prefetch as non-streaming
Mark these as a non-streaming instructions, which should trap if full
a64 support is not enabled in streaming mode. In this case, introduce
PRF_ns (prefetch non-streaming) to handle the checks.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ccb1cefc3858a800986d88bddbeb781b236b0e63
https://github.com/qemu/qemu/commit/ccb1cefc3858a800986d88bddbeb781b236b0e63
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/sme-fa64.decode
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Mark LDFF1 and LDNF1 as non-streaming
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3ebc26e79d05cf53129e283529cf3bc8a5c5953e
https://github.com/qemu/qemu/commit/3ebc26e79d05cf53129e283529cf3bc8a5c5953e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/sme-fa64.decode
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Mark LD1RO as non-streaming
Mark these as a non-streaming instructions, which should trap
if full a64 support is not enabled in streaming mode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3d74825f4d68a54cf1cd772dda8b502695b2d783
https://github.com/qemu/qemu/commit/3d74825f4d68a54cf1cd772dda8b502695b2d783
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/translate-a64.c
M target/arm/translate-a64.h
Log Message:
-----------
target/arm: Add SME enablement checks
These functions will be used to verify that the cpu
is in the correct state for a given instruction.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-16-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 285b1d5fcef3ef352333f08bde669551054fbee4
https://github.com/qemu/qemu/commit/285b1d5fcef3ef352333f08bde669551054fbee4
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/translate-a64.c
Log Message:
-----------
target/arm: Handle SME in sve_access_check
The pseudocode for CheckSVEEnabled gains a check for Streaming
SVE mode, and for SME present but SVE absent.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-17-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 0d935760346b7ea07cbf5f63667151198012c922
https://github.com/qemu/qemu/commit/0d935760346b7ea07cbf5f63667151198012c922
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/sve.decode
M target/arm/translate-a64.h
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement SME RDSVL, ADDSVL, ADDSPL
These SME instructions are nominally within the SVE decode space,
so we add them to sve.decode and translate-sve.c.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-18-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ad939afbfa4a0709d44d5806576607154a7489a8
https://github.com/qemu/qemu/commit/ad939afbfa4a0709d44d5806576607154a7489a8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/helper-sme.h
M target/arm/sme.decode
M target/arm/sme_helper.c
M target/arm/translate-sme.c
Log Message:
-----------
target/arm: Implement SME ZERO
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e9ad3ef19ee4af62152fdc7f1150bf59a7f997d0
https://github.com/qemu/qemu/commit/e9ad3ef19ee4af62152fdc7f1150bf59a7f997d0
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/helper-sme.h
M target/arm/helper-sve.h
M target/arm/sme.decode
M target/arm/sme_helper.c
M target/arm/sve_helper.c
M target/arm/translate-a64.h
M target/arm/translate-sme.c
M target/arm/translate.h
Log Message:
-----------
target/arm: Implement SME MOVA
We can reuse the SVE functions for implementing moves to/from
horizontal tile slices, but we need new ones for moves to/from
vertical tile slices.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7390e0e9ab8475b7d291b70b05d484827ec9f3e2
https://github.com/qemu/qemu/commit/7390e0e9ab8475b7d291b70b05d484827ec9f3e2
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/helper-sme.h
M target/arm/sme.decode
M target/arm/sme_helper.c
M target/arm/translate-sme.c
Log Message:
-----------
target/arm: Implement SME LD1, ST1
We cannot reuse the SVE functions for LD[1-4] and ST[1-4],
because those functions accept only a Zreg register number.
For SME, we want to pass a pointer into ZA storage.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8713f73e5338469d07c3e95a8dc9bbece919974b
https://github.com/qemu/qemu/commit/8713f73e5338469d07c3e95a8dc9bbece919974b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/translate-a64.h
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Export unpredicated ld/st from translate-sve.c
Add a TCGv_ptr base argument, which will be cpu_env for SVE.
We will reuse this for SME save and restore array insns.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-22-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4c46a5f12c1802f79a4ed98fff8ff10d8e8c32ea
https://github.com/qemu/qemu/commit/4c46a5f12c1802f79a4ed98fff8ff10d8e8c32ea
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/sme.decode
M target/arm/translate-sme.c
Log Message:
-----------
target/arm: Implement SME LDR, STR
We can reuse the SVE functions for LDR and STR, passing in the
base of the ZA vector and a zero offset.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: bc4420d9bd8ea2c8a7162256b319a27630d2895a
https://github.com/qemu/qemu/commit/bc4420d9bd8ea2c8a7162256b319a27630d2895a
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/helper-sme.h
M target/arm/sme.decode
M target/arm/sme_helper.c
M target/arm/translate-sme.c
Log Message:
-----------
target/arm: Implement SME ADDHA, ADDVA
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 558e956c71929f3ed2d571ff14ea067b5655bd24
https://github.com/qemu/qemu/commit/558e956c71929f3ed2d571ff14ea067b5655bd24
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/helper-sme.h
M target/arm/sme.decode
M target/arm/sme_helper.c
M target/arm/translate-sme.c
Log Message:
-----------
target/arm: Implement FMOPA, FMOPS (non-widening)
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-25-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 920f640d39970cfd4753cbbb091e76531e28134b
https://github.com/qemu/qemu/commit/920f640d39970cfd4753cbbb091e76531e28134b
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/helper-sme.h
M target/arm/sme.decode
M target/arm/sme_helper.c
M target/arm/translate-sme.c
Log Message:
-----------
target/arm: Implement BFMOPA, BFMOPS
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-26-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3916841ac75e74f54fb8cce0292e7e1e9851fb22
https://github.com/qemu/qemu/commit/3916841ac75e74f54fb8cce0292e7e1e9851fb22
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/helper-sme.h
M target/arm/sme.decode
M target/arm/sme_helper.c
M target/arm/translate-sme.c
Log Message:
-----------
target/arm: Implement FMOPA, FMOPS (widening)
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-27-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 23a5e3859f55c11018f046957dbbbbbbbba39b28
https://github.com/qemu/qemu/commit/23a5e3859f55c11018f046957dbbbbbbbba39b28
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/helper-sme.h
M target/arm/sme.decode
M target/arm/sme_helper.c
M target/arm/translate-sme.c
Log Message:
-----------
target/arm: Implement SME integer outer product
This is SMOPA, SUMOPA, USMOPA_s, UMOPA, for both Int8 and Int16.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-28-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 598ab0b24c0cb807b3f380ab422915dd6c229026
https://github.com/qemu/qemu/commit/598ab0b24c0cb807b3f380ab422915dd6c229026
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/sve.decode
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement PSEL
This is an SVE instruction that operates using the SVE vector
length but that it is present only if SME is implemented.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-29-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 7dbfafc157290b52af6109b82b8398d10ef5c3b3
https://github.com/qemu/qemu/commit/7dbfafc157290b52af6109b82b8398d10ef5c3b3
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/helper-sve.h
M target/arm/sve.decode
M target/arm/sve_helper.c
M target/arm/translate-sve.c
Log Message:
-----------
target/arm: Implement REVD
This is an SVE instruction that operates using the SVE vector
length but that it is present only if SME is implemented.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-30-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 6b5a3bdf3a71ab3f3bc1e9665ea54ca47c0455ec
https://github.com/qemu/qemu/commit/6b5a3bdf3a71ab3f3bc1e9665ea54ca47c0455ec
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/helper.h
M target/arm/sve.decode
M target/arm/translate-sve.c
M target/arm/vec_helper.c
Log Message:
-----------
target/arm: Implement SCLAMP, UCLAMP
This is an SVE instruction that operates using the SVE vector
length but that it is present only if SME is implemented.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-31-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 04fbce7639b7461d6d18f5ebf352fa80c5e94f5d
https://github.com/qemu/qemu/commit/04fbce7639b7461d6d18f5ebf352fa80c5e94f5d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Reset streaming sve state on exception boundaries
We can handle both exception entry and exception return by
hooking into aarch64_sve_change_el.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-32-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 78cb9776662adc62881fd5d7cc44cd925a3010c9
https://github.com/qemu/qemu/commit/78cb9776662adc62881fd5d7cc44cd925a3010c9
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu64.c
Log Message:
-----------
target/arm: Enable SME for -cpu max
Note that SME remains effectively disabled for user-only,
because we do not yet set CPACR_EL1.SMEN. This needs to
wait until the kernel ABI is implemented.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-33-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 95aa4fdd58c50ba1d800bb106d73ef8a656e016e
https://github.com/qemu/qemu/commit/95aa4fdd58c50ba1d800bb106d73ef8a656e016e
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M linux-user/aarch64/target_cpu.h
Log Message:
-----------
linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-34-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 2a98579711cfba611fbf2afdba6783c35c7d9850
https://github.com/qemu/qemu/commit/2a98579711cfba611fbf2afdba6783c35c7d9850
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M linux-user/aarch64/cpu_loop.c
Log Message:
-----------
linux-user/aarch64: Reset PSTATE.SM on syscalls
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-35-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4a29c36316b58a232715cbf8185dec28a681892c
https://github.com/qemu/qemu/commit/4a29c36316b58a232715cbf8185dec28a681892c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M linux-user/aarch64/signal.c
Log Message:
-----------
linux-user/aarch64: Add SM bit to SVE signal context
Make sure to zero the currently reserved fields.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-36-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 5726597c3bab1653c8707ec964832eac46bdea37
https://github.com/qemu/qemu/commit/5726597c3bab1653c8707ec964832eac46bdea37
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M linux-user/aarch64/signal.c
Log Message:
-----------
linux-user/aarch64: Tidy target_restore_sigframe error return
Fold the return value setting into the goto, so each
point of failure need not do both.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-37-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: affb1a50b95b0d523868db759038bb0ff915a906
https://github.com/qemu/qemu/commit/affb1a50b95b0d523868db759038bb0ff915a906
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M linux-user/aarch64/signal.c
Log Message:
-----------
linux-user/aarch64: Do not allow duplicate or short sve records
In parse_user_sigframe, the kernel rejects duplicate sve records,
or records that are smaller than the header. We were silently
allowing these cases to pass, dropping the record.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-38-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 8e5e19ee4193acfe17ce43e708c79211c11f5779
https://github.com/qemu/qemu/commit/8e5e19ee4193acfe17ce43e708c79211c11f5779
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M linux-user/aarch64/signal.c
Log Message:
-----------
linux-user/aarch64: Verify extra record lock succeeded
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-39-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: d3b4f7170f7cb0987b83f70e15bfdc13e820d56d
https://github.com/qemu/qemu/commit/d3b4f7170f7cb0987b83f70e15bfdc13e820d56d
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M linux-user/aarch64/signal.c
Log Message:
-----------
linux-user/aarch64: Move sve record checks into restore
Move the checks out of the parsing loop and into the
restore function. This more closely mirrors the code
structure in the kernel, and is slightly clearer.
Reject rather than silently skip incorrect VL and SVE record sizes,
bringing our checks in to line with those the kernel does.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-40-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 78fd56ba13a472d20975d4bca1633b3dccd70954
https://github.com/qemu/qemu/commit/78fd56ba13a472d20975d4bca1633b3dccd70954
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M linux-user/aarch64/signal.c
Log Message:
-----------
linux-user/aarch64: Implement SME signal handling
Set the SM bit in the SVE record on signal delivery, create the ZA record.
Restore SM and ZA state according to the records present on return.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-41-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fd72f5d0bae2bcdb695cb8da57b41c49c001f91f
https://github.com/qemu/qemu/commit/fd72f5d0bae2bcdb695cb8da57b41c49c001f91f
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M linux-user/aarch64/target_prctl.h
M linux-user/syscall.c
Log Message:
-----------
linux-user: Rename sve prctls
Add "sve" to the sve prctl functions, to distinguish
them from the coming "sme" prctls with similar names.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-42-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 24d87c187c46a935f2b6bd7194d9958fb28be786
https://github.com/qemu/qemu/commit/24d87c187c46a935f2b6bd7194d9958fb28be786
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M linux-user/aarch64/target_prctl.h
M linux-user/syscall.c
Log Message:
-----------
linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL
These prctl set the Streaming SVE vector length, which may
be completely different from the Normal SVE vector length.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-43-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 4630353559fc1924c5f692aacb0d52e7e9ba5f5c
https://github.com/qemu/qemu/commit/4630353559fc1924c5f692aacb0d52e7e9ba5f5c
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Only set ZEN in reset if SVE present
There's no reason to set CPACR_EL1.ZEN if SVE disabled.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-44-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 78011586b90d1d72bd14bacfdfcec1b4b9ab6114
https://github.com/qemu/qemu/commit/78011586b90d1d72bd14bacfdfcec1b4b9ab6114
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Enable SME for user-only
Enable SME, TPIDR2_EL0, and FA64 if supported by the cpu.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-45-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f9982ceaf26df27d15547a3a7990a95019e9e3a8
https://github.com/qemu/qemu/commit/f9982ceaf26df27d15547a3a7990a95019e9e3a8
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M linux-user/elfload.c
Log Message:
-----------
linux-user/aarch64: Add SME related hwcap entries
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220708151540.18136-46-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 9fed1bca6bc643ce91b6117f4974421aaede4751
https://github.com/qemu/qemu/commit/9fed1bca6bc643ce91b6117f4974421aaede4751
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2022-07-11 (Mon, 11 Jul 2022)
Changed paths:
M docs/system/arm/emulation.rst
M linux-user/aarch64/cpu_loop.c
M linux-user/aarch64/signal.c
M linux-user/aarch64/target_cpu.h
M linux-user/aarch64/target_prctl.h
M linux-user/elfload.c
M linux-user/syscall.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper-sme.h
M target/arm/helper-sve.h
M target/arm/helper.c
M target/arm/helper.h
M target/arm/meson.build
A target/arm/sme-fa64.decode
A target/arm/sme.decode
M target/arm/sme_helper.c
M target/arm/sve.decode
M target/arm/sve_helper.c
M target/arm/translate-a64.c
M target/arm/translate-a64.h
A target/arm/translate-sme.c
M target/arm/translate-sve.c
M target/arm/translate-vfp.c
M target/arm/translate.c
M target/arm/translate.h
M target/arm/vec_helper.c
Log Message:
-----------
Merge tag 'pull-target-arm-20220711' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm:
* Implement SME emulation, for both system and linux-user
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# uu+gSmYoToLhC35Uan5otg==
# =D1/T
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 11 Jul 2022 07:27:03 PM +0530
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[full]
* tag 'pull-target-arm-20220711' of
https://git.linaro.org/people/pmaydell/qemu-arm: (45 commits)
linux-user/aarch64: Add SME related hwcap entries
target/arm: Enable SME for user-only
target/arm: Only set ZEN in reset if SVE present
linux-user/aarch64: Implement PR_SME_GET_VL, PR_SME_SET_VL
linux-user: Rename sve prctls
linux-user/aarch64: Implement SME signal handling
linux-user/aarch64: Move sve record checks into restore
linux-user/aarch64: Verify extra record lock succeeded
linux-user/aarch64: Do not allow duplicate or short sve records
linux-user/aarch64: Tidy target_restore_sigframe error return
linux-user/aarch64: Add SM bit to SVE signal context
linux-user/aarch64: Reset PSTATE.SM on syscalls
linux-user/aarch64: Clear tpidr2_el0 if CLONE_SETTLS
target/arm: Enable SME for -cpu max
target/arm: Reset streaming sve state on exception boundaries
target/arm: Implement SCLAMP, UCLAMP
target/arm: Implement REVD
target/arm: Implement PSEL
target/arm: Implement SME integer outer product
target/arm: Implement FMOPA, FMOPS (widening)
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Compare: https://github.com/qemu/qemu/compare/63b38f6c85ac...9fed1bca6bc6