[Qemu-commits] [qemu/qemu] fe68cc: target/hexagon: don't look for static glib

[Richard Henderson]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: fe68cc0923ebfa0c12e4176f61ec9b363a07a73a
      
https://github.com/qemu/qemu/commit/fe68cc0923ebfa0c12e4176f61ec9b363a07a73a
  Author: Alyssa Ross <hi@alyssa.is>
  Date:   2024-08-13 (Tue, 13 Aug 2024)

  Changed paths:
    M target/hexagon/meson.build

  Log Message:
  -----------
  target/hexagon: don't look for static glib

When cross compiling QEMU configured with --static, I've been getting
configure errors like the following:

    Build-time dependency glib-2.0 found: NO

    ../target/hexagon/meson.build:303:15: ERROR: Dependency lookup for glib-2.0 
with method 'pkgconfig' failed: Could not generate libs for glib-2.0:
    Package libpcre2-8 was not found in the pkg-config search path.
    Perhaps you should add the directory containing `libpcre2-8.pc'
    to the PKG_CONFIG_PATH environment variable
    Package 'libpcre2-8', required by 'glib-2.0', not found

This happens because --static sets the prefer_static Meson option, but
my build machine doesn't have a static libpcre2.  I don't think it
makes sense to insist that native dependencies are static, just
because I want the non-native QEMU binaries to be static.

Signed-off-by: Alyssa Ross <hi@alyssa.is>
Link: https://lore.kernel.org/r/20240805104921.4035256-1-hi@alyssa.is
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: 416f2b16c02c618c0f233372ebfe343f9ee667d4
      
https://github.com/qemu/qemu/commit/416f2b16c02c618c0f233372ebfe343f9ee667d4
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-08-13 (Tue, 13 Aug 2024)

  Changed paths:
    M target/i386/tcg/decode-new.c.inc

  Log Message:
  -----------
  target/i386: Do not apply REX to MMX operands

Cc: qemu-stable@nongnu.org
Fixes: b3e22b2318a ("target/i386: add core of new i386 decoder")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2495
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Link: 
https://lore.kernel.org/r/20240812025844.58956-2-richard.henderson@linaro.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: 45230bca852f0a8c3a6bd9cb84e621bcde1c7e9a
      
https://github.com/qemu/qemu/commit/45230bca852f0a8c3a6bd9cb84e621bcde1c7e9a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-08-13 (Tue, 13 Aug 2024)

  Changed paths:
    M target/i386/tcg/decode-new.c.inc

  Log Message:
  -----------
  target/i386: Use unit not type in decode_modrm

Rather that enumerating the types that can produce
MMX operands, examine the unit.  No functional change.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: 
https://lore.kernel.org/r/20240812025844.58956-3-richard.henderson@linaro.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: 20516e8d0e07739bd2e9bc8f51f319e37a9bc86c
      
https://github.com/qemu/qemu/commit/20516e8d0e07739bd2e9bc8f51f319e37a9bc86c
  Author: Zheyu Ma <zheyuma97@gmail.com>
  Date:   2024-08-13 (Tue, 13 Aug 2024)

  Changed paths:
    M hw/misc/stm32l4x5_rcc.c

  Log Message:
  -----------
  hw/misc/stm32l4x5_rcc: Add validation for MCOPRE and MCOSEL values

This commit adds validation checks for the MCOPRE and MCOSEL values in
the rcc_update_cfgr_register function. If the MCOPRE value exceeds
0b100 or the MCOSEL value exceeds 0b111, an error is logged and the
corresponding clock mux is disabled. This helps in identifying and
handling invalid configurations in the RCC registers.

Reproducer:
cat << EOF | qemu-system-aarch64 -display \
none -machine accel=qtest, -m 512M -machine b-l475e-iot01a -qtest \
stdio
writeq 0x40021008 0xffffffff
EOF

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2356
Signed-off-by: Zheyu Ma <zheyuma97@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 8e0c9a9efa21a16190cbac288e414bbf1d80f639
      
https://github.com/qemu/qemu/commit/8e0c9a9efa21a16190cbac288e414bbf1d80f639
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-08-13 (Tue, 13 Aug 2024)

  Changed paths:
    M target/arm/tcg/translate-a64.c

  Log Message:
  -----------
  target/arm: Clear high SVE elements in handle_vec_simd_wshli

AdvSIMD instructions are supposed to zero bits beyond 128.
Affects SSHLL, USHLL, SSHLL2, USHLL2.

Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240717060903.205098-15-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>


  Commit: 150c24f34e9c3388c0f0ad04ddd997e5559db800
      
https://github.com/qemu/qemu/commit/150c24f34e9c3388c0f0ad04ddd997e5559db800
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-08-13 (Tue, 13 Aug 2024)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Update translation regime comment for new features

We have a long comment describing the Arm architectural translation
regimes and how we map them to QEMU MMU indexes.  This comment has
got a bit out of date:

 * FEAT_SEL2 allows Secure EL2 and corresponding new regimes
 * FEAT_RME introduces Realm state and its translation regimes
 * We now model the Cortex-R52 so that is no longer a hypothetical
 * We separated Secure Stage 2 and NonSecure Stage 2 MMU indexes
 * We have an MMU index per physical address spacea

Add the missing pieces so that the list of architectural translation
regimes matches the Arm ARM, and the list and count of QEMU MMU
indexes in the comment matches the enum.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240809160430.1144805-2-peter.maydell@linaro.org


  Commit: 4c2c0474693229c1f533239bb983495c5427784d
      
https://github.com/qemu/qemu/commit/4c2c0474693229c1f533239bb983495c5427784d
  Author: Peter Maydell <peter.maydell@linaro.org>
  Date:   2024-08-13 (Tue, 13 Aug 2024)

  Changed paths:
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/ptw.c
    M target/arm/tcg/hflags.c
    M target/arm/tcg/translate-a64.c
    M target/arm/tcg/translate.c
    M target/arm/tcg/translate.h

  Log Message:
  -----------
  target/arm: Fix usage of MMU indexes when EL3 is AArch32

Our current usage of MMU indexes when EL3 is AArch32 is confused.
Architecturally, when EL3 is AArch32, all Secure code runs under the
Secure PL1&0 translation regime:
 * code at EL3, which might be Mon, or SVC, or any of the
   other privileged modes (PL1)
 * code at EL0 (Secure PL0)

This is different from when EL3 is AArch64, in which case EL3 is its
own translation regime, and EL1 and EL0 (whether AArch32 or AArch64)
have their own regime.

We claimed to be mapping Secure PL1 to our ARMMMUIdx_EL3, but didn't
do anything special about Secure PL0, which meant it used the same
ARMMMUIdx_EL10_0 that NonSecure PL0 does.  This resulted in a bug
where arm_sctlr() incorrectly picked the NonSecure SCTLR as the
controlling register when in Secure PL0, which meant we were
spuriously generating alignment faults because we were looking at the
wrong SCTLR control bits.

The use of ARMMMUIdx_EL3 for Secure PL1 also resulted in the bug that
we wouldn't honour the PAN bit for Secure PL1, because there's no
equivalent _PAN mmu index for it.

We could fix this in one of two ways:
 * The most straightforward is to add new MMU indexes EL30_0,
   EL30_3, EL30_3_PAN to correspond to "Secure PL1&0 at PL0",
   "Secure PL1&0 at PL1", and "Secure PL1&0 at PL1 with PAN".
   This matches how we use indexes for the AArch64 regimes, and
   preserves propirties like being able to determine the privilege
   level from an MMU index without any other information. However
   it would add two MMU indexes (we can share one with ARMMMUIdx_EL3),
   and we are already using 14 of the 16 the core TLB code permits.

 * The more complicated approach is the one we take here. We use
   the same MMU indexes (E10_0, E10_1, E10_1_PAN) for Secure PL1&0
   than we do for NonSecure PL1&0. This saves on MMU indexes, but
   means we need to check in some places whether we're in the
   Secure PL1&0 regime or not before we interpret an MMU index.

The changes in this commit were created by auditing all the places
where we use specific ARMMMUIdx_ values, and checking whether they
needed to be changed to handle the new index value usage.

Note for potential stable backports: taking also the previous
(comment-change-only) commit might make the backport easier.

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2326
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20240809160430.1144805-3-peter.maydell@linaro.org


  Commit: 7700d2293c085c0481b71cc0f8c04ca20e7bd7d3
      
https://github.com/qemu/qemu/commit/7700d2293c085c0481b71cc0f8c04ca20e7bd7d3
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-08-13 (Tue, 13 Aug 2024)

  Changed paths:
    M target/i386/tcg/emit.c.inc

  Log Message:
  -----------
  target/i386: Assert MMX and XMM registers in range

The mmx assert would fire without the fix for #2495.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Link: 
https://lore.kernel.org/r/20240812025844.58956-4-richard.henderson@linaro.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: 940d802b24e63650e0eacad3714e2ce171cba17c
      
https://github.com/qemu/qemu/commit/940d802b24e63650e0eacad3714e2ce171cba17c
  Author: Alexander Ivanov <alexander.ivanov@virtuozzo.com>
  Date:   2024-08-13 (Tue, 13 Aug 2024)

  Changed paths:
    M util/module.c

  Log Message:
  -----------
  module: Prevent crash by resetting local_err in module_load_qom_all()

Set local_err to NULL after it has been freed in error_report_err(). This
avoids triggering assert(*errp == NULL) failure in error_setv() when
local_err is reused in the loop.

Signed-off-by: Alexander Ivanov <alexander.ivanov@virtuozzo.com>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Reviewed-by: Denis V. Lunev <den@openvz.org>
Link: 
https://lore.kernel.org/r/20240809121340.992049-2-alexander.ivanov@virtuozzo.com
[Do the same by moving the declaration instead. - Paolo]
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: 3ef11c991e501768f2fa646e8438f075be1cd2f5
      
https://github.com/qemu/qemu/commit/3ef11c991e501768f2fa646e8438f075be1cd2f5
  Author: Paolo Bonzini <pbonzini@redhat.com>
  Date:   2024-08-13 (Tue, 13 Aug 2024)

  Changed paths:
    M po/it.po

  Log Message:
  -----------
  po: update Italian translation

Reported-by: bovirus <https://gitlab.com/bovirus>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2451
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>


  Commit: 3cc050c54008d4e2a12ad3f4dbec9e24ad27bf1a
      
https://github.com/qemu/qemu/commit/3cc050c54008d4e2a12ad3f4dbec9e24ad27bf1a
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-08-14 (Wed, 14 Aug 2024)

  Changed paths:
    M hw/misc/stm32l4x5_rcc.c
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/internals.h
    M target/arm/ptw.c
    M target/arm/tcg/hflags.c
    M target/arm/tcg/translate-a64.c
    M target/arm/tcg/translate.c
    M target/arm/tcg/translate.h

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20240813' of 
https://git.linaro.org/people/pmaydell/qemu-arm into staging

target-arm queue:
 * hw/misc/stm32l4x5_rcc: Add validation for MCOPRE and MCOSEL values
 * target/arm: Clear high SVE elements in handle_vec_simd_wshli
 * target/arm: Fix usage of MMU indexes when EL3 is AArch32

# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAma7eSIZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3gbJEACHhZAvP4f1vic8DNGPw8Yr
# v+pRQON+vF+PDBSyNkYCRL5Gy1P257Aujw1ed2dpoDhMemC/co67W2zdzToCvDd5
# XZxlHb/iUCTeZbA/Zp66ZADlvVOdvvQL8EHbd4mSBEZp9rvPSmxatx4I5jstLiAV
# 5HimP+AjjGMfklMu+RelW7A7WDRJ0h7F4PwXCA8tLeHPH5XHSkweGYt3OVfSlUAs
# +RKiltByC/quujLHxrQcVtLZON1KKiB0P8VPRcaR1QIFARiR1IfLvzhKVpqyOlnV
# 3a+ZILtCJE1YEM+h7Aunz/l9MQ0DZe5DzbIdKOQ7NUkerlhq81kriPp67yLv25lk
# zgqkHGGDEnIGpSXdmbXTNLcGlH+5O+fWl2RMzYrSFJqvwyRu9egLLi6E0xaNCRvY
# gdb6CGPhhu21C1o5Nax0CiaZe3vzzRvC5QsIJ0yww6y7VaGFVt/XRaKBdLHB97nZ
# t/9ifa3fmhVEW6pQEy8VdAeFoxIT2lJ2xJgBdMwpZCJlCxB8xKU/rZfrXKS/UUqV
# 9Klbcfrx1WFT7zrAWS0Ig7nPttJ+XgjYfgHI3q2e80F6xRmAmaAjnbtVRS+L3It9
# eZ4SmuzurWipRLpdmxdOX1IXdZD9rJMzk9IUIZoklctlR/D+75Iuy0N7gY8G2dbp
# fmh38lEQZ0IC90VmNtWltw==
# =So/3
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 14 Aug 2024 01:17:54 AM AEST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [full]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" 
[full]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]

* tag 'pull-target-arm-20240813' of 
https://git.linaro.org/people/pmaydell/qemu-arm:
  target/arm: Fix usage of MMU indexes when EL3 is AArch32
  target/arm: Update translation regime comment for new features
  target/arm: Clear high SVE elements in handle_vec_simd_wshli
  hw/misc/stm32l4x5_rcc: Add validation for MCOPRE and MCOSEL values

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


  Commit: a733f37aef3b7d1d33bfe2716af88cdfd67ba64e
      
https://github.com/qemu/qemu/commit/a733f37aef3b7d1d33bfe2716af88cdfd67ba64e
  Author: Richard Henderson <richard.henderson@linaro.org>
  Date:   2024-08-14 (Wed, 14 Aug 2024)

  Changed paths:
    M po/it.po
    M target/hexagon/meson.build
    M target/i386/tcg/decode-new.c.inc
    M target/i386/tcg/emit.c.inc
    M util/module.c

  Log Message:
  -----------
  Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging

* fix --static compilation of hexagon
* fix incorrect application of REX to MMX operands
* fix crash on module load
* update Italian translation

# -----BEGIN PGP SIGNATURE-----
#
# iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAma7kZ4UHHBib256aW5p
# QHJlZGhhdC5jb20ACgkQv/vSX3jHroOy7QgAriuxfgw3Yvu9UPPfEZT5V9p5XfDf
# LceO3C6OABIkFoGSO8WK5dWfQy3oYbrwEXX/l/PW1lUc2DFrSUo9YtIfjelRkxoC
# 0EAAbV5A+xCLYmujFqBSe/6usRj82uKjSET1KK1aCam7ONZLNZf2yb4OwdShvLSN
# MPgtBOrwznR1qh3KJtLB6YSRC0Rie1hOxbXFpx1AklXYnIiqUdMjXOHSjs+Amva0
# VczuqwjtVdNDTPqbZlCXatPtZ8nwYeEOD2jOqgjAoEwwabZ1fFGDCNXlqEDLSdTm
# Cc+IZPYU5a8+tVfH0DYEMgMSkRhDUqVZ/076L+pRi+Q8ClxWV8fKsf5qKw==
# =jJtu
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 14 Aug 2024 03:02:22 AM AEST
# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg:                issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]

* tag 'for-upstream' of https://gitlab.com/bonzini/qemu:
  po: update Italian translation
  module: Prevent crash by resetting local_err in module_load_qom_all()
  target/i386: Assert MMX and XMM registers in range
  target/i386: Use unit not type in decode_modrm
  target/i386: Do not apply REX to MMX operands
  target/hexagon: don't look for static glib

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


Compare: https://github.com/qemu/qemu/compare/9eb51530c12a...a733f37aef3b

To unsubscribe from these emails, change your notification settings at 
https://github.com/qemu/qemu/settings/notifications