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[Qemu-commits] [qemu/qemu] 6d630d: contrib/plugins/cflow: fix warning
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From: |
Peter Maydell |
|
Subject: |
[Qemu-commits] [qemu/qemu] 6d630d: contrib/plugins/cflow: fix warning |
|
Date: |
Wed, 06 Nov 2024 03:15:45 -0800 |
Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 6d630d84ca551840ae4ce629d6adfc2fe97e741a
https://github.com/qemu/qemu/commit/6d630d84ca551840ae4ce629d6adfc2fe97e741a
Author: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M contrib/plugins/cflow.c
Log Message:
-----------
contrib/plugins/cflow: fix warning
contrib/plugins/cflow.c: In function ‘plugin_exit’:
contrib/plugins/cflow.c:167:19: error: declaration of ‘n’ shadows a previous
local [-Werror=shadow=local]
167 | NodeData *n = l->data;
| ^
contrib/plugins/cflow.c:139:9: note: shadowed declaration is here
139 | int n = 0;
| ^
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20241023212812.1376972-2-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Commit: 2181b928877770e9869edaa5b7008f926a83989e
https://github.com/qemu/qemu/commit/2181b928877770e9869edaa5b7008f926a83989e
Author: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
A contrib/plugins/meson.build
M meson.build
Log Message:
-----------
meson: build contrib/plugins with meson
Tried to unify this meson.build with tests/tcg/plugins/meson.build but
the resulting modules are not output in the right directory.
Originally proposed by Anton Kochkov, thank you!
Solves: https://gitlab.com/qemu-project/qemu/-/issues/1710
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20241023212812.1376972-3-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Commit: 55c84a72aba4a9406320943e6348bb120c2df08f
https://github.com/qemu/qemu/commit/55c84a72aba4a9406320943e6348bb120c2df08f
Author: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M Makefile
M configure
R contrib/plugins/Makefile
Log Message:
-----------
contrib/plugins: remove Makefile for contrib/plugins
Now replaced by meson build.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20241023212812.1376972-4-pierrick.bouvier@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Commit: 8a132968b2ce3f7078c8643dbc00e5c642eef0f6
https://github.com/qemu/qemu/commit/8a132968b2ce3f7078c8643dbc00e5c642eef0f6
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M fpu/softfloat-specialize.c.inc
M include/fpu/softfloat-helpers.h
M include/fpu/softfloat-types.h
Log Message:
-----------
softfloat: Allow 2-operand NaN propagation rule to be set at runtime
IEEE 758 does not define a fixed rule for which NaN to pick as the
result if both operands of a 2-operand operation are NaNs. As a
result different architectures have ended up with different rules for
propagating NaNs.
QEMU currently hardcodes the NaN propagation logic into the binary
because pickNaN() has an ifdef ladder for different targets. We want
to make the propagation rule instead be selectable at runtime,
because:
* this will let us have multiple targets in one QEMU binary
* the Arm FEAT_AFP architectural feature includes letting
the guest select a NaN propagation rule at runtime
* x86 specifies different propagation rules for x87 FPU ops
and for SSE ops, and specifying the rule in the float_status
would let us emulate this, instead of wrongly using the
x87 rules everywhere
In this commit we add an enum for the propagation rule, the field in
float_status, and the corresponding getters and setters. We change
pickNaN to honour this, but because all targets still leave this
field at its default 0 value, the fallback logic will pick the rule
type with the old ifdef ladder.
It's valid not to set a propagation rule if default_nan_mode is
enabled, because in that case there's no need to pick a NaN; all the
callers of pickNaN() catch this case and skip calling it. So we can
already assert that we don't get into the "no rule defined" codepath
for our four targets which always set default_nan_mode: Hexagon,
RiscV, SH4 and Tricore, and for the one target which does not have FP
at all: avr. These targets will not need to be updated to call
set_float_2nan_prop_rule().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-2-peter.maydell@linaro.org
Commit: d22c9949d73d714e1ea2caf033131d882ad1d66a
https://github.com/qemu/qemu/commit/d22c9949d73d714e1ea2caf033131d882ad1d66a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M tests/fp/fp-bench.c
M tests/fp/fp-test-log2.c
M tests/fp/fp-test.c
Log Message:
-----------
tests/fp: Explicitly set 2-NaN propagation rule
Explicitly set a 2-NaN propagation rule in the softfloat tests. In
meson.build we put -DTARGET_ARM in fpcflags, and so we should select
here the Arm propagation rule of float_2nan_prop_s_ab.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-3-peter.maydell@linaro.org
Commit: d1ff996788a41280e2e0213b9571afeca4d6ca90
https://github.com/qemu/qemu/commit/d1ff996788a41280e2e0213b9571afeca4d6ca90
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M fpu/softfloat-specialize.c.inc
M linux-user/arm/nwfpe/fpa11.c
M target/arm/cpu.c
Log Message:
-----------
target/arm: Explicitly set 2-NaN propagation rule
Set the 2-NaN propagation rule explicitly in the float_status words
we use. We wrap this plus the pre-existing setting of the
tininess-before-rounding flag in a new function
arm_set_default_fp_behaviours() to avoid repetition, since we have a
lot of float_status words at this point.
The situation with FPA11 emulation in linux-user is a little odd, and
arguably "correct" behaviour there would be to exactly match a real
Linux kernel's FPA11 emulation. However FPA11 emulation is
essentially dead at this point and so it seems better to continue
with QEMU's current behaviour and leave a comment describing the
situation.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-4-peter.maydell@linaro.org
Commit: 0c587f13397a306f7ad4f8b0b7cb9184488012b5
https://github.com/qemu/qemu/commit/0c587f13397a306f7ad4f8b0b7cb9184488012b5
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M fpu/softfloat-specialize.c.inc
M target/mips/cpu.c
M target/mips/fpu_helper.h
M target/mips/msa.c
Log Message:
-----------
target/mips: Explicitly set 2-NaN propagation rule
Set the 2-NaN propagation rule explicitly in the float_status words
we use.
For active_fpu.fp_status, we do this in a new fp_reset() function
which mirrors the existing msa_reset() function in doing "first call
restore to set the fp status parts that depend on CPU state, then set
the fp status parts that are constant".
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20241025141254.2141506-5-peter.maydell@linaro.org
Commit: 1bb5257def132090bdff2cd1352841915553aaaf
https://github.com/qemu/qemu/commit/1bb5257def132090bdff2cd1352841915553aaaf
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M fpu/softfloat-specialize.c.inc
M target/loongarch/tcg/fpu_helper.c
Log Message:
-----------
target/loongarch: Explicitly set 2-NaN propagation rule
Set the 2-NaN propagation rule explicitly in the float_status word we
use.
(There are a couple of places in fpu_helper.c where we create a
dummy float_status word with "float_status *s = { };", but these
are only used for calling float*_is_quiet_nan() so it doesn't
matter that we don't set a 2-NaN propagation rule there.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-6-peter.maydell@linaro.org
Commit: 2915876e035088d516d88394028903064072543e
https://github.com/qemu/qemu/commit/2915876e035088d516d88394028903064072543e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M fpu/softfloat-specialize.c.inc
M target/hppa/fpu_helper.c
Log Message:
-----------
target/hppa: Explicitly set 2-NaN propagation rule
Set the 2-NaN propagation rule explicitly in env->fp_status.
Really we only need to do this at CPU reset (after reset has zeroed
out most of the CPU state struct, which typically includes fp_status
fields). However target/hppa does not currently implement CPU reset
at all, so leave a TODO comment to note that this could be moved if
we ever do implement reset.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-7-peter.maydell@linaro.org
Commit: 841f9d74751f8615dbc6215504db7abbc0ebff5e
https://github.com/qemu/qemu/commit/841f9d74751f8615dbc6215504db7abbc0ebff5e
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M fpu/softfloat-specialize.c.inc
M target/s390x/cpu.c
Log Message:
-----------
target/s390x: Explicitly set 2-NaN propagation rule
Set the 2-NaN propagation rule explicitly in env->fpu_status.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-8-peter.maydell@linaro.org
Commit: 5aaab56a1ab63d7604308be4e746b8804ccff7da
https://github.com/qemu/qemu/commit/5aaab56a1ab63d7604308be4e746b8804ccff7da
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M fpu/softfloat-specialize.c.inc
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Explicitly set 2-NaN propagation rule
Set the 2-NaN propagation rule explicitly in env->fp_status
and env->vec_status.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-9-peter.maydell@linaro.org
Commit: 0527cfd94c1d648870176b5610aaefb4fc1d7eba
https://github.com/qemu/qemu/commit/0527cfd94c1d648870176b5610aaefb4fc1d7eba
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M fpu/softfloat-specialize.c.inc
M target/m68k/cpu.c
M target/m68k/fpu_helper.c
Log Message:
-----------
target/m68k: Explicitly set 2-NaN propagation rule
Explicitly set the 2-NaN propagation rule on env->fp_status
and on the temporary fp_status that we use in frem (since
we pass that to a division operation function).
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Commit: ad58ba13d04b85c141bca2d927fb9de6490bf0c1
https://github.com/qemu/qemu/commit/ad58ba13d04b85c141bca2d927fb9de6490bf0c1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M target/m68k/helper.c
Log Message:
-----------
target/m68k: Initialize float_status fields in gdb set/get functions
In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we use a temporary
float_status variable to pass to floatx80_to_float64() and
float64_to_floatx80(), but we don't initialize it, meaning that those
functions could access uninitialized data. Zero-init the structs.
(We don't need to set a NaN-propagation rule here because we
don't use these with a 2-argument fpu operation.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-11-peter.maydell@linaro.org
Commit: 65c1c039cdbcf66e9bc5b0366c8f7cc22284359a
https://github.com/qemu/qemu/commit/65c1c039cdbcf66e9bc5b0366c8f7cc22284359a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M target/sparc/cpu.c
Log Message:
-----------
target/sparc: Move cpu_put_fsr(env, 0) call to reset
Currently we call cpu_put_fsr(0) in sparc_cpu_realizefn(), which
initializes various fields in the CPU struct:
* fsr_cexc_ftt
* fcc[]
* fsr_qne
* fsr
It also sets the rounding mode in env->fp_status.
This is largely pointless, because when we later reset the CPU
this will zero out all the fields up until the "end_reset_fields"
label, which includes all of these (but not fp_status!)
Move the cpu_put_fsr(env, 0) call to reset, because that expresses
the logical requirement: we want to reset FSR to 0 on every reset.
This isn't a behaviour change because the fields are all zero anyway.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-12-peter.maydell@linaro.org
Commit: 4482f32dcd1faa035e03ded557fa980e8b528c31
https://github.com/qemu/qemu/commit/4482f32dcd1faa035e03ded557fa980e8b528c31
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M fpu/softfloat-specialize.c.inc
M target/sparc/cpu.c
M target/sparc/fop_helper.c
Log Message:
-----------
target/sparc: Explicitly set 2-NaN propagation rule
Set the NaN propagation rule explicitly in the float_status
words we use.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-13-peter.maydell@linaro.org
Commit: 80de5f24e09cd9885a5e8d72cc01c097c23bf227
https://github.com/qemu/qemu/commit/80de5f24e09cd9885a5e8d72cc01c097c23bf227
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M target/xtensa/cpu.c
M target/xtensa/cpu.h
M target/xtensa/fpu_helper.c
Log Message:
-----------
target/xtensa: Factor out calls to set_use_first_nan()
In xtensa we currently call set_use_first_nan() in a lot of
places where we want to switch the NaN-propagation handling.
We're about to change the softfloat API we use to do that,
so start by factoring all the calls out into a single
xtensa_use_first_nan() function.
The bulk of this change was done with
sed -i -e 's/set_use_first_nan(\([^,]*\),[^)]*)/xtensa_use_first_nan(env,
\1)/' target/xtensa/fpu_helper.c
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-14-peter.maydell@linaro.org
Commit: 8d988eb44cd2723a6bd31a2895bdaba48524b6e0
https://github.com/qemu/qemu/commit/8d988eb44cd2723a6bd31a2895bdaba48524b6e0
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M fpu/softfloat-specialize.c.inc
M target/xtensa/fpu_helper.c
Log Message:
-----------
target/xtensa: Explicitly set 2-NaN propagation rule
Set the NaN propagation rule explicitly in xtensa_use_first_nan().
(When we convert the softfloat pickNaNMulAdd routine to also
select a NaN propagation rule at runtime, we will be able to
remove the use_first_nan flag because the propagation rules
will handle everything.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-15-peter.maydell@linaro.org
Commit: 62d39b28ef4e7ad41a3ef3e37037615de6dfc194
https://github.com/qemu/qemu/commit/62d39b28ef4e7ad41a3ef3e37037615de6dfc194
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M fpu/softfloat-specialize.c.inc
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/tcg/fpu_helper.c
Log Message:
-----------
target/i386: Set 2-NaN propagation rule explicitly
Set the NaN propagation rule explicitly for the float_status words
used in the x86 target.
This is a no-behaviour-change commit, so we retain the existing
behaviour of using the x87-style "prefer QNaN over SNaN, then prefer
the NaN with the larger significand" for MMX and SSE. This is
however not the documented hardware behaviour, so we leave a TODO
note about what we should be doing instead.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-16-peter.maydell@linaro.org
Commit: 8403a5015c5d5ef01792dc5ebf3c10aa5594931f
https://github.com/qemu/qemu/commit/8403a5015c5d5ef01792dc5ebf3c10aa5594931f
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M fpu/softfloat-specialize.c.inc
M target/alpha/cpu.c
Log Message:
-----------
target/alpha: Explicitly set 2-NaN propagation rule
Set the NaN propagation rule explicitly for the float_status word
used in this target.
This is a no-behaviour-change commit, so we retain the existing
behaviour of x87-style pick-largest-significand NaN propagation.
This is however not the architecturally correct handling, so we leave
a TODO note to that effect.
We also leave a TODO note pointing out that all this code in the cpu
initfn (including the existing setting up of env->flags and the FPCR)
should be in a currently non-existent CPU reset function.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-17-peter.maydell@linaro.org
Commit: c18a13edceca5419beb6eb703ffad6980d926f3b
https://github.com/qemu/qemu/commit/c18a13edceca5419beb6eb703ffad6980d926f3b
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M target/microblaze/cpu.c
Log Message:
-----------
target/microblaze: Move setting of float rounding mode to reset
Although the floating point rounding mode for Microblaze is always
nearest-even, we cannot set it just once in the CPU initfn. This is
because env->fp_status is in the part of the CPU state struct that is
zeroed on reset.
Move the call to set_float_rounding_mode() into the reset fn.
(This had no guest-visible effects because it happens that the
float_round_nearest_even enum value is 0, so when the struct was
zeroed it didn't corrupt the setting.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-18-peter.maydell@linaro.org
Commit: 4fafdcc833f2bfe0037512921dc37ebeed053853
https://github.com/qemu/qemu/commit/4fafdcc833f2bfe0037512921dc37ebeed053853
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M fpu/softfloat-specialize.c.inc
M target/microblaze/cpu.c
Log Message:
-----------
target/microblaze: Explicitly set 2-NaN propagation rule
Set the NaN propagation rule explicitly for the float_status word
used in the microblaze target.
This is probably not the architecturally correct behaviour,
but since this is a no-behaviour-change patch, we leave a
TODO note to that effect.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-19-peter.maydell@linaro.org
Commit: 355e6cfb94f61214ad4f633ce568debec5a8fc0d
https://github.com/qemu/qemu/commit/355e6cfb94f61214ad4f633ce568debec5a8fc0d
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M fpu/softfloat-specialize.c.inc
M target/openrisc/cpu.c
Log Message:
-----------
target/openrisc: Explicitly set 2-NaN propagation rule
Set the NaN propagation rule explicitly for the float_status word
used in the openrisc target.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-20-peter.maydell@linaro.org
Commit: ba6558461cb0280ad861b376cbfff4680be82570
https://github.com/qemu/qemu/commit/ba6558461cb0280ad861b376cbfff4680be82570
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M fpu/softfloat-specialize.c.inc
M target/rx/cpu.c
Log Message:
-----------
target/rx: Explicitly set 2-NaN propagation rule
Set the NaN propagation rule explicitly for the float_status word
used in the rx target.
This not the architecturally correct behaviour, but since this is a
no-behaviour-change patch, we leave a TODO note to that effect.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-21-peter.maydell@linaro.org
Commit: bc0b360def4d4735c3f30e0a35ae9f49209df37a
https://github.com/qemu/qemu/commit/bc0b360def4d4735c3f30e0a35ae9f49209df37a
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M fpu/softfloat-specialize.c.inc
M include/fpu/softfloat-types.h
Log Message:
-----------
softfloat: Remove fallback rule from pickNaN()
Now that all targets have been converted to explicitly set a NaN
propagation rule, we can remove the set of target ifdefs (which now
list every target) and clean up the references to fallback behaviour
for float_2nan_prop_none.
The "default" case in the switch will catch any remaining places
where status->float_2nan_prop_rule was not set by the target.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241025141254.2141506-22-peter.maydell@linaro.org
Commit: 056c5c90c171c4895b407af0cf3d198e1d44b40f
https://github.com/qemu/qemu/commit/056c5c90c171c4895b407af0cf3d198e1d44b40f
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/ptw.c
M target/arm/tcg/hflags.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.c
M target/arm/tcg/translate.h
Log Message:
-----------
Revert "target/arm: Fix usage of MMU indexes when EL3 is AArch32"
This reverts commit 4c2c0474693229c1f533239bb983495c5427784d.
This commit tried to fix a problem with our usage of MMU indexes when
EL3 is AArch32, using what it described as a "more complicated
approach" where we share the same MMU index values for Secure PL1&0
and NonSecure PL1&0. In theory this should work, but the change
didn't account for (at least) two things:
(1) The design change means we need to flush the TLBs at any point
where the CPU state flips from one to the other. We already flush
the TLB when SCR.NS is changed, but we don't flush the TLB when we
take an exception from NS PL1&0 into Mon or when we return from Mon
to NS PL1&0, and the commit didn't add any code to do that.
(2) The ATS12NS* address translate instructions allow Mon code (which
is Secure) to do a stage 1+2 page table walk for NS. I thought this
was OK because do_ats_write() does a page table walk which doesn't
use the TLBs, so because it can pass both the MMU index and also an
ARMSecuritySpace argument we can tell the table walk that we want NS
stage1+2, not S. But that means that all the code within the ptw
that needs to find e.g. the regime EL cannot do so only with an
mmu_idx -- all these functions like regime_sctlr(), regime_el(), etc
would need to pass both an mmu_idx and the security_space, so they
can tell whether this is a translation regime controlled by EL1 or
EL3 (and so whether to look at SCTLR.S or SCTLR.NS, etc).
In particular, because regime_el() wasn't updated to look at the
ARMSecuritySpace it would return 1 even when the CPU was in Monitor
mode (and the controlling EL is 3). This meant that page table walks
in Monitor mode would look at the wrong SCTLR, TCR, etc and would
generally fault when they should not.
Rather than trying to make the complicated changes needed to rescue
the design of 4c2c04746932, we revert it in order to instead take the
route that that commit describes as "the most straightforward" fix,
where we add new MMU indexes EL30_0, EL30_3, EL30_3_PAN to correspond
to "Secure PL1&0 at PL0", "Secure PL1&0 at PL1", and "Secure PL1&0 at
PL1 with PAN".
This revert will re-expose the "spurious alignment faults in
Secure PL0" issue #2326; we'll fix it again in the next commit.
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Thomas Huth <thuth@redhat.com>
Message-id: 20241101142845.1712482-2-peter.maydell@linaro.org
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Commit: efbe180ad2ed75d4cc64dfc6fb46a015eef713d1
https://github.com/qemu/qemu/commit/efbe180ad2ed75d4cc64dfc6fb46a015eef713d1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/ptw.c
M target/arm/tcg/op_helper.c
M target/arm/tcg/translate.c
Log Message:
-----------
target/arm: Add new MMU indexes for AArch32 Secure PL1&0
Our current usage of MMU indexes when EL3 is AArch32 is confused.
Architecturally, when EL3 is AArch32, all Secure code runs under the
Secure PL1&0 translation regime:
* code at EL3, which might be Mon, or SVC, or any of the
other privileged modes (PL1)
* code at EL0 (Secure PL0)
This is different from when EL3 is AArch64, in which case EL3 is its
own translation regime, and EL1 and EL0 (whether AArch32 or AArch64)
have their own regime.
We claimed to be mapping Secure PL1 to our ARMMMUIdx_EL3, but didn't
do anything special about Secure PL0, which meant it used the same
ARMMMUIdx_EL10_0 that NonSecure PL0 does. This resulted in a bug
where arm_sctlr() incorrectly picked the NonSecure SCTLR as the
controlling register when in Secure PL0, which meant we were
spuriously generating alignment faults because we were looking at the
wrong SCTLR control bits.
The use of ARMMMUIdx_EL3 for Secure PL1 also resulted in the bug that
we wouldn't honour the PAN bit for Secure PL1, because there's no
equivalent _PAN mmu index for it.
Fix this by adding two new MMU indexes:
* ARMMMUIdx_E30_0 is for Secure PL0
* ARMMMUIdx_E30_3_PAN is for Secure PL1 when PAN is enabled
The existing ARMMMUIdx_E3 is used to mean "Secure PL1 without PAN"
(and would be named ARMMMUIdx_E30_3 in an AArch32-centric scheme).
These extra two indexes bring us up to the maximum of 16 that the
core code can currently support.
This commit:
* adds the new MMU index handling to the various places
where we deal in MMU index values
* adds assertions that we aren't AArch32 EL3 in a couple of
places that currently use the E10 indexes, to document why
they don't also need to handle the E30 indexes
* documents in a comment why regime_has_2_ranges() doesn't need
updating
Notes for backporting: this commit depends on the preceding revert of
4c2c04746932; that revert and this commit should probably be
backported to everywhere that we originally backported 4c2c04746932.
Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2326
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2588
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241101142845.1712482-3-peter.maydell@linaro.org
Commit: e6b2fa1b81ac6b05c4397237c846a295a9857920
https://github.com/qemu/qemu/commit/e6b2fa1b81ac6b05c4397237c846a295a9857920
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M target/arm/tcg/vec_helper.c
Log Message:
-----------
target/arm: Fix SVE SDOT/UDOT/USDOT (4-way, indexed)
Our implementation of the indexed version of SVE SDOT/UDOT/USDOT got
the calculation of the inner loop terminator wrong. Although we
correctly account for the element size when we calculate the
terminator for the first iteration:
intptr_t segend = MIN(16 / sizeof(TYPED), opr_sz_n);
we don't do that when we move it forward after the first inner loop
completes. The intention is that we process the vector in 128-bit
segments, which for a 64-bit element size should mean (1, 2), (3, 4),
(5, 6), etc. This bug meant that we would iterate (1, 2), (3, 4, 5,
6), (7, 8, 9, 10) etc and apply the wrong indexed element to some of
the operations, and also index off the end of the vector.
You don't see this bug if the vector length is small enough that we
don't need to iterate the outer loop, i.e. if it is only 128 bits,
or if it is the 64-bit special case from AA32/AA64 AdvSIMD. If the
vector length is 256 bits then we calculate the right results for the
elements in the vector but do index off the end of the vector. Vector
lengths greater than 256 bits see wrong answers. The instructions
that produce 32-bit results behave correctly.
Fix the recalculation of 'segend' for subsequent iterations, and
restore a version of the comment that was lost in the refactor of
commit 7020ffd656a5 that explains why we only need to clamp segend to
opr_sz_n for the first iteration, not the later ones.
Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2595
Fixes: 7020ffd656a5 ("target/arm: Macroize helper_gvec_{s,u}dot_idx_{b,h}")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241101185544.2130972-1-peter.maydell@linaro.org
Commit: a5c02408c1de0a0592d90f153328a4295b6fbca6
https://github.com/qemu/qemu/commit/a5c02408c1de0a0592d90f153328a4295b6fbca6
Author: Richard Henderson <richard.henderson@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M include/disas/capstone.h
Log Message:
-----------
disas: Fix build against Capstone v6 (again)
Like 9971cbac2f3, which set CAPSTONE_AARCH64_COMPAT_HEADER,
also set CAPSTONE_SYSTEMZ_COMPAT_HEADER. Fixes the build
against capstone v6-alpha.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-id: 20241022013047.830273-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: e8217c573f9777d90333f5f92aa35d3ae71a7bd6
https://github.com/qemu/qemu/commit/e8217c573f9777d90333f5f92aa35d3ae71a7bd6
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/rtc/ds1338.c
M hw/rtc/trace-events
Log Message:
-----------
hw/rtc/ds1338: Trace send and receive operations
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-id: 20241103143330.123596-2-shentey@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: afd431e45aac6d0e3529ca2ea02d77be90f14397
https://github.com/qemu/qemu/commit/afd431e45aac6d0e3529ca2ea02d77be90f14397
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/timer/imx_gpt.c
M hw/timer/trace-events
Log Message:
-----------
hw/timer/imx_gpt: Convert DPRINTF to trace events
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-id: 20241103143330.123596-3-shentey@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: fe06088b3c5b3bd1a31b499db38b9542deaa2a3e
https://github.com/qemu/qemu/commit/fe06088b3c5b3bd1a31b499db38b9542deaa2a3e
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/watchdog/wdt_imx2.c
Log Message:
-----------
hw/watchdog/wdt_imx2: Remove redundant assignment
The same statement is executed unconditionally right before the if statement.
Cc: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241103143330.123596-4-shentey@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 3647dca9fbf4fb267c401cdd94519b7a60af0b0b
https://github.com/qemu/qemu/commit/3647dca9fbf4fb267c401cdd94519b7a60af0b0b
Author: Bernhard Beschow <shentey@gmail.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/sensor/tmp105.c
A hw/sensor/trace-events
A hw/sensor/trace.h
M meson.build
Log Message:
-----------
hw/sensor/tmp105: Convert printf() to trace event, add tracing for read/write
access
printf() unconditionally prints to the console which disturbs `-serial stdio`.
Fix that by converting into a trace event. While at it, add some tracing for
read and write access.
Fixes: 7e7c5e4c1ba5 "Nokia N800 machine support (ARM)."
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20241103143330.123596-5-shentey@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: ab4b56d981d753eb2ecc610d2b5d5689716aae9c
https://github.com/qemu/qemu/commit/ab4b56d981d753eb2ecc610d2b5d5689716aae9c
Author: Nabih Estefan <nabihestefan@google.com>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M hw/net/npcm_gmac.c
M hw/net/trace-events
Log Message:
-----------
hw/net/npcm_gmac: Change error log to trace event
Convert the LOG_GUEST_ERROR for the "tx descriptor is owned
by software" to a trace message. This condition is normal
when there is there is nothing to transmit, and we would
otherwise spam the logs with it in that situation.
Signed-off-by: Nabih Estefan <nabihestefan@google.com>
Signed-off-by: Roque Arcudia Hernandez <roqueh@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20241014184847.1594056-1-roqueh@google.com
[PMM: tweaked commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: 374cdc8efe4a039510cca47e8399d54a1aeb4f2d
https://github.com/qemu/qemu/commit/374cdc8efe4a039510cca47e8399d54a1aeb4f2d
Author: Gustavo Romero <gustavo.romero@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/cpu-features.h
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/tcg/cpu64.c
Log Message:
-----------
target/arm: Enable FEAT_CMOW for -cpu max
FEAT_CMOW introduces support for controlling cache maintenance
instructions executed in EL0/1 and is mandatory from Armv8.8.
On real hardware, the main use for this feature is to prevent processes
from invalidating or flushing cache lines for addresses they only have
read permission, which can impact the performance of other processes.
QEMU implements all cache instructions as NOPs, and, according to rule
[1], which states that generating any Permission fault when a cache
instruction is implemented as a NOP is implementation-defined, no
Permission fault is generated for any cache instruction when it lacks
read and write permissions.
QEMU does not model any cache topology, so the PoU and PoC are before
any cache, and rules [2] apply. These rules state that generating any
MMU fault for cache instructions in this topology is also
implementation-defined. Therefore, for FEAT_CMOW, we do not generate any
MMU faults either, instead, we only advertise it in the feature
register.
[1] Rule R_HGLYG of section D8.14.3, Arm ARM K.a.
[2] Rules R_MZTNR and R_DNZYL of section D8.14.3, Arm ARM K.a.
Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20241104142606.941638-1-gustavo.romero@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: c003aeff91c29ad0c17511621035bee287adead5
https://github.com/qemu/qemu/commit/c003aeff91c29ad0c17511621035bee287adead5
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M Makefile
M configure
R contrib/plugins/Makefile
M contrib/plugins/cflow.c
A contrib/plugins/meson.build
M meson.build
Log Message:
-----------
Merge tag 'pull-plugin-tweaks-051124-1' of https://gitlab.com/stsquad/qemu
into staging
final plugin updates for 9.2
- fix a warning in cflow plugin
- replace Makefile with meson.build
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# Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44
* tag 'pull-plugin-tweaks-051124-1' of https://gitlab.com/stsquad/qemu:
contrib/plugins: remove Makefile for contrib/plugins
meson: build contrib/plugins with meson
contrib/plugins/cflow: fix warning
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Commit: f15f7273ea55472d5904c53566c82369d81214c1
https://github.com/qemu/qemu/commit/f15f7273ea55472d5904c53566c82369d81214c1
Author: Peter Maydell <peter.maydell@linaro.org>
Date: 2024-11-05 (Tue, 05 Nov 2024)
Changed paths:
M docs/system/arm/emulation.rst
M fpu/softfloat-specialize.c.inc
M hw/net/npcm_gmac.c
M hw/net/trace-events
M hw/rtc/ds1338.c
M hw/rtc/trace-events
M hw/sensor/tmp105.c
A hw/sensor/trace-events
A hw/sensor/trace.h
M hw/timer/imx_gpt.c
M hw/timer/trace-events
M hw/watchdog/wdt_imx2.c
M include/disas/capstone.h
M include/fpu/softfloat-helpers.h
M include/fpu/softfloat-types.h
M linux-user/arm/nwfpe/fpa11.c
M meson.build
M target/alpha/cpu.c
M target/arm/cpu-features.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/ptw.c
M target/arm/tcg/cpu64.c
M target/arm/tcg/hflags.c
M target/arm/tcg/op_helper.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.c
M target/arm/tcg/translate.h
M target/arm/tcg/vec_helper.c
M target/hppa/fpu_helper.c
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/tcg/fpu_helper.c
M target/loongarch/tcg/fpu_helper.c
M target/m68k/cpu.c
M target/m68k/fpu_helper.c
M target/m68k/helper.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/mips/fpu_helper.h
M target/mips/msa.c
M target/openrisc/cpu.c
M target/ppc/cpu_init.c
M target/rx/cpu.c
M target/s390x/cpu.c
M target/sparc/cpu.c
M target/sparc/fop_helper.c
M target/xtensa/cpu.c
M target/xtensa/cpu.h
M target/xtensa/fpu_helper.c
M tests/fp/fp-bench.c
M tests/fp/fp-test-log2.c
M tests/fp/fp-test.c
Log Message:
-----------
Merge tag 'pull-target-arm-20241105' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Fix MMU indexes for AArch32 Secure PL1&0 in a less complex and buggy way
* Fix SVE SDOT/UDOT/USDOT (4-way, indexed)
* softfloat: set 2-operand NaN propagation rule at runtime
* disas: Fix build against Capstone v6 (again)
* hw/rtc/ds1338: Trace send and receive operations
* hw/timer/imx_gpt: Convert DPRINTF to trace events
* hw/watchdog/wdt_imx2: Remove redundant assignment
* hw/sensor/tmp105: Convert printf() to trace event, add tracing for
read/write access
* hw/net/npcm_gmac: Change error log to trace event
* target/arm: Enable FEAT_CMOW for -cpu max
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# H8FIFIJbtv5aIixqtKcUBUmrBCYy4EoiRMLkqfC09VW60wtWswAP4KBQxi1ogehV
# jJw8AgSLCl2MsVmyzgleZQ==
# =Woag
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 05 Nov 2024 11:19:06 GMT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
[ultimate]
# gpg: aka "Peter Maydell <peter@archaic.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20241105' of
https://git.linaro.org/people/pmaydell/qemu-arm: (31 commits)
target/arm: Enable FEAT_CMOW for -cpu max
hw/net/npcm_gmac: Change error log to trace event
hw/sensor/tmp105: Convert printf() to trace event, add tracing for read/write
access
hw/watchdog/wdt_imx2: Remove redundant assignment
hw/timer/imx_gpt: Convert DPRINTF to trace events
hw/rtc/ds1338: Trace send and receive operations
disas: Fix build against Capstone v6 (again)
target/arm: Fix SVE SDOT/UDOT/USDOT (4-way, indexed)
target/arm: Add new MMU indexes for AArch32 Secure PL1&0
Revert "target/arm: Fix usage of MMU indexes when EL3 is AArch32"
softfloat: Remove fallback rule from pickNaN()
target/rx: Explicitly set 2-NaN propagation rule
target/openrisc: Explicitly set 2-NaN propagation rule
target/microblaze: Explicitly set 2-NaN propagation rule
target/microblaze: Move setting of float rounding mode to reset
target/alpha: Explicitly set 2-NaN propagation rule
target/i386: Set 2-NaN propagation rule explicitly
target/xtensa: Explicitly set 2-NaN propagation rule
target/xtensa: Factor out calls to set_use_first_nan()
target/sparc: Explicitly set 2-NaN propagation rule
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Compare: https://github.com/qemu/qemu/compare/9eb9350c0e51...f15f7273ea55
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