[Qemu-devel] [PATCH, MIPS64] Fix Status_rw_bitmask values

[Aurelien Jarno]

Hi all,

The patch below fixes the Status_rw_bitmask values for 64-bit CPUs:
- Reverse endianess is currently not implemented, the RE bit should
  not be writable. 
- 64-bit is implemented, the PX bit should be writable.

Bye,
Aurelien

Index: target-mips/translate_init.c
===================================================================
RCS file: /sources/qemu/qemu/target-mips/translate_init.c,v
retrieving revision 1.13
diff -u -d -p -r1.13 translate_init.c
--- target-mips/translate_init.c        1 Jun 2007 21:57:32 -0000       1.13
+++ target-mips/translate_init.c        4 Jun 2007 13:00:30 -0000
@@ -145,7 +145,7 @@ static mips_def_t mips_defs[] =
         .CP0_Config3 = MIPS_CONFIG3,
         .SYNCI_Step = 16,
         .CCRes = 2,
-        .Status_rw_bitmask = 0x3678FFFF,
+        .Status_rw_bitmask = 0x34F8FFFF,
        /* The R4000 has a full 64bit FPU doesn't use the fcr0 bits. */
         .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
     },
@@ -161,7 +161,7 @@ static mips_def_t mips_defs[] =
         .CP0_Config3 = MIPS_CONFIG3,
         .SYNCI_Step = 32,
         .CCRes = 2,
-        .Status_rw_bitmask = 0x3278FFFF,
+        .Status_rw_bitmask = 0x30F8FFFF,
     },
     {
         .name = "5Kf",
@@ -175,7 +175,7 @@ static mips_def_t mips_defs[] =
         .CP0_Config3 = MIPS_CONFIG3,
         .SYNCI_Step = 32,
         .CCRes = 2,
-        .Status_rw_bitmask = 0x3678FFFF,
+        .Status_rw_bitmask = 0x34F8FFFF,
        /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
         .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
                     (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
@@ -192,7 +192,7 @@ static mips_def_t mips_defs[] =
         .CP0_Config3 = MIPS_CONFIG3,
         .SYNCI_Step = 32,
         .CCRes = 2,
-        .Status_rw_bitmask = 0x36FBFFFF,
+        .Status_rw_bitmask = 0x34FBFFFF,
        /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
         .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
                     (1 << FCR0_D) | (1 << FCR0_S) |

-- 
  .''`.  Aurelien Jarno             | GPG: 1024D/F1BCDB73
 : :' :  Debian developer           | Electrical Engineer
 `. `'   address@hidden         | address@hidden
   `-    people.debian.org/~aurel32 | www.aurel32.net