Re: [Qemu-devel] [PATCH 09/10] target-alpha: Implement load-locked/store-conditional properly.

[Blue Swirl]

On 3/25/10, Richard Henderson <address@hidden> wrote:
> On 03/25/2010 06:39 AM, Nathan Froyd wrote:
>  > On Wed, Mar 24, 2010 at 05:11:43PM -0700, Richard Henderson wrote:
>  >> Use __sync_bool_compare_and_swap to yield correctly atomic results.
>  >> As yet, this assumes running on an strict-memory-ordering host (i.e. x86),
>  >> since we're still "implementing" the memory-barrier instructions as nops.
>  >
>  > Did the approach taken by other targets (arm/mips/ppc) not work on
>  > Alpha?
>
>
> Mips doesn't even pretend to be atomic.
>
>  Powerpc and Arm -- if I've got this straight -- use some sort of 
> stop-the-world
>  mutex+condition and then perform the compare-and-exchange by hand.  I can't
>  see how that's better than using an actual compare-and-exchange provided by
>  the host cpu.  In fact, I'm mildly horrified by the prospect.
>
>  Honestly.  Even ARM and HPPA which doesn't (always) natively have cmpxchg, 
> have
>  an easy to use kernel trap to perform the operation.  I suppose real 80386 
> and
>  sparc-pre-v9 don't have anything particularly useful, but frankly it wouldn't
>  bother me to deprecate them as hosts since the modern editions all do work.

Sparc V8 has two atomic instructions, ldstub and swap.