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[Qemu-devel] [PATCH v3 21/27] tcg-ppc64: Use I constraint for mul
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 21/27] tcg-ppc64: Use I constraint for mul |
Date: |
Mon, 1 Apr 2013 21:23:24 -0700 |
The mul_i32 pattern was loading non-16-bit constants into a register,
when we can get the middle-end to do that for us. The mul_i64 pattern
was not considering that MULLI takes 64-bit inputs.
Reviewed-by: Aurelien Jarno <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/ppc64/tcg-target.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index bd12b5c..69e558d 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -1465,17 +1465,12 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc,
const TCGArg *args,
break;
case INDEX_op_mul_i32:
+ a0 = args[0], a1 = args[1], a2 = args[2];
if (const_args[2]) {
- if (args[2] == (int16_t) args[2])
- tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
- | (args[2] & 0xffff));
- else {
- tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
- tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
- }
+ tcg_out32(s, MULLI | TAI(a0, a1, a2));
+ } else {
+ tcg_out32(s, MULLW | TAB(a0, a1, a2));
}
- else
- tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
break;
case INDEX_op_div_i32:
@@ -1634,7 +1629,12 @@ static void tcg_out_op (TCGContext *s, TCGOpcode opc,
const TCGArg *args,
break;
case INDEX_op_mul_i64:
- tcg_out32 (s, MULLD | TAB (args[0], args[1], args[2]));
+ a0 = args[0], a1 = args[1], a2 = args[2];
+ if (const_args[2]) {
+ tcg_out32(s, MULLI | TAI(a0, a1, a2));
+ } else {
+ tcg_out32(s, MULLD | TAB(a0, a1, a2));
+ }
break;
case INDEX_op_div_i64:
tcg_out32 (s, DIVD | TAB (args[0], args[1], args[2]));
@@ -1836,7 +1836,7 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_ld32s_i64, { "r", "r" } },
{ INDEX_op_add_i32, { "r", "r", "ri" } },
- { INDEX_op_mul_i32, { "r", "r", "ri" } },
+ { INDEX_op_mul_i32, { "r", "r", "rI" } },
{ INDEX_op_div_i32, { "r", "r", "r" } },
{ INDEX_op_divu_i32, { "r", "r", "r" } },
{ INDEX_op_rem_i32, { "r", "r", "r" } },
@@ -1880,7 +1880,7 @@ static const TCGTargetOpDef ppc_op_defs[] = {
{ INDEX_op_rotl_i64, { "r", "r", "ri" } },
{ INDEX_op_rotr_i64, { "r", "r", "ri" } },
- { INDEX_op_mul_i64, { "r", "r", "r" } },
+ { INDEX_op_mul_i64, { "r", "r", "rI" } },
{ INDEX_op_div_i64, { "r", "r", "r" } },
{ INDEX_op_divu_i64, { "r", "r", "r" } },
{ INDEX_op_rem_i64, { "r", "r", "r" } },
--
1.8.1.4
- Re: [Qemu-devel] [PATCH v3 16/27] tcg-ppc64: Implement bswap16 and bswap32, (continued)
[Qemu-devel] [PATCH v3 18/27] tcg-ppc64: Implement compound logicals, Richard Henderson, 2013/04/02
[Qemu-devel] [PATCH v3 19/27] tcg-ppc64: Handle constant inputs for some compound logicals, Richard Henderson, 2013/04/02
[Qemu-devel] [PATCH v3 21/27] tcg-ppc64: Use I constraint for mul,
Richard Henderson <=
[Qemu-devel] [PATCH v3 20/27] tcg-ppc64: Implement deposit, Richard Henderson, 2013/04/02
[Qemu-devel] [PATCH v3 22/27] tcg-ppc64: Use TCGType throughout compares, Richard Henderson, 2013/04/02
[Qemu-devel] [PATCH v3 23/27] tcg-ppc64: Rewrite setcond, Richard Henderson, 2013/04/02
[Qemu-devel] [PATCH v3 24/27] tcg-ppc64: Implement movcond, Richard Henderson, 2013/04/02
[Qemu-devel] [PATCH v3 25/27] tcg-ppc64: Use getauxval for ISA detection, Richard Henderson, 2013/04/02
[Qemu-devel] [PATCH v3 26/27] tcg-ppc64: Implement add2/sub2_i64, Richard Henderson, 2013/04/02
[Qemu-devel] [PATCH v3 27/27] tcg-ppc64: Implement mulu2/muls2_i64, Richard Henderson, 2013/04/02
Re: [Qemu-devel] [PATCH v3 00/27] Modernize tcg/ppc64, Alexander Graf, 2013/04/02