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Re: [Qemu-devel] [PATCH 1/5] configure: move TARGET_*_ALIGNMENT to targe


From: Aurelien Jarno
Subject: Re: [Qemu-devel] [PATCH 1/5] configure: move TARGET_*_ALIGNMENT to target-*/cpu.h
Date: Tue, 2 Apr 2013 19:57:36 +0200
User-agent: Mutt/1.5.20 (2009-06-14)

On Tue, Apr 02, 2013 at 05:43:36PM +0100, Peter Maydell wrote:
> On 2 April 2013 15:44, Paolo Bonzini <address@hidden> wrote:
> > This is no different from, for example, TARGET_LONG_BITS.  It does
> > not belong in configure.
> 
> > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> > index 42c36e2..19d4e4c 100644
> > --- a/target-ppc/cpu.h
> > +++ b/target-ppc/cpu.h
> > @@ -27,6 +27,7 @@
> >  #if defined (TARGET_PPC64)
> >  /* PowerPC 64 definitions */
> >  #define TARGET_LONG_BITS 64
> > +#define TARGET_LONG_ALIGNMENT 8
> >  #define TARGET_PAGE_BITS 12
> 
> Doesn't this incorrectly set the long alignment to 8
> for ppc64abi32? (Probably similar problem for
> sparc32plus and mipsn32. The underlying point here is that
> alignment is an ABI decision and you can have more than one
> ABI for a particular TARGET_FOO.)
> 

I'll do a test for mipsn32, but first I'll try to look how/where it is
used.

Note that ppc64abi32 and sparc32plus are different than mipsn32. The
first two are basically executing a 32-bit binary (with the 32-bit
ABI) on a 64-bit emulated CPU, with for sparc access to more
instructions. mipsn32 is a different ABI using 64-bit registers, but
32-bit pointers, simlar to x32.

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
address@hidden                 http://www.aurel32.net



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