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Re: [Qemu-devel] [PATCH 1/2] tcg/aarch64: Fix addsub2 for 0+C
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH 1/2] tcg/aarch64: Fix addsub2 for 0+C |
Date: |
Wed, 7 Dec 2016 18:10:35 +0000 |
On 7 December 2016 at 18:07, Richard Henderson <address@hidden> wrote:
> When al == xzr, we cannot use addi/subi because that encodes xsp.
> Force a zero into the temp register for that (rare) case.
Incidentally I was slightly surprised that the optimisation
pass didn't turn "add2 rlo, rhi, 0, 0, 0, 0" into moves of 0
into rlo and rhi. Constant shifts of xzr in the guest don't
seem worth spending much effort on optimising though :-)
thanks
-- PMM