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Re: [Qemu-devel] [PATCH v3 1/2] intel_iommu: check validity for GAW bits
From: |
Tian, Kevin |
Subject: |
Re: [Qemu-devel] [PATCH v3 1/2] intel_iommu: check validity for GAW bits in CE |
Date: |
Fri, 16 Dec 2016 02:28:47 +0000 |
> From: Peter Xu [mailto:address@hidden
> Sent: Wednesday, December 14, 2016 10:54 AM
>
> On Wed, Dec 14, 2016 at 04:48:42AM +0200, Michael S. Tsirkin wrote:
> > On Wed, Dec 14, 2016 at 10:09:04AM +0800, Peter Xu wrote:
> > > Currently vt-d Context Entry (CE) only allows 39/48 bits address width.
> > > If guest software configured more than that, we complain and report.
> > >
> > > Signed-off-by: Peter Xu <address@hidden>
> > > ---
> > > hw/i386/intel_iommu.c | 17 ++++++++++++++++-
> > > hw/i386/intel_iommu_internal.h | 2 ++
> > > 2 files changed, 18 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> > > index 5f3e351..517a2a3 100644
> > > --- a/hw/i386/intel_iommu.c
> > > +++ b/hw/i386/intel_iommu.c
> > > @@ -599,9 +599,19 @@ static inline uint32_t
> vtd_get_level_from_context_entry(VTDContextEntry *ce)
> > > return 2 + (ce->hi & VTD_CONTEXT_ENTRY_AW);
> > > }
> > >
> > > +/* Return 0 if failed to fetch valid aw */
> > > static inline uint32_t vtd_get_agaw_from_context_entry(VTDContextEntry
> > > *ce)
> > > {
> > > - return 30 + (ce->hi & VTD_CONTEXT_ENTRY_AW) * 9;
> > > + uint8_t aw = (ce->hi & VTD_CONTEXT_ENTRY_AW);
> > > + /*
> > > + * According to vt-d spec 10.4.2 bits 12:8, SAGAW only allows
> > > + * 39/48 bits.
> > > + */
> > > + if (aw > VTD_CE_AW_48BIT) {
> >
> > 5-level is almost sure to allow more. I don't see the point of this test.
>
> Please check above comment - spec only allow 3/4 level page table.
>
> My version of vt-d spec is 2016 Oct. I suppose that's new enough...
>
It is in the works and will be published in January.
Thanks
Kevin