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Re: [Qemu-devel] [PATCH] x86: implement la57 paging mode
From: |
Paolo Bonzini |
Subject: |
Re: [Qemu-devel] [PATCH] x86: implement la57 paging mode |
Date: |
Thu, 22 Dec 2016 13:38:05 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 |
On 22/12/2016 13:37, Kirill A. Shutemov wrote:
> On Fri, Dec 16, 2016 at 01:59:36PM +0100, Paolo Bonzini wrote:
>>
>>
>> On 15/12/2016 01:13, Kirill A. Shutemov wrote:
>>> The new paging more is extension of IA32e mode with more additional page
>>> table level.
>>>
>>> It brings support of 57-bit vitrual address space (128PB) and 52-bit
>>> physical address space (4PB).
>>>
>>> The structure of new page table level is identical to pml4.
>>>
>>> The feature is enumerated with CPUID.(EAX=07H, ECX=0):ECX[bit 16].
>>>
>>> CR4.LA57[bit 12] need to be set when pageing enables to activate 5-level
>>> paging mode.
>>>
>>> Signed-off-by: Kirill A. Shutemov <address@hidden>
>>
>> Looks good, thanks! The target-i386/translate.c bits are not necessary,
>> but I guess they can also be removed on commit.
>
> Is there anything else I need to do to make it applied?
No, but 2.8 was only released a couple days ago so we were in freeze.
Paolo