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[Qemu-devel] [PATCH v11 23/24] hw/misc/imx6_src: defer clearing of SRC_S
From: |
Alex Bennée |
Subject: |
[Qemu-devel] [PATCH v11 23/24] hw/misc/imx6_src: defer clearing of SRC_SCR reset bits |
Date: |
Thu, 9 Feb 2017 17:09:03 +0000 |
The arm_reset_cpu/set_cpu_on/set_cpu_off() functions do their work
asynchronously in the target vCPUs context. As a result we need to
ensure the SRC_SCR reset bits correctly report the reset status at the
right time. To do this we defer the clearing of the bit with an async
job which will run after the work queued by ARM powerctl functions.
Signed-off-by: Alex Bennée <address@hidden>
---
hw/misc/imx6_src.c | 58 +++++++++++++++++++++++++++++++++++++++++++++---------
1 file changed, 49 insertions(+), 9 deletions(-)
diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c
index 55b817b8d7..f7c1d94a3e 100644
--- a/hw/misc/imx6_src.c
+++ b/hw/misc/imx6_src.c
@@ -14,6 +14,7 @@
#include "qemu/bitops.h"
#include "qemu/log.h"
#include "arm-powerctl.h"
+#include "qom/cpu.h"
#ifndef DEBUG_IMX6_SRC
#define DEBUG_IMX6_SRC 0
@@ -113,6 +114,45 @@ static uint64_t imx6_src_read(void *opaque, hwaddr offset,
unsigned size)
return value;
}
+
+/* The reset is asynchronous so we need to defer clearing the reset
+ * bit until the work is completed.
+ */
+
+struct src_scr_reset_info {
+ IMX6SRCState *s;
+ unsigned long reset_bit;
+};
+
+static void imx6_clear_reset_bit(CPUState *cpu, run_on_cpu_data data)
+{
+ struct src_scr_reset_info *ri = data.host_ptr;
+ IMX6SRCState *s = ri->s;
+
+ assert(qemu_mutex_iothread_locked());
+
+ s->regs[SRC_SCR] = deposit32(s->regs[SRC_SCR], ri->reset_bit, 1, 0);
+ DPRINTF("reg[%s] <= 0x%" PRIx32 "\n",
+ imx6_src_reg_name(SRC_SCR), s->regs[SRC_SCR]);
+
+ g_free(ri);
+}
+
+static void imx6_defer_clear_reset_bit(int cpuid,
+ IMX6SRCState *s,
+ unsigned long reset_shift)
+{
+ struct src_scr_reset_info *ri;
+
+ ri = g_malloc(sizeof(struct src_scr_reset_info));
+ ri->s = s;
+ ri->reset_bit = reset_shift;
+
+ async_run_on_cpu(arm_get_cpu_by_id(cpuid), imx6_clear_reset_bit,
+ RUN_ON_CPU_HOST_PTR(ri));
+}
+
+
static void imx6_src_write(void *opaque, hwaddr offset, uint64_t value,
unsigned size)
{
@@ -153,7 +193,7 @@ static void imx6_src_write(void *opaque, hwaddr offset,
uint64_t value,
arm_set_cpu_off(3);
}
/* We clear the reset bits as the processor changed state */
- clear_bit(CORE3_RST_SHIFT, ¤t_value);
+ imx6_defer_clear_reset_bit(3, s, CORE3_RST_SHIFT);
clear_bit(CORE3_RST_SHIFT, &change_mask);
}
if (EXTRACT(change_mask, CORE2_ENABLE)) {
@@ -162,11 +202,11 @@ static void imx6_src_write(void *opaque, hwaddr offset,
uint64_t value,
arm_set_cpu_on(2, s->regs[SRC_GPR5], s->regs[SRC_GPR6],
3, false);
} else {
- /* CORE 3 is shut down */
+ /* CORE 2 is shut down */
arm_set_cpu_off(2);
}
/* We clear the reset bits as the processor changed state */
- clear_bit(CORE2_RST_SHIFT, ¤t_value);
+ imx6_defer_clear_reset_bit(2, s, CORE2_RST_SHIFT);
clear_bit(CORE2_RST_SHIFT, &change_mask);
}
if (EXTRACT(change_mask, CORE1_ENABLE)) {
@@ -175,28 +215,28 @@ static void imx6_src_write(void *opaque, hwaddr offset,
uint64_t value,
arm_set_cpu_on(1, s->regs[SRC_GPR3], s->regs[SRC_GPR4],
3, false);
} else {
- /* CORE 3 is shut down */
+ /* CORE 1 is shut down */
arm_set_cpu_off(1);
}
/* We clear the reset bits as the processor changed state */
- clear_bit(CORE1_RST_SHIFT, ¤t_value);
+ imx6_defer_clear_reset_bit(1, s, CORE1_RST_SHIFT);
clear_bit(CORE1_RST_SHIFT, &change_mask);
}
if (EXTRACT(change_mask, CORE0_RST)) {
arm_reset_cpu(0);
- clear_bit(CORE0_RST_SHIFT, ¤t_value);
+ imx6_defer_clear_reset_bit(0, s, CORE0_RST_SHIFT);
}
if (EXTRACT(change_mask, CORE1_RST)) {
arm_reset_cpu(1);
- clear_bit(CORE1_RST_SHIFT, ¤t_value);
+ imx6_defer_clear_reset_bit(1, s, CORE1_RST_SHIFT);
}
if (EXTRACT(change_mask, CORE2_RST)) {
arm_reset_cpu(2);
- clear_bit(CORE2_RST_SHIFT, ¤t_value);
+ imx6_defer_clear_reset_bit(2, s, CORE2_RST_SHIFT);
}
if (EXTRACT(change_mask, CORE3_RST)) {
arm_reset_cpu(3);
- clear_bit(CORE3_RST_SHIFT, ¤t_value);
+ imx6_defer_clear_reset_bit(3, s, CORE3_RST_SHIFT);
}
if (EXTRACT(change_mask, SW_IPU2_RST)) {
/* We pretend the IPU2 is reset */
--
2.11.0
- [Qemu-devel] [PATCH v11 13/24] cputlb: add assert_cpu_is_self checks, (continued)
- [Qemu-devel] [PATCH v11 13/24] cputlb: add assert_cpu_is_self checks, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 12/24] tcg: handle EXCP_ATOMIC exception for system emulation, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 08/24] tcg: drop global lock during TCG code execution, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 07/24] tcg: rename tcg_current_cpu to tcg_current_rr_cpu, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 15/24] cputlb: introduce tlb_flush_* async work., Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 16/24] cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmap, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 19/24] cputlb: introduce tlb_flush_*_all_cpus[_synced], Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 18/24] cputlb: atomically update tlb fields used by tlb_reset_dirty, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 21/24] target-arm: don't generate WFE/YIELD calls for MTTCG, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 17/24] cputlb: add tlb_flush_by_mmuidx async routines, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 23/24] hw/misc/imx6_src: defer clearing of SRC_SCR reset bits,
Alex Bennée <=
- [Qemu-devel] [PATCH v11 24/24] tcg: enable MTTCG by default for ARM on x86 hosts, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 20/24] target-arm/powerctl: defer cpu reset work to CPU context, Alex Bennée, 2017/02/09
- [Qemu-devel] [PATCH v11 22/24] target-arm: ensure all cross vCPUs TLB flushes complete, Alex Bennée, 2017/02/09