[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v2 05/11] target/ppc: update ca32 in arithmetic subs
From: |
Nikunj A Dadhania |
Subject: |
[Qemu-devel] [PATCH v2 05/11] target/ppc: update ca32 in arithmetic substract |
Date: |
Wed, 22 Feb 2017 14:59:42 +0530 |
Signed-off-by: Nikunj A Dadhania <address@hidden>
---
target/ppc/translate.c | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b589d09..184d10f 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -827,7 +827,15 @@ static inline void gen_op_arith_compute_ca32(DisasContext
*ctx,
}
t0 = tcg_temp_new();
- tcg_gen_xor_tl(t0, arg0, arg1);
+ if (!add_ca && sub) {
+ /* Invert arg0 before xor as in the !add_ca case,
+ * we do not get inverse of arg0
+ */
+ tcg_gen_not_tl(t0, arg0);
+ tcg_gen_xor_tl(t0, t0, arg1);
+ } else {
+ tcg_gen_xor_tl(t0, arg0, arg1);
+ }
tcg_gen_xor_tl(t0, t0, res);
tcg_gen_extract_tl(cpu_ca32, t0, 32, 1);
tcg_temp_free(t0);
@@ -1382,11 +1390,13 @@ static inline void gen_op_arith_subf(DisasContext *ctx,
TCGv ret, TCGv arg1,
zero = tcg_const_tl(0);
tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
+ gen_op_arith_compute_ca32(ctx, t0, inv1, arg2, add_ca, 1);
tcg_temp_free(zero);
tcg_temp_free(inv1);
} else {
tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
tcg_gen_sub_tl(t0, arg2, arg1);
+ gen_op_arith_compute_ca32(ctx, t0, arg1, arg2, add_ca, 1);
}
} else if (add_ca) {
/* Since we're ignoring carry-out, we can simplify the
--
2.7.4
- [Qemu-devel] [PATCH v2 00/11] POWER9 TCG enablements - part15, Nikunj A Dadhania, 2017/02/22
- [Qemu-devel] [PATCH v2 01/11] target/ppc: move cpu_[read, write]_xer to cpu.c, Nikunj A Dadhania, 2017/02/22
- [Qemu-devel] [PATCH v2 03/11] target/ppc: support for 32-bit carry and overflow, Nikunj A Dadhania, 2017/02/22
- [Qemu-devel] [PATCH v2 04/11] target/ppc: update ca32 in arithmetic add, Nikunj A Dadhania, 2017/02/22
- [Qemu-devel] [PATCH v2 05/11] target/ppc: update ca32 in arithmetic substract,
Nikunj A Dadhania <=
- [Qemu-devel] [PATCH v2 07/11] target/ppc: use tcg ops for neg instruction, Nikunj A Dadhania, 2017/02/22
- [Qemu-devel] [PATCH v2 02/11] target/ppc: optimize gen_write_xer(), Nikunj A Dadhania, 2017/02/22
- [Qemu-devel] [PATCH v2 06/11] target/ppc: update overflow flags for add/sub, Nikunj A Dadhania, 2017/02/22
- [Qemu-devel] [PATCH v2 08/11] target/ppc: update ov/ov32 for nego, Nikunj A Dadhania, 2017/02/22