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Re: [Qemu-devel] [PATCH v3 03/10] target/ppc: support for 32-bit carry a
From: |
David Gibson |
Subject: |
Re: [Qemu-devel] [PATCH v3 03/10] target/ppc: support for 32-bit carry and overflow |
Date: |
Thu, 23 Feb 2017 20:29:27 +1100 |
User-agent: |
Mutt/1.7.1 (2016-10-04) |
On Thu, Feb 23, 2017 at 12:32:44PM +0530, Nikunj A Dadhania wrote:
> David Gibson <address@hidden> writes:
>
> > -static void gen_read_xer(TCGv dst)
> >> +static void gen_read_xer(DisasContext *ctx, TCGv dst)
> >> {
> >> TCGv t0 = tcg_temp_new();
> >> TCGv t1 = tcg_temp_new();
> >> @@ -3715,15 +3719,30 @@ static void gen_read_xer(TCGv dst)
> >> tcg_gen_or_tl(t0, t0, t1);
> >> tcg_gen_or_tl(dst, dst, t2);
> >> tcg_gen_or_tl(dst, dst, t0);
> >> + if (is_isa300(ctx)) {
> >> + tcg_gen_shli_tl(t0, cpu_ov32, XER_OV32);
> >> + tcg_gen_or_tl(dst, dst, t0);
> >> + tcg_gen_shli_tl(t0, cpu_ca32, XER_CA32);
> >> + tcg_gen_or_tl(dst, dst, t0);
> >
> > Could you use 2 deposits here, instead of 2 shifts and 2 ors?
>
> I checked the implementation of tcg_gen_deposit_i64, resultant will have much
> more than 2 shifts + 2 ors.
Ok, fair enough.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- [Qemu-devel] [PATCH v3 03/10] target/ppc: support for 32-bit carry and overflow, (continued)
[Qemu-devel] [PATCH v3 04/10] target/ppc: update ca32 in arithmetic add, Nikunj A Dadhania, 2017/02/22
[Qemu-devel] [PATCH v3 05/10] target/ppc: update ca32 in arithmetic substract, Nikunj A Dadhania, 2017/02/22
[Qemu-devel] [PATCH v3 06/10] target/ppc: update overflow flags for add/sub, Nikunj A Dadhania, 2017/02/22
[Qemu-devel] [PATCH v3 08/10] target/ppc: add ov32 flag for multiply low insns, Nikunj A Dadhania, 2017/02/22
[Qemu-devel] [PATCH v3 09/10] target/ppc: add ov32 flag in divide operations, Nikunj A Dadhania, 2017/02/22
[Qemu-devel] [PATCH v3 07/10] target/ppc: use tcg ops for neg instruction, Nikunj A Dadhania, 2017/02/22