Re: [Qemu-devel] [Qemu-arm] [PATCH v2 00/13] Rewrite NVIC to not depend on the GIC

[Peter Maydell]

On 24 February 2017 at 13:55, Alex Bennée <address@hidden> wrote:
> Even this branch is failing the tests for me:

> =============== Testing test9-kern.bin ===============

> not ok 9 - 00000000 == 00000800 icsr

> =============== Testing test10-kern.bin ===============
> not ok 1 - 00000000 == 00000800 ICSR

> not ok 9 - 00000000 == 00000800 ICSR

> =============== Testing test4-kern.bin ===============
> not ok 5 - 00000000 == 00000800 ICSR

> not ok 9 - 00410000 == 00410800 ICSR

Ah, I missed the test failures, but these are all test bugs.
All of these failures are for reads of ICSR when we're not
in an exception handler and the mismatch is because the
expected value of RETTOBASE differs. The bit is architecturally
UNKNOWN, and we did a late swap from making it be clear to
making it be set, because that seemed to be more in line
with the Cortex-M3 documented behaviour.

I didn't notice that the tests needed to be updated to
mask out the UNKNOWN bit before comparison.

thanks
-- PMM