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[Qemu-devel] [PULL 17/21] hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interfa
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 17/21] hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers |
Date: |
Tue, 28 Feb 2017 17:16:12 +0000 |
From: Vijaya Kumar K <address@hidden>
Reset CPU interface registers of GICv3 when CPU is reset.
For this, ARMCPRegInfo struct is registered with one ICC
register whose resetfn is called when cpu is reset.
All the ICC registers are reset under one single register
reset function instead of calling resetfn for each ICC
register.
Signed-off-by: Vijaya Kumar K <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Eric Auger <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gicv3_kvm.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index cda1af4..81f0403 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -604,6 +604,32 @@ static void kvm_arm_gicv3_get(GICv3State *s)
}
}
+static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ ARMCPU *cpu;
+ GICv3State *s;
+ GICv3CPUState *c;
+
+ c = (GICv3CPUState *)env->gicv3state;
+ s = c->gic;
+ cpu = ARM_CPU(c->cpu);
+
+ /* Initialize to actual HW supported configuration */
+ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS,
+ KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity),
+ &c->icc_ctlr_el1[GICV3_NS], false);
+
+ c->icc_ctlr_el1[GICV3_S] = c->icc_ctlr_el1[GICV3_NS];
+ c->icc_pmr_el1 = 0;
+ c->icc_bpr[GICV3_G0] = GIC_MIN_BPR;
+ c->icc_bpr[GICV3_G1] = GIC_MIN_BPR;
+ c->icc_bpr[GICV3_G1NS] = GIC_MIN_BPR;
+
+ c->icc_sre_el1 = 0x7;
+ memset(c->icc_apr, 0, sizeof(c->icc_apr));
+ memset(c->icc_igrpen, 0, sizeof(c->icc_igrpen));
+}
+
static void kvm_arm_gicv3_reset(DeviceState *dev)
{
GICv3State *s = ARM_GICV3_COMMON(dev);
@@ -621,6 +647,34 @@ static void kvm_arm_gicv3_reset(DeviceState *dev)
kvm_arm_gicv3_put(s);
}
+/*
+ * CPU interface registers of GIC needs to be reset on CPU reset.
+ * For the calling arm_gicv3_icc_reset() on CPU reset, we register
+ * below ARMCPRegInfo. As we reset the whole cpu interface under single
+ * register reset, we define only one register of CPU interface instead
+ * of defining all the registers.
+ */
+static const ARMCPRegInfo gicv3_cpuif_reginfo[] = {
+ { .name = "ICC_CTLR_EL1", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4,
+ /*
+ * If ARM_CP_NOP is used, resetfn is not called,
+ * So ARM_CP_NO_RAW is appropriate type.
+ */
+ .type = ARM_CP_NO_RAW,
+ .access = PL1_RW,
+ .readfn = arm_cp_read_zero,
+ .writefn = arm_cp_write_ignore,
+ /*
+ * We hang the whole cpu interface reset routine off here
+ * rather than parcelling it out into one little function
+ * per register
+ */
+ .resetfn = arm_gicv3_icc_reset,
+ },
+ REGINFO_SENTINEL
+};
+
static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
{
GICv3State *s = KVM_ARM_GICV3(dev);
@@ -644,6 +698,12 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error
**errp)
gicv3_init_irqs_and_mmio(s, kvm_arm_gicv3_set_irq, NULL);
+ for (i = 0; i < s->num_cpu; i++) {
+ ARMCPU *cpu = ARM_CPU(qemu_get_cpu(i));
+
+ define_arm_cp_regs(cpu, gicv3_cpuif_reginfo);
+ }
+
/* Try to create the device via the device control API */
s->dev_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_ARM_VGIC_V3, false);
if (s->dev_fd < 0) {
--
2.7.4
- [Qemu-devel] [PULL 00/21] target-arm queue, Peter Maydell, 2017/02/28
- [Qemu-devel] [PULL 05/21] armv7m: Make ARMv7M object take memory region link, Peter Maydell, 2017/02/28
- [Qemu-devel] [PULL 03/21] armv7m: QOMify the armv7m container, Peter Maydell, 2017/02/28
- [Qemu-devel] [PULL 02/21] armv7m: Move NVICState struct definition into header, Peter Maydell, 2017/02/28
- [Qemu-devel] [PULL 08/21] armv7m: Don't put core v7M devices under CONFIG_STELLARIS, Peter Maydell, 2017/02/28
- [Qemu-devel] [PULL 11/21] stm32f205: Rename 'nvic' local to 'armv7m', Peter Maydell, 2017/02/28
- [Qemu-devel] [PULL 01/21] armv7m: Abstract out the "load kernel" code, Peter Maydell, 2017/02/28
- [Qemu-devel] [PULL 04/21] armv7m: Use QOMified armv7m object in armv7m_init(), Peter Maydell, 2017/02/28
- [Qemu-devel] [PULL 18/21] qdev: Have qdev_set_parent_bus() handle devices already on a bus, Peter Maydell, 2017/02/28
- [Qemu-devel] [PULL 17/21] hw/intc/arm_gicv3_kvm: Reset GICv3 cpu interface registers,
Peter Maydell <=
- [Qemu-devel] [PULL 07/21] armv7m: Make bitband device take the address space to access, Peter Maydell, 2017/02/28
- [Qemu-devel] [PULL 09/21] armv7m: Split systick out from NVIC, Peter Maydell, 2017/02/28
- [Qemu-devel] [PULL 21/21] bcm2835: add sdhost and gpio controllers, Peter Maydell, 2017/02/28
- [Qemu-devel] [PULL 15/21] hw/intc/arm_gicv3_kvm: Implement get/put functions, Peter Maydell, 2017/02/28
- [Qemu-devel] [PULL 10/21] stm32f205: Create armv7m object without using armv7m_init(), Peter Maydell, 2017/02/28
- [Qemu-devel] [PULL 14/21] hw/intc/arm_gicv3_kvm: Add ICC_SRE_EL1 register to vmstate, Peter Maydell, 2017/02/28
- [Qemu-devel] [PULL 16/21] target-arm: Add GICv3CPUState in CPUARMState struct, Peter Maydell, 2017/02/28
- [Qemu-devel] [PULL 19/21] hw/sd: add card-reparenting function, Peter Maydell, 2017/02/28
- [Qemu-devel] [PULL 20/21] bcm2835_gpio: add bcm2835 gpio controller, Peter Maydell, 2017/02/28
- [Qemu-devel] [PULL 06/21] armv7m: Make NVIC expose a memory region rather than mapping itself, Peter Maydell, 2017/02/28