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[PATCH 6/9] target/mips: Alias MSA vector registers on FPU scalar regist
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From: |
Philippe Mathieu-Daudé |
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Subject: |
[PATCH 6/9] target/mips: Alias MSA vector registers on FPU scalar registers |
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Date: |
Wed, 2 Dec 2020 19:44:12 +0100 |
Commits 863f264d10f ("add msa_reset(), global msa register") and
cb269f273fd ("fix multiple TCG registers covering same data")
removed the FPU scalar registers and replaced them by aliases to
the MSA vector registers.
While this might be the case for CPU implementing MSA, this makes
QEMU code incoherent for CPU not implementing it. It is simpler
to inverse the logic and alias the MSA vector registers on the
FPU scalar ones.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a05c25e50b8..41880f21abd 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31682,16 +31682,20 @@ void mips_tcg_init(void)
offsetof(CPUMIPSState,
active_tc.gpr[i]),
regnames[i]);
-
for (i = 0; i < 32; i++) {
int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
- msa_wr_d[i * 2] =
- tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2]);
+
+ fpu_f64[i] = tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2]);
+ }
+ /* MSA */
+ for (i = 0; i < 32; i++) {
+ int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
+
/*
- * The scalar floating-point unit (FPU) registers are mapped on
- * the MSA vector registers.
+ * The MSA vector registers are mapped on the
+ * scalar floating-point unit (FPU) registers.
*/
- fpu_f64[i] = msa_wr_d[i * 2];
+ msa_wr_d[i * 2] = fpu_f64[i];
off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
msa_wr_d[i * 2 + 1] =
tcg_global_mem_new_i64(cpu_env, off, msaregnames[i * 2 + 1]);
--
2.26.2
- [PATCH 1/9] target/mips: Introduce ase_msa_available() helper, (continued)
- [PATCH 1/9] target/mips: Introduce ase_msa_available() helper, Philippe Mathieu-Daudé, 2020/12/02
- [PATCH 2/9] target/mips: Simplify msa_reset(), Philippe Mathieu-Daudé, 2020/12/02
- [PATCH 3/9] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA, Philippe Mathieu-Daudé, 2020/12/02
- [PATCH 4/9] target/mips: Simplify MSA TCG logic, Philippe Mathieu-Daudé, 2020/12/02
- [PATCH 5/9] target/mips: Remove now unused ASE_MSA definition, Philippe Mathieu-Daudé, 2020/12/02
- [PATCH 6/9] target/mips: Alias MSA vector registers on FPU scalar registers,
Philippe Mathieu-Daudé <=
- [PATCH 7/9] target/mips: Extract msa_translate_init() from mips_tcg_init(), Philippe Mathieu-Daudé, 2020/12/02
[PATCH 8/9] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods, Philippe Mathieu-Daudé, 2020/12/02
[PATCH 9/9] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ(), Philippe Mathieu-Daudé, 2020/12/02