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[PULL 01/36] hw/arm/smmuv3: Fix up L1STD_SPAN decoding
From: |
Peter Maydell |
Subject: |
[PULL 01/36] hw/arm/smmuv3: Fix up L1STD_SPAN decoding |
Date: |
Thu, 10 Dec 2020 11:47:21 +0000 |
From: Kunkun Jiang <jiangkunkun@huawei.com>
Accroding to the SMMUv3 spec, the SPAN field of Level1 Stream Table
Descriptor is 5 bits([4:0]).
Fixes: 9bde7f0674f(hw/arm/smmuv3: Implement translate callback)
Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com>
Message-id: 20201124023711.1184-1-jiangkunkun@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/smmuv3-internal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index fa3c088972e..b6f7e53b7c7 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -633,6 +633,6 @@ static inline uint64_t l1std_l2ptr(STEDesc *desc)
return hi << 32 | lo;
}
-#define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 4))
+#define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 5))
#endif
--
2.20.1
- [PULL 00/36] target-arm queue, Peter Maydell, 2020/12/10
- [PULL 03/36] xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers, Peter Maydell, 2020/12/10
- [PULL 06/36] sbsa-ref: allow to use Cortex-A53/57/72 cpus, Peter Maydell, 2020/12/10
- [PULL 01/36] hw/arm/smmuv3: Fix up L1STD_SPAN decoding,
Peter Maydell <=
- [PULL 05/36] MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller, Peter Maydell, 2020/12/10
- [PULL 04/36] tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller, Peter Maydell, 2020/12/10
- [PULL 02/36] hw/net/can: Introduce Xilinx ZynqMP CAN controller, Peter Maydell, 2020/12/10
- [PULL 09/36] i.MX31: Fix bad printf format specifiers, Peter Maydell, 2020/12/10
- [PULL 07/36] tests/qtest/npcm7xx_rng-test: dump random data on failure, Peter Maydell, 2020/12/10
- [PULL 14/36] target/arm: Don't clobber ID_PFR1.Security on M-profile cores, Peter Maydell, 2020/12/10
- [PULL 08/36] i.MX25: Fix bad printf format specifiers, Peter Maydell, 2020/12/10
- [PULL 10/36] i.MX6: Fix bad printf format specifiers, Peter Maydell, 2020/12/10
- [PULL 16/36] target/arm: Implement CLRM instruction, Peter Maydell, 2020/12/10
- [PULL 17/36] target/arm: Enforce M-profile VMRS/VMSR register restrictions, Peter Maydell, 2020/12/10