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[PATCH v3 11/15] target/riscv: Specify the XLEN for CPUs
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From: |
Alistair Francis |
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Subject: |
[PATCH v3 11/15] target/riscv: Specify the XLEN for CPUs |
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Date: |
Mon, 14 Dec 2020 12:34:26 -0800 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Tested-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.c | 33 +++++++++++++++++++++++----------
1 file changed, 23 insertions(+), 10 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 32a6916b8a..7d6f032122 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -158,22 +158,36 @@ static void riscv_base_cpu_init(Object *obj)
set_misa(env, 0);
}
-static void rvxx_sifive_u_cpu_init(Object *obj)
+#ifdef TARGET_RISCV64
+static void rv64_sifive_u_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
}
-static void rvxx_sifive_e_cpu_init(Object *obj)
+static void rv64_sifive_e_cpu_init(Object *obj)
{
CPURISCVState *env = &RISCV_CPU(obj)->env;
- set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU);
+ set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
set_priv_version(env, PRIV_VERSION_1_10_0);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
+#else
+static void rv32_sifive_u_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
+ set_priv_version(env, PRIV_VERSION_1_10_0);
+}
-#if defined(TARGET_RISCV32)
+static void rv32_sifive_e_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
+ set_priv_version(env, PRIV_VERSION_1_10_0);
+ qdev_prop_set_bit(DEVICE(obj), "mmu", false);
+}
static void rv32_ibex_cpu_init(Object *obj)
{
@@ -191,7 +205,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj)
set_resetvec(env, DEFAULT_RSTVEC);
qdev_prop_set_bit(DEVICE(obj), "mmu", false);
}
-
#endif
static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
@@ -643,13 +656,13 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_sifive_e_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_sifive_u_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init),
#elif defined(TARGET_RISCV64)
DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvxx_sifive_e_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_sifive_u_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
#endif
};
--
2.29.2
- [PATCH v3 02/15] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU, (continued)
- [PATCH v3 02/15] target/riscv: Add a TYPE_RISCV_CPU_BASE CPU, Alistair Francis, 2020/12/14
- [PATCH v3 03/15] riscv: spike: Remove target macro conditionals, Alistair Francis, 2020/12/14
- [PATCH v3 04/15] riscv: virt: Remove target macro conditionals, Alistair Francis, 2020/12/14
- [PATCH v3 05/15] hw/riscv: boot: Remove compile time XLEN checks, Alistair Francis, 2020/12/14
- [PATCH v3 06/15] hw/riscv: virt: Remove compile time XLEN checks, Alistair Francis, 2020/12/14
- [PATCH v3 07/15] hw/riscv: spike: Remove compile time XLEN checks, Alistair Francis, 2020/12/14
- [PATCH v3 08/15] hw/riscv: sifive_u: Remove compile time XLEN checks, Alistair Francis, 2020/12/14
- [PATCH v3 09/15] target/riscv: fpu_helper: Match function defs in HELPER macros, Alistair Francis, 2020/12/14
- [PATCH v3 10/15] target/riscv: Add a riscv_cpu_is_32bit() helper function, Alistair Francis, 2020/12/14
- [PATCH v3 11/15] target/riscv: Specify the XLEN for CPUs,
Alistair Francis <=
- [PATCH v3 12/15] target/riscv: cpu: Remove compile time XLEN checks, Alistair Francis, 2020/12/14
- [PATCH v3 13/15] target/riscv: cpu_helper: Remove compile time XLEN checks, Alistair Francis, 2020/12/14
- [PATCH v3 14/15] target/riscv: csr: Remove compile time XLEN checks, Alistair Francis, 2020/12/14
- [PATCH v3 15/15] target/riscv: cpu: Set XLEN independently from target, Alistair Francis, 2020/12/14