[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 01/24] target/mips/translate: Extract decode_opc_legacy() from
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v2 01/24] target/mips/translate: Extract decode_opc_legacy() from decode_opc() |
Date: |
Tue, 15 Dec 2020 23:57:34 +0100 |
As we will slowly move to decodetree generated decoders,
extract the legacy decoding from decode_opc(), so new
decoders are added in decode_opc() while old code is
removed from decode_opc_legacy().
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 45 ++++++++++++++++++++++++-----------------
1 file changed, 26 insertions(+), 19 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index cc876019bf7..5c62b32c6ae 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -30518,30 +30518,13 @@ static void gen_msa(CPUMIPSState *env, DisasContext
*ctx)
}
-static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
+static bool decode_opc_legacy(CPUMIPSState *env, DisasContext *ctx)
{
int32_t offset;
int rs, rt, rd, sa;
uint32_t op, op1;
int16_t imm;
- /* make sure instructions are on a word boundary */
- if (ctx->base.pc_next & 0x3) {
- env->CP0_BadVAddr = ctx->base.pc_next;
- generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL);
- return;
- }
-
- /* Handle blikely not taken case */
- if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) {
- TCGLabel *l1 = gen_new_label();
-
- tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
- tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK);
- gen_goto_tb(ctx, 1, ctx->base.pc_next + 4);
- gen_set_label(l1);
- }
-
op = MASK_OP_MAJOR(ctx->opcode);
rs = (ctx->opcode >> 21) & 0x1f;
rt = (ctx->opcode >> 16) & 0x1f;
@@ -31269,8 +31252,32 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
break;
default: /* Invalid */
MIPS_INVAL("major opcode");
+ return false;
+ }
+ return true;
+}
+
+static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
+{
+ /* make sure instructions are on a word boundary */
+ if (ctx->base.pc_next & 0x3) {
+ env->CP0_BadVAddr = ctx->base.pc_next;
+ generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL);
+ return;
+ }
+
+ /* Handle blikely not taken case */
+ if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) {
+ TCGLabel *l1 = gen_new_label();
+
+ tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1);
+ tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK);
+ gen_goto_tb(ctx, 1, ctx->base.pc_next + 4);
+ gen_set_label(l1);
+ }
+
+ if (!decode_opc_legacy(env, ctx)) {
gen_reserved_instruction(ctx);
- break;
}
}
--
2.26.2
- [PATCH v2 00/24] target/mips: Convert MSA ASE to decodetree, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 01/24] target/mips/translate: Extract decode_opc_legacy() from decode_opc(),
Philippe Mathieu-Daudé <=
- [PATCH v2 02/24] target/mips/translate: Expose check_mips_64() to 32-bit mode, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Philippe Mathieu-Daudé, 2020/12/15
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Richard Henderson, 2020/12/15
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Philippe Mathieu-Daudé, 2020/12/15
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Jiaxun Yang, 2020/12/15
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Jiaxun Yang, 2020/12/15
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Philippe Mathieu-Daudé, 2020/12/16
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Philippe Mathieu-Daudé, 2020/12/16
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Jiaxun Yang, 2020/12/16