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[PATCH v2 12/24] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v2 12/24] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() |
Date: |
Tue, 15 Dec 2020 23:57:45 +0100 |
In preparation of using the decodetree script, explode
gen_msa_branch() as following:
- OPC_BZ_V -> BxZ_V(EQ)
- OPC_BNZ_V -> BxZ_V(NE)
- OPC_BZ_[BHWD] -> BxZ(false)
- OPC_BNZ_[BHWD] -> BxZ(true)
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/mips/translate.c | 71 ++++++++++++++++++++++++++++-------------
1 file changed, 49 insertions(+), 22 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a3618a3beb2..9be946256b3 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28615,49 +28615,76 @@ static void gen_check_zero_element(TCGv tresult,
uint8_t df, uint8_t wt)
tcg_temp_free_i64(t1);
}
+static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
+{
+ TCGv_i64 t0;
+
+ check_msa_access(ctx);
+
+ if (ctx->hflags & MIPS_HFLAG_BMASK) {
+ gen_reserved_instruction(ctx);
+ return true;
+ }
+ t0 = tcg_temp_new_i64();
+ tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]);
+ tcg_gen_setcondi_i64(cond, t0, t0, 0);
+ tcg_gen_trunc_i64_tl(bcond, t0);
+ tcg_temp_free_i64(t0);
+
+ ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
+
+ ctx->hflags |= MIPS_HFLAG_BC;
+ ctx->hflags |= MIPS_HFLAG_BDS32;
+
+ return true;
+}
+
+static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool
if_not)
+{
+ check_msa_access(ctx);
+
+ if (ctx->hflags & MIPS_HFLAG_BMASK) {
+ gen_reserved_instruction(ctx);
+ return true;
+ }
+
+ gen_check_zero_element(bcond, df, wt);
+ if (if_not) {
+ tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0);
+ }
+
+ ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
+ ctx->hflags |= MIPS_HFLAG_BC;
+ ctx->hflags |= MIPS_HFLAG_BDS32;
+
+ return true;
+}
+
static void gen_msa_branch(DisasContext *ctx, uint32_t op1)
{
uint8_t df = (ctx->opcode >> 21) & 0x3;
uint8_t wt = (ctx->opcode >> 16) & 0x1f;
int64_t s16 = (int16_t)ctx->opcode;
- check_msa_access(ctx);
-
- if (ctx->hflags & MIPS_HFLAG_BMASK) {
- gen_reserved_instruction(ctx);
- return;
- }
switch (op1) {
case OPC_BZ_V:
case OPC_BNZ_V:
- {
- TCGv_i64 t0 = tcg_temp_new_i64();
- tcg_gen_or_i64(t0, msa_wr_d[wt << 1], msa_wr_d[(wt << 1) + 1]);
- tcg_gen_setcondi_i64((op1 == OPC_BZ_V) ?
- TCG_COND_EQ : TCG_COND_NE, t0, t0, 0);
- tcg_gen_trunc_i64_tl(bcond, t0);
- tcg_temp_free_i64(t0);
- }
+ gen_msa_BxZ_V(ctx, wt, s16, (op1 == OPC_BZ_V) ?
+ TCG_COND_EQ : TCG_COND_NE);
break;
case OPC_BZ_B:
case OPC_BZ_H:
case OPC_BZ_W:
case OPC_BZ_D:
- gen_check_zero_element(bcond, df, wt);
+ gen_msa_BxZ(ctx, df, wt, s16, false);
break;
case OPC_BNZ_B:
case OPC_BNZ_H:
case OPC_BNZ_W:
case OPC_BNZ_D:
- gen_check_zero_element(bcond, df, wt);
- tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, bcond, 0);
+ gen_msa_BxZ(ctx, df, wt, s16, true);
break;
}
-
- ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
-
- ctx->hflags |= MIPS_HFLAG_BC;
- ctx->hflags |= MIPS_HFLAG_BDS32;
}
static void gen_msa_i8(DisasContext *ctx)
--
2.26.2
- [PATCH v2 02/24] target/mips/translate: Expose check_mips_64() to 32-bit mode, (continued)
- [PATCH v2 02/24] target/mips/translate: Expose check_mips_64() to 32-bit mode, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 04/24] target/mips: Introduce ase_msa_available() helper, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 05/24] target/mips: Simplify msa_reset(), Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 06/24] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 07/24] target/mips: Simplify MSA TCG logic, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 08/24] target/mips: Remove now unused ASE_MSA definition, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 09/24] target/mips: Alias MSA vector registers on FPU scalar registers, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 10/24] target/mips: Extract msa_translate_init() from mips_tcg_init(), Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 11/24] target/mips: Remove CPUMIPSState* argument from gen_msa*() methods, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 12/24] target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ(),
Philippe Mathieu-Daudé <=
- [PATCH v2 13/24] target/mips: Rename msa_helper.c as mod-msa_helper.c, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 14/24] target/mips: Move msa_reset() to mod-msa_helper.c, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 15/24] target/mips: Extract MSA helpers from op_helper.c, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 16/24] target/mips: Extract MSA helper definitions, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 17/24] target/mips: Declare gen_msa/_branch() in 'translate.h', Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 18/24] target/mips: Extract MSA translation routines, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 19/24] target/mips: Introduce decode tree bindings for MSA opcodes, Philippe Mathieu-Daudé, 2020/12/15