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Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() hel
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper |
Date: |
Wed, 16 Dec 2020 00:48:25 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.5.0 |
On 12/16/20 12:27 AM, Richard Henderson wrote:
> On 12/15/20 4:57 PM, Philippe Mathieu-Daudé wrote:
>> +bool isa_rel6_available(const CPUMIPSState *env)
>> +{
>> + if (TARGET_LONG_BITS == 64) {
>> + return cpu_supports_isa(env, ISA_MIPS64R6);
>> + }
>> + return cpu_supports_isa(env, ISA_MIPS32R6);
>> +}
>
> So... does qemu-system-mips64 support 32-bit cpus?
Well... TBH I never tested it :S It looks the TCG code
is compiled with 64-bit TL registers, the machine address
space is 64-bit regardless the CPU, and I see various
#ifdef MIPS64 code that look dubious with 32-bit CPU.
>
> If so, this needs to be written
>
> if (TARGET_LONG_BITS == 64 && cpu_supports_isa(...)) {
> return true;
> }
>
> Otherwise, this will return false for a mips32r6 cpu.
I see. Rel6 is new to me, so I'll have to look at the ISA
manuals before returning to this thread with an answer.
Thanks for reviewing the series!
Phil.
- [PATCH v2 00/24] target/mips: Convert MSA ASE to decodetree, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 01/24] target/mips/translate: Extract decode_opc_legacy() from decode_opc(), Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 02/24] target/mips/translate: Expose check_mips_64() to 32-bit mode, Philippe Mathieu-Daudé, 2020/12/15
- [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Philippe Mathieu-Daudé, 2020/12/15
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Richard Henderson, 2020/12/15
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper,
Philippe Mathieu-Daudé <=
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Jiaxun Yang, 2020/12/15
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Jiaxun Yang, 2020/12/15
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Philippe Mathieu-Daudé, 2020/12/16
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Philippe Mathieu-Daudé, 2020/12/16
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Jiaxun Yang, 2020/12/16
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Jiaxun Yang, 2020/12/16
- Re: [PATCH v2 03/24] target/mips/cpu: Introduce isa_rel6_available() helper, Philippe Mathieu-Daudé, 2020/12/16
[PATCH v2 04/24] target/mips: Introduce ase_msa_available() helper, Philippe Mathieu-Daudé, 2020/12/15
[PATCH v2 05/24] target/mips: Simplify msa_reset(), Philippe Mathieu-Daudé, 2020/12/15
[PATCH v2 06/24] target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA, Philippe Mathieu-Daudé, 2020/12/15